repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_pe.v | 36,620 | module MODULE1( clk, rst,
VAR93, VAR12,
VAR59, VAR135, VAR108, VAR156,
VAR119, VAR116, VAR52, VAR85,
VAR96, VAR32, VAR98, VAR26,
VAR25, VAR123, VAR95, VAR133,
VAR23,
VAR143, VAR57,
VAR104, VAR86, VAR129,
VAR68, VAR5,
VAR17, VAR16,
VAR37, VAR107,
VAR64, VAR28,
VAR55, VAR34, VAR103,
VAR77, VAR126,
VAR146, VAR42,
VAR124, ... | gpl-2.0 |
megari/sd2snes | verilog/sd2snes_cx4/main.v | 21,198 | module MODULE1(
input VAR257,
input [23:0] VAR53,
input VAR238,
input VAR165,
input VAR305,
inout [7:0] VAR194,
input VAR319,
input VAR231,
output VAR47,
output VAR196,
output VAR2,
input VAR323,
input [7:0] VAR36,
input VAR301,
input VAR174,
inout [15:0] VAR176,
output [22:0] VAR302,
output VAR77,
output VAR55,
output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai_2.v | 2,368 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR10,
VAR9,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR11 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR10;
input VAR9;
input VAR4 ;
input VAR1 ;
VAR3 VAR7 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR4(VAR4),
.... | apache-2.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/altera_avalon_st_clock_crosser.v | 4,885 | module MODULE1(
VAR16,
VAR21,
VAR20,
VAR22,
VAR30,
VAR29,
VAR19,
VAR7,
VAR14,
VAR28
);
parameter VAR2 = 1;
parameter VAR5 = 8;
parameter VAR15 = 2;
parameter VAR10 = 2;
parameter VAR6 = 1;
localparam VAR26 = VAR2 * VAR5;
input VAR16;
input VAR21;
output VAR20;
input VAR22;
input [VAR26-1:0] VAR30;
input VAR29;
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o_2.v | 2,463 | module MODULE2 (
VAR11 ,
VAR10,
VAR4,
VAR3 ,
VAR1 ,
VAR9,
VAR8,
VAR7 ,
VAR2
);
output VAR11 ;
input VAR10;
input VAR4;
input VAR3 ;
input VAR1 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR2 ;
VAR6 VAR5 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR.v | 9,165 | module MODULE1 (
input wire clk, input wire VAR8, input wire [15:0] VAR5, input wire VAR2, input wire [1:0] VAR6, output wire [29:0] VAR3, output wire VAR1, output wire [1:0] VAR4 );
VAR7 VAR9 (
.clk (clk), .VAR8 (VAR8), .VAR5 (VAR5), .VAR2 (VAR2), .VAR6 (VAR6), .VAR3 (VAR3), .VAR1 (VAR1), .VAR4 (VAR4) );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.pp.blackbox.v | 1,374 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR2,
VAR4 ,
VAR5 ,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR3 ;
input VAR2;
input VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/rank_cntrl.v | 16,479 | module MODULE1 #
(
parameter VAR94 = 100,
parameter VAR78 = "8",
parameter VAR5 = 0,
parameter VAR49 = 4,
parameter VAR57 = 2,
parameter VAR33 = 5,
parameter VAR51 = 30,
parameter VAR38 = 8,
parameter VAR3 = 4,
parameter VAR71 = 4,
parameter VAR53 = 20,
parameter VAR81 = 16,
parameter VAR89 = 2,
parameter VAR29 = 4,
pa... | lgpl-3.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_VCU118/mkDM_FPR_Tap.v | 7,716 | module MODULE1(VAR69,
VAR59,
VAR49,
VAR34,
VAR40,
VAR64,
VAR8,
VAR53,
VAR60,
VAR23,
VAR52,
VAR31,
VAR7,
VAR22,
VAR48,
VAR44,
VAR9);
input VAR69;
input VAR59;
input VAR49;
output [69 : 0] VAR34;
output VAR40;
input [64 : 0] VAR64;
input VAR8;
output VAR53;
input [69 : 0] VAR60;
input VAR23;
output VAR52;
input VAR31;
ou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.functional.pp.v | 2,006 | module MODULE1 (
VAR1 ,
VAR14 ,
VAR4 ,
VAR10 ,
VAR11,
VAR3,
VAR15 ,
VAR16
);
output VAR1 ;
input VAR14 ;
input VAR4 ;
input VAR10 ;
input VAR11;
input VAR3;
input VAR15 ;
input VAR16 ;
wire VAR2 ;
wire VAR8 ;
wire VAR6;
and VAR7 (VAR2 , VAR14, VAR4 );
nor VAR5 (VAR8 , VAR10, VAR2 );
VAR9 VAR13 (VAR6, VAR8, VAR11, VAR3)... | apache-2.0 |
finnball/igloo | infra/hdl/vga.v | 1,433 | module MODULE1(
input clk,
output VAR18,
output VAR4,
output VAR16,
output VAR6
);
parameter VAR19 = 640;
parameter VAR12 = 96;
parameter VAR17 = 16;
parameter VAR11 = 48;
parameter VAR5 = VAR19 + VAR12 + VAR17 + VAR11;
parameter VAR8 = 480;
parameter VAR3 = 2;
parameter VAR7 = 10;
parameter VAR1 = 33;
parameter VAR9 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i_4.v | 2,214 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR9 ,
VAR2 ,
VAR4,
VAR8,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR5 ;
input VAR1 ;
VAR3 VAR10 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (... | apache-2.0 |
silent-observer/RCPU | CPU/source/TubeController.v | 1,983 | module MODULE2 (
input wire[3:0] VAR7,
input wire VAR10,
output reg[6:0] VAR3
);
always @ (*) begin
if (VAR10) begin
case (VAR7)
4'h0: VAR3 = 7'h00; 4'h1: VAR3 = 7'h73; 4'h2: VAR3 = 7'h78; 4'h3: VAR3 = 7'h50; 4'h4: VAR3 = 7'h1C; 4'h5: VAR3 = 7'h76; 4'h6: VAR3 = 7'h38; default: VAR3 = 7'b0;
endcase
end
else begin
case (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.functional.pp.v | 1,988 | module MODULE1 (
VAR13 ,
VAR4 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR11,
VAR1,
VAR14 ,
VAR16
);
output VAR13 ;
input VAR4 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR11;
input VAR1;
input VAR14 ;
input VAR16 ;
wire VAR15 ;
wire VAR17 ;
wire VAR2;
not VAR8 (VAR15 , VAR4 );
and VAR9 (VAR17 , VAR15, VAR3, VAR7, VAR5 );
VAR12 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.functional.v | 1,737 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR13 ,
VAR4 ,
VAR11
);
output VAR3 ;
output VAR10 ;
input VAR13 ;
input VAR4 ;
input VAR11;
wire VAR8;
wire VAR2 ;
not VAR12 (VAR2 , VAR11 );
VAR9 VAR5 VAR6 (VAR8 , VAR4, VAR13, VAR2 );
buf VAR7 (VAR3 , VAR8 );
not VAR1 (VAR10 , VAR8 );
endmodule | apache-2.0 |
freecores/zet86 | impl/virtex4-ml403ep/lcd/lcd_display.v | 3,540 | module MODULE1 (
input [63:0] VAR8, input [63:0] VAR11, input [15:0] VAR5, input [15:0] VAR15,
input clk, input rst,
output reg VAR19,
output reg VAR4,
output reg VAR22,
output reg [7:4] VAR12
);
parameter VAR2 = 8;
parameter VAR16 = 16;
reg [VAR16+VAR2+1:0] VAR10 = 0;
reg [ 5:0] VAR13;
wire [127:0] VAR1;
wire [ 31:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o_1.v | 2,437 | module MODULE2 (
VAR10 ,
VAR8 ,
VAR9 ,
VAR11 ,
VAR7 ,
VAR4 ,
VAR12,
VAR3,
VAR1 ,
VAR6
);
output VAR10 ;
input VAR8 ;
input VAR9 ;
input VAR11 ;
input VAR7 ;
input VAR4 ;
input VAR12;
input VAR3;
input VAR1 ;
input VAR6 ;
VAR5 VAR2 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b.symbol.v | 1,334 | module MODULE1 (
input VAR6 ,
input VAR7,
output VAR3
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T11-mux-2-1/mux2.v | 1,243 | module MODULE1(input wire clk, output reg [3:0] VAR1);
parameter VAR10 = 22; parameter VAR6 = 4'b1010; parameter VAR2 = 4'b0101;
wire [3:0] VAR8;
wire [3:0] VAR7;
wire sel;
assign VAR8 = VAR6;
assign VAR7 = VAR2;
always @(sel or VAR8 or VAR7)
if (sel==0)
VAR1 <= VAR8;
else
VAR1 <= VAR7;
VAR5 #(.VAR11(VAR10))
VAR9 (
.VA... | gpl-2.0 |
cpulabs/mist1032isa | src/mmu/mmu_table_load.v | 2,880 | module MODULE1(
input wire VAR16,
input wire VAR14,
input wire VAR19,
input wire VAR5,
input wire [31:0] VAR6,
output wire VAR20,
output wire VAR8,
input wire VAR11,
output wire [31:0] VAR17,
input wire VAR7,
input wire [63:0] VAR2,
output wire VAR13,
output wire [31:0] VAR1,
output wire [11:0] VAR18,
output wire [11:0... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.symbol.v | 1,396 | module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR1,
output VAR3
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa.functional.pp.v | 3,007 | module MODULE1 (
VAR8,
VAR1 ,
VAR24 ,
VAR18 ,
VAR11 ,
VAR10,
VAR23,
VAR14 ,
VAR3
);
output VAR8;
output VAR1 ;
input VAR24 ;
input VAR18 ;
input VAR11 ;
input VAR10;
input VAR23;
input VAR14 ;
input VAR3 ;
wire VAR6 ;
wire VAR30 ;
wire VAR7 ;
wire VAR17 ;
wire VAR32 ;
wire VAR12 ;
wire VAR9 ;
wire VAR27;
wire VAR5 ;
wi... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/IPv6_LISP/parser_h.v | 15,667 | module MODULE1(
input VAR18,
input [130:0] VAR43,
input clk,
input reset,
input VAR26,
input VAR2,
input [138:0] VAR23,
output reg VAR15,
output reg VAR46,
output reg VAR45,
output reg [138:0] VAR13,
output reg VAR47,
output reg [138:0] VAR11,
output reg VAR19,
output reg [359:0] VAR7,
output reg [7:0] VAR9,
output reg... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_lp.v | 2,192 | module MODULE2 (
VAR10,
VAR4 ,
VAR6 ,
VAR8 ,
VAR3,
VAR2,
VAR1 ,
VAR9
);
output VAR10;
output VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR9 ;
VAR7 VAR5 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODULE2... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/efc/rtl/efc_lib.v | 1,718 | module MODULE1 (VAR3, VAR4, VAR2 );
parameter VAR10 = 1;
input [VAR10-1:0] VAR3 ; input VAR4 ;
output [VAR10-1:0] VAR2 ;
VAR7 VAR8[VAR10-1:0] (
.VAR9 (VAR2),
.VAR6 (VAR4),
.VAR1 (VAR3),
.VAR5(1'b1));
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfbbn/sky130_fd_sc_hs__sdfbbn.behavioral.v | 3,472 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR33 ,
VAR15 ,
VAR18 ,
VAR31 ,
VAR36 ,
VAR5,
VAR19 ,
VAR23
);
output VAR11 ;
output VAR2 ;
input VAR33 ;
input VAR15 ;
input VAR18 ;
input VAR31 ;
input VAR36 ;
input VAR5;
input VAR19 ;
input VAR23 ;
wire VAR34 ;
wire VAR16 ;
wire VAR29 ;
wire VAR7 ;
reg VAR8 ;
wire VAR13 ;
wire VAR9 ;... | apache-2.0 |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/017861a2/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v | 5,675 | module MODULE1 #
(
parameter integer VAR39 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR39-1:0] VAR12,
output wire [1:0] VAR36,
output wire VAR50,
input wire VAR34,
input wire [1:0] VAR20,
input wire VAR51,
output wire VAR28,
input wire VAR42,
input wire [VAR39-1:0] VAR4,
input wire [7:0] VAR6,
input wire ... | mit |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/debouncer.v | 4,455 | module MODULE1 (clk, in, out, VAR6);
output reg out; input in; input clk;
input VAR6;
reg [VAR7-1:0] counter;
parameter [VAR7-1:0]
VAR5 = VAR7'h0,
VAR1 = VAR7'h1,
VAR9 = VAR7'h2,
VAR8 = VAR7'h3;
reg [VAR7-1:0] VAR4;
always @(posedge clk or negedge VAR6)
begin
if (~VAR6)
begin
counter <= #VAR3 VAR7'b0;
out <= #VAR3 1'b0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.behavioral.pp.v | 2,146 | module MODULE1 (
VAR17,
VAR5,
VAR4 ,
VAR16,
VAR11,
VAR14 ,
VAR9
);
input VAR17;
input VAR5;
output VAR4 ;
input VAR16;
input VAR11;
input VAR14 ;
input VAR9 ;
wire VAR9 VAR12 ;
wire VAR9 VAR15 ;
wire VAR3 ;
wire VAR1;
and VAR8 (VAR12 , VAR14, VAR9 );
nor VAR6 (VAR15 , VAR16, VAR11 );
nor VAR2 (VAR3 , VAR15, VAR12 );
VA... | apache-2.0 |
ayushmaanbhav/cpu32bit | imemory.v | 1,626 | module MODULE1(output [31:0] VAR1,input [6:0] addr,input clk);
reg [31:0] VAR1;
reg [7:0] VAR2 [511:0];
begin
begin | mit |
EliasLuiz/TCC | Leon3/lib/opencores/ge_1000baseX/ge_1000baseX.v | 27,070 | module MODULE1 #(
parameter VAR85 = 5'b00000,
VAR21 = 0
)(
input VAR69,
input VAR39,
input VAR78,
input VAR118,
input VAR32,
input [9:0] VAR163,
output [9:0] VAR37,
output [7:0] VAR107,
output VAR70,
output VAR128,
output VAR18,
output reg VAR146,
input [7:0] VAR71,
input VAR41,
input VAR102,
input VAR53,
input VAR132,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4b/sky130_fd_sc_hd__and4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR8 ,
VAR1,
VAR9,
VAR4 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR9;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp_2.v | 2,218 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR6 ,
VAR8,
VAR7
);
input VAR9 ;
input VAR1 ;
output VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR8;
input VAR7;
VAR2 VAR4 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR9,
VAR1 ,
VAR5 ,
VAR3,
VAR6
)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo_1.v | 2,318 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR1 ,
VAR7,
VAR6,
VAR8,
VAR4 ,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR1 ;
input VAR7;
input VAR6;
input VAR8;
input VAR4 ;
input VAR3 ;
VAR2 VAR10 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
V... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_gtx_es_wr.v | 9,605 | module MODULE1 (
VAR47,
VAR15,
VAR14,
VAR37,
VAR52,
VAR35,
VAR36,
VAR40,
VAR6,
VAR11,
VAR32,
VAR12,
VAR4,
VAR50,
VAR23,
VAR3,
VAR5,
VAR53,
VAR43,
VAR26,
VAR25,
VAR39,
VAR17);
input VAR47;
input VAR15;
input [31:0] VAR14;
input [15:0] VAR37;
input [15:0] VAR52;
input [15:0] VAR35;
input VAR36;
input VAR40;
input VAR6;
i... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.behavioral.pp.v | 1,311 | module MODULE1( VAR6, VAR4, VAR3, VAR9, VAR2, VAR7 );
input VAR6, VAR4, VAR3;
inout VAR2, VAR7;
output VAR9;
VAR1 VAR8(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9),.VAR2(VAR2),.VAR7(VAR7));
VAR1 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR9(VAR9),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_pr/sky130_fd_sc_ls__udp_dlatch_pr.blackbox.v | 1,291 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR1;
endmodule | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/vfabric_fptosi.v | 2,402 | module MODULE1(VAR5, VAR14,
VAR8, VAR23, VAR12,
VAR1, VAR16, VAR19);
parameter VAR21 = 32;
parameter VAR18 = 3;
parameter VAR11 = 64;
input VAR5, VAR14;
input [VAR21-1:0] VAR8;
input VAR23;
output VAR12;
output [VAR21-1:0] VAR1;
input VAR16;
output VAR19;
reg [VAR18-1:0] VAR28;
wire [VAR21-1:0] VAR26;
wire VAR9;
wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.pp.blackbox.v | 1,269 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR5 ,
VAR2,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR1;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/crt_sp/crt.v | 16,631 | module MODULE1
(
input [1:0] VAR7,
input VAR73,
input VAR91,
input VAR187,
input VAR172,
input VAR45,
input VAR98,
input VAR33,
input [3:0] VAR166,
input [31:0] VAR117,
input [7:2] VAR142,
input VAR120,
input [7:0] VAR28,
input VAR66, input [20:0] VAR188, input [31:0] VAR97,
input [39:0] VAR149,
input VAR74,
input VAR2... | gpl-3.0 |
HarmonInstruments/hififo | hdl/hififo_fpc_fifo.v | 3,811 | module MODULE1
(
input VAR2,
input reset,
output [31:0] VAR16,
output interrupt,
input [1:0] VAR43,
input [63:0] VAR13,
input [7:0] VAR23,
input [5:0] VAR15,
input VAR34,
input VAR25,
output reg VAR24, output [63:0] VAR21,
input VAR54,
output [2:0] VAR26,
input VAR44, input VAR35,
output [63:0] VAR42,
output VAR3
);
re... | gpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/SD/SD_Control.v | 10,324 | module MODULE1(
input VAR51, input VAR52, input [7:0] VAR16,
output reg VAR36, output VAR38, output reg [7:0] VAR40,
output VAR20,
input VAR25,
output reg [4:0] VAR45,
input VAR12,
input VAR47,
output VAR43,
input [29:0] VAR31,
input [4095:0] VAR34,
output reg [4095:0] VAR35);
wire [2:0] VAR4;
wire [8:0] VAR44;
reg [4:... | lgpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_lsu.v | 7,943 | module MODULE1(
VAR16, VAR19, VAR11, VAR43, VAR1, VAR36, VAR33,
VAR26, VAR21, VAR23, VAR6, VAR14,
VAR20, VAR3, VAR9, VAR5, VAR12, VAR10,
VAR35, VAR7, VAR13, VAR37, VAR18
);
parameter VAR8 = VAR22;
parameter VAR45 = VAR25;
input [31:0] VAR16;
input [31:0] VAR19;
input [VAR4-1:0] VAR11;
input [VAR8-1:0] VAR43;
output [VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.functional.pp.v | 1,935 | module MODULE1( VAR14, VAR3, VAR26, VAR9, VAR16, VAR10, VAR4, VAR22, VAR21 );
input VAR10, VAR4, VAR9, VAR16, VAR3, VAR26;
inout VAR22, VAR21;
output VAR14;
wire VAR1;
not VAR7( VAR1, VAR10 );
wire VAR12;
not VAR17( VAR12, VAR4 );
wire VAR27;
and VAR19( VAR27, VAR1, VAR12 );
wire VAR24;
not VAR11( VAR24, VAR9 );
wire V... | apache-2.0 |
CospanDesign/nysa-artemis-platform | artemis/slave/wb_artemis_ddr3/rtl/wb_artemis_ddr3.v | 8,897 | module MODULE1 (
input clk,
input rst,
output VAR36,
output VAR10,
output [2:0] VAR57,
output [5:0] VAR64,
output [29:0] VAR4,
input VAR37,
input VAR44,
output VAR5,
output VAR43,
output [3:0] VAR58,
output [31:0] VAR70,
input VAR41,
input VAR25,
input [6:0] VAR15,
input VAR7,
input VAR55,
output VAR46,
output VAR32,
i... | gpl-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Top.v | 10,898 | module MODULE1(
input VAR71,
input VAR20,
output VAR60,
output VAR42,
input VAR51,
output VAR47,
output VAR48,
output VAR80,
inout [15:0] VAR106,
input [10:0] VAR1,
input VAR65, input VAR101, input VAR67, input VAR83, output VAR33, output VAR107 );
wire VAR53, VAR28, VAR43;
wire VAR11;
reg reset;
always @(posedge VAR53... | lgpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/vga640x480.v | 2,399 | module MODULE1(
VAR4,
VAR9,
VAR2,
VAR3,
VAR7,
VAR15,
VAR5
);
input VAR4; input VAR9;
output VAR2; output VAR3;
output [9:0] VAR7; output [9:0] VAR15;
output VAR5;
localparam VAR14 = 800 , VAR12 = 521 , VAR10 = 144 , VAR11 = 784 ,
VAR1 = 31 , VAR8 = 511 ;
reg [9:0] VAR13, VAR16; reg VAR6;
assign VAR7 = VAR13;
assign VAR... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T26-rom/romleds.v | 1,050 | module MODULE1 (input wire clk,
output wire [3:0] VAR3);
parameter VAR5 = VAR10;
reg [3:0] addr;
reg VAR7 = 0;
wire VAR11;
VAR12
VAR6 (
.clk(clk),
.addr(addr),
.VAR2(VAR3)
);
always @(negedge clk)
if (VAR7 == 0)
addr <= 0;
else if (VAR11)
addr <= addr + 1;
VAR9 #(.VAR8(VAR5))
VAR1 ( .clk(clk),
.VAR4(VAR11)
);
always @(... | gpl-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/clib/c_damq_tracker.v | 7,792 | module MODULE1
(clk, reset, VAR50, VAR47, VAR37, VAR26, VAR19,
VAR21, VAR6, VAR3, VAR32, VAR22, VAR36);
parameter VAR30 = 4;
parameter VAR10 = 32;
parameter VAR1 = 0;
parameter VAR13 = 0;
parameter VAR16 = 0;
parameter VAR43 = 0;
parameter VAR27 = VAR40;
localparam VAR17
= VAR43 ? (VAR10 - VAR30) : VAR10;
localparam VA... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_odt_gen.v | 13,845 | module MODULE1
VAR33 = 2,
VAR6 = 1,
VAR31 = 2, VAR44 = 2,
VAR37 = 1,
VAR43 = 4,
VAR13 = 4,
VAR5 = 3,
VAR16 = 3,
VAR9 = 4,
VAR4 = 4
)
(
VAR11,
VAR39,
VAR10,
VAR8,
VAR14,
VAR34,
VAR1,
VAR41,
VAR19,
VAR26,
VAR29,
VAR17,
VAR7,
VAR36,
VAR42
);
input VAR11;
input VAR39;
input [VAR16 -1:0] VAR10;
input [VAR13 -1:0] VAR8;
inpu... | lgpl-3.0 |
ptracton/pmodacl2 | behavioral/adxl362/adxl362_accelerometer.v | 4,888 | module MODULE1 (
VAR4, VAR17, VAR6, VAR13, VAR21, VAR25,
VAR11,
VAR20, VAR18, VAR24, VAR26
) ;
parameter VAR9 = "VAR13.VAR23";
parameter VAR1 = "VAR21.VAR23";
parameter VAR19 = "VAR25.VAR23";
parameter VAR12 = "VAR14.VAR23";
parameter VAR16 = 16;
input wire VAR20;
input wire VAR18;
input wire [1:0] VAR24;
input wire VA... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_tanpi_s5.v | 1,187 | module MODULE1 (
enable,
VAR7,
VAR5,
VAR2);
input enable;
input VAR7;
input [31:0] VAR5;
output [31:0] VAR2;
wire [31:0] VAR1;
wire [31:0] VAR2 = VAR1[31:0];
VAR8 VAR9(
.en (enable),
.clk (VAR7),
.VAR3 (VAR5),
.VAR6 (VAR1),
.VAR4(1'b0));
endmodule | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/orpsoc_top.v | 18,145 | module MODULE1 #(
parameter VAR199 = 16,
parameter VAR345 = 13,
parameter VAR207 = 2,
parameter VAR205 = 6,
parameter VAR227 = 3
)(
input VAR356,
input VAR12,
input VAR7,
output VAR274,
output [12:0] VAR393,
output [2:0] VAR341,
output VAR257,
output VAR287,
output VAR68,
output VAR265,
output VAR405,
output VAR194,
ou... | gpl-2.0 |
marmolejo/zet | cores/wb_abrg/wb_regslice.v | 2,059 | module MODULE1 (
input clk,
input rst,
input [19:1] VAR18,
input [15:0] VAR11,
output reg [15:0] VAR8,
input [ 1:0] VAR7,
input VAR5,
input VAR15,
input VAR14,
input VAR19,
output reg VAR12,
output reg [19:1] VAR17,
output reg [15:0] VAR4,
input [15:0] VAR13,
output reg [ 1:0] VAR9,
output reg VAR6,
output reg VAR2,
ou... | gpl-3.0 |
orbancedric/DeepGate | src/core/parameterized_RAM_last.v | 1,931 | module MODULE1 #(
parameter VAR1 = 10,
parameter VAR4 = 2
)(
input VAR11,
input VAR12,
input VAR5,
input [7:0] VAR7,
output reg [7:0] VAR3 = 0,
output wire VAR8,
output wire VAR13
);
reg [7:0] VAR9 [VAR1*VAR4*2 - 1'b1: 0];
reg [VAR14(VAR1*VAR4*2):0] VAR6 = 0;
reg [VAR14(VAR1*VAR4*2 - 1'b1):0] VAR2 = 0;
reg [1:0] VAR10 ... | gpl-3.0 |
kielfriedt/ece472 | lab5/HazardDetect.v | 1,475 | module MODULE1(clk, reset, VAR6, VAR5, VAR4, VAR1, VAR7, VAR3, VAR2);
input VAR6, clk, reset;
input [4:0] VAR5, VAR1, VAR7, VAR4;
output VAR3, VAR2;
reg VAR3, VAR2;
always @(clk or VAR4 or VAR5 or VAR7 or VAR1 )
begin
if(((VAR5 == VAR1) && (VAR5 != 0)) || ((VAR4 == VAR7) && (VAR4 != 0)))
begin
assign VAR3 = 1;
assign V... | gpl-3.0 |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/buffer_builder.v | 5,889 | module MODULE1 #(
parameter VAR23 = 13, parameter VAR37 = 32
)(
input VAR10,
input rst,
input [1:0] VAR2, output reg VAR13,
input VAR8,
input [VAR23 - 1: 0] VAR17,
input [VAR37 - 1: 0] VAR11,
input VAR1,
input [23:0] VAR29,
input [1:0] VAR16,
output reg [1:0] VAR34,
input [23:0] VAR22,
output reg VAR20,
output [VAR37 -... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o_2.v | 2,348 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR7 ,
VAR10 ,
VAR4 ,
VAR8,
VAR11,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
input VAR8;
input VAR11;
input VAR6 ;
input VAR1 ;
VAR2 VAR3 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR6(VAR6),
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_2.functional.pp.v | 1,235 | module MODULE1( VAR8, VAR4, VAR13, VAR2, VAR1, VAR10 );
input VAR2, VAR13, VAR4;
inout VAR1, VAR10;
output VAR8;
wire VAR6;
not VAR3( VAR6, VAR2 );
wire VAR9;
not VAR12( VAR9, VAR13 );
wire VAR11;
not VAR7( VAR11, VAR4 );
and VAR5( VAR8, VAR6, VAR9, VAR11 );
endmodule | apache-2.0 |
yupferris/hello-everyweeks | hello.v | 1,666 | module MODULE1(
input VAR7,
input VAR14,
output VAR10);
reg [7:0] VAR15;
reg VAR2;
wire VAR6;
reg [0:VAR13 - 1] VAR12;
reg [1:0] state;
always @(posedge VAR7 or negedge VAR14)
if (VAR14 == 1'b0) begin
VAR15 <= 0;
VAR2 <= 0;
VAR12 <= VAR4;
state <= VAR11;
end else begin
case (state)
if (VAR12[0:7] != 0) begin
VAR15 <= V... | bsd-2-clause |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T23-fsmtx/fsmtx2.v | 4,890 | module MODULE1 (input wire clk, output reg VAR20 );
parameter VAR10 = VAR7;
parameter VAR1 = "VAR14";
parameter VAR24 = VAR22;
reg [9:0] VAR3;
wire VAR4;
reg VAR11;
wire VAR19;
reg VAR23 = 0;
reg [3:0] VAR16;
wire VAR6; wire VAR8;
always @(posedge clk)
VAR11 <= VAR4;
always @(posedge clk)
if (VAR23 == 0)
VAR3 <= 10'b11... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.behavioral.v | 1,110 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
boztalay/HighSchoolSeniorProject | FPGA Stuff/OZ4_Mandelbrot/Hardware/OZ4_Mandelbrot/FIFO30x16.v | 14,036 | module MODULE1(
rst,
VAR219,
VAR288,
din,
VAR120,
VAR164,
dout,
VAR42,
VAR224,
VAR22,
VAR193
);
input rst;
input VAR219;
input VAR288;
input [30 : 0] din;
input VAR120;
input VAR164;
output [30 : 0] dout;
output VAR42;
output VAR224;
output VAR22;
output VAR193;
VAR206 #(
.VAR110(0),
.VAR392(0),
.VAR171(0),
.VAR118(0),... | mit |
open-power/snap | actions/hdl_helloworld/hw/hdl/fifo_axi_lcl.v | 4,215 | module MODULE1(
input clk ,
input VAR12,
input VAR15 ,
output reg VAR14 ,
output reg VAR22 ,
input VAR20 , output reg VAR13 , input VAR8 ,
input [511:0] din ,
input VAR4 , output VAR18, output reg VAR9 , output [511:0] dout ,
output VAR23 ,
output VAR19,
output reg VAR6
);
reg [04:00] VAR16 ;
reg [04:00] VAR26 ;
wire[0... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.behavioral.pp.v | 1,179 | module MODULE1( VAR1, VAR2, VAR4, VAR5 );
input VAR1;
inout VAR4, VAR5;
output VAR2;
VAR6 VAR3(.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5));
VAR6 VAR7(.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/and4/gf180mcu_fd_sc_mcu7t5v0__and4_4.behavioral.v | 1,322 | module MODULE1( VAR6, VAR4, VAR3, VAR8, VAR7 );
input VAR3, VAR8, VAR4, VAR6;
output VAR7;
VAR2 VAR5(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7));
VAR2 VAR1(.VAR6(VAR6),.VAR4(VAR4),.VAR3(VAR3),.VAR8(VAR8),.VAR7(VAR7)); | apache-2.0 |
svofski/mahponk | src/vga.v | 6,013 | module MODULE1(clk, VAR43, VAR76, VAR10, VAR59, VAR46, VAR28, VAR53, VAR33, VAR47, VAR2, VAR55, VAR69, VAR65, VAR7);
input clk;
output VAR43;
output VAR76;
output VAR10;
output VAR59;
output VAR46, VAR28, VAR53;
input VAR33;
output VAR47;
output VAR2;
output VAR55;
output VAR69;
input VAR65;
input VAR7;
wand VAR46;
wan... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/buf/sky130_fd_sc_hdll__buf_1.v | 2,009 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2,
VAR6,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR7 ;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR2;
supply0 VAR6;... | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/common/resetter.v | 1,061 | module MODULE1(
clk,
VAR1,
VAR3 );
parameter VAR6 = 4;
input clk;
input VAR1;
output VAR3; reg VAR3;
reg [VAR6:0] VAR5;
reg VAR2,VAR4;
begin
begin
begin | gpl-3.0 |
horia141/bachelor-thesis | prj/components/RegBank/RegBankP2.v | 3,891 | module MODULE1(VAR15,reset,VAR13,VAR17,VAR3,VAR20);
input wire VAR15;
input wire reset;
input wire [11:0] VAR13;
input wire VAR17;
output wire [7:0] VAR3;
output wire [7:0] VAR20;
reg [1:0] VAR18;
reg [7:0] VAR23;
reg [7:0] VAR7;
wire [3:0] VAR21;
wire [7:0] VAR22;
reg [256*8-1:0] VAR14;
reg [256*8-1:0] VAR24;
assign V... | mit |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_1/synth/design_1_auto_us_1.v | 10,494 | module MODULE1 (
VAR30,
VAR80,
VAR79,
VAR14,
VAR31,
VAR35,
VAR17,
VAR99,
VAR93,
VAR24,
VAR2,
VAR51,
VAR68,
VAR25,
VAR64,
VAR32,
VAR82,
VAR36,
VAR86,
VAR88,
VAR55,
VAR53,
VAR5,
VAR100,
VAR50,
VAR16,
VAR23,
VAR47,
VAR34,
VAR89,
VAR44,
VAR52,
VAR18,
VAR21,
VAR39,
VAR26,
VAR91,
VAR41,
VAR98,
VAR28
);
input wire VAR30;
inpu... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp0.v | 15,897 | module MODULE1(
VAR26, VAR14,
VAR6, VAR51, VAR24, VAR11,
VAR35, VAR46,
VAR29, VAR33, VAR40,
VAR41, VAR45, VAR32,
VAR16, VAR15, VAR31,
VAR36
);
output [7:0] VAR26;
output [VAR22-1:0] VAR14;
input [7:0] VAR33; input [7:0] VAR29; input [7:0] VAR46; input [7:0] VAR35; input [7:0] VAR11; input VAR24; input [7:0] VAR51; inpu... | gpl-2.0 |
agnicol88/Gaussian_Num_Gen | Vivado/gng/gng.srcs/sources_1/new/coeff_store.v | 23,854 | module MODULE1(
input clk,
input [7:0] addr,
output [17:0] VAR3,
output [17:0] VAR1,
output [20:0] VAR6
);
reg [56:0] VAR2 = 57'd0;
reg [17:0] VAR7 = 18'd0;
reg [17:0] VAR5 = 18'd0;
reg [20:0] VAR4 = 21'd0;
assign VAR3 = VAR7;
assign VAR1 = VAR5;
assign VAR6 = VAR4;
always @ (posedge clk) begin
VAR7 <= VAR2[56:39];
VAR... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/traffic_gen/afifo.v | 6,916 | module MODULE1 #
(
parameter VAR25 = 100,
parameter VAR32 = 32,
parameter VAR15 = 16,
parameter VAR39 = 4,
parameter VAR10 = 1 )
(
input VAR3,
input rst,
input VAR23,
input [VAR32-1:0] VAR40,
input VAR37,
input VAR16,
output [VAR32-1:0] VAR17,
output reg VAR34,
output reg VAR36,
output reg VAR33
);
reg [VAR32-1:0] VAR2... | lgpl-3.0 |
jimurai/okWishboneMaster | verilog/dp_ram.v | 1,108 | module MODULE1 #(
parameter VAR8 = 16,
parameter VAR13 = 10
) (
input wire VAR7,
input wire VAR12,
input wire [VAR13-1:0] VAR4,
input wire [VAR8-1:0] VAR1,
output reg [VAR8-1:0] VAR11,
input wire VAR3,
input wire VAR6,
input wire [VAR13-1:0] VAR2,
input wire [VAR8-1:0] VAR9,
output reg [VAR8-1:0] VAR10
);
reg [VAR8-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b.functional.pp.v | 1,998 | module MODULE1 (
VAR10 ,
VAR11 ,
VAR9 ,
VAR17 ,
VAR16 ,
VAR12,
VAR2,
VAR8 ,
VAR15
);
output VAR10 ;
input VAR11 ;
input VAR9 ;
input VAR17 ;
input VAR16 ;
input VAR12;
input VAR2;
input VAR8 ;
input VAR15 ;
wire VAR3 ;
wire VAR14 ;
wire VAR5;
not VAR1 (VAR3 , VAR16 );
or VAR7 (VAR14 , VAR3, VAR17, VAR9, VAR11 );
VAR6 V... | apache-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/imports/hdl/daala_idct4_mmap_v1_0_S00_AXI.v | 14,666 | module MODULE1 #
(
parameter integer VAR39 = 32,
parameter integer VAR22 = 4
)
(
input wire VAR23,
input wire VAR27,
input wire [VAR22-1 : 0] VAR16,
input wire [2 : 0] VAR26,
input wire VAR53,
output wire VAR32,
input wire [VAR39-1 : 0] VAR52,
input wire [(VAR39/8)-1 : 0] VAR10,
input wire VAR18,
output wire VAR6,
outp... | bsd-2-clause |
asicguy/gplgpu | hdl/altera_plls/pix_pll_bt_bb.v | 12,245 | module MODULE1 (
VAR3,
VAR5,
VAR1,
VAR4,
VAR2);
input VAR3;
input VAR5;
output VAR1;
output VAR4;
output VAR2;
tri0 VAR3;
endmodule | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Dynamic_Saturation_block.v | 2,320 | module MODULE1
(
VAR2,
VAR8,
VAR4,
VAR10,
VAR14
);
input signed [17:0] VAR2; input signed [35:0] VAR8; input signed [17:0] VAR4; output signed [35:0] VAR10; output VAR14;
wire signed [35:0] VAR3; wire VAR6;
wire signed [35:0] VAR7; wire VAR5;
wire signed [35:0] VAR1; wire signed [35:0] VAR9; wire signed [35:0] VAR11; w... | gpl-3.0 |
efabless/openlane | designs/151/src/datapath.v | 10,651 | module MODULE1(
input clk, reset,
input VAR80,
input wire [1:0] VAR82,
input wire VAR28,
input wire VAR35,
input wire VAR30,
output wire [4:0] VAR99,
output wire [4:0] VAR69,
output wire [4:0] VAR75,
output wire [6:0] VAR22,
output wire [2:0] VAR65,
input wire [1:0] VAR14,
input wire [2:0] VAR45,
input wire [1:0] VAR84... | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_decoder.v | 2,220 | module MODULE1
(VAR5, VAR4);
parameter VAR3 = 8;
localparam VAR2 = VAR7(VAR3);
input [0:VAR2-1] VAR5;
output [0:VAR3-1] VAR4;
wire [0:VAR3-1] VAR4;
generate
genvar VAR6;
for(VAR6 = 0; VAR6 < VAR3; VAR6 = VAR6 + 1)
begin:VAR1
assign VAR4[VAR6] = (VAR5 == VAR6);
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf.behavioral.pp.v | 1,746 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5,
VAR3,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR9 ;
input VAR5;
input VAR3;
input VAR6 ;
input VAR2 ;
wire VAR12 ;
wire VAR1;
buf VAR4 (VAR12 , VAR9 );
VAR10 VAR7 (VAR1, VAR12, VAR5, VAR3);
buf VAR11 (VAR8 , VAR1 );
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/DE5-Net/fpga/rtl/fpga.v | 11,843 | module MODULE1 (
input wire VAR168,
input wire [3:0] VAR57,
input wire [3:0] VAR1,
output wire [6:0] VAR191,
output wire VAR246,
output wire [6:0] VAR90,
output wire VAR35,
output wire [3:0] VAR67,
output wire [3:0] VAR108,
output wire VAR156,
output wire VAR128,
output wire VAR59,
input wire VAR155,
input wire VAR123,... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_49.v | 34,524 | module MODULE1 (
clk,
reset,
VAR22,
VAR105,
VAR23,
VAR16,
VAR181
);
parameter VAR67 = 18;
parameter VAR235 = 49;
parameter VAR285 = 25;
localparam VAR56 = 56;
input clk;
input reset;
input VAR22;
input VAR105;
input [VAR67-1:0] VAR23; output VAR16;
output [VAR67-1:0] VAR181;
localparam VAR243 = 18; localparam VAR54 = 3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp.functional.pp.v | 1,644 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR1 ,
VAR11,
VAR6,
VAR12 ,
VAR3
);
output VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR11;
input VAR6;
input VAR12 ;
input VAR3 ;
wire VAR10;
VAR7 VAR8 VAR5 (VAR10 , VAR1, VAR2, , VAR11, VAR6);
buf VAR4 (VAR9 , VAR10 );
endmodule | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/vfabric_sextend.v | 1,512 | module MODULE1(VAR5, VAR2,
VAR3, VAR8, VAR10,
VAR1, VAR7, VAR6);
parameter VAR4 = 32;
parameter VAR9 = 64;
input VAR5, VAR2;
input [VAR4-1:0] VAR3;
input VAR8;
output VAR10;
output [VAR9-1:0] VAR1;
input VAR7;
output VAR6;
assign VAR1 = {{VAR9{VAR3[VAR4-1]}}, VAR3[VAR4-1:0]};
assign VAR10 = VAR7;
assign VAR6 = VAR8;
en... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/submidRecursiveKOA.v | 5,160 | module MODULE1
(
input wire clk,
input wire [VAR2-1:0] VAR18,
input wire [VAR2-1:0] VAR11,
output reg [2*VAR2-1:0] VAR1
);
wire [1:0] VAR19;
wire [3:0] VAR5;
assign VAR19 = 2'b00;
assign VAR5 = 4'b0000;
wire [VAR2/2-1:0] VAR4;
wire [VAR2/2:0] VAR20;
wire [VAR2/2-3:0] VAR21;
wire [VAR2/2-4:0] VAR13;
reg [4*(VAR2/2)+2:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2b/sky130_fd_sc_hd__nand2b.functional.pp.v | 1,936 | module MODULE1 (
VAR15 ,
VAR11 ,
VAR1 ,
VAR14,
VAR7,
VAR9 ,
VAR10
);
output VAR15 ;
input VAR11 ;
input VAR1 ;
input VAR14;
input VAR7;
input VAR9 ;
input VAR10 ;
wire VAR8 ;
wire VAR3 ;
wire VAR12;
not VAR4 (VAR8 , VAR1 );
or VAR5 (VAR3 , VAR8, VAR11 );
VAR6 VAR2 (VAR12, VAR3, VAR14, VAR7);
buf VAR13 (VAR15 , VAR12 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111a/sky130_fd_sc_hd__o2111a_2.v | 2,448 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR6 ,
VAR11 ,
VAR8,
VAR4,
VAR10 ,
VAR12
);
output VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR11 ;
input VAR8;
input VAR4;
input VAR10 ;
input VAR12 ;
VAR5 VAR2 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR8(V... | apache-2.0 |
hanw/sonic-lite | hw/verilog/gearbox/gearbox_66_40.v | 5,511 | module MODULE1 (
input clk,
input VAR3, input [65:0] din, output reg VAR4,
output reg VAR6,
output reg VAR7,
output [39:0] dout
);
reg [5:0] VAR1 = 0 ;
reg [103:0] VAR9 = 0 ;
assign dout = VAR9[39:0];
reg [65:0] VAR2 = 0;
always @(posedge clk) begin
VAR2 <= din[65:0];
VAR1 <= (VAR3 | VAR1[5]) ? 6'h0 : (VAR1 + 1'b1);
if... | mit |
manu3193/GatoTDD | Controlador_Gato.v | 4,268 | module MODULE1(
clk,
VAR56,
VAR88,
VAR24,
VAR73,
VAR16,
VAR69,
state,
VAR92, VAR58, VAR14, VAR7, VAR62,
VAR97, VAR84,
VAR110, VAR104, VAR74,
VAR85,
VAR36,
VAR41,
VAR102,
VAR81,
VAR42,
VAR38,
VAR52,
VAR20
);
input clk, VAR56, VAR88;
output [2:0] state;
output [3:0] VAR24;
output [1:0] VAR73, VAR16, VAR69;
output VAR97, ... | mit |
impedimentToProgress/UCI-BlueChip | AttackFiles/Attacks/privEsc/lib/opencores/ata/ata_device_oc.v | 15,606 | module MODULE1( VAR2, VAR9, VAR8, VAR16, VAR3,
VAR22, VAR18, VAR17, VAR20 );
input VAR2;
inout [15:0] VAR9;
input [2:0] VAR8;
input VAR16, VAR3;
input VAR22, VAR18;
output VAR17;
output VAR20;
integer VAR6;
integer VAR7;
reg VAR17;
reg VAR12;
reg VAR20;
integer VAR19;
reg [15:0] VAR13[32:0];
reg [15:0] dout;
reg VAR11;... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_INVBUF_SLVT_TT_201020.v | 17,248 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
MeshSr/onetswitch45 | ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/core/tx_queue.v | 10,742 | module MODULE1
parameter VAR34 = 64,
parameter VAR45 = VAR34/8,
parameter VAR49 = 1,
parameter VAR66 = 'hff,
parameter VAR67 = 32,
parameter VAR63 = VAR67/8
)
(input [VAR34-1:0] VAR31,
input [VAR45-1:0] VAR64,
input VAR30,
output VAR28,
input VAR2,
output reg VAR38,
output [VAR67 - 1 : 0] VAR35,
output reg VAR68,
outpu... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill.pp.symbol.v | 1,175 | module MODULE1 (
input VAR3 ,
input VAR1,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
mwswartwout/EECS318 | hw1/problem5/behavioral.v | 1,198 | module MODULE1(out, VAR2, VAR4, VAR3, VAR1);
output out;
reg VAR2, VAR4, VAR3, VAR1;
if (~VAR2 && ~VAR4 && ~VAR3 && ~VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b0;
out = 1'b1;
end
if (~VAR2 && ~VAR4 && ~VAR3 && VAR1)
begin
VAR2 = 1'b0;
VAR4 = 1'b1;
out = 1'b1;
end
if (~VAR2 && ~VAR4 && VAR3 && ~VAR1)
begin
VAR2 = 1'b1;
VAR4 = 1... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/xilinx_pcie_2_0_ep_v6.v | 17,967 | module MODULE1 # (
parameter VAR125 = "VAR129",
parameter VAR90 = 64, parameter VAR35 = VAR90 / 8 )
(
output [3:0] VAR131,
output [3:0] VAR48,
input [3:0] VAR88,
input [3:0] VAR21,
output VAR110,
output VAR16,
output VAR120,
input VAR128,
input VAR42,
input VAR71
);
wire VAR121;
wire VAR17;
wire VAR39;
wire [5:0] VAR54... | lgpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/esaxilite/hdl/esaxilite.v | 2,478 | module MODULE1 (
VAR24, VAR19, VAR9,
VAR11, VAR23, VAR22, VAR12,
VAR4, VAR26, VAR1, VAR16, VAR15, VAR6,
VAR8, VAR7, VAR3,
VAR25, VAR14, VAR13,
VAR5, VAR20, VAR17, VAR10,
VAR21, VAR2
);
parameter VAR18 = 16;
input [15:0] VAR8;
input [2:0] VAR7;
output VAR24;
input VAR3;
input [15:0] VAR25;
input [2:0] VAR14;
output VAR1... | gpl-3.0 |
stevenokm/mor1kx | rtl/verilog/mor1kx_lsu_espresso.v | 7,734 | module MODULE1
(
VAR1, VAR3, VAR12, VAR14,
VAR18, VAR4, VAR27, VAR45, VAR15,
VAR42,
clk, rst, VAR37, VAR39, VAR20, VAR25,
VAR26, VAR31, VAR16, VAR23,
VAR7, VAR6, VAR36, VAR33,
VAR11, VAR9
);
parameter VAR2 = 32;
parameter VAR29 = "VAR41";
input clk, rst;
input VAR37;
input [VAR2-1:0] VAR39;
input [VAR2-1:0] VAR20;
inpu... | mpl-2.0 |
Gum-Joe/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_trn_monitor.v | 23,857 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR88, input wire [31:0] VAR12, input wire [31:0] VAR22, output reg VAR45, input wire VAR7,
input wire VAR86,
input wire VAR37, VAR65
output reg [4:0] VAR9,
output reg [31:0] VAR57,
output reg VAR75,
output wire [4:0] VAR109,
input [31:0] VAR72,
output reg VAR5... | bsd-2-clause |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.