repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai.pp.blackbox.v | 1,414 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR3 ,
VAR4 ,
VAR2,
VAR7,
VAR8 ,
VAR10
);
output VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR3 ;
input VAR4 ;
input VAR2;
input VAR7;
input VAR8 ;
input VAR10 ;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_force_adapt.v | 12,861 | module MODULE1 (
input VAR11,
input VAR7,
input [5:0] VAR28,
input [2:0] VAR47,
input [1:0] VAR21,
input VAR32,
input VAR1,
input [1:0] VAR22,
input [31:0] VAR12,
input [31:0] VAR14,
input [31:0] VAR24,
input [31:0] VAR6,
input [31:0] VAR49,
input [31:0] VAR55,
input [31:0] VAR4,
input [31:0] VAR45,
input [1:0] VAR23,
... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/cycloneiii_atoms.v | 253,033 | module MODULE1(
primitive VAR8 (VAR17, VAR3, VAR10, VAR7, VAR6, VAR5, VAR2);
input VAR10;
input VAR6;
input VAR5;
input VAR7;
input VAR3;
input VAR2;
output VAR17; reg VAR17;
VAR1 VAR17 = 1'b0;
VAR12
(??) ? ? 1 1 ? : ? : -; VAR16 ? ? 1 1 ? : ? : -; 1 1 (01) 1 1 ? : ? : 1; 1 1 (01) 1 VAR16 ? : ? : 1;
1 1 ? 1 VAR16 ? : 1... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_autoStart.v | 2,126 | module MODULE1 (
address,
VAR5,
clk,
VAR9,
VAR2,
VAR3,
VAR8,
VAR7
)
;
output VAR8;
output [ 31: 0] VAR7;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR9;
input VAR2;
input [ 31: 0] VAR3;
wire VAR1;
reg VAR6;
wire VAR8;
wire VAR4;
wire [ 31: 0] VAR7;
assign VAR1 = 1;
assign VAR4 = {1 {(address == 0)}} & VAR6;
a... | gpl-3.0 |
niketancm/tsea26 | lab2-3/rtl/loop_controller.v | 3,194 | module MODULE1
parameter VAR3 = VAR11,
parameter VAR7 = VAR32,
parameter VAR24 = VAR40)
(
input wire VAR2,
input wire VAR17,
input wire VAR26,
input wire [VAR8-1:0] VAR34,
input wire [VAR3-1:0] VAR19,
input wire [VAR3-1:0] VAR16,
output wire VAR5,
output wire [VAR3-1:0] VAR23,
output wire [VAR3-1:0] VAR31,
input wire [... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/settings_bus.v | 1,581 | module MODULE1
(input VAR8,
input VAR2,
input [VAR10-1:0] VAR4,
input [VAR13-1:0] VAR6,
input VAR7,
input VAR11,
output reg VAR9,
output reg VAR12,
output reg [7:0] addr,
output reg [31:0] VAR5);
reg VAR1, VAR3;
always @(posedge VAR8)
if(VAR2)
begin
VAR12 <= 1'b0;
addr <= 8'd0;
VAR5 <= 32'd0;
end
else if(VAR11 & VAR7 &... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.behavioral.v | 1,893 | module MODULE1 (
VAR2 ,
VAR13,
VAR7,
VAR9
);
output VAR2 ;
output VAR13;
input VAR7;
input VAR9 ;
supply1 VAR12;
supply0 VAR6;
supply1 VAR14 ;
supply0 VAR10 ;
wire VAR16 ;
reg VAR1 ;
wire VAR17 ;
wire VAR15;
wire VAR3 ;
VAR5 VAR8 (VAR16 , VAR17, VAR15, VAR1, VAR12, VAR6);
assign VAR3 = ( VAR12 === 1'b1 );
buf VAR4 (VAR... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_alu_a.v | 2,180 | module MODULE1 (
address,
VAR5,
clk,
VAR9,
VAR6,
VAR4,
VAR2,
VAR3
)
;
output [ 31: 0] VAR2;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR9;
input VAR6;
input [ 31: 0] VAR4;
wire VAR7;
reg [ 31: 0] VAR1;
wire [ 31: 0] VAR2;
wire [ 31: 0] VAR8;
wire [ 31: 0] VAR3;
assign VAR7 = 1;
assign V... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/xgmii_deinterleave.v | 2,166 | module MODULE1
(
input wire [72:0] VAR3,
output wire [63:0] VAR1,
output wire [7:0] VAR2
);
assign VAR1[7:0] = VAR3[7:0];
assign VAR2[0] = VAR3[8];
assign VAR1[15:8] = VAR3[16:9];
assign VAR2[1] = VAR3[17];
assign VAR1[23:16] = VAR3[25:18];
assign VAR2[2] = VAR3[26];
assign VAR1[31:24] = VAR3[34:27];
assign VAR2[3] = V... | mit |
SiLab-Bonn/pyBAR | firmware/mmc3_8_chip_multi_tx_eth_SHIP/src/mmc3_8chip_multi_tx_eth_SHIP.v | 34,678 | module MODULE1(
input wire VAR6,
input wire VAR49,
output wire [3:0] VAR325,
output wire VAR22,
output wire VAR44,
input wire [3:0] VAR184,
input wire VAR415,
input wire VAR206,
output wire VAR169,
inout wire VAR341,
output wire VAR306,
output wire [7:0] VAR120,
output wire [7:0] VAR205, VAR52,
output wire [7:0] VAR7, ... | bsd-3-clause |
vipinkmenon/fpgadriver | src/hw/fpga/source/user_logic_if/user_dma_req_arbitrator.v | 5,092 | module MODULE1 #(
parameter VAR37 = 'd4,
parameter VAR28 = 'd32,
parameter VAR20 = 'd12,
parameter VAR38 = 'd8,
parameter VAR22 = 'd64,
parameter VAR21 = 'd5
)
(
input VAR35,
input VAR10,
input [VAR37-1:0] VAR16,
input [VAR28*VAR37-1:0] VAR2,
input [VAR20*VAR37-1:0] VAR6,
input [VAR38*VAR37-1 :0] VAR30,
output reg [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.symbol.v | 1,349 | module MODULE1 (
input VAR2,
input VAR7,
input VAR3,
output VAR8
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_cx4/cx4_mul.v | 4,636 | module MODULE1 (
VAR11,
VAR18,
VAR16,
VAR20);
input VAR11;
input [23:0] VAR18;
input [23:0] VAR16;
output [47:0] VAR20;
wire [47:0] VAR10;
wire [47:0] VAR20 = VAR10[47:0];
VAR12 VAR1 (
.VAR11 (VAR11),
.VAR18 (VAR18),
.VAR16 (VAR16),
.VAR20 (VAR10),
.VAR2 (1'b0),
.VAR6 (1'b1),
.VAR15 (1'b0),
.sum (1'b0));
VAR1.VAR7 = "... | gpl-2.0 |
mdsalman729/flexpret_project | fpga/generated-src/Core.v | 161,872 | module MODULE1(input clk, input reset,
input [3:0] VAR233,
input [3:0] VAR239,
input [3:0] VAR78,
input [3:0] VAR7,
input [3:0] VAR197,
input [3:0] VAR26,
input [3:0] VAR9,
input [3:0] VAR120,
input [1:0] VAR86,
input [1:0] VAR111,
input [1:0] VAR169,
input [1:0] VAR47,
output[1:0] VAR39,
output VAR187
);
wire VAR75;
w... | bsd-3-clause |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter.v | 6,149 | module MODULE1 #(
parameter VAR2 = 18,
parameter VAR19 = 0,
parameter VAR4 = 18,
parameter VAR14 = 0,
parameter VAR9 = 0,
parameter VAR17 = 0,
parameter VAR18 = 1,
parameter VAR10 = 1,
parameter VAR24 = 0,
parameter VAR25 = 18,
parameter VAR12 = 0,
parameter VAR1 = 1,
parameter VAR20 = 0,
parameter VAR7 = 1,
parameter ... | gpl-2.0 |
kyzhai/NUNY | src/hardware/tryagain_bb.v | 5,008 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
defparam/snes-hook | verilog/snes_bus_sync.v | 4,455 | module MODULE2 (
input clk, input VAR3,
input [7:0] VAR9, output VAR10 );
parameter VAR4 = 1'b1;
parameter VAR13 = 1'b0;
reg [7:0] VAR2 [0:1];
reg VAR8 = VAR13;
reg VAR7 = 0;
always @(posedge clk or negedge VAR3) begin
if (~VAR3) begin
VAR2[0] <= 8'b0; VAR2[1] <= 8'b0;
VAR7 <= 1'b0;
VAR8 <= VAR13;
end
else begin
VAR2[0... | gpl-3.0 |
jeffkub/n64-cart-reader | old/n64cartridge/src/sdram/sdram_control_fsm.v | 46,628 | module MODULE1 (
VAR104,
VAR82,
VAR10,
VAR37,
VAR5,
VAR125, VAR103, VAR54, VAR16, VAR69, VAR24,
VAR70,
VAR49, VAR63, VAR7, VAR23, VAR87, VAR116,
VAR31,
VAR124,
VAR85,
VAR110,
VAR8,
VAR12, VAR11, VAR39, VAR112, VAR43, VAR131, VAR19, VAR25, VAR75, VAR67, VAR78 );
input VAR104;
input VAR82;
input VAR10;
input VAR5;
input ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.functional.v | 1,728 | module MODULE1( VAR21, VAR14, VAR23, VAR18, VAR17, VAR13, VAR25 );
input VAR18, VAR23, VAR17, VAR21, VAR14, VAR25;
output VAR13;
not VAR1( VAR8, VAR17 );
wire VAR9;
not VAR19( VAR9, VAR23 );
wire VAR20;
not VAR15( VAR20, VAR21 );
wire VAR26;
and VAR11( VAR26, VAR9, VAR20 );
wire VAR6;
not VAR2( VAR6, VAR14 );
wire VAR1... | apache-2.0 |
AttackerJin/8bit_datapath_AES | AES128/sbox_case_4.v | 5,703 | module MODULE2 ( VAR62, VAR40 );
input [1:0] VAR62;
output [1:0] VAR40;
assign VAR40 = { VAR62[0], VAR62[1] };
endmodule
module MODULE5 ( VAR62, VAR23, VAR49, VAR60, VAR6 );
input [1:0] VAR62;
input VAR23;
input [1:0] VAR49;
input VAR60;
output [1:0] VAR6;
wire VAR54, VAR2, VAR45;
assign VAR54 = ~(VAR23 & VAR60);
assig... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.v | 3,782 | module MODULE1
(input VAR40
, input VAR42
, input VAR3
, input VAR57 , input VAR48
, output VAR55
, output VAR45
);
wire [1:0] VAR5;
wire [8:0] VAR63;
wire VAR58;
assign VAR63[0] = VAR40;
VAR29 VAR54 (.VAR20(VAR63[0]), .VAR22(VAR63[1]) );
VAR29 VAR10 (.VAR20(VAR63[1]), .VAR22(VAR63[2]) );
VAR18 VAR11 (.VAR20(VAR63[1]),... | bsd-3-clause |
gitlabhq/linguist | samples/Verilog/sign_extender.v | 1,665 | module MODULE1
parameter
VAR6 = 8,
VAR3 = 16
)
(
input [VAR6-1:0] VAR1,
output reg [VAR3-1:0] VAR7
);
wire [VAR3-VAR6-1:0] VAR4;
generate
genvar VAR5;
for (VAR5 = 0; VAR5 < VAR3-VAR6; VAR5 = VAR5 + 1) begin : VAR2
assign VAR4[VAR5] = (VAR1[VAR6-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
VAR7 = {VAR4,VAR1};
end... | mit |
cfib/bf2hw | lib/toplevel/sync_fifo.v | 5,269 | module MODULE1
parameter VAR17 = 32,
parameter VAR20 = 32,
parameter VAR15 = VAR10(VAR17),
parameter VAR3 = VAR10(VAR17+1)
)
(
input clk,
input reset,
input VAR5,
input VAR1,
output reg VAR21,
output reg VAR6,
output [VAR20-1:0] VAR16,
input [VAR20-1:0] VAR8,
output reg [VAR3-1:0] VAR13
);
function integer VAR10;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.pp.symbol.v | 1,350 | module MODULE1 (
input VAR3,
input VAR1,
input VAR4 ,
input VAR6 ,
output VAR2 ,
input VAR5,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp.behavioral.pp.v | 1,841 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR2,
VAR7,
VAR4,
VAR9 ,
VAR1
);
output VAR5 ;
input VAR13 ;
input VAR2;
input VAR7;
input VAR4;
input VAR9 ;
input VAR1 ;
wire VAR3 ;
wire VAR12;
wire VAR11 ;
reg VAR14 ;
wire VAR10 ;
VAR8 VAR15 (VAR3 , VAR11, VAR12, VAR14, VAR7, VAR4);
buf VAR6 (VAR5 , VAR3 );
assign VAR10 = ( VAR7 ===... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/Tiger4NSC/src/ScrambleDecoder.v | 9,005 | module MODULE1
(
parameter VAR35 = 32 ,
parameter VAR8 = 32 ,
parameter VAR3 = 16 ,
parameter VAR27 = 3
)
(
VAR40 ,
VAR29 ,
VAR34 ,
VAR20 ,
VAR31 ,
VAR12 ,
VAR50 ,
VAR48 ,
VAR51 ,
VAR7 ,
VAR53 ,
VAR23 ,
VAR13 ,
VAR52 ,
VAR17 ,
VAR45 ,
VAR21 ,
VAR16 ,
VAR33 ,
VAR10 ,
VAR15 ,
VAR49 ,
VAR22 ,
VAR30
);
input VAR40 ;
input ... | gpl-3.0 |
everskar2013/PentiumX | Hardware/Code/Coprocessor.v | 1,208 | module MODULE1(
clk,
rst,
VAR3,
VAR15,
VAR11,
VAR10,
VAR6,
VAR2,
VAR4,
VAR13,
VAR1,
VAR14,
VAR7,
VAR12,
VAR9
);
input clk, rst;
input wire [31: 0] VAR11, VAR10;
input wire [ 4: 0] VAR3, VAR15;
input wire [ 4: 0] VAR6;
input wire VAR2, VAR4, VAR13,
VAR7, VAR12;
output wire [31: 0] VAR1, VAR14, VAR9;
integer VAR5 = 0;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_mux_2to1_n/sky130_fd_sc_hs__udp_mux_2to1_n.blackbox.v | 1,236 | module MODULE1 (
VAR2 ,
VAR3,
VAR1,
VAR4
);
output VAR2 ;
input VAR3;
input VAR1;
input VAR4 ;
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_m01_regslice_0/synth/zc702_m01_regslice_0.v | 10,708 | module MODULE1 (
VAR52,
VAR11,
VAR100,
VAR109,
VAR31,
VAR5,
VAR102,
VAR33,
VAR24,
VAR83,
VAR94,
VAR70,
VAR78,
VAR60,
VAR55,
VAR43,
VAR27,
VAR45,
VAR54,
VAR67,
VAR50,
VAR91,
VAR56,
VAR80,
VAR18,
VAR36,
VAR51,
VAR17,
VAR108,
VAR92,
VAR10,
VAR28,
VAR34,
VAR40,
VAR3,
VAR38,
VAR6,
VAR25,
VAR16,
VAR95
);
input wire VAR52;
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.blackbox.v | 1,278 | module MODULE1 (
VAR4,
VAR1,
VAR6
);
output VAR4;
input VAR1;
input VAR6;
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_xfer_cntrl.v | 4,640 | module MODULE1 #(
parameter VAR16 = 8) (
input VAR1,
input VAR14,
input [(VAR16-1):0] VAR2,
output VAR17,
input VAR15,
input VAR12,
output [(VAR16-1):0] VAR11);
reg VAR5 = 'd0;
reg VAR18 = 'd0;
reg VAR9 = 'd0;
reg [ 5:0] VAR21 = 'd0;
reg VAR4 = 'd0;
reg VAR22 = 'd0;
reg [(VAR16-1):0] VAR3 = 'd0;
reg VAR20 = 'd0;
reg VA... | mit |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/acl_multistage_adder.v | 5,327 | module MODULE1(VAR14, VAR6, VAR13, enable, VAR19, VAR20, VAR15, VAR21);
parameter VAR1 = 32;
parameter VAR24 = 19;
input VAR14, VAR6, VAR13, VAR21, enable;
input [VAR1-1:0] VAR20;
input [VAR1-1:0] VAR15;
output [VAR1-1:0] VAR19;
wire [VAR1-1:0] VAR8;
wire [VAR1-1:0] VAR26;
function integer VAR7;
input integer VAR5;
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai.pp.symbol.v | 1,387 | module MODULE1 (
input VAR8 ,
input VAR1 ,
input VAR4 ,
input VAR10 ,
input VAR9 ,
output VAR6 ,
input VAR5 ,
input VAR3,
input VAR7,
input VAR2
);
endmodule | apache-2.0 |
phase4ground/DVB-receiver | modem/hdl/library/fir_filter/fir_filter.v | 9,335 | module MODULE1 #
(
parameter integer VAR42 = 16,
parameter integer VAR2 = 16,
parameter integer VAR43 = 16,
parameter integer VAR25 = 16,
parameter integer VAR33 = -2,
parameter integer VAR53 = 1
)
(
input wire VAR40,
input wire VAR24,
output wire VAR34,
input wire [VAR2-1:0] VAR66,
input wire VAR51,
input wire VAR46,
... | gpl-3.0 |
bsteinsbo/DE1-SoC-Sound | DE1_SOC_Linux_Audio/DE1_SOC_Linux_Audio.v | 17,245 | module MODULE1(
inout VAR257,
output VAR9,
input VAR205,
output VAR203,
input VAR131,
inout VAR12,
inout VAR247,
output VAR259,
inout VAR62,
output VAR19,
input VAR250,
input VAR42,
input VAR45,
input VAR237,
output [12:0] VAR231,
output [1:0] VAR141,
output VAR33,
output VAR97,
output VAR209,
output VAR235,
inout [15:... | lgpl-2.1 |
bluespec/Flute | src_SSITH_P2/xilinx_ip/hdl/mkTLM2Source.v | 30,703 | module MODULE1(VAR84,
VAR35,
VAR31,
VAR163,
VAR139,
VAR152,
VAR60,
VAR1,
VAR81,
VAR72);
input [2 : 0] VAR84;
input VAR35;
input VAR31;
input VAR163;
input VAR139;
output [110 : 0] VAR152;
output VAR60;
input [44 : 0] VAR1;
input VAR81;
output VAR72;
wire [110 : 0] VAR152;
wire VAR72, VAR60;
reg VAR148;
wire VAR127, VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR6 ,
VAR2 ,
VAR1 ,
VAR8 ,
VAR4,
VAR7,
VAR5 ,
VAR10
);
output VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR4;
input VAR7;
input VAR5 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.behavioral.v | 1,733 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR11 ,
VAR5 ,
VAR4,
VAR8
);
output VAR10 ;
input VAR1 ;
input VAR11 ;
input VAR5 ;
input VAR4;
input VAR8;
wire VAR6 ;
wire VAR7;
xor VAR3 (VAR6 , VAR1, VAR11, VAR5 );
VAR12 VAR9 (VAR7, VAR6, VAR4, VAR8);
buf VAR2 (VAR10 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn.behavioral.v | 1,312 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR4
);
output VAR2 ;
input VAR3 ;
input VAR4;
supply1 VAR6;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR5 ;
bufif0 VAR1 (VAR2 , VAR3, VAR4 );
endmodule | apache-2.0 |
AEW2015/PYNQ_PR_Overlay | Pynq-Z1/vivado/ip/Pmods/PmodJSTK_v1_0/src/PmodJSTK.v | 10,163 | module MODULE1
(VAR37,
VAR95,
VAR104,
VAR87,
VAR91,
VAR150,
VAR151,
VAR34,
VAR98,
VAR159,
VAR119,
VAR44,
VAR127,
VAR97,
VAR116,
VAR25,
VAR153,
VAR27,
VAR157,
VAR2,
VAR118,
VAR112,
VAR92,
VAR110,
VAR154,
VAR71,
VAR152,
VAR109,
VAR122,
VAR85,
VAR52,
VAR100,
VAR55,
VAR108,
VAR158,
VAR168,
VAR1,
VAR139,
VAR121,
VAR46,
VAR1... | bsd-3-clause |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/DE2_NIOS_DEVICE_LED.v | 19,591 | module MODULE1
(
VAR175, VAR198, VAR88, VAR45, VAR166, VAR116, VAR205, VAR42, VAR136, VAR25, VAR2, VAR4, VAR74, VAR36, VAR72, VAR111, VAR85, VAR49, VAR124, VAR161, VAR48, VAR126, VAR190, VAR200, VAR58, VAR35, VAR119, VAR151, VAR103, VAR82, VAR164, VAR66, VAR19, VAR203, VAR55, VAR78, VAR104, VAR197, VAR94, VAR29, VAR191... | gpl-3.0 |
CospanDesign/sdio-device | rtl/generic/crc16.v | 2,879 | module MODULE1 #(
parameter VAR1 = 16'h1021,
parameter VAR4 = 16'h0000
)(
input clk,
input rst,
input en,
input bit,
output reg [15:0] VAR2
);
wire VAR3;
assign VAR3 = bit ^ VAR2[15];
always @ (posedge clk) begin
if (rst) begin
VAR2 <= 0;
end
else begin
if (en) begin
VAR2[15] <= VAR2[14];
VAR2[14] <= VAR2[13];
VAR2[13]... | mit |
jkanasu/utl | lab14eve16/asic/j01c_carrySkipAdder.v | 1,236 | module MODULE1(VAR8,VAR9,VAR10,VAR2,VAR11);
output [3:0]VAR8;
output VAR9;
input [3:0]VAR10,VAR2;
input VAR11;
wire [3:0]VAR7,VAR1; wire [4:0]VAR6; wire VAR5;
assign VAR6[0] = VAR11;
genvar VAR3;
for (VAR3=0; VAR3<=3; VAR3=VAR3+1)
begin
assign VAR1[VAR3] = VAR10[VAR3] ^ VAR2[VAR3];
assign VAR6[VAR3+1] = ( VAR10[VAR3] &... | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/DM9000A_IF.v | 1,398 | module MODULE1( VAR18,
VAR14,
VAR8,
VAR12,
VAR13,
VAR7,
VAR20,
VAR6,
VAR1,
VAR2,
VAR10,
VAR16,
VAR3,
VAR17,
VAR15,
VAR4,
VAR9,
VAR19 );
input [15:0] VAR18;
input VAR8;
input VAR12;
input VAR13;
input VAR7;
input VAR20;
input VAR6;
input VAR1;
output [15:0] VAR14;
output VAR2;
inout [15:0] VAR10;
output VAR16;
output VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_2.functional.v | 1,390 | module MODULE1( VAR4, VAR6, VAR14, VAR13, VAR1 );
input VAR1, VAR13, VAR14, VAR6;
output VAR4;
wire VAR11;
not VAR3( VAR11, VAR1 );
wire VAR12;
not VAR7( VAR12, VAR13 );
wire VAR10;
not VAR9( VAR10, VAR14 );
wire VAR8;
not VAR5( VAR8, VAR6 );
or VAR2( VAR4, VAR11, VAR12, VAR10, VAR8 );
endmodule | apache-2.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/dmem.v | 1,082 | module MODULE1(
output [31:0] VAR5,
input [31:0] VAR3, VAR2,
input VAR1, clk
);
reg [31:0] VAR4 [0:255];
assign VAR5 = (VAR3 != 0) ? VAR4[VAR3[7:0]] : 0;
always @ (posedge clk)
if (VAR1)
VAR4[VAR3[7:0]] <= VAR2;
endmodule | gpl-3.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/issue/instruction_arbiter.v | 7,459 | module MODULE1
(
VAR1, VAR56, VAR72,
VAR15, VAR81, VAR64,
VAR77, VAR58, VAR33,
VAR23, VAR11, VAR83, VAR14, VAR8,
VAR86, VAR46,
clk, rst, VAR16, VAR37,
VAR60, VAR3, VAR24,
VAR74, VAR80, VAR84, VAR55,
VAR34, VAR26, VAR6, VAR18,
VAR40
);
input clk, rst;
input [VAR17-1:0] VAR16, VAR37,
VAR60, VAR3;
input VAR24, VAR74,
VAR8... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfstp/sky130_fd_sc_hvl__dfstp.pp.blackbox.v | 1,339 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1 ,
VAR7,
VAR6 ,
VAR5 ,
VAR8 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR7;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
endmodule | apache-2.0 |
antmicro/yosys | techlibs/gatemate/mux_map.v | 1,493 | module \VAR12 (VAR14, VAR15, VAR21, VAR4, VAR16, VAR10, VAR9, VAR13, VAR27, VAR3, VAR25, VAR20);
input VAR14, VAR15, VAR21, VAR4, VAR16, VAR10, VAR9, VAR13, VAR27, VAR3, VAR25;
output VAR20;
VAR17 VAR28 (
.VAR18(VAR14), .VAR26(VAR15), .VAR19(VAR21), .VAR6(VAR4),
.VAR24(VAR16), .VAR5(VAR10), .VAR7(VAR9), .VAR8(VAR13),
.... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.v | 2,507 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR7 ,
VAR12 ,
VAR6,
VAR2 ,
VAR9 ,
VAR11 ,
VAR3 ,
VAR10
);
output VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR12 ;
input VAR6;
input VAR2 ;
input VAR9 ;
input VAR11 ;
input VAR3 ;
input VAR10 ;
VAR4 VAR8 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR12(VAR12),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9... | apache-2.0 |
mossmann/unambiguous-encapsulation | code-search/verilog/icblbc/icblbc_ram.v | 7,009 | module MODULE1 (
address,
VAR55,
VAR7,
VAR6,
VAR10);
input [10:0] address;
input VAR55;
input [7:0] VAR7;
input VAR6;
output [7:0] VAR10;
tri1 VAR55;
wire [7:0] VAR48;
wire [7:0] VAR10 = VAR48[7:0];
VAR8 VAR41 (
.VAR43 (address),
.VAR3 (VAR55),
.VAR30 (VAR7),
.VAR27 (VAR6),
.VAR22 (VAR48),
.VAR36 (1'b0),
.VAR2 (1'b0),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn.behavioral.pp.v | 3,157 | module MODULE1 (
VAR22 ,
VAR1 ,
VAR29 ,
VAR15 ,
VAR6 ,
VAR24,
VAR17,
VAR12 ,
VAR21 ,
VAR9 ,
VAR2 ,
VAR20
);
output VAR22 ;
input VAR1 ;
input VAR29 ;
input VAR15 ;
input VAR6 ;
input VAR24;
input VAR17;
input VAR12 ;
input VAR21 ;
input VAR9 ;
input VAR2 ;
input VAR20 ;
wire VAR16 ;
wire VAR5 ;
wire VAR32 ;
reg VAR19 ;... | apache-2.0 |
plindstroem/oh | elink/hdl/eclocks.v | 12,079 | module MODULE1 (
VAR32, VAR51, VAR132, VAR109, VAR71, VAR104,
VAR38, VAR21, VAR45,
reset, VAR74, VAR126, VAR36
);
parameter VAR128 = 4; else
parameter VAR128 = 8; VAR3
parameter VAR4 = 100;
parameter VAR5 = 300;
parameter VAR152 = 300;
parameter VAR125 = 200;
parameter VAR80 = 600;
parameter VAR107 = 90; parameter VAR3... | gpl-3.0 |
CeesWolfs/ceespu | src/ceespu.v | 8,647 | module MODULE1(
input VAR20,
input VAR40,
input VAR49,
input [1:0] VAR87,
input [31:0] VAR123,
output [15:0] VAR25,
output VAR12,
output VAR4,
input [31:0] VAR76,
input VAR119,
output VAR51,
output [15:0] VAR18,
output [31:0] VAR28,
output VAR62,
output [3:0] VAR82
);
wire [13:0] VAR26, VAR94, VAR83, VAR61 ,VAR104;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b.symbol.v | 1,317 | module MODULE1 (
input VAR4 ,
input VAR5 ,
input VAR6 ,
input VAR7,
output VAR8
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.behavioral.pp.v | 8,443 | module MODULE1 (
VAR54 ,
VAR85 ,
VAR9 ,
VAR36,
VAR63,
VAR26 ,
VAR28
);
output VAR54 ;
input [15:0] VAR85 ;
input [15:0] VAR9 ;
input VAR36;
input VAR63;
input VAR26 ;
input VAR28 ;
wire VAR82 ;
wire VAR69 ;
wire VAR39 ;
wire VAR59 ;
wire VAR56 ;
wire VAR45 ;
wire VAR64 ;
wire VAR80 ;
wire VAR27 ;
wire VAR61 ;
wire VAR4... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/system_acl_iface_hps.v | 16,175 | module MODULE1 #(
parameter VAR10 = 0,
parameter VAR90 = 0
) (
output wire VAR45, input wire VAR67, output wire [11:0] VAR19, output wire [20:0] VAR85, output wire [3:0] VAR93, output wire [2:0] VAR81, output wire [1:0] VAR6, output wire [1:0] VAR71, output wire [3:0] VAR4, output wire [2:0] VAR27, output wire VAR56, i... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_adcfifo/axi_adcfifo_dma.v | 8,896 | module MODULE1 (
VAR46,
VAR59,
VAR65,
VAR1,
VAR34,
VAR50,
VAR28,
VAR5,
VAR55,
VAR37,
VAR21,
VAR61);
parameter VAR6 = 512;
parameter VAR52 = 64;
parameter VAR54 = 1;
localparam VAR68 = VAR6/VAR52;
localparam VAR22 = 8;
localparam VAR49 = (VAR68 == 2) ? (VAR22 - 1) :
((VAR68 == 4) ? (VAR22 - 2) : (VAR22 - 3));
input VAR4... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cmn/block_ram/dual_port_ram_sync.v | 2,493 | module MODULE1
parameter VAR9 = 6,
parameter VAR11 = 8
)
(
input wire clk,
input wire VAR8,
input wire [VAR9-1:0] VAR10,
input wire [VAR9-1:0] VAR2,
input wire [VAR11-1:0] VAR6,
output wire [VAR11-1:0] VAR5,
output wire [VAR11-1:0] VAR3
);
reg [VAR11-1:0] VAR4 [2**VAR9-1:0];
reg [VAR9-1:0] VAR7;
reg [VAR9-1:0] VAR1;
al... | mit |
mithro/HDMI2USB | hdl/UART/RX_module.v | 3,865 | module MODULE1
parameter VAR4 = 8, VAR6 = 16 )
(
input wire clk, reset,
input wire VAR7, VAR9,
output reg VAR2,
output wire [7:0] dout
);
localparam [1:0] VAR3 = 2'b00,VAR8 = 2'b01,VAR15 = 2'b10,VAR12 = 2'b11;
reg [1:0] state, VAR5;
reg [3:0] VAR16, VAR1;
reg [2:0] VAR13, VAR10;
reg [7:0] VAR11, VAR14;
always @(posedge... | bsd-2-clause |
mda-ut/Tempest | fpga/fpga_hw/top_level/imu/imu.v | 3,383 | module MODULE1(
input VAR23,
input VAR35,
input VAR4,
inout VAR26,
output VAR19,
output [8*32-1:0] VAR7,
input VAR11,
output VAR8,
output VAR28,
output VAR30
);
wire [11:0] VAR20;
wire [11:0] VAR13;
wire [11:0] VAR24;
wire [11:0] VAR14;
wire [11:0] VAR5;
wire [11:0] VAR2;
wire [11:0] VAR32;
wire [11:0] VAR36;
VAR33 VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.symbol.v | 1,366 | module MODULE1 (
input VAR2,
input VAR4,
input VAR8,
input VAR7,
input VAR6,
output VAR3
);
supply1 VAR5;
supply0 VAR1;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbusl/rtl/bw_clk_cl_jbusl_jbus.v | 4,046 | module MODULE1(VAR11 ,VAR28 ,VAR45 ,VAR36 ,VAR40 ,
VAR31 ,VAR37 ,VAR22 ,VAR34 ,VAR3 ,VAR25 ,VAR17 );
output VAR11 ;
output VAR28 ;
output VAR45 ;
output VAR17 ;
input VAR36 ;
input VAR40 ;
input VAR31 ;
input VAR37 ;
input VAR22 ;
input VAR34 ;
input VAR3 ;
input VAR25 ;
wire [3:0] VAR20 ;
wire [2:0] VAR13 ;
wire [1:0]... | gpl-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber25/a25_core.v | 29,400 | module MODULE1
(
input VAR141,
input VAR274, input VAR223,
input VAR181,
output [31:0] VAR174,
output [15:0] VAR265,
output VAR277,
input [127:0] VAR78,
output [127:0] VAR285,
output VAR234,
output VAR158,
input VAR255,
input VAR41
);
wire [31:0] VAR305;
wire VAR330;
wire [31:0] VAR297; wire [31:0] VAR157;
wire VAR183;... | gpl-2.0 |
Canaan-Creative/MM | verilog/superkdf9/components/alink/tx_phy.v | 6,343 | module MODULE1(
input clk ,
input rst ,
input VAR38 ,
input VAR3 ,
input VAR23 ,
input [31:0] VAR8 ,
output VAR30 ,
input [31:0] VAR39 ,output VAR11 ,
output reg VAR37 ,
output reg [31:0] VAR40 ,
output reg [31:0] VAR32 ,
output reg [31:0] VAR10 ,
output reg [31:0] VAR21 ,
output [VAR12-1:0] VAR19 ,
output [VAR12-1:0] ... | unlicense |
hoglet67/CoPro6502 | src/zet/flash/bootrom.v | 1,596 | module MODULE1 (
input clk,
input rst,
input [15:0] VAR7,
output [15:0] VAR2,
input [19:1] VAR1,
input VAR6,
input VAR5,
input VAR12,
input VAR8,
input [ 1:0] VAR9,
output VAR4
);
reg [15:0] VAR10[0:8191];
wire [ 12:0] VAR3;
wire VAR11;
assign VAR3 = VAR1[13:1];
assign VAR11 = VAR12 & VAR8;
assign VAR4 = VAR11;
assign ... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/board/Read_Master/MM_to_ST_Adapter.v | 13,480 | module MODULE1 (
clk,
reset,
VAR35,
VAR7,
address,
VAR12,
VAR37,
VAR13,
VAR4,
VAR17,
VAR18,
VAR10,
VAR23,
VAR33
);
parameter VAR8 = 32; parameter VAR31 = 32;
parameter VAR16 = 32;
parameter VAR19 = 2; parameter VAR6 = 5;
parameter VAR40 = 2; parameter VAR42 = 1; parameter VAR5 = 1; parameter VAR39 = 0;
input clk;
input... | mit |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/bench/verilog/wb_master_model.v | 5,566 | module MODULE1(clk, rst, VAR3, din, dout, VAR2, VAR8, VAR1, sel, ack, VAR6, VAR7);
parameter VAR4 = 32;
parameter VAR9 = 32;
input clk, rst;
output [VAR9 -1:0] VAR3;
input [VAR4 -1:0] din;
output [VAR4 -1:0] dout;
output VAR2, VAR8;
output VAR1;
output [VAR4/8 -1:0] sel;
input ack, VAR6, VAR7;
reg [VAR9 -1:0] VAR3;
reg... | gpl-2.0 |
alr46664/lab4 | verilog_source/pipeline2.v | 2,313 | module MODULE1(
VAR23, VAR25, VAR32, VAR34, VAR35, VAR4, VAR31, VAR30, VAR5, VAR28, VAR24, VAR2, VAR12, VAR6 );
input VAR23, VAR25;
input [VAR10-1:0] VAR32;
input [VAR37-1:0] VAR34;
input [VAR22-1:0] VAR35;
input [VAR11-1:0] VAR4;
input VAR31;
output reg signed [VAR11-1:0] VAR2;
output reg [VAR10-1:0] VAR12;
output reg... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/generic/adapter_ppfifo_2_axi_stream.v | 4,627 | module MODULE1 #(
parameter VAR1 = 24,
parameter VAR13 = VAR1 / 8,
parameter VAR6 = 0
)(
input rst,
input VAR15,
output reg VAR19,
input [23:0] VAR11,
input [(VAR1 + 1) - 1:0] VAR8,
output VAR14,
input VAR18,
output [3:0] VAR16,
input VAR3,
output [VAR1 - 1:0] VAR4,
output VAR5,
output reg VAR12,
output [31:0] VAR2
);
... | mit |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkCSR_MIE.v | 5,900 | module MODULE1(VAR21,
VAR18,
VAR39,
VAR37,
VAR15,
VAR17,
VAR14,
VAR26,
VAR25,
VAR23,
VAR9,
VAR40,
VAR10);
input VAR21;
input VAR18;
input VAR39;
output [63 : 0] VAR37;
input [27 : 0] VAR15;
input [63 : 0] VAR17;
input VAR14;
output [63 : 0] VAR26;
output [63 : 0] VAR25;
input [27 : 0] VAR23;
input [63 : 0] VAR9;
input ... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T23-fsmtx/fsmtx.v | 4,807 | module MODULE1 (input wire clk, input wire VAR18, output reg VAR3 );
parameter VAR17 = VAR11;
parameter VAR1 = "VAR10";
reg [9:0] VAR14;
reg VAR7;
wire VAR9;
reg VAR5 = 0;
reg [3:0] VAR2;
wire VAR4; wire VAR12;
always @(posedge clk)
VAR7 <= VAR18;
always @(posedge clk)
if (VAR5 == 0)
VAR14 <= 10'b1111111111;
else if (V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.behavioral.pp.v | 1,149 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill_8.v | 1,848 | module MODULE2 (
VAR6,
VAR1,
VAR3 ,
VAR5
);
input VAR6;
input VAR1;
input VAR3 ;
input VAR5 ;
VAR4 VAR2 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR5 ;
VAR4 VAR2 ();
endmodule | apache-2.0 |
jefflieu/recon | hw/cmn/io/recon_io.v | 9,866 | module MODULE1 (
address,
VAR11,
clk,
VAR16,
write,
read,
VAR13,
VAR20,
irq,
VAR23 ,
VAR27 ,
VAR10 ,
VAR1
)
;
parameter VAR5 = 16;
parameter VAR19 = 8;
output [ 31: 0] VAR20;
input [ 5: 0] address;
input VAR11;
input clk;
input VAR16;
input write;
input read;
input [ 31: 0] VAR13;
output [VAR5-1:0] VAR23;
output [VAR5-... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.functional.pp.v | 2,245 | module MODULE1 (
VAR19 ,
VAR11,
VAR10,
VAR3 ,
VAR5 ,
VAR17,
VAR18,
VAR12 ,
VAR7
);
output VAR19 ;
input VAR11;
input VAR10;
input VAR3 ;
input VAR5 ;
input VAR17;
input VAR18;
input VAR12 ;
input VAR7 ;
wire VAR9 ;
wire VAR1 ;
wire VAR16 ;
wire VAR2;
and VAR8 (VAR9 , VAR3, VAR5 );
nor VAR14 (VAR1 , VAR11, VAR10 );
nor ... | apache-2.0 |
smithe0/GestureControlInterface | DE2Component_FLASH/niosII_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,556 | module MODULE1
parameter VAR10 = 8,
VAR31 = 8,
VAR37 = 0,
VAR25 = 0,
VAR35 = 1,
VAR19 = 0,
VAR3 = 1,
VAR30 = 2,
VAR40 = 2,
VAR29 = 1,
VAR16 = VAR10 / VAR31,
VAR34 = VAR22(VAR16)
)
(
input VAR2,
input VAR17,
input VAR8,
input VAR39,
output VAR27,
input VAR45,
input [VAR10 - 1 : 0] VAR14,
input [VAR35 - 1 : 0] VAR11,
inp... | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/gpio/hdl/parallella_gpio_emio.v | 4,753 | module MODULE1
(
VAR18,
VAR35, VAR12,
VAR6, VAR8
);
parameter VAR22 = 24; parameter VAR25 = 0; parameter VAR34 = 64;
inout [VAR22-1:0] VAR35;
inout [VAR22-1:0] VAR12;
output [VAR34-1:0] VAR18;
input [VAR34-1:0] VAR6;
input [VAR34-1:0] VAR8;
genvar VAR1;
generate
if( VAR25 == 1 ) begin: VAR27
VAR9
.VAR13("VAR15"),
.VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.pp.symbol.v | 1,358 | module MODULE1 (
input VAR4 ,
output VAR6 ,
output VAR7 ,
input VAR5,
input VAR2 ,
input VAR3,
input VAR8,
input VAR1
);
endmodule | apache-2.0 |
google/CFU-Playground | proj/mport/cfu.v | 1,971 | module MODULE1 (
input VAR18,
output VAR5,
input [9:0] VAR12,
input [31:0] VAR8,
input [31:0] VAR15,
output VAR14,
input VAR17,
output [31:0] VAR10,
input reset,
input clk,
output [13:0] VAR1,
output [13:0] VAR13,
output [13:0] VAR11,
output [13:0] VAR2,
input [31:0] VAR9,
input [31:0] VAR16,
input [31:0] VAR7,
input [... | apache-2.0 |
cpulabs/mist1032isa | src/core/dispatch/dispatch.v | 34,825 | module MODULE1 #(
parameter VAR205 = 0
)(
input wire VAR237,
input wire VAR305,
input wire VAR303,
input wire VAR283,
input wire VAR324,
input wire VAR272,
input wire VAR251,
input wire VAR196,
input wire VAR112,
input wire [31:0] VAR327,
input wire VAR318,
input wire VAR128,
input wire VAR185,
input wire VAR123,
input... | bsd-2-clause |
Elphel/x353 | compressor/stuffer333.v | 17,650 | module MODULE1 (clk, en, VAR51, VAR23, VAR5, VAR79, VAR1, VAR70, VAR46, VAR67, VAR44, VAR9, VAR76, VAR8, VAR53, VAR17
,VAR77, VAR28,
VAR50
);
input clk;
input en;
input VAR51; input VAR23;
input VAR5;
input [ 3:0] VAR79;
input [15:0] VAR1;
input VAR70; input [31:0] VAR46; input [19:0] VAR67;
output VAR44;
output [15:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41o/sky130_fd_sc_ls__a41o.symbol.v | 1,381 | module MODULE1 (
input VAR1,
input VAR10,
input VAR6,
input VAR9,
input VAR2,
output VAR3
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_4.functional.pp.v | 1,681 | module MODULE1( VAR10, VAR25, VAR7, VAR6, VAR18, VAR11, VAR19, VAR23 );
input VAR6, VAR7, VAR10, VAR25, VAR11, VAR19, VAR23;
output VAR18;
wire VAR16;
not VAR9( VAR16, VAR7 );
wire VAR15;
not VAR5( VAR15, VAR10 );
wire VAR14;
and VAR22( VAR14, VAR16, VAR15 );
wire VAR2;
not VAR21( VAR2, VAR25 );
wire VAR13;
and VAR24( ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2.functional.v | 1,305 | module MODULE1 (
VAR2,
VAR6,
VAR3
);
output VAR2;
input VAR6;
input VAR3;
wire VAR1;
xnor VAR4 (VAR1, VAR6, VAR3 );
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
cwilkens/fpga-hero-ii | fpga-hero-ii.srcs/sources_1/new/PS3spiControl.v | 3,537 | module MODULE1(
input clk,
input VAR13,
input VAR11,
input VAR10,
output reg [7:0] VAR16,
output reg [7:0] VAR5
);
reg [7:0] VAR8;
reg [3:0] VAR14;
reg [2:0] VAR12;
reg VAR15;
reg [2:0] VAR9;
reg [2:0] VAR3;
reg [1:0] VAR1;
always@ (posedge clk) begin
VAR9 <= {VAR9[1:0], VAR11};
VAR3 <= {VAR3[1:0], VAR10};
VAR1 <= {VAR... | mit |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/low_level_command_processor.v | 39,189 | module MODULE1(
clk, VAR24, reset, VAR81, VAR77, VAR57, VAR3, VAR73,
VAR85, VAR20,
VAR104, VAR45, VAR71, VAR88,
VAR2, VAR87, VAR31,
VAR63, VAR70, VAR109 );
input clk;
input VAR24;
input reset; input VAR81;
output reg VAR77;
input [VAR61-1:0] VAR57;
input [VAR61-1:0] VAR3; input [VAR61-1:0] VAR73;
inout VAR85;
inout VAR... | gpl-2.0 |
svenstaro/uni-projekt | verilog/fifo_bb.v | 5,100 | module MODULE1 (
VAR3,
VAR6,
VAR4,
VAR2,
VAR5,
VAR1);
input VAR3;
input [7:0] VAR6;
input VAR4;
input VAR2;
output VAR5;
output [7:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.behavioral.v | 1,513 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR3 ,
VAR10
);
output VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR10;
supply1 VAR4;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR11 ;
wire VAR12 ;
wire VAR13;
nor VAR1 (VAR12 , VAR9, VAR3 );
and VAR5 (VAR13, VAR10, VAR12 );
buf VAR7 (VAR6 , VAR13 );
endmodule | apache-2.0 |
queq/just-stuff | pov/TopMobile/LEDS/top_ASCCI.v | 1,791 | module MODULE1(
input clk,
input [76:0] string,
input VAR26,
input [7:0]VAR39,
output [15:0]VAR10,
output [6:0] VAR4,
output VAR30
);
wire [3:0]VAR7;
wire VAR3;
wire [3:0]VAR43;
wire VAR53;
wire VAR24;
wire VAR42;
wire VAR2;
wire VAR52;
wire VAR14;
wire VAR47;
wire VAR33;
wire VAR19;
wire [6:0]VAR20;
wire [10:0]VAR11;
... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_n_to_1.v | 3,423 | module MODULE1 #(parameter VAR2(VAR16 )
,parameter VAR2(VAR47 )
,parameter VAR2(VAR17 )
,parameter VAR15 = 0
,parameter VAR22 = VAR23(VAR47)
)
(input VAR20
, input VAR28
, input [VAR47-1:0][VAR16-1:0] VAR29
, input [VAR47-1:0] VAR45
, output [VAR47-1:0] VAR11
, output VAR34
, output [VAR16-1:0] VAR13
, output [VAR22-1:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.functional.v | 1,476 | module MODULE1 (
VAR5 ,
VAR3,
VAR4,
VAR7,
VAR9
);
output VAR5 ;
input VAR3;
input VAR4;
input VAR7;
input VAR9;
wire VAR10 ;
wire VAR2;
or VAR6 (VAR10 , VAR4, VAR3 );
nand VAR1 (VAR2, VAR9, VAR10, VAR7);
buf VAR8 (VAR5 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp.functional.pp.v | 1,767 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR7,
VAR11,
VAR10 ,
VAR3
);
output VAR9 ;
input VAR8 ;
input VAR7;
input VAR11;
input VAR10 ;
input VAR3 ;
wire VAR6 ;
wire VAR4;
buf VAR2 (VAR6 , VAR8 );
VAR1 VAR12 (VAR4, VAR6, VAR7, VAR11);
buf VAR5 (VAR9 , VAR4 );
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/vga/dual_port_16x6.v | 2,743 | module MODULE1
(
input VAR4,
input VAR10, input VAR9,
input clk,
input VAR2,
input [3:0] VAR7, input [3:0] VAR3, input [5:0] din,
output reg [5:0] VAR1, output reg [5:0] VAR6 );
reg [5:0] VAR5[15:0];
integer VAR8;
always @(posedge VAR9 or negedge VAR4)
if (!VAR4) begin
for (VAR8 = 0; VAR8 < 16; VAR8 = VAR8 + 1) VAR5[VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.blackbox.v | 1,291 | module MODULE1 (
VAR5 ,
VAR4,
VAR3,
VAR6
);
output VAR5 ;
input VAR4;
input VAR3;
input VAR6 ;
supply1 VAR7;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b_1.v | 2,229 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR3 ,
VAR10 ,
VAR1,
VAR7,
VAR6 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR1;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR9 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
tommythorn/yari | shared/rtl/altera/cyclone/dpram.v | 4,431 | module MODULE1 (VAR18,
VAR24, VAR5, VAR63, VAR69, VAR77,
VAR7, VAR76, VAR1, VAR70, VAR4);
parameter VAR36 = 32;
parameter VAR8 = 7;
parameter VAR53 = "VAR60";
input [VAR8-1:0] VAR24;
input [VAR8-1:0] VAR7;
input [VAR36/8-1:0] VAR5;
input [VAR36/8-1:0] VAR76;
input VAR18;
input [VAR36-1:0] VAR63;
input [VAR36-1:0] VAR1;... | gpl-2.0 |
gtaylormb/opl3_fpga | fpga/modules/opl3_fpga_1.0/hdl/opl3_fpga_v1_0_S_AXI.v | 63,642 | module MODULE1 #
(
parameter integer VAR94 = 32,
parameter integer VAR144 = 9
)
(
input wire VAR95,
input wire VAR24,
input wire [VAR144-1 : 0] VAR138,
input wire [2 : 0] VAR135,
input wire VAR120,
output wire VAR54,
input wire [VAR94-1 : 0] VAR1,
input wire [(VAR94/8)-1 : 0] VAR93,
input wire VAR36,
output wire VAR158... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.symbol.v | 1,352 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR3,
output VAR4
);
supply1 VAR5;
supply0 VAR6;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | matchfilter_bb.v | 2,137 | module MODULE1 (
clk,
VAR4,
VAR5,
VAR3,
VAR1,
VAR7,
VAR9,
VAR6,
VAR2,
VAR8);
input clk;
input VAR4;
input [14:0] VAR5;
input VAR3;
input VAR1;
input [1:0] VAR7;
output [29:0] VAR9;
output VAR6;
output VAR2;
output [1:0] VAR8;
endmodule | mit |
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