repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
kmod/bitcoin_mining | fpga/fpga.v | 4,735 | module MODULE1(
input wire VAR7,
input wire [7:0] VAR26,
input wire [4:0] VAR28,
output wire [7:0] VAR34,
output wire [7:0] VAR23,
output wire [3:0] VAR41,
output wire VAR32,
input wire VAR4
);
wire clk; VAR8 VAR8(.VAR42(VAR7), .VAR43(clk));
assign VAR34 = VAR26;
reg [4:0] VAR10, VAR37;
always @(posedge clk) begin
{VAR... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/spree/reg_file_pipe.v | 3,967 | module MODULE1(clk,VAR10,
VAR5, VAR14, VAR8,
VAR12, VAR11, VAR9,
VAR13, VAR1, VAR4);
parameter VAR6=32;
parameter VAR3=32;
parameter VAR7=5;
input clk;
input VAR10;
input VAR8;
input VAR9;
input [VAR7-1:0] VAR5,VAR12,VAR13;
output [VAR6-1:0] VAR14, VAR11;
input [VAR6-1:0] VAR1;
input VAR4;
reg [VAR6-1:0] VAR14, VAR11;
... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/xilinx_internal_jtag/rtl/verilog/xilinx_internal_jtag.v | 17,631 | module MODULE1 (
VAR7,
VAR16,
VAR17,
VAR47,
VAR31,
VAR43,
VAR45,
VAR28,
VAR29,
VAR30
);
parameter VAR24 = 1;
input VAR16;
output VAR7;
output VAR17;
output VAR47;
output VAR31;
output VAR43;
output VAR45;
output VAR28;
output VAR29;
output VAR30;
wire VAR16;
wire VAR7;
wire VAR12;
wire VAR17;
wire VAR47;
wire VAR31;
wi... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_uartrx.v | 11,082 | module MODULE1(
input VAR52,
input reset,
input VAR63,
input VAR15,
output VAR29,
output [7:0] VAR56,
input [15:0] VAR35
);
reg [1:0] VAR100;
reg [31:0] VAR79;
wire VAR83;
wire VAR25;
reg [11:0] VAR6;
reg [31:0] VAR99;
wire VAR40;
wire VAR96;
wire VAR57;
wire pulse;
wire [12:0] VAR12;
wire [11:0] VAR24;
wire [11:0] VAR... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_7/synth/bd_350b_slot_2_aw_0.v | 4,561 | module MODULE1 (
VAR21,
VAR19,
dout
);
input wire [0 : 0] VAR21;
input wire [0 : 0] VAR19;
output wire [1 : 0] dout;
VAR38 #(
.VAR3(1),
.VAR11(1),
.VAR8(1),
.VAR18(1),
.VAR9(1),
.VAR20(1),
.VAR4(1),
.VAR48(1),
.VAR47(1),
.VAR37(1),
.VAR10(1),
.VAR28(1),
.VAR23(1),
.VAR13(1),
.VAR64(1),
.VAR65(1),
.VAR6(1),
.VAR1(1),
.V... | mit |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_wiz_v3_3_exdes.v | 5,491 | module MODULE1
parameter VAR10 = 100
)
( input VAR5,
input VAR21,
output [2:1] VAR15,
input VAR17,
output VAR11
);
localparam VAR1 = 16;
localparam VAR18 = 2;
genvar VAR19;
wire VAR16 = !VAR11 || VAR17 || VAR21;
reg [VAR18:1] VAR8;
reg [VAR18:1] VAR20;
reg [VAR18:1] VAR7;
reg [VAR18:1] VAR12;
wire [VAR18:1] VAR6;
wire ... | gpl-2.0 |
DreamIP/GPStudio | support/process/gradient/hdl/gradient.v | 11,458 | module MODULE1(
VAR52,
VAR61,
VAR33,
VAR5,
VAR2,
VAR23,
VAR25,
VAR57,
VAR40,
VAR27,
VAR58,
VAR26,
VAR55,
VAR47,
VAR4,
VAR53
);
parameter VAR37 = 8;
parameter VAR7 = 16;
parameter VAR12 = 16;
parameter VAR59 = 50000000;
parameter VAR51 = 9;
parameter VAR50 = 8;
parameter VAR35 = 32'd41;
parameter VAR22 = 32'd50;
localpa... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_8.behavioral.v | 1,093 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR1 VAR4(.VAR3(VAR3),.VAR5(VAR5));
VAR1 VAR2(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.symbol.v | 1,570 | module MODULE1 (
input VAR2 ,
output VAR12 ,
output VAR11 ,
input VAR7,
input VAR8 ,
input VAR1 ,
input VAR9 ,
input VAR6
);
supply1 VAR5;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_dpram.v | 5,511 | module MODULE1
(
VAR13, VAR4, VAR10, VAR12,
VAR9, VAR14, VAR11, VAR5, VAR3
);
parameter VAR6 = 5;
parameter VAR7 = 32;
input VAR13; input VAR4; input [VAR6-1:0] VAR10; output [VAR7-1:0] VAR12; input VAR9; input VAR14; input VAR11; input [VAR6-1:0] VAR5; input [VAR7-1:0] VAR3;
reg [VAR7-1:0] VAR1 [(1<<VAR6)-1:0] ; reg [... | mit |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_pcie/source/PCIeGen2x8If128_axi_basic_top.v | 11,063 | module MODULE1 #(
parameter VAR4 = 128, parameter VAR45 = "VAR50", parameter VAR26 = "VAR10", parameter VAR6 = "VAR10", parameter VAR29 = 1,
parameter VAR30 = (VAR4 == 128) ? 2 : 1, parameter VAR38 = VAR4 / 8 ) (
input [VAR4-1:0] VAR31, input VAR46, output VAR21, input [VAR38-1:0] VAR34, input VAR24, input [3:0] VAR12,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.symbol.v | 1,403 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR6,
input VAR8
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
rakeshkadamati/MIPS-32-Bit-Verilog | gates.v | 2,361 | module MODULE1(VAR8,VAR12,out);
input [31:0] VAR8;
input [31:0] VAR12;
output [31:0] out;
and VAR37(out[0],VAR8[0],VAR12[0]);
and VAR22(out[1],VAR8[1],VAR12[1]);
and VAR29(out[2],VAR8[2],VAR12[2]);
and VAR26(out[3],VAR8[3],VAR12[3]);
and VAR20(out[4],VAR8[4],VAR12[4]);
and VAR18(out[5],VAR8[5],VAR12[5]);
and VAR1(out[6... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv.behavioral.pp.v | 1,748 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR6,
VAR10,
VAR7 ,
VAR11
);
output VAR12 ;
input VAR3 ;
input VAR6;
input VAR10;
input VAR7 ;
input VAR11 ;
wire VAR1 ;
wire VAR4;
not VAR2 (VAR1 , VAR3 );
VAR9 VAR5 (VAR4, VAR1, VAR6, VAR10);
buf VAR8 (VAR12 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf.behavioral.pp.v | 1,670 | module MODULE1 (
VAR2,
VAR8,
VAR3 ,
VAR6
);
input VAR2;
input VAR8;
output VAR3 ;
input VAR6 ;
wire VAR7 ;
wire VAR1;
buf VAR5 (VAR7 , VAR6 );
VAR9 VAR4 (VAR1, VAR7, VAR2, VAR8);
buf VAR10 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.pp.symbol.v | 1,355 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR2 ,
input VAR6,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/rtl/verilog/dual_clock_fifo.v | 3,744 | module MODULE1 #(
parameter VAR13 = 3,
parameter VAR2 = 32
)
(
input wire VAR16,
input wire VAR4,
input wire VAR3,
input wire [VAR2-1:0] VAR19,
input wire VAR9,
input wire VAR18,
input wire VAR10,
output reg [VAR2-1:0] VAR7,
output reg VAR15,
output reg VAR12
);
reg [VAR13-1:0] VAR21;
reg [VAR13-1:0] VAR1;
reg [VAR13-1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o_1.v | 2,469 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR7 ,
VAR11 ,
VAR12 ,
VAR5,
VAR10,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR7 ;
input VAR11 ;
input VAR12 ;
input VAR5;
input VAR10;
input VAR1 ;
input VAR2 ;
VAR3 VAR9 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp.pp.symbol.v | 1,377 | module MODULE1 (
input VAR7 ,
output VAR4 ,
output VAR1 ,
input VAR3,
input VAR5 ,
input VAR6 ,
input VAR2
);
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | db/PLL_altpll.v | 3,649 | module MODULE1
(
clk,
VAR11,
VAR7) ;
output [4:0] clk;
input [1:0] VAR11;
output VAR7;
tri0 [1:0] VAR11;
wire [4:0] VAR2;
wire VAR12;
wire VAR9;
VAR14 VAR32
(
.VAR18(),
.clk(VAR2),
.VAR4(),
.VAR27(VAR12),
.VAR24(VAR12),
.VAR11(VAR11),
.VAR7(VAR9),
.VAR26(),
.VAR10(),
.VAR33(),
.VAR31(),
.VAR40()
,
.VAR13(1'b0),
.VAR44(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fahcon/sky130_fd_sc_ls__fahcon.blackbox.v | 1,369 | module MODULE1 (
VAR5,
VAR9 ,
VAR4 ,
VAR1 ,
VAR3
);
output VAR5;
output VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
supply1 VAR7;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.functional.pp.v | 1,819 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR9 ,
VAR6 ,
VAR12,
VAR10,
VAR7 ,
VAR5
);
output VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR12;
input VAR10;
input VAR7 ;
input VAR5 ;
wire VAR13 ;
wire VAR4;
nand VAR1 (VAR13 , VAR9, VAR2, VAR6 );
VAR11 VAR3 (VAR4, VAR13, VAR12, VAR10);
buf VAR14 (VAR8 , VAR4 );
endmodule | apache-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/Clk_ctrl.v | 5,246 | module MODULE1(
VAR15 ,
VAR10 ,
VAR23 ,
VAR6 ,
VAR8 ,
VAR18 ,
VAR12 ,
VAR22 ,
VAR3 ,
VAR5
);
input VAR15 ;
input VAR10 ;
input [2:0] VAR23 ;
output VAR6 ;input VAR8 ;
input VAR18 ; output VAR12 ;
output VAR22 ;
output VAR3 ;
output VAR5 ;
wire VAR24 ;
wire VAR19 ;
assign VAR6 =VAR10 ;
assign VAR22 =VAR8 ;
VAR20 VAR14(
... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_infrastructure.v | 18,349 | module MODULE1 #
(
parameter VAR13 = "VAR27", parameter VAR22 = 100, parameter VAR41 = 3000, parameter VAR16 = 2, parameter VAR17 = "VAR8",
parameter VAR5 = 4, parameter VAR24 = 1, parameter VAR42 = 45.0, parameter VAR32 = 16, parameter VAR21 = 4, parameter VAR3 = 64, parameter VAR2 = 16, parameter VAR33 = 1
)
(
input ... | mit |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_exp2lin.v | 1,231 | module MODULE1(
output reg signed [15:0] VAR2,
input signed [9:0] VAR1,
input [2:0] VAR3
);
always @(*) begin
case( VAR3 )
3'd7: VAR2 = { VAR1, 6'b0 };
3'd6: VAR2 = { {1{VAR1[9]}}, VAR1, 5'b0 };
3'd5: VAR2 = { {2{VAR1[9]}}, VAR1, 4'b0 };
3'd4: VAR2 = { {3{VAR1[9]}}, VAR1, 3'b0 };
3'd3: VAR2 = { {4{VAR1[9]}}, VAR1, 2'b0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a.pp.symbol.v | 1,390 | module MODULE1 (
input VAR8 ,
input VAR3 ,
input VAR10 ,
input VAR4 ,
input VAR7 ,
output VAR6 ,
input VAR1 ,
input VAR2,
input VAR5,
input VAR9
);
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_wdata_router.v | 6,787 | module MODULE1 #
(
parameter VAR5 = "none", parameter integer VAR11 = 1, parameter integer VAR29 = 1, parameter integer VAR31 = 1, parameter integer VAR9 = 0 )
(
input wire VAR18,
input wire VAR21,
input wire [VAR11-1:0] VAR7,
input wire VAR20,
input wire VAR6,
output wire VAR24,
output wire [VAR11-1:0] VAR16, output w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/conb/sky130_fd_sc_lp__conb.symbol.v | 1,270 | module MODULE1 (
output VAR4,
output VAR5
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.functional.pp.v | 1,386 | module MODULE1( VAR12, VAR11, VAR13, VAR17, VAR7, VAR10 );
input VAR11, VAR12, VAR17;
inout VAR7, VAR10;
output VAR13;
wire VAR2;
not VAR4( VAR2, VAR11 );
wire VAR16;
not VAR1( VAR16, VAR17 );
wire VAR9;
and VAR5( VAR9, VAR2, VAR16 );
wire VAR8;
not VAR6( VAR8, VAR12 );
wire VAR14;
and VAR3( VAR14, VAR8, VAR16 );
or VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand3/sky130_fd_sc_hvl__nand3_1.v | 2,183 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR4 ,
VAR6 ,
VAR5,
VAR1,
VAR10 ,
VAR2
);
output VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR5;
input VAR1;
input VAR10 ;
input VAR2 ;
VAR7 VAR3 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
jcrono/sd-host | src/dat/capa_fisica.v | 13,698 | module MODULE1(input logic VAR26,
input logic VAR32,
input logic [15:0] timeout ,
input logic VAR1,
input logic VAR9,
input logic reset,
input logic VAR6, input logic VAR20, input logic [31:0] VAR18,
input logic VAR25, output logic VAR27, output logic VAR2, output logic VAR24,
output logic VAR29,
output logic VAR22, ou... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_aon_wrapper.v | 15,158 | module MODULE1(
output VAR150,
output VAR39,
output VAR18,
input VAR27,
input VAR12,
output [32-1:0] VAR19,
output VAR134,
output VAR91,
output VAR123,
output VAR32,
output VAR165,
input VAR37,
input [2:0] VAR84,
input [2:0] VAR50,
input [2:0] VAR178,
input [4:0] VAR54,
input [28:0] VAR153,
input [3:0] VAR4,
input [31:... | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v | 1,454 | module MODULE1(VAR1, VAR7, VAR4, VAR5, VAR3, VAR6, VAR9, VAR8, VAR2)
;
input VAR1;
input VAR7;
input [0:0]VAR4;
input [11:0]VAR5;
input [7:0]VAR3;
input VAR6;
input VAR9;
input [8:0]VAR8;
output [63:0]VAR2;
endmodule | gpl-3.0 |
rkrajnc/minimig-de1 | rtl/mor1kx/mor1kx_wrapper.v | 3,274 | module MODULE1 #(
parameter VAR100 = 24
)(
input wire clk,
input wire rst,
output wire VAR85,
output wire VAR59,
output wire [ 4-1:0] VAR88,
output wire [ VAR100-1:0] VAR14,
output wire [ 32-1:0] VAR68,
input wire [ 32-1:0] VAR80,
input wire VAR24,
output wire VAR57,
output wire VAR56,
output wire [ 4-1:0] VAR3,
output... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_clock_pair_generator.v | 4,047 | module MODULE1
(
VAR4,
VAR26,
VAR12) ;
input [0:0] VAR4;
output [0:0] VAR26;
output [0:0] VAR12;
wire [0:0] VAR7;
wire [0:0] VAR16;
wire [0:0] VAR34;
wire [0:0] VAR24;
wire [0:0] VAR28;
wire [0:0] VAR22;
wire [0:0] VAR33;
wire [0:0] VAR15;
wire [0:0] VAR8;
wire [0:0] VAR6;
VAR2 VAR35
(
.VAR9(VAR22),
.VAR3(VAR7[0:0]),
.... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_ram.v | 4,275 | module MODULE1
(
VAR9,
VAR12,
reset,
VAR3,
VAR5,
VAR4,
VAR1,
VAR11,
VAR14,
VAR7
);
parameter VAR6 = 1; parameter VAR10 = 1;
input VAR9; input VAR12; input reset;
input VAR3; input [VAR10-1:0] VAR5; input VAR4; input [VAR10-1:0] VAR1;input [VAR6-1:0] VAR11; input VAR14;
output [VAR6-1:0] VAR7; wire [VAR6-1:0] VAR7;
reg ... | lgpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_d5m.v | 8,020 | module MODULE1 (
VAR1,
VAR9,
VAR10
);
parameter VAR4 = 16'd2591;
parameter VAR8 = 16'd1943;
parameter VAR6 = 16'h0000;
parameter VAR7 = 16'h0000;
input [ 4: 0] VAR1;
input [15: 0] VAR9;
output [35: 0] VAR10;
reg [31: 0] VAR3;
assign VAR10 = {VAR3[31:24], 1'b0,
VAR3[23:16], 1'b0,
VAR3[15: 8], 1'b0,
VAR3[ 7: 0], 1'b0};
a... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S9_altera_bb.v | 6,213 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1,
VAR5,
VAR4);
input [10:0] address;
input VAR2;
input [7:0] VAR3;
input VAR1;
input VAR5;
output [7:0] VAR4;
tri1 VAR2;
tri1 VAR1;
endmodule | mit |
lvd2/ngs | fpga/current/dma/dma_sequencer.v | 6,317 | module MODULE1(
input wire clk,
input wire VAR43,
input wire VAR54,
input wire VAR40,
input wire VAR36,
input wire VAR27,
input wire [21:0] VAR51,
input wire [21:0] VAR53,
input wire [21:0] VAR5,
input wire [21:0] VAR14,
input wire VAR31,
input wire VAR35,
input wire VAR52,
input wire VAR49,
input wire [7:0] VAR21,
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.behavioral.pp.v | 1,772 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR8,
VAR2,
VAR1 ,
VAR10
);
output VAR11 ;
input VAR3 ;
input VAR8;
input VAR2;
input VAR1 ;
input VAR10 ;
wire VAR12 ;
wire VAR9;
buf VAR7 (VAR12 , VAR3 );
VAR4 VAR6 (VAR9, VAR12, VAR8, VAR2);
buf VAR5 (VAR11 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.blackbox.v | 1,342 | module MODULE1 (
VAR1 ,
VAR4,
VAR5,
VAR2 ,
VAR6
);
output VAR1 ;
output VAR4;
input VAR5;
input VAR2 ;
input VAR6 ;
supply1 VAR3;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.pp.blackbox.v | 1,320 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR5 ,
VAR2,
VAR6,
VAR4 ,
VAR7
);
output VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR5 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
Marcoslz22/Tercer_Proyecto | Contador_AD_Dia.v | 1,242 | module MODULE1(
input rst,
input [7:0]VAR6,
input [1:0] en,
input [7:0] VAR2,
input VAR5,
input clk,
output reg [(VAR3-1):0] VAR4
);
parameter VAR3 = 7;
parameter VAR1 = 99;
always @(posedge clk)
if (rst)
VAR4 <= 1;
else if (en == 2'd2 && VAR6 == 8'h7D)
begin
if (VAR2 == 8'h73 && VAR5)
begin
if (VAR4 == VAR1)
VAR4 <= 1... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_090.v | 1,468 | module MODULE2 (
VAR1,
VAR12
);
input [31:0] VAR1;
output [31:0]
VAR12;
wire [31:0]
VAR3,
VAR9,
VAR5,
VAR11,
VAR13,
VAR7,
VAR4,
VAR6;
assign VAR3 = VAR1;
assign VAR11 = VAR3 << 4;
assign VAR7 = VAR13 << 5;
assign VAR4 = VAR13 + VAR7;
assign VAR6 = VAR4 << 1;
assign VAR9 = VAR3 << 6;
assign VAR5 = VAR3 + VAR9;
assign VA... | mit |
alexforencich/verilog-cam | rtl/priority_encoder.v | 3,205 | module MODULE1 #
(
parameter VAR5 = 4,
parameter VAR4 = "VAR7"
)
(
input wire [VAR5-1:0] VAR8,
output wire VAR6,
output wire [VAR2(VAR5)-1:0] VAR14,
output wire [VAR5-1:0] VAR13
);
parameter VAR15 = 2**VAR2(VAR5);
parameter VAR16 = VAR15/2;
generate
if (VAR5 == 1) begin
assign VAR6 = VAR8;
assign VAR14 = 0;
end else if... | mit |
Digilent/vivado-library | ip/Pmods/PmodJSTK_v1_0/src/PmodJSTK.v | 13,318 | module MODULE1
(VAR99,
VAR2,
VAR167,
VAR49,
VAR183,
VAR198,
VAR123,
VAR60,
VAR180,
VAR174,
VAR81,
VAR86,
VAR66,
VAR119,
VAR54,
VAR67,
VAR98,
VAR79,
VAR17,
VAR173,
VAR152,
VAR109,
VAR155,
VAR10,
VAR27,
VAR13,
VAR206,
VAR8,
VAR51,
VAR92,
VAR128,
VAR184,
VAR15,
VAR5,
VAR196,
VAR62,
VAR121,
VAR122,
VAR83,
VAR113,
VAR84,
VA... | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/ISP1362_IF.v | 1,398 | module MODULE1( VAR3,
VAR18,
VAR1,
VAR12,
VAR20,
VAR9,
VAR11,
VAR7,
VAR13,
VAR17,
VAR16,
VAR4,
VAR19,
VAR14,
VAR2,
VAR5,
VAR8,
VAR6 );
input [15:0] VAR3;
input [1:0] VAR1;
input VAR12;
input VAR20;
input VAR9;
input VAR11;
input VAR7;
output [15:0] VAR18;
output VAR13;
output VAR17;
inout [15:0] VAR16;
output [1:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21o/sky130_fd_sc_hvl__a21o_1.v | 2,256 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR5 ,
VAR9 ,
VAR8,
VAR3,
VAR4 ,
VAR7
);
output VAR10 ;
input VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR8;
input VAR3;
input VAR4 ;
input VAR7 ;
VAR6 VAR2 (
.VAR10(VAR10),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/rx_control.v | 6,083 | module MODULE1
(input clk, input rst,
input VAR66, input [7:0] VAR52, input [31:0] VAR27,
input [31:0] VAR8,
output VAR3,
output [31:0] VAR61,
output [3:0] VAR42,
input VAR59,
output VAR37,
input [31:0] VAR21,
output VAR40,
input VAR71,
output [15:0] VAR56,
output VAR67,
output VAR43,
output [31:0] VAR35
);
wire [31:0]... | gpl-2.0 |
eda-globetrotter/MarcheProcessor | processor/prog_counter.v | 1,414 | module MODULE1 (VAR2,VAR1,rst,clk);
output [0:31] VAR2;
input [0:31] VAR1;
input clk;
input rst;
reg [0:31] VAR2;
always @(posedge clk)
begin
if(rst)
begin
VAR2<=32'd0;
end
else
begin
VAR2<=VAR1+32'd4;
end
end
endmodule | mit |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_control.v | 5,180 | module MODULE1
VAR4 = 1,
VAR33 = 1,
VAR9 = 15)
(
input wire rst,
input wire clk,
input wire VAR34,
input wire VAR15,
input wire [VAR33-1:0] VAR27,
input wire [VAR9-1:0] VAR18,
input wire VAR14,
input wire VAR26, input wire VAR12,
output wire enable,
output wire VAR16,
output wire VAR8,
output wire VAR28,
output wire [1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/isobufsrc/sky130_fd_sc_hdll__isobufsrc.symbol.v | 1,387 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR5
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_1.behavioral.v | 2,848 | module MODULE1( VAR16, VAR8, VAR21, VAR26 );
input VAR21, VAR16, VAR8;
output VAR26;
reg VAR24;
VAR2 VAR25(.VAR16(VAR16),.VAR8(VAR8),.VAR21(VAR21),.VAR26(VAR26),.VAR24(VAR24));
VAR2 VAR17(.VAR16(VAR16),.VAR8(VAR8),.VAR21(VAR21),.VAR26(VAR26),.VAR24(VAR24));
buf VAR12(VAR19,VAR8);
not VAR20(VAR4,VAR21);
and VAR13(VAR5,V... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/ssio_sdr_in_diff.v | 2,943 | module MODULE1 #
(
parameter VAR12 = "VAR18",
parameter VAR24 = "VAR5",
parameter VAR14 = 1
)
(
input wire VAR29,
input wire VAR26,
input wire [VAR14-1:0] VAR30,
input wire [VAR14-1:0] VAR21,
output wire VAR11,
output wire [VAR14-1:0] VAR16
);
wire VAR31;
wire [VAR14-1:0] VAR1;
genvar VAR25;
generate
if (VAR12 == "VAR2... | mit |
sittner/lcnc-mdsio | vhdl/source/can/can_fifo.v | 19,248 | module MODULE1
(
clk,
rst,
wr,
VAR84,
addr,
VAR25,
VAR11,
VAR96,
VAR31,
VAR19,
VAR81,
VAR5,
VAR78
,
VAR76,
VAR6,
VAR90
);
parameter VAR70 = 1;
input clk;
input rst;
input wr;
input [7:0] VAR84;
input [5:0] addr;
input VAR96;
input VAR31;
input VAR19;
input VAR11;
output [7:0] VAR25;
output VAR81;
output VAR5;
output [6... | gpl-3.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/verilog/HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp.v | 2,402 | module MODULE1
VAR30 = 0,
VAR32 = 5,
VAR10 = 32,
VAR22 = 32,
VAR19 = 32
)(
input wire clk,
input wire reset,
input wire VAR31,
input wire [VAR10-1:0] VAR16,
input wire [VAR22-1:0] VAR15,
input wire [1:0] VAR7,
output wire [VAR19-1:0] dout
);
wire VAR2;
wire VAR21;
wire VAR18;
wire [31:0] VAR14;
wire VAR9;
wire [31:0] V... | mit |
tloinuy/opencpi-opencv | opencpi/hdl/prims/ocpi/arSRLFIFOD.v | 2,907 | module MODULE1 (VAR12,VAR5,VAR10,VAR14,VAR1,VAR8,VAR17,VAR6,VAR16);
parameter VAR3 = 128;
parameter VAR9 = 5;
parameter VAR15 = 2**VAR9;
input VAR12;
input VAR5;
input VAR16;
input VAR10;
input VAR14;
output VAR1;
output VAR8;
input[VAR3-1:0] VAR17;
output[VAR3-1:0] VAR6;
reg[VAR9-1:0] pos; reg[VAR3-1:0] VAR4[VAR15-1:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn.behavioral.pp.v | 2,608 | module MODULE1 (
VAR16 ,
VAR7 ,
VAR5,
VAR25 ,
VAR24 ,
VAR17 ,
VAR1 ,
VAR22 ,
VAR14
);
output VAR16 ;
output VAR7 ;
input VAR5;
input VAR25 ;
input VAR24 ;
input VAR17 ;
input VAR1 ;
input VAR22 ;
input VAR14 ;
wire VAR2 ;
wire VAR9 ;
reg VAR13 ;
wire VAR18 ;
wire VAR8 ;
wire VAR3 ;
wire VAR6;
wire VAR12 ;
wire VAR15 ;
... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/dma_pcie_bridge/dma_pcie_bridge.v | 4,798 | module MODULE1
(
clk,
reset,
VAR27,
VAR36,
VAR33,
VAR29,
VAR39,
VAR28,
VAR10,
VAR12,
VAR38,
VAR32,
VAR19,
VAR16,
VAR31,
VAR40,
VAR37,
VAR9,
VAR35,
VAR42
);
parameter VAR22 = 256;
parameter VAR4 = 64;
parameter VAR34 = 6;
parameter VAR8 = 10;
parameter VAR21 = 30; parameter VAR15 = 0;
localparam VAR5 = VAR22 / 8;
localp... | mit |
ipcoregarfield/GEM_Project | Example_CORDIC/Verilog Design/Verilog Codes/CORDIC.v | 5,673 | module MODULE1
(
VAR37,
VAR2,
VAR5,
VAR8
);
localparam VAR7 = (VAR23 == 3) ? (7 + VAR25) : ( (VAR23 == 2) ? (2 + VAR25) :(VAR25));
localparam VAR10 = 2 * VAR7;
localparam VAR9 = 2 * VAR7;
localparam VAR17 = 15'd16384;
input VAR37;
input VAR2;
input signed[(VAR10 - 1) : 0] VAR5;
output signed[(VAR9 - 1) : 0] VAR8;
wire[... | gpl-3.0 |
himingway/PIC16C5x | src/wRegWriteControl.v | 1,664 | module MODULE1 (
input clk , input VAR1 , input [ 7:0] VAR8 , input [VAR6-1:0] VAR2, input [ VAR3-1:0] VAR4 , input [ VAR3-1:0] VAR7 , output [ VAR3-1:0] VAR9 );
reg [VAR3-1:0] VAR5;
assign VAR9 = VAR5;
always @(posedge clk) begin
if (!VAR1) begin
VAR5 <= VAR3'b0;
end
else begin
case (VAR2)
end
end
end
end
VAR5 <= 0;
e... | mit |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/axi_elink_if.v | 10,815 | module MODULE1 (
VAR25, VAR23, VAR4, VAR15,
VAR74, VAR43, VAR70,
VAR76, VAR28, VAR66,
VAR12, VAR39, VAR84,
VAR90, VAR64, VAR40,
VAR78, VAR42, VAR17,
VAR32, VAR33, VAR52,
VAR53, VAR56, VAR92,
VAR81, VAR14, VAR36,
VAR91, VAR60, reset, VAR7, VAR65,
VAR71, VAR22, VAR68,
VAR79, VAR72, VAR47,
VAR1, VAR97, VAR62,
VAR24, VAR46... | gpl-3.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v | 31,504 | module MODULE1 #
(
parameter VAR170 = 100,
parameter VAR155 = "VAR180",
parameter VAR49 = "1T",
parameter VAR77 = 3,
parameter VAR138 = 2,
parameter VAR20 = "8",
parameter VAR66 = 12,
parameter VAR54 = 4,
parameter VAR38 = 5,
parameter VAR40 = 5,
parameter VAR181 = 8,
parameter VAR177 = "VAR165",
parameter VAR98 = "VAR... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/clock_control/synthesis/submodules/clock_control_altclkctrl_0.v | 3,982 | module MODULE1
(
VAR4,
VAR1,
VAR16) ;
input VAR4;
input [3:0] VAR1;
output VAR16;
tri1 VAR4;
tri0 [3:0] VAR1;
wire VAR15;
wire [1:0] VAR12;
VAR5 VAR9
(
.VAR4(VAR4),
.VAR3(),
.VAR1(VAR1[0]),
.VAR16(VAR15));
VAR9.VAR8 = "VAR11",
VAR9.VAR18 = "VAR14 edge",
VAR9.VAR13 = "VAR5";
assign
VAR12 = {2{1'b0}},
VAR16 = VAR15;
end... | gpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_base/upd77c25_datrom.v | 9,221 | module MODULE1 (
VAR60,
VAR22,
VAR14,
VAR3,
VAR39,
VAR26);
input VAR60;
input [15:0] VAR22;
input [10:0] VAR14;
input [10:0] VAR3;
input VAR39;
output [15:0] VAR26;
tri1 VAR60;
tri0 VAR39;
wire [15:0] VAR18;
wire [15:0] VAR26 = VAR18[15:0];
VAR29 VAR25 (
.VAR50 (VAR3),
.VAR5 (VAR14),
.VAR7 (VAR60),
.VAR59 (VAR22),
.VAR... | gpl-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/cpu_0_jtag_debug_module_tck.v | 8,074 | module MODULE1 (
VAR30,
VAR11,
VAR25,
VAR3,
VAR23,
VAR39,
VAR27,
VAR34,
VAR14,
VAR9,
VAR29,
VAR16,
VAR37,
VAR12,
VAR20,
VAR8,
VAR28,
VAR32,
VAR35,
VAR1,
VAR7,
VAR33,
VAR4,
VAR6,
VAR5,
VAR17,
VAR26,
VAR2,
VAR24,
VAR31,
VAR19
)
;
output [ 1: 0] VAR26;
output VAR2;
output [ 37: 0] VAR24;
output VAR31;
output VAR19;
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp.functional.v | 1,880 | module MODULE1 (
VAR1 ,
VAR10,
VAR11,
VAR4 ,
VAR13,
VAR12
);
output VAR1 ;
output VAR10;
input VAR11;
input VAR4 ;
input VAR13;
input VAR12;
wire VAR8 ;
wire VAR9;
VAR3 VAR15 (VAR9, VAR4, VAR13, VAR12 );
VAR6 VAR5 VAR14 (VAR8 , VAR9, VAR11 );
buf VAR2 (VAR1 , VAR8 );
not VAR7 (VAR10 , VAR8 );
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_auto_us_1/system_auto_us_1_stub.v | 3,102 | module MODULE1(VAR24, VAR30, VAR13,
VAR10, VAR18, VAR6, VAR27, VAR32, VAR4,
VAR26, VAR22, VAR7, VAR29, VAR12, VAR19,
VAR9, VAR16, VAR11, VAR25, VAR23, VAR1,
VAR33, VAR31, VAR34, VAR3, VAR5, VAR21,
VAR15, VAR8, VAR17, VAR20, VAR14, VAR2,
VAR28)
;
input VAR24;
input VAR30;
input [31:0]VAR13;
input [7:0]VAR10;
input [2:0]... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_errctl.v | 53,654 | module MODULE1(
VAR405, VAR322, VAR400,
VAR32, VAR397,
VAR106, VAR355, VAR100,
VAR284, VAR323, VAR294,
VAR230, VAR40, VAR296,
VAR1, VAR228, VAR370,
VAR282, VAR345, VAR232,
VAR283, VAR86,
VAR85, VAR247,
VAR183, VAR43,
VAR209, VAR261,
VAR255, VAR371,
VAR269, VAR394,
VAR72, VAR236,
VAR363, VAR92,
VAR111, VAR211,
VAR59, VA... | gpl-2.0 |
tdene/synth_opt_adders | src/pptrees/mappings/behavioral_map.v | 3,182 | module MODULE14
(
VAR6, VAR9
);
output VAR6;
input VAR9;
assign VAR6 = ~VAR9;
endmodule
module MODULE5
(
VAR6, VAR9
);
output VAR6;
input VAR9;
assign VAR6 = VAR9;
endmodule
module MODULE15
(
VAR6, VAR9, VAR4
);
output VAR6;
input VAR9, VAR4;
assign VAR6 = ~(VAR9&VAR4);
endmodule
module MODULE13
(
VAR6, VAR9, VAR4
);
o... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_1.functional.pp.v | 1,583 | module MODULE1( VAR10, VAR1, VAR18, VAR9, VAR15, VAR11 );
input VAR1, VAR10, VAR18;
inout VAR15, VAR11;
output VAR9;
wire VAR19;
and VAR2( VAR19, VAR1, VAR10, VAR18 );
wire VAR7;
not VAR14( VAR7, VAR10 );
wire VAR17;
not VAR21( VAR17, VAR18 );
wire VAR20;
and VAR5( VAR20, VAR7, VAR17, VAR1 );
wire VAR3;
not VAR8( VAR3,... | apache-2.0 |
tgiv014/ECE441_Proj3 | sevseg_decoder.v | 2,911 | module MODULE1(VAR3, VAR2, VAR7, VAR10, VAR9, VAR6, VAR1, VAR4);
input [3:0] VAR3;
output reg VAR2, VAR7, VAR10, VAR9, VAR6, VAR1, VAR4;
parameter VAR5 = 1'b0;
parameter VAR8 = 1'b1;
always @(VAR3)
case (VAR3)
4'h0: begin
VAR2 = VAR5;
VAR7 = VAR5;
VAR10 = VAR5;
VAR9 = VAR5;
VAR6 = VAR5;
VAR1 = VAR5;
VAR4 = VAR8;
end
4'... | mit |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_auto_us_0/synth/triangle_intersect_auto_us_0.v | 9,770 | module MODULE1 (
VAR14,
VAR84,
VAR38,
VAR76,
VAR58,
VAR82,
VAR40,
VAR78,
VAR101,
VAR68,
VAR20,
VAR62,
VAR4,
VAR90,
VAR61,
VAR53,
VAR89,
VAR59,
VAR44,
VAR39,
VAR79,
VAR32,
VAR94,
VAR16,
VAR47,
VAR30,
VAR81,
VAR52,
VAR25,
VAR100,
VAR36,
VAR19,
VAR60,
VAR35
);
input wire VAR14;
input wire VAR84;
input wire [31 : 0] VAR38;... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/ucore/regfile.v | 7,284 | module MODULE1
(
VAR24,VAR14, VAR43,VAR36,VAR30, VAR11,VAR41,VAR20, VAR37,VAR12,VAR21 );
input VAR24;
input VAR14;
input VAR43;
input [5:0] VAR36;
input [31:0] VAR30;
input VAR11;
input [5:0] VAR41;
output [31:0] VAR20;
input VAR37;
input [5:0] VAR12;
output [31:0] VAR21;
reg [63:0] VAR10[31:0];
always @(posedge VAR24 ... | mit |
varunnagpaal/Digital-Hardware-Modelling | systemverilog/Sequential/regfile_16x32b_4rd_2wr.v | 2,450 | module MODULE1(input wire clk,
input wire rst,
input wire [3:0] VAR14,
output wire [31:0] VAR12,
input wire [3:0] VAR16,
output wire [31:0] VAR5,
input wire [3:0] VAR1,
output wire [31:0] VAR11,
input wire [3:0] VAR2,
output wire [31:0] VAR6,
input wire [3:0] VAR15,
input wire [31:0] VAR9,
input wire VAR8,
input wire [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.functional.pp.v | 1,891 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR10,
VAR1 ,
VAR3 ,
VAR5 ,
VAR4
);
output VAR8 ;
input VAR12 ;
input VAR10;
input VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR4 ;
wire VAR6 ;
wire VAR11;
not VAR7 (VAR6 , VAR10 );
and VAR13 (VAR11, VAR12, VAR6 );
VAR2 VAR9 (VAR8 , VAR11, VAR1, VAR3);
endmodule | apache-2.0 |
lee-dohm/atom-linguist | samples/Verilog/t_sqrt_pipelined.v | 2,075 | module MODULE1();
parameter
VAR3 = 4;
localparam
VAR1 = VAR3 / 2 + VAR3 % 2;
reg [VAR3-1:0] VAR5;
reg clk, VAR7, VAR6;
wire [VAR1-1:0] VAR4;
wire VAR8;
VAR2
.VAR3(VAR3)
)
VAR2
(
.clk(clk),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4)
); | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/ad9467_fmc/kc705/system_top.v | 8,256 | module MODULE1 (
VAR100,
VAR37,
VAR42,
VAR80,
VAR76,
VAR32,
VAR3,
VAR58,
VAR82,
VAR12,
VAR69,
VAR70,
VAR7,
VAR94,
VAR63,
VAR30,
VAR96,
VAR59,
VAR67,
VAR44,
VAR60,
VAR90,
VAR92,
VAR10,
VAR15,
VAR31,
VAR49,
VAR97,
VAR5,
VAR1,
VAR27,
VAR41,
VAR20,
VAR66,
VAR55,
VAR79,
VAR14,
VAR53,
VAR38,
VAR95,
VAR26,
VAR9,
VAR65,
VAR25,... | gpl-3.0 |
MarcoVogt/basil | firmware/modules/fei4_rx/sync_master.v | 6,678 | module MODULE1(
input wire clk, input wire VAR56, input wire VAR8, input wire rst, output wire VAR43, output wire VAR40, output wire VAR34, output wire VAR44, output wire [1:0] VAR21, output reg VAR32 );
wire VAR38 ;
wire VAR1 ;
wire VAR18 ;
wire VAR42 ;
reg VAR5 ;
reg VAR10 ;
reg VAR54 ;
reg VAR16 ;
reg VAR15 ;
reg VA... | bsd-3-clause |
donnaware/TabX1 | rtl/tabx1/ps2_keyboard.v | 21,239 | module MODULE2 (
input clk, input reset, input VAR76, input VAR59, output [7:0] VAR4, output [7:0] VAR62, output VAR81, output VAR47, output VAR9, output VAR64 );
wire VAR73;
wire VAR5;
wire VAR44;
assign VAR81 = VAR44;
wire VAR53 = VAR44;
wire [ 7:0] VAR40 = 8'h00; wire VAR34 = 1'b0;
wire VAR54 = 1'b1;
wire VAR82;
wir... | gpl-3.0 |
Raamakrishnan/MyProc | MyProc1/Proc.v | 6,418 | module MODULE1;
parameter VAR12 = 32;
parameter VAR10 = 16;
parameter VAR15 = (1<<13);
reg[7:0] VAR7[0:VAR15-1]; reg[VAR12-1:0] VAR5[0:VAR10-1]; reg[VAR12-1:0] VAR16; reg[VAR12-1:0] VAR1; reg VAR17; reg VAR18; reg VAR14; reg VAR9; reg VAR11; VAR4 VAR2 VAR10-1
reg[VAR12-1:0] VAR8; reg[VAR12-1:0] VAR6; reg[VAR12:0] VAR3;... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/dma_done_fifo.v | 8,505 | module MODULE1 # (
parameter VAR14 = 21,
parameter VAR21 = 4
)
(
input clk,
input VAR69,
input VAR26,
input [VAR14-1:0] VAR8,
output VAR32,
output VAR20,
input VAR9,
output [VAR14-1:0] VAR68,
output VAR5,
input VAR12,
input VAR18,
input VAR52,
input [VAR14-1:0] VAR74,
output VAR43
);
localparam VAR50 = 0;
localparam VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b_2.v | 2,082 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR7 ,
VAR5 ,
VAR6,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR8;
VAR3 VAR2 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4 ,
VAR1 ,
VAR7 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.pp.symbol.v | 1,497 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR2,
input VAR10 ,
input VAR1 ,
input VAR3 ,
input VAR6 ,
input VAR8 ,
input VAR7 ,
input VAR9
);
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_47.v | 30,389 | module MODULE4 (
clk,
reset,
VAR84,
VAR263,
VAR78,
VAR51,
VAR231
);
parameter VAR260 = 18;
parameter VAR88 = 47;
parameter VAR246 = 24;
localparam VAR75 = 48;
input clk;
input reset;
input VAR84;
input VAR263;
input [VAR260-1:0] VAR78; output VAR51;
output [VAR260-1:0] VAR231;
localparam VAR83 = 18; localparam VAR101 =... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn_2.v | 2,148 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR8,
VAR2,
VAR3,
VAR4 ,
VAR6
);
output VAR9 ;
input VAR5 ;
input VAR8;
input VAR2;
input VAR3;
input VAR4 ;
input VAR6 ;
VAR1 VAR7 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR9 ,
VAR5 ,
VAR8
);
output VAR9 ;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and4/gf180mcu_fd_sc_mcu9t5v0__and4_1.behavioral.v | 1,322 | module MODULE1( VAR8, VAR2, VAR7, VAR3, VAR4 );
input VAR8, VAR2, VAR7, VAR3;
output VAR4;
VAR5 VAR1(.VAR8(VAR8),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4));
VAR5 VAR6(.VAR8(VAR8),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a_2.v | 2,428 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR9 ,
VAR6 ,
VAR12,
VAR4,
VAR2 ,
VAR3
);
output VAR10 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR9 ;
input VAR6 ;
input VAR12;
input VAR4;
input VAR2 ;
input VAR3 ;
VAR11 VAR5 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(V... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ec_alu.v | 2,327 | module MODULE1(VAR22, VAR34, VAR6, VAR30, VAR12, VAR4, VAR9);
input wire [232:0] VAR34, VAR6, VAR30, VAR12;
input wire [9:0] VAR22;
output wire [232:0] VAR4, VAR9;
wire [232:0] VAR13, VAR25;
wire [232:0] VAR39, VAR20;
wire [232:0] VAR21, VAR3;
wire [232:0] VAR14, VAR15, VAR26, VAR36, VAR40, VAR8;
wire [232:0] VAR31;
wi... | gpl-3.0 |
AbhishekShah212/School_Projects | ELEN232/pset3/Problem4.v | 3,825 | module MODULE1(
input VAR5,
input VAR4,
input VAR1,
input VAR6,
output reg VAR2,
output reg VAR7,
output reg VAR3
);
reg [3:0] select;
always @ (VAR5 or VAR4 or VAR1 or VAR6)
begin
select = {VAR5, VAR4, VAR1, VAR6};
case(select)
4'b0000: begin
VAR2 = 1;
VAR7 = 0;
VAR3 = 1;
end
4'b0001: begin
VAR2 = 0;
VAR7 = 1;
VAR3 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp_1.v | 2,440 | module MODULE1 (
VAR3,
VAR5 ,
VAR9 ,
VAR2 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR10
);
input VAR3;
input VAR5 ;
input VAR9 ;
output VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR10 ;
VAR8 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
genkilife/miaow | src/verilog/rtl/common/decoder_6b_40b_en.v | 1,733 | module MODULE1(
VAR1,
en,
out);
input[5:0] VAR1;
wire[5:0] VAR1;
output[39:0] out;
wire[39:0] out;
input en;
wire en;
reg[39:0] VAR2;
always@(VAR1)
begin
VAR2 = 40'd0;
case (VAR1)
0: VAR2[0]=1'b1;
1: VAR2[1]=1'b1;
2: VAR2[2]=1'b1;
3: VAR2[3]=1'b1;
4: VAR2[4]=1'b1;
5: VAR2[5]=1'b1;
6: VAR2[6]=1'b1;
7: VAR2[7]=1'b1;
8: V... | bsd-3-clause |
zhangly/azpr_cpu | rtl/io/rom/rtl/rom.v | 1,574 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR5, input wire VAR1, input wire [VAR3] addr, output wire [VAR13] VAR6, output reg VAR10 );
VAR2 VAR11 (
.VAR14 (clk), .address (addr), .VAR9 (VAR6) );
always @(posedge clk or VAR12 reset) begin
if (reset == VAR8) begin
VAR10 <= VAR4;
end else begin
if ((VA... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad7980_v1_00_a/hdl/verilog/axi_ad7980.v | 10,393 | module MODULE1 (
VAR143,
VAR71,
VAR83,
VAR46,
VAR92,
VAR107,
VAR154,
VAR118,
VAR133,
VAR104,
VAR91,
VAR80,
VAR32,
VAR108,
VAR150,
VAR10,
VAR130,
VAR117,
VAR100,
VAR110,
VAR52,
VAR4,
VAR125,
VAR34,
VAR152,
VAR127,
VAR55,
VAR27,
VAR5,
VAR36,
VAR95,
VAR121,
VAR137,
VAR114,
VAR112,
VAR13,
VAR140);
parameter VAR153 = 0;
par... | mit |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb_pixelfeed.v | 5,047 | module MODULE1 #(
parameter VAR22 = 26
) (
input VAR44,
input VAR28,
input VAR13,
input [17:0] VAR29,
input [VAR22-1:0] VAR25,
output VAR4,
output reg [VAR22-1:0] VAR19,
output reg VAR8,
input VAR3,
input [63:0] VAR31,
output reg VAR24,
output [VAR22-1:0] VAR6,
input [63:0] VAR10,
input VAR21,
output VAR26,
output [15:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_sn.blackbox.v | 1,502 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR7,
VAR4 ,
VAR6 ,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR7;
input VAR4 ;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_16.v | 12,460 | module MODULE1 (
clk,
reset,
VAR46,
VAR81,
VAR12,
VAR94,
VAR17
);
parameter VAR70 = 18;
parameter VAR47 = 16;
parameter VAR40 = 8;
localparam VAR75 = 17;
input clk;
input reset;
input VAR46;
input VAR81;
input [VAR70-1:0] VAR12; output VAR94;
output [VAR70-1:0] VAR17;
localparam VAR32 = 18; localparam VAR85 = 36; local... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.pp.symbol.v | 1,448 | module MODULE1 (
input VAR8,
input VAR5,
input VAR9 ,
input VAR7 ,
output VAR3 ,
input VAR4 ,
input VAR6,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4bb/sky130_fd_sc_ls__or4bb.symbol.v | 1,327 | module MODULE1 (
input VAR7 ,
input VAR2 ,
input VAR5,
input VAR9,
output VAR4
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/8bitRISCProcessor/8bitRISCProcessor/RISC/ModmCountr.v | 1,271 | module MODULE1
input wire clk, reset,
output wire VAR9,
output wire [VAR3(VAR7)-1:0] VAR5
);
localparam VAR4 = VAR3(VAR7); reg [VAR4-1:0] VAR2;
wire [VAR4-1:0] VAR6;
always @(posedge clk, posedge reset)
if (reset)
VAR2 <= 0;
else
VAR2 <= VAR6;
assign VAR6 = (VAR2==(VAR7-1)) ? 0 : VAR2 + 1;
assign VAR5 = VAR2;
assign VA... | gpl-2.0 |
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