repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
sh-chris110/chris | FPGA/chris.system_ok/db/ip/soc_design/soc_design.v | 26,825 | module MODULE1 (
input wire VAR47, input wire VAR85 );
wire VAR178; wire [31:0] VAR48; wire VAR108; wire VAR133; wire [16:0] VAR78; wire [3:0] VAR216; wire VAR176; wire VAR170; wire VAR57; wire [31:0] VAR32; wire [3:0] VAR24; wire [31:0] VAR63; wire VAR153; wire [16:0] VAR34; wire VAR195; wire VAR22; wire [3:0] VAR38; ... | gpl-2.0 |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/soc_system_sysid_qsys.v | 2,206 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR1;
input VAR2;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1481413105 : 2899645186;
endmodule | epl-1.0 |
ad510/ee201l_cpu | InstrucMemoryHardcoded.v | 6,138 | module MODULE1 (VAR20, VAR21, VAR16, addr, VAR28, VAR27);
parameter VAR25 = 8;
parameter VAR4 = 256;
input VAR20;
input VAR21, VAR16;
input [VAR25-1:0] VAR28;
input [7:0] addr;
output [VAR25-1:0] VAR27;
reg [VAR25-1:0] VAR13;
always @ (posedge VAR20)
begin : VAR15
case (addr)
8'h0: VAR13 <= 32'VAR7; 8'h1: VAR13 <= 32'V... | mit |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,640 | module MODULE1 (
VAR18,
VAR41,
clk,
VAR52,
VAR10,
VAR40,
VAR44,
VAR39,
VAR42,
VAR33,
VAR12,
VAR26,
VAR46,
VAR35,
VAR13,
VAR31,
VAR48,
VAR55,
VAR50,
VAR3,
VAR36,
VAR53,
VAR28,
VAR19,
VAR24,
VAR23,
VAR14,
VAR29,
VAR1,
VAR17,
VAR30,
VAR22,
VAR25
)
;
output [ 37: 0] VAR36;
output VAR53;
output VAR28;
output VAR19;
output V... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/bin_cam/src/dpram.v | 8,859 | module MODULE1 (
VAR13,
VAR9,
VAR5,
VAR69,
VAR18,
VAR79,
VAR33,
VAR66
);
parameter VAR2 = "VAR26 VAR46";
parameter VAR12 = 8;
localparam VAR49 = 2**VAR12;
parameter VAR48 = 32; localparam VAR77 = VAR34(VAR48); localparam VAR70 = 2**VAR77;
localparam VAR62 = VAR49 * VAR70; localparam VAR3 = VAR12 + VAR77;
input VAR13;
i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a.pp.blackbox.v | 1,393 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR9 ,
VAR1 ,
VAR5 ,
VAR4,
VAR3,
VAR2 ,
VAR7
);
output VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.pp.symbol.v | 1,270 | module MODULE1 (
input VAR2 ,
input VAR3,
output VAR1,
input VAR4 ,
input VAR5,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/controller/bank_mach.v | 29,834 | module MODULE1 #
(
parameter VAR172 = 100,
parameter VAR20 = "1T",
parameter VAR86 = 3,
parameter VAR125 = 2,
parameter VAR42 = "8",
parameter VAR85 = 12,
parameter VAR18 = 4,
parameter VAR175 = 5,
parameter VAR96 = 8,
parameter VAR176 = "VAR148",
parameter VAR152 = "VAR164",
parameter VAR170 = "VAR164",
parameter VAR7... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3b/sky130_fd_sc_ms__or3b.functional.v | 1,371 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR6
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR6;
wire VAR7 ;
wire VAR9;
not VAR8 (VAR7 , VAR6 );
or VAR1 (VAR9, VAR2, VAR3, VAR7 );
buf VAR5 (VAR4 , VAR9 );
endmodule | apache-2.0 |
efabless/openlane | designs/chacha/src/chacha.v | 30,533 | module MODULE2(
input wire clk,
input wire VAR15,
input wire VAR159,
input wire VAR172,
input wire [7 : 0] addr,
input wire [31 : 0] VAR143,
output wire [31 : 0] VAR18
);
localparam VAR87 = 8'h00;
localparam VAR109 = 8'h01;
localparam VAR4 = 8'h02;
localparam VAR86 = 8'h08;
localparam VAR95 = 0;
localparam VAR171 = 1;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi.pp.symbol.v | 1,440 | module MODULE1 (
input VAR8 ,
input VAR4 ,
input VAR5 ,
input VAR1 ,
input VAR3 ,
output VAR10 ,
input VAR7 ,
input VAR9,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.blackbox.v | 1,264 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_nios2_qsys_0.v | 5,808 | module MODULE1 (
input wire clk, input wire VAR3, input wire VAR26, output wire [18:0] VAR25, output wire [3:0] VAR14, output wire VAR8, input wire [31:0] VAR19, input wire VAR15, output wire VAR16, output wire [31:0] VAR6, output wire VAR22, output wire [18:0] VAR9, output wire VAR11, input wire [31:0] VAR24, input wi... | gpl-3.0 |
mindrobots/P8X32A_Emulation | P8X32A_BeMicroCV/cog.v | 17,326 | module MODULE1
(
input VAR41,
input VAR13, input VAR14,
input VAR38,
input VAR106, input [27:0] VAR39,
input VAR86,
input VAR36, output VAR92,
output VAR104,
output VAR83,
output [1:0] VAR57,
output [15:0] VAR74,
output [31:0] VAR46,
input [31:0] VAR111,
input VAR9,
input VAR97,
input [31:0] VAR80,
input [7:0] VAR42, o... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rx_engine_classic.v | 23,567 | module MODULE1
parameter VAR27 = 128,
parameter VAR47=6)
( input VAR29,
input VAR6, input VAR45, output VAR97,
output VAR59,
input [VAR27-1:0] VAR32,
input VAR69,
output VAR64,
input VAR95,
input [VAR19-1:0] VAR84,
input VAR16,
input [VAR19-1:0] VAR39,
input [VAR50-1:0] VAR24,
output [VAR27-1:0] VAR33,
output VAR54,
ou... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks117.v | 10,575 | module MODULE1(VAR10, VAR9, VAR13);
input wire [116:0] VAR10;
input wire [116:0] VAR9;
output wire [232:0] VAR13;
wire [114:0] VAR3;
wire [116:0] VAR1;
wire [116:0] VAR8;
wire [58:0] VAR6;
wire [58:0] VAR12;
VAR5 VAR2(VAR10[58:0], VAR9[58:0], VAR1);
VAR11 VAR4(VAR10[116:59], VAR9[116:59], VAR3);
assign VAR6[57:0] = VAR... | gpl-3.0 |
tsujamin/tsu0 | rtl/control_unit.v | 4,261 | module MODULE1();
parameter VAR2 = 12;
parameter VAR1 = 16;
reg VAR3;
VAR4 begin VAR3 <= 1'b1;
forever VAR3 = ~VAR3;
end | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b.pp.symbol.v | 1,318 | module MODULE1 (
input VAR2 ,
input VAR5 ,
input VAR4 ,
input VAR3 ,
output VAR6 ,
input VAR7 ,
input VAR1,
input VAR8,
input VAR9
);
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/new/PS2_top.v | 1,907 | module MODULE1(
input VAR29,
input VAR15,
input VAR16 ,
input VAR18 ,
output VAR12,VAR24,VAR10,VAR14,VAR4,VAR11,
output wire VAR22 , output wire VAR28 , output wire VAR9 , output reg VAR1 , output reg VAR19 , output reg VAR6 ) ;
localparam VAR21 = 3'd1;
localparam VAR13 = 3'd2;
localparam VAR20 = 3'd3;
localparam VAR25... | apache-2.0 |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_RegisterFile_0_0/RAT_RegisterFile_0_0_stub.v | 1,427 | module MODULE1(VAR4, VAR3, VAR7, VAR2, VAR6, VAR1, VAR5)
;
input [7:0]VAR4;
output [7:0]VAR3;
output [7:0]VAR7;
input [4:0]VAR2;
input [4:0]VAR6;
input VAR1;
input VAR5;
endmodule | mit |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/TF_EECS301_Lab2_TopLevel.v | 1,960 | module MODULE1();
reg [3:0] VAR1;
reg [1:0] VAR2;
wire [9:0] VAR7;
wire [6:0] VAR5;
wire [6:0] VAR3;
wire [6:0] VAR4;
wire [6:0] VAR6;
wire [6:0] VAR8;
wire [6:0] VAR12;
localparam VAR9 = 50000000; localparam VAR10 = ((1.0 / VAR9) * 1000000000.0) / 2.0;
reg VAR11;
begin
begin | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/synth/OpenSSD2_Tiger4NSC_0_0.v | 14,564 | module MODULE1 (
VAR8,
VAR65,
VAR11,
VAR34,
VAR51,
VAR88,
VAR86,
VAR84,
VAR69,
VAR42,
VAR76,
VAR57,
VAR74,
VAR2,
VAR60,
VAR29,
VAR91,
VAR62,
VAR36,
VAR22,
VAR17,
VAR56,
VAR47,
VAR18,
VAR82,
VAR83,
VAR28,
VAR64,
VAR63,
VAR46,
VAR53,
VAR44,
VAR66,
VAR25,
VAR23,
VAR50,
VAR33,
VAR14,
VAR79,
VAR32,
VAR75,
VAR21,
VAR40,
VAR7... | gpl-3.0 |
lowRISC/flexpret | Gateway.v | 8,433 | module MODULE1(
VAR9,
VAR37,
VAR39,
VAR11,
VAR1,
VAR33,
VAR31,
VAR21,
VAR6,
VAR35,
VAR8,
VAR5,
VAR30
);
parameter VAR13 = 8, VAR18 = 32, VAR4 = VAR18;
localparam VAR29 = 32'hffff0000, VAR36 = 32'hffff0004, VAR20 = 32'hffff0008, VAR15 = 32'hffff000C;
input wire VAR9, VAR37;
input [VAR13-1:0] VAR39;
input VAR11;
output V... | bsd-3-clause |
twlostow/dsi-shield | hdl/rtl/dsi_core/dsi_core.v | 15,392 | module MODULE1
(
VAR98,
VAR161,
VAR123,
VAR84,
VAR45,
VAR66,
VAR120,
VAR68,
VAR153,
VAR28,
VAR69,
VAR20,
VAR103,
VAR86,
VAR112,
VAR158,
VAR191,
VAR172,
VAR118,
VAR47,
VAR14,
VAR26,
VAR88,
VAR95,
VAR114,
VAR43,
VAR30,
VAR31,
VAR85,
VAR156,
VAR34,
VAR175,
VAR2
);
parameter VAR142 = 1;
parameter VAR3 = 3;
parameter VAR4 =... | lgpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_mul.v | 6,867 | module MODULE1 (
clk,
VAR19,
VAR18,
VAR2,
VAR23,
VAR17);
parameter VAR4 = 16;
parameter VAR15 = VAR4 - 1;
input clk;
input [16:0] VAR19;
input [ 7:0] VAR18;
output [24:0] VAR2;
input [VAR15:0] VAR23;
output [VAR15:0] VAR17;
reg VAR3 = 'd0;
reg [VAR15:0] VAR7 = 'd0;
reg [23:0] VAR8 = 'd0;
reg [23:0] VAR9 = 'd0;
reg [23:... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_spram_32x24.v | 8,265 | module MODULE1(
VAR7, VAR23, VAR30,
clk, rst, VAR20, VAR28, VAR24, addr, VAR8, VAR19
);
parameter VAR27 = 5;
parameter VAR26 = 24;
input VAR7;
input [VAR15 - 1:0] VAR30;
output VAR23;
input clk; input rst; input VAR20; input VAR28; input VAR24; input [VAR27-1:0] addr; input [VAR26-1:0] VAR8; output [VAR26-1:0] VAR19;
w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxtp/sky130_fd_sc_ls__dlxtp.pp.symbol.v | 1,333 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR2,
input VAR4 ,
input VAR7,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3.pp.blackbox.v | 1,302 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR6 ,
VAR7 ,
VAR2,
VAR1,
VAR4 ,
VAR5
);
output VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR7 ;
input VAR2;
input VAR1;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/cheat.v | 9,350 | module MODULE1(
input clk,
input [7:0] VAR53,
input [23:0] VAR38,
input [7:0] VAR19,
input VAR34,
input VAR56,
input VAR11,
input VAR12,
input VAR22,
input VAR59,
input VAR8,
input VAR31,
input VAR10,
input VAR48,
input VAR57,
input VAR24,
output VAR60,
output [8:0] VAR44,
output [7:0] VAR35,
output VAR2,
output VAR32,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.pp.symbol.v | 1,257 | module MODULE1 (
input VAR6 ,
input VAR7 ,
output VAR5 ,
input VAR3 ,
input VAR4,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
cybero/Verilog | src/PicoBlaze (kcpsm6)/Utilities/KCPSM6_Release9_30Sept14/UART_and_PicoTerm/uart_tx6.v | 11,248 | module MODULE1 (
input [7:0] VAR13,
input VAR83,
input VAR16,
input VAR30,
output VAR27,
output VAR75,
output VAR77,
output VAR20,
input clk );
wire [7:0] VAR35;
wire [7:0] VAR24;
wire [3:0] VAR66;
wire [3:0] VAR45;
wire VAR26;
wire VAR39;
wire VAR38;
wire VAR11;
wire VAR21;
wire [3:0] VAR84;
wire [3:0] VAR82;
wire [3:... | mit |
skarpenko/ultiparc | rtl/src/ibus2ocp.v | 2,437 | module MODULE1(
VAR7,
VAR4,
VAR1,
VAR15,
VAR18,
VAR11,
VAR3,
VAR13,
VAR19,
VAR2,
VAR5,
VAR9
);
input wire [VAR12-1:0] VAR7;
input wire VAR4;
output reg [VAR6-1:0] VAR1;
output reg VAR15;
output reg VAR18;
output reg [VAR12-1:0] VAR11;
output reg [2:0] VAR3;
output reg [VAR6-1:0] VAR13;
output reg [VAR8-1:0] VAR19;
inpu... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.pp.blackbox.v | 1,523 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR8 ,
VAR10 ,
VAR4 ,
VAR11,
VAR3 ,
VAR5 ,
VAR6 ,
VAR2
);
output VAR9 ;
output VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR11;
input VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/verilog/HLS_accel_CONTROL_BUS_s_axi.v | 8,816 | module MODULE1
VAR35 = 4,
VAR4 = 32
)(
input wire VAR40,
input wire VAR25,
input wire VAR1,
input wire [VAR35-1:0] VAR8,
input wire VAR6,
output wire VAR30,
input wire [VAR4-1:0] VAR2,
input wire [VAR4/8-1:0] VAR52,
input wire VAR46,
output wire VAR5,
output wire [1:0] VAR21,
output wire VAR11,
input wire VAR16,
input ... | mit |
asicguy/gplgpu | hdl/de/ded_colsel.v | 8,399 | module MODULE1
(
input VAR6, input VAR10, input VAR22, input VAR13, input [1:0] VAR20, input VAR19, input [31:0] VAR4, input [31:0] VAR14, input [(VAR12<<3)-1:0] VAR16, input [VAR12-1:0] VAR8, input [(VAR12<<3)-1:0] VAR3, input VAR9,
output reg [(VAR12<<3)-1:0] VAR15, output [VAR12-1:0] VAR21 );
reg [(VAR12<<3)-1:0] VA... | gpl-3.0 |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/RegistroWithMuxInput.v | 3,844 | module MODULE1#(parameter VAR24 = 4)
(VAR38,VAR36,reset,VAR35,VAR18,VAR10,VAR17,VAR26,VAR21,VAR8,VAR30,VAR41,VAR45,VAR5,VAR14,
VAR40,VAR39,VAR33,VAR34,VAR47,VAR42,VAR9,VAR50,VAR19,VAR44,VAR29,VAR32,VAR16,VAR31);
input signed [VAR24-1:0] VAR10,VAR17,VAR26,VAR21,VAR8,VAR30,VAR41,VAR45,VAR5,
VAR14,VAR40,VAR39,VAR33,VAR34,... | gpl-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/altera_up_video_decoder_add_endofpacket.v | 5,718 | module MODULE1 (
clk,
reset,
VAR14,
VAR8,
VAR3,
VAR10,
VAR16,
VAR9,
VAR11,
VAR5,
VAR15,
VAR7
);
parameter VAR2 = 15;
input clk;
input reset;
input [VAR2: 0] VAR14;
input VAR8;
input VAR3;
input VAR10;
input VAR16;
output VAR9;
output reg [VAR2: 0] VAR11;
output reg VAR5;
output reg VAR15;
output reg VAR7;
wire VAR4;
re... | gpl-3.0 |
skalldri/mips-verilog | memory/memory2.v | 3,137 | module MODULE1 (clk, addr, din, dout, VAR5, VAR9, VAR14, VAR7, enable);
parameter VAR3 = "VAR15.VAR4";
input clk;
input [31:0] addr;
input [31:0] din;
input [2:0] VAR9;
input VAR14; input enable;
output reg VAR7;
output reg [31:0] dout;
output reg [31:0] VAR5;
reg [7:0] VAR10[0:VAR11];
reg [31:0] VAR13 = 'hffff; reg [5... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_2.behavioral.v | 1,193 | module MODULE1( VAR6, VAR1, VAR3 );
input VAR6, VAR1;
output VAR3;
VAR2 VAR4(.VAR6(VAR6),.VAR1(VAR1),.VAR3(VAR3));
VAR2 VAR5(.VAR6(VAR6),.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/bus_if.v | 5,676 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR19, input wire VAR39, output reg VAR4,
input wire [VAR23] addr, input wire VAR5, input wire VAR14, input wire [VAR6] VAR35, output reg [VAR6] VAR17,
input wire [VAR6] VAR37, output wire [VAR23] VAR1, output reg VAR24, output wire VAR26, output wire [VAR6]... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/regfileww.v | 5,172 | module MODULE1 (VAR1,VAR2,VAR6,VAR7,VAR3,VAR4,
VAR13,VAR8,VAR14,VAR9,clk);
output [127:0] VAR1,VAR2;
input [0:127] VAR6;
input clk;
input VAR14;
input VAR13, VAR8;
input [4:0] VAR4, VAR7, VAR3;
input [15:0] VAR9;
reg [127:0] VAR1,VAR2;
reg [127:0] VAR5 [31:0];
reg [127:0] VAR10; reg [127:0] VAR11; reg [7:0] VAR12;
alwa... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/pcx_dp4.v | 15,875 | module MODULE1(
VAR41, VAR13,
VAR4, VAR3, VAR23, VAR38,
VAR20, VAR11,
VAR32, VAR8, VAR33,
VAR14, VAR39, VAR48,
VAR15, VAR28, VAR7,
VAR22
);
output [7:0] VAR41;
output [VAR50-1:0] VAR13;
input [7:0] VAR8; input [7:0] VAR32; input [7:0] VAR11; input [7:0] VAR20; input [7:0] VAR38; input VAR23; input [7:0] VAR3; input VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.blackbox.v | 1,319 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR2;
supply1 VAR4;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/7segment.v | 2,338 | module MODULE2(VAR9, VAR11);
input [3:0] VAR9;
output reg [6:0] VAR11;
always @
case (VAR16)
0:VAR14 = (VAR11[6]?5'b11111:0)
^ (VAR11[5]?5'b00001:0)
^ (VAR11[1]?5'b10000:0);
1:VAR14 = (VAR11[1]?5'b10000:0)
^ (VAR11[5]?5'b00001:0);
2:VAR14 = (VAR11[0]?5'b11111:0)
^ (|VAR11[5:4]?5'b00001:0)
^ (|VAR11[2:1]?5'b10000:0);
3:... | gpl-3.0 |
GustavoOS/ARMAria | src/ControlUnit/instructiondecoder.v | 14,458 | module MODULE1 #(
parameter VAR5 = 16,
parameter VAR6 = 7,
parameter VAR15 = 4,
parameter VAR8 = 12,
parameter VAR2 = 4,
parameter VAR19 = 2048,
parameter VAR14 = 4'hc,
parameter VAR3 = 4'he,
parameter VAR9 = 4'hf
)(
input [(VAR5 - 1) : 0] VAR16,
output reg [(VAR6 - 1) : 0] VAR12,
output reg [(VAR15 - 1) : 0] VAR4, VAR... | mit |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/ewrapper_link_txo.v | 12,046 | module MODULE1(
VAR23, VAR25,
reset, VAR37, VAR49, VAR16,
VAR28, VAR60, VAR13,
VAR48, VAR4, VAR35
);
input reset; input VAR37;
input VAR49;
input VAR16;
input [1:0] VAR28;
input [3:0] VAR60;
input [31:0] VAR13;
input [31:0] VAR48;
input [31:0] VAR4;
input VAR35;
output VAR23;
output [71:0] VAR25;
reg VAR53;
reg VAR58;
... | lgpl-3.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/lsu/lsu.v | 8,014 | module MODULE1
(
VAR50,
VAR53, VAR4,
VAR47, VAR55,
VAR11, VAR56,
VAR46,
VAR61, VAR59,
VAR70,
VAR84,
VAR32,
VAR96, VAR66, VAR23,
VAR30, VAR37, VAR40,
VAR86, VAR104,
VAR28,
VAR101,
VAR75, VAR68, VAR39,
VAR95, VAR45,
VAR38, VAR49,
VAR14, VAR97,
VAR13, VAR73, VAR63,
clk, rst, VAR62, VAR44, VAR52, VAR98,
VAR18, VAR36, VAR6,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb.blackbox.v | 1,294 | module MODULE1 (
VAR7 ,
VAR1,
VAR6,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR1;
input VAR6;
input VAR3 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/BypassCrossingWire.v | 1,381 | module MODULE1(VAR3, VAR2);
parameter VAR1 = 1;
input [VAR1 - 1 : 0] VAR2;
output [VAR1 - 1 : 0] VAR3;
assign VAR3 = VAR2;
endmodule | lgpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/hps_sdram_p0_acv_ldc.v | 3,402 | module MODULE1
(
VAR20,
VAR23,
VAR43,
VAR5,
VAR25,
VAR32,
VAR3,
VAR4,
VAR22
);
parameter VAR13 = "";
parameter VAR45 = 0;
parameter VAR10 = "false";
parameter VAR21 = "false";
input VAR20;
input VAR23;
input VAR43;
input [VAR13-1:0] VAR5;
output VAR25;
output VAR32;
output VAR3;
output VAR4;
output VAR22;
wire VAR9;
wi... | gpl-3.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_qpram.v | 2,978 | module MODULE1 #(
parameter VAR22 = 11
) (
input VAR31,
input [VAR22-1:0] VAR24,
output reg [15:0] VAR21,
input [VAR22-1:0] VAR15,
output reg [15:0] VAR26,
input [VAR22-1:0] VAR27,
output reg [15:0] VAR6,
input [VAR22-1:0] VAR16,
output reg [15:0] VAR29,
input VAR11,
input [VAR22-1:0] VAR10,
input [255:0] VAR18
);
wire... | lgpl-3.0 |
kyzhai/NUNY | src/hardware/lab3/synthesis/submodules/lab3_master_0_timing_adt.v | 1,769 | module MODULE1 (
input clk,
input VAR5,
input VAR8,
input [ 7: 0] VAR6,
output reg VAR1,
output reg [ 7: 0] VAR3,
input VAR4
);
reg [ 7: 0] VAR2;
reg [ 7: 0] VAR9;
reg [ 0: 0] ready;
reg VAR7;
always @(negedge VAR7) begin
end
always @* begin
VAR2 = {VAR6};
{VAR3} = VAR9;
end
always @* begin
ready[0] = VAR4;
VAR1 = VAR8... | gpl-2.0 |
amontefusco/gnuradio-amontefusco | gr-gpio/src/fpga/lib/integrator.v | 2,214 | module MODULE1
( VAR12,reset,enable,VAR16,VAR14,VAR2,VAR11,VAR9);
parameter VAR7 = 16;
parameter VAR3 = 8;
input VAR12;
input reset;
input enable;
input [7:0] VAR16;
input VAR14;
input VAR2;
input [VAR7-1:0] VAR11;
wire [VAR7-1:0] VAR10;
output [VAR7-1:0] VAR9;
reg [VAR7-1:0] VAR9;
wire [VAR7+VAR3-1:0] VAR1;
reg [VAR7+... | gpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/code/SynchronizeClkDomains.v | 3,133 | module MODULE1(
VAR12,VAR14,VAR20,
VAR16,VAR15, VAR4 ,VAR6,
VAR2, VAR13, VAR19,VAR5,
VAR1,VAR11,VAR22,VAR17
);
input VAR12;
input VAR14;
input VAR20;
input VAR16;
input VAR4;
output reg VAR15;
output reg VAR6;
input [2:0] VAR2;
input [VAR3-4:0] VAR13;
input VAR19;
input [2:0] VAR5;
output reg [2:0] VAR1;
output reg [VA... | gpl-2.0 |
aanunez/KeypadScanner | Source/PulseCounter.v | 1,110 | module MODULE1(
input VAR6,
input VAR1,
input VAR2,
output [3:0] VAR3
);
reg [3:0] VAR4;
reg VAR5;
always @(posedge VAR1, negedge VAR6) begin
if ( VAR6 == 0 )
VAR4 <= 4'b0000;
end
else begin
if ((VAR2==1) & (VAR5==0)) begin
VAR4 <= VAR4 + 1'b1;
VAR5 <= 1;
end
else if (VAR2==0) begin
VAR5 <= 0;
end
end
end
assign VAR3 =... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/mux.v | 5,122 | module MODULE1
parameter VAR13 = 4,
parameter VAR4 = 2,
parameter VAR2 = 32,
parameter VAR8 = "VAR7"
)
(
input [(VAR13)*VAR2-1:0] VAR11,
input [VAR4-1:0] VAR6,
output [VAR2-1:0] VAR9
);
generate
if(VAR8 == "VAR7") begin
MODULE3
.VAR13 (VAR13),
.VAR4 (VAR4),
.VAR2 (VAR2))
VAR14
(
.VAR9 (VAR9[VAR2-1:0]),
.VAR11 (VAR11[(V... | gpl-3.0 |
aj-michael/Digital-Systems | hw1problem1/encoder43table.v | 1,073 | module MODULE1(VAR4, VAR7, VAR2, VAR5, VAR6, VAR1, VAR3);
input VAR4, VAR7, VAR2, VAR5;
output reg VAR6, VAR1, VAR3;
always@(VAR4, VAR7, VAR2, VAR5)
case({VAR4, VAR7, VAR2, VAR5})
4'b0000: {VAR6, VAR1, VAR3} = 3'b000;
4'b0001: {VAR6, VAR1, VAR3} = 3'b001;
4'b0010: {VAR6, VAR1, VAR3} = 3'b001;
4'b0011: {VAR6, VAR1, VAR3... | mit |
HighlandersFRC/fpga | led_string/led_string.srcs/sources_1/new/main.v | 2,513 | module MODULE1 (
input VAR26,
output reset,
output VAR22,
output VAR2,
output VAR21,
output VAR4,
output VAR3,
output VAR33,
output VAR6,
output VAR7,
output VAR14,
output reg VAR13,
output reg VAR23
);
wire [7 : 0] VAR17;
wire [10 : 0] VAR24;
wire [7 : 0] VAR11;
wire VAR5;
wire VAR18;
wire [31 : 0] VAR12;
wire VAR20;
... | mit |
google/bbcpu | mul4x4.v | 1,634 | module MODULE1(
input [3 : 0] VAR6,
input [3 : 0] VAR8,
output [7 : 0] VAR11);
wire [2 : 0] VAR9, VAR7;
wire [7 : 0] VAR24, VAR21, VAR23, VAR1, VAR18, VAR20;
assign VAR24 = {4'b0, VAR8[0] ? VAR6 : {3'b0}};
VAR12 VAR25(
.VAR6({4'b0, VAR8[1] ? VAR6 : {3'b0}}),
.VAR22(3'b001),
.VAR11(VAR21),
.VAR15(VAR9[0]));
VAR12 VAR10(... | apache-2.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/adc_pll/adc_pll_0002.v | 2,236 | module MODULE1(
input wire VAR30,
input wire rst,
output wire VAR2,
output wire VAR56,
output wire VAR44
);
VAR6 #(
.VAR51("false"),
.VAR36("240.0 VAR59"),
.VAR33("VAR35"),
.VAR24(2),
.VAR32("60.000000 VAR59"),
.VAR47("2315 VAR23"),
.VAR3(50),
.VAR45("60.000000 VAR59"),
.VAR70("2315 VAR23"),
.VAR25(50),
.VAR18("0 VAR59... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb8to1/sky130_fd_sc_hdll__muxb8to1_1.v | 2,219 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR7 ,
VAR1,
VAR9,
VAR5 ,
VAR2
);
output VAR4 ;
input [7:0] VAR8 ;
input [7:0] VAR7 ;
input VAR1;
input VAR9;
input VAR5 ;
input VAR2 ;
VAR3 VAR6 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR4,
VAR8,
VAR7
);
o... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.behavioral.v | 1,108 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR2 VAR4(.VAR5(VAR5),.VAR1(VAR1));
VAR2 VAR3(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/mux_32.v | 3,166 | module MODULE1(
VAR19,
VAR15 ,
VAR6 ,
VAR24 ,
VAR34 ,
VAR10 ,
VAR28 ,
VAR11 ,
VAR5 ,
VAR8 ,
VAR14 ,
VAR21,
VAR32,
VAR25,
VAR2,
VAR22,
VAR18,
VAR12,
VAR9,
VAR20,
VAR23,
VAR17,
VAR27,
VAR29,
VAR7,
VAR26,
VAR16,
VAR13,
VAR3,
VAR30,
VAR33,
VAR1,
VAR31,
VAR4
);
input [4:0] VAR19;
input signed [15:0] VAR15 ;
input signed [15... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.blackbox.v | 1,264 | module MODULE1 (
VAR8,
VAR4,
VAR1,
VAR5
);
output VAR8;
input VAR4;
input VAR1;
input VAR5;
supply1 VAR7;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.v | 2,469 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR1 ,
VAR12 ,
VAR5 ,
VAR8 ,
VAR7,
VAR10,
VAR11 ,
VAR3
);
output VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR12 ;
input VAR5 ;
input VAR8 ;
input VAR7;
input VAR10;
input VAR11 ;
input VAR3 ;
VAR6 VAR9 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(V... | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/rom.v | 4,900 | module MODULE1
parameter VAR12 = 0)
(
input VAR8,
input VAR19,
input [(VAR3+2)-1:2] VAR9,
input VAR1,
input VAR7,
input [2:0] VAR4,
input [1:0] VAR18,
output reg [31:0] VAR11,
output reg VAR16);
reg [VAR3-1:0] VAR14;
always @ (posedge VAR8 or posedge VAR19)
if (VAR19)
VAR11 <= 32'h15000000;
else
case (VAR14)
0 : VAR11 ... | gpl-2.0 |
trun/fpgaboy | src/gb/joypad.v | 1,066 | module MODULE1(
input wire VAR8,
input wire reset,
input wire VAR3,
output reg VAR7,
input wire [15:0] VAR5,
input wire [7:0] VAR1,
output wire [7:0] VAR11,
input wire VAR9,
input wire VAR6,
input wire VAR2,
output reg [1:0] VAR10,
input wire [3:0] VAR4
);
always @(posedge VAR8) begin
if (reset)
VAR7 <= 0;
end
else beg... | mit |
SiLab-Bonn/basil | basil/firmware/modules/i2c/i2c_core.v | 8,727 | module MODULE1 #(
parameter VAR10 = 16,
parameter VAR16 = 1,
parameter VAR37 = 0
) (
input wire VAR66,
input wire VAR35,
input wire [VAR10-1:0] VAR6,
input wire [7:0] VAR54,
input wire VAR46,
input wire VAR22,
output reg [7:0] VAR60,
input wire VAR42,
inout wire VAR2,
inout wire VAR12
);
localparam VAR29 = 1;
reg [7:0]... | bsd-3-clause |
parallella/oh | common/hdl/oh_mem_dp.v | 3,266 | module MODULE1
( input VAR10, input VAR11, input [VAR20-1:0] VAR16, input [VAR28-1:0] VAR33, input [VAR20-1:0] VAR19, input VAR6, input VAR7, input [VAR28-1:0] VAR34, output [VAR20-1:0] VAR8, input VAR3, input VAR26, input [VAR20-1:0] VAR31, input [VAR28-1:0] VAR9, input [VAR20-1:0] VAR4, input VAR22, input VAR35, inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.blackbox.v | 1,287 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR3;
endmodule | apache-2.0 |
mfkiwl/parallella-platform | hdl/ewrapper_link_top.v | 9,072 | module MODULE1 (
VAR65, VAR27, VAR80,
VAR102, VAR110, VAR69,
VAR92, VAR3, VAR13,
VAR19, VAR73, VAR114, VAR56,
VAR1, VAR20, VAR21, VAR59, VAR112,
VAR85, VAR35, VAR28, VAR48,
reset, VAR106, VAR46, VAR17,
VAR81, VAR57, VAR18,
VAR14, VAR66, VAR5,
VAR63, VAR47, VAR75, VAR53,
VAR38, VAR97, VAR22, VAR25, VAR68,
VAR31, VAR51, ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xnor2/sky130_fd_sc_hvl__xnor2.functional.v | 1,309 | module MODULE1 (
VAR1,
VAR5,
VAR3
);
output VAR1;
input VAR5;
input VAR3;
wire VAR4;
xnor VAR6 (VAR4, VAR5, VAR3 );
buf VAR2 (VAR1 , VAR4 );
endmodule | apache-2.0 |
ptracton/vscale_soc | rtl/uart16550-1.5.4/rtl/verilog/uart_transmitter.v | 12,335 | module MODULE1
(clk, VAR27, VAR12, VAR5, VAR39, enable, VAR44, VAR41, VAR13, VAR31, VAR36);
input clk;
input VAR27;
input [7:0] VAR12;
input VAR5;
input [7:0] VAR39;
input enable;
input VAR31;
input VAR36; output VAR44;
output [2:0] VAR41;
output [VAR29-1:0] VAR13;
reg [2:0] VAR41;
reg [4:0] counter;
reg [2:0] VAR14; r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b.behavioral.v | 1,475 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR10 ,
VAR7
);
output VAR8 ;
input VAR5 ;
input VAR10 ;
input VAR7;
supply1 VAR9;
supply0 VAR13;
supply1 VAR4 ;
supply0 VAR6 ;
wire VAR11 ;
wire VAR2;
not VAR12 (VAR11 , VAR7 );
or VAR3 (VAR2, VAR10, VAR5, VAR11 );
buf VAR1 (VAR8 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon.pp.blackbox.v | 1,625 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR3,
VAR2 ,
VAR7 ,
VAR1 ,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR3;
input VAR2 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
cthulhuology/avm | rom.v | 3,889 | module MODULE1 (
input VAR13,
input VAR8,
input [VAR12-1:0] VAR5,
output [VAR12-1:0] VAR6);
reg [10:0] VAR7;
always @* begin
VAR7 <= VAR5[10:0];
end
VAR15 #(
) VAR14 (
.VAR1(VAR6[1:0]),
.VAR19(VAR7),
.VAR25(VAR13),
.VAR24(1'b1),
.VAR22(VAR8),
.VAR3(2'VAR18),
.VAR21(11'b0),
.VAR16(VAR13),
.VAR9(1'b0),
.VAR17(1'b0),
.VAR... | bsd-3-clause |
sittner/lcnc-mdsio | vhdl/source/uart16550/uart_top.v | 11,621 | module MODULE1 (
VAR36,
VAR3, VAR30, VAR37, VAR38, VAR40, VAR22, VAR13, VAR14, VAR49,
VAR16,
VAR28, VAR1,
VAR31, VAR15, VAR43, VAR19, VAR17, VAR7
, VAR33
);
parameter VAR5 = VAR9;
parameter VAR25 = VAR2;
input VAR36;
input VAR3;
input [VAR25-1:0] VAR30;
input [VAR5-1:0] VAR37;
output [VAR5-1:0] VAR38;
input VAR40;
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.blackbox.v | 1,337 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR5 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR3;
supply1 VAR7;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/hdmi/serdes_n_to_1.v | 5,373 | module MODULE1 (VAR40, VAR38, reset, VAR16, VAR15, VAR42) ;
parameter integer VAR28 = 8 ;
input VAR40 ; input VAR38 ; input reset ; input VAR16 ; input [VAR28-1 : 0] VAR15 ; output VAR42 ;
wire VAR34 ; wire VAR14 ; wire VAR2 ; wire VAR7 ; wire [8:0] VAR37 ;
genvar VAR18 ; generate
for (VAR18 = 0 ; VAR18 <= (VAR28 - 1) ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3.blackbox.v | 1,256 | module MODULE1 (
VAR2,
VAR3,
VAR4,
VAR1
);
output VAR2;
input VAR3;
input VAR4;
input VAR1;
supply1 VAR5;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_new_io_pads.v | 12,070 | module MODULE1(
VAR13,
VAR151,
VAR35,
VAR148,
VAR130,
VAR10,
VAR39,
VAR139,
VAR60,
VAR98,
VAR94,
VAR113,
VAR108,
VAR19,
VAR122,
VAR27,
VAR51,
VAR74,
VAR17,
VAR101,
VAR7,
VAR5,
VAR115,
VAR26,
VAR145,
VAR43,
VAR69,
VAR44,
VAR48,
VAR126,
VAR40,
VAR65,
VAR2,
VAR77,
VAR121,
VAR93,
VAR127,
VAR90,
VAR49,
VAR83,
VAR52,
VAR64,
... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.functional.pp.v | 1,692 | module MODULE1( VAR1, VAR5, VAR17, VAR19, VAR11, VAR8, VAR4, VAR15 );
input VAR17, VAR5, VAR1, VAR11, VAR8;
inout VAR4, VAR15;
output VAR19;
wire VAR2;
not VAR21( VAR2, VAR17 );
wire VAR16;
not VAR13( VAR16, VAR5 );
wire VAR6;
not VAR14( VAR6, VAR1 );
wire VAR3;
and VAR18( VAR3, VAR2, VAR16, VAR6 );
wire VAR20;
not VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.functional.v | 1,281 | module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
wire VAR3;
not VAR2 (VAR3, VAR4 );
buf VAR5 (VAR1 , VAR3 );
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/eth_crc32.v | 2,991 | module MODULE1
(input VAR16, input VAR1, input VAR4, input [7:0] VAR14, output [31:0] VAR12);
wire VAR13;
VAR1 #(1) VAR17(.VAR16(VAR16), .VAR14(VAR4), .rst(1'b0), .en(1'b1), .VAR18(VAR13));
wire [7:0] VAR19; VAR1 #(8) VAR2(.VAR16(VAR16), .VAR14(VAR14), .rst(1'b0), .en(1'b1), .VAR18(VAR19));
wire [31:0] VAR3;
wire [31:0... | apache-2.0 |
parallella/oh | common/hdl/oh_standby.v | 3,033 | module MODULE1 #(parameter VAR19 = 5, parameter VAR6 = 5) ( input VAR11, input VAR15, input VAR4, input VAR18, input VAR12, output VAR1, output VAR8 );
reg [VAR19-1:0] VAR21;
wire VAR2;
wire VAR5;
wire VAR22;
wire VAR3;
VAR17 #(.VAR9(2)) VAR17 ( .dout(VAR2),
.VAR15(VAR15),
.din(VAR15),
.clk(VAR11)
);
VAR20 VAR10 ( .out... | mit |
DreamSourceLab/DSLogic-hdl | src/ipcore_dir/in_dcm.v | 5,910 | module MODULE1
( input VAR7,
output VAR9,
output VAR13,
input VAR14,
output VAR12
);
VAR43 VAR30
(.VAR18 (VAR4),
.VAR16 (VAR7));
wire VAR3;
wire VAR17;
wire [7:0] VAR15;
wire VAR45;
wire VAR1;
wire VAR40;
VAR46
.VAR11 (2),
.VAR33 (5),
.VAR24 ("VAR10"),
.VAR37 (20.833),
.VAR48 ("VAR22"),
.VAR19 ("2X"),
.VAR51 ("VAR2"),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.functional.v | 1,538 | module MODULE1 (
VAR1,
VAR3,
VAR4
);
output VAR1;
input VAR3;
input VAR4 ;
wire VAR2 ;
wire VAR9;
not VAR7 (VAR9 , VAR4 );
VAR8 VAR6 (VAR2 , VAR3, VAR9 );
and VAR5 (VAR1 , VAR2, VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_4.v | 2,463 | module MODULE2 (
VAR4 ,
VAR3,
VAR8,
VAR5 ,
VAR9 ,
VAR6,
VAR11,
VAR1 ,
VAR7
);
output VAR4 ;
input VAR3;
input VAR8;
input VAR5 ;
input VAR9 ;
input VAR6;
input VAR11;
input VAR1 ;
input VAR7 ;
VAR10 VAR2 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR7(VA... | apache-2.0 |
m-labs/milkymist | cores/asfifo/rtl/asfifo_graycounter.v | 1,307 | module MODULE1 #(
parameter VAR2 = 2
) (
output reg [VAR2-1:0] VAR4,
input VAR3,
input rst,
input clk
);
reg [VAR2-1:0] VAR1;
always @(posedge clk, posedge rst) begin
if(rst) begin
VAR1 <= {VAR2{1'b0}} + 1;
VAR4 <= {VAR2{1'b0}};
end else if(VAR3) begin
VAR1 <= VAR1 + 1;
VAR4 <= {VAR1[VAR2-1],
VAR1[VAR2-2:0] ^ VAR1[VAR2... | lgpl-3.0 |
rohit91/novena-sd-fpga | novena-sd.srcs/sources_1/imports/common/reg_wo_4burst.v | 2,837 | module MODULE1(
input wire clk,
input wire [15:0] VAR8, input wire [18:0] VAR11,
input wire [2:0] VAR15, input wire VAR19, input wire VAR18, input wire VAR10, output wire [63:0] VAR9,
output reg [15:0] VAR6, output wire VAR13 );
reg [63:0] VAR1;
reg [2:0] VAR16;
reg VAR4;
reg [15:0] VAR12;
reg VAR17;
reg [2:0] VAR2;
re... | apache-2.0 |
Sajid3/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/bootrom.v | 4,937 | module MODULE1
parameter VAR7 = 0)
(
input VAR8,
input VAR2,
input [(VAR6+2)-1:2] VAR16,
input VAR19,
input VAR11,
input [2:0] VAR18,
input [1:0] VAR13,
output reg [31:0] VAR9,
output reg VAR5);
reg [VAR6-1:0] VAR12;
always @ (posedge VAR8 or posedge VAR2)
if (VAR2)
VAR9 <= 32'h15000000;
else
case (VAR12)
default:
VAR9... | apache-2.0 |
kadircet/CENG | 232/hw5/lab_5_2_cow/Board232.v | 1,918 | module MODULE1 (
input VAR4,
input [3:0] VAR5,
input [7:0] VAR3,
output [7:0] VAR10,
output reg [6:0] VAR9,
output reg [3:0] VAR2,
output VAR6,
output [2:1] VAR12,
output [2:0] VAR8,
output [2:0] VAR1,
output VAR7,
output VAR11
);
assign VAR6 = 1'b1;
begin
end
begin
begin
begin | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_drp.v | 38,970 | module MODULE1 #
(
parameter VAR28 = "VAR38", parameter VAR11 = "3.0", parameter VAR42 = "VAR171", parameter VAR149 = "VAR129", parameter VAR83 = "VAR90", parameter VAR64 = "VAR171", parameter VAR71 = "VAR90", parameter VAR43 = 0, parameter VAR22 = 0, parameter VAR9 = 2'd1, parameter VAR203 = 5'd21
)
(
input VAR86,
inp... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | wwp/cpu.v | 1,218 | module MODULE2(VAR11, VAR1, out, sel);
input [0:127] VAR11, VAR1;
input sel;
output [0:127] out;
reg [0:127] out;
always @ (VAR11 or VAR1 or sel)
begin
out<= sel ? VAR11 : VAR1;
end endmodule
module MODULE1(VAR5,
VAR8,
VAR2, VAR3, VAR9, VAR6, VAR7, VAR10, VAR4 );
input VAR5, VAR8;
input [0:31] VAR2, VAR3; input [0:127]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai.functional.pp.v | 2,174 | module MODULE1 (
VAR5 ,
VAR14 ,
VAR13 ,
VAR8,
VAR6,
VAR12,
VAR16 ,
VAR7
);
output VAR5 ;
input VAR14 ;
input VAR13 ;
input VAR8;
input VAR6;
input VAR12;
input VAR16 ;
input VAR7 ;
wire VAR3 ;
wire VAR18 ;
wire VAR4 ;
wire VAR9;
not VAR15 (VAR3 , VAR8 );
or VAR10 (VAR18 , VAR13, VAR14 );
nand VAR17 (VAR4 , VAR3, VAR18 ... | apache-2.0 |
asicguy/gplgpu | hdl/altera_plls/clk_global.v | 6,779 | module MODULE1
(
VAR5,
VAR1,
VAR3,
VAR4) ;
input [1:0] VAR5;
input VAR1;
input [3:0] VAR3;
output VAR4;
tri0 [1:0] VAR5;
tri1 VAR1;
tri0 [3:0] VAR3;
reg [1:0] VAR9;
wire VAR6;
wire VAR10;
wire VAR2;
wire [1:0] VAR11;
wire [3:0] VAR8;
wire [1:0] VAR7; | gpl-3.0 |
8l/kestrel | 2/nexys2/uxa/ps2io/M_uxa_ps2_fifo.v | 4,190 | module MODULE1(
input [7:0] VAR1,
input VAR10,
input VAR11,
output [7:0] VAR4,
input VAR3,
output VAR9,
output VAR7,
input VAR6,
input VAR5
);
reg [7:0] VAR8[15:0];
reg [3:0] VAR2;
reg [3:0] VAR12;
assign VAR9 = (VAR12 == (VAR2-1));
assign VAR7 = ~(VAR12 == VAR2);
assign VAR4 = VAR8[VAR2];
always @(posedge VAR6) begin
... | apache-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-vc707/mig_interface_model.v | 4,169 | module MODULE1
(
input [27:0] VAR18,
input [2:0] VAR10,
input VAR5,
input [511:0] VAR13,
input VAR17,
input [63:0] VAR3,
input VAR25,
output wire [511:0] VAR21,
output wire VAR2,
output wire VAR19,
output wire VAR30,
output wire VAR32,
output reg VAR8,
output reg VAR11,
output reg VAR16,
input VAR31
);
parameter VAR34 ... | gpl-2.0 |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/Assign4/qstn2_FSM_Multiplyier/fsm_mulplier.v | 1,890 | module MODULE1(input clk,rst,VAR5,input[7:0] VAR12,VAR11,output [15:0] VAR9 ,output reg VAR16);
localparam VAR15=4'b0001,
VAR7=4'b0010,
VAR6=4'b0100,
VAR14=4'b1000;
reg [3:0] VAR2,VAR8;
reg [2:0] VAR10,VAR3;
reg [15:0] VAR1,VAR13;
reg VAR4 ;
always @(posedge clk, posedge rst)
if(rst)begin
VAR2 <= VAR15;
VAR10<= 3'b0;
V... | gpl-2.0 |
prernaa/CPUVerilog | phase1_top.v | 15,892 | module MODULE1(
input clk,
input rst
);
wire [15:0] VAR210;
wire [15:0] VAR113;
wire [15:0] VAR217;
wire [15:0] VAR222;
wire [15:0] VAR75;
wire [15:0] VAR151;
wire [3:0] VAR39;
wire VAR140;
wire [15:0] VAR10;
wire [15:0] VAR235;
wire [15:0] VAR71;
wire[3:0] VAR213;
wire VAR37;
wire VAR100;
wire [2:0] VAR76;
wire VAR50;... | mit |
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