repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPCG_Toggle_bCMD_manager.v | 7,984 | module MODULE1
(
parameter VAR32 = 4
)
(
VAR4 ,
VAR21 ,
VAR13 ,
VAR24 ,
VAR16 ,
VAR20 ,
VAR33 ,
VAR30 ,
VAR17 ,
VAR14 ,
VAR6 ,
VAR23 ,
VAR10 ,
VAR2 ,
VAR15 ,
VAR19 ,
VAR5 ,
VAR22 ,
VAR25 ,
VAR28
);
input VAR4 ;
input VAR21 ;
input [VAR32 - 1:0] VAR13 ;
input VAR24 ;
input VAR16 ;
input VAR20 ;
input VAR33 ;
input VAR30... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.blackbox.v | 1,375 | module MODULE1 (
VAR2 ,
VAR10,
VAR7,
VAR6,
VAR1,
VAR9
);
output VAR2 ;
input VAR10;
input VAR7;
input VAR6;
input VAR1;
input VAR9;
supply1 VAR4;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
freecores/zet86 | rtl-model/regfile.v | 3,125 | module MODULE1 (
output [15:0] VAR25,
output [15:0] VAR6,
output [15:0] VAR12,
output [15:0] VAR30,
output [15:0] VAR20,
output [15:0] VAR15,
output [15:0] VAR11,
output [15:0] VAR4,
output [15:0] VAR18,
output [15:0] VAR24,
input [31:0] VAR21,
output [15:0] VAR27,
output reg [8:0] VAR7,
input wr,
input VAR26,
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufbuf/sky130_fd_sc_hd__bufbuf.behavioral.pp.v | 1,768 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR7,
VAR12,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR11 ;
input VAR7;
input VAR12;
input VAR2 ;
input VAR8 ;
wire VAR4 ;
wire VAR6;
buf VAR1 (VAR4 , VAR11 );
VAR10 VAR5 (VAR6, VAR4, VAR7, VAR12);
buf VAR9 (VAR3 , VAR6 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_fast_cfg_init_cntr.v | 3,209 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR2 = 8'hA5,
parameter VAR1 = 1
) (
input clk,
input rst,
output reg [VAR4-1:0] VAR3
);
always @(posedge clk) begin
if(rst) begin
end else begin
if(VAR3 != VAR2) begin
end
end
end
endmodule | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Design-of-various-multiplier-Array-Booth-Wallace--master/Booth multiplier/Booth multiplier.v | 5,499 | module MODULE1(VAR72,VAR24,VAR81);
input [7:0] VAR72,VAR24;
output [15:0] VAR81;
wire [7:0] VAR47,VAR86,VAR120,VAR28,VAR124,VAR79,VAR39,VAR63;
wire [9:0] VAR84,VAR71,VAR94;
wire [7:0] VAR51;
wire [3:0] VAR42,VAR25,VAR69;
wire [10:0] VAR85,VAR96;
wire [8:0] VAR110,VAR103;
wire [9:0] VAR83;
wire [11:0] VAR60;
wire [3:0] ... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/ecc/mig_7series_v1_8_ecc_buf.v | 6,293 | module MODULE1
parameter VAR48 = 100,
parameter VAR27 = 64,
parameter VAR28 = 4,
parameter VAR4 = 1,
parameter VAR32 = 64,
parameter VAR1 = 4
)
(
VAR6,
clk, rst, VAR40, VAR10, VAR17,
VAR11, VAR43, VAR8
);
input clk;
input rst;
input [VAR28-1:0] VAR40;
input [VAR4-1:0] VAR10;
wire [4:0] VAR23;
input [VAR28-1:0] VAR17;
i... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_4.behavioral.pp.v | 1,383 | module MODULE1( VAR2, VAR7, VAR1, VAR3, VAR5, VAR8, VAR9 );
input VAR3, VAR1, VAR7, VAR2;
inout VAR8, VAR9;
output VAR5;
VAR6 VAR10(.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR9(VAR9));
VAR6 VAR4(.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR9(VAR9)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.v | 2,312 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR5,
VAR2 ,
VAR1 ,
VAR4 ,
VAR10
);
output VAR9 ;
output VAR6 ;
input VAR7 ;
input VAR5;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR10 ;
VAR8 VAR3 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10)
);
endmodule
module MOD... | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_vdiv.v | 3,459 | module MODULE1(
input VAR24,
input VAR11,
output VAR41,
input VAR19,
output reg VAR43,
input signed [17:0] VAR38,
input signed [17:0] VAR39,
input signed [17:0] VAR20,
input signed [17:0] VAR52,
input VAR17,
input [16:0] VAR35,
input VAR8,
input [16:0] VAR44,
input VAR22,
input [16:0] VAR16,
input VAR3,
input [16:0] VA... | lgpl-3.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/crc_7/crc_7.v | 2,871 | module MODULE1(VAR7, clk, rst, VAR9, VAR6, VAR16);
input VAR7;
input clk;
input rst;
input [VAR4-1:0] VAR9;
output [VAR13:0] VAR6;
output VAR16;
localparam VAR4 = 32, VAR13 = 7;
localparam VAR5 = 8'b10001001 ;
reg VAR17; reg [VAR4-1:0] VAR10; reg [VAR13:0] VAR11; VAR1 VAR17 = 1'b0;
localparam VAR3 = 3'd0, VAR8 = 3'd1, ... | mit |
nyaxt/dmix | ringbuf.v | 1,030 | module MODULE1
parameter VAR11 = 16,
parameter VAR2 = 4,
parameter VAR5 = VAR11/2
)(
input wire clk,
input wire rst,
input wire [23:0] VAR10,
input wire VAR7,
input wire VAR4,
input wire [(VAR2-1):0] VAR1,
output wire [23:0] VAR13);
reg [23:0] VAR3 [(VAR11-1):0];
reg [(VAR2-1):0] VAR8;
always @(posedge clk) begin
if(rs... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/cpc_clks/cpc_clks_0002.v | 2,269 | module MODULE1(
input wire VAR72,
input wire rst,
output wire VAR3,
output wire VAR52,
output wire VAR48,
output wire VAR59,
output wire VAR42
);
VAR43 #(
.VAR19("true"),
.VAR30("50.0 VAR65"),
.VAR70("VAR44"),
.VAR4(4),
.VAR14("48.000000 VAR65"),
.VAR64("0 VAR25"),
.VAR17(50),
.VAR69("16.000000 VAR65"),
.VAR8("0 VAR25"... | gpl-3.0 |
cfelton/minnesota | mn/cores/usbext/fpgalink/comm_fpga_fx2_v1_stub.v | 1,721 | module MODULE1 (
VAR10,
VAR17,
VAR15,
VAR19,
VAR18,
VAR13,
VAR4,
VAR1,
VAR12,
VAR8,
VAR7,
VAR11,
VAR5,
VAR14,
VAR9,
VAR6,
VAR2,
VAR16
);
input VAR10;
input VAR17;
output VAR15;
reg VAR15;
input [7:0] VAR19;
output [7:0] VAR18;
reg [7:0] VAR18;
output VAR13;
reg VAR13;
output VAR4;
reg VAR4;
input VAR1;
output VAR12;
re... | gpl-3.0 |
antmicro/yosys | techlibs/greenpak4/cells_map.v | 5,298 | module MODULE1(input VAR35, VAR47, VAR40, output reg VAR42);
parameter [0:0] VAR21 = 1'VAR41;
VAR4 #(
.VAR21(VAR21),
.VAR36(1'b1),
) VAR12 (
.VAR35(VAR35),
.VAR47(VAR47),
.VAR15(VAR40),
.VAR42(VAR42)
);
endmodule
module MODULE7(input VAR35, VAR47, VAR30, output reg VAR42);
parameter [0:0] VAR21 = 1'VAR41;
VAR4 #(
.VAR2... | isc |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_switches.v | 1,839 | module MODULE1 (
address,
clk,
VAR6,
VAR4,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR6;
input VAR4;
wire VAR1;
wire [ 7: 0] VAR5;
wire [ 7: 0] VAR3;
reg [ 31: 0] VAR2;
assign VAR1 = 1;
assign VAR3 = {8 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (VAR4... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.symbol.v | 1,283 | module MODULE1 (
input VAR5,
output VAR1
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/ram.v | 1,654 | module MODULE1 #(
parameter VAR11 = 198,
parameter VAR2 = 6
) (
input clk,
input wire VAR4,
input wire [VAR2-1:0] VAR14,
input wire [VAR11-1:0] VAR10,
output reg [VAR11-1:0] VAR7,
input wire VAR13,
input wire [VAR2-1:0] VAR8,
input wire [VAR11-1:0] VAR6,
output reg [VAR11-1:0] VAR9
);
reg [VAR11-1:0] VAR5 [(2**VAR2)-1:... | apache-2.0 |
alanachtenberg/CSCE-350 | Lab 7/lab7_5.v | 5,260 | module MODULE2(VAR29, VAR22, VAR59, VAR23, VAR2, VAR47, VAR38);
input VAR23, VAR59, VAR2, VAR47, VAR38;
output VAR29, VAR22;
wire VAR17;
wire VAR53, VAR12;
wire VAR8, VAR10;
wire VAR52, VAR57;
wire VAR51, VAR42;
and (VAR17, VAR38, VAR59);
not (VAR53, VAR23);
not (VAR12, VAR17);
nand VAR13(VAR8,VAR17, VAR23);
nand VAR24... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o.pp.symbol.v | 1,352 | module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR3 ,
output VAR1 ,
input VAR4 ,
input VAR7,
input VAR2,
input VAR8
);
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build3/umult8.v | 1,138 | module MODULE1(VAR3, VAR2, VAR7);
input [0:7] VAR3, VAR2;
output [0:15] VAR7;
reg [0:15] VAR5;
reg [0:15] VAR6;
reg [0:15] VAR1;
reg [0:15] VAR7;
integer VAR4;
always @ (VAR3 or VAR2)
begin
VAR5=16'b0;
VAR6=16'b0;
VAR1=16'b0;
VAR6={{8{1'b0}},VAR2[0:7]};
VAR5={{8{1'b0}},VAR3[0:7]};
for (VAR4=15; VAR4>7; VAR4=VAR4-1)
beg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.behavioral.v | 1,375 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR4 ;
input VAR6;
supply1 VAR5;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR3 ;
or VAR2 (VAR7 , VAR4, VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.functional.pp.v | 2,245 | module MODULE1 (
VAR4 ,
VAR7,
VAR3,
VAR11 ,
VAR2 ,
VAR15,
VAR13,
VAR8 ,
VAR9
);
output VAR4 ;
input VAR7;
input VAR3;
input VAR11 ;
input VAR2 ;
input VAR15;
input VAR13;
input VAR8 ;
input VAR9 ;
wire VAR12 ;
wire VAR14 ;
wire VAR16 ;
wire VAR6;
and VAR1 (VAR12 , VAR11, VAR2 );
nor VAR5 (VAR14 , VAR7, VAR3 );
nor VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b_4.v | 2,147 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR9 ,
VAR8,
VAR7,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR5 ;
input VAR9 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR3 ;
VAR6 VAR2 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1 ,
VAR5,
VAR9
);
output VAR1 ... | apache-2.0 |
sabertazimi/open-hust-verilog | regfile.v | 1,624 | module MODULE1
(
input clk,
input rst,
input VAR6,
input [4:0] VAR12,
input [4:0] VAR1,
input [4:0] VAR13,
input [VAR8-1:0] VAR2,
output [VAR8-1:0] VAR7,
output [VAR8-1:0] VAR5,
output [VAR8-1:0] VAR10,
output [VAR8-1:0] VAR3
);
reg [4:0] VAR9;
reg [VAR8-1:0] MODULE1 [0:31];
always @ (posedge clk) begin
if (rst) begin
... | mit |
travisg/cpu | rtl/cpu/alu.v | 1,902 | module MODULE1(
input [3:0] VAR3,
input [31:0] VAR5,
input [31:0] VAR2,
output reg [31:0] VAR1
);
always @(VAR3 or VAR5 or VAR2)
begin
case (VAR3)
default: VAR1 = 32'VAR4;
endcase
end
endmodule | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v | 20,180 | module MODULE1 #
(
parameter VAR41 = 100,
parameter VAR23 = 256,
parameter VAR19 = 5,
parameter VAR34 = "VAR57",
parameter VAR11 = 2 ,
parameter VAR59 = "VAR35"
)
(
VAR20, VAR2, VAR9, VAR65,
VAR52, VAR80, VAR81, VAR63,
VAR84,
rst, clk, VAR88, VAR16, VAR17, VAR50,
VAR86, VAR101, VAR103, VAR43
);
input rst;
input clk;
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o.pp.symbol.v | 1,401 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR10 ,
input VAR3 ,
input VAR4 ,
output VAR6 ,
input VAR7 ,
input VAR1,
input VAR9,
input VAR5
);
endmodule | apache-2.0 |
donnaware/TabX1 | rtl/tabx1/lcd1.v | 24,686 | module MODULE1 (
input VAR66, input VAR59, input reset,
input [ 7:0] VAR82, output reg [ 7:0] VAR25,
input [19:0] VAR33, input VAR52, input VAR40, output VAR92,
inout reg [ 7:0] VAR42, output reg [11:0] VAR86, output reg VAR36, output reg VAR28, output reg VAR93,
output [ 5:0] VAR60, output [ 5:0] VAR65, output [ 5:0] ... | gpl-3.0 |
parallella/oh | common/hdl/oh_iobuf.v | 1,446 | module MODULE1 #(parameter VAR3 = 1, parameter VAR7 = "VAR5" )
(
inout VAR13, inout VAR15, inout VAR16, input VAR10, input VAR17, input VAR4, input [3:0] VAR8, input [VAR3-1:0] VAR2, input [VAR3-1:0] VAR6, output [VAR3-1:0] out, input [VAR3-1:0] in, inout [VAR3-1:0] VAR11
);
genvar VAR18;
for (VAR18 = 0; VAR18 < VAR3; ... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/acl_fp_fabs.v | 4,748 | module MODULE1
(
VAR2,
VAR4,
VAR5,
VAR8) ;
input VAR2;
input VAR4;
input [31:0] VAR5;
output [31:0] VAR8;
tri1 VAR2;
tri0 VAR4;
reg [30:0] VAR7;
wire VAR6;
wire [31:0] VAR3;
wire VAR1; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.v | 2,358 | module MODULE1 (
VAR10 ,
VAR6,
VAR8 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR1
);
output VAR10 ;
input VAR6;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
VAR4 VAR2 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
qeedquan/fpga | de2-115/vgadla/vgadla.v | 6,458 | module MODULE1
(
input wire VAR38,
input wire [3:0] VAR20,
input wire [17:0] VAR32,
inout wire [15:0] VAR5,
output wire [19:0] VAR12,
output wire VAR21,
output wire VAR57,
output wire VAR16,
output wire VAR15,
output wire VAR35,
output wire VAR26,
output wire VAR56,
output wire VAR52,
output wire VAR24,
output wire VAR... | mit |
chriswynnyk/american-put-verilog | american_put_stratix/src/mem_1k.v | 9,473 | module MODULE1 (
VAR46,
VAR2,
VAR30,
VAR21,
VAR6,
VAR37,
VAR20);
input [63:0] VAR46;
input [9:0] VAR2;
input VAR30;
input [9:0] VAR21;
input VAR6;
input VAR37;
output [63:0] VAR20;
tri1 VAR37;
wire [63:0] VAR44;
wire [63:0] VAR20 = VAR44[63:0];
VAR10 VAR28 (
.VAR57 (VAR37),
.VAR35 (VAR6),
.VAR43 (VAR30),
.VAR18 (VAR21)... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_xcvr_rx_if.v | 3,062 | module MODULE1 (
input VAR6,
input [ 3:0] VAR8,
input [31:0] VAR7,
output reg VAR2,
output reg [31:0] VAR4);
reg [31:0] VAR3 = 'd0;
reg [ 3:0] VAR5 = 'd0;
reg [ 3:0] VAR1 = 'd0;
always @(posedge VAR6) begin
VAR3 <= VAR7;
VAR1 <= VAR8;
if (VAR8 != 4'h0) begin
VAR5 <= VAR8;
end
VAR2 <= |VAR1;
if (VAR5[0] == 1'b1) begin
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4b/sky130_fd_sc_hs__or4b.pp.blackbox.v | 1,282 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR1,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR1;
input VAR6;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab3/array_io_prj/solution4/syn/verilog/array_io.v | 66,193 | module MODULE1 (
VAR19,
VAR61,
VAR266,
VAR311,
VAR59,
VAR44,
VAR262,
VAR228,
VAR247,
VAR98,
VAR110,
VAR249,
VAR123,
VAR196,
VAR195,
VAR36,
VAR52,
VAR317,
VAR126,
VAR67,
VAR182,
VAR50,
VAR269,
VAR112,
VAR45,
VAR326,
VAR82,
VAR205,
VAR117,
VAR261,
VAR179,
VAR216,
VAR193,
VAR4,
VAR174,
VAR162,
VAR103,
VAR288,
VAR135,
VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3/sky130_fd_sc_hs__nand3_1.v | 2,048 | module MODULE2 (
VAR5 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR3,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR1;
VAR7 VAR8 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR4,
VAR2,
VAR6
);
output VAR5;
input VAR4;
input VAR2;
in... | apache-2.0 |
skarpenko/ultiparc | rtl/src/intr_controller.v | 4,508 | module MODULE1(
clk,
VAR11,
VAR14,
VAR1,
VAR20,
VAR10,
VAR19,
VAR5,
VAR12,
VAR8,
VAR2
);
localparam [VAR15-1:0] VAR18 = 32'h000;
localparam [VAR15-1:0] VAR6 = 32'h004;
localparam [VAR15-1:0] VAR13 = 32'h008;
input wire clk;
input wire VAR11;
input wire [31:0] VAR14;
output wire VAR1;
input wire [VAR15-1:0] VAR20;
input... | bsd-2-clause |
chriz2600/DreamcastHDMI | Core/source/filter/output_data.v | 2,267 | module MODULE1(
input VAR19,
input VAR11,
input VAR1,
input VAR4,
input VAR10,
input VAR17,
input [8:0] VAR14,
input [23:0] VAR6,
output reg [23:0] VAR16
);
localparam VAR7 = 9'd256;
localparam VAR13 = VAR13;
localparam VAR13 = 9'd64;
reg [23:0] VAR2;
reg [8:0] VAR22;
wire [23:0] VAR15;
VAR3 VAR18 (
.VAR19(VAR19),
.VAR... | mit |
merckhung/zet | cores/gpio/rtl/sw_leds.v | 2,337 | module MODULE1 (
input VAR1,
input VAR14,
input VAR9,
output [15:0] VAR7,
input [15:0] VAR4,
input [ 1:0] VAR13,
input VAR18,
input VAR15,
input VAR2,
output VAR16,
output reg [13:0] VAR5,
input [ 7:0] VAR19,
input VAR17,
input VAR20,
output reg VAR8
);
wire VAR3;
reg VAR10;
reg VAR6;
reg VAR11;
reg [2:0] VAR12;
assign... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/buffers/RxFifoBI.v | 5,448 | module MODULE1 (
address,
VAR9,
VAR15,
VAR1,
VAR17,
VAR6,
VAR7,
VAR19,
VAR11,
VAR5,
VAR12,
VAR3,
VAR14,
VAR4
);
input [2:0] address;
input VAR9;
input VAR15;
input VAR1;
input VAR17;
input VAR6;
input [7:0] VAR19;
input [7:0] VAR11;
output [7:0] VAR5;
output VAR12;
output VAR3;
output VAR14;
input [15:0] VAR4;
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22oi/sky130_fd_sc_hvl__a22oi.functional.pp.v | 2,175 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR11,
VAR17,
VAR15 ,
VAR10
);
output VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR11;
input VAR17;
input VAR15 ;
input VAR10 ;
wire VAR6 ;
wire VAR18 ;
wire VAR19 ;
wire VAR13;
nand VAR16 (VAR6 , VAR7, VAR9 );
nand VAR14 (VAR18 , VAR1, VAR8 );
... | apache-2.0 |
asicguy/gplgpu | hdl/vga/crt_reg_dec.v | 8,210 | module MODULE1
(
input VAR29,
input VAR47,
input VAR31,
input VAR16,
input VAR42,
input VAR17,
input VAR7, input VAR23,
input VAR35,
input VAR19,
input VAR40,
input VAR36,
input [15:0] VAR25,
input [15:0] VAR11,
output [7:0] VAR43, output reg [7:0] VAR39, output VAR6, output VAR45,
output [3:0] VAR24,
output VAR37,
out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp.functional.v | 1,645 | module MODULE1 (
VAR11,
VAR6,
VAR4,
VAR3,
VAR2
);
input VAR11;
input VAR6;
output VAR4;
input VAR3;
input VAR2 ;
wire VAR9 ;
wire VAR8 ;
wire VAR5 ;
wire VAR12;
not VAR13 (VAR8 , VAR2 );
VAR7 VAR10 (VAR9 , VAR3, VAR8, VAR11, VAR6);
and VAR1 (VAR4 , VAR9, VAR2 );
endmodule | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_2_OC/SingleCycleCPUOnBoard/single_cycle_cpu_display.v | 5,353 | module MODULE1(
input clk,
input VAR27,
input VAR17,
output VAR10,
output VAR3,
output VAR37,
output VAR39,
output VAR26,
inout[15:0] VAR8,
output VAR40,
inout VAR41,
inout VAR28,
output VAR35,
output VAR23
);
wire VAR18; reg VAR11;
reg VAR5;
always @(posedge clk)
begin
if (!VAR27)
begin
VAR11<= 1'b0;
end
else
begin
VA... | mit |
hanw/sonic-lite | hw/verilog/si570/clock_divider.v | 2,231 | module MODULE1(
VAR4,
VAR2,
VAR1,
);
input VAR4;
input VAR2;
output VAR1;
reg [VAR5-1:0] VAR3;
always@(posedge VAR4 or negedge VAR2)
begin
if (!VAR2)
VAR3 <= 0;
end
else
VAR3 <= VAR3 + 1;
end
assign VAR1 = VAR3[VAR5-1];
endmodule | mit |
jas0n1ee/THU-DSD | FB/epcs_flash_controller.v | 17,705 | module MODULE3 (
VAR1,
clk,
VAR76,
VAR94,
VAR49,
VAR40,
VAR64,
VAR44,
VAR60,
VAR27,
VAR6,
VAR73,
VAR25,
VAR18,
irq,
VAR31
)
;
output VAR60;
output VAR27;
output VAR6;
output [ 15: 0] VAR73;
output VAR25;
output VAR18;
output irq;
output VAR31;
input VAR1;
input clk;
input [ 15: 0] VAR76;
input VAR94;
input [ 2: 0] VAR4... | mit |
theHawke/real-dcpu | ALU/shift16.v | 3,948 | module MODULE1 (
VAR12,
VAR17,
VAR6,
VAR1);
input [31:0] VAR12;
input VAR17;
input [3:0] VAR6;
output [31:0] VAR1;
wire [31:0] VAR18;
wire [31:0] VAR1 = VAR18[31:0];
VAR4 VAR5 (
.VAR12 (VAR12),
.VAR17 (VAR17),
.VAR6 (VAR6),
.VAR1 (VAR18)
,
.VAR7 (),
.VAR8 (),
.VAR3 (),
.VAR9 (),
.VAR14 ()
);
VAR5.VAR2 = "VAR10",
VAR5.... | gpl-2.0 |
cpulabs/mist1032isa | src/lib/mist1032isa_async_fifo.v | 3,801 | module MODULE1
parameter VAR25 = 16,
parameter VAR13 = 4,
parameter VAR3 = 2
)
(
input wire VAR23,
input wire VAR11,
input wire VAR16,
input wire VAR2,
input wire [VAR25-1:0] VAR12,
output wire VAR33,
input wire VAR22,
input wire VAR9,
output wire [VAR25-1:0] VAR14,
output wire VAR15
);
wire [VAR3:0] VAR18;
wire VAR26;... | bsd-2-clause |
olajep/oh | src/adi/hdl/library/common/up_dac_common.v | 15,322 | module MODULE1 #(
parameter VAR6 = 0,
parameter VAR24 = 0,
parameter VAR72 = 1'b0,
parameter VAR47 = 6'h10,
parameter VAR13 = 0,
parameter VAR69 = 0,
parameter VAR111 = 0) (
output VAR25,
input VAR105,
output VAR65,
output VAR40,
output VAR103,
output VAR95,
output VAR56,
output VAR109,
output VAR38,
output VAR90,
outp... | mit |
gbraad/minimig-de1 | rtl/ctrl/ctrl_boot.v | 6,711 | module MODULE1 (
address,
VAR33,
VAR17);
input [10:0] address;
input VAR33;
output [31:0] VAR17;
tri1 VAR33;
wire [31:0] VAR9;
wire [31:0] VAR17 = VAR9[31:0];
VAR52 VAR8 (
.VAR22 (address),
.VAR49 (VAR33),
.VAR55 (VAR9),
.VAR37 (1'b0),
.VAR21 (1'b0),
.VAR51 (1'b1),
.VAR18 (1'b0),
.VAR4 (1'b0),
.VAR5 (1'b1),
.VAR27 (1'b... | gpl-3.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_0/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_carry_and.v | 4,336 | module MODULE1 #
(
parameter VAR4 = "VAR3"
)
(
input wire VAR9,
input wire VAR8,
output wire VAR10
);
generate
if ( VAR4 == "VAR1" ) begin : VAR2
assign VAR10 = VAR9 & VAR8;
end else begin : VAR7
VAR5 VAR6
(
.VAR12 (VAR10),
.VAR13 (VAR9),
.VAR11 (1'b0),
.VAR8 (VAR8)
);
end
endgenerate
endmodule | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0/bd_0/ip/ip_6/synth/bd_350b_slot_0_r_0.v | 4,558 | module MODULE1 (
VAR39,
VAR42,
dout
);
input wire [0 : 0] VAR39;
input wire [0 : 0] VAR42;
output wire [1 : 0] dout;
VAR57 #(
.VAR69(1),
.VAR36(1),
.VAR67(1),
.VAR15(1),
.VAR24(1),
.VAR2(1),
.VAR18(1),
.VAR38(1),
.VAR26(1),
.VAR62(1),
.VAR66(1),
.VAR11(1),
.VAR14(1),
.VAR10(1),
.VAR6(1),
.VAR13(1),
.VAR19(1),
.VAR51(1)... | mit |
tugrulyatagan/RISC-processor | xilinx_processor/control_unit.v | 8,853 | module MODULE1(
input [15:0] VAR13,
output reg [2:0] VAR10,
output reg [2:0] VAR19,
output reg [2:0] VAR6,
output reg VAR5,
output reg VAR7,
output reg [7:0] VAR2,
output reg [15:0] VAR1,
output reg VAR11,
output reg VAR17,
output reg VAR18,
output reg [3:0] VAR16,
output reg VAR4,
output reg VAR8,
output reg VAR12
);
... | gpl-2.0 |
skalldri/mips-verilog | fetch-decode/fetch.v | 1,114 | module MODULE1 (clk, VAR11, VAR13, VAR5, VAR12, VAR4, enable, VAR6, VAR2, VAR9, VAR10);
parameter VAR3 = 32'h80020000;
input clk;
input VAR11;
input VAR13;
input [31:0] VAR6;
input VAR2;
input [31:0] VAR9;
input VAR10;
output [31:0] VAR5;
output [2:0] VAR4;
output VAR12; output enable;
reg [31:0] VAR8 = 32'h8001FFFC; r... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.behavioral.v | 1,921 | module MODULE1 (
VAR5 ,
VAR13 ,
VAR1 ,
VAR9 ,
VAR15,
VAR14
);
output VAR5 ;
input VAR13 ;
input VAR1 ;
input VAR9 ;
input VAR15;
input VAR14;
wire VAR6 ;
reg VAR3 ;
wire VAR11 ;
wire VAR16 ;
wire VAR7;
wire VAR10 ;
wire VAR4 ;
VAR8 VAR2 (VAR6 , VAR11, VAR7, VAR16, VAR3, VAR15, VAR14);
assign VAR10 = ( VAR15 === 1'b1 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b_lp.v | 2,237 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR7,
VAR10,
VAR5 ,
VAR6
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR7;
input VAR10;
input VAR5 ;
input VAR6 ;
VAR1 VAR2 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/mcm00.v | 3,125 | module MODULE1(
clk,
rst,
VAR2,
VAR11,
VAR14,
VAR15,
VAR10,
o0,
o1,
o2,
o3
);
input clk;
input rst;
input VAR2;
input signed [19:0] VAR11;
input signed [19:0] VAR14;
input signed [19:0] VAR15;
input signed [19:0] VAR10;
output reg signed [19+7+1:0] o0;
output reg signed [19+7+1:0] o1;
output reg signed [19+7+1:0] o2;
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1.symbol.v | 1,207 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/yacc/mul_div_module5.v | 8,683 | module MODULE1(VAR17,VAR20,VAR38,VAR4,VAR18,VAR47,VAR41,VAR16,state,VAR5,VAR31,VAR3);
parameter VAR6=16; parameter VAR34=2;
parameter VAR6=1; parameter VAR34=32; VAR2
parameter VAR6=16; parameter VAR34=2;
parameter VAR6=16; parameter VAR34=2; else
parameter VAR6=1; parameter VAR34=32; VAR2
input VAR17,VAR20;
input [31:... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mm_interconnect_0_avalon_st_adapter.v | 6,146 | module MODULE1 #(
parameter VAR13 = 34,
parameter VAR21 = 0,
parameter VAR3 = 34,
parameter VAR2 = 0,
parameter VAR16 = 0,
parameter VAR23 = 0,
parameter VAR24 = 1,
parameter VAR8 = 1,
parameter VAR5 = 0,
parameter VAR19 = 34,
parameter VAR17 = 0,
parameter VAR25 = 1,
parameter VAR9 = 0,
parameter VAR10 = 1,
parameter ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/inv/sky130_fd_sc_hd__inv_6.v | 1,995 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR6,
VAR1,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR4 ;
VAR2 VAR8 (
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR6;
supply0 VAR1;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrbp/sky130_fd_sc_hvl__dfrbp.pp.symbol.v | 1,434 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR8 ,
input VAR5,
input VAR9 ,
input VAR1 ,
input VAR2 ,
input VAR6 ,
input VAR7
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.functional.v | 1,909 | module MODULE1( VAR2, VAR9, VAR3, VAR13, VAR20, VAR10, VAR17 );
input VAR10, VAR17, VAR13, VAR20, VAR9, VAR3;
output VAR2;
wire VAR14;
not VAR5( VAR14, VAR10 );
wire VAR16;
not VAR23( VAR16, VAR17 );
wire VAR25;
and VAR7( VAR25, VAR14, VAR16 );
wire VAR15;
not VAR18( VAR15, VAR13 );
wire VAR22;
not VAR24( VAR22, VAR20 ... | apache-2.0 |
siamumar/TinyGarbled | circuit_synthesis/aes/KeyExpansionSeq.v | 1,309 | module MODULE1
(
VAR18,
counter,
VAR16
);
localparam VAR5 = 10;
input [127:0] VAR18;
input [3:0] counter;
output [127:0] VAR16;
wire [31:0] VAR10[3:0];
wire [31:0] VAR9[3:0];
wire [31:0] VAR12;
wire [7:0] VAR6[VAR5:0];
wire [31:0] VAR17;
wire [31:0] VAR2;
wire [95:0] VAR13;
assign VAR6[0] = 8'h01;
assign VAR6[1] = 8'h0... | gpl-3.0 |
ElegantLin/My-CPU | Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/div.v | 4,942 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR1,
input wire[31:0] VAR19,
input wire[31:0] VAR8,
input wire VAR4,
input wire VAR18,
output reg[63:0] VAR15,
output reg VAR22
);
wire[32:0] VAR5;
reg[5:0] VAR13;
reg[64:0] VAR21;
reg[1:0] state;
reg[31:0] VAR7;
reg[31:0] VAR9;
reg[31:0] VAR6;
assign VAR5 = {... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_4.v | 2,345 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR10,
VAR2,
VAR5 ,
VAR6
);
output VAR8 ;
input VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR10;
input VAR2;
input VAR5 ;
input VAR6 ;
VAR11 VAR7 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR... | apache-2.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/Barrel_shifter.v | 1,323 | module MODULE1#(parameter VAR7=26, parameter VAR15=5)(
input wire clk,
input wire rst,
input wire VAR11,
input wire [VAR15-1:0] VAR4,
input wire [VAR7-1:0] VAR5,
input wire VAR14,
input wire VAR3,
output wire [VAR7-1:0] VAR10
);
wire [VAR7-1:0] VAR9;
VAR17 #(.VAR7(VAR7),.VAR15(VAR15)) VAR17(
.clk(clk),
.rst(rst),
.VAR1... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/vg93/fapch_counter.v | 1,697 | module MODULE1
(
input wire VAR2,
input wire VAR6,
output reg VAR4,
output reg VAR8
);
reg [4:0] VAR5;
reg VAR10, VAR3;
wire VAR11;
wire VAR9;
reg [3:0] VAR7;
wire VAR12;
reg [5:0] VAR1;
always @(posedge VAR2)
VAR5[4:0] <= { VAR5[3:0], (~VAR6) };
always @(posedge VAR2)
begin
if( VAR5[4:1]==4'b1111 ) VAR10 <= 1'b1;
end
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah.symbol.v | 1,296 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
output VAR8,
output VAR7
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.behavioral.v | 1,361 | module MODULE1 (
VAR11,
VAR3,
VAR8,
VAR1
);
output VAR11;
input VAR3;
input VAR8;
input VAR1;
supply1 VAR6;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR5 ;
wire VAR10;
or VAR7 (VAR10, VAR8, VAR3, VAR1 );
buf VAR2 (VAR11 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi.functional.pp.v | 2,070 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR9 ,
VAR14 ,
VAR3 ,
VAR13 ,
VAR8,
VAR15,
VAR16 ,
VAR2
);
output VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR14 ;
input VAR3 ;
input VAR13 ;
input VAR8;
input VAR15;
input VAR16 ;
input VAR2 ;
wire VAR18 ;
wire VAR17 ;
wire VAR5;
and VAR11 (VAR18 , VAR10, VAR9, VAR14, VAR3 );
nor VAR6 (V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/source/cmm_errman_ram8x26.v | 4,629 | module MODULE1 (
VAR2,
VAR4, VAR6,
VAR7,
VAR8,
rst,
clk
);
output [49:0] VAR2;
input [49:0] VAR4;
input [2:0] VAR6;
input [2:0] VAR7;
input VAR8;
input rst;
input clk;
reg [49:0] VAR5 [0:7];
always @(posedge clk) begin
if (VAR8)
VAR5[VAR6] <= #VAR3 VAR4;
end
reg [49:0] VAR1;
always @(posedge clk or posedge rst)
begin
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.functional.v | 1,545 | module MODULE1 (
VAR1 ,
VAR10,
VAR7,
VAR9,
VAR3
);
output VAR1 ;
input VAR10;
input VAR7;
input VAR9;
input VAR3;
wire VAR6 ;
wire VAR12 ;
wire VAR5;
nand VAR2 (VAR6 , VAR7, VAR10 );
nand VAR11 (VAR12 , VAR3, VAR9 );
and VAR4 (VAR5, VAR6, VAR12);
buf VAR8 (VAR1 , VAR5 );
endmodule | apache-2.0 |
Mw1993/5CPipelinedCPU | data_mem.v | 1,037 | module MODULE1(clk,addr,VAR5,VAR2,VAR4,VAR3);
input clk;
input [15:0] addr;
input VAR5; input VAR2; input [15:0] VAR4;
output reg [15:0] VAR3;
reg [15:0]VAR1[0:65535];
always @(addr,VAR5,clk)
if (~clk && VAR5 && ~VAR2)
VAR3 <= VAR1[addr];
always @(addr,VAR2,clk)
if (~clk && VAR2 && ~VAR5)
VAR1[addr] <= VAR4;
endmodule | gpl-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/spi_slave_rxq.v | 2,717 | module MODULE1
(input VAR16,
input VAR56, input VAR36, input VAR43,
output [7:0] VAR62, output VAR7, output VAR67);
wire [7:0] VAR21;
wire VAR63, VAR14;
VAR61 VAR51
(.clk(VAR16), .VAR56(VAR56), .VAR36(VAR36), .VAR43(VAR43),
.VAR62(VAR21), .VAR7(VAR63), .VAR67(VAR14));
wire VAR2, VAR68;
wire [7:0] VAR26;
wire [7:0] VAR3... | apache-2.0 |
kramble/FPGA-Litecoin-Miner | ICARUS-LX150/ltcminer_icarus.v | 11,847 | module MODULE1 (VAR43, VAR76, VAR31, VAR112, VAR13, VAR15, VAR95, VAR32, VAR16, VAR2);
function integer VAR34; input integer VAR70;
begin
VAR70 = VAR70-1;
for (VAR34=0; VAR70>0; VAR34=VAR34+1)
VAR70 = VAR70>>1;
end
endfunction
parameter VAR10 = VAR10;
parameter VAR10 = 25; VAR77
parameter VAR104 = VAR104; else
paramete... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/bd_0/ip/ip_2/synth/bd_c3fe_slot_0_aw_0.v | 4,561 | module MODULE1 (
VAR35,
VAR55,
dout
);
input wire [0 : 0] VAR35;
input wire [0 : 0] VAR55;
output wire [1 : 0] dout;
VAR23 #(
.VAR14(1),
.VAR68(1),
.VAR26(1),
.VAR7(1),
.VAR39(1),
.VAR47(1),
.VAR64(1),
.VAR5(1),
.VAR51(1),
.VAR4(1),
.VAR52(1),
.VAR66(1),
.VAR69(1),
.VAR6(1),
.VAR3(1),
.VAR8(1),
.VAR58(1),
.VAR15(1),
.V... | mit |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/bfm_apbtoapb.v | 6,187 | module MODULE1 ( VAR25, VAR16, VAR4, VAR21, VAR27, VAR12, VAR39, VAR37, VAR8,
VAR33, VAR19, VAR29, VAR28, VAR34, VAR40, VAR13, VAR3, VAR24);
parameter[9:0] VAR36 = 1;
localparam VAR5 = VAR36 * 1;
input VAR25;
input VAR16;
input[31:0] VAR4;
input VAR21;
input VAR27;
input[31:0] VAR12;
output[31:0] VAR39;
reg[31:0] VAR39... | mit |
mbus/mbus | mbus/verilog/no_pwr_gating_ben/mbus_wire_ctrl_Ben.v | 1,781 | module MODULE1(
input VAR4,
input VAR9,
input VAR11,
input VAR5,
input VAR7,
input VAR10,
output reg VAR8,
output reg VAR2,
input VAR6,
input VAR3
);
always @ *
begin
if( !VAR4 )
VAR2 <= 1'b1;
end
else if (VAR10==VAR1)
begin
if (VAR3==1'b1)
VAR2 <= 1'b1;
end
else
VAR2 <= VAR11;
end
else
VAR2 <= VAR7;
if ( !VAR4 )
VAR8 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.symbol.v | 1,329 | module MODULE1 (
input VAR8,
input VAR9 ,
input VAR6 ,
input VAR2 ,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
AngelTerrones/MUSB | Boards/xilinx_diligent_s3e/rtl/verilog/memory/memory.v | 4,375 | module MODULE1#(
parameter VAR18 = 8 )(
input clk,
input rst,
input [VAR18-1:0] VAR23, input [31:0] VAR19, input [3:0] VAR20, input VAR4, output reg [31:0] VAR10, output reg VAR11, input [VAR18-1:0] VAR21, input [31:0] VAR7, input [3:0] VAR12, input VAR14, output reg [31:0] VAR5, output reg VAR17 );
wire [31:0] VAR6;
w... | mit |
asicguy/gplgpu | hdl/vga/ram_9x32_2p.v | 2,281 | module MODULE1
(
input VAR1,
input VAR2,
input [4:0] VAR7,
input [4:0] VAR5,
input [8:0] VAR6,
output reg [8:0] VAR3
);
reg [8:0] VAR4 [0:31];
always @(posedge VAR1) if(VAR2) VAR4[VAR7] <= VAR6;
always @(posedge VAR1) VAR3 <= VAR4[VAR5];
endmodule | gpl-3.0 |
qmn/riscv-invicta | hardware/src/top.v | 2,605 | module MODULE1 (
input clk,
input reset
);
wire VAR23;
wire [31:0] VAR12;
wire VAR18;
wire VAR24;
wire [31:0] VAR21;
wire [31:0] VAR4;
wire [3:0] VAR6;
wire VAR2;
wire VAR15;
wire VAR7;
wire[31:0] VAR9;
wire [31:0] VAR1;
wire VAR14;
VAR10 VAR20(.clk(clk), .reset(reset), .VAR23(VAR23),
.VAR12(VAR12), .VAR18(VAR18), .VAR... | bsd-2-clause |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_wait_generate.v | 2,054 | module MODULE1
(
input wire rst,
input wire clk,
input wire VAR8,
output wire VAR10
);
reg VAR4 = 0;
reg VAR1 = 0;
always @ (posedge clk, posedge rst) begin
if(rst) VAR4 <= 1'b0;
end
else VAR4 <= VAR8;
end
always @ (posedge clk, posedge rst) begin
if(rst) VAR1 <= 1'b0;
end
else VAR1 <= VAR8 & VAR4 & (! VAR1 & !VAR10);
... | apache-2.0 |
mindrobots/P8X32A_Emulation | P8X32A_Pipistrello/src/cog_vid.v | 5,135 | module MODULE1
(
input VAR17,
input VAR14,
input VAR13,
input VAR27,
input VAR24,
input [31:0] VAR6,
input [31:0] VAR3,
input [31:0] VAR21,
input [7:0] VAR5,
input VAR32,
output ack,
output [31:0] VAR10
);
reg [31:0] VAR25;
reg [31:0] VAR23;
always @(posedge VAR17 or negedge VAR13)
if (!VAR13)
VAR25 <= 32'b0;
else if (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b_2.v | 2,302 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR4 ,
VAR11 ,
VAR10 ,
VAR3,
VAR9,
VAR5 ,
VAR7
);
output VAR8 ;
input VAR1 ;
input VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR3;
input VAR9;
input VAR5 ;
input VAR7 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_geninterp18.v | 1,602 | module MODULE1(
input VAR2,
input VAR13,
input VAR15,
input signed [17:0] VAR3,
input VAR10,
input [16:0] VAR6,
input [16:0] VAR4,
input [16:0] VAR12,
output signed [17:0] VAR14
);
reg VAR11;
reg [16:0] VAR7;
reg [16:0] VAR1;
reg [16:0] VAR8;
always @(posedge VAR2) begin
if(VAR13) begin
VAR11 <= VAR10;
VAR7 <= VAR6;
VA... | lgpl-3.0 |
ludisu13/Estructuras2 | tarea45/decodificador.v | 6,621 | module MODULE1(
input wire VAR9,
input wire[15:0] VAR10,
input wire VAR5, VAR12, VAR1, VAR11, VAR13, VAR8,
output reg VAR3,
output reg VAR2,
output reg[9:0] VAR7,
output reg[7:0] VAR6,
output reg VAR4,
output reg VAR14
);
always @( posedge VAR9)
begin
case(VAR10[15:10])
begin
VAR2<=0;
VAR4<=0;
VAR14<=0;
VAR3<=0;
VAR7<=... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311a/sky130_fd_sc_ls__o311a.functional.v | 1,459 | module MODULE1 (
VAR7 ,
VAR4,
VAR3,
VAR2,
VAR9,
VAR10
);
output VAR7 ;
input VAR4;
input VAR3;
input VAR2;
input VAR9;
input VAR10;
wire VAR11 ;
wire VAR6;
or VAR1 (VAR11 , VAR3, VAR4, VAR2 );
and VAR5 (VAR6, VAR11, VAR9, VAR10);
buf VAR8 (VAR7 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.blackbox.v | 1,418 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR4;
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/PLL_ADV.v | 82,459 | module MODULE1 (
VAR32,
VAR200,
VAR163,
VAR256,
VAR166,
VAR164,
VAR68,
VAR179,
VAR285,
VAR299,
VAR314,
VAR49,
VAR199,
VAR112,
VAR26,
VAR229,
VAR140,
VAR324,
VAR259,
VAR203,
VAR296,
VAR57,
VAR42,
VAR223,
VAR107,
VAR48,
VAR78,
VAR197
);
parameter VAR242 = "VAR198";
parameter VAR250 = "VAR327";
parameter VAR136 = "VAR327"... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly.v | 27,048 | module MODULE1(
clk,
rst,
VAR193,
VAR54,
VAR28,
VAR48,
VAR245,
VAR243,
VAR196,
VAR136,
VAR249,
VAR261,
VAR224,
VAR101,
VAR148,
VAR31,
VAR67,
VAR238,
VAR173,
VAR84,
VAR229,
VAR227,
VAR62,
VAR24,
VAR195,
VAR127,
VAR128,
VAR130,
VAR83,
VAR167,
VAR47,
VAR129,
VAR121,
VAR60,
VAR234,
VAR185,
VAR228,
VAR6,
o0 ,
o1 ,
o2 ,
o3 ,... | gpl-3.0 |
ILoveSpeccy/Aeon-Lite | cores/bashkiria-2m/src/k580wi53.v | 4,593 | module MODULE1(input clk,
input VAR21, input VAR41, input VAR22,
input VAR33, input VAR17, input VAR25,
output VAR14, output VAR32, output VAR40,
input[1:0] addr, input rd, input VAR9, input[7:0] VAR38, output reg[7:0] VAR31);
wire[7:0] VAR36;
wire[7:0] VAR27;
wire[7:0] VAR7;
always @
case ({VAR15,VAR6})
2'b00: VAR31 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.functional.v | 1,489 | module MODULE1 (
VAR11 ,
VAR6,
VAR7,
VAR2,
VAR10,
VAR1
);
output VAR11 ;
input VAR6;
input VAR7;
input VAR2;
input VAR10;
input VAR1;
wire VAR3 ;
wire VAR8;
and VAR9 (VAR3 , VAR6, VAR7 );
or VAR5 (VAR8, VAR10, VAR2, VAR3, VAR1);
buf VAR4 (VAR11 , VAR8 );
endmodule | apache-2.0 |
rqou/openfpga | hdl/xc2c-model/XC2CZIA.v | 9,145 | module MODULE1(
VAR3, VAR1, VAR6,
VAR5,
VAR2);
parameter VAR4 = 32; | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4_4.v | 2,275 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR6 ,
VAR5,
VAR11,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR5;
input VAR11;
input VAR4 ;
input VAR8 ;
VAR10 VAR3 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.behavioral.v | 2,045 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR7 ,
VAR11 ,
VAR14 ,
VAR12,
VAR15
);
output VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR11 ;
input VAR14 ;
input VAR12;
input VAR15;
wire VAR14 VAR16 ;
wire VAR14 VAR10 ;
wire VAR5 ;
wire VAR17;
and VAR4 (VAR16 , VAR11, VAR14 );
and VAR2 (VAR10 , VAR9, VAR7 );
or VAR8 (VAR5 , VAR10, VAR16... | apache-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_altpll_0.v | 10,973 | module MODULE1
(
VAR1,
VAR4,
VAR6,
VAR8) ;
input VAR1;
input VAR4;
input [0:0] VAR6;
output [0:0] VAR8;
tri0 VAR1;
tri1 VAR4;
reg [0:0] VAR9;
reg [0:0] VAR2;
reg [0:0] VAR5;
wire VAR10;
wire VAR7;
wire VAR3; | gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.