repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
bbrown1867/ObjectTracking | hw/common/video_input/video_input.v | 2,062 | module MODULE1
(
input wire VAR15,
input wire VAR49,
input wire [7:0] VAR42,
input wire VAR40,
output wire VAR45,
input wire VAR41,
output wire [9:0] VAR33,
output wire [9:0] VAR4,
output wire [9:0] VAR46,
output wire [9:0] VAR35,
output wire [9:0] VAR54,
output wire VAR22
);
wire [15:0] VAR47;
wire VAR5;
wire [9:0] VA... | mit |
kyzhai/NUNY | src/hardware/book.v | 6,344 | module MODULE1 (
address,
VAR45,
VAR31);
input [11:0] address;
input VAR45;
output [11:0] VAR31;
tri1 VAR45;
wire [11:0] VAR14;
wire [11:0] VAR31 = VAR14[11:0];
VAR28 VAR6 (
.VAR33 (address),
.VAR25 (VAR45),
.VAR7 (VAR14),
.VAR32 (1'b0),
.VAR34 (1'b0),
.VAR17 (1'b1),
.VAR47 (1'b0),
.VAR20 (1'b0),
.VAR22 (1'b1),
.VAR41 ... | gpl-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_sdram.v | 24,402 | module MODULE2 (
clk,
rd,
VAR19,
wr,
VAR82,
VAR74,
VAR12,
VAR35,
VAR50,
VAR84
)
;
output VAR74;
output VAR12;
output VAR35;
output VAR50;
output [ 61: 0] VAR84;
input clk;
input rd;
input VAR19;
input wr;
input [ 61: 0] VAR82;
wire VAR74;
wire VAR12;
wire VAR35;
reg [ 1: 0] VAR37;
reg [ 61: 0] VAR3;
reg [ 61: 0] VAR9;
... | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_alu.v | 10,001 | module MODULE1(
VAR13, VAR6, VAR38, VAR23,
VAR30, VAR12, VAR25,
VAR33, VAR20,
VAR24, VAR39, VAR2,
VAR8, VAR37, VAR15, flag
);
parameter VAR34 = VAR17;
input [VAR34-1:0] VAR13;
input [VAR34-1:0] VAR6;
input [VAR34-1:0] VAR38;
input VAR23;
input [VAR29-1:0] VAR30;
input [VAR3-1:0] VAR12;
input [VAR1-1:0] VAR25;
input [4:... | gpl-3.0 |
antmicro/yosys | techlibs/intel/cycloneive/arith_map.v | 3,237 | module MODULE1
(input VAR41,
input VAR20,
input VAR24,
output VAR40,
output VAR27);
wire VAR41;
wire VAR20;
wire VAR40;
wire VAR24;
wire VAR27;
wire VAR28;
assign VAR28 = 1'b1;
VAR39 VAR10 (.VAR18(VAR27),
.VAR15(VAR41),
.VAR16(VAR20),
.VAR1(VAR24),
.VAR32(VAR28));
VAR39 VAR43 (.VAR18(VAR40),
.VAR15(VAR24),
.VAR16(VAR... | isc |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpad/sky130_fd_io__top_power_hvc_wpad.functional.v | 1,097 | module MODULE1 ( VAR17, VAR4, VAR5
);
inout VAR17;
inout VAR4;
inout VAR5;
supply1 VAR7;
supply1 VAR2;
supply0 VAR1;
supply1 VAR9;
supply1 VAR6;
supply1 VAR10;
supply1 VAR15;
supply1 VAR18;
supply1 VAR16;
supply1 VAR19;
supply1 VAR8;
supply1 VAR11;
supply0 VAR12;
supply0 VAR14;
supply0 VAR3;
supply0 VAR13;
assign VAR9 ... | apache-2.0 |
johan92/yafpgatetris | ip_cores/vga/vga_time_generator.v | 8,600 | module MODULE1(
clk,
VAR24,
VAR5,
VAR4,
VAR42,
VAR15,
VAR12,
VAR26,
VAR38,
VAR21,
VAR41,
VAR1,
VAR29,
VAR20,
VAR8,
VAR6,
VAR7,
VAR28,
VAR30
);
input clk;
input VAR24;
input [11:0] VAR5;
input [11:0] VAR4;
input [11:0] VAR42;
input [11:0] VAR15;
input [11:0] VAR12;
input [11:0] VAR26;
input [11:0] VAR38;
input [11:0] VA... | mit |
ptracton/wb_soc_template | rtl/uart16550/rtl/verilog/uart_transmitter.v | 12,272 | module MODULE1 (clk, VAR16, VAR17, VAR40, VAR37, enable, VAR41, VAR5, VAR11, VAR2, VAR24);
input clk;
input VAR16;
input [7:0] VAR17;
input VAR40;
input [7:0] VAR37;
input enable;
input VAR2;
input VAR24; output VAR41;
output [2:0] VAR5;
output [VAR6-1:0] VAR11;
reg [2:0] VAR5;
reg [4:0] counter;
reg [2:0] VAR3; reg [6... | mit |
donnaware/AGC | rtl/de0/modules/ng_ALU.v | 4,149 | module MODULE1(
input VAR4, input [100:0] VAR2, input [ 15:0] VAR14, output [ 15:0] VAR8 );
wire VAR19 = VAR2[VAR26(VAR19)]; wire VAR5 = VAR2[VAR26(VAR5)]; wire VAR18 = VAR2[VAR26(VAR18)]; wire VAR20 = VAR2[VAR26(VAR20)]; wire VAR7 = VAR2[VAR26(VAR7)]; wire VAR21 = VAR2[VAR26(VAR21)]; wire VAR10 = VAR2[VAR26(VAR10)]; w... | gpl-3.0 |
brianbennett/fpga_nes | hw/src/cpu/rp2a03.v | 4,843 | module MODULE1
(
input wire VAR5, input wire VAR17,
input wire VAR42, input wire [ 7:0] din, input wire VAR24, input wire VAR31, output wire [ 7:0] dout, output wire [15:0] VAR10, output wire VAR36, output wire VAR27,
input wire VAR48, input wire VAR49, output wire VAR51, output wire VAR15,
input wire [ 3:0] VAR26, out... | bsd-2-clause |
ShepardSiegel/ocpi | libsrc/hdl/bsv/bram_patch/BRAM1_cur.v | 2,806 | module MODULE1(VAR8,
VAR3,
VAR6,
VAR4,
VAR11,
VAR1
);
parameter VAR14 = 0;
parameter VAR13 = 1;
parameter VAR10 = 1;
parameter VAR7 = 1;
input VAR8;
input VAR3;
input VAR6;
input [VAR13-1:0] VAR4;
input [VAR10-1:0] VAR11;
output [VAR10-1:0] VAR1;
reg [VAR10-1:0] VAR2[0:VAR7-1];
reg [VAR10-1:0] VAR5;
reg [VAR10-1:0] VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.functional.v | 1,422 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4 ,
VAR10 ,
VAR3
);
output VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR3;
wire VAR8 ;
wire VAR9;
not VAR5 (VAR8 , VAR3 );
nor VAR1 (VAR9, VAR7, VAR4, VAR10, VAR8);
buf VAR2 (VAR6 , VAR9 );
endmodule | apache-2.0 |
mammenx/pegasus | wxp/dgn/rtl/common/pkt_ff_async/pkt_ff_async.v | 7,214 | module MODULE1 #(VAR44 = 32, VAR54 = 128, VAR29=2)
(
input VAR2,
input VAR19,
input VAR17,
input VAR45,
input VAR15,
input VAR37,
input VAR43,
input [VAR44-1:0] VAR46,
output VAR41,
input VAR5,
output VAR63,
output VAR51,
output VAR59,
output [VAR44-1:0] VAR3,
input VAR58,
output VAR32
);
localparam VAR9 = VAR35(VAR54)... | gpl-3.0 |
kyzhai/NUNY | src/hardware/ninjasymbol.v | 6,433 | module MODULE1 (
address,
VAR32,
VAR50);
input [11:0] address;
input VAR32;
output [11:0] VAR50;
tri1 VAR32;
wire [11:0] VAR15;
wire [11:0] VAR50 = VAR15[11:0];
VAR33 VAR20 (
.VAR11 (address),
.VAR6 (VAR32),
.VAR49 (VAR15),
.VAR8 (1'b0),
.VAR29 (1'b0),
.VAR36 (1'b1),
.VAR3 (1'b0),
.VAR46 (1'b0),
.VAR35 (1'b1),
.VAR22 (... | gpl-2.0 |
zeruniverse/pipelined_CPU | ISE project/pipeid.v | 1,806 | module MODULE1(VAR10,VAR18,VAR38,VAR39,VAR8,VAR37,VAR42,VAR49,VAR26,VAR24,VAR4,VAR19,VAR23,VAR3,VAR40,VAR27,VAR41,VAR45,VAR14,VAR13,VAR50,VAR35,VAR46,VAR33,VAR16,VAR7,VAR11,VAR22,VAR1,VAR20,VAR47,VAR21,VAR2,VAR6);
input wire VAR10,VAR39,VAR8,VAR37,VAR40,VAR27,VAR3;
input wire [4:0] VAR18,VAR38,VAR26,VAR2;
input wire [3... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_link/bsg_link_osdr_phy.v | 1,997 | module MODULE1
,parameter VAR11 = 0)
(input VAR10
,input VAR1
,input [VAR5-1:0] VAR6
,output VAR7
,output [VAR5-1:0] VAR2
);
VAR8 VAR4
(.VAR10 (VAR10)
,.VAR1(VAR1)
,.VAR7 (VAR7)
);
VAR3 #(.VAR5(VAR5)) VAR9
(.VAR10(VAR10),.VAR6(VAR6),.VAR2(VAR2));
endmodule | bsd-3-clause |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_ocmc.v | 4,054 | module MODULE1(
VAR68,
VAR6,
VAR11,
VAR37,
VAR28,
VAR44,
VAR55,
VAR41,
VAR9,
VAR43,
VAR3,
VAR18,
VAR61,
VAR45,
VAR7,
VAR53,
VAR62,
VAR36,
VAR27,
VAR64,
VAR23,
VAR63,
VAR38,
VAR66,
VAR58,
VAR2
);
input VAR68;
input VAR6;
output VAR11;
input VAR37;
input VAR28;
output VAR44;
input[VAR16-1:0] VAR55;
input[VAR65-1:0] VAR41... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_rank_monitor.v | 45,574 | module MODULE1 #
( parameter
VAR169 = 2,
VAR16 = 4,
VAR145 = 16, VAR139 = 3, VAR72 = "VAR33",
VAR177 = 2,
VAR168 = 1,
VAR81 = 4,
VAR119 = 4,
VAR179 = 8,
VAR37 = 0,
VAR172 = 4,
VAR12 = 3,
VAR188 = 4,
VAR133 = 10,
VAR99 = 4,
VAR13 = 5,
VAR184 = 6,
VAR91 = 3,
VAR69 = 5,
VAR97 = 4,
VAR87 = 4,
VAR1 = 3,
VAR192 = 5,
VAR162 =... | gpl-3.0 |
asicguy/gplgpu | hdl/bios_internal/bios_internal.v | 3,575 | module MODULE1
(
input VAR1,
input VAR12,
input VAR2,
input VAR9,
input VAR4,
output reg VAR11
);
reg [31:0] VAR5;
reg [23:0] VAR3;
wire [15:0] VAR14;
reg [4:0] counter;
reg [1:0] VAR19;
parameter VAR10 = 8'b00000011;
parameter VAR15 = 0, VAR8 = 1, VAR16 = 2, VAR18 = 3;
always @(posedge VAR1, negedge VAR12) begin
if (!... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_axi_basic_tx.v | 9,964 | module MODULE1 #(
parameter VAR5 = 128, parameter VAR28 = "VAR16", parameter VAR23 = "VAR45", parameter VAR41 = "VAR45", parameter VAR20 = 1,
parameter VAR40 = (VAR5 == 128) ? 2 : 1, parameter VAR26 = VAR5 / 8 ) (
input [VAR5-1:0] VAR35, input VAR11, output VAR24, input [VAR26-1:0] VAR2, input VAR19, input [3:0] VAR43,... | gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_operandmuxes.v | 8,213 | module MODULE1(
clk, rst,
VAR11, VAR17, VAR16, VAR15, VAR8, VAR9,
VAR1, VAR14, VAR18, VAR5, VAR3, VAR10
);
parameter VAR13 = VAR19;
input clk;
input rst;
input VAR11;
input VAR17;
input [VAR13-1:0] VAR16;
input [VAR13-1:0] VAR15;
input [VAR13-1:0] VAR8;
input [VAR13-1:0] VAR9;
input [VAR13-1:0] VAR1;
input [VAR2-1:0] V... | gpl-2.0 |
AngelTerrones/ADA | rtl/ada_branch_unit.v | 4,623 | module MODULE1(
input [5:0] VAR13, input [31:0] VAR2, input [31:0] VAR4, input [31:0] VAR19, input [20:0] VAR10,
output [31:0] VAR1, output VAR15, output VAR12 );
reg [31:0] VAR17;
reg VAR8;
wire VAR22;
wire VAR9;
wire VAR21;
wire VAR14;
wire VAR7;
wire VAR18;
wire [31:0] VAR16;
wire [31:0] VAR6;
wire [5:0] VAR20;
assi... | mit |
aj-michael/Digital-Systems | Pong/Phase3/TermProjectPhase3/ipcore_dir/Clock50MHz/example_design/Clock50MHz_exdes.v | 4,919 | module MODULE1
parameter VAR27 = 100
)
( input VAR5,
input VAR10,
output [1:1] VAR6,
output VAR11,
output VAR7
);
localparam VAR4 = 16;
wire VAR17 = !VAR7 || VAR10;
reg VAR9;
reg VAR24;
reg VAR18;
reg VAR8;
wire VAR20;
wire VAR25;
wire clk;
reg [VAR4-1:0] counter;
VAR23 VAR15
( .VAR5 (VAR5),
.VAR1 (VAR20),
.VAR7 (VAR7)... | mit |
PyLCARS/PythonUberHDL | PYNQLearn/ClockDivider.v | 1,271 | module MODULE1 (
VAR6,
VAR4,
clk,
rst
);
input [31:0] VAR6;
output VAR4;
wire VAR4;
input clk;
input rst;
reg [31:0] VAR2;
reg VAR1;
always @(posedge clk, posedge rst) begin: VAR3
if (rst) begin
VAR2 <= 0;
end
else if ((({1'b0, VAR2}) == (({1'b0, VAR6}) - 1))) begin
VAR2 <= 0;
end
else begin
VAR2 <= (VAR2 + 1);
end
end... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp.pp.blackbox.v | 1,407 | module MODULE1 (
VAR1 ,
VAR2,
VAR4 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR5 ,
VAR8
);
output VAR1 ;
input VAR2;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/ExaNIC_X10/fpga/rtl/sync_signal.v | 1,743 | module MODULE1 #(
parameter VAR2=1, parameter VAR1=2 )(
input wire clk,
input wire [VAR2-1:0] in,
output wire [VAR2-1:0] out
);
reg [VAR2-1:0] VAR3[VAR1-1:0];
assign out = VAR3[VAR1-1];
integer VAR4;
always @(posedge clk) begin
VAR3[0] <= in;
for (VAR4 = 1; VAR4 < VAR1; VAR4 = VAR4 + 1) begin
VAR3[VAR4] <= VAR3[VAR4-1]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.functional.v | 1,329 | module MODULE1 (
VAR2,
VAR5,
VAR3,
VAR8,
VAR6
);
output VAR2;
input VAR5;
input VAR3;
input VAR8;
input VAR6;
wire VAR4;
nor VAR1 (VAR4, VAR5, VAR3, VAR8, VAR6 );
buf VAR7 (VAR2 , VAR4 );
endmodule | apache-2.0 |
jncronin/jca | cpu/rom_tristate.v | 1,339 | module MODULE1(VAR3, VAR4, VAR2, VAR1);
input VAR3;
input VAR4;
input [7:0] VAR2;
output [7:0] VAR1;
assign VAR1 = (~VAR3 & ~VAR4) ? VAR2 : 8'VAR5;
endmodule | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/02 verilog/ProyectoDigital1/Microfono/fifo.v | 2,257 | module MODULE1
parameter VAR16 = 4,
parameter VAR1 = 18
)
(
input clk, reset,
input rd, wr,
input [VAR1-1:0] VAR6,
output [VAR1-1:0] VAR9,
output VAR10,
output VAR15
);
parameter VAR4 = (1 << VAR16);
reg [VAR1-1:0] VAR17 [VAR4-1:0];
reg [VAR16-1:0] VAR5, VAR3;
reg [VAR16-1:0] VAR14, VAR2;
reg VAR7, VAR11, VAR8, VAR13;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf_1.v | 2,034 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR5,
VAR8,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR4 ;
input VAR5;
input VAR8;
input VAR1 ;
input VAR3 ;
VAR7 VAR6 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR5;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.pp.symbol.v | 1,348 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR7 ,
output VAR1 ,
input VAR3 ,
input VAR6,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
schelleg/PYNQ | boards/ip/io_switch_1.1/src/io_switch.v | 69,415 | module MODULE1 #(
parameter VAR95=28,
parameter VAR100 = 2,
parameter VAR13 = 3,
parameter VAR92 = 2
)
(
input [31:0] VAR64, input [31:0] VAR36, input [31:0] VAR23, input [31:0] VAR7, input [31:0] VAR69, input [31:0] VAR3, input [31:0] VAR108, input [31:0] VAR104,
input [VAR95-1:0] VAR101,
output [VAR95-1:0] VAR112,
ou... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.blackbox.v | 1,628 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR8 ,
VAR7 ,
VAR5 ,
VAR6,
VAR4 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
sam-falvo/kestrel | cores/KCP53K/cpu2/rtl/verilog/xrs.v | 2,391 | module MODULE1(
input VAR30,
input [4:0] VAR1,
input [63:0] VAR12,
input [2:0] VAR15,
output [63:0] VAR25,
output [63:0] VAR19,
input [4:0] VAR21,
input [4:0] VAR18
);
wire [63:0] VAR4 = ((VAR15 == VAR24) ? {56'd0, VAR12[7:0]} : 0)
| ((VAR15 == VAR8) ? {48'd0, VAR12[15:0]} : 0)
| ((VAR15 == VAR6) ? {32'd0, VAR12[31:0]}... | mpl-2.0 |
HackSlash/SparcCool | cpu/register_file.v | 3,504 | module MODULE1 (VAR23, VAR16, VAR14, VAR33, VAR1, rst, clk);
input [5:0] VAR23, VAR16;
output [32:0] VAR14;
input [32:0] VAR33;
input VAR1, rst, clk;
register VAR31(.VAR1(VAR1), .rst(rst), .clk(clk));
register VAR6(.VAR1(VAR1), .rst(rst), .clk(clk));
register VAR5(.VAR1(VAR1), .rst(rst), .clk(clk));
register VAR34(.VAR... | unlicense |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/sd_fifo.v | 4,094 | module MODULE1
(
input [1:0] VAR1,
input [7:0] VAR64,
output [7:0] VAR24,
input VAR37,
input VAR11,
input VAR33,
input [1:0] VAR13,
input [7:0] VAR40,
output [7:0] VAR3,
input VAR26,
input VAR39,
input VAR20,
output [1:4] VAR47,
output [1:4] VAR36,
input rst
);
wire [8:0] VAR41, VAR17, VAR57, VAR44, VAR61, VAR23, VAR22... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41o/sky130_fd_sc_ls__a41o_2.v | 2,426 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR10 ,
VAR4 ,
VAR9 ,
VAR1 ,
VAR11,
VAR3,
VAR5 ,
VAR12
);
output VAR8 ;
input VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR9 ;
input VAR1 ;
input VAR11;
input VAR3;
input VAR5 ;
input VAR12 ;
VAR2 VAR7 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms2/ac701/system_top.v | 8,235 | module MODULE1 (
VAR75,
VAR68,
VAR51,
VAR62,
VAR34,
VAR3,
VAR29,
VAR7,
VAR74,
VAR106,
VAR37,
VAR38,
VAR18,
VAR48,
VAR61,
VAR97,
VAR55,
VAR47,
VAR23,
VAR53,
VAR84,
VAR70,
VAR80,
VAR63,
VAR1,
VAR13,
VAR8,
VAR60,
VAR78,
VAR98,
VAR95,
VAR104,
VAR103,
VAR85,
VAR35,
VAR76,
VAR42,
VAR89,
VAR21,
VAR100,
VAR49,
VAR92,
VAR93,
VA... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_2048x32.v | 12,824 | module MODULE1(
VAR66, VAR67, VAR20,
clk, rst, VAR65, VAR63, VAR56, addr, VAR42, VAR24
);
parameter VAR41 = 11;
parameter VAR72 = 32;
input VAR66;
input [VAR22 - 1:0] VAR20;
output VAR67;
input clk; input rst; input VAR65; input VAR63; input VAR56; input [VAR41-1:0] addr; input [VAR72-1:0] VAR42; output [VAR72-1:0] VAR... | gpl-3.0 |
hanw/sonic-lite | hw/verilog/si570/initial_config.v | 3,245 | module MODULE1(
VAR2, VAR5, VAR3,
VAR6,
);
input VAR2;
input VAR5;
output VAR3;
input VAR6;
wire VAR3;
reg [VAR1-1:0] VAR4;
always@(posedge VAR2 or negedge VAR5)
begin
if (!VAR5)
begin
VAR4 <= 0;
end
else if (VAR4 == 20'hfffff)
begin
VAR4 <=20'hfffff;
end
else
begin
VAR4 <= VAR4 + 1;
end
end
assign VAR3 = ((VAR4 == 20'... | mit |
hj3938/FPGA-Imaging-Library | Geometry/Pan/HDL/Pan.srcs/sources_1/new/Pan.v | 5,671 | module MODULE1(
clk,
VAR10,
VAR21,
VAR29,
VAR25,
VAR9,
VAR19,
VAR16,
VAR4,
VAR12,
VAR30,
VAR15);
parameter VAR11 = 0;
parameter VAR14 = 8;
parameter VAR22 = 320;
parameter VAR13 = 240;
parameter VAR24 = 9;
input clk;
input VAR10;
input signed [VAR24 : 0] VAR21;
input signed [VAR24 : 0] VAR29;
input VAR25;
input [VAR14 ... | lgpl-2.1 |
jotego/jt51 | syn/xilinx/ym09/hdl/debouncer.v | 1,812 | module MODULE1(
input clk,
input rst,
input VAR2,
output reg VAR8, output VAR1, output VAR9 );
reg VAR4; always @(posedge clk) VAR4 <= ~VAR2; reg VAR5; always @(posedge clk) VAR5 <= VAR4;
reg [15:0] VAR3;
wire VAR6 = (VAR8==VAR5);
wire VAR7 = &VAR3;
always @(posedge clk or posedge rst) begin
if( rst ) begin
VAR3 <= 16'... | gpl-3.0 |
SymbiFlow/yosys | techlibs/common/techmap.v | 15,811 | module 90simplemapboolops;
endmodule
module 90simplemapreduceops;
endmodule
module 90simplemaplogicops;
endmodule
module 90simplemapcompareops;
endmodule
module 90simplemapvarious;
endmodule
module 90simplemapregisters;
endmodule
module 90shiftopsshrshlsshlsshr (VAR33, VAR59, VAR16);
parameter VAR23 = 0;
parameter VAR2... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.symbol.v | 1,402 | module MODULE1 (
input VAR6,
input VAR3,
input VAR1,
input VAR7,
input VAR10,
output VAR8
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.behavioral.pp.v | 2,026 | module MODULE1 (
VAR14 ,
VAR1 ,
VAR11 ,
VAR15 ,
VAR13 ,
VAR10,
VAR8,
VAR7 ,
VAR3
);
output VAR14 ;
input VAR1 ;
input VAR11 ;
input VAR15 ;
input VAR13 ;
input VAR10;
input VAR8;
input VAR7 ;
input VAR3 ;
wire VAR16 ;
wire VAR9 ;
wire VAR17;
and VAR12 (VAR16 , VAR15, VAR1, VAR11 );
or VAR2 (VAR9 , VAR16, VAR13 );
VAR4 ... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | fifo.v | 3,222 | module MODULE1 (VAR13, VAR8, VAR6, VAR16, VAR9, VAR15, VAR11, VAR2 );
input VAR13;
input [18:0] VAR8;
input VAR6;
input VAR16;
input VAR9;
output[18:0] VAR15;
output VAR11;
output VAR2;
wire VAR3;
wire VAR5;
reg [3:0] VAR12;
reg [3:0] VAR7;
reg VAR1;
reg VAR4;
reg [18:0] MODULE1 [0:15] ;
reg [18:0] VAR10;
reg [4:0] VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41a/sky130_fd_sc_ls__o41a_1.v | 2,411 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR11 ,
VAR3 ,
VAR5 ,
VAR12 ,
VAR4,
VAR1,
VAR10 ,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR12 ;
input VAR4;
input VAR1;
input VAR10 ;
input VAR6 ;
VAR8 VAR9 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr.blackbox.v | 1,376 | module MODULE1 (
VAR2,
VAR7
);
output VAR2;
input VAR7;
supply1 VAR1 ;
supply0 VAR4 ;
supply1 VAR5;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba.functional.v | 1,467 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR3;
wire VAR4 ;
wire VAR9;
nor VAR7 (VAR4 , VAR5, VAR1 );
nor VAR6 (VAR9, VAR3, VAR4 );
buf VAR8 (VAR2 , VAR9 );
endmodule | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_cpu_cpu_debug_slave_wrapper.v | 9,028 | module MODULE1 (
VAR33,
VAR53,
clk,
VAR50,
VAR11,
VAR20,
VAR17,
VAR3,
VAR10,
VAR6,
VAR26,
VAR8,
VAR4,
VAR19,
VAR54,
VAR12,
VAR13,
VAR34,
VAR25,
VAR22,
VAR48,
VAR35,
VAR57,
VAR47,
VAR56,
VAR39,
VAR40,
VAR31,
VAR41,
VAR44,
VAR21,
VAR51,
VAR46
)
;
output [ 37: 0] VAR48;
output VAR35;
output VAR57;
output VAR47;
output VAR... | gpl-3.0 |
chaohu/Daily-Learning | Verilog/lab5/lab5_1/lab5_3_1/lab5_3_1.srcs/sources_1/new/lab5_3_1.v | 2,017 | module MODULE1(
input VAR6,reset,clk,
output reg [2:0] VAR2,
output reg [2:0] state,VAR1
);
parameter VAR4 = 0,VAR5 = 1,VAR7 = 3,VAR8 = 5,VAR3 = 7,VAR9 = 2;
reg [5:0] VAR10 [7:0];
begin
begin
end
begin
begin
begin
end
begin
end
begin
end
begin
end
begin
end
begin
end | mit |
ServerTech/neptune | code/reg_array_dual.v | 2,158 | module MODULE1(clk, rst, VAR9, VAR11, VAR3, VAR13, VAR10, VAR7, VAR1, VAR6, VAR4);
parameter VAR5 = 'd16; parameter VAR12 = 'd8; parameter VAR2 = 'd3;
input wire clk , rst ; input wire VAR9 , VAR11 ; input wire [VAR2-1:0] VAR3 , VAR13 ;
input [VAR5-1:0] VAR10 , VAR7 ;
output reg VAR1 ;
output reg [VAR5-1:0] VAR6 , VAR4... | mit |
DougFirErickson/parallella-hw | fpga/src/emmu/hdl/emmu.v | 5,932 | module MODULE1 (
VAR32, VAR16, VAR22, VAR15,
VAR18, VAR29, VAR39,
VAR36,
clk, reset, VAR8, VAR28, VAR5, VAR20, VAR13, VAR37,
VAR26, VAR7, VAR35,
VAR6, VAR2, VAR21,
VAR33
);
parameter VAR27 = 32; parameter VAR9 = 32; parameter VAR24 = 12; parameter VAR30 = 64; parameter VAR40 = VAR30-VAR9+VAR24; parameter VAR34 = VAR24+... | gpl-3.0 |
Obijuan/ACC | hw/roadmap/05-click-counter2/click_counter2.v | 3,473 | module MODULE3 (input VAR23,
input clk,
input rst,
output VAR1,
output VAR7,
output VAR32,
output VAR30,
output VAR35,
output VAR6,
output VAR14,
output VAR33);
wire VAR29, VAR24;
wire VAR20, VAR26;
wire VAR37;
VAR5 #(
.VAR27(6'VAR25 101001),
.VAR16(1'VAR25 1)
) VAR15 (
.VAR3(clk),
.VAR36(VAR24)
);
VAR5 #(
.VAR27(6'VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkbuf/sky130_fd_sc_hdll__clkbuf_12.v | 2,056 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR3,
VAR6,
VAR2 ,
VAR5
);
output VAR4 ;
input VAR8 ;
input VAR3;
input VAR6;
input VAR2 ;
input VAR5 ;
VAR1 VAR7 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR8
);
output VAR4;
input VAR8;
supply1 VAR3;
supply0 VAR6;... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.ip_user_files/ipstatic/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_reg_map.v | 4,353 | module MODULE1();
parameter VAR28 = 32'h20000000; parameter VAR25 = 32'h10000000;
reg [VAR2-1:0] VAR7 [0:(VAR25/VAR11)-1]; reg [VAR2-1:0] VAR34 [0:(VAR25/VAR11)-1]; parameter VAR23 = 26;
reg [VAR2-1:0] VAR15 [0:(VAR28/VAR11)-1]; parameter VAR23 = 27;
task automatic VAR20;
input VAR33;
begin
end
endtask
task automatic V... | gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/num/num_stub.v | 1,252 | module MODULE1(VAR4, VAR5, VAR2, VAR3, VAR1)
;
input VAR4;
input [0:0]VAR5;
input [12:0]VAR2;
input [11:0]VAR3;
output [11:0]VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a.functional.v | 1,562 | module MODULE1 (
VAR12 ,
VAR3,
VAR8,
VAR9 ,
VAR7
);
output VAR12 ;
input VAR3;
input VAR8;
input VAR9 ;
input VAR7 ;
wire VAR4 ;
wire VAR10 ;
wire VAR6;
nand VAR5 (VAR4 , VAR8, VAR3 );
or VAR1 (VAR10 , VAR7, VAR9 );
and VAR2 (VAR6, VAR4, VAR10);
buf VAR11 (VAR12 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2_12.v | 2,209 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR4,
VAR6,
VAR10 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR4;
input VAR6;
input VAR10 ;
input VAR5 ;
VAR8 VAR7 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256.v | 13,843 | module MODULE1(
rst,
VAR239,
VAR35,
din,
VAR156,
VAR8,
dout,
VAR406,
VAR151,
VAR266,
VAR388
);
input rst;
input VAR239;
input VAR35;
input [31 : 0] din;
input VAR156;
input VAR8;
output [255 : 0] dout;
output VAR406;
output VAR151;
output [9 : 0] VAR266;
output [12 : 0] VAR388;
VAR325 #(
.VAR115(0),
.VAR378(0),
.VAR238... | gpl-2.0 |
ptracton/wb_dsp | rtl/fifo_to_sram.v | 2,500 | module MODULE1 (
VAR12, VAR3, VAR2,
VAR9, VAR4, VAR13, VAR10, VAR6, VAR7,
VAR5, VAR14, VAR1
) ;
parameter VAR8=32;
input VAR9;
input VAR4;
input VAR13;
input VAR10;
input VAR6;
input [5:0] VAR7;
input [5:0] VAR5;
input VAR14;
output wire VAR12;
input [VAR8-1:0] VAR1;
output reg [VAR8-1:0] VAR3;
output reg VAR2;
reg VAR... | mit |
scalable-networks/ext | uhd/fpga/usrp1/megacells/add32.v | 8,527 | module MODULE2
(
VAR29,
VAR4,
VAR2) ;
input [7:0] VAR29;
input [7:0] VAR4;
output [7:0] VAR2;
wire [7:0] VAR31;
wire [0:0] VAR1;
wire [0:0] VAR16;
wire [0:0] VAR23;
wire [0:0] VAR22;
wire [0:0] VAR27;
wire [0:0] VAR10;
wire [0:0] VAR18;
wire [7:0] VAR30;
wire [7:0] VAR6;
VAR32 VAR3
(
.VAR21(1'b0),
.VAR28(VAR31[0:0]),
.... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3/sky130_fd_sc_hdll__and3.blackbox.v | 1,262 | module MODULE1 (
VAR7,
VAR6,
VAR8,
VAR3
);
output VAR7;
input VAR6;
input VAR8;
input VAR3;
supply1 VAR5;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41a/sky130_fd_sc_ls__o41a_2.v | 2,411 | module MODULE2 (
VAR10 ,
VAR5 ,
VAR2 ,
VAR9 ,
VAR7 ,
VAR6 ,
VAR1,
VAR8,
VAR3 ,
VAR11
);
output VAR10 ;
input VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR6 ;
input VAR1;
input VAR8;
input VAR3 ;
input VAR11 ;
VAR4 VAR12 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o.behavioral.v | 1,539 | module MODULE1 (
VAR14 ,
VAR2,
VAR7,
VAR9,
VAR11
);
output VAR14 ;
input VAR2;
input VAR7;
input VAR9;
input VAR11;
supply1 VAR12;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR6 ;
wire VAR4 ;
wire VAR8;
and VAR5 (VAR4 , VAR2, VAR7 );
or VAR3 (VAR8, VAR4, VAR11, VAR9);
buf VAR13 (VAR14 , VAR8 );
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab2-ManualKeypadScannerAndEncoder/DebouncerWithoutLatch.v | 1,220 | module MODULE1(VAR8, VAR2, VAR10, VAR6) ;
input VAR8, VAR10, VAR6;
output reg VAR2;
parameter VAR1=0, VAR5=1, VAR11=2, VAR12=3;
reg [1:0] VAR4, VAR9;
wire VAR7;
reg VAR3;
always @ (posedge VAR6) begin
if(VAR10==1) VAR4 <= 0;
end
else VAR4<=VAR9;
case (VAR4)
0: begin VAR2<=0; VAR3<=1; end 1: begin VAR2<=0; VAR3<=0; end ... | mit |
gralco/click-clock-board | mojo_io_shield/source/elevator.v | 3,404 | module MODULE1 (
clk,
VAR2,
rst,
en,
VAR9,
VAR4,
VAR7,
VAR8
);
input clk;
input VAR2;
input rst;
input en;
output [7:0] VAR9;
reg [7:0] VAR9;
output [17:0] VAR4;
reg [17:0] VAR4;
output [7:0] VAR7;
wire [7:0] VAR7;
output [3:0] VAR8; wire [3:0] VAR8;
reg [3:0] VAR6 [0:6-1];
reg [1:0] VAR1, VAR5;
assign VAR7[0] = (((VAR... | gpl-3.0 |
kyzhai/NUNY | src/hardware/two_new2.v | 6,389 | module MODULE1 (
address,
VAR23,
VAR8);
input [9:0] address;
input VAR23;
output [11:0] VAR8;
tri1 VAR23;
wire [11:0] VAR40;
wire [11:0] VAR8 = VAR40[11:0];
VAR25 VAR19 (
.VAR30 (address),
.VAR27 (VAR23),
.VAR13 (VAR40),
.VAR44 (1'b0),
.VAR41 (1'b0),
.VAR45 (1'b1),
.VAR46 (1'b0),
.VAR35 (1'b0),
.VAR22 (1'b1),
.VAR21 (1... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Open_Loop_Control.v | 4,817 | module MODULE1
(
VAR27,
reset,
VAR14,
VAR29,
VAR7,
VAR35,
VAR4,
VAR34,
VAR33,
VAR6,
VAR32
);
input VAR27;
input reset;
input VAR14;
input VAR29;
input signed [17:0] VAR7; input signed [17:0] VAR35; input signed [17:0] VAR4; output signed [17:0] VAR34; output signed [17:0] VAR33; output signed [17:0] VAR6; output signed... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlclkp/sky130_fd_sc_ms__dlclkp.symbol.v | 1,276 | module MODULE1 (
input VAR5 ,
input VAR3,
output VAR2
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/fifo/sync_fifo.v | 2,929 | module MODULE1 #(
parameter VAR2 = 16, parameter VAR4 = 32 )(
input wire clk, input wire VAR9, input wire rst, input wire [ VAR4-1:0] VAR7, output wire [ VAR4-1:0] VAR1, input wire VAR14, input wire VAR5, output wire VAR12, output wire VAR13 );
function integer VAR3;
input [31:0] VAR17;
integer VAR10;
begin
VAR10 = VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xor3/gf180mcu_fd_sc_mcu9t5v0__xor3_2.functional.pp.v | 1,583 | module MODULE1( VAR13, VAR3, VAR16, VAR17, VAR2, VAR19 );
input VAR3, VAR13, VAR16;
inout VAR2, VAR19;
output VAR17;
wire VAR8;
and VAR14( VAR8, VAR3, VAR13, VAR16 );
wire VAR15;
not VAR7( VAR15, VAR13 );
wire VAR9;
not VAR21( VAR9, VAR16 );
wire VAR1;
and VAR4( VAR1, VAR15, VAR9, VAR3 );
wire VAR11;
not VAR5( VAR11, V... | apache-2.0 |
lvd2/zxevo | fpga/sdload/trunk/video/video_fetch.v | 3,455 | module MODULE1(
input wire clk,
input wire VAR7, input wire VAR1,
input wire VAR13,
input wire VAR9, input wire VAR6,
output reg VAR4,
input wire [15:0] VAR10, input wire VAR3, output reg VAR5,
output reg [63:0] VAR11
);
reg [3:0] VAR8;
reg [1:0] VAR2; reg VAR12;
reg [15:0] VAR14 [0:3];
always @(posedge clk)
if( VAR9 &... | gpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/ExUnit.v | 14,399 | module MODULE1(
VAR101, reset,
VAR148, VAR133,
VAR59, VAR68,
VAR26,
VAR184, VAR140,
VAR193, VAR94,
VAR77
);
input VAR101; input reset;
output[31:0] VAR148; inout[127:0] VAR133; output VAR59; output VAR68; input VAR26;
output[31:0] VAR184; inout[31:0] VAR140; output VAR193; output VAR94; input[1:0] VAR77;
assign VAR148 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b_1.v | 2,209 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR9 ,
VAR3 ,
VAR8,
VAR10,
VAR7 ,
VAR6
);
output VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR10;
input VAR7 ;
input VAR6 ;
VAR1 VAR4 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE... | apache-2.0 |
sh-chris110/chris | FPGA/chris.bak/Qsys/soc_design/synthesis/soc_design.v | 30,586 | module MODULE1 (
input wire VAR5, input wire VAR143, input wire VAR130, output wire VAR207 );
wire VAR96; wire [31:0] VAR122; wire VAR174; wire VAR241; wire [17:0] VAR77; wire [3:0] VAR167; wire VAR87; wire VAR111; wire VAR197; wire [31:0] VAR38; wire [3:0] VAR106; wire [31:0] VAR133; wire VAR48; wire [17:0] VAR230; wi... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_sig_bot_b.v | 81,006 | module MODULE1(VAR143 ,VAR265 ,VAR235 ,VAR244 ,
VAR268 ,VAR12 ,VAR193 ,VAR245 ,VAR79 ,
VAR62 ,VAR304 ,VAR83 ,VAR333 ,
VAR401 ,VAR305 ,VAR314 ,VAR349 ,
VAR182 ,VAR392 ,VAR118 ,VAR269 ,
VAR44 ,VAR337 ,VAR217 ,VAR46 ,VAR66 ,
VAR60 ,VAR339 ,VAR243 ,VAR81 ,VAR380 ,
VAR32 ,VAR406 ,VAR172 ,VAR4 ,
VAR71 ,VAR398 ,VAR323 ,VAR264... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.symbol.v | 1,393 | module MODULE1 (
input VAR9,
input VAR4,
input VAR3,
input VAR1,
input VAR2,
output VAR8
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR10 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2_qpram32_ss.v | 1,928 | module MODULE1 #(
parameter VAR17 = 11
) (
input VAR10,
input [VAR17-1:0] VAR12,
output [31:0] VAR11,
input [VAR17-1:0] VAR22,
output [31:0] VAR1,
input [VAR17-1:0] VAR18,
output [31:0] VAR24,
input [VAR17-1:0] VAR21,
output [31:0] VAR16,
input VAR6,
input [VAR17-1-1:0] VAR5,
input [63:0] VAR19
);
wire [63:0] VAR4;
wir... | lgpl-3.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/ip/edge_detect/altera_edge_detector.v | 2,382 | module MODULE1 #(
parameter VAR18 = 0, parameter VAR16 = 0, parameter VAR19 = 0 ) (
input clk,
input VAR10,
input VAR17,
output VAR13
);
localparam VAR11 = 0, VAR1 = 1, VAR12 = 2;
localparam VAR9 = VAR16 ? 1'b1 : 1'b0;
localparam VAR5 = VAR16 ? 1'b0 : 1'b1;
reg [1:0] state, VAR15;
reg VAR2;
wire VAR3;
assign VAR3 = (VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb.behavioral.v | 1,532 | module MODULE1 (
VAR4 ,
VAR3,
VAR5,
VAR7 ,
VAR8
);
output VAR4 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR8 ;
supply1 VAR11;
supply0 VAR2;
supply1 VAR10 ;
supply0 VAR6 ;
wire VAR12;
wire VAR14;
nand VAR1 (VAR12, VAR8, VAR7 );
or VAR13 (VAR14, VAR5, VAR3, VAR12);
buf VAR9 (VAR4 , VAR14 );
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb_asfifo_xilinx.v | 1,960 | module MODULE1 #(
parameter VAR19 = 18,
parameter VAR3 = 11
) (
output [17:0] VAR25,
output VAR8,
input VAR4,
input VAR17,
input [17:0] VAR7,
output VAR33,
input VAR28,
input VAR32,
input VAR10
);
wire VAR21;
wire VAR27;
VAR16 #(
.VAR19(9),
.VAR35("VAR14")
) VAR1 (
.VAR15(),
.VAR13(),
.VAR11(VAR25[7:0]),
.VAR29(VAR25[8... | lgpl-3.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_gpu_dma.v | 30,149 | module MODULE1 (
VAR124, VAR45,
VAR32, VAR52, VAR27, VAR113,
VAR56, VAR131,
VAR93, VAR53, VAR44, VAR62, VAR100, VAR47, VAR5, VAR99, VAR10, VAR19, VAR90, VAR63, VAR110,
VAR106,
VAR69,
VAR16,
VAR23, VAR129, VAR103, VAR101,
VAR39, VAR60 );
output VAR124; output VAR45;
output [VAR67:0] VAR32; output [15:0] VAR52; output VA... | bsd-3-clause |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/mega/ram_16x8k.v | 7,533 | module MODULE1 (
address,
VAR3,
VAR22,
VAR34,
VAR5,
VAR42,
VAR56);
input [12:0] address;
input [1:0] VAR3;
input VAR22;
input VAR34;
input [15:0] VAR5;
input VAR42;
output [15:0] VAR56;
tri1 [1:0] VAR3;
tri1 VAR22;
tri1 VAR34;
wire [15:0] VAR7;
wire [15:0] VAR56 = VAR7[15:0];
VAR47 VAR19 (
.VAR49 (address),
.VAR29 (VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode.symbol.v | 1,245 | module MODULE1 (
input VAR1
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/ff_jbi_sc2_1.v | 3,300 | module MODULE1(
VAR20, VAR8, VAR3,
VAR11, VAR10, VAR14,
VAR24, VAR30,
VAR9, VAR29,
VAR25, VAR32, VAR31, VAR6,
VAR1, VAR17, VAR13,
VAR12, VAR27, VAR23, VAR26, VAR7
);
output [31:0] VAR20;
output [31:0] VAR8;
output [6:0] VAR3;
output VAR11;
output VAR10;
output VAR14;
output VAR24;
output VAR30;
output VAR9;
input [31:0... | gpl-2.0 |
richard42/CoCo3FPGA | PH2_CLK_bb.v | 2,935 | module MODULE1 (
VAR2,
VAR1);
input VAR2;
output VAR1;
endmodule | bsd-3-clause |
aselectroworks/HDL | rtl/verilog/fs_counter.v | 4,026 | module MODULE1(
VAR3
, VAR8
, VAR2
, VAR4
);
input VAR3; input VAR8; input VAR2; output [3:0] VAR4;
reg [9:0] VAR6;
reg [9:0] VAR1;
reg [2:0] VAR7;
always @ (posedge VAR2 or negedge VAR3) begin
if(VAR2) begin
VAR7[0] <= 1'b0;
end
else begin
VAR7[2:0] <= {VAR7[1:0], VAR8};
end
end
wire VAR5 = (VAR7[1] ^ VAR7[2]) & ~VAR7... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb_2.v | 2,187 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR7 ,
VAR5,
VAR9
);
output VAR8 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR7 ;
input VAR5;
input VAR9;
VAR6 VAR3 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR8 ,
VAR2 ,
VAR1 ,
VAR4,
VAR7
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3_lp.v | 2,206 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR2 ,
VAR10 ,
VAR6,
VAR3,
VAR9 ,
VAR4
);
output VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR6;
input VAR3;
input VAR9 ;
input VAR4 ;
VAR8 VAR1 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/pps_wb.v | 9,110 | module MODULE1
(
VAR26,VAR25,
VAR17,
VAR9,VAR1,VAR22,VAR24,
VAR28,VAR3,VAR11,
VAR2,VAR21,VAR10,
VAR23,VAR4,
VAR15,VAR16,VAR18,VAR13
);
parameter VAR20 = VAR27;
input VAR26;
input VAR25;
input [31:0] VAR17; input VAR9;
input [6:0] VAR1;
input [1:0] VAR22;
input [31:0] VAR24;
input [VAR8-1:0] VAR28; input VAR11; input [3... | mit |
defano/digital-design | knight-rider/rtl/knight-rider.v | 2,192 | module MODULE1 (
clk,
reset,
VAR4);
input clk;
input reset;
output [7:0] VAR4;
reg [20:0] VAR2;
reg [7:0] VAR4;
reg VAR3;
assign VAR1 = VAR2 == 21'h1FFFFF;
always@ (posedge clk or negedge reset)
if (!reset)
VAR2 <= 21'h0;
else
VAR2 <= VAR2 + 1;
always@ (posedge clk or negedge reset)
if (!reset)
VAR4[7:0] <= 8'b10000000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3b/sky130_fd_sc_lp__nor3b.pp.blackbox.v | 1,348 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR7 ,
VAR5,
VAR1,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR1;
input VAR8 ;
input VAR2 ;
endmodule | apache-2.0 |
hhuang25/uwaterloo_ece224 | ANT - Copy/seven_seg_middle_pio.v | 2,206 | module MODULE1 (
address,
VAR6,
clk,
VAR9,
VAR2,
VAR8,
VAR1,
VAR7
)
;
output [ 15: 0] VAR1;
output [ 15: 0] VAR7;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR9;
input VAR2;
input [ 15: 0] VAR8;
wire VAR3;
reg [ 15: 0] VAR5;
wire [ 15: 0] VAR1;
wire [ 15: 0] VAR4;
wire [ 15: 0] VAR7;
assign VAR3 = 1;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.pp.blackbox.v | 1,254 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4 ,
VAR7,
VAR6,
VAR3 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR7;
input VAR6;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.functional.v | 1,344 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR1;
not VAR5 (VAR1, VAR4 );
buf VAR3 (VAR2 , VAR1 );
endmodule | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/paraPortAlloc_st1.v | 1,985 | module MODULE1(
VAR2,
VAR13,
VAR14,
VAR7,
VAR12,
VAR3,
VAR5
);
input [VAR16-2:0] VAR14;
input [(VAR16-1)*3-1:0] VAR7;
input VAR2, VAR13;
input [VAR4-1:0] VAR12;
output [VAR16-2:0] VAR3, VAR5;
wire [VAR16-2:0] VAR11 [0:2];
wire [VAR16-2:0] VAR9, VAR1, VAR10;
wire [VAR4-1:0] VAR15;
assign VAR11 [0] = VAR7 [0+:4];
assign ... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly_32.v | 6,412 | module MODULE1(
enable,
VAR15,
VAR4,
VAR23,
VAR42,
VAR21,
VAR19,
VAR40,
VAR59,
VAR52,
VAR45,
VAR32,
VAR3,
VAR16,
VAR36,
VAR37,
VAR25,
VAR54,
VAR8,
VAR9,
VAR26,
VAR51,
VAR66,
VAR18,
VAR53,
VAR38,
VAR50,
VAR49,
VAR41,
VAR27,
VAR31,
VAR5,
VAR56,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7,
VAR65,
VAR35,
o10,
o11,
o12,
o13,
o14,
o15,
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn_1.v | 2,374 | module MODULE2 (
VAR9 ,
VAR4,
VAR7 ,
VAR1 ,
VAR6 ,
VAR5 ,
VAR3 ,
VAR2
);
output VAR9 ;
input VAR4;
input VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
VAR8 VAR10 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf_16.v | 1,999 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR7,
VAR2,
VAR6 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR6 ;
input VAR1 ;
VAR8 VAR5 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR7;
supply0 VAR2;... | apache-2.0 |
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