repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
bangonkali/sram | i2c_sram_embedded.v | 8,345 | module MODULE1 (
VAR3,
VAR38,
VAR35,
VAR7,
VAR20,
state,
VAR29
);
inout VAR3;
input VAR38;
wire VAR34;
reg VAR33;
reg VAR4;
input [6:0] VAR35;
output reg [6:0] VAR20;
reg [7:0] VAR18;
output reg VAR29;
reg [8:0] counter;
output reg [32:0] state;
output reg [7:0] VAR7;
assign VAR34 = VAR3;
assign VAR3 = VAR33 ? VAR4: 1'... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N16_R4_P4_syn.v | 3,578 | module MODULE1 ( VAR13, VAR22, VAR28, VAR65, VAR6 );
input [8:0] VAR13;
input [8:0] VAR22;
output [8:0] VAR65;
input VAR28;
output VAR6;
wire VAR50, VAR39, VAR43, VAR83, VAR4, VAR5, VAR63, VAR11;
VAR46 VAR15 ( .VAR13(VAR13[3]), .VAR22(VAR22[3]), .VAR12(VAR43) );
VAR25 VAR70 ( .VAR61(VAR13[1]), .VAR72(VAR22[1]), .VAR8(V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.blackbox.v | 1,268 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR7 ;
input VAR3;
supply1 VAR6;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
mbus/mbus | layer_controller_v3/verilog/int_action_rom.v | 9,818 | module MODULE1 #(
parameter VAR19 = 13
)
(
output [VAR13*VAR19-1:0] VAR14,
output [(VAR11*3)*VAR19-1:0] VAR9,
output [2*VAR19-1:0] VAR5
);
wire [VAR13-1:0] VAR29 [0:VAR19-1];
wire [(VAR11*3)-1:0] VAR21 [0:VAR19-1];
wire [1:0] VAR15 [0:VAR19-1];
genvar VAR6;
generate
for (VAR6=0; VAR6<VAR19; VAR6=VAR6+1)
begin: VAR17
as... | apache-2.0 |
sundw2014/sdr-transmiter | software/AD9708_FPGA/ROM_Sin.v | 6,348 | module MODULE1 (
address,
VAR42,
VAR49);
input [15:0] address;
input VAR42;
output [7:0] VAR49;
tri1 VAR42;
wire [7:0] VAR18;
wire [7:0] VAR49 = VAR18[7:0];
VAR32 VAR20 (
.VAR1 (address),
.VAR36 (VAR42),
.VAR13 (VAR18),
.VAR38 (1'b0),
.VAR25 (1'b0),
.VAR4 (1'b1),
.VAR39 (1'b0),
.VAR26 (1'b0),
.VAR45 (1'b1),
.VAR43 (1'b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf_m.v | 1,990 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR1,
VAR3,
VAR2 ,
VAR5
);
output VAR8 ;
input VAR4 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR5 ;
VAR6 VAR7 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR8,
VAR4
);
output VAR8;
input VAR4;
supply1 VAR1;
supply0 VAR3;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b.behavioral.pp.v | 1,989 | module MODULE1 (
VAR14 ,
VAR1 ,
VAR3 ,
VAR10,
VAR7,
VAR9 ,
VAR12
);
output VAR14 ;
input VAR1 ;
input VAR3 ;
input VAR10;
input VAR7;
input VAR9 ;
input VAR12 ;
wire VAR2 ;
wire VAR13 ;
wire VAR11;
not VAR15 (VAR2 , VAR1 );
and VAR6 (VAR13 , VAR2, VAR3 );
VAR8 VAR5 (VAR11, VAR13, VAR10, VAR7);
buf VAR4 (VAR14 , VAR11 )... | apache-2.0 |
tommythorn/yari | DE2-70/rtl/ssram_ctrl.v | 9,869 | module MODULE1
(input wire VAR22
,input wire reset
,output VAR30
,input [1:0] VAR52
,input [29:0] VAR21 ,input VAR34
,input VAR40
,input [31:0] VAR11
,input [3:0] VAR50
,output reg [31:0] VAR15
,output reg [1:0] VAR10 = 0
,output wire VAR3
,output reg VAR38 = 1 ,output reg VAR58 = 1 ,output reg [18:0] VAR35 = 0
,output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbp/sky130_fd_sc_ms__dlrbp.pp.blackbox.v | 1,440 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR3,
VAR7 ,
VAR6 ,
VAR1 ,
VAR4 ,
VAR8 ,
VAR2
);
output VAR9 ;
output VAR5 ;
input VAR3;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
endmodule | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/radio-86rk/src/rk_kbd.v | 4,868 | module MODULE1(
input clk,
input reset,
input VAR13,
input VAR1,
input[7:0] addr,
output reg[7:0] VAR5,
output reg VAR6,
output reg VAR2,
output[2:0] VAR7);
reg[7:0] VAR9[10:0];
assign VAR7 = VAR9[8][2:0];
always @(addr,VAR9) begin
VAR5 =
(VAR9[0] & {8{addr[0]}})|
(VAR9[1] & {8{addr[1]}})|
(VAR9[2] & {8{addr[2]}})|
(VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3b/sky130_fd_sc_ms__nor3b.functional.pp.v | 1,995 | module MODULE1 (
VAR14 ,
VAR12 ,
VAR16 ,
VAR5 ,
VAR3,
VAR13,
VAR9 ,
VAR4
);
output VAR14 ;
input VAR12 ;
input VAR16 ;
input VAR5 ;
input VAR3;
input VAR13;
input VAR9 ;
input VAR4 ;
wire VAR6 ;
wire VAR10 ;
wire VAR8;
nor VAR15 (VAR6 , VAR12, VAR16 );
and VAR7 (VAR10 , VAR5, VAR6 );
VAR11 VAR1 (VAR8, VAR10, VAR3, VAR1... | apache-2.0 |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider.v | 4,048 | module MODULE1
(
input clk,
output VAR4,
output VAR5,
output VAR1
);
VAR3 VAR2
(
.clk(clk),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai_lp.v | 2,449 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR6 ,
VAR10 ,
VAR9 ,
VAR2 ,
VAR5,
VAR8,
VAR12 ,
VAR4
);
output VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR10 ;
input VAR9 ;
input VAR2 ;
input VAR5;
input VAR8;
input VAR12 ;
input VAR4 ;
VAR11 VAR1 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VA... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v | 1,678 | module MODULE1 #(parameter VAR6(VAR3), parameter VAR6(VAR14))
(input VAR20
, input VAR17
, input VAR2
, input [VAR3-1:0] VAR12
, input [VAR14-1:0] VAR9
, input VAR10
, output [VAR3-1:0] VAR21
, output VAR18
, output VAR4
);
wire [VAR14-1:0] VAR7;
wire VAR22 = (!VAR7);
wire VAR19 = VAR22 & VAR2;
VAR15 #(.VAR1(VAR14), .V... | bsd-3-clause |
mshaklunov/usb_devtrsac | rtl/usb_fifo_sync.v | 3,196 | module MODULE1 #(
parameter VAR5=4,
parameter VAR14=0,
parameter VAR18=0
)
(
input clk,
input VAR21,
input VAR12,
input VAR9,
input[(1<<VAR14)-1:0] VAR13,
input VAR17,
output[(1<<VAR18)-1:0] VAR3,
output VAR2,
output VAR1
);
localparam VAR11= 1<<VAR5;
reg[VAR11-1:0] VAR16;
reg[VAR5:VAR14] VAR6;
reg[VAR5:VAR18] VAR19;
g... | mit |
kyzhai/NUNY | src/hardware/moon.v | 6,344 | module MODULE1 (
address,
VAR24,
VAR37);
input [11:0] address;
input VAR24;
output [11:0] VAR37;
tri1 VAR24;
wire [11:0] VAR12;
wire [11:0] VAR37 = VAR12[11:0];
VAR21 VAR18 (
.VAR31 (address),
.VAR32 (VAR24),
.VAR28 (VAR12),
.VAR7 (1'b0),
.VAR1 (1'b0),
.VAR40 (1'b1),
.VAR17 (1'b0),
.VAR47 (1'b0),
.VAR33 (1'b1),
.VAR4 (... | gpl-2.0 |
SymbiFlow/prjxray-experiments-archive-2017 | bram_rom/top.v | 23,591 | module MODULE2(input clk, VAR103, VAR62, output do);
localparam integer VAR71 = 256;
localparam integer VAR7 = 256;
reg [VAR71-1:0] din;
wire [VAR7-1:0] dout;
reg [VAR71-1:0] VAR109;
reg [VAR7-1:0] VAR182;
always @(posedge clk) begin
VAR109 <= {VAR109, VAR62};
VAR182 <= {VAR182, VAR109[VAR71-1]};
if (VAR103) begin
din ... | isc |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_rx_frame_sync.v | 4,493 | module MODULE1 #
(
parameter VAR5 = 2,
parameter VAR8 = 1,
parameter VAR6 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR4,
output wire VAR7,
output wire VAR9
);
parameter VAR1 = VAR8 > VAR6 ? VAR8 : VAR6;
parameter VAR3 = VAR2(VAR1); | mit |
jmacneal/Design-Project | Display/VGA_Controller/VGA_Audio_PLL.v | 11,713 | module MODULE1 (
VAR38,
VAR13,
VAR51,
VAR50,
VAR41);
input VAR38;
input VAR13;
output VAR51;
output VAR50;
output VAR41;
wire [5:0] VAR6;
wire [0:0] VAR56 = 1'h0;
wire [2:2] VAR7 = VAR6[2:2];
wire [1:1] VAR5 = VAR6[1:1];
wire [0:0] VAR59 = VAR6[0:0];
wire VAR51 = VAR59;
wire VAR50 = VAR5;
wire VAR41 = VAR7;
wire VAR16 ... | gpl-3.0 |
jeremyherbert/real_time_stdev | variance/hdl/variance.v | 3,439 | module MODULE1 #(
parameter VAR1=14, parameter VAR9=7 )
(
input wire [VAR1-1:0] VAR12,
output reg [VAR1*2-1:0] VAR15,
input wire reset,
input wire clk
);
reg [VAR16(VAR4 * VAR13)-1:0] VAR8;
reg [VAR16(VAR18 * VAR13)-1:0] VAR7;
wire [VAR1-1:0] VAR19;
wire VAR3;
VAR14 #(.VAR1(VAR1), .VAR17(VAR13)) VAR5 (
.VAR12(VAR12),
.... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi.symbol.v | 1,397 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR3,
output VAR7
);
supply1 VAR6;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v | 3,955 | module MODULE1 (clk, VAR3, enable, VAR4, VAR2, rst, VAR1, VAR5);
input clk;
input VAR3;
input enable;
input VAR4;
input VAR2;
input rst;
output [31:0] VAR1;
output VAR5;
reg [31:0] VAR6;
wire [31:0] VAR7;
assign VAR7[0] = VAR6[1];
assign VAR7[1] = VAR6[2];
assign VAR7[2] = VAR6[3];
assign VAR7[3] = VAR6[4];
assign VAR7... | mit |
jcrono/sd-host | src/cmd/communication/deserializer.v | 1,335 | module MODULE1(
clk, enable, reset, VAR3, in, out, VAR1 );
parameter VAR5 = 136; parameter VAR4 = 8; parameter VAR2 = 8'hFF;
input clk, enable, reset, in;
input [VAR4-1:0] VAR3;
output reg VAR1;
output reg [VAR5-1:0] out;
reg [VAR4-1:0] counter;
always@(posedge reset) begin
out = 0;
counter = VAR3;
VAR1 = 0;
end
always... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2.functional.pp.v | 1,902 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR4 ,
VAR11 ,
VAR14,
VAR10,
VAR3 ,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR11 ;
input VAR14;
input VAR10;
input VAR3 ;
input VAR7 ;
wire VAR15 ;
wire VAR13;
VAR2 VAR12 (VAR15 , VAR5, VAR4, VAR11 );
VAR8 VAR6 (VAR13, VAR15, VAR14, VAR10);
buf VAR9 (VAR1 , VAR13 );
endmodu... | apache-2.0 |
peteasa/oh | src/common/hdl/oh_par2ser.v | 2,386 | module MODULE1 #(parameter VAR9 = 64, parameter VAR17 = 1, parameter VAR11 = VAR4(VAR9/VAR17) )
(
input clk, input VAR8, input [VAR9-1:0] din, output [VAR17-1:0] dout, output VAR7, input VAR5, input VAR14, input [7:0] VAR13, input VAR16, input VAR6, input VAR10, output VAR15 );
reg [VAR9-1:0] VAR1;
reg [VAR11-1:0] VAR2... | mit |
chimeh/stopwatch_verilog | src/clock_div.v | 2,103 | module MODULE1(input VAR8, input VAR4, output VAR9, output VAR11);
wire VAR10; wire VAR6;
assign VAR9 = VAR10;
assign VAR11 = VAR6;
MODULE3 MODULE1 (.clk(VAR8),
.VAR4(VAR4),
.VAR2(VAR10));
MODULE2 MODULE2(.clk(VAR8),
.VAR4(VAR4),
.VAR5(VAR6));
endmodule
module MODULE3(clk, VAR4, VAR2);
input clk;
input VAR4;
output VAR... | unlicense |
sergev/vak-opensource | hardware/basys3/abacus/divider.v | 1,366 | module MODULE1(
input [7:0] VAR1, input [7:0] VAR7, input clk,
output [7:0] VAR6, output [7:0] VAR5
);
integer VAR2;
reg [7:0] VAR8;
reg [7:0] VAR4;reg [7:0] VAR3;
always @(posedge clk) begin
VAR3 [7:0] = 8'b0; VAR4 [7:0] = VAR1[7:0];
for (VAR2=0;VAR2<=7;VAR2=VAR2+1) begin
VAR3 = VAR3<<1;VAR3[0] = VAR4[7];VAR4 = VAR4<<... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_1.behavioral.pp.v | 18,950 | module MODULE1( VAR37, VAR43, VAR194, VAR72, VAR100, VAR149, VAR220, VAR56 );
input VAR72, VAR194, VAR37, VAR100, VAR43;
inout VAR220, VAR56;
output VAR149;
reg VAR135;
VAR186 VAR271(.VAR37(VAR37),.VAR43(VAR43),.VAR194(VAR194),.VAR72(VAR72),.VAR100(VAR100),.VAR149(VAR149),.VAR220(VAR220),.VAR56(VAR56),.VAR135(VAR135));... | apache-2.0 |
titorgalaxy/lzw | hw/src/StroppedMemory.v | 9,306 | module MODULE1(
VAR32,
VAR55,
VAR35,
VAR27,
VAR34,
VAR14,
reset,
clk
);
parameter VAR12 = VAR52; parameter VAR53 = VAR52; parameter VAR36 = VAR44;
output reg [VAR44-1:0] VAR32;
input [VAR44-1:0] VAR55;
input [VAR44+VAR13-1:0] VAR35; input [VAR37-1:0] VAR27; input VAR34; input VAR14;
input reset;
input clk;
reg [VAR44-1... | gpl-3.0 |
devinacker/sd2snes | verilog/sd2snes_cx4/cx4.v | 27,294 | module MODULE1(
input [7:0] VAR35,
output [7:0] VAR22,
input [12:0] VAR26,
input VAR27,
input VAR17,
input VAR28,
input VAR43,
input [7:0] VAR49,
output [23:0] VAR13,
output VAR30,
input VAR20,
output VAR45,
output [2:0] VAR21,
input VAR48
);
reg [2:0] VAR1;
parameter VAR12 = 2'b00;
parameter VAR54 = 2'b01;
parameter V... | gpl-2.0 |
csturton/wirepatch | system/hardware/cores/or1200/or1200_freeze.v | 6,703 | module MODULE1
(
clk, rst,
VAR8, VAR16, VAR4, VAR32, VAR2, VAR26,
VAR18, VAR24, VAR12,
VAR15, VAR3,
VAR6, VAR9, VAR11, VAR25, VAR20, VAR13,
VAR14, VAR1,
VAR19, VAR28
);
input clk;
input rst;
input [VAR22-1:0] VAR8;
input [VAR31-1:0] VAR16;
input VAR4;
input VAR32;
input VAR2;
input VAR26;
input VAR18;
input VAR15;
inpu... | mit |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_max_sel.v | 3,252 | module MODULE1
(VAR5, VAR19);
parameter VAR1 = 32;
parameter VAR2 = 4;
input [0:VAR1*VAR2-1] VAR5;
output [0:VAR1-1] VAR19;
wire [0:VAR1-1] VAR19;
wire [0:VAR2*VAR1-1] VAR9
VAR14
.VAR18(VAR1))
VAR20
(.VAR17(VAR5),
.VAR3(VAR9));
wire [0:VAR2-1] VAR8;
VAR15
.VAR4(VAR2))
VAR24
(.VAR17(VAR9),
.VAR3(VAR8));
wire [0:VAR2-1] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2_1.v | 2,135 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR4,
VAR8,
VAR2 ,
VAR5
);
output VAR7 ;
input VAR1 ;
input VAR4;
input VAR8;
input VAR2 ;
input VAR5 ;
VAR3 VAR6 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7,
VAR1
);
output VAR7;
input VAR1;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b.behavioral.pp.v | 1,951 | module MODULE1 (
VAR13 ,
VAR10 ,
VAR8 ,
VAR15 ,
VAR2,
VAR7,
VAR16 ,
VAR5
);
output VAR13 ;
input VAR10 ;
input VAR8 ;
input VAR15 ;
input VAR2;
input VAR7;
input VAR16 ;
input VAR5 ;
wire VAR9 ;
wire VAR3 ;
wire VAR11;
not VAR12 (VAR9 , VAR15 );
or VAR4 (VAR3 , VAR8, VAR10, VAR9 );
VAR14 VAR6 (VAR11, VAR3, VAR2, VAR7);... | apache-2.0 |
sh-chris110/chris | FPGA/chris.system.dma.ok/Qsys/soc_design/synthesis/submodules/soc_design_dma.v | 32,931 | module MODULE1 (
VAR63,
clk,
VAR4,
VAR20,
VAR75,
VAR108,
VAR50,
VAR81,
VAR88,
VAR99,
VAR76,
VAR25,
VAR57,
VAR21
)
;
output [ 15: 0] VAR21;
input VAR63;
input clk;
input VAR4;
input [ 2: 0] VAR20;
input VAR75;
input VAR108;
input [ 25: 0] VAR50;
input VAR81;
input [ 15: 0] VAR88;
input VAR99;
input [ 25: 0] VAR76;
input... | gpl-2.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10f/dsp_map.v | 4,730 | module \VAR7 (input [19:0] VAR2, input [17:0] VAR20, output [37:0] VAR17);
parameter VAR32 = 0;
parameter VAR22 = 0;
parameter VAR34 = 0;
parameter VAR1 = 0;
parameter VAR37 = 0;
wire [19:0] VAR12;
wire [17:0] VAR24;
wire [37:0] VAR16;
assign VAR12 = (VAR34 == 20) ? VAR2 :
(VAR32) ? {{(20 - VAR34){VAR2[VAR34-1]}}, VAR2... | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/alt_mem_ddrx_ecc_decoder_64_syn.v | 58,593 | module MODULE2
(
VAR121,
VAR165) ;
input [6:0] VAR121;
output [127:0] VAR165;
tri0 [6:0] VAR121;
wire [5:0] VAR61;
wire VAR169;
wire VAR250;
wire [127:0] VAR202;
wire [63:0] VAR129;
wire [63:0] VAR145;
wire [3:0] VAR155;
wire [3:0] VAR150;
wire [3:0] VAR181;
wire [3:0] VAR133;
wire [3:0] VAR157;
wire [3:0] VAR184;
wire... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_mem.v | 6,531 | module MODULE1 (
VAR3, VAR6,
VAR23, VAR16, VAR20, VAR34, clk,
VAR13, VAR15, VAR28, VAR12
);
output [255:0] VAR3;
output [64:0] VAR6;
input [4:0] VAR23; input [3:0] VAR16;
input [63:0] VAR20;
input VAR34;
input clk;
input [3:0] VAR13;
input [4:0] VAR15;
input VAR28;
input VAR12;
wire VAR29;
wire VAR14;
wire VAR33;
wire ... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/gpif/gpmc16_to_fifo36.v | 2,190 | module MODULE1
parameter VAR25 = 9,
parameter VAR44 = 128
)
(
input VAR6, input VAR27,
input [15:0] VAR5,
input valid,
output reg ready,
input VAR9, input VAR23,
output [35:0] VAR35,
output VAR31,
input VAR26
);
wire [35:0] VAR43;
wire VAR21, VAR10;
wire [18:0] VAR38;
wire VAR20, VAR30;
wire [15:0] VAR1;
always @(posed... | gpl-2.0 |
everskar2013/PentiumX | Hardware/Code/led_Dev_IO.v | 1,260 | module MODULE1(
clk,
rst,
VAR1,
VAR6,
VAR4,
VAR2,
VAR3
);
input wire clk, rst, VAR1;
input wire [31: 0] VAR6;
output wire [ 7: 0] VAR2;
output reg [ 1: 0] VAR4 = 0;
output reg [21: 0] VAR3 = 0;
reg [ 7: 0] VAR5 = 0;
assign VAR2 = VAR5;
always @(negedge clk or posedge rst) begin
if( rst ) begin
VAR5 <= 8'hAA;
VAR4 <= 2'... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_4.functional.pp.v | 1,066 | module MODULE1( VAR6, VAR5, VAR7, VAR4, VAR2 );
input VAR7, VAR5;
inout VAR4, VAR2;
output VAR6;
wire VAR9;
not VAR8( VAR9, VAR7 );
wire VAR3;
not VAR1( VAR3, VAR5 );
and VAR10( VAR6, VAR9, VAR3 );
endmodule | apache-2.0 |
solowandererY2K/FPGA-Quantum-Compiler | src/squarer_bb.v | 3,523 | module MODULE1 (
VAR2,
VAR1);
input [39:0] VAR2;
output [79:0] VAR1;
endmodule | mit |
glennchid/font5-firmware | src/verilog/synthesis/data_processing.v | 28,330 | module MODULE1(
input clk,
input rst,
input VAR15,
input [12:0] VAR88,
input [12:0] VAR37,
input [12:0] VAR18,
input [12:0] VAR50,
input VAR113,
input VAR64,
input VAR116,
input VAR77,
input VAR95,
input VAR107,
input [12:0] VAR20,
input [6:0] VAR90,
input [14:0] VAR3,
input VAR60,
input [6:0] VAR108,
input [14:0] VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4.functional.v | 1,312 | module MODULE1 (
VAR2,
VAR5,
VAR8,
VAR1,
VAR7
);
output VAR2;
input VAR5;
input VAR8;
input VAR1;
input VAR7;
wire VAR6;
nand VAR3 (VAR6, VAR7, VAR1, VAR8, VAR5 );
buf VAR4 (VAR2 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.blackbox.v | 1,322 | module MODULE1 (
VAR3,
VAR6
);
output VAR3;
input VAR6;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_31.v | 22,983 | module MODULE3 (
clk,
reset,
VAR85,
VAR95,
VAR174,
VAR26,
VAR110
);
parameter VAR178 = 18;
parameter VAR92 = 31;
parameter VAR86 = 16;
localparam VAR140 = 37;
input clk;
input reset;
input VAR85;
input VAR95;
input [VAR178-1:0] VAR174; output VAR26;
output [VAR178-1:0] VAR110;
localparam VAR124 = 18; localparam VAR171 ... | mit |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ip/block_design_xbar_0/synth/block_design_xbar_0.v | 13,320 | module MODULE1 (
VAR25,
VAR8,
VAR58,
VAR123,
VAR72,
VAR71,
VAR30,
VAR127,
VAR47,
VAR125,
VAR69,
VAR110,
VAR122,
VAR45,
VAR118,
VAR103,
VAR76,
VAR49,
VAR41,
VAR14,
VAR15,
VAR97,
VAR67,
VAR126,
VAR120,
VAR81,
VAR62,
VAR50,
VAR132,
VAR40,
VAR12,
VAR59,
VAR94,
VAR11,
VAR89,
VAR1,
VAR38,
VAR52,
VAR5,
VAR4
);
input wire VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3.functional.v | 1,308 | module MODULE1 (
VAR5,
VAR2,
VAR4,
VAR6
);
output VAR5;
input VAR2;
input VAR4;
input VAR6;
wire VAR3;
xnor VAR7 (VAR3, VAR2, VAR4, VAR6 );
buf VAR1 (VAR5 , VAR3 );
endmodule | apache-2.0 |
franmolinaca/papiGB | rtl/bios.v | 8,057 | module MODULE1
(
input wire VAR3,
input wire [7:0] VAR2,
output reg [7:0] VAR1
);
always @ ( posedge VAR3 )
begin
case ( VAR2 )
8'd0: VAR1 = 8'h31;
8'd1: VAR1 = 8'hFE;
8'd2 : VAR1 = 8'hFF;
8'd3 : VAR1 = 8'hAF;
8'd4 : VAR1 = 8'h21;
8'd5 : VAR1 = 8'hFF;
8'd6 : VAR1 = 8'h9F;
8'd7 : VAR1 = 8'h32;
8'd8 : VAR1 = 8'hCB;
8'd9 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.functional.pp.v | 2,212 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR18 ,
VAR4 ,
VAR11 ,
VAR16 ,
VAR15,
VAR17,
VAR7 ,
VAR6
);
output VAR3 ;
input VAR1 ;
input VAR18 ;
input VAR4 ;
input VAR11 ;
input VAR16 ;
input VAR15;
input VAR17;
input VAR7 ;
input VAR6 ;
wire VAR2 ;
wire VAR12 ;
wire VAR14 ;
wire VAR13;
or VAR19 (VAR2 , VAR11, VAR4 );
or VAR9 (VAR1... | apache-2.0 |
DreamSourceLab/DSLogic-hdl | src/sdramc/sdram_io.v | 4,118 | module MODULE1 (
input VAR39,
input [12:0] VAR26,
input [1:0] VAR56,
input [15:0] VAR40,
output reg [15:0] VAR59,
input VAR44,
input VAR55,
input VAR19,
input VAR32,
input VAR38,
input VAR18,
input VAR33,
output [12:0] VAR28,
output [1:0] VAR47,
output [15:0] VAR23,
input [15:0] VAR49,
output [15:0] VAR17,
output VAR45... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfstp/sky130_fd_sc_hs__sdfstp.blackbox.v | 1,382 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR2
);
input VAR5 ;
input VAR8 ;
output VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR2;
supply1 VAR7;
supply0 VAR6;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_random.v | 5,701 | module MODULE1 (VAR9, VAR12, VAR8, VAR4, VAR5, VAR13, VAR11,
VAR6, VAR10);
input VAR9;
input VAR12;
input VAR8;
input VAR4;
input [3:0] VAR5;
input [15:0] VAR13;
input [9:0] VAR11;
output VAR6;
output VAR10;
wire VAR3;
reg [9:0] VAR2;
wire [9:0] VAR1;
reg [9:0] VAR7;
always @ (posedge VAR9 or posedge VAR12)
begin
if(VA... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/subRecursiveKOA.v | 4,965 | module MODULE1
(
input wire clk,
input wire [VAR12-1:0] VAR21,
input wire [VAR12-1:0] VAR13,
output wire [2*VAR12-1:0] VAR4
);
localparam integer VAR26 = VAR26;
generate
if (VAR12 <= VAR26) begin : VAR28
VAR23 #(.VAR12(VAR12))
VAR27 (
.clk(clk),
.VAR21(VAR21),
.VAR13(VAR13),
.VAR4(VAR4)
);
end else begin : VAR17
reg [2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfstp/sky130_fd_sc_hdll__sdfstp.blackbox.v | 1,426 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR4 ,
VAR3 ,
VAR2 ,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR5;
supply1 VAR9;
supply0 VAR7;
supply1 VAR10 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Chapna/TTCache | src/way.v | 4,321 | module MODULE1 (enable, word, VAR1,
write, rst, VAR11, VAR23, VAR2,
VAR14, VAR12, VAR24,
VAR21, VAR22, ack);
parameter VAR4 = 2;
input enable;
input rst;
input [0:1] word;
input VAR1;
input write;
input rst;
input [0:4] VAR11;
input [0:15] VAR23;
input VAR2;
output reg VAR14;
output reg VAR12;
output reg [0:4] VAR24;
o... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.pp.symbol.v | 1,358 | module MODULE1 (
input VAR1,
input VAR2,
input VAR4 ,
input VAR5 ,
output VAR6 ,
input VAR7,
input VAR3
);
endmodule | apache-2.0 |
yht1995/Digital-WeighingScale | FPGA/DispScan.v | 1,325 | module MODULE1
(
input clk,en,
input [3:0]VAR4,VAR1,VAR8,VAR7,
input VAR5,
output reg [3:0]select,out,
output reg VAR10
);
reg [1:0]state;
localparam VAR2 = 0, VAR9 = 1, VAR3 = 2, VAR6 = 3;
always @ (state or en)
begin
if (en)
begin
case (state)
VAR2:
begin
select <= 4'b0001;
out[3:0] <= VAR4[3:0];
VAR10 <= 0;
end
VAR9... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.functional.v | 1,787 | module MODULE1( VAR16, VAR20, VAR24, VAR7, VAR6, VAR5, VAR3, VAR23 );
input VAR7, VAR24, VAR5, VAR16, VAR6, VAR20, VAR23;
output VAR3;
not VAR2( VAR19, VAR5 );
not VAR21( VAR18, VAR6 );
wire VAR15;
not VAR26( VAR15, VAR24 );
wire VAR22;
not VAR28( VAR22, VAR16 );
wire VAR27;
and VAR11( VAR27, VAR15, VAR22 );
wire VAR8;... | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_trigger_block.v | 8,009 | module MODULE1 #(
parameter VAR8 = 1,
parameter VAR22 = 5,
parameter VAR5 = 1
)
(
input VAR47 , input VAR12 , input [ 14-1: 0] VAR1 , input [ 14-1: 0] VAR43 , output [ 14-1: 0] VAR20 , output [ 14-1: 0] VAR2 , output VAR9 ,
input [ 16-1: 0] addr,
input VAR6,
input VAR19,
output reg ack,
output reg [ 32-1: 0] VAR42,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/fill/sky130_fd_sc_hvl__fill.behavioral.pp.v | 1,151 | module MODULE1 (
VAR3,
VAR4,
VAR1 ,
VAR2
);
input VAR3;
input VAR4;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
bbrown1867/ObjectTracking | hw/measure/measure.v | 10,655 | module MODULE1(
input VAR133,
input VAR125,
input VAR60,
output [8:0] VAR108,
output [17:0] VAR34,
input [3:0] VAR161,
input [17:0] VAR142,
output [7:0] VAR118,
output VAR164,
output VAR177,
output [7:0] VAR75,
output VAR146,
output [7:0] VAR2,
output VAR13,
output VAR111,
output VAR26,
inout VAR178,
input VAR69,
input... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/route_switch.v | 2,131 | module MODULE1(VAR4, VAR8,
VAR9, VAR7, VAR12,
VAR5, VAR3, VAR2);
parameter VAR1 = 32;
parameter VAR11 = 2;
input VAR4, VAR8;
input [VAR1-1:0] VAR9;
input VAR7;
output VAR12;
output reg [VAR1-1:0] VAR5;
input [VAR11-1:0] VAR3;
output [VAR11-1:0] VAR2;
wire [VAR11-1:0] VAR6;
reg [VAR11-1:0] VAR10;
assign VAR6 = VAR3 & VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b.pp.symbol.v | 1,324 | module MODULE1 (
input VAR3 ,
input VAR7 ,
input VAR2 ,
input VAR6 ,
output VAR1 ,
input VAR5 ,
input VAR9,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
patrick-samy/ace | control/instruction-decoder.v | 1,309 | module MODULE1(input[31:0] VAR17,
output[3:0] VAR10,
output VAR15,
output[1:0] VAR8,
output[7:0] VAR4,
output VAR9,
output[1:0] VAR1,
output[7:0] VAR14,
output[1:0] VAR6);
register#(4) VAR3(VAR17[31:28], 1, VAR10);
register#(1) VAR5(VAR17[27], 1, VAR15);
register#(2) VAR13(VAR17[26:25], 1,
VAR8);
register#(8) VAR7(VAR1... | mit |
bigeagle/riffa | fpga/riffa_hdl/interrupt.v | 7,145 | module MODULE1 #(
parameter VAR38 = 4'd12
)
(
input VAR36,
input VAR3,
input [VAR38-1:0] VAR13, input [VAR38-1:0] VAR20, input [VAR38-1:0] VAR23, input [VAR38-1:0] VAR18, input [VAR38-1:0] VAR29, input VAR14, input VAR10, input [31:0] VAR9, output [31:0] VAR16, output [31:0] VAR26, input VAR37, input VAR30, input VAR4,... | bsd-3-clause |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/mybufg.v | 2,504 | module MODULE1 (
VAR3,
VAR1
);
input VAR3;
output VAR1;
VAR2 VAR4 (VAR1,VAR3);
endmodule | lgpl-3.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/ipcore_dir/gsu_umult.v | 6,162 | module MODULE1 (
VAR29, VAR42, VAR21
);
output [15 : 0] VAR29;
input [7 : 0] VAR42;
input [7 : 0] VAR21;
wire \VAR28/VAR39 ;
wire \VAR18/VAR22<35>VAR12 ;
wire \VAR18/VAR22<34>VAR12 ;
wire \VAR18/VAR22<33>VAR12 ;
wire \VAR18/VAR22<32>VAR12 ;
wire \VAR18/VAR22<31>VAR12 ;
wire \VAR18/VAR22<30>VAR12 ;
wire \VAR18/VAR22<29>... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf.pp.symbol.v | 1,236 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4 ,
input VAR6,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b/RegGPR2.v | 13,821 | module MODULE1(
VAR99, reset,
VAR40, VAR96,
VAR21, VAR98,
VAR76, VAR41,
VAR94, VAR2,
VAR51, VAR44,
VAR71,
VAR104, VAR83,
VAR58, VAR69,
VAR91, VAR86,
VAR16, VAR11,
VAR6, VAR79,
VAR66, VAR85,
VAR82, VAR18,
VAR3, VAR64,
VAR12, VAR107,
VAR52, VAR81,
VAR48, VAR90,
VAR28, VAR70
);
input VAR99;
input reset;
input[6:0] VAR40;
... | mit |
cliffordwolf/picorv32 | picorv32.v | 94,474 | module MODULE1 #(
parameter [ 0:0] VAR31 = 1,
parameter [ 0:0] VAR52 = 1,
parameter [ 0:0] VAR61 = 1,
parameter [ 0:0] VAR114 = 1,
parameter [ 0:0] VAR38 = 0,
parameter [ 0:0] VAR99 = 1,
parameter [ 0:0] VAR48 = 0,
parameter [ 0:0] VAR32 = 0,
parameter [ 0:0] VAR13 = 0,
parameter [ 0:0] VAR34 = 0,
parameter [ 0:0] VAR1... | isc |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_AO_SLVT_FF_210930.v | 231,331 | module MODULE1 (VAR10, VAR2, VAR3, VAR8, VAR4);
output VAR10;
input VAR2, VAR3, VAR8, VAR4;
wire VAR7, VAR9, VAR11;
wire VAR6, VAR1, VAR5;
not (VAR6, VAR4);
not (VAR11, VAR8);
not (VAR9, VAR3);
and (VAR1, VAR9, VAR11);
not (VAR7, VAR2);
and (VAR5, VAR7, VAR11);
or (VAR10, VAR5, VAR1, VAR6); | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_sdb/rtl/axi_sdb.v | 10,282 | module MODULE1 #(
input clk,
input VAR15,
input VAR27,
output reg VAR8,
input [31:0] VAR16,
input [2:0] VAR21,
input VAR11,
output reg VAR25,
input [31:0] VAR24,
input [3:0] VAR4,
output reg VAR29,
input VAR1,
output reg [1:0] VAR30,
input VAR18,
output reg VAR23,
input [31:0] VAR3,
input [2:0] VAR6,
output reg VAR26,
... | mit |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_clock_module.v | 9,432 | module MODULE1 (
VAR41, VAR47, VAR8, VAR31, VAR33, VAR36,
VAR45, VAR17, VAR20, VAR21, VAR38, VAR39, VAR11, VAR37, VAR46, VAR3, VAR29 );
output VAR41; output VAR47; output [15:0] VAR8; output VAR31; output VAR33; output VAR36;
input VAR45; input VAR17; input VAR20; input VAR21; input [7:0] VAR38; input [15:0] VAR39; inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd2/sky130_fd_sc_hs__clkdlyinv3sd2.functional.v | 1,759 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR1,
VAR5
);
output VAR6 ;
input VAR4 ;
input VAR1;
input VAR5;
wire VAR2 ;
wire VAR3;
not VAR10 (VAR2 , VAR4 );
VAR7 VAR8 (VAR3, VAR2, VAR1, VAR5);
buf VAR9 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111a/sky130_fd_sc_hd__o2111a.pp.symbol.v | 1,400 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR5 ,
input VAR4 ,
input VAR6 ,
output VAR1 ,
input VAR7 ,
input VAR9,
input VAR3,
input VAR10
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2_6.v | 2,091 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR2 ,
VAR7,
VAR5,
VAR4 ,
VAR1
);
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR7;
input VAR5;
input VAR4 ;
input VAR1 ;
VAR9 VAR3 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR8,
VAR6,
VAR2
);
output VAR8;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.behavioral.v | 2,671 | module MODULE1 (
VAR16 ,
VAR5 ,
VAR9 ,
VAR6 ,
VAR18 ,
VAR8
);
output VAR16 ;
output VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR18 ;
input VAR8;
supply1 VAR25;
supply0 VAR15;
supply1 VAR17 ;
supply0 VAR24 ;
wire VAR23 ;
wire VAR12 ;
wire VAR28 ;
wire VAR4 ;
wire VAR21;
wire VAR13 ;
reg VAR20 ;
wire VAR14 ;
wire VAR7 ;
wi... | apache-2.0 |
thinkoco/de1_soc_opencl | de1soc_sharedonly_vga/ip/vga_pll/vga_pll.v | 17,417 | module MODULE1 (
input wire VAR3, input wire rst, output wire VAR5, output wire VAR6, output wire VAR4 );
VAR2 VAR1 (
.VAR3 (VAR3), .rst (rst), .VAR5 (VAR5), .VAR6 (VAR6), .VAR4 (VAR4) );
endmodule | apache-2.0 |
parallella/oh | elink/hdl/etx_arbiter.v | 4,463 | module MODULE1 (
VAR25, VAR14, VAR33, VAR12, VAR10,
VAR44,
clk, VAR36, VAR18, VAR52, VAR29, VAR34,
VAR13, VAR39, VAR28, VAR30
);
parameter VAR20 = 32;
parameter VAR53 = 2*VAR20+40;
parameter VAR45 = 0;
input clk;
input VAR36;
input VAR18;
input [VAR53-1:0] VAR52;
output VAR25;
input VAR29;
input [VAR53-1:0] VAR34;
outp... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_ldexp.v | 2,442 | module MODULE1(VAR28, VAR7,
VAR27, VAR19, VAR11,
VAR18, VAR15, VAR22,
VAR4, VAR3, VAR26);
parameter VAR31 = 32;
parameter VAR23 = 64;
input VAR28, VAR7;
input [VAR31-1:0] VAR27, VAR18;
input VAR19, VAR15;
output VAR11, VAR22;
output [VAR31-1:0] VAR4;
output VAR3;
input VAR26;
wire [VAR31-1:0] VAR10, VAR32;
wire VAR24, ... | mit |
hoangt/NOCulator | hring/hw/buffered/src/vcr_la_routing_logic.v | 10,522 | module MODULE1
(clk, reset, VAR23, VAR31, VAR26, VAR7,
VAR12);
parameter VAR14 = 2;
parameter VAR30 = 4;
localparam VAR24 = VAR9(VAR30);
parameter VAR15 = 2;
localparam VAR22 = VAR15 * VAR24;
parameter VAR32 = 1;
localparam VAR33 = VAR9(VAR32);
localparam VAR29 = VAR22 + VAR33;
parameter VAR21 = VAR27;
localparam VAR17... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_wbctl.v | 43,193 | module MODULE1(
VAR73, VAR164, VAR210, VAR145, VAR89,
VAR225, VAR178,
VAR161, VAR171,
VAR53, VAR113,
VAR184, VAR165, VAR39,
VAR197, VAR195, VAR65,
VAR9, VAR69, VAR194,
VAR35, VAR23,
VAR98, VAR56, VAR41,
VAR33, VAR159, VAR156, VAR196, VAR45, VAR188, VAR38,
VAR149, VAR80, VAR215,
VAR18, VAR168, VAR155,
VAR219, VAR139, VA... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/iodelay_ctrl_eco20100428.v | 3,792 | module MODULE1 #
(
parameter VAR12 = 100, parameter VAR7 = "VAR9", parameter VAR8 = 0 )
(
input VAR5,
input VAR15,
output VAR1
);
localparam VAR13 = 31;
wire VAR19;
wire VAR17;
wire VAR11;
reg [VAR13-1:0] VAR14 ;
wire VAR10;
wire VAR4;
assign VAR4 = VAR8 ? ~VAR15: VAR15;
assign VAR19 = VAR5;
assign VAR10 = VAR4;
always... | lgpl-3.0 |
drom/quark | v/mux16.v | 1,027 | module MODULE1 #( parameter VAR8 = 1 ) (
sel,
VAR9,
VAR4,
VAR2,
VAR11,
VAR10,
VAR1,
VAR13,
VAR5,
VAR18,
VAR14,
VAR6,
VAR12,
VAR16,
VAR7,
VAR3,
VAR15,
VAR17
);
input [3:0] sel;
input [VAR8-1:0]
VAR9,
VAR4,
VAR2,
VAR11,
VAR10,
VAR1,
VAR13,
VAR5,
VAR18,
VAR14,
VAR6,
VAR12,
VAR16,
VAR7,
VAR3,
VAR15;
output [VAR8-1:0] VAR17... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai_2.v | 2,361 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR7 ,
VAR5 ,
VAR11 ,
VAR2,
VAR9,
VAR6 ,
VAR10
);
output VAR1 ;
input VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR11 ;
input VAR2;
input VAR9;
input VAR6 ;
input VAR10 ;
VAR4 VAR8 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VA... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T26-rom/rom32x4.v | 1,232 | module MODULE1 (input clk,
input wire [4:0] addr,
output reg [3:0] VAR2);
reg [3:0] VAR1 [0:31];
always @(negedge clk) begin
VAR2 <= VAR1[addr];
end | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.pp.symbol.v | 1,265 | module MODULE1 (
input VAR3 ,
input VAR1,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/soc_system_leds.v | 2,145 | module MODULE1 (
address,
VAR9,
clk,
VAR4,
VAR1,
VAR8,
VAR2,
VAR3
)
;
output [ 7: 0] VAR2;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR4;
input VAR1;
input [ 31: 0] VAR8;
wire VAR5;
reg [ 7: 0] VAR6;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR7;
wire [ 31: 0] VAR3;
assign VAR5 = 1;
assign VAR7 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.behavioral.v | 1,413 | module MODULE1 (
VAR9,
VAR4,
VAR6,
VAR10
);
output VAR9;
input VAR4;
input VAR6;
input VAR10;
supply1 VAR5;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR11 ;
wire VAR2;
nor VAR7 (VAR2, VAR10, VAR4, VAR6 );
buf VAR3 (VAR9 , VAR2 );
endmodule | apache-2.0 |
shangdawei/proxmark3-lcd | fpga/lo_read.v | 3,759 | module MODULE1(
VAR1, VAR18, VAR12,
VAR19, VAR5, VAR21, VAR9, VAR13, VAR17,
VAR20, VAR8,
VAR15, VAR4, VAR10, VAR14,
VAR6, VAR22,
VAR2,
VAR11, VAR7
);
input VAR1, VAR18, VAR12;
output VAR19, VAR5, VAR21, VAR9, VAR13, VAR17;
input [7:0] VAR20;
output VAR8;
input VAR10;
output VAR15, VAR4, VAR14;
input VAR6, VAR22;
output... | gpl-2.0 |
vineeshvs/research | full_adder.v | 1,352 | module MODULE1 (VAR15, b0, VAR24, VAR17, b1, VAR11, VAR29, VAR25, VAR21);
input VAR15;
input b0;
input VAR24;
input VAR17;
input b1;
output VAR11;
output VAR29;
output VAR25;
output VAR1;
output VAR21;
wire VAR5;
wire VAR13;
wire VAR7;
wire VAR1;
wire VAR26;
assign VAR2 = VAR5 | VAR13;
assign VAR29 = VAR7;
VAR3 VAR16 (... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3.behavioral.v | 1,724 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR5,
VAR9
);
output VAR1 ;
input VAR8 ;
input VAR5;
input VAR9;
wire VAR10 ;
wire VAR4;
buf VAR7 (VAR10 , VAR8 );
VAR2 VAR3 (VAR4, VAR10, VAR5, VAR9);
buf VAR6 (VAR1 , VAR4 );
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase4/hsyncModule.v | 1,809 | module MODULE1(VAR3, VAR15, VAR16, VAR1, VAR12, VAR8, VAR10, VAR11, reset, VAR7);
parameter VAR6=10;
input [VAR6-1:0] VAR15, VAR12, VAR1, VAR16;
input VAR3, reset, VAR7;
output VAR8, VAR10;
output reg [VAR6-1:0] VAR11;
wire [VAR6-1:0] VAR4;
VAR9 VAR5(VAR3, VAR14, reset, VAR7);
assign VAR10=VAR4==VAR13; wire [VAR6-1:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd1/sky130_fd_sc_hs__clkdlyinv3sd1.blackbox.v | 1,287 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR4;
supply0 VAR1;
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/axi/mig_7series_v4_0_axi_mc_cmd_translator.v | 9,737 | module MODULE1 #
(
parameter integer VAR23 = 32,
parameter integer VAR11 = 30,
parameter integer VAR9 = 32,
parameter integer VAR16 = 1,
parameter integer VAR28 = 2,
parameter integer VAR7 = 2,
parameter integer VAR15 = 0
)
(
input wire clk ,
input wire reset ,
input wire [VAR23-1:0] VAR27 ,
input wire [7:0] VAR10 ,
in... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/median/prj/solution1/impl/verilog/image_filter.v | 45,290 | module MODULE1 (
VAR217,
VAR137,
VAR209,
VAR23,
VAR17,
VAR218,
VAR109,
VAR12,
VAR76,
VAR24,
VAR156,
VAR48,
VAR250,
VAR47,
VAR237,
VAR16,
VAR284,
VAR111,
VAR128,
VAR155,
VAR330,
VAR221,
VAR317,
VAR208,
VAR172,
VAR95
);
parameter VAR96 = 32'b00000000000000000000000000000000;
parameter VAR129 = 4'b0000;
parameter VAR283 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf_16.v | 2,036 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR3,
VAR5,
VAR2 ,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR3;
input VAR5;
input VAR2 ;
input VAR1 ;
VAR4 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR6,
VAR7
);
output VAR6;
input VAR7;
supply1 VAR3;
supply0 VAR5;... | apache-2.0 |
kyzhai/NUNY | src/hardware/city_bb.v | 4,974 | module MODULE1 (
address,
VAR2,
VAR1);
input [14:0] address;
input VAR2;
output [15:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/conb/sky130_fd_sc_ls__conb.behavioral.v | 1,279 | module MODULE1 (
VAR4,
VAR1
);
output VAR4;
output VAR1;
supply1 VAR7;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR6 ;
pullup VAR3 (VAR4 );
pulldown VAR5 (VAR1 );
endmodule | apache-2.0 |
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