repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap.blackbox.v | 1,216 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/nf2_dma_que_intfc.v | 15,263 | module MODULE1
parameter VAR45 = 32,
parameter VAR51=VAR45/8,
parameter VAR30=64,
parameter VAR29=32
)
(
output reg VAR68,
input [VAR45-1:0] VAR41,
input [VAR51-1:0] VAR24,
output reg VAR50,
input [VAR45-1:0] VAR31,
input [VAR51-1:0] VAR33,
output reg VAR61,
input [VAR45-1:0] VAR76,
input [VAR51-1:0] VAR52,
output reg ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba.pp.symbol.v | 1,383 | module MODULE1 (
input VAR5 ,
input VAR7 ,
input VAR3,
output VAR1 ,
input VAR4 ,
input VAR8,
input VAR6,
input VAR2
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_dq_edgelogic.v | 9,843 | module MODULE1(
VAR50, VAR106, VAR66,
VAR48, VAR40, VAR4,
clk, VAR76, VAR68, VAR51, VAR114, VAR78, VAR85,
VAR99, VAR84, VAR81, VAR104,
VAR42, VAR17,
VAR43, VAR58, VAR103, VAR47, VAR21, VAR2
);
input clk;
input VAR76;
input VAR68;
input VAR51;
input VAR114;
input VAR78;
input VAR85;
input VAR99;
input [1:0] VAR84;
input... | gpl-2.0 |
jhennessy/parallella-hw-old | fpga/hdl/elink/ewrapper_io_tx_slow.v | 7,501 | module MODULE1
(
VAR4, VAR37, VAR15,
VAR33,
VAR63, VAR48, VAR61, VAR41, VAR69, VAR59,
VAR55
);
input VAR63; input VAR48; input VAR61; input VAR41;
input VAR69;
input VAR59;
input [71:0] VAR55;
output [8:0] VAR4;
output [8:0] VAR37;
output VAR15;
output VAR33;
reg [1:0] VAR2;
reg VAR32;
reg VAR47;
reg [8:0] VAR18;
reg [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.pp.symbol.v | 1,330 | module MODULE1 (
input VAR7 ,
input VAR2 ,
input VAR5 ,
input VAR1 ,
output VAR3 ,
input VAR8 ,
input VAR6,
input VAR9,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32ai/sky130_fd_sc_lp__o32ai.blackbox.v | 1,392 | module MODULE1 (
VAR7 ,
VAR4,
VAR6,
VAR5,
VAR8,
VAR1
);
output VAR7 ;
input VAR4;
input VAR6;
input VAR5;
input VAR8;
input VAR1;
supply1 VAR9;
supply0 VAR10;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn.blackbox.v | 1,518 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR4 ,
VAR8 ,
VAR9 ,
VAR2,
VAR12
);
output VAR1 ;
input VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR2;
input VAR12;
supply1 VAR7;
supply1 VAR5 ;
supply0 VAR10 ;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/ip/Dilation/acl_fp_custom_mul_hc_dbl_pumped.v | 6,176 | module MODULE1
(
input logic VAR1,
input logic VAR14,
input logic VAR13,
input logic VAR8,
input logic VAR2,
output logic VAR3,
output logic VAR15,
input logic [VAR7-1:0] VAR5,
input logic [VAR7-1:0] b1,
input logic [VAR7-1:0] VAR11,
input logic [VAR7-1:0] VAR10,
output logic [VAR7-1:0] VAR12,
output logic [VAR7-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.pp.symbol.v | 1,299 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR1 ,
input VAR2 ,
output VAR3 ,
input VAR5 ,
input VAR9,
input VAR8,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.pp.symbol.v | 1,352 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR2 ,
output VAR4 ,
input VAR7 ,
input VAR1,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/sine_table_11bit.v | 70,734 | module MODULE1
(input VAR3,
input [10:0] VAR1,
output reg [31:0] VAR2);
always @(posedge VAR3) begin
case (VAR1)
11'd0: VAR2 = 32'h0;
11'd1: VAR2 = 32'h3e9d1452;
11'd2: VAR2 = 32'h3f1d1422;
11'd3: VAR2 = 32'h3f6b9dba;
11'd4: VAR2 = 32'h3f9d1360;
11'd5: VAR2 = 32'h3fc45783;
11'd6: VAR2 = 32'h3feb9b2c;
11'd7: VAR2 = 32'h... | apache-2.0 |
keith-epidev/VHDL-lib | top/lab_3/part_2/ip/clk_193MHz/clk_193MHz_stub.v | 1,182 | module MODULE1(VAR2, MODULE1, VAR1)
;
input VAR2;
output MODULE1;
output VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.pp.blackbox.v | 1,388 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR3 ,
VAR6,
VAR5 ,
VAR8 ,
VAR4,
VAR9 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR6;
input VAR5 ;
input VAR8 ;
input VAR4;
input VAR9 ;
input VAR1 ;
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/example/ZCU102/fpga/rtl/fpga.v | 16,502 | module MODULE1 (
input wire VAR309,
input wire VAR246,
input wire reset,
input wire VAR136,
input wire VAR276,
input wire VAR63,
input wire VAR252,
input wire VAR22,
input wire [7:0] VAR163,
output wire [7:0] VAR204,
input wire VAR131,
output wire VAR119,
input wire VAR17,
output wire VAR230,
input wire VAR137,
input w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4b/sky130_fd_sc_lp__nand4b.behavioral.v | 1,528 | module MODULE1 (
VAR7 ,
VAR4,
VAR13 ,
VAR6 ,
VAR12
);
output VAR7 ;
input VAR4;
input VAR13 ;
input VAR6 ;
input VAR12 ;
supply1 VAR3;
supply0 VAR10;
supply1 VAR1 ;
supply0 VAR5 ;
wire VAR11 ;
wire VAR9;
not VAR14 (VAR11 , VAR4 );
nand VAR2 (VAR9, VAR12, VAR6, VAR13, VAR11);
buf VAR8 (VAR7 , VAR9 );
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/keygen/rloc_272_4/key_gen.v | 1,318 | module MODULE1(
clk,
reset,
VAR2,
VAR6,
VAR3,
VAR5,
VAR1,
VAR8,
VAR4,
VAR7
);
input clk;
input reset;
input VAR2;
input [7:0] VAR6;
input [127:0] VAR3;
input [127:0] VAR5;
input [7:0] VAR1;
input VAR8;
output VAR4;
output [107:0] VAR7;
reg VAR4;
reg [107:0] VAR7;
always @ (posedge clk or negedge reset)
begin
if(!reset)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.behavioral.pp.v | 1,867 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR10,
VAR6,
VAR3 ,
VAR11
);
output VAR7 ;
input VAR2 ;
input VAR10;
input VAR6;
input VAR3 ;
input VAR11 ;
wire VAR1 ;
wire VAR4;
not VAR8 (VAR1 , VAR2 );
VAR9 VAR12 (VAR4, VAR1, VAR10, VAR6);
buf VAR5 (VAR7 , VAR4 );
endmodule | apache-2.0 |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/Controller.v | 14,968 | module MODULE1(
input VAR9,VAR34,
input [31:0] VAR43,
input [1:0] VAR24,
output reg[2:0] VAR8,VAR33,
output reg[3:0] VAR40,VAR21,VAR37,
output reg[1:0] VAR30,VAR25,VAR19,VAR1,
output reg VAR13,VAR6,VAR2,VAR38,VAR20,VAR27,VAR5,VAR26,VAR4,
output reg VAR42,
output [3:0]VAR11
);
reg VAR34;
wire VAR18;
assign VAR18 = VAR34... | gpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_txethmac.v | 17,810 | module MODULE1 (VAR86, VAR5, VAR75, VAR68, VAR31, VAR59, VAR77,
VAR57, VAR63, VAR27, VAR9, VAR62, VAR91, VAR83, VAR18, VAR89,
VAR93, VAR39, VAR7, VAR25, VAR73, VAR79,
VAR30, VAR52, VAR24, VAR6, VAR43, VAR65, VAR80, VAR85,
VAR42, VAR14, VAR36, VAR10, VAR56,
VAR46, VAR17, VAR4, VAR8
);
parameter VAR22 = 1;
input VAR86; i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21boi/sky130_fd_sc_hdll__a21boi.functional.pp.v | 2,194 | module MODULE1 (
VAR13 ,
VAR1 ,
VAR8 ,
VAR5,
VAR4,
VAR2,
VAR11 ,
VAR9
);
output VAR13 ;
input VAR1 ;
input VAR8 ;
input VAR5;
input VAR4;
input VAR2;
input VAR11 ;
input VAR9 ;
wire VAR6 ;
wire VAR12 ;
wire VAR15 ;
wire VAR14;
not VAR18 (VAR6 , VAR5 );
and VAR7 (VAR12 , VAR1, VAR8 );
nor VAR3 (VAR15 , VAR6, VAR12 );
VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.functional.v | 1,666 | module MODULE1( VAR17, VAR19, VAR4, VAR15, VAR7, VAR1 );
input VAR4, VAR17, VAR19, VAR1, VAR7;
output VAR15;
wire VAR16;
not VAR6( VAR16, VAR4 );
wire VAR10;
not VAR14( VAR10, VAR17 );
wire VAR12;
not VAR21( VAR12, VAR19 );
wire VAR5;
and VAR18( VAR5, VAR16, VAR10, VAR12 );
wire VAR11;
not VAR9( VAR11, VAR1 );
wire VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.functional.pp.v | 2,306 | module MODULE1 (
VAR11 ,
VAR14 ,
VAR22 ,
VAR20 ,
VAR7 ,
VAR4 ,
VAR15,
VAR9 ,
VAR21 ,
VAR8 ,
VAR5
);
output VAR11 ;
output VAR14 ;
input VAR22 ;
input VAR20 ;
input VAR7 ;
input VAR4 ;
input VAR15;
input VAR9 ;
input VAR21 ;
input VAR8 ;
input VAR5 ;
wire VAR3 ;
wire VAR1 ;
wire VAR13;
not VAR2 (VAR1 , VAR15 );
VAR16 VA... | apache-2.0 |
lvd2/ngs | fpga/current/ports/ports.v | 15,852 | module MODULE1(
input wire VAR85,
input wire VAR56,
input wire [ 7:0] din, output reg [ 7:0] dout, output reg VAR77, input wire [15:0] VAR29,
input wire VAR87,
input wire VAR122,
input wire VAR137,
input wire VAR102,
input wire [ 7:0] VAR72, output reg [ 7:0] VAR12, input wire [ 7:0] VAR41,
input wire VAR35, input wire... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.pp.blackbox.v | 1,405 | module MODULE1 (
VAR4,
VAR6 ,
VAR7 ,
VAR2 ,
VAR8 ,
VAR5 ,
VAR3 ,
VAR1
);
input VAR4;
input VAR6 ;
input VAR7 ;
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
titets/MILL | rtl/stages.v | 1,966 | module MODULE1(
input wire [VAR7-1:0] VAR1,
input wire [VAR2-1:0] VAR16,
input wire VAR13,
output reg [VAR15-1:0] VAR9, VAR12, VAR8,
output reg VAR3, VAR10, VAR4, VAR17
);
reg VAR5;
VAR20 VAR3 = 1'b0;
VAR20 VAR17 = 1'b0;
VAR20 VAR4 = 1'b0;
VAR20 VAR5 = 1'd0;
always @(VAR16) begin
VAR10 = 1'b0;
if(VAR16 == VAR14) begin
... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_axic_srl_fifo.v | 8,230 | module MODULE1 #
(
parameter VAR39 = "none", parameter integer VAR4 = 1, parameter integer VAR5 = 33, parameter integer VAR32 = 2, parameter VAR7 = 1 )
(
input wire VAR15, input wire VAR36, input wire [VAR4-1:0] VAR33, input wire VAR16, output wire VAR10, output wire [VAR4-1:0] VAR12, output wire VAR8, input wire VAR25... | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_mig_7series_0_0/system_mig_7series_0_0/user_design/rtl/controller/mig_7series_v4_0_rank_common.v | 20,639 | module MODULE1 #
(
parameter VAR28 = 100,
parameter VAR102 = "VAR103",
parameter VAR96 = 40,
parameter VAR48 = 4,
parameter VAR45 = 4,
parameter VAR113 = 2,
parameter VAR82 = 20,
parameter VAR118 = 2,
parameter VAR2 = 4,
parameter VAR64 = 39,
parameter VAR23 = 640000
)
(
VAR73, VAR115, VAR31, VAR21, VAR3,
VAR95, VAR40,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap_2.v | 1,752 | module MODULE1 (
VAR3,
VAR2
);
input VAR3;
input VAR2;
VAR4 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR2;
VAR4 VAR1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.symbol.v | 1,335 | module MODULE1 ();
supply1 VAR5 ;
supply1 VAR1;
supply0 VAR4 ;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.v | 3,966 | if (VAR10 == VAR12 && VAR21 == VAR15) \
begin: VAR34 \
VAR45 VAR11 \
( \
.VAR7 ( VAR14 ) \
,.VAR3 ( VAR13 ) \
,.VAR37 ( ~VAR39 ) \
,.VAR20 ( ~VAR24 ) \
,.VAR40 ( VAR32 ) \
\
,.VAR42 ( VAR6 ) \
,.VAR25 ( ~VAR46 ) \
,.VAR38 ( VAR32 ) \
,.VAR23 ( VAR43 ) \
\
,.VAR36 ( 2'b00 ) \
,.VAR31 ( 2'b00 ) \
); \
end
module MODULE1 ... | bsd-3-clause |
olajep/oh | src/common/hdl/oh_lat0.v | 1,146 | module MODULE1 #(parameter VAR6 = 1 )
( input clk, input [VAR6-1:0] in, output [VAR6-1:0] out );
localparam VAR5 = VAR4;
generate
if(VAR5)
begin : VAR2
VAR1 VAR7 [VAR6-1:0] (.clk(clk),
.in(in[VAR6-1:0]),
.out(out[VAR6-1:0]));
end
else
begin : VAR2
reg [VAR6-1:0] VAR3;
always @ (clk or in)
if (!clk)
VAR3[VAR6-1:0] <= in... | mit |
petrmikheev/miksys | verilog/RAM512x16_2RW_bb.v | 9,028 | module MODULE1 (
VAR3,
VAR7,
VAR11,
VAR2,
VAR5,
VAR9,
VAR8,
VAR10,
VAR1,
VAR6,
VAR4);
input [8:0] VAR3;
input [8:0] VAR7;
input [1:0] VAR11;
input [1:0] VAR2;
input VAR5;
input [15:0] VAR9;
input [15:0] VAR8;
input VAR10;
input VAR1;
output [15:0] VAR6;
output [15:0] VAR4;
tri1 [1:0] VAR11;
tri1 [1:0] VAR2;
tri1 VAR5;
... | gpl-3.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v | 25,941 | module MODULE1 #
(
parameter VAR98 = 100,
parameter VAR13 = "1T",
parameter VAR43 = 3,
parameter VAR78 = 2,
parameter VAR128 = "8",
parameter VAR15 = 12,
parameter VAR62 = 5,
parameter VAR73 = 8,
parameter VAR129 = "VAR132",
parameter VAR136 = "VAR97",
parameter VAR64 = 4,
parameter VAR125 = 4,
parameter VAR67 = 2,
par... | mit |
DougFirErickson/parallella-hw | fpga/old/hdl/parallella-I/parallella_z7_top.v | 37,490 | module MODULE1 (
VAR183, VAR313, VAR169, VAR199, VAR132, VAR40,
VAR100, VAR240, VAR182, VAR99, VAR262,
VAR73, VAR98, VAR176, VAR111,
VAR266, VAR141, VAR38, VAR191, VAR14,
VAR86, VAR214, VAR403, VAR148, VAR119, VAR271, VAR93,
VAR29, VAR408, VAR402, VAR246, VAR102, VAR373,
VAR41, VAR224, VAR66, VAR303, VAR395, VAR249,
VA... | gpl-3.0 |
praveendath92/securePUF | ipcore_dir/SysMon.v | 7,263 | module MODULE1
(
VAR20, VAR54, VAR11, VAR13, VAR60, VAR67, VAR31, VAR42, VAR17, VAR64, VAR26, VAR23, VAR1, VAR24, VAR33, VAR18);
input [6:0] VAR20;
input VAR54;
input VAR11;
input [15:0] VAR13;
input VAR60;
input VAR33;
input VAR18;
output VAR67;
output [4:0] VAR31;
output [15:0] VAR42;
output VAR17;
output VAR64;
outp... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_rpt.v | 7,767 | module MODULE1(VAR33 ,VAR77 ,VAR59 ,VAR35 ,VAR51 ,VAR6 ,VAR97 ,VAR11 ,VAR44 ,
VAR67 ,VAR69 ,VAR60 ,VAR63 ,VAR98 ,VAR78 ,VAR80 ,VAR21 ,VAR38 ,VAR32 ,VAR92 ,
VAR74 ,VAR30 ,VAR62 ,VAR34 ,VAR24 ,VAR2 ,VAR85 ,VAR90 ,VAR65 ,VAR31 ,VAR19
,VAR3 ,VAR89 ,VAR79 ,VAR91 ,VAR48 ,VAR10 ,VAR71 );
output [1:0] VAR33 ;
output [1:0] VAR3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a_lp.v | 2,436 | module MODULE2 (
VAR4 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR12 ,
VAR3 ,
VAR6,
VAR10,
VAR2 ,
VAR11
);
output VAR4 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR12 ;
input VAR3 ;
input VAR6;
input VAR10;
input VAR2 ;
input VAR11 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR6(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah.behavioral.pp.v | 2,616 | module MODULE1 (
VAR21,
VAR6 ,
VAR14 ,
VAR7 ,
VAR17 ,
VAR18,
VAR19,
VAR16 ,
VAR10
);
output VAR21;
output VAR6 ;
input VAR14 ;
input VAR7 ;
input VAR17 ;
input VAR18;
input VAR19;
input VAR16 ;
input VAR10 ;
wire VAR15 ;
wire VAR20 ;
wire VAR1 ;
wire VAR12 ;
wire VAR2 ;
wire VAR3 ;
wire VAR11;
xor VAR9 (VAR15 , VAR14, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor2/sky130_fd_sc_ms__xor2.functional.pp.v | 1,814 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR1 ,
VAR6,
VAR13,
VAR12 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR6;
input VAR13;
input VAR12 ;
input VAR8 ;
wire VAR5 ;
wire VAR3;
xor VAR7 (VAR5 , VAR1, VAR9 );
VAR10 VAR11 (VAR3, VAR5, VAR6, VAR13);
buf VAR4 (VAR2 , VAR3 );
endmodule | apache-2.0 |
hanw/sonic-lite | hw/verilog/traffic_controller/avalon_st_prtmux.v | 3,172 | module MODULE1
(
input wire VAR9,
input wire[5:0] VAR2,
input wire VAR5,
input wire VAR7,
input wire[63:0] VAR1,
input wire[2:0] VAR3,
output reg VAR19,
input wire VAR11,
input wire[5:0] VAR12,
input wire VAR16,
input wire VAR20,
input wire[63:0] VAR23,
input wire[2:0] VAR21,
output reg VAR13,
input wire VAR22,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.symbol.v | 1,460 | module MODULE1 (
input VAR5,
input VAR4,
input VAR9 ,
input VAR1 ,
output VAR3
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b.pp.symbol.v | 1,330 | module MODULE1 (
input VAR6 ,
input VAR9 ,
input VAR8 ,
input VAR4 ,
output VAR1 ,
input VAR3 ,
input VAR2,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
solowandererY2K/FPGA-Quantum-Compiler | src/mult_unit.v | 4,371 | module MODULE1 (
VAR17,
VAR4,
VAR3);
input [35:0] VAR17;
input [35:0] VAR4;
output [71:0] VAR3;
wire [71:0] VAR10;
wire [71:0] VAR3 = VAR10[71:0];
VAR11 VAR6 (
.VAR17 (VAR17),
.VAR4 (VAR4),
.VAR3 (VAR10),
.VAR18 (1'b0),
.VAR16 (1'b1),
.VAR14 (1'b0),
.sum (1'b0));
VAR6.VAR8 = "VAR2=9",
VAR6.VAR9 = "VAR7",
VAR6.VAR5 = "... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.behavioral.v | 3,323 | module MODULE1 (
VAR35 ,
VAR26 ,
VAR13 ,
VAR2 ,
VAR16 ,
VAR28 ,
VAR4 ,
VAR3
);
output VAR35 ;
output VAR26 ;
input VAR13 ;
input VAR2 ;
input VAR16 ;
input VAR28 ;
input VAR4 ;
input VAR3;
supply1 VAR8;
supply0 VAR31;
supply1 VAR37 ;
supply0 VAR1 ;
wire VAR21 ;
wire VAR23 ;
wire VAR18 ;
reg VAR12 ;
wire VAR32 ;
wire VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41ai/sky130_fd_sc_hd__o41ai_4.v | 2,424 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR7 ,
VAR5 ,
VAR10 ,
VAR4 ,
VAR2,
VAR3,
VAR1 ,
VAR11
);
output VAR6 ;
input VAR8 ;
input VAR7 ;
input VAR5 ;
input VAR10 ;
input VAR4 ;
input VAR2;
input VAR3;
input VAR1 ;
input VAR11 ;
VAR9 VAR12 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VA... | apache-2.0 |
mdsalman729/flexpret_project | src/uart/ParityGen.v | 3,881 | module MODULE1(VAR2, VAR3);
parameter VAR4 = 0,
VAR1 = 8;
input [VAR1-1:0] VAR2;
output reg VAR3;
always @ (VAR2) begin
case (VAR4)
1: VAR3 = ~^VAR2;
2: VAR3 = ^VAR2;
3: VAR3 = 1;
4: VAR3 = 0;
default: VAR3 = 1'b0;
endcase
end
endmodule
------------------------------------------------------------------------------ | bsd-3-clause |
AngelTerrones/Antares | Hardware/verilog/antares_divider.v | 4,697 | module MODULE1 (
input clk,
input rst,
input VAR7,
input VAR8,
input [31:0] VAR6,
input [31:0] VAR12,
output [31:0] VAR13,
output [31:0] VAR3,
output VAR10
);
reg VAR15; reg VAR2; reg VAR11; reg [4:0] VAR5; reg [31:0] VAR9; reg [31:0] VAR4; reg [31:0] VAR14;
wire [32:0] VAR1;
assign VAR13 = !VAR2 ? VAR9 : -VAR9;
assign... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.behavioral.v | 1,674 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR4,
VAR10
);
output VAR8 ;
input VAR1 ;
input VAR4;
input VAR10;
wire VAR6 ;
wire VAR5;
not VAR9 (VAR6 , VAR1 );
VAR3 VAR2 (VAR5, VAR6, VAR4, VAR10);
buf VAR7 (VAR8 , VAR5 );
endmodule | apache-2.0 |
dk00/old-stuff | csie/09computer-architecture/project/code/dcache_one_way_example/Data_Memory.v | 1,563 | module MODULE1
(
VAR10,
VAR6,
VAR15,
VAR3,
VAR1,
VAR11,
VAR7,
VAR5
);
input VAR10;
input VAR6;
input [31:0] VAR15;
input [255:0] VAR3;
input VAR1;
input VAR11;
output VAR7;
output [255:0] VAR5;
reg [255:0] memory [0:511]; reg [3:0] VAR9;
reg ack;
reg VAR4;
reg [255:0] VAR8;
wire [26:0] addr;
parameter VAR13 = 3'h0,
VAR... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor3/sky130_fd_sc_ls__xnor3.symbol.v | 1,289 | module MODULE1 (
input VAR1,
input VAR3,
input VAR8,
output VAR2
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ISURCL/A-Scalable-Unsegmented-Multi-port-Memory-for-FPGA-based-Systems | std_fifo/std_fifo.v | 2,291 | module MODULE1(rst, clk, VAR15, VAR12, VAR13, VAR4, VAR16, VAR19, VAR18, VAR9, VAR5);
parameter VAR14 = 8;
parameter VAR1 = 6;
parameter VAR17 = VAR2(VAR1-1);
parameter VAR3 = 1;
parameter VAR11 = 1;
input rst;
input clk;
input VAR15;
input VAR12;
input [VAR14-1:0] VAR13;
output [VAR14-1:0] VAR4;
output VAR16;
output V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.blackbox.v | 1,321 | module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
kevintownsend/R3 | verilog/smvm.v | 12,145 | module MODULE1(
input clk,
input reset,
input VAR104,
input VAR70,
output VAR7,
output [63:0] VAR29,
output VAR80,
output VAR107,
output [47:0] VAR131,
output [63:0] VAR78,
input VAR108,
input VAR62,
input [31:0] VAR126,
input [63:0] VAR28,
input VAR73,
output VAR95,
input [47:0] VAR63,
input [47:0] VAR96,
input [47:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3.functional.v | 1,265 | module MODULE1 (
VAR3,
VAR2,
VAR1,
VAR6
);
output VAR3;
input VAR2;
input VAR1;
input VAR6;
wire VAR5;
or VAR7 (VAR5, VAR1, VAR2, VAR6 );
buf VAR4 (VAR3 , VAR5 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_2.behavioral.pp.v | 3,792 | module MODULE1( VAR19, VAR9, VAR13, VAR32, VAR17, VAR21 );
input VAR19, VAR9, VAR13;
inout VAR17, VAR21;
output VAR32;
reg VAR10;
VAR14 VAR27(.VAR19(VAR19),.VAR9(VAR9),.VAR13(VAR13),.VAR32(VAR32),.VAR17(VAR17),.VAR21(VAR21),.VAR10(VAR10));
VAR14 VAR8(.VAR19(VAR19),.VAR9(VAR9),.VAR13(VAR13),.VAR32(VAR32),.VAR17(VAR17),.... | apache-2.0 |
kylemsguy/FPGA-Litecoin-Miner | experimental/hashvariant-B.v | 24,144 | module MODULE1 (VAR13, VAR55, VAR14, VAR103, VAR24, VAR109, VAR59, VAR112, VAR1, VAR25);
input VAR13;
input [255:0] VAR55;
input [255:0] VAR14;
input [127:0] VAR103;
input [31:0] VAR24;
input [3:0] VAR109; output [31:0] VAR59;
output [31:0] VAR112;
output VAR1; input VAR25;
reg VAR113 = 1'b1;
reg reset = 1'b1;
always @... | gpl-3.0 |
AngelTerrones/MUSB | Hardware/musb/musb_load_store_unit.v | 14,220 | module MODULE1(
input clk, input rst, input [31:0] VAR41, output reg [31:0] VAR14, input [31:0] VAR37, input [31:0] VAR36, input VAR12, input VAR5, input VAR30, input VAR40, input VAR16, output reg [31:0] VAR29, input [31:0] VAR27, input VAR35, input VAR31, output [31:0] VAR43, output [3:0] VAR8, output VAR9, input [31... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai_lp.v | 2,369 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR11,
VAR7,
VAR10 ,
VAR1
);
output VAR6 ;
input VAR4 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR11;
input VAR7;
input VAR10 ;
input VAR1 ;
VAR8 VAR2 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR10(VAR10),
.... | apache-2.0 |
azonenberg/openfpga | hdl/common/JtagPipeBridge.v | 10,768 | module MODULE1(
output wire VAR11,
output wire VAR24,
output wire VAR12,
input wire VAR13
);
localparam VAR17 = 8'h00;
localparam VAR18 = 8'h01;
localparam VAR19 = 8'h02;
localparam VAR9 = 8'h03;
localparam VAR23 = 8'h06;
localparam VAR7 = 8'h07;
localparam VAR6 = 8'h08;
localparam VAR16 = 8'h0e;
localparam VAR4 = 8'h1... | lgpl-2.1 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.behavioral.v | 8,879 | module MODULE1( VAR46, VAR20, VAR34, VAR61, VAR1 );
input VAR46, VAR20, VAR61, VAR34;
output VAR1;
reg VAR14;
VAR50 VAR68(.VAR46(VAR46),.VAR20(VAR20),.VAR34(VAR34),.VAR61(VAR61),.VAR1(VAR1),.VAR14(VAR14));
VAR50 VAR22(.VAR46(VAR46),.VAR20(VAR20),.VAR34(VAR34),.VAR61(VAR61),.VAR1(VAR1),.VAR14(VAR14));
not VAR25(VAR9,VAR... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/rtl_model/rf_2p.v | 3,379 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR5 ,
VAR14 ,
VAR7 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR11
);
parameter VAR6=32;
parameter VAR10=8;
input VAR12; input VAR8; input [VAR10-1:0] VAR5; output [VAR6-1:0] VAR14;
input VAR7; input VAR2; input VAR9; input [VAR10-1:0] VAR1; input [VAR6-1:0] VAR11;
reg [VAR6-1:0] VAR3[(1<<VAR10)-1:0];
reg... | gpl-3.0 |
ehab93/MIPS-Processor | mem/im.v | 1,237 | module MODULE1 (
input clk,
input [31:0] addr,
output [31:0] VAR4
);
reg [31:0] VAR17 [0:VAR13-1];
reg [7:0] VAR10, VAR16, VAR15, VAR19;
parameter VAR7 = "../program/VAR12.VAR9";
parameter VAR7 = "../program/VAR1.VAR9";
parameter VAR7 = "../program/VAR11.VAR9";
parameter VAR7 = "../program/VAR5.VAR9";
parameter VAR7 = ... | mit |
bbrown1867/ObjectTracking | hw/common/video_input/MAC_3.v | 15,140 | module MODULE1 (
VAR58,
VAR123,
VAR92,
VAR74,
VAR27,
VAR83,
VAR116,
VAR34,
VAR24);
input VAR58;
input VAR123;
input [7:0] VAR92;
input [7:0] VAR74;
input [7:0] VAR27;
input [16:0] VAR83;
input [16:0] VAR116;
input [16:0] VAR34;
output [26:0] VAR24;
tri0 VAR58;
tri1 VAR123;
tri0 [7:0] VAR92;
tri0 [7:0] VAR74;
tri0 [7:0]... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_frf.v | 5,591 | module MODULE1 (
VAR9, VAR1,
VAR16, VAR35, VAR19, VAR23, VAR21, VAR6, VAR10,
VAR30, VAR25
) ;
input VAR16;
input VAR35;
input VAR19;
input VAR23;
input VAR21;
input [1:0] VAR6;
input VAR10;
input [77:0] VAR30;
input [6:0] VAR25;
output VAR9;
output [77:0] VAR1;
wire [7:0] VAR28;
wire [7:0] VAR3;
wire [7:0] VAR34;
reg [... | gpl-2.0 |
JakeMercer/mac | rmii.v | 1,877 | module MODULE1
(
input wire reset,
input wire VAR21,
output reg [1:0] VAR10,
output wire VAR7,
input wire [1:0] VAR4,
input wire VAR17,
input wire VAR16,
input wire VAR8,
input wire [7:0] VAR2,
input wire VAR23,
output wire VAR13,
output wire VAR12,
output reg [7:0] VAR3,
output wire VAR15,
output wire VAR5,
output wir... | mit |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/demux.v | 2,687 | module MODULE1
parameter VAR1 = 12,
parameter VAR4 = 1
)
(
input [VAR4-1:0] VAR5, input [VAR3(VAR1)-1:0] VAR8, output [VAR1*VAR4-1:0] VAR2 );
genvar VAR6;
reg [VAR1*VAR4-1:0] VAR7;
assign VAR2 = VAR7;
always @(*) begin
VAR7 = 0;
VAR7[VAR4*VAR8 +: VAR4] = VAR5;
end
endmodule | mit |
olofk/oh | memory/hdl/memory_dp.v | 2,373 | module MODULE1(
VAR11,
VAR13, VAR2, VAR7, VAR9, VAR4, VAR8, VAR3
);
parameter VAR1 = 14;
parameter VAR6 = 32;
parameter VAR10 = VAR6/8; parameter VAR15 = 1<<VAR1;
input VAR13; input [VAR10-1:0] VAR2; input [VAR1-1:0] VAR7; input [VAR6-1:0] VAR9;
input VAR4; input VAR8; input [VAR1-1:0] VAR3; output[VAR6-1:0] VAR11;
reg... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/ex_stage.v | 5,214 | module MODULE1 (
input wire clk, input wire reset, input wire VAR9, input wire VAR7, input wire VAR1, output wire [VAR12] VAR23, input wire [VAR16] VAR34, input wire VAR27, input wire [VAR36] VAR2, input wire [VAR12] VAR22, input wire [VAR12] VAR11, input wire VAR38, input wire [VAR31] VAR37, input wire [VAR12] VAR39, ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_2.behavioral.pp.v | 1,236 | module MODULE1( VAR6, VAR1, VAR4, VAR3, VAR2 );
input VAR6, VAR1;
inout VAR3, VAR2;
output VAR4;
VAR7 VAR5(.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2));
VAR7 VAR8(.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/sctag_cpx_rptr_3.v | 1,918 | module MODULE1 (
VAR1,
VAR2
);
output [163:0] VAR1;
input [163:0] VAR2;
assign VAR1 = VAR2;
endmodule | gpl-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Position/clk_generator.v | 1,100 | module MODULE1(
input clk,
input en,
input [31:0] VAR3,
input [31:0] VAR2,
output reg VAR1
);
reg [31:0] VAR4;
VAR5 VAR1 = 1'b0;
VAR5 VAR4 = 32'h00000000;
always@(negedge clk) begin
if(en) begin
if(VAR2 > VAR4) begin VAR4 <= VAR2 + VAR3; VAR1 <= ~VAR1; end
else begin
VAR4 <= VAR4; VAR1 <= VAR1; end
end
else begin
VAR4 ... | mit |
donnaware/TabX1 | rtl/tabx1/ram1.v | 9,142 | module MODULE1 (
VAR12,
VAR25,
VAR2,
VAR56,
VAR3,
VAR32,
VAR57);
input [7:0] VAR12;
input [9:0] VAR25;
input VAR2;
input [10:0] VAR56;
input VAR3;
input VAR32;
output [15:0] VAR57;
tri1 VAR3;
tri0 VAR32;
wire [15:0] VAR28;
wire [15:0] VAR57 = VAR28[15:0];
VAR42 VAR9 (
.VAR41 (VAR56),
.VAR43 (VAR3),
.VAR47 (VAR12),
.VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.functional.pp.v | 1,902 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR7 ,
VAR3 ,
VAR1,
VAR13,
VAR6 ,
VAR4
);
output VAR9 ;
input VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR1;
input VAR13;
input VAR6 ;
input VAR4 ;
wire VAR10 ;
wire VAR5;
VAR15 VAR11 (VAR10 , VAR8, VAR7, VAR3 );
VAR12 VAR14 (VAR5, VAR10, VAR1, VAR13);
buf VAR2 (VAR9 , VAR5 );
endmodule | apache-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_register_syn.v | 4,516 | module MODULE1
( VAR2,
VAR3,
VAR4,
clk,
VAR1
);
parameter VAR6 = 8; parameter VAR5 = 0;
input [VAR6-1:0] VAR2;
input VAR4;
input clk;
input VAR1;
output [VAR6-1:0] VAR3;
reg [VAR6-1:0] VAR3;
always @ (posedge clk)
begin
if (VAR1) VAR3<=VAR5;
end
else if (VAR4) VAR3<=VAR2;
end
endmodule | gpl-3.0 |
HeberthVG/papiGB | rtl/sound_controller_modules/SoundControllerOSC1.v | 1,730 | module MODULE1
(
input wire VAR3,
input wire VAR1,
output wire VAR6,
output wire VAR5,
output wire VAR2
);
reg [16:0] VAR4;
always @ (posedge VAR3) begin
if (VAR1) begin
VAR4 <= 0;
end
else begin
VAR4 <= VAR4+1;
end
end
assign VAR6 = VAR4[15];
assign VAR5 = VAR4[14];
assign VAR2 = VAR4[13];
endmodule | gpl-2.0 |
calee0219/Course | DLAB/Lab06/DALU.v | 3,456 | module MODULE1(
clk,
rst,
VAR2,
VAR9,
VAR7,
out
);
input clk;
input rst;
input VAR2;
input [18:0] VAR9;
output reg VAR7;
output reg signed [15:0] out;
parameter VAR4=0, VAR13=1, VAR8=2, VAR14=3;
reg [1:0] VAR3, VAR1;
wire [2:0] VAR10;
wire signed [5:0] VAR5, VAR12;
wire signed [3:0] VAR11;
wire signed [9:0] VAR6;
assig... | mit |
parallella/oh | enoc/hdl/emesh_if.v | 2,999 | module MODULE1 (
VAR21, VAR16, VAR12,
VAR7, VAR26, VAR18,
VAR6, VAR11, VAR22,
VAR23, VAR13, VAR25,
VAR3, VAR9, VAR20, VAR14,
VAR19, VAR2, VAR15, VAR8,
VAR24, VAR4, VAR5, VAR17
);
parameter VAR1 = 32;
parameter VAR10 = 2*VAR1+40;
input VAR3;
input [VAR10-1:0] VAR9;
output VAR21;
output VAR16;
output [VAR10-1:0] VAR12;
i... | mit |
GREO/GNU-Radio | usrp/fpga/sdr_lib/rx_chain_dual.v | 3,230 | module MODULE1
(input VAR34,
input VAR5,
input reset,
input enable,
input wire [7:0] VAR9,
input VAR27,
input VAR8,
input wire [31:0] VAR35,
input wire [15:0] VAR21,
input wire [15:0] VAR13,
output wire [15:0] VAR45,
output wire [15:0] VAR24,
input wire [31:0] VAR4,
input wire [15:0] VAR26,
input wire [15:0] VAR33,
out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.functional.v | 1,317 | module MODULE1 (
VAR4,
VAR6,
VAR1,
VAR2
);
output VAR4;
input VAR6;
input VAR1;
input VAR2;
wire VAR3;
nor VAR5 (VAR3, VAR2, VAR6, VAR1 );
buf VAR7 (VAR4 , VAR3 );
endmodule | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/fast_spi_rx/fast_spi_rx_core.v | 3,774 | module MODULE1 #(
parameter VAR22 = 16,
parameter VAR5 = 4'b0001
) (
input wire VAR25,
input wire VAR62,
input wire VAR32,
input wire VAR36,
output wire VAR14,
output wire [31:0] VAR18,
input wire VAR29,
input wire [VAR22-1:0] VAR23,
input wire [7:0] VAR12,
output reg [7:0] VAR38,
input wire VAR33,
input wire VAR24,
in... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.behavioral.v | 1,571 | module MODULE1 (
VAR15 ,
VAR9,
VAR5,
VAR7,
VAR3,
VAR14
);
output VAR15 ;
input VAR9;
input VAR5;
input VAR7;
input VAR3;
input VAR14;
supply1 VAR4;
supply0 VAR10;
supply1 VAR12 ;
supply0 VAR11 ;
wire VAR2 ;
wire VAR1;
or VAR8 (VAR2 , VAR3, VAR7, VAR5, VAR9 );
nand VAR13 (VAR1, VAR14, VAR2 );
buf VAR6 (VAR15 , VAR1 );
e... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu7t5v0__icgtp_1.behavioral.pp.v | 2,782 | module MODULE1( VAR14, VAR15, VAR25, VAR1, VAR20, VAR8 );
input VAR25, VAR15, VAR14;
inout VAR20, VAR8;
output VAR1;
reg VAR23;
VAR10 VAR16(.VAR14(VAR14),.VAR15(VAR15),.VAR25(VAR25),.VAR1(VAR1),.VAR20(VAR20),.VAR8(VAR8),.VAR23(VAR23));
VAR10 VAR21(.VAR14(VAR14),.VAR15(VAR15),.VAR25(VAR25),.VAR1(VAR1),.VAR20(VAR20),.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.pp.symbol.v | 1,390 | module MODULE1 (
input VAR9 ,
input VAR2 ,
input VAR5 ,
input VAR4 ,
input VAR8 ,
output VAR10 ,
input VAR1 ,
input VAR3,
input VAR7,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p.functional.pp.v | 1,805 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR3,
VAR2,
VAR4 ,
VAR5
);
output VAR11 ;
input VAR8 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR5 ;
wire VAR1 ;
wire VAR9;
buf VAR6 (VAR1 , VAR8 );
VAR10 VAR7 (VAR9, VAR1, VAR3, VAR2);
buf VAR12 (VAR11 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai_4.v | 2,424 | module MODULE2 (
VAR4 ,
VAR12 ,
VAR1 ,
VAR7 ,
VAR5 ,
VAR8 ,
VAR3,
VAR6,
VAR11 ,
VAR2
);
output VAR4 ;
input VAR12 ;
input VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR3;
input VAR6;
input VAR11 ;
input VAR2 ;
VAR9 VAR10 (
.VAR4(VAR4),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.pp.blackbox.v | 1,482 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR4 ,
VAR9 ,
VAR5 ,
VAR1,
VAR7 ,
VAR3 ,
VAR10 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR1;
input VAR7 ;
input VAR3 ;
input VAR10 ;
input VAR6 ;
endmodule | apache-2.0 |
sigilance/paper-processor | 4-bit/jno.v | 1,198 | module MODULE1 (VAR15, VAR17, VAR13, VAR6, VAR16, VAR7, VAR3);
output [1:0] VAR15;
input [1:0] VAR17;
input [3:0] VAR13;
input VAR6, VAR16, VAR7, VAR3, VAR1, VAR10;
wire VAR9, VAR11, VAR4, VAR5;
and (VAR5, VAR6, ~VAR16);
VAR8 VAR14 (VAR9, VAR4, VAR11, VAR7, VAR3, VAR17[1], VAR17[0]); VAR12 VAR2 (VAR15[1], VAR15[0], VAR... | mit |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/system1.v | 36,026 | module MODULE1 (
input wire VAR17, input wire [31:0] VAR228, input wire [31:0] VAR101, input wire [31:0] VAR16, input wire [31:0] VAR116, output wire [31:0] VAR46, output wire [31:0] VAR193, output wire [31:0] VAR77, output wire [31:0] VAR111, input wire VAR155 );
wire [31:0] VAR250; wire VAR133; wire VAR62; wire [20:0... | mit |
seyedmaysamlavasani/GorillaPP | chisel/KmeansAndMesh/emulator/Offloaded.v | 43,510 | module MODULE3(input clk, input reset,
output VAR40,
input VAR108,
input [31:0] VAR114,
input VAR55,
output VAR177,
output[31:0] VAR47,
input VAR58,
input VAR159,
input [15:0] VAR156,
input [7:0] VAR32,
input [15:0] VAR240,
input [3:0] VAR154,
output VAR23,
output VAR205,
output[15:0] VAR130,
output[7:0] VAR86,
output[... | bsd-3-clause |
zhangly/azpr_cpu | rtl/io/uart/rtl/uart_tx.v | 2,864 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR9, input wire [VAR6] VAR12, output wire VAR16, output reg VAR2,
output reg VAR11 );
reg [VAR1] state; reg [VAR20] VAR25; reg [VAR18] VAR22; reg [VAR6] VAR10;
assign VAR16 = (state == VAR8) ? VAR15 : VAR3;
always @(posedge clk or VAR23 reset) begin
if (res... | mit |
jlrandulfe/UviSpace | DE1-SoC/FPGA_Design/ip/camera_controller/config_controller/camera_config.v | 6,534 | module MODULE1 #(
parameter VAR34 = 50000000, parameter VAR35 = 20000 ) (
input VAR10,
input VAR12,
input [15:0] VAR16,
input [15:0] VAR14,
input [15:0] VAR8,
input [15:0] VAR30,
input [15:0] VAR15,
input [15:0] VAR32,
input [15:0] VAR20,
output VAR22,
output VAR19,
inout VAR6
);
reg [15:0] VAR18;
reg [31:0] VAR9;
reg ... | gpl-3.0 |
danbone/core | rtl/riscv_fifo.v | 3,089 | (VAR7 <= 2) ? 1 : \
(VAR7 <= 4) ? 2 : \
(VAR7 <= 8) ? 3 : \
(VAR7 <= 16) ? 4 : \
(VAR7 <= 32) ? 5 : \
(VAR7 <= 64) ? 6 : \
(VAR7 <= 128) ? 7 : \
(VAR7 <= 256) ? 8 : \
-1
module MODULE1 #(
parameter VAR13 = 3,
parameter VAR21 = 32,
parameter VAR3 = 1,
parameter VAR2 = 1,
parameter VAR9 = 0
)
(
input clk,
input VAR23,
in... | mit |
borti4938/sd2snes | verilog/sd2snes_base/main.v | 26,980 | module MODULE1(
output [22:0] VAR273,
output VAR244,
input VAR72,
output VAR398,
input VAR103,
output [21:0] VAR273,
output VAR360,
output VAR234,
output VAR279,
output VAR367,
output VAR5,
input VAR188,
input VAR18,
input [23:0] VAR240,
input VAR141,
input VAR143,
input VAR361,
inout [7:0] VAR158,
input VAR406,
input ... | gpl-2.0 |
hhuang25/uwaterloo_ece224 | Lab1/pio_missed.v | 1,794 | module MODULE1 (
address,
clk,
VAR4,
VAR5,
VAR1
)
;
output [ 15: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 15: 0] VAR4;
input VAR5;
wire VAR6;
wire [ 15: 0] VAR2;
wire [ 15: 0] VAR3;
reg [ 15: 0] VAR1;
assign VAR6 = 1;
assign VAR3 = {16 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR5)
begin
if (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp.behavioral.v | 2,153 | module MODULE1 (
VAR14 ,
VAR20,
VAR8 ,
VAR10
);
output VAR14 ;
input VAR20;
input VAR8 ;
input VAR10 ;
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR3 ;
wire VAR17 ;
reg VAR13 ;
wire VAR11 ;
wire VAR18 ;
wire VAR19;
wire VAR1 ;
wire VAR9 ;
wire VAR16 ;
VAR15 VAR7 (VAR1, VAR17, VAR11, VAR18 );
VAR12 VAR6 (VAR17 ... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/niosII_system/synthesis/submodules/niosII_system_nios2_qsys_0_mult_cell.v | 6,387 | module MODULE1 (
VAR25,
VAR10,
clk,
VAR43,
VAR24
)
;
output [ 31: 0] VAR24;
input [ 31: 0] VAR25;
input [ 31: 0] VAR10;
input clk;
input VAR43;
wire [ 31: 0] VAR24;
wire [ 31: 0] VAR49;
wire [ 15: 0] VAR11;
wire VAR18;
assign VAR18 = ~VAR43;
VAR6 VAR19
(
.VAR21 (VAR18),
.VAR50 (clk),
.VAR9 (VAR25[15 : 0]),
.VAR45 (VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211ai/sky130_fd_sc_ms__o211ai.functional.v | 1,468 | module MODULE1 (
VAR3 ,
VAR7,
VAR1,
VAR8,
VAR9
);
output VAR3 ;
input VAR7;
input VAR1;
input VAR8;
input VAR9;
wire VAR4 ;
wire VAR6;
or VAR5 (VAR4 , VAR1, VAR7 );
nand VAR10 (VAR6, VAR9, VAR4, VAR8);
buf VAR2 (VAR3 , VAR6 );
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaD_release/sound/sound_dac2.v | 2,114 | module MODULE1(
VAR8,
VAR7, VAR5, VAR9,
VAR6,
VAR4 );
input VAR8;
output VAR7;
output VAR5;
output VAR9;
output reg VAR6;
input [15:0] VAR4;
reg [16:0] VAR1;
reg [2:0] VAR2; reg [6:0] sync;
wire VAR3;
begin
begin
end
begin
begin
begin
begin
end | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfstp/sky130_fd_sc_lp__dfstp_lp.v | 2,281 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR5,
VAR1 ,
VAR2 ,
VAR7 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR5;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
VAR4 VAR8 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
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