repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR6 ,
VAR10,
VAR2,
VAR12 ,
VAR1
);
output VAR7 ;
input VAR11 ;
input VAR6 ;
input VAR10;
input VAR2;
input VAR12 ;
input VAR1 ;
wire VAR3 ;
wire VAR9;
and VAR4 (VAR3 , VAR11, VAR6 );
VAR13 VAR8 (VAR9, VAR3, VAR10, VAR2);
buf VAR5 (VAR7 , VAR9 );
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_8-parallel/src/vivado_ip_dram/controller/mig_7series_v2_3_arb_mux.v | 19,765 | module MODULE1 #
(
parameter VAR34 = 100,
parameter VAR44 = "VAR104",
parameter VAR66 = "1T",
parameter VAR61 = 11,
parameter VAR49 = 3,
parameter VAR122 = "8",
parameter VAR101 = 4,
parameter VAR90 = 5,
parameter VAR57 = 5,
parameter VAR117 = 31,
parameter VAR89 = 8,
parameter VAR84 = "VAR12",
parameter VAR95 = "VAR79... | mit |
hoangt/multiported-ram | mpram_lvt_1ht.v | 7,819 | module MODULE1
localparam VAR27 = VAR17(VAR33 );
reg [VAR27 -1:0] VAR35 [VAR6-1:0] ; reg [VAR5 -1:0] VAR16 [VAR6-1:0] ; wire [VAR5*VAR21 -1:0] VAR31 [VAR6-1:0] ; reg [VAR5 -1:0] VAR24 [VAR6-1:0][VAR21-1:0]; reg [VAR5 -1:0] VAR3 [VAR6-1:0][VAR21-1:0]; wire [VAR5 -1:0] VAR1 [VAR21-1:0] ; wire [VAR6*VAR21-1:0] VAR22 ; reg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtp/sky130_fd_sc_hd__dlxtp.symbol.v | 1,339 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR1
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b.functional.pp.v | 1,988 | module MODULE1 (
VAR3 ,
VAR16 ,
VAR9 ,
VAR12 ,
VAR1 ,
VAR17,
VAR10,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR16 ;
input VAR9 ;
input VAR12 ;
input VAR1 ;
input VAR17;
input VAR10;
input VAR6 ;
input VAR7 ;
wire VAR13 ;
wire VAR2 ;
wire VAR14;
not VAR11 (VAR13 , VAR16 );
and VAR5 (VAR2 , VAR13, VAR9, VAR12, VAR1 );
VAR4 VA... | apache-2.0 |
CospanDesign/nysa-sdio-device | rtl/generic/crc7.v | 2,288 | module MODULE1 #(
parameter VAR3 = 8'h09,
parameter VAR2 = 8'h00
)(
input clk,
input rst,
input bit,
output [6:0] VAR1,
input VAR4
);
reg [7:0] VAR5;
assign VAR1 = VAR5[6:0];
always @ (posedge clk) begin
if (rst) begin
VAR5 <= VAR2;
end
else begin
if (!VAR4)
VAR5[7:0] <= bit ? ({VAR5[6:0], 1'b0} ^ VAR3) : {VAR5[6:0], 1... | mit |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/ewrapper_io_rx_slow.v | 8,448 | module MODULE1 (
VAR15, VAR19,
VAR9, VAR40, VAR5, VAR32, VAR1,
VAR24, VAR10
);
input VAR9; input VAR40;
input VAR5;
input VAR32;
input [8:0] VAR1;
input [8:0] VAR24;
input VAR10;
output VAR15; output [71:0] VAR19;
reg [1:0] VAR45;
reg [8:0] VAR8;
reg [8:0] VAR14;
reg [8:0] VAR30;
reg [8:0] VAR7;
reg [8:0] VAR54;
reg [8... | gpl-3.0 |
SiLab-Bonn/fe65_p2 | firmware/src/fe65p2_mio.v | 12,195 | module MODULE1 (
input wire VAR126,
inout wire [7:0] VAR86,
input wire [15:0] VAR136,
input wire VAR78,
input wire VAR175,
inout wire [7:0] VAR14,
input wire VAR52,
input wire VAR98,
input wire VAR184,
output wire [19:0] VAR156,
inout wire [15:0] VAR9,
output wire VAR138,
output wire VAR62,
output wire VAR101,
output w... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/remove_pkt.v | 18,834 | module MODULE1
parameter VAR73 = 64,
parameter VAR75=VAR73/8,
parameter VAR98 = 8,
parameter VAR89 = 13,
parameter VAR83 = 6,
parameter VAR57 = 4,
parameter VAR38 = VAR78,
parameter VAR82 = 11,
parameter VAR61 = VAR82-VAR35(VAR75),
parameter VAR34 = VAR35(VAR98)
)
( VAR27,
VAR5,
VAR64,
VAR55,
VAR85,
VAR21,
VAR97,
VAR47... | mit |
olajep/oh | src/common/hdl/oh_8b10b_encode.v | 7,025 | module MODULE1(
input clk,
input VAR6,
input VAR58,
input [7:0] VAR20,
input VAR49,
output VAR37,
output [9:0] VAR50
);
reg VAR31;
reg VAR30;
reg [7:0] VAR17;
reg [9:0] VAR29;
reg VAR5;
wire [9:0] VAR34;
wire VAR32;
wire [7:0] VAR23;
wire VAR12;
wire [9:0] VAR28;
wire [4:0] VAR19;
wire [2:0] VAR1;
wire VAR8,VAR7,VAR39,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a.pp.blackbox.v | 1,428 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR2 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR3,
VAR7,
VAR1 ,
VAR4
);
output VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR7;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
ultraembedded/altor32 | rtl/soc/soc.v | 8,207 | module MODULE1
(
VAR36,
VAR38,
VAR87,
VAR14,
VAR11,
VAR97,
VAR66,
VAR76,
VAR46,
VAR56,
VAR45,
VAR82
);
parameter [31:0] VAR34 = 12288;
parameter [31:0] VAR98 = 1;
parameter VAR102 = 115200;
parameter VAR71 = 1;
parameter VAR94 = "VAR79";
parameter VAR89 = "VAR79";
input VAR36 ;
input VAR38 ;
input [(VAR98 - 1):0] VAR87... | lgpl-3.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_regslice.v | 5,440 | module MODULE1
parameter VAR10 = 64,
parameter VAR16 = 64,
parameter VAR8 = 3 ,
parameter VAR2 = 2
)
(
input [VAR10-1:0 ] din ,
output [VAR10-1:0 ] dout ,
output [VAR10-1:0 ] VAR18 ,
input [VAR16-1:0] VAR11 ,
output [VAR16-1:0] VAR13 ,
output VAR6 ,
output reg VAR1,
output VAR15 ,
input clk ,
input reset
);
reg [VAR10-... | mit |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_b_downsizer.v | 10,782 | module MODULE1 #
(
parameter VAR3 = "none",
parameter integer VAR23 = 1
)
(
input wire VAR32,
input wire VAR28,
input wire VAR6,
input wire VAR20,
input wire [8-1:0] VAR27,
output wire VAR34,
input wire [VAR23-1:0] VAR9,
output wire [VAR23-1:0] VAR29,
output wire [2-1:0] VAR21,
output wire VAR7,
input wire VAR25,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold/sky130_fd_sc_lp__bushold.symbol.v | 1,392 | module MODULE1 (
inout VAR6 ,
input VAR4
);
supply1 VAR5;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/m32632/example.v | 4,683 | module MODULE1 ( VAR73, VAR49, VAR60, VAR14, VAR19, VAR32);
input VAR73;
input VAR49;
input VAR60;
input VAR14;
input [7:0] VAR19;
output [7:0] VAR32;
reg VAR27,VAR26;
wire VAR51;
wire VAR16;
wire VAR23;
wire VAR59;
wire [11:2] VAR33;
wire [31:0] VAR18;
wire [2:0] VAR57;
wire [2:0] VAR20;
wire VAR63;
wire [27:0] VAR43;... | gpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_convert_from_half.v | 3,542 | module MODULE1(VAR9, VAR4, VAR10, VAR6, VAR14, VAR7, VAR13, VAR20, enable);
parameter VAR2 = 1;
input VAR9, VAR4;
input [15:0] VAR10;
output [31:0] VAR6;
input VAR14, VAR13, enable;
output VAR7, VAR20;
wire VAR18;
reg VAR5;
wire VAR15;
reg [7:0] VAR8;
reg [22:0] VAR3;
reg VAR21;
assign VAR18 = (VAR2 == 1) ? (~VAR5 | ~V... | mit |
open-power/snap | actions/hdl_helloworld/hw/hdl/memcpy_engine.v | 5,513 | module MODULE1 #(
parameter VAR32 = 64,
parameter VAR2 = 512
)
(
input clk ,
input VAR24 ,
input [VAR32 - 1:0] VAR8,
input [VAR32 - 1:0] VAR30,
input [063:0] VAR9 , input VAR34 ,
output VAR28 ,
input VAR22 ,
output VAR27 ,
output [VAR32 - 1:0] VAR4 ,
output [007:0] VAR31 ,
input VAR16 ,
output reg VAR33 ,
output reg [V... | apache-2.0 |
RECS-Tsukuba/fpga-filter-hardware | filter_unit.v | 4,056 | module MODULE1 #(
parameter VAR29 = 2,
parameter VAR20 = 2'd0,
parameter VAR9 = 2'd1,
parameter VAR17 = 2'd2,
parameter VAR21 = 2'd3,
parameter VAR27 = 3,
parameter VAR1 = 8 + VAR29
)(
input [VAR1-1:0] VAR18,
input [9:0] VAR15,
input clk,
input rst,
input VAR26,
output [VAR1-1:0] VAR2
);
integer VAR34,VAR32;
reg [VAR1-... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso1p/sky130_fd_sc_hdll__inputiso1p.behavioral.pp.v | 1,742 | module MODULE1 (
VAR7 ,
VAR11 ,
VAR8,
VAR5 ,
VAR1 ,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR11 ;
input VAR8;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
wire VAR10;
or VAR6 (VAR10, VAR11, VAR8 );
VAR9 VAR4 (VAR7 , VAR10, VAR5, VAR1);
endmodule | apache-2.0 |
aquaxis/FPGAMAG18 | modules/cache_v1/src/fmrv32im_cache.v | 7,312 | module MODULE1
parameter VAR8 = 0,
parameter VAR22 = 0,
parameter VAR50 = ""
)
(
input VAR52,
input VAR21,
output VAR46,
input VAR20,
input [31:0] VAR54,
output [31:0] VAR29,
output VAR17,
output VAR18,
input VAR47,
input [3:0] VAR42,
input [31:0] VAR53,
input [31:0] VAR7,
output [31:0] VAR24,
output VAR9,
output VAR37... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/dram_ddr_rptr.v | 4,410 | module MODULE1(
VAR9, VAR16, VAR17,
VAR24, VAR8, VAR13,
VAR18, VAR23,
VAR7, VAR10,
VAR22, VAR3, VAR5,
VAR31, VAR30, VAR15,
VAR32, VAR11,
VAR19, VAR26, VAR36,
VAR12, VAR27, VAR14,
VAR2, VAR29, VAR34,
VAR35, VAR25, VAR28,
VAR21, VAR4, VAR20, VAR6,
VAR1, VAR33
);
output VAR9;
output [31:0] VAR16;
output [255:0] VAR17;
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b.blackbox.v | 1,299 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR4;
supply1 VAR2;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4b/sky130_fd_sc_hdll__and4b_1.v | 2,316 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR1 ,
VAR8,
VAR2,
VAR3 ,
VAR11
);
output VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR1 ;
input VAR8;
input VAR2;
input VAR3 ;
input VAR11 ;
VAR10 VAR4 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvp/sky130_fd_sc_hvl__einvp.pp.blackbox.v | 1,293 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6 ,
VAR3,
VAR2,
VAR4 ,
VAR7
);
output VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR7 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_iqcor.v | 4,896 | module MODULE1 (
clk,
VAR5,
VAR22,
VAR26,
VAR6,
VAR15,
VAR8,
VAR9,
VAR7,
VAR19,
VAR13,
VAR20);
input clk;
input [15:0] VAR5;
input [15:0] VAR22;
output [15:0] VAR26;
output [15:0] VAR6;
input VAR15;
input [15:0] VAR8;
input [15:0] VAR9;
input [15:0] VAR7;
input [15:0] VAR19;
input [15:0] VAR13;
input [15:0] VAR20;
reg ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.symbol.v | 1,321 | module MODULE1 (
input VAR4,
output VAR3
);
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/uart16550/rtl/verilog/uart_top.v | 14,032 | module MODULE1 (
VAR10,
VAR45, VAR12, VAR20, VAR40, VAR42, VAR43, VAR1, VAR13, VAR34,
VAR38,
VAR28, VAR33,
VAR3, VAR24, VAR7, VAR44, VAR25, VAR5
, VAR39
);
parameter VAR15 = VAR49;
parameter VAR26 = VAR36;
parameter VAR14 = 1;
input VAR10;
input VAR45;
input [VAR26-1:0] VAR12;
input [VAR15-1:0] VAR20;
output [VAR15-1:0... | mit |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/queue_splitter.v | 17,471 | module MODULE1 #(
parameter VAR12 = 64,
parameter VAR52=VAR12/8,
parameter VAR72 = 2,
parameter VAR106 = 4,
parameter VAR23 = 8
)( output [VAR12-1:0] VAR51,
output [VAR52-1:0] VAR99,
input VAR101,
output reg VAR96,
output [VAR12-1:0] VAR3,
output [VAR52-1:0] VAR59,
input VAR91,
output reg VAR69,
output [VAR12-1:0] VAR8... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.blackbox.v | 1,214 | module MODULE1 (
VAR4
);
input VAR4;
supply1 VAR5;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_phy_dq_iob.v | 21,882 | module MODULE1 #
(
parameter VAR37 = "VAR3",
parameter VAR5 = "VAR49",
parameter VAR23 = 2
)
(
input VAR78,
input VAR55,
input VAR40,
input VAR52,
input VAR86,
input VAR21,
input VAR90,
input [1:0] VAR25,
input VAR76,
input VAR63,
input VAR61,
input VAR74,
input VAR83,
output VAR26,
output VAR27,
inout VAR87
);
wire VA... | lgpl-3.0 |
asicguy/gplgpu | hdl/vga/vga.v | 26,878 | module MODULE1
(
input [22:0] VAR98, input [3:0] VAR1, input VAR16, input VAR14, input VAR75, input VAR59, input VAR57, input VAR164, input VAR222, input VAR90, input VAR11, input [31:0] VAR173, input [31:0] VAR129, input VAR53, input VAR110,
output [31:0] VAR151,
output [31:0] VAR172,
output VAR121, output VAR34, outp... | gpl-3.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_003.v | 6,161 | module MODULE1 #(
parameter VAR9 = 34,
parameter VAR1 = 0,
parameter VAR8 = 34,
parameter VAR19 = 0,
parameter VAR23 = 0,
parameter VAR7 = 0,
parameter VAR6 = 1,
parameter VAR24 = 1,
parameter VAR16 = 0,
parameter VAR12 = 34,
parameter VAR15 = 0,
parameter VAR5 = 1,
parameter VAR13 = 0,
parameter VAR17 = 1,
parameter V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111a/sky130_fd_sc_ls__o2111a.behavioral.v | 1,588 | module MODULE1 (
VAR12 ,
VAR11,
VAR15,
VAR4,
VAR8,
VAR3
);
output VAR12 ;
input VAR11;
input VAR15;
input VAR4;
input VAR8;
input VAR3;
supply1 VAR14;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR13 ;
wire VAR1;
or VAR9 (VAR13 , VAR15, VAR11 );
and VAR6 (VAR1, VAR4, VAR8, VAR13, VAR3);
buf VAR2 (VAR12 , VAR1 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp.functional.pp.v | 2,712 | module MODULE1 (
VAR8 ,
VAR20 ,
VAR24 ,
VAR14 ,
VAR16 ,
VAR22,
VAR9,
VAR23 ,
VAR17 ,
VAR7 ,
VAR6 ,
VAR5
);
output VAR8 ;
input VAR20 ;
input VAR24 ;
input VAR14 ;
input VAR16 ;
input VAR22;
input VAR9;
input VAR23 ;
input VAR17 ;
input VAR7 ;
input VAR6 ;
input VAR5 ;
wire VAR19 ;
wire VAR18 ;
wire VAR3 ;
wire VAR4;
no... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_4.behavioral.v | 2,148 | module MODULE1( VAR3, VAR5, VAR6 );
input VAR3, VAR5;
output VAR6;
reg VAR8;
VAR7 VAR9(.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6),.VAR8(VAR8));
VAR7 VAR2(.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6),.VAR8(VAR8));
not VAR1(VAR4,VAR5);
buf VAR11(VAR10,VAR5); | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp_synth.v | 4,230 | module MODULE1 (
VAR2,
VAR1,
VAR4,
VAR3,
VAR5,
VAR6
);
input VAR2;
input VAR1;
input [1 : 0] VAR4;
input [9 : 0] VAR3;
input [15 : 0] VAR5;
output [15 : 0] VAR6;
endmodule | bsd-3-clause |
kevintownsend/convey_spmv | rtl/mac/mac.v | 2,150 | module MODULE1(clk, rst, wr, VAR30, VAR32, VAR18, VAR23, VAR17, VAR10, VAR14, VAR25);
parameter VAR2 = 1024;
parameter VAR19 = VAR11(VAR2 - 1);
input clk, rst, wr;
input [VAR19 - 1:0] VAR30;
input [63:0] VAR32, VAR18;
output VAR23;
output [63:0] VAR17;
input VAR10;
output VAR14;
input VAR25;
wire [65:0] VAR35, VAR6;
wi... | apache-2.0 |
thinkoco/de1_soc_opencl | de1soc_sharedonly_vga/system/system_bb.v | 4,723 | module MODULE1 (
VAR60,
VAR33,
VAR38,
VAR5,
VAR16,
VAR14,
VAR24,
VAR48,
VAR19,
VAR57,
VAR36,
VAR30,
VAR9,
VAR62,
VAR7,
VAR28,
VAR42,
VAR18,
VAR45,
VAR10,
VAR29,
VAR35,
VAR41,
VAR2,
VAR52,
VAR23,
VAR43,
VAR46,
VAR15,
VAR65,
VAR22,
VAR58,
VAR37,
VAR26,
VAR63,
VAR50,
VAR55,
VAR59,
VAR49,
VAR66,
VAR56,
VAR34,
VAR39,
VAR3,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.blackbox.v | 1,288 | module MODULE1 (
VAR6,
VAR2,
VAR5,
VAR8
);
output VAR6;
input VAR2;
input VAR5;
input VAR8;
supply1 VAR7;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/cf_csc_1.v | 4,299 | module MODULE1 (
clk,
VAR31,
VAR18,
VAR1,
VAR17,
VAR6,
VAR8,
VAR4,
VAR25,
VAR26,
VAR12,
VAR30,
VAR2);
input clk;
input VAR31;
input VAR18;
input VAR1;
input [23:0] VAR17;
input [16:0] VAR6;
input [16:0] VAR8;
input [16:0] VAR4;
input [24:0] VAR25;
output VAR26;
output VAR12;
output VAR30;
output [ 7:0] VAR2;
wire [24:0... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_1.functional.v | 1,909 | module MODULE1( VAR6, VAR22, VAR24, VAR11, VAR7, VAR12, VAR4 );
input VAR4, VAR12, VAR11, VAR7, VAR22, VAR6;
output VAR24;
wire VAR20;
not VAR21( VAR20, VAR4 );
wire VAR16;
not VAR5( VAR16, VAR12 );
wire VAR23;
and VAR19( VAR23, VAR20, VAR16 );
wire VAR9;
not VAR18( VAR9, VAR11 );
wire VAR25;
not VAR8( VAR25, VAR7 );
w... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_get_0_0/synth/zc702_get_0_0.v | 11,197 | module MODULE1 (
VAR68,
VAR10,
VAR12,
VAR13,
VAR25,
VAR36,
VAR65,
VAR11,
VAR61,
VAR66,
VAR1,
VAR31,
VAR29,
VAR24,
VAR52,
VAR9,
VAR72,
VAR34,
VAR27,
VAR57,
VAR71,
VAR5,
VAR35,
VAR21,
VAR63,
VAR54,
VAR39,
VAR8,
VAR58,
VAR40,
VAR33,
VAR4,
VAR67,
VAR37,
VAR7,
VAR20,
VAR30,
VAR32,
VAR44,
VAR38,
VAR26,
VAR14,
VAR62,
VAR19,
V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i.symbol.v | 1,352 | module MODULE1 (
input VAR4,
input VAR5,
output VAR1 ,
input VAR7
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
osecpu/fpga | osecpu.v | 2,339 | module MODULE1(clk, reset, VAR50, VAR32, VAR51);
input clk;
input reset;
output reg [31:0] VAR50 = 0;
output [15:0] VAR51;
output [7:0] VAR32;
wire [31:0] VAR59, VAR29, VAR26;
wire [3:0] VAR20;
wire VAR55;
wire [5:0] VAR61, VAR5, VAR17;
wire [31:0] VAR28, VAR46, VAR8;
wire VAR3;
wire [5:0] VAR52, VAR38, VAR24;
wire [11... | mit |
euryecetelecom/euryspace | hw/rtl/euryspace_soc/wb_intercon.v | 36,197 | module MODULE1
(input VAR18,
input VAR73,
input [31:0] VAR126,
input [31:0] VAR339,
input [3:0] VAR277,
input VAR111,
input VAR87,
input VAR257,
input [2:0] VAR187,
input [1:0] VAR357,
output [31:0] VAR3,
output VAR181,
output VAR43,
output VAR396,
input [31:0] VAR86,
input [31:0] VAR275,
input [3:0] VAR183,
input VAR1... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,009 | module MODULE1
(
VAR22,
VAR4,
VAR3) ;
input [0:0] VAR22;
output [0:0] VAR4;
output [0:0] VAR3;
wire [0:0] VAR35;
wire [0:0] VAR6;
wire [0:0] VAR19;
wire [0:0] VAR8;
wire [0:0] VAR2;
wire [0:0] VAR33;
wire [0:0] VAR5;
wire [0:0] VAR27;
wire [0:0] VAR26;
wire [0:0] VAR25;
VAR12 VAR17
(
.VAR14(VAR33),
.VAR30(VAR35[0:0]),
... | gpl-3.0 |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_pipereg.v | 1,756 | typedef VAR8 VAR4;
module MODULE1 (VAR5, VAR7, VAR6, VAR1, ready, valid, clk, VAR2);
input VAR5, VAR7, clk, VAR2;
input VAR4 VAR6;
output VAR4 VAR1;
output valid, ready;
logic valid;
VAR4 VAR3;
always@(posedge clk) begin
if (!VAR2) begin
valid<=1'b0;
end else begin
end
assert (!(VAR5 & !ready)) else
if (VAR7) begin
end... | gpl-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/system_0_clock_0.v | 23,542 | module MODULE2 (
VAR19,
VAR33,
VAR15,
VAR2
)
;
output VAR2;
input VAR19;
input VAR33;
input VAR15;
reg VAR50;
wire VAR2;
always @(posedge VAR19 or negedge VAR15)
begin
if (VAR15 == 0)
VAR50 <= 0;
end
else
VAR50 <= VAR33;
end
assign VAR2 = VAR33 ^ VAR50;
endmodule
module MODULE5 (
VAR68,
VAR13,
VAR27,
VAR42,
VAR57,
VAR4... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai.pp.blackbox.v | 1,393 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR2,
VAR6,
VAR4 ,
VAR9
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211o/sky130_fd_sc_ms__a211o_4.v | 2,348 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR11 ,
VAR9 ,
VAR8 ,
VAR7,
VAR1,
VAR5 ,
VAR4
);
output VAR10 ;
input VAR2 ;
input VAR11 ;
input VAR9 ;
input VAR8 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR4 ;
VAR6 VAR3 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.... | apache-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_lfsr.v | 3,706 | module MODULE1
(clk, reset, VAR23, VAR21, VAR22, VAR20, VAR7, VAR19);
parameter VAR15 = 32;
parameter VAR5 = 0;
parameter [VAR5:(VAR5+VAR15)-1] VAR10 = {VAR15{1'b1}};
parameter VAR16 = 1;
parameter VAR18 = VAR11;
input clk;
input reset;
input VAR23;
input VAR21;
input [0:VAR15-1] VAR22;
input VAR20;
input [VAR5:(VAR5+V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2.symbol.v | 1,322 | module MODULE1 (
input VAR8,
input VAR6,
output VAR1 ,
input VAR4
);
supply1 VAR3;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/ecc/ecc_buf.v | 6,156 | module MODULE1
parameter VAR27 = 100,
parameter VAR31 = 64,
parameter VAR32 = 4,
parameter VAR21 = 1,
parameter VAR44 = 64
)
(
VAR45,
clk, rst, VAR15, VAR18, VAR37,
VAR7, VAR13, VAR2
);
input clk;
input rst;
input [VAR32-1:0] VAR15;
input [VAR21-1:0] VAR18;
wire [4:0] VAR23;
input [VAR32-1:0] VAR37;
input [VAR21-1:0] V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.v | 2,477 | module MODULE1 (
VAR6 ,
VAR4,
VAR8,
VAR9 ,
VAR2 ,
VAR7,
VAR3,
VAR1 ,
VAR11
);
output VAR6 ;
input VAR4;
input VAR8;
input VAR9 ;
input VAR2 ;
input VAR7;
input VAR3;
input VAR1 ;
input VAR11 ;
VAR10 VAR5 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR11(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2i/sky130_fd_sc_ls__mux2i.behavioral.v | 1,654 | module MODULE1 (
VAR2 ,
VAR1,
VAR5,
VAR11
);
output VAR2 ;
input VAR1;
input VAR5;
input VAR11 ;
supply1 VAR8;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR9;
VAR3 VAR10 (VAR9, VAR1, VAR5, VAR11 );
buf VAR12 (VAR2 , VAR9);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.functional.pp.v | 8,443 | module MODULE1 (
VAR44 ,
VAR7 ,
VAR24 ,
VAR9,
VAR29,
VAR3 ,
VAR16
);
output VAR44 ;
input [15:0] VAR7 ;
input [15:0] VAR24 ;
input VAR9;
input VAR29;
input VAR3 ;
input VAR16 ;
wire VAR67 ;
wire VAR31 ;
wire VAR14 ;
wire VAR79 ;
wire VAR5 ;
wire VAR57 ;
wire VAR84 ;
wire VAR50 ;
wire VAR43 ;
wire VAR71 ;
wire VAR53 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxbp/sky130_fd_sc_hd__dfxbp.pp.blackbox.v | 1,314 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR8,
VAR4,
VAR2 ,
VAR6
);
output VAR1 ;
output VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR8;
input VAR4;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4/sky130_fd_sc_hs__and4_4.v | 2,115 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR9 ,
VAR2 ,
VAR6 ,
VAR4,
VAR8
);
output VAR7 ;
input VAR5 ;
input VAR9 ;
input VAR2 ;
input VAR6 ;
input VAR4;
input VAR8;
VAR3 VAR1 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR7,
VAR5,
VAR9,
VAR2,
VAR6
);
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fillcap/gf180mcu_fd_sc_mcu9t5v0__fillcap_4.behavioral.pp.v | 1,084 | module MODULE1( VAR1, VAR3 );
inout VAR1, VAR3;
VAR4 VAR5(.VAR1(VAR1),.VAR3(VAR3));
VAR4 VAR2(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp.functional.v | 1,648 | module MODULE1 (
VAR11,
VAR2,
VAR7
);
output VAR11;
input VAR2;
input VAR7 ;
wire VAR3 ;
wire VAR5 ;
wire VAR6 ;
wire VAR10;
not VAR4 (VAR5 , VAR7 );
VAR1 VAR12 VAR8 (VAR3 , VAR2, VAR5 );
and VAR9 (VAR11 , VAR3, VAR7 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_rptr_a.v | 6,235 | module MODULE1(VAR20 ,VAR91 ,VAR18 ,VAR40 ,VAR48 ,VAR83 ,VAR86
,VAR47 ,VAR49 ,VAR38 ,VAR79 ,VAR56 ,VAR75 ,VAR15 ,VAR6 ,VAR57 ,VAR31 ,
VAR23 ,VAR9 ,VAR4 ,VAR84 ,VAR78 ,VAR11 ,VAR61 ,VAR71 ,VAR19 ,VAR30 ,VAR43 ,
VAR39 ,VAR66 ,VAR22 ,VAR2 ,VAR28 ,VAR81 ,VAR50 ,VAR35 ,VAR64 ,VAR80 ,VAR95
,VAR72 ,VAR54 ,VAR27 ,VAR14 ,VAR52 ... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Video_DMA.v | 9,426 | module MODULE1 (
clk,
reset,
VAR14,
VAR5,
VAR16,
VAR33,
VAR2,
VAR3,
VAR39,
VAR10,
VAR4,
VAR30,
VAR12,
VAR8,
VAR40,
VAR15,
VAR44,
VAR41
);
parameter VAR36 = 15; parameter VAR11 = 0; parameter VAR29 = 320; parameter VAR35 = 240;
parameter VAR31 = 16; parameter VAR22 = 8; parameter VAR1 = 7;
parameter VAR18 = 15;
paramete... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp.functional.v | 1,752 | module MODULE1 (
VAR11 ,
VAR7,
VAR13 ,
VAR2,
VAR3
);
output VAR11 ;
input VAR7;
input VAR13 ;
input VAR2;
input VAR3;
wire VAR6 ;
wire VAR1;
VAR4 VAR5 (VAR1, VAR13, VAR2, VAR3 );
VAR9 VAR8 VAR12 (VAR6 , VAR1, VAR7 );
buf VAR10 (VAR11 , VAR6 );
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/src/v/bsg_wormhole_stream_out.v | 8,220 | module MODULE1
, parameter VAR44 = 0
, parameter VAR23(VAR1)
, parameter VAR26 = 0
, parameter VAR23(VAR20)
, parameter VAR23(VAR25)
, parameter VAR23(VAR31)
, parameter VAR17 = VAR44 + VAR1 + VAR26 + VAR20
)
(input VAR52
, input VAR45
, input [VAR65-1:0] VAR48
, input VAR35
, output VAR24
, output [VAR17-1:0] VAR15
, ... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_8.behavioral.pp.v | 1,167 | module MODULE1( VAR4, VAR6, VAR3, VAR2 );
input VAR4;
inout VAR3, VAR2;
output VAR6;
VAR1 VAR7(.VAR4(VAR4),.VAR6(VAR6),.VAR3(VAR3),.VAR2(VAR2));
VAR1 VAR5(.VAR4(VAR4),.VAR6(VAR6),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.functional.v | 2,393 | module MODULE1 (
VAR17 ,
VAR16 ,
VAR22 ,
VAR23 ,
VAR7 ,
VAR12 ,
VAR20 ,
VAR14
);
output VAR17 ;
output VAR16 ;
input VAR22 ;
input VAR23 ;
input VAR7 ;
input VAR12 ;
input VAR20 ;
input VAR14;
wire VAR2 ;
wire VAR11 ;
wire VAR18 ;
wire VAR8 ;
wire VAR19;
not VAR10 (VAR2 , VAR14 );
not VAR9 (VAR11 , VAR20 );
not VAR6 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi_2.v | 2,352 | module MODULE2 (
VAR10 ,
VAR8 ,
VAR11 ,
VAR7 ,
VAR3 ,
VAR5,
VAR6,
VAR4 ,
VAR2
);
output VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR7 ;
input VAR3 ;
input VAR5;
input VAR6;
input VAR4 ;
input VAR2 ;
VAR9 VAR1 (
.VAR10(VAR10),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b_2.v | 2,291 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR10 ,
VAR6,
VAR2,
VAR11 ,
VAR3
);
output VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR10 ;
input VAR6;
input VAR2;
input VAR11 ;
input VAR3 ;
VAR5 VAR4 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pe_pp_pg/sky130_fd_sc_hs__udp_dff_pe_pp_pg.blackbox.v | 1,386 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR6 ,
VAR1,
VAR4 ,
VAR5
);
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR1;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.v | 2,695 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR12 ,
VAR6,
VAR11 ,
VAR4 ,
VAR8 ,
VAR2
);
output VAR9 ;
output VAR7 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR12 ;
input VAR6;
input VAR11 ;
input VAR4 ;
input VAR8 ;
input VAR2 ;
VAR3 VAR13 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR... | apache-2.0 |
hacktoberfest17/programming | computer_architecture/Unspecified/mux.v | 1,399 | module MODULE1(VAR8,VAR6,VAR10,VAR12,VAR4,VAR11,VAR2,VAR3,VAR1,VAR5,VAR7,VAR9);
input VAR8,VAR6,VAR10,VAR12,VAR4,VAR11,VAR2,VAR3,VAR1,VAR5,VAR7;
output VAR9;
assign VAR9=((VAR8&(!VAR1)&(!VAR5)&(!VAR7))|(VAR6&(!VAR1)&(!VAR5)&(VAR7))|(VAR10&(!VAR1)&(VAR5)&(!VAR7))|(VAR12&(!VAR1)&(VAR5)&(VAR7))|(VAR4&(VAR1)&(!VAR5)&(!VAR7... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_1.functional.v | 1,158 | module MODULE1( VAR3, VAR5, VAR10 );
input VAR5, VAR3;
output VAR10;
wire VAR1;
and VAR6( VAR1, VAR5, VAR3 );
wire VAR8;
not VAR4( VAR8, VAR5 );
wire VAR9;
not VAR7( VAR9, VAR3 );
wire VAR11;
and VAR2( VAR11, VAR8, VAR9 );
or VAR12( VAR10, VAR1, VAR11 );
endmodule | apache-2.0 |
jaechoon2/FPGA-Imaging-Library | BoardInit_AXI/hdl/BoardInit_AXI_v1_0_S00_AXI.v | 31,230 | module MODULE1 #
(
parameter integer VAR100 = 9,
parameter integer VAR3 = 8,
parameter integer VAR50 = 8,
parameter integer VAR96 = 32,
parameter integer VAR28 = 7
)
(
input wire VAR48,
input wire VAR10,
output wire VAR89,
output wire VAR92,
output wire[VAR3 - 1 : 0] VAR54,
output wire[VAR3 - 1 : 0] VAR64,
output wire[... | lgpl-2.1 |
gbraad/minimig-de1 | rtl/or1200/or1200_sprs.v | 14,160 | module MODULE1(
clk, rst,
VAR25, VAR29, flag, VAR73, VAR39, VAR14,
VAR84, VAR59, VAR70, VAR23, VAR56,
VAR85, VAR52, VAR63, VAR36,
VAR18, VAR19, VAR53, VAR72, VAR8, VAR20, VAR28, VAR30,
VAR60, VAR76, VAR86, VAR49, VAR41,
VAR2, VAR1, VAR15,
VAR44, VAR68, VAR40,
VAR5, VAR55, VAR12, VAR51,
VAR62, VAR82, VAR81,
VAR6, VAR42
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211a/sky130_fd_sc_hdll__o211a_1.v | 2,364 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR6 ,
VAR10,
VAR2,
VAR9 ,
VAR11
);
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR10;
input VAR2;
input VAR9 ;
input VAR11 ;
VAR8 VAR7 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR9(VAR9),
.VA... | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Level_1_Cache.v | 3,865 | module MODULE1(
input VAR45,
input VAR76,
input [29:0] VAR42,
input [3:0] VAR19,
input [31:0] VAR68,
output [31:0] VAR26,
input VAR33,
output VAR50,
input VAR46,
output VAR56,
output [29:0] VAR60,
output VAR6,
input [4095:0] VAR39,
output [4095:0] VAR85,
output VAR32,
input VAR63,
output VAR84
);
wire [3:0] VAR23, VAR8... | lgpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_add_sub/float_add_sub.v | 110,547 | module MODULE1
(
VAR8,
VAR5,
VAR2,
VAR11,
VAR3,
VAR12) ;
input VAR8;
input VAR5;
input VAR2;
input [25:0] VAR11;
input [4:0] VAR3;
output [25:0] VAR12;
tri0 VAR8;
tri1 VAR5;
tri0 VAR2;
reg [0:0] VAR10;
reg [25:0] VAR14;
wire [5:0] VAR4;
wire VAR13;
wire [15:0] VAR6;
wire [155:0] VAR9;
wire [4:0] VAR7;
wire [129:0] VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn.functional.pp.v | 1,872 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR1,
VAR7,
VAR3,
VAR5 ,
VAR13
);
output VAR11 ;
input VAR2 ;
input VAR1;
input VAR7;
input VAR3;
input VAR5 ;
input VAR13 ;
wire VAR12 ;
wire VAR8;
VAR10 VAR9 (VAR12 , VAR2, VAR7, VAR3 );
VAR10 VAR6 (VAR8, VAR1, VAR7, VAR3 );
notif0 VAR4 (VAR11 , VAR12, VAR8);
endmodule | apache-2.0 |
valkwarble/finalProject | source/zbt_6111.v | 2,879 | module MODULE1(clk, VAR5, VAR11, addr, VAR3, VAR2,
VAR7, VAR6, VAR4, VAR9, VAR8);
input clk; input VAR5; input VAR11; input [18:0] addr; input [35:0] VAR3; output [35:0] VAR2; output VAR7; output VAR6; output [18:0] VAR4; inout [35:0] VAR9; output VAR8;
wire VAR8 = ~VAR5;
reg [1:0] VAR1;
always @(posedge clk)
VAR1 <= V... | gpl-2.0 |
pwwu/FPGA | VGAbased/final/study_text.v | 4,783 | module MODULE1
(
input wire clk,
input wire [9:0] VAR13, VAR5,
output wire [3:0] VAR12,
output reg [2:0] VAR18
);
wire [10:0] VAR16;
reg [6:0] VAR11, VAR10;
reg [3:0] VAR15;
reg [2:0] VAR14;
wire [7:0] VAR7;
wire VAR8, VAR6;
wire [5:0] VAR9;
wire [3:0] VAR2;
wire [2:0] VAR4;
VAR17 VAR3
(.clk(clk), .addr(VAR16), .VAR1(V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe.blackbox.v | 1,210 | module MODULE1 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi.symbol.v | 1,379 | module MODULE1 (
input VAR6,
input VAR5,
input VAR8,
input VAR1,
output VAR9
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type.v | 1,113 | module MODULE1
(
VAR1,
VAR3
);
input signed [35:0] VAR1; output signed [35:0] VAR3;
wire signed [35:0] VAR2;
assign VAR2 = {VAR1[35], VAR1[35:1]};
assign VAR3 = VAR2;
endmodule | gpl-3.0 |
Anirudh94/Connect4-FPGA | Connect4/redDiskWin.v | 6,235 | module MODULE1 (
address,
VAR16,
VAR19);
input [7:0] address;
input VAR16;
output [2:0] VAR19;
tri1 VAR16;
wire [2:0] VAR5;
wire [2:0] VAR19 = VAR5[2:0];
VAR50 VAR40 (
.VAR6 (address),
.VAR7 (VAR16),
.VAR38 (VAR5),
.VAR35 (1'b0),
.VAR10 (1'b0),
.VAR23 (1'b1),
.VAR8 (1'b0),
.VAR28 (1'b0),
.VAR24 (1'b1),
.VAR46 (1'b1),
.... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_seeed_tft/rtl/seeed_tft.v | 6,125 | module MODULE1 #(
parameter VAR6 = 12
)(
input rst,
input clk,
output [31:0] VAR11,
input VAR34,
input [7:0] VAR47,
input [31:0] VAR44,
input [31:0] VAR50,
input [7:0] VAR42,
input VAR20,
input VAR30,
input VAR5,
input VAR33,
input VAR27,
input VAR60,
input VAR23,
input VAR9,
input [7:0] VAR3,
output [7:0] VAR46,
outpu... | mit |
rkrajnc/minimig-mist | rtl/minimig/paula_intcontroller.v | 4,459 | module MODULE1
(
input clk, input VAR23,
input reset, input [8:1] VAR7, input [15:0] VAR12, output [15:0] VAR26, input VAR17, input VAR9, input VAR1, input VAR15, input VAR19, input VAR21, input VAR16, input VAR18, input [3:0] VAR20, output [3:0] VAR25, output VAR11, output reg [2:0] VAR22 );
parameter VAR8 = 9'h01c;
p... | gpl-3.0 |
jacgoudsmit/P8X32A_Emulation | P8X32A_Nexys4/src/hub_mem.v | 2,747 | module MODULE1
(
input VAR1,
input VAR4,
input VAR5,
input [3:0] VAR8,
input [13:0] VAR3,
input [31:0] VAR6,
output [31:0] VAR10
);
reg [7:0] VAR7 [16*1024-1:0]; reg [7:0] VAR9 [16*1024-1:0];
reg [7:0] VAR11 [16*1024-1:0];
reg [7:0] VAR2 [16*1024-1:0];
begin
begin
begin
begin
begin | gpl-3.0 |
aj-michael/Digital-Systems | Pong/Phase3/TermProjectPhase3/CRTClock.v | 1,033 | module MODULE1(VAR2, VAR3, VAR1, VAR6, VAR7);
parameter VAR5=10;
input [VAR5-1:0] VAR2;
input [VAR5-1:0] VAR3;
output VAR1;
input VAR6;
input VAR7;
reg [VAR5-1:0] counter;
wire [VAR5-1:0] VAR4;
assign VAR4 = (VAR2 / VAR3) - 1;
assign VAR1 = counter > (VAR4 >> 1);
always @ (posedge VAR7 or posedge VAR6)
if (VAR6) counte... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrbp/sky130_fd_sc_hs__dfrbp.blackbox.v | 1,338 | module MODULE1 (
VAR5,
VAR3 ,
VAR7 ,
VAR4 ,
VAR6
);
input VAR5;
input VAR3 ;
input VAR7 ;
output VAR4 ;
output VAR6 ;
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_mm_interconnect_1.v | 16,432 | module MODULE1 (
input wire VAR54, input wire VAR91, input wire [29:0] VAR27, output wire VAR63, input wire [0:0] VAR26, input wire [7:0] VAR74, input wire VAR61, output wire [63:0] VAR25, output wire VAR23, input wire VAR98, input wire [63:0] VAR1, input wire VAR92, output wire [3:0] VAR88, output wire VAR59, output w... | mit |
freecores/logicprobe | src/fpga/LogicProbe.v | 6,429 | module MODULE2(VAR1, reset, VAR20, VAR31, VAR3, VAR8);
input VAR1;
input reset;
input VAR20;
input VAR31;
input [127:0] VAR3;
output VAR8;
wire VAR16;
reg [12:0] VAR23;
wire [7:0] VAR25;
reg write;
wire ready;
reg VAR21;
reg state;
MODULE3
MODULE3(VAR1, reset, VAR20, VAR31, VAR3, VAR16, VAR23, VAR25);
MODULE4
MODULE2(V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo_2.v | 2,334 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR8 ,
VAR1,
VAR6,
VAR2,
VAR9 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR6;
input VAR2;
input VAR9 ;
input VAR4 ;
VAR10 VAR5 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
V... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_sgmii/altera_tse_rgmii_in1.v | 5,071 | module MODULE1 (
VAR7,
VAR22,
VAR4,
VAR18,
VAR17);
input VAR7;
input VAR22;
input VAR4;
output VAR18;
output VAR17;
wire [0:0] VAR8;
wire [0:0] VAR19;
wire [0:0] VAR2 = VAR8[0:0];
wire VAR18 = VAR2;
wire [0:0] VAR14 = VAR19[0:0];
wire VAR17 = VAR14;
wire VAR10 = VAR22;
wire VAR5 = VAR10;
VAR9 VAR16 (
.VAR22 (VAR5),
.VA... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/fifo/ram_352_64.v | 11,235 | module MODULE1 (
VAR35,
VAR9,
VAR31,
VAR42,
VAR54,
VAR60,
VAR58,
VAR50,
VAR11,
VAR1,
VAR33);
input [5:0] VAR35;
input [5:0] VAR9;
input VAR31;
input [351:0] VAR42;
input [351:0] VAR54;
input VAR60;
input VAR58;
input VAR50;
input VAR11;
output [351:0] VAR1;
output [351:0] VAR33;
tri1 VAR31;
tri1 VAR60;
tri1 VAR58;
tri0... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_add_op.v | 2,484 | module MODULE1( VAR5, VAR19, VAR11, VAR7, VAR8, VAR15, VAR6,
VAR9, VAR1, VAR12,
VAR2, VAR20, VAR14, VAR17, enable);
parameter VAR21 = 1;
input VAR5, VAR19, VAR8, VAR15;
input [26:0] VAR11;
input [26:0] VAR7;
input [8:0] VAR6;
input VAR2, VAR14, enable;
output reg [27:0] VAR9;
output reg [8:0] VAR1;
output reg VAR12;
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2_1.v | 2,113 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR5 ,
VAR9,
VAR2,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR9;
input VAR2;
input VAR6 ;
input VAR3 ;
VAR8 VAR4 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1,
VAR7,
VAR5
);
output VAR1;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor3/sky130_fd_sc_hdll__xor3_2.v | 2,215 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR5 ,
VAR2 ,
VAR9,
VAR10,
VAR1 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR2 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR8 ;
VAR6 VAR3 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR1 ,
input VAR4 ,
output VAR6 ,
input VAR5 ,
input VAR7,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s.behavioral.v | 1,438 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR4;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR3 ;
wire VAR7;
buf VAR1 (VAR7, VAR6 );
buf VAR8 (VAR2 , VAR7 );
endmodule | apache-2.0 |
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