repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jobisoft/jTDC | modules/counter/slimfast_multioption_counter.v | 5,867 | module MODULE2 (VAR16,
VAR8,
reset,
VAR18);
parameter VAR17 = 1;
parameter VAR19 = 1;
parameter VAR4 = 31;
parameter VAR22 = 32;
input wire VAR16;
input wire VAR8;
input wire reset;
output wire [VAR22-1:0] VAR18;
wire [VAR4-3:0] VAR11;
wire [VAR4-3:0] VAR15;
MODULE1 #(.VAR17(VAR17),.VAR19(VAR19),.VAR4(VAR4),.VAR22(VAR2... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ddr3_source/clocking/mig_7series_v1_9_clk_ibuf.v | 5,125 | module MODULE1 #
(
parameter VAR1 = "VAR5",
parameter VAR23 = "VAR18"
)
(
input VAR22, input VAR11,
input VAR16,
output VAR20,
output VAR15
);
wire VAR4 ;
generate
if (VAR1 == "VAR5") begin: VAR10
VAR19 #
(
.VAR6 (VAR23),
.VAR14 ("VAR21")
)
VAR12
(
.VAR3 (VAR22),
.VAR2 (VAR11),
.VAR17 (VAR4)
);
assign VAR15 = VAR16;
en... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.pp.symbol.v | 1,497 | module MODULE1 (
input VAR1 ,
output VAR5 ,
input VAR2,
input VAR3 ,
input VAR9 ,
input VAR6 ,
input VAR10 ,
input VAR4 ,
input VAR7 ,
input VAR8
);
endmodule | apache-2.0 |
AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM | idxram.v | 5,431 | module MODULE1
wire [2 :0] VAR18 = VAR9[2 :0];
wire [1 :0] VAR1 = VAR9[4 :3];
wire [4 :0] VAR16 = VAR9[4 :0];
wire [VAR20(VAR25)+4:0] VAR24 = VAR9[VAR20(VAR25)+9:5];
wire [32*5-1:0] VAR5;
genvar VAR28;
generate
for (VAR28=0 ; VAR28<4 ; VAR28=VAR28+1) begin: VAR29
VAR7 #( .VAR8 (5 ), .VAR4 (40 ), .VAR26 (VAR25*1024/4 ),... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.behavioral.pp.v | 2,086 | module MODULE1 (
VAR17 ,
VAR12 ,
VAR13 ,
VAR16 ,
VAR9 ,
VAR3 ,
VAR14,
VAR5,
VAR8 ,
VAR7
);
output VAR17 ;
input VAR12 ;
input VAR13 ;
input VAR16 ;
input VAR9 ;
input VAR3 ;
input VAR14;
input VAR5;
input VAR8 ;
input VAR7 ;
wire VAR18 ;
wire VAR2 ;
wire VAR6;
or VAR1 (VAR18 , VAR13, VAR12 );
nand VAR15 (VAR2 , VAR9, V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync.v | 4,832 | if (VAR29 == VAR9 && VAR23 == VAR39) \
begin: VAR40 \
VAR37 VAR1 \
(.VAR3(VAR21) \
,.VAR6(VAR43) \
,.VAR5(~VAR7) \
,.VAR42(~VAR28) \
,.VAR17(VAR22) \
,.VAR44(VAR24) \
,.VAR20(1'b0) \
); \
end
if (VAR29 == VAR9 && VAR23 == VAR39) \
begin: VAR40 \
wire [VAR33-1:0] VAR32,VAR35; \
assign VAR21 = VAR32[VAR39-1:0]; \
assign ... | bsd-3-clause |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ddr2_if.v | 81,752 | module MODULE1(
input VAR189,
input VAR176,
input reset,
inout [35:0] VAR202,
input VAR7,
input VAR6,
output [31:0] VAR32,
output VAR61,
input VAR113,
input VAR233,
output [31:0] VAR135,
output VAR200,
input VAR37,
input VAR122,
output [31:0] VAR79,
output VAR41,
input VAR182,
input VAR162,
output [31:0] VAR9,
output V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai.blackbox.v | 1,392 | module MODULE1 (
VAR6 ,
VAR1,
VAR5,
VAR9,
VAR10,
VAR7
);
output VAR6 ;
input VAR1;
input VAR5;
input VAR9;
input VAR10;
input VAR7;
supply1 VAR3;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai_1.v | 2,330 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR9 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR4,
VAR5
);
output VAR6 ;
input VAR10 ;
input VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR4;
input VAR5;
VAR8 VAR1 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_sdram_clk.v | 10,654 | module MODULE1
(
VAR9,
VAR7,
VAR8,
VAR1) ;
input VAR9;
input VAR7;
input [0:0] VAR8;
output [0:0] VAR1;
tri0 VAR9;
tri1 VAR7;
reg [0:0] VAR2;
reg [0:0] VAR6;
reg [0:0] VAR3;
wire VAR10;
wire VAR4;
wire VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.symbol.v | 1,380 | module MODULE1 (
input VAR8,
input VAR5,
input VAR10,
input VAR9,
input VAR6,
output VAR2
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/vrt/vita_pkt_gen.v | 1,528 | module MODULE1
(input clk, input reset, input VAR7,
input [15:0] VAR9,
output [35:0] VAR2, output VAR3, input VAR10);
reg [15:0] state;
reg [31:0] VAR5, VAR6;
wire VAR4 = (state == 0);
wire VAR1 = (state == (VAR9-1));
wire VAR8 = VAR3 & VAR10;
assign VAR3 = 1;
always @(posedge clk)
if(reset | VAR7)
begin
state <= 0;
VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.functional.pp.v | 2,026 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR2 ,
VAR16 ,
VAR17 ,
VAR1,
VAR8,
VAR5 ,
VAR9
);
output VAR6 ;
input VAR12 ;
input VAR2 ;
input VAR16 ;
input VAR17 ;
input VAR1;
input VAR8;
input VAR5 ;
input VAR9 ;
wire VAR14 ;
wire VAR15 ;
wire VAR7;
and VAR3 (VAR14 , VAR16, VAR12, VAR2 );
or VAR10 (VAR15 , VAR14, VAR17 );
VAR11 VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_dctldp.v | 53,990 | module MODULE1 (
VAR131, VAR124, VAR83, VAR263,
VAR250, VAR294, VAR13,
VAR91, VAR334, VAR232, VAR273,
VAR173, VAR272, VAR56,
VAR107, VAR149, VAR249,
VAR53, VAR284, VAR329, VAR182,
VAR297, VAR99, VAR48,
VAR341, VAR160, VAR111,
VAR161, VAR209, VAR318, VAR222,
VAR51, VAR104, VAR144,
VAR199, VAR266, VAR103,
VAR333, VAR313,... | gpl-2.0 |
lee-dohm/atom-linguist | samples/Verilog/sqrt_pipelined.v | 7,283 | module MODULE1
(
input clk, input VAR7, input VAR6, input [VAR13-1:0] VAR11, output reg VAR15, output reg [VAR3-1:0] VAR8 );
parameter
VAR13 = 16; localparam
VAR3 = VAR13 / 2 + VAR13 % 2;
reg [VAR3-1:0] VAR12; reg [VAR3*VAR13-1:0] VAR1; reg [VAR3*VAR13-1:0] VAR10; wire [VAR3*VAR13-1:0] VAR5;
always @ (posedge clk or ne... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.behavioral.pp.v | 2,059 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR10 ,
VAR14 ,
VAR17 ,
VAR18 ,
VAR8,
VAR6,
VAR16 ,
VAR12
);
output VAR2 ;
input VAR9 ;
input VAR10 ;
input VAR14 ;
input VAR17 ;
input VAR18 ;
input VAR8;
input VAR6;
input VAR16 ;
input VAR12 ;
wire VAR11 ;
wire VAR5 ;
wire VAR13;
or VAR1 (VAR11 , VAR17, VAR14, VAR10, VAR9 );
nand VAR15... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo.pp.blackbox.v | 1,392 | module MODULE1 (
VAR6 ,
VAR5 ,
VAR8 ,
VAR7,
VAR4,
VAR1,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR7;
input VAR4;
input VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
merckhung/zet | cores/vdu/rtl/vdu.v | 12,231 | module MODULE1 (
input VAR62,
input VAR9,
input [15:0] VAR28,
output reg [15:0] VAR23,
input [19:1] VAR12,
input VAR33,
input VAR72,
input [ 1:0] VAR49,
input VAR55,
input VAR94,
output VAR74,
output reg [ 1:0] VAR11,
output reg [ 1:0] VAR102,
output reg [ 1:0] VAR19,
output reg VAR57,
output reg VAR1
);
parameter VAR5... | gpl-3.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/pcx_stall.v | 6,945 | module MODULE1();
reg VAR15;
wire clk;
wire VAR10, VAR30, VAR17, VAR8;
wire VAR2, VAR28, VAR19, VAR4;
reg VAR1, VAR22, VAR14, VAR5;
integer VAR20, VAR9, VAR26;
integer VAR11, VAR23, VAR27, VAR24, VAR12;
reg VAR16, VAR25, VAR7, VAR29, VAR13;
reg [3:0] VAR6;
reg [3:0] VAR3;
wire [3:0] VAR18;
reg [3:0] VAR21; | gpl-2.0 |
meteorcloudy/CPU_verilog | diff_e2m.v | 1,109 | module MODULE1(
clk,VAR22,
VAR23,VAR19,VAR9,VAR1,VAR11,VAR20,VAR18,
VAR6,VAR8,VAR24,VAR7,VAR5,VAR16,VAR25
);
input clk,VAR22;
input VAR23,VAR19,VAR9;
input[4:0] VAR1;
input[31:0] VAR11,VAR20;
input[1:0] VAR18;
output VAR6,VAR8,VAR24;
output[4:0] VAR7;
output[31:0] VAR5,VAR16;
output[1:0] VAR25;
VAR15 VAR2(VAR23,clk,VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp_1.v | 2,035 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR7,
VAR2,
VAR6
);
output VAR3 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR6;
VAR1 VAR5 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3 ,
VAR4 ,
VAR7
);
output VAR3 ;
input VAR4 ;
input VAR7;
supply1 VAR2;
supply0 VAR6;
VAR1 VAR5 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2oi/sky130_fd_sc_hdll__a2bb2oi_4.v | 2,493 | module MODULE1 (
VAR8 ,
VAR11,
VAR5,
VAR4 ,
VAR7 ,
VAR9,
VAR10,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR11;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR3 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/soc_system_led_pio.v | 2,449 | module MODULE1 (
address,
VAR3,
clk,
VAR4,
VAR9,
VAR7,
VAR5,
VAR1,
VAR6
)
;
output [ 3: 0] VAR1;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR3;
input clk;
input [ 3: 0] VAR4;
input VAR9;
input VAR7;
input [ 31: 0] VAR5;
wire VAR8;
wire [ 3: 0] VAR2;
reg [ 3: 0] VAR11;
wire [ 3: 0] VAR1;
wire [ 3: 0] VAR10;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211ai/sky130_fd_sc_lp__o211ai.pp.blackbox.v | 1,397 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR7 ,
VAR3,
VAR5,
VAR1 ,
VAR9
);
output VAR2 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR7 ;
input VAR3;
input VAR5;
input VAR1 ;
input VAR9 ;
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_clock_converter_v2_1/hdl/verilog/axi_clock_converter_v2_1_axic_sample_cycle_ratio.v | 5,912 | module MODULE1 # (
parameter VAR11 = 2 )
(
input wire VAR4,
input wire VAR17,
output wire VAR9,
output wire VAR3
);
localparam VAR14 = VAR11 > 2 ? VAR11-1 : VAR11-1;
reg VAR1 = 0;
reg VAR6;
reg VAR8;
wire VAR10;
wire VAR13;
reg [VAR14-1:0] VAR15;
reg VAR12;
generate
if (VAR11 == 1) begin : VAR7
assign VAR9 = 1'b1;
assi... | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/reorder_queue_input.v | 17,729 | module MODULE1
parameter VAR37 = 5, parameter VAR63 = 8, parameter VAR60 = 5, parameter VAR18 = 10, parameter VAR78 = VAR11/32,
parameter VAR46 = VAR86(VAR78),
parameter VAR72 = VAR86(VAR78+1),
parameter VAR43 = 2**VAR37)
(input VAR6, input VAR8, input VAR27, input [VAR11-1:0] VAR50, input [(VAR11/32)-1:0] VAR36, input... | bsd-3-clause |
rkrajnc/minimig-de1 | rtl/minimig/Bitplanes.v | 11,290 | module MODULE2
(
input clk, input VAR42, input VAR22, input VAR20,
input [8:1] VAR11, input [15:0] VAR26, input VAR12, input VAR46, input [8:0] VAR29, output [6:1] VAR28 );
parameter VAR6 = 9'h102;
parameter VAR21 = 9'h110;
parameter VAR32 = 9'h112;
parameter VAR39 = 9'h114;
parameter VAR13 = 9'h116;
parameter VAR18 = ... | gpl-3.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/firdecim.v | 5,097 | module MODULE1
(
VAR19, VAR3, VAR20, VAR16, VAR2, VAR11,
VAR15, VAR4, VAR6, VAR1
);
parameter VAR9 = 16;
parameter VAR5 = 32;
parameter VAR10 = 16;
output signed [(VAR9-1):0] VAR19 ;
output signed [(VAR5-1):0] VAR2;
output signed [(VAR5-1):0] VAR11;
output VAR3;
output VAR20;
output VAR16;
input VAR15;
input VAR4;
inpu... | gpl-2.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/radio_bridge_v1_21_a/hdl/verilog/radio_bridge.v | 14,913 | module MODULE2
(
VAR102,
VAR94,
VAR73,
VAR109,
VAR22,
VAR104,
VAR55,
VAR31,
VAR33,
VAR106,
VAR75,
VAR115,
VAR13,
VAR93,
VAR8,
VAR38,
VAR56,
VAR65,
VAR51,
VAR32,
VAR85,
VAR107,
VAR80,
VAR114,
VAR113,
VAR60,
VAR49,
VAR41,
VAR21,
VAR66,
VAR74,
VAR76,
VAR68,
VAR122,
VAR61,
VAR59,
VAR46,
VAR35,
VAR2,
VAR97,
VAR121,
VAR100,
... | bsd-2-clause |
jairov4/accel-oil | solution_kintex7/syn/verilog/nfa_accept_samples_generic_hw.v | 67,236 | module MODULE1 (
VAR162,
VAR184,
VAR74,
VAR10,
VAR171,
VAR189,
VAR296,
VAR140,
VAR64,
VAR130,
VAR275,
VAR138,
VAR269,
VAR167,
VAR111,
VAR248,
VAR57,
VAR83,
VAR67,
VAR161,
VAR174,
VAR229,
VAR254,
VAR223,
VAR51,
VAR152,
VAR109,
VAR178,
VAR53,
VAR286,
VAR175,
VAR196,
VAR94,
VAR194,
VAR237,
VAR144,
VAR221,
VAR160,
VAR205,
... | lgpl-3.0 |
Willster419/ELEC3725_vivado_projects | assignment_7/cpu4.v | 16,564 | module MODULE2(VAR18,clk,VAR17,VAR56);
input clk;
output [31:0] VAR17;
inout [31:0] VAR56;
wire [5:0] VAR30; wire [5:0] VAR29; input [31:0] VAR18; wire [31:0] VAR35; wire [31:0] VAR57; wire [5:0] VAR52; wire [31:0] VAR9; wire [5:0] VAR54; reg VAR6; wire VAR48; reg [1:0] VAR1; wire [1:0] VAR36; wire [1:0] VAR5; wire [1:... | gpl-3.0 |
natsutan/NPU | fpga_implement/npu8/npu8.srcs/sources_1/ip/mul17_16/mul17_16_stub.v | 1,216 | module MODULE1(VAR1, VAR3, VAR4, VAR2)
;
input VAR1;
input [16:0]VAR3;
input [15:0]VAR4;
output [24:0]VAR2;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi_lp.v | 2,360 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR10 ,
VAR4,
VAR2,
VAR6 ,
VAR9
);
output VAR11 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR10 ;
input VAR4;
input VAR2;
input VAR6 ;
input VAR9 ;
VAR8 VAR3 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.... | apache-2.0 |
efabless/openlane | designs/wbqspiflash/src/wbqspiflash.v | 51,177 | module MODULE1(VAR33,
VAR12, VAR2, VAR4, VAR7,
VAR20, VAR36,
VAR32, VAR24, VAR30,
VAR18, VAR1, VAR8, VAR13, VAR6,
VAR34);
parameter VAR14=22;
parameter [0:0] VAR3 = 1'b0;
localparam VAR23 = VAR14-2;
input wire VAR33;
input wire VAR12, VAR2, VAR4, VAR7;
input wire [(VAR23-1):0] VAR20;
input wire [31:0] VAR36;
output reg... | apache-2.0 |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_top.v | 32,536 | module MODULE1(VAR461, VAR373,
VAR115, VAR93, VAR369, VAR110, VAR283, VAR352,
VAR449, VAR21, VAR397, VAR127,
VAR85, VAR273, VAR408, VAR205, VAR237, VAR433,
VAR30, VAR74, VAR47, VAR100,
VAR429, VAR190, VAR327, VAR417, VAR272, VAR140,
VAR442, VAR60, VAR32, VAR400,
VAR170, VAR423, VAR463, VAR61, VAR304, VAR142,
VAR148, VA... | apache-2.0 |
skalldri/mips-verilog | register-file/register-file.v | 1,364 | module MODULE1 (clk, VAR4, VAR6, VAR2, VAR9, VAR12, VAR1, VAR10, VAR5);
parameter VAR13 = 32;
input clk;
input VAR4;
input [31:0] VAR6;
input [5:0] VAR2;
input [5:0] VAR9;
input [4:0] VAR12;
input [31:0] VAR5;
output [31:0] VAR1;
output [31:0] VAR10;
reg [31:0] VAR1 = 0;
reg [31:0] VAR10 = 0;
reg [31:0] VAR3[0:VAR13-1]... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9122_v1_00_a/hdl/verilog/axi_ad9122.v | 11,615 | module MODULE1 (
VAR22,
VAR145,
VAR116,
VAR53,
VAR127,
VAR18,
VAR54,
VAR50,
VAR5,
VAR58,
VAR144,
VAR143,
VAR91,
VAR114,
VAR87,
VAR15,
VAR137,
VAR49,
VAR14,
VAR47,
VAR146,
VAR65,
VAR134,
VAR77,
VAR69,
VAR19,
VAR57,
VAR46,
VAR7,
VAR24,
VAR23,
VAR16,
VAR28,
VAR78,
VAR34,
VAR100,
VAR89,
VAR98,
VAR26);
parameter VAR62 = 0;
... | mit |
tmolteno/TART | hardware/FPGA/ddrmem/spartan3/clocks.v | 2,073 | module MODULE1 (
VAR4, VAR2,
VAR3, VAR1
);
input VAR4;
input VAR2;
output VAR3;
output VAR1;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.functional.pp.v | 2,207 | module MODULE1 (
VAR8 ,
VAR16 ,
VAR20 ,
VAR15 ,
VAR2 ,
VAR7 ,
VAR13,
VAR5,
VAR19 ,
VAR17
);
output VAR8 ;
input VAR16 ;
input VAR20 ;
input VAR15 ;
input VAR2 ;
input VAR7 ;
input VAR13;
input VAR5;
input VAR19 ;
input VAR17 ;
wire VAR4 ;
wire VAR12 ;
wire VAR9 ;
wire VAR11;
and VAR10 (VAR4 , VAR15, VAR2 );
and VAR18 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtn/sky130_fd_sc_hd__dlxtn_2.v | 2,204 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR6,
VAR1 ,
VAR8 ,
VAR2 ,
VAR5
);
output VAR7 ;
input VAR3 ;
input VAR6;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
VAR9 VAR4 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR3 ,
VAR6
);
output VA... | apache-2.0 |
alanachtenberg/CSCE-350 | Project3/ALUControl.v | 1,307 | module MODULE1 (VAR6, VAR12, VAR15);
input [3:0] VAR12;
input [5:0] VAR15;
output[3:0] VAR6;
reg [3:0] VAR6;
always @ (VAR6 or VAR12 or VAR15)
begin
if(VAR12==4'b1111)
begin
case(VAR15)
6'b100000 :VAR6 = VAR8;
6'b100010 :VAR6 = VAR1;
6'b100001 :VAR6 = VAR9;
6'b100011 :VAR6 = VAR16;
6'b000000 :VAR6 = VAR3;
6'b100100 :VA... | gpl-2.0 |
asicguy/gplgpu | hdl/math/flt_det.v | 2,284 | module MODULE1
(
input clk,
input VAR4,
input [128:0] VAR9,
output [31:0] VAR10
);
wire [31:0] VAR8;
wire [31:0] VAR6;
reg [2:0] VAR5;
always @(posedge clk, negedge VAR4)
if(!VAR4) VAR5 <= 3'b000;
else VAR5 <= {VAR5[1:0], VAR9[128]};
VAR7 VAR1(clk, VAR4, VAR9[127:96], VAR9[95:64], VAR8);
VAR7 VAR3(clk, VAR4, VAR9[63:32... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_above.v | 1,149 | module MODULE1(
input VAR3,
input VAR2,
input [31:0] VAR7,
input [31:0] VAR8,
input VAR6,
output [31:0] VAR5,
output reg VAR1
);
reg VAR4;
always @(posedge VAR3) begin
if(VAR2)
VAR1 <= 1'b0;
end
else
VAR1 <= VAR6;
case({VAR7[31], VAR8[31]})
2'b00: VAR4 <= VAR7[30:0] > VAR8[30:0];
2'b01: VAR4 <= 1'b1;
2'b10: VAR4 <= 1'b... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.v | 2,265 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR1,
VAR8 ,
VAR4 ,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR1;
input VAR8 ;
input VAR4 ;
input VAR3 ;
input VAR6 ;
VAR2 VAR9 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7 ,
VAR5 ,
VAR1
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.behavioral.pp.v | 1,712 | module MODULE1 (
VAR9,
VAR7,
VAR4 ,
VAR2 ,
VAR6
);
input VAR9;
input VAR7;
output VAR4 ;
input VAR2 ;
input VAR6 ;
wire VAR8 ;
wire VAR3;
xor VAR1 (VAR8 , VAR6, VAR2 );
VAR11 VAR5 (VAR3, VAR8, VAR9, VAR7);
buf VAR10 (VAR4 , VAR3 );
endmodule | apache-2.0 |
revaldinho/opc | opc5ls/opc5lscpu.v | 4,799 | module MODULE1( input[15:0] din, input clk, input VAR55, input VAR45, input VAR50, output VAR63, output VAR54, output[15:0] dout, output[15:0] address, output VAR42);
parameter VAR28=4'h0,VAR27=4'h1,VAR22=4'h2,VAR34=4'h3,VAR61=4'h4,VAR60=4'h5,VAR4=4'h6,VAR41=4'h7,VAR64=4'h8,VAR49=4'h9,VAR17=4'hA,VAR19=4'hB,VAR5=4'hC,VA... | gpl-3.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_axis_dwidth_converter_1_1/axis_register_slice_v1_1/hdl/verilog/axis_register_slice_v1_1_axis_register_slice.v | 8,862 | module MODULE1 #
(
parameter VAR61 = "VAR52",
parameter integer VAR20 = 32,
parameter integer VAR29 = 1,
parameter integer VAR62 = 1,
parameter integer VAR39 = 1,
parameter [31:0] VAR8 = 32'hFF,
parameter integer VAR16 = 0
)
(
input wire VAR46,
input wire VAR7,
input wire VAR33,
input wire VAR12,
output wire VAR37,
inp... | bsd-2-clause |
oddball/genMem | vendorMemModels/someTwoPortVendorMem_4096_32_0.v | 1,128 | module MODULE1 (VAR2,
VAR14,
VAR1,
VAR12,
VAR6,
VAR7,
VAR4,
VAR13,
VAR15,
VAR3,
VAR10,
VAR9,
VAR5,
VAR8);
output [31:0] VAR2;
input VAR14;
input VAR1;
input VAR12;
input [11:0] VAR6;
input [31:0] VAR7;
input VAR4;
output [31:0] VAR13;
input VAR15;
input VAR3;
input VAR10;
input [11:0] VAR9;
input [31:0] VAR5;
input VAR... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x4_128/pci_express_compiler-library/altpcie_pll_phy5_62p5.v | 17,944 | module MODULE1 (
VAR22,
VAR108,
VAR14,
VAR81,
VAR75,
VAR3);
input VAR22;
input VAR108;
output VAR14;
output VAR81;
output VAR75;
output VAR3;
tri0 VAR22;
wire [5:0] VAR37;
wire VAR68;
wire [0:0] VAR15 = 1'h0;
wire [2:2] VAR8 = VAR37[2:2];
wire [1:1] VAR51 = VAR37[1:1];
wire [0:0] VAR55 = VAR37[0:0];
wire VAR14 = VAR55;... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfstp/sky130_fd_sc_ms__dfstp.functional.pp.v | 1,825 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR6 ,
VAR1,
VAR10 ,
VAR13 ,
VAR9 ,
VAR7
);
output VAR12 ;
input VAR4 ;
input VAR6 ;
input VAR1;
input VAR10 ;
input VAR13 ;
input VAR9 ;
input VAR7 ;
wire VAR14;
wire VAR2 ;
not VAR11 (VAR2 , VAR1 );
VAR15 VAR3 VAR5 (VAR14 , VAR6, VAR4, VAR2, , VAR10, VAR13);
buf VAR8 (VAR12 , VAR14 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.pp.symbol.v | 1,325 | module MODULE1 (
input VAR6 ,
input VAR1 ,
output VAR7 ,
input VAR5 ,
input VAR2,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/udp_tx.v | 9,350 | module MODULE2
( input VAR79,
input [7:0] VAR3,
input VAR33,
input [15:0] VAR80,
input [31:0] VAR97,
input [31:0] VAR49,
output [7:0] VAR15,
output VAR18,
output VAR37);
wire [31:0] VAR77, VAR28;
sync #(32) VAR11(.clk(VAR57), .in(VAR97), .out(VAR77));
sync #(32) VAR83(.clk(VAR57), .in(VAR49), .out(VAR28));
wire [15:0] ... | apache-2.0 |
wgml/sysrek | rgb2hsv/ipcore_dir/sub10.v | 16,252 | module MODULE2 (
clk, VAR74, VAR121, VAR53, VAR186
);
input clk;
input VAR74;
input [9 : 0] VAR121;
input [9 : 0] VAR53;
output [9 : 0] VAR186;
wire \VAR46/VAR108 ;
wire \VAR46/VAR152 ;
wire \VAR46/VAR112 ;
wire \VAR46/VAR168 ;
wire \VAR46/VAR92 ;
wire \VAR46/VAR190 ;
wire \VAR46/VAR119 ;
wire \VAR46/VAR91 ;
wire \VAR4... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_img_0_data_stream_1_V.v | 3,017 | module MODULE2 (
clk,
VAR18,
VAR26,
VAR24,
VAR5);
parameter VAR27 = 32'd8;
parameter VAR25 = 32'd1;
parameter VAR21 = 32'd2;
input clk;
input [VAR27-1:0] VAR18;
input VAR26;
input [VAR25-1:0] VAR24;
output [VAR27-1:0] VAR5;
reg[VAR27-1:0] VAR1 [0:VAR21-1];
integer VAR4;
always @ (posedge clk)
begin
if (VAR26)
begin
for... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/bp_litex/bp2wb_convertor.v | 9,136 | module MODULE1
import VAR42::*;
import VAR55::*;
, localparam VAR57 = VAR19 / 64
, localparam VAR28 = VAR19 / 8
, localparam VAR37 = VAR34 / 8 , localparam VAR7 = VAR21(VAR28)
, localparam VAR50 = VAR21(VAR57)
, localparam VAR15 = VAR21(VAR37)
, localparam VAR56 = 64
, localparam VAR27 = VAR53
, localparam VAR38 = 64 ,... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/rtl/bw_clk_cl_sparc_cmp.v | 3,670 | module MODULE1(
VAR4, VAR7, VAR11, VAR10,
VAR12, VAR13, VAR14, VAR1, VAR9, VAR2, VAR5,
VAR6
);
output VAR10; output VAR11; output VAR7; output VAR4;
input VAR6; input VAR5; input VAR2; input VAR9; input VAR1; input VAR14; input VAR13; input VAR12;
VAR3 VAR8 (
.VAR11 (VAR11),
.VAR10 (VAR10),
.VAR7 (VAR7),
.VAR4 (VAR4),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.functional.v | 1,222 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR1;
notif0 VAR2 (VAR4 , VAR3, VAR1 );
endmodule | apache-2.0 |
olajep/oh | src/spi/hdl/spi_slave_io.v | 6,297 | module MODULE1 #( parameter VAR43 = 104 )
(
input VAR5, input VAR32, input VAR4, output VAR54, input VAR40, input VAR28, input VAR52, input VAR27, output VAR25, output VAR8, output [5:0] VAR7, output [7:0] VAR14, input [7:0] VAR26, input clk, input VAR15, output VAR29, output [VAR43-1:0] VAR6, input VAR41 );
reg VAR48;... | mit |
theapi/de0-nano | pong/game_engine.v | 5,592 | module MODULE1 (
VAR7,
VAR4,
VAR19,
VAR21,
VAR6,
VAR23,
VAR10,
VAR5,
VAR2,
VAR27
);
input VAR7;
input VAR4;
input VAR19;
input [7:0] VAR21;
input [7:0] VAR6;
input [10:0] VAR23;
input [10:0] VAR10;
output [10:0] VAR5;
output [10:0] VAR2;
output [2:0] VAR27;
reg [2:0] VAR31;
reg [10:0] VAR25;
reg [10:0] VAR26;
reg [10:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.functional.v | 1,475 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR6 ,
VAR2
);
output VAR9 ;
input VAR1 ;
input VAR6 ;
input VAR2;
wire VAR8 ;
wire VAR4;
nor VAR7 (VAR8 , VAR1, VAR6 );
nor VAR5 (VAR4, VAR2, VAR8 );
buf VAR3 (VAR9 , VAR4 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_timer.v | 4,405 | module MODULE1 (
VAR9, VAR3,
VAR25, VAR15, VAR5, clk, VAR22
);
input VAR25; input VAR15; output VAR9; output VAR3;
input VAR5; input clk; input VAR22;
wire [1:0] state;
reg VAR9, VAR3;
reg [1:0] VAR30;
parameter VAR14 = 2'b00;
parameter VAR16 = 2'b01;
parameter VAR11 = 2'b10;
parameter VAR7 = 2'b11;
parameter VAR4 = 2'... | gpl-2.0 |
aabdelfattah/alhaitham-hardware | alt_div_bb.v | 3,481 | module MODULE1 (
VAR2,
VAR3,
VAR4,
VAR1);
input [31:0] VAR2;
input [31:0] VAR3;
output [31:0] VAR4;
output [31:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_lp.v | 2,443 | module MODULE2 (
VAR7 ,
VAR4 ,
VAR1 ,
VAR8 ,
VAR11 ,
VAR5 ,
VAR9,
VAR12,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR8 ;
input VAR11 ;
input VAR5 ;
input VAR9;
input VAR12;
input VAR6 ;
input VAR2 ;
VAR3 VAR10 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR9(VA... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/altera_avalon_st_packets_to_bytes.v | 9,392 | module MODULE1
parameter VAR3 = 0)
(
input clk,
input VAR27,
output reg VAR23,
input VAR1,
input [7: 0] VAR22,
input [VAR26-1: 0] VAR19,
input VAR12,
input VAR29,
input VAR8,
output reg VAR6,
output reg [7: 0] VAR11
);
localparam VAR25 = (VAR26-1)/7;
localparam VAR18 = VAR26-1;
reg VAR13, VAR2, VAR10;
reg VAR16, VAR17,... | gpl-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_spram_256x32.v | 9,626 | module MODULE1(
clk, rst, VAR21, VAR47, VAR34, addr, VAR26, do
,
VAR50, VAR52, VAR24 VAR18
);
input clk; input rst; input VAR21; input [3:0] VAR47; input VAR34; input [7:0] addr; input [31:0] VAR26; output [31:0] do;
input VAR50; output VAR52; input [VAR41 - 1:0] VAR24; VAR18
VAR15 VAR42
(
.VAR23 (do[7:0]),
.VAR30 ({1'... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxtp/sky130_fd_sc_ms__sedfxtp.blackbox.v | 1,399 | module MODULE1 (
VAR4 ,
VAR9,
VAR8 ,
VAR3 ,
VAR6,
VAR7
);
output VAR4 ;
input VAR9;
input VAR8 ;
input VAR3 ;
input VAR6;
input VAR7;
supply1 VAR2;
supply0 VAR10;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
freecores/zet86 | impl/virtex4-ml403ep/mem/flash_cntrl.v | 1,969 | module MODULE1 (
input VAR3,
input VAR16,
input [15:0] VAR4,
output [15:0] VAR8,
input [16:1] VAR11,
input VAR2,
input VAR9,
input VAR12,
input VAR17,
output reg VAR6,
output reg [20:0] VAR15,
input [15:0] VAR7,
output VAR14,
output reg VAR1
);
reg [11:0] VAR5;
wire VAR10;
wire VAR13;
assign VAR8 = VAR7;
assign VAR14 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.pp.symbol.v | 1,297 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR8 ,
input VAR9 ,
output VAR5 ,
input VAR4 ,
input VAR2,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
Nrpickle/ECE272 | Lab5_TekBotSM/clock_counter.v | 1,250 | module MODULE1(
input VAR3, input VAR2,
output reg VAR4
);
reg [20:0] VAR1;
always @ (posedge VAR3, negedge VAR2)
begin
VAR1 <= VAR1 + 1; if(!VAR2)
begin
VAR4 <= 0;
VAR1 <= 0; end
else
if(VAR1 >= 519999) begin VAR4 <= ~VAR4;
VAR1 <= 0; end
end
endmodule | mit |
jameshegarty/rigel | platform/camera/vsrc/SCCBCtrl.v | 8,327 | module MODULE1 (VAR5, VAR16, VAR14, VAR1, VAR2, VAR6, VAR4, VAR7, VAR9, VAR11,
VAR8, VAR20, VAR18, VAR17);
input VAR5; input VAR16; input VAR14; input VAR1; input [7:0] VAR2; input [15:0] VAR6; output reg [7:0] VAR4; input VAR7; input VAR9; output VAR11; output reg VAR8; output VAR20; inout VAR18;
output reg [6:0] VAR1... | mit |
HarmonInstruments/verilog | math/div_3e9.v | 1,726 | module MODULE1
(
input VAR6,
input [62:0] VAR5, input VAR1,
output reg [62:0] VAR8,
output reg [10:0] VAR3,
output reg VAR2 = 0);
reg [53:0] VAR4;
reg [6:0] state = 0;
wire [53:0] VAR7 = VAR4 - 54'h165A0BC0000000;
always @ (posedge VAR6)
begin
if(VAR1)
VAR3 <= VAR5[62:52] - (1023+31);
end
else if(state == 64)
VAR3 <= V... | gpl-3.0 |
combinatorylogic/soc | backends/c2/hw/blackice2/vgafifo.v | 14,745 | module MODULE1 (VAR50, VAR14, VAR11, VAR2, VAR38, VAR17, VAR49, VAR30, VAR37, VAR12);
parameter VAR45 = 7; parameter VAR4 = 16;
input VAR50; input VAR14; input VAR11; input VAR2; input VAR38; input [VAR4 -1:0] VAR17; input VAR49; output [VAR4 -1:0] VAR30;
output VAR37; reg VAR37;
output VAR12; reg VAR12;
reg VAR16, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregrbp/sky130_fd_sc_lp__sregrbp.pp.symbol.v | 1,412 | module MODULE1 (
input VAR4 ,
output VAR10 ,
output VAR2 ,
input VAR9,
input VAR6 ,
input VAR8 ,
input VAR5 ,
input VAR3 ,
input VAR7 ,
input VAR11 ,
input VAR1
);
endmodule | apache-2.0 |
efabless/openlane | designs/usb_cdc_core/src/usbf_device_core.v | 29,760 | module MODULE1
(
input VAR42
,input VAR115
,input [ 7:0] VAR10
,input VAR95
,input VAR164
,input VAR153
,input VAR161
,input [ 1:0] VAR133
,input VAR185
,input VAR92
,input VAR77
,input VAR128
,input VAR43
,input VAR171
,input VAR195
,input VAR154
,input [ 7:0] VAR146
,input VAR122
,input VAR48
,input VAR26
,input VAR1... | apache-2.0 |
alexforencich/verilog-ethernet | example/ZCU102/fpga/rtl/fpga.v | 12,950 | module MODULE1 (
input wire VAR214,
input wire VAR165,
input wire reset,
input wire VAR124,
input wire VAR84,
input wire VAR25,
input wire VAR101,
input wire VAR228,
input wire [7:0] VAR37,
output wire [7:0] VAR204,
input wire VAR210,
output wire VAR152,
input wire VAR57,
output wire VAR234,
input wire VAR212,
input wi... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.functional.v | 1,360 | module MODULE1( VAR11, VAR7, VAR8, VAR2 );
input VAR11, VAR7, VAR2;
output VAR8;
wire VAR14;
not VAR5( VAR14, VAR11 );
wire VAR1;
not VAR3( VAR1, VAR2 );
wire VAR4;
and VAR15( VAR4, VAR14, VAR1 );
wire VAR13;
not VAR6( VAR13, VAR7 );
wire VAR10;
and VAR9( VAR10, VAR13, VAR1 );
or VAR12( VAR8, VAR4, VAR10 );
endmodule | apache-2.0 |
horia141/bachelor-thesis | prj/sequencers/Seq/Seq.v | 9,915 | module MODULE1(VAR21,reset,VAR28,VAR20,VAR25,VAR36,VAR7,VAR26,VAR35,VAR2,VAR6,VAR18);
input wire VAR21;
input wire reset;
input wire [19:0] VAR28;
input wire [4095:0] VAR20;
input wire VAR25;
input wire [7:0] VAR36;
input wire [7:0] VAR7;
input wire [7:0] VAR26;
input wire [7:0] VAR35;
output wire [7:0] VAR2;
output wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3_2.v | 2,057 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR3,
VAR4
);
output VAR7 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR4;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7,
VAR8,
VAR6,
VAR5
);
output VAR7;
input VAR8;
input VAR6;
in... | apache-2.0 |
AbhishekShah212/School_Projects | ELEN232/pset4/Problem3.v | 3,547 | module MODULE1(
input [7:0] VAR6,
input [1:0] VAR2,
input VAR1,
input VAR3,
input VAR5,
output reg [7:0] VAR4
);
always @ (VAR6, VAR2, VAR1, VAR3, VAR5)
begin
if (VAR2 == 2'b00) VAR4 = VAR6;
end
else if (VAR2 == 2'b01) begin
if ( VAR5 == 1)
begin
if (VAR3 == 1)
begin
VAR4 = {VAR6[0], VAR6[7:1]};
end
else
begin
VAR4 = {... | mit |
bunnie/novena-gpbb-fpga | novena-gpbb.srcs/sources_1/imports/imports/novena_fpga.v | 22,566 | module MODULE1(
input wire VAR93,
input wire [1:0] VAR84,
input wire [18:16] VAR60,
input wire VAR227,
input wire VAR200,
input wire VAR45,
inout wire [15:0] VAR25,
output wire VAR9,
output wire VAR189,
output wire VAR203,
output wire VAR99,
output wire VAR178,
output wire VAR12,
output wire VAR63,
output wire VAR135,
... | apache-2.0 |
peteg944/music-fpga | Enlightened Main Project/MicrophoneTop.v | 1,260 | module MODULE1(
output VAR8,
output VAR7,
output VAR11,
input VAR4,
input clk,
input rst,
output [9:0] VAR3
);
localparam VAR1 = 16'h1388; localparam VAR6 = 16'h09C4; reg [12:0] counter;
reg VAR9;
wire [9:0] VAR2;
VAR5 VAR10(VAR8, VAR7, VAR11, VAR4, clk, rst, VAR9, , VAR3);
always @ (posedge clk) begin
if(rst) begin
co... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/nfc-substrate/bch_shared_kes-1.0.0/d_KES_PE_ELU_eMAXodr.v | 5,165 | module MODULE1 (
input wire VAR19,
input wire VAR4,
input wire VAR10,
input wire VAR8,
input wire [VAR23-1:0] VAR11,
input wire [VAR23-1:0] VAR3,
input wire [VAR23-1:0] VAR25,
output reg VAR18
);
parameter [11:0] VAR5 = 12'b000000000000;
parameter [11:0] VAR7 = 12'b000000000001;
parameter VAR20 = 2'b01; parameter VAR2 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp/sky130_fd_sc_lp__sdfrtp.pp.blackbox.v | 1,474 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR2 ,
VAR8,
VAR10 ,
VAR5 ,
VAR6 ,
VAR9
);
output VAR4 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR2 ;
input VAR8;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR9 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_csr_ctl.v | 39,915 | module MODULE1(
VAR150, VAR165,
VAR149, VAR161,
VAR134, VAR29,
VAR23, VAR57,
VAR156, VAR97, VAR115,
VAR75, VAR89, VAR21,
VAR50, VAR118, VAR114,
VAR120, VAR41, VAR159, VAR99,
VAR87, VAR79, VAR53,
VAR108, VAR144, VAR62, VAR92,
VAR36, VAR146, VAR51, VAR167,
VAR164, VAR33, VAR69, VAR96,
VAR78, VAR1, VAR25, VAR10,
VAR63, VA... | gpl-2.0 |
hakehuang/pycpld | ips/ip/uart7bit/uart_tx7to7.v | 2,509 | module MODULE1(
clk,
VAR10,
VAR1,
VAR16,
VAR13,
VAR4,
VAR8
);
input clk;
input VAR10;
input [2:0] VAR1;
input [6:0] VAR16;
input VAR13;
output VAR4;
output VAR8;
parameter VAR5 = 13'd5208, VAR9 = 13'd2603, VAR3 = 13'd1301, VAR14 = 13'd867, VAR12 = 13'd434, VAR7 = 13'd195;
reg [12:0] VAR2;
reg VAR11;
reg [3:0] VAR15;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.symbol.v | 1,432 | module MODULE1 (
input VAR3,
input VAR5,
input VAR2,
input VAR7,
input VAR9,
output VAR1
);
supply1 VAR10;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba_2.v | 2,316 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5 ,
VAR8,
VAR10,
VAR9,
VAR7 ,
VAR6
);
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR8;
input VAR10;
input VAR9;
input VAR7 ;
input VAR6 ;
VAR2 VAR3 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp_1.v | 2,316 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR4 ,
VAR10 ,
VAR3 ,
VAR7 ,
VAR5,
VAR1
);
input VAR8 ;
input VAR2 ;
output VAR4 ;
output VAR10 ;
input VAR3 ;
input VAR7 ;
input VAR5;
input VAR1;
VAR9 VAR6 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/dbg_interface/dbg_top.v | 50,076 | module MODULE1(
VAR86, VAR213, VAR204, VAR155, VAR138, VAR223,
VAR73, VAR222, VAR60, VAR39, VAR7, VAR96,
VAR41, VAR89, VAR100, VAR152, VAR137,
VAR26, VAR166, VAR129, VAR135, VAR158, VAR63,
VAR114, VAR171,
VAR53, VAR104, VAR134, VAR115, VAR197, VAR157,
VAR23, VAR170, VAR101, VAR83
);
parameter VAR200 = 1;
input VAR86; i... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/readUSBWireData.v | 10,680 | module MODULE1 (VAR36, VAR10, VAR2, VAR17, VAR21, VAR34, VAR37, clk, rst, VAR32, VAR23, VAR26);
input [1:0] VAR36;
output VAR10;
input VAR17;
input clk;
input VAR34;
input rst;
input VAR37;
output [1:0] VAR2;
output VAR21;
output VAR32;
output VAR23;
input VAR26;
wire [1:0] VAR36;
reg VAR10;
wire VAR17;
wire clk;
wire ... | gpl-3.0 |
titorgalaxy/lzw | hw/src/LeftShift.v | 1,659 | module MODULE1(
VAR7,
VAR3,
VAR4
);
parameter VAR6=0;
localparam VAR5=(1<<VAR6);
output reg [VAR5-1:0] VAR7; input [VAR5-1:0] VAR3; input [VAR6-1:0] VAR4;
reg [VAR5-1:0] VAR1 [VAR6+1-1:0];
always @ begin
if(VAR4[VAR2]) begin
VAR1[VAR2] <= VAR1[VAR2+1][VAR5-1-(1<<VAR2):0] << (1<<VAR2);
end
else begin
VAR1[VAR2] <= VAR1[... | gpl-3.0 |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/ewrapper_io_rx_slow.v | 7,753 | module MODULE1 (
VAR56, VAR10,
VAR52, VAR14, VAR17, VAR24, VAR2,
VAR22, VAR20
);
input VAR52; input VAR14;
input VAR17;
input VAR24;
input [8:0] VAR2;
input [8:0] VAR22;
input VAR20;
output VAR56; output [71:0] VAR10;
reg [3:0] VAR46;
reg VAR33;
reg [8:0] VAR3;
reg [8:0] VAR15;
reg [8:0] VAR16;
reg [8:0] VAR50;
reg [8:... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp.pp.blackbox.v | 1,474 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR9 ,
VAR2 ,
VAR7 ,
VAR10,
VAR5 ,
VAR3 ,
VAR6 ,
VAR1
);
output VAR8 ;
input VAR4 ;
input VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR10;
input VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilogOrig/Top.v | 67,276 | module MODULE9(
input VAR284,
output VAR42,
input VAR285);
wire VAR286;
assign VAR42 = VAR286;
assign VAR286 = VAR284 ? 1'h0 : 1'h1;
endmodule
module MODULE11(
input VAR284,
output VAR42,
input VAR285);
wire VAR286;
assign VAR42 = VAR286;
assign VAR286 = VAR284 ? 1'h0 : 1'h1;
endmodule
module MODULE19(
input VAR284,
ou... | bsd-3-clause |
rohit21122012/CPU | ALU/Logic/OR/OR_32bit.v | 1,052 | module MODULE1(out , VAR9 ,VAR15);
output [31:0] out;
input [31:0] VAR9,VAR15;
or VAR13(out[0],VAR9[0],VAR15[0]);
or VAR30(out[1],VAR9[1],VAR15[1]);
or VAR2(out[2],VAR9[2],VAR15[2]);
or VAR16(out[3],VAR9[3],VAR15[3]);
or VAR25(out[4],VAR9[4],VAR15[4]);
or VAR28(out[5],VAR9[5],VAR15[5]);
or VAR19(out[6],VAR9[6],VAR15[6]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2.behavioral.pp.v | 1,792 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR5 ,
VAR13,
VAR8,
VAR10 ,
VAR1
);
output VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR13;
input VAR8;
input VAR10 ;
input VAR1 ;
wire VAR11 ;
wire VAR3;
nand VAR7 (VAR11 , VAR5, VAR9 );
VAR4 VAR2 (VAR3, VAR11, VAR13, VAR8);
buf VAR12 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.pp.blackbox.v | 1,367 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR2 ,
VAR3,
VAR5 ,
VAR6 ,
VAR8 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR3;
input VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/example_design/PIO_64_TX_ENGINE.v | 9,678 | module MODULE1 #(
parameter VAR17 = 64,
parameter VAR32 = 1,
parameter VAR9 = VAR17 / 8
)(
input clk,
input VAR25,
input VAR5,
output reg [VAR17-1:0] VAR11,
output reg [VAR9-1:0] VAR6,
output reg VAR2,
output reg VAR33,
output VAR37,
input VAR31,
input VAR30,
output reg VAR40,
input [2:0] VAR23,
input VAR27,
input VAR3... | lgpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/DSP48E_1.v | 1,935 | module MODULE1(
input signed [20:0] VAR3,
input signed [14:0] VAR6,
input VAR8,
input clk,
input VAR12,
output reg [12:0] VAR15,
input VAR5
);
reg [7:0] VAR2;
reg signed [47:0] VAR11, VAR9,VAR7,VAR10;
reg signed [47:0] VAR16 =48'b0;
reg signed [47:0] VAR1 =48'b0;
reg signed [47:0] VAR14 =48'b0;
reg signed [12:0] VAR13;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3.blackbox.v | 1,254 | module MODULE1 (
VAR6,
VAR3,
VAR7,
VAR5
);
output VAR6;
input VAR3;
input VAR7;
input VAR5;
supply1 VAR8;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
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