repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_swpla.v | 3,832 | module MODULE1(
out,
in
);
input [31:0] in;
output out;
wire [31:0] in;
reg out;
always @ (in)
begin
if (in[31:30] == 2'b01) out = 1'b1;
end
else if (in[31:30] == 2'b00) begin
if (in[24:22] == 3'b100) out = 1'b0;
end
else out = 1'b1;
end else if (in[31:30] == 2'b10) begin
if (in[24:23] == 2'b11) out = 1'b1;
end
else if... | gpl-2.0 |
fallen/milkymist-mmu | cores/softusb/rtl/softusb_tx.v | 5,397 | module MODULE1(
input VAR41,
input VAR28,
input [7:0] VAR31,
input VAR5,
output reg VAR25,
output reg VAR33,
output reg VAR39,
output reg VAR32,
input VAR15,
input VAR16
);
reg VAR11;
reg VAR35;
reg VAR13;
always @(posedge VAR41) begin
VAR33 <= VAR11;
VAR39 <= VAR35;
VAR32 <= VAR13;
end
reg VAR22;
reg [5:0] VAR8;
alway... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_2.behavioral.pp.v | 1,333 | module MODULE1( VAR2, VAR5, VAR9, VAR6, VAR1, VAR4 );
input VAR6, VAR9, VAR5;
inout VAR1, VAR4;
output VAR2;
VAR7 VAR8(.VAR2(VAR2),.VAR5(VAR5),.VAR9(VAR9),.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4));
VAR7 VAR3(.VAR2(VAR2),.VAR5(VAR5),.VAR9(VAR9),.VAR6(VAR6),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nrs/sky130_fd_sc_ls__udp_dff_nrs.symbol.v | 1,410 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR3,
input VAR5 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai.functional.v | 1,951 | module MODULE1 (
VAR13,
VAR7,
VAR4 ,
VAR1 ,
VAR5 ,
VAR8 ,
VAR9 ,
VAR15
);
input VAR13;
input VAR7;
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR9 ;
input VAR15 ;
wire VAR9 VAR12 ;
wire VAR3 ;
wire VAR16;
or VAR14 (VAR12 , VAR9, VAR8, VAR5, VAR1 );
nand VAR6 (VAR3 , VAR15, VAR12 );
VAR10 VAR11 (VAR16, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr.behavioral.pp.v | 1,940 | module MODULE1 (
VAR12 ,
VAR13 ,
VAR5 ,
VAR1 ,
VAR8,
VAR7 ,
VAR2
);
output VAR12 ;
input VAR13 ;
input VAR5 ;
input VAR1 ;
input VAR8;
input VAR7 ;
input VAR2 ;
wire VAR3 ;
wire VAR9;
buf VAR10 (VAR3 , VAR13 );
VAR11 VAR6 (VAR9, VAR3, VAR8, VAR1);
buf VAR4 (VAR12 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111ai/sky130_fd_sc_hs__o2111ai.blackbox.v | 1,366 | module MODULE1 (
VAR6 ,
VAR5,
VAR1,
VAR3,
VAR2,
VAR4
);
output VAR6 ;
input VAR5;
input VAR1;
input VAR3;
input VAR2;
input VAR4;
supply1 VAR8;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.symbol.v | 1,345 | module MODULE1 (
input VAR7,
input VAR2,
input VAR3,
output VAR8
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/source/rtl/Barrel_shifter.v | 1,561 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR4,
input wire [VAR14-1:0] VAR5,
input wire [VAR20-1:0] VAR19,
input wire VAR13,
input wire VAR1,
output wire [VAR20-1:0] VAR6
);
wire [VAR20-1:0] VAR17;
VAR2 #(.VAR20(VAR20),.VAR14(VAR14)) VAR2(
.clk(clk),
.rst(rst),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR19),
... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/01BLUETOOTH/Version_02/02 verilog/Prueba1/recepcion.v | 1,058 | module MODULE1(input VAR3,
output reg VAR1,
output reg [7:0] dout,
input wire VAR2); | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/NVMeHostController4L/src/pcie_hcmd_sq_fifo.v | 9,622 | module MODULE1 # (
parameter VAR63 = 19,
parameter VAR18 = 7
)
(
input VAR52,
input VAR35,
input VAR15,
input [VAR63-1:0] VAR69,
output VAR30,
input VAR5,
input VAR48,
input VAR14,
output [VAR63-1:0] VAR1,
output VAR67
);
localparam VAR53 = 0;
localparam VAR43 = 3'b001;
localparam VAR34 = 3'b010;
localparam VAR47 = 3'b... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4/sky130_fd_sc_hs__nor4_4.v | 2,148 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR3 ,
VAR1 ,
VAR8 ,
VAR7,
VAR6
);
output VAR5 ;
input VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR7;
input VAR6;
VAR2 VAR4 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5,
VAR9,
VAR3,
VAR1,
VAR8
);
... | apache-2.0 |
tommythorn/yari | shared/rtl/target/Fmax/main.v | 7,737 | module MODULE1(input wire VAR58,
input wire VAR22,
input wire VAR21,
output wire VAR13,
input wire VAR71,
input wire VAR38,
input wire VAR44,
input wire VAR33,
input wire VAR53,
input wire VAR35,
input wire VAR16,
input wire VAR30,
input wire VAR45,
inout wire [ 7:0] VAR27,
input wire [ 5:0] VAR43, input wire VAR75,
ou... | gpl-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_p_src_rows_V_2_loc_channel1.v | 3,047 | module MODULE1 (
clk,
VAR21,
VAR23,
VAR10,
VAR24);
parameter VAR18 = 32'd12;
parameter VAR9 = 32'd2;
parameter VAR22 = 32'd3;
input clk;
input [VAR18-1:0] VAR21;
input VAR23;
input [VAR9-1:0] VAR10;
output [VAR18-1:0] VAR24;
reg[VAR18-1:0] VAR3 [0:VAR22-1];
integer VAR19;
always @ (posedge clk)
begin
if (VAR23)
begin
f... | gpl-3.0 |
brysonli12/CS152A-Lab4-TicTacToe | Game/GameState.v | 5,083 | module MODULE1 (
input rst, input VAR6 , input clk,
input [3:0] VAR17, input VAR8,
input [8:0] VAR16,
input [8:0] VAR3,
output wire [8:0] VAR4,
output wire [8:0] VAR12,
output wire [2:0] VAR13,
output wire [7:0] VAR10
);
reg [8:0] VAR9;
reg [8:0] VAR2;
reg [8:0] VAR1;
reg [8:0] VAR15 = 9'b000000000;
reg [2:0] VAR14 = 0... | mit |
lbl-cal/StanfordNoC | router/src/clib/c_fbgen.v | 218,452 | module MODULE1
(VAR2);
parameter VAR3 = 32;
parameter VAR1 = 0;
output [0:VAR3-1] VAR2;
wire [0:VAR3-1] VAR2;
generate
if(VAR3 == 1)
begin
assign VAR2 = 1'h1;
end
else if(VAR3 == 2)
begin
assign VAR2 = 2'h3;
end
else if(VAR3 == 3)
begin
if((VAR1 % 2) == 0) assign VAR2 = 3'h5;
end
else if((VAR1 % 2) == 1) assign VAR2 = ... | bsd-2-clause |
bluespec/Flute | src_bsc_lib_RTL/BRAM1BELoad.v | 4,488 | module MODULE1(VAR9,
VAR3,
VAR1,
VAR10,
VAR6,
VAR2
);
parameter VAR17 = "";
parameter VAR16 = 0;
parameter VAR11 = 1;
parameter VAR4 = 1;
parameter VAR15 = 1;
parameter VAR13 = 1;
parameter VAR12 = 1;
parameter VAR14 = 0;
input VAR9;
input VAR3;
input [VAR13-1:0] VAR1;
input [VAR11-1:0] VAR10;
input [VAR4-1:0] VAR6;
ou... | apache-2.0 |
dawsonjon/fpu | double_to_float/file_writer.v | 1,166 | module MODULE1(VAR4,VAR2,clk,rst,VAR1);
integer VAR5;
integer VAR3;
input clk;
input rst;
input [31:0] VAR4;
input VAR2;
output VAR1;
reg VAR6;
reg state;
reg [31:0] VAR7;
begin
begin
begin
begin | mit |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_iq_block.v | 13,386 | module MODULE1 #(
parameter VAR62 = 1, parameter VAR16 = 5, parameter VAR6 = 50,
parameter VAR28 = 11, parameter VAR14 = 17, parameter VAR57 = 32,
parameter VAR66 = 14, parameter VAR42 = 24, parameter VAR7 = 18 , parameter VAR87 = 8 ,
parameter VAR64 = 2,
parameter VAR83 = 5,
parameter VAR47 = 10
)
(
input VAR43 , inpu... | mit |
MeshSr/onetswitch30 | ons30-app52-ref_ofshw/vivado/onets_7030_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/output_port_lookup.v | 21,016 | module MODULE1
parameter VAR57=VAR89/8,
parameter VAR40 = 8,
parameter VAR58 = 64,
parameter VAR19 = 16,
parameter VAR39 = 0,
parameter VAR64=2
)
( output [VAR89-1:0] VAR56,
output [VAR57-1:0] VAR108,
output VAR101,
input VAR82,
input [VAR89-1:0] VAR46,
input [VAR57-1:0] VAR63,
input VAR15,
output VAR103,
input [31:0] ... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.pp.symbol.v | 1,412 | module MODULE1 (
input VAR1 ,
output VAR6 ,
output VAR5 ,
input VAR11,
input VAR4 ,
input VAR7 ,
input VAR3 ,
input VAR2 ,
input VAR10 ,
input VAR8 ,
input VAR9
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/ccx2mb_v1_00_a/hdl/verilog/mb2cpx.v | 3,974 | module MODULE1 (
VAR4,
VAR1,
VAR18,
VAR3,
VAR11,
VAR7,
VAR8,
VAR5
);
parameter VAR10 = (((VAR14+1-1)/VAR13)+1);
parameter VAR17 = (VAR13 * VAR10) -
(VAR14+1);
output VAR4;
output [VAR14-1:0] VAR1;
output VAR18;
input VAR3;
input VAR11;
input VAR7;
input VAR8;
input [VAR13-1:0] VAR5;
wire VAR4;
wire [VAR14-1:0] VAR1;
wi... | gpl-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/alt_mem_ddrx_cmd_gen.v | 118,132 | module MODULE1
VAR325 = 33,
VAR2 = 3,
VAR71 = 8,
VAR346 = 4,
VAR324 = 4,
VAR152 = 5,
VAR30 = 2,
VAR323 = 2,
VAR149 = 5,
VAR126 = 2,
VAR233 = 2, VAR153 = 8,
VAR102 = 1, VAR369 = 1, VAR275 = 3,
VAR124 = 13,
VAR196 = 10,
VAR116 = 10,
VAR267 = 1,
VAR298 = 1,
VAR70 = 0,
VAR370 = 4,
VAR165 = 4,
VAR229 = 8,
VAR28 = 12,
VAR175... | gpl-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_rx/CRC_chk.v | 6,212 | module MODULE1(
VAR4 ,
VAR5 ,
VAR8 ,
VAR9 ,
VAR1 ,
VAR12 ,
VAR11
);
input VAR4 ;
input VAR5 ;
input[7:0] VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR12 ;
output VAR11 ;
reg [31:0] VAR7;
wire[31:0] VAR2;
function[31:0] VAR2;
input[7:0] VAR3;
input[31:0] VAR10;
reg[31:0] VAR6;
begin
VAR6[0]=VAR10[24]^VAR10[30]^VAR3[1]^VAR3... | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/Final/Processor.v | 8,423 | module MODULE1 (
);
wire [31:0] VAR23, VAR45;
wire [1:0] VAR12;
reg [31:0] VAR37, VAR1, VAR55, VAR59;
input [31:0] VAR29;
wire [4:0] VAR44, VAR41, VAR39;
reg [6:0] VAR60;
reg [3:0] VAR46;
reg [1:0] VAR11, VAR33;
reg VAR51, VAR34, VAR43, VAR24, VAR8, VAR57;
parameter VAR22 = 7'b0000000;
parameter VAR9 = 7'b1000000;
para... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3b/sky130_fd_sc_ls__nand3b.pp.symbol.v | 1,313 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR7 ,
output VAR5 ,
input VAR3 ,
input VAR8,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/register_file.v | 1,423 | module MODULE1(clk, VAR22, VAR3, VAR35, VAR28, write, VAR14, VAR13, VAR24, in, reset);
output [15:0] VAR22, VAR3;
input [15:0] in, VAR24;
input [2:0] VAR35, VAR28, VAR14;
input write, clk, reset, VAR13;
wire [15:0] VAR12, VAR21, VAR36, VAR11, VAR7, VAR25, VAR29, VAR26;
wire [6:0] VAR15;
wire [7:0] VAR23;
VAR31 VAR10(VA... | gpl-2.0 |
jotego/jt51 | hdl/jt51_kon.v | 1,740 | module MODULE1(
input rst,
input clk,
input VAR6,
input [3:0] VAR9,
input [2:0] VAR10,
input [1:0] VAR13,
input [2:0] VAR2,
input VAR8,
input VAR15,
input VAR7,
output reg VAR12
);
reg din;
wire VAR11;
reg [3:0] VAR14;
always @(posedge clk) if (VAR6)
VAR12 <= (VAR15&&VAR7) || VAR11;
always @(*) begin
case( VAR13 )
2'd0... | gpl-3.0 |
ptracton/wb_dsp | rtl/wb_dsp_algorithm_sm.v | 8,567 | module MODULE1 (
VAR12, VAR48, VAR19, VAR28, VAR55,
VAR22, VAR21, VAR4,
VAR3, VAR29, VAR47, VAR9, VAR26,
VAR57, VAR37,
VAR40, VAR42, VAR50, VAR45
) ;
parameter VAR49 = 32;
parameter VAR31 = 32;
parameter VAR54 = 0;
input VAR3;
input VAR29;
output reg VAR12;
output reg [VAR31-1:0] VAR48;
output reg [3:0] VAR19;
output r... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.functional.v | 1,187 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
output VAR1;
pullup VAR4 (VAR3 );
pulldown VAR2 (VAR1 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/a79f7727e74fe6ae/zynq_design_1_axi_bram_ctrl_0_bram_0_stub.v | 1,733 | module MODULE1(VAR3, VAR7, VAR9, VAR11, VAR10, VAR1, VAR12, VAR2, VAR8, VAR6,
VAR13, VAR4, VAR14, VAR5)
;
input VAR3;
input VAR7;
input VAR9;
input [3:0]VAR11;
input [31:0]VAR10;
input [31:0]VAR1;
output [31:0]VAR12;
input VAR2;
input VAR8;
input VAR6;
input [3:0]VAR13;
input [31:0]VAR4;
input [31:0]VAR14;
output [31:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221ai/sky130_fd_sc_hs__o221ai.behavioral.pp.v | 2,113 | module MODULE1 (
VAR11,
VAR18,
VAR9 ,
VAR8 ,
VAR3 ,
VAR1 ,
VAR5 ,
VAR14
);
input VAR11;
input VAR18;
output VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR14 ;
wire VAR5 VAR7 ;
wire VAR5 VAR4 ;
wire VAR16 ;
wire VAR12;
or VAR13 (VAR7 , VAR5, VAR1 );
or VAR15 (VAR4 , VAR3, VAR8 );
nand VAR2 (VAR16 ,... | apache-2.0 |
unihd-cag/openhmc | rtl/hmc_controller/crc/crc_128_init.v | 25,763 | module MODULE1 (
input wire clk,
input wire VAR3,
input wire [127:0] VAR1,
output reg [31:0] VAR2
);
always @(posedge clk or negedge VAR3) else
always @(posedge clk) VAR4
begin
if (!VAR3) begin
VAR2 <= 32'h0;
end else
begin
VAR2[31] <= VAR1[2]^VAR1[5]^VAR1[10]^VAR1[12]^VAR1[13]^VAR1[14]^VAR1[16]^VAR1[17]^VAR1[20]^VAR1[... | lgpl-3.0 |
phanrahan/magmathon | notebooks/tutorial/coreir/Counter.v | 1,763 | module MODULE1 #(
parameter VAR26 = 1,
parameter VAR13 = 1,
parameter VAR18 = 1,
parameter VAR25 = 1
) (
input clk,
input VAR27,
input [VAR26-1:0] in,
output [VAR26-1:0] out
);
reg [VAR26-1:0] VAR11;
wire VAR9;
assign VAR9 = VAR13 ? VAR27 : ~VAR27;
wire VAR6;
assign VAR6 = VAR18 ? clk : ~clk;
always @(posedge VAR6, pos... | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b_downsizer.v | 11,689 | module MODULE1 #
(
parameter VAR21 = "none",
parameter integer VAR4 = 4,
parameter integer VAR32 = 0,
parameter integer VAR33 = 1
)
(
input wire VAR2,
input wire VAR38,
input wire VAR34,
input wire VAR13,
input wire [4-1:0] VAR29,
output wire VAR27,
output wire [VAR4-1:0] VAR37,
output wire [2-1:0] VAR39,
output wire [... | gpl-3.0 |
nyaxt/dmix | mixer.v | 5,217 | module MODULE1 #(
parameter VAR18 = 8, parameter VAR23 = 3,
parameter VAR61 = 2,
parameter VAR13 = 1,
parameter VAR22 = 32
)(
input wire clk, input wire rst,
input wire [(VAR18-1):0] VAR36,
output wire [(VAR18-1):0] VAR31, input wire [(VAR18-1):0] VAR49,
input wire [(VAR18*24-1):0] VAR48,
input wire [(VAR18*VAR22-1):0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2.pp.symbol.v | 1,417 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR5,
input VAR4 ,
input VAR7,
input VAR2,
input VAR6
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.functional.v | 1,142 | module MODULE1( VAR10, VAR3, VAR2 );
input VAR3, VAR10;
output VAR2;
wire VAR12;
not VAR9( VAR12, VAR10 );
wire VAR5;
and VAR1( VAR5, VAR12, VAR3 );
wire VAR4;
not VAR11( VAR4, VAR3 );
wire VAR7;
and VAR8( VAR7, VAR4, VAR10 );
or VAR6( VAR2, VAR5, VAR7 );
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/spiral_0.v | 1,463 | module MODULE1(
VAR1,
VAR2,
VAR4
);
input signed [19:0] VAR1;
output signed [19+7:0] VAR2;
output signed [19+7:0] VAR4;
wire signed [26:0] VAR7,
VAR10,
VAR5,
VAR8,
VAR11,
VAR3,
VAR9,
VAR6;
assign VAR7 = VAR1;
assign VAR10 = VAR7 << 3;
assign VAR5 = VAR7 + VAR10;
assign VAR8 = VAR7 << 6;
assign VAR11 = VAR7 + VAR8;
assi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_refgen_new/sky130_fd_io__top_refgen_new.pp.blackbox.v | 2,805 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR11 ,
VAR17 ,
VAR20 ,
VAR3 ,
VAR8 ,
VAR9 ,
VAR13 ,
VAR6,
VAR22 ,
VAR1 ,
VAR10 ,
VAR21 ,
VAR25 ,
VAR24 ,
VAR27 ,
VAR26 ,
VAR15 ,
VAR12 ,
VAR18 ,
VAR7 ,
VAR23 ,
VAR19 ,
VAR2 ,
VAR4 ,
VAR16
);
output VAR14 ;
output VAR5 ;
inout VAR11 ;
inout VAR17 ;
inout VAR20 ;
input VAR3 ;
input VAR8 ;... | apache-2.0 |
fzyz999/5-stage-MIPS | control/hazard.v | 2,285 | module MODULE1 (VAR55,VAR56,VAR17,VAR43,VAR24,VAR31);
input [31:0] VAR55,VAR56,VAR17;
input VAR43,VAR24;
output VAR31;
wire VAR29,VAR7,VAR26,VAR39,VAR27,VAR25,VAR32,VAR22,VAR34,VAR9,VAR10,VAR52;
wire VAR28,VAR47,VAR41,VAR14,VAR19,VAR49,VAR15,VAR5,VAR13,VAR8,VAR40,VAR23;
wire VAR12,VAR50,VAR20,VAR11,VAR44,VAR37,VAR51,VA... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbSlaveCyc2Wrap.v | 5,771 | module MODULE1(
VAR21,
VAR12,
VAR19,
VAR18,
VAR31,
VAR22,
VAR34,
VAR6,
irq,
VAR9,
VAR4,
VAR25,
VAR30,
VAR23,
VAR13,
VAR1,
VAR7
);
input VAR21;
input VAR12;
input [7:0] VAR19;
input [7:0] VAR18;
output [7:0] VAR31;
input VAR22;
input VAR34;
output VAR6;
output irq;
input VAR9;
inout VAR4 ;
inout VAR25 ;
output VAR30 ;
o... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_txstatem.v | 5,229 | module MODULE1 (VAR5, VAR3,
VAR28, VAR13, VAR36, VAR24, VAR33, VAR12,
VAR37, VAR25, VAR26, VAR8, VAR11,
VAR22, VAR9, VAR10, VAR6, VAR18,
VAR14, VAR21, VAR1, VAR32, VAR15,
VAR34, VAR30, VAR20, VAR35, VAR4,
VAR29
);
input VAR5;
input VAR3;
input VAR28;
input VAR13;
input VAR36;
input VAR24;
input VAR33;
input VAR12;
inpu... | gpl-3.0 |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_altpll_sys.v | 11,870 | module MODULE1
(
VAR9,
VAR7,
VAR10,
VAR6) ;
input VAR9;
input VAR7;
input [0:0] VAR10;
output [0:0] VAR6;
tri0 VAR9;
tri1 VAR7;
reg [0:0] VAR2;
reg [0:0] VAR8;
reg [0:0] VAR3;
wire VAR1;
wire VAR4;
wire VAR5; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp.behavioral.v | 2,340 | module MODULE1 (
VAR18 ,
VAR6,
VAR21 ,
VAR16,
VAR4
);
output VAR18 ;
input VAR6;
input VAR21 ;
input VAR16;
input VAR4;
supply1 VAR2;
supply0 VAR11;
supply1 VAR25 ;
supply0 VAR19 ;
wire VAR1 ;
wire VAR3 ;
reg VAR10 ;
wire VAR13 ;
wire VAR7;
wire VAR14;
wire VAR23;
wire VAR15 ;
wire VAR12 ;
wire VAR5 ;
wire VAR9 ;
VAR8 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3_1.v | 2,153 | module MODULE2 (
VAR5 ,
VAR9 ,
VAR8 ,
VAR10 ,
VAR2,
VAR1,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR8 ;
input VAR10 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR4 ;
VAR7 VAR3 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp_2.v | 2,084 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR6,
VAR2,
VAR1 ,
VAR3
);
output VAR4 ;
input VAR8 ;
input VAR6;
input VAR2;
input VAR1 ;
input VAR3 ;
VAR7 VAR5 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4,
VAR8
);
output VAR4;
input VAR8;
supply1 VAR6;
supply0 VAR2;... | apache-2.0 |
alr46664/lab4 | verilog_source/pipeline_ctrl.v | 2,977 | module MODULE1(
clk, VAR10, VAR18, VAR11,
VAR12, VAR2, VAR8, VAR5, VAR15, VAR9,
VAR3,
VAR20, VAR17,
VAR1, VAR16, VAR6, VAR21, VAR19, VAR7
);
input clk, VAR10;
input [VAR23-1:0] VAR18, VAR11;
input [VAR13-1:0] VAR12, VAR2, VAR8;
input VAR5;
input [VAR23-1:0] VAR15, VAR9, VAR3;
input signed [VAR4-1:0] VAR20, VAR17, VAR1,... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_phy_ocd_cntlr.v | 9,807 | module MODULE1 #
(parameter VAR44 = 100,
parameter VAR52 = 3,
parameter VAR9 = 8)
(
VAR35, VAR24, VAR40,
VAR12, VAR7, VAR25,
VAR37, VAR15, VAR38,
VAR27, VAR36, VAR26,
VAR46,
clk, rst, VAR51, VAR19,
VAR28, VAR45, VAR39,
VAR5, VAR34, VAR16
);
localparam VAR49 = 1;
input clk;
input rst;
output VAR35, VAR24;
reg VAR4, VAR1... | mit |
buhii/LGA-FHP2 | ltcppg.v | 5,328 | module MODULE1
(
input [63:0] VAR29,
input [63:0] VAR95,
input [63:0] VAR104,
input [63:0] VAR45,
input [63:0] VAR13,
input [63:0] VAR84,
input [63:0] VAR80,
input [63:0] VAR58,
input [63:0] VAR35,
output [63:0] VAR26
);
wire [7:0] VAR72;
wire [7:0] VAR18;
wire [7:0] VAR25;
wire [7:0] VAR50;
wire [7:0] VAR78;
wire [7:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.v | 2,441 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR11 ,
VAR10 ,
VAR1,
VAR2 ,
VAR4 ,
VAR7 ,
VAR3
);
output VAR8 ;
output VAR5 ;
input VAR11 ;
input VAR10 ;
input VAR1;
input VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
VAR6 VAR9 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7)... | apache-2.0 |
hanw/Open-Source-FPGA-Bitcoin-Miner | src/sha256_transform.v | 4,978 | module MODULE2 #(
parameter VAR35 = 6'd4
) (
input clk,
input VAR27,
input [5:0] VAR31,
input [255:0] VAR23,
input [511:0] VAR9,
output reg [255:0] VAR2
);
localparam VAR21 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'... | gpl-3.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/z80/zports.v | 21,299 | module MODULE1(
input wire VAR77, input wire VAR45, input wire VAR103,
input wire VAR59,
input wire VAR132,
input wire [ 7:0] din,
output reg [ 7:0] dout,
output wire VAR12,
input wire [15:0] VAR109,
input wire VAR4,
input wire VAR144,
input wire VAR137,
input wire VAR32,
input wire VAR123,
output reg VAR112, output re... | gpl-3.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_co_ord_delay_actual.v | 29,427 | module MODULE1 (
VAR179,
VAR45,
VAR260,
VAR146,
VAR133,
VAR304,
VAR240,
VAR125,
VAR193,
VAR163,
VAR212,
VAR48,
VAR171,
VAR154,
VAR301,
VAR50,
VAR267,
VAR185,
VAR104,
VAR300,
VAR127,
VAR178,
VAR3,
VAR217,
VAR224,
VAR78,
VAR117,
VAR278,
VAR276,
VAR313,
VAR141,
VAR186,
VAR130,
VAR129,
VAR42,
VAR192,
VAR162,
VAR29,
VAR239,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_pwrgood_pp_p/sky130_fd_sc_hvl__udp_pwrgood_pp_p.symbol.v | 1,289 | module MODULE1 (
input VAR2 ,
output VAR3,
input VAR1
);
endmodule | apache-2.0 |
justingallagher/fpga-trace | hls/triangle_intersect/tri_intersect/impl/ip/hdl/verilog/tri_intersect_fdiv_32ns_32ns_32_30.v | 1,934 | module MODULE1
VAR16 = 50,
VAR11 = 30,
VAR14 = 32,
VAR5 = 32,
VAR24 = 32
)(
input wire clk,
input wire reset,
input wire VAR25,
input wire [VAR14-1:0] VAR22,
input wire [VAR5-1:0] VAR4,
output wire [VAR24-1:0] dout
);
wire VAR2;
wire VAR23;
wire VAR6;
wire [31:0] VAR18;
wire VAR12;
wire [31:0] VAR3;
wire VAR21;
wire [3... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/33befe9f7af11a93/led_controller_design_led_controller_0_0_stub.v | 2,568 | module MODULE1(VAR10, VAR16, VAR15,
VAR12, VAR17, VAR7, VAR19, VAR14,
VAR9, VAR18, VAR2, VAR1, VAR6,
VAR22, VAR11, VAR21, VAR8, VAR3,
VAR13, VAR20, VAR5, VAR4)
;
output [7:0]VAR10;
input [3:0]VAR16;
input [2:0]VAR15;
input VAR12;
output VAR17;
input [31:0]VAR7;
input [3:0]VAR19;
input VAR14;
output VAR9;
output [1:0]VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22a/sky130_fd_sc_hdll__o22a.pp.symbol.v | 1,376 | module MODULE1 (
input VAR3 ,
input VAR8 ,
input VAR7 ,
input VAR9 ,
output VAR1 ,
input VAR6 ,
input VAR4,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
AmeerAbdelhadi/2D-Binary-Content-Addressable-Memory-BCAM | trcam.v | 8,135 | module MODULE1
localparam VAR35 = 16384 ; localparam VAR8 = 512 ; localparam VAR5 = VAR16(VAR8) ; localparam VAR12 = (VAR37<VAR5) ? VAR5 : VAR37; localparam VAR4 = (VAR35/(2**VAR12))<1 ? 1 : (VAR35/(2**VAR12)) ; localparam VAR10 = VAR17 / VAR4 ;
wire [VAR16(VAR17)-VAR16(VAR4)-1:0] VAR29 = VAR22[VAR16(VAR17)-1:VAR16(VAR... | bsd-3-clause |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/config_parser.v | 5,500 | module MODULE1 (
input rst,
input clk,
input VAR16,
output reg VAR5,
input [31:0] VAR15,
input VAR6,
output reg [9:0] VAR20,
output reg VAR8,
output reg [31:0] VAR3,
output reg [31:0] VAR18,
output reg [31:0] VAR22,
output reg [31:0] VAR1,
output reg [31:0] VAR12,
output reg [31:0] VAR13
);
localparam VAR25 = 4'h0;
loc... | mit |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_10_0_0/RAT_Mux4x1_10_0_0_stub.v | 1,344 | module MODULE1(VAR4, VAR6, VAR3, VAR5, VAR1, VAR2)
;
input [9:0]VAR4;
input [9:0]VAR6;
input [9:0]VAR3;
input [9:0]VAR5;
input [1:0]VAR1;
output [9:0]VAR2;
endmodule | mit |
liqimai/ZPC | PersonalComputer/NumIn.v | 2,021 | module MODULE3(
input clk,
input[7:0] VAR1,
output reg[31:0] VAR17
);
wire[7:0] VAR14;
MODULE2 MODULE9(clk,VAR1[0],VAR14[0]);
MODULE2 MODULE3(clk,VAR1[1],VAR14[1]);
MODULE2 MODULE6(clk,VAR1[2],VAR14[2]);
MODULE2 MODULE5(clk,VAR1[3],VAR14[3]);
MODULE2 MODULE8(clk,VAR1[4],VAR14[4]);
MODULE2 MODULE2(clk,VAR1[5],VAR14[5]);... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32a/sky130_fd_sc_hs__o32a_2.v | 2,301 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR9 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR2,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR2;
input VAR3;
VAR10 VAR8 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 ... | apache-2.0 |
efabless/openlane | designs/synth_ram/src/synth_ram.v | 1,211 | module MODULE1 #( parameter integer VAR1 = 64) (
input clk,
input VAR4,
input [3:0] VAR6,
input [21:0] addr,
input [31:0] VAR5,
output[31:0] VAR2
);
reg [31:0] VAR2;
reg [31:0] VAR3 [0:VAR1-1];
always @(posedge clk) begin
if (VAR4 == 1'b1) begin
VAR2 <= VAR3[addr];
if (VAR6[0]) VAR3[addr][ 7: 0] <= VAR5[ 7: 0];
if (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.behavioral.pp.v | 2,300 | module MODULE1 (
VAR20 ,
VAR21 ,
VAR3 ,
VAR23 ,
VAR16,
VAR2 ,
VAR11 ,
VAR13 ,
VAR9
);
output VAR20 ;
output VAR21 ;
input VAR3 ;
input VAR23 ;
input VAR16;
input VAR2 ;
input VAR11 ;
input VAR13 ;
input VAR9 ;
wire VAR19 ;
wire VAR22 ;
reg VAR5 ;
wire VAR6 ;
wire VAR15;
wire VAR12 ;
wire VAR18 ;
wire VAR8 ;
wire VAR17 ... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/ip_pid_controller/hdl/ip_pid_controller.v | 21,029 | module MODULE2 (
VAR203,
VAR164,
VAR178,
VAR168
);
input VAR203;
input VAR164;
input VAR178;
output VAR168;
wire VAR71;
wire VAR129;
wire [7:0] VAR5;
wire [7:0] VAR59;
wire VAR45;
wire VAR13;
wire VAR21;
wire VAR9;
wire VAR196;
wire VAR100;
wire VAR167;
wire VAR89;
assign VAR71 = VAR203;
assign VAR129 = VAR164;
assign ... | gpl-3.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/ex_stage.v | 4,555 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR8, input wire VAR18, input wire VAR2,
output wire [VAR13] VAR4,
input wire [VAR40] VAR29, input wire VAR11, input wire [VAR23] VAR33, input wire [VAR13] VAR7, input wire [VAR13] VAR28, input wire VAR37, input wire [VAR20] VAR39, input wire [VAR13] VAR26, ... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/BCHSharedKESforTiger4/src/SharedKESTop.v | 16,791 | module MODULE1
parameter VAR27 = 4,
parameter VAR66 = 2,
parameter VAR48 = 12,
parameter VAR101 = 9,
parameter VAR133 = 27,
parameter VAR30 = 15
)
(
VAR79 ,
VAR142 ,
VAR20 ,
VAR126 ,
VAR43 ,
VAR114 ,
VAR41 ,
VAR29 ,
VAR72 ,
VAR2 ,
VAR152 ,
VAR5 ,
VAR31 ,
VAR125 ,
VAR104 ,
VAR112 ,
VAR10 ,
VAR83 ,
VAR19 ,
VAR121 ,
VAR14... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/read_signal_breakout.v | 5,643 | module MODULE1 (
VAR6, VAR16,
VAR14,
VAR5,
VAR11,
VAR9,
VAR3,
VAR12,
VAR7,
VAR4, VAR2, VAR15, VAR8,
VAR13,
VAR17,
VAR1
);
parameter VAR10 = 256;
input [VAR10-1:0] VAR6;
output wire [255:0] VAR16;
output wire [63:0] VAR14;
output wire [31:0] VAR5;
output wire [7:0] VAR11;
output wire VAR9;
output wire VAR3;
output wire ... | gpl-3.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/single_cycle_cpu_display.v | 6,075 | module MODULE1(
input clk,
input VAR37,
input VAR21,
output VAR22,
output VAR20,
output VAR42,
output VAR25,
output VAR10,
inout[15:0] VAR1,
output VAR39,
inout VAR3,
inout VAR45,
output VAR47,
output VAR9
);
wire VAR46; reg VAR17;
reg VAR4;
always @(posedge clk)
begin
if (!VAR37)
begin
VAR17<= 1'b0;
end
else
begin
VAR... | mit |
lvd2/zxevo | fpga/sdload/trunk/slave/slavespi.v | 7,082 | module MODULE1(
input wire VAR18,
input wire VAR21,
input wire VAR2, output wire VAR15, input wire VAR25, input wire VAR3,
input wire [ 7:0] VAR22,
output wire [39:0] VAR13,
output wire VAR4,
output wire [ 7:0] VAR27,
output wire VAR12,
output wire VAR23,
output wire VAR29,
output wire VAR10,
input wire [ 7:0] VAR26,
i... | gpl-3.0 |
Mahalakshmi23/BASYS2-Board-programmer | basys2.v | 2,675 | module MODULE1(
input [3:0] VAR4,
input [3:0] VAR1,
input clk,
output [3:0] VAR9,
output [6:0] final,
output [3:0] VAR3
);
reg [17:0] counter;
reg [3:0] VAR12;
reg [3:0] VAR5 = 4'b1111;
reg [6:0] VAR8=7'b1111111;
reg [6:0] VAR10=7'b1111111;
reg [6:0] VAR7=7'b1111111;
reg [6:0] VAR11=7'b1111111;
reg [6:0] VAR6=7'b111111... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/submodules/spw_light_time_in.v | 2,169 | module MODULE1 (
address,
VAR9,
clk,
VAR1,
VAR4,
VAR7,
VAR5,
VAR3
)
;
output [ 5: 0] VAR5;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR1;
input VAR4;
input [ 31: 0] VAR7;
wire VAR8;
reg [ 5: 0] VAR6;
wire [ 5: 0] VAR5;
wire [ 5: 0] VAR2;
wire [ 31: 0] VAR3;
assign VAR8 = 1;
assign VAR2 ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai.functional.v | 1,447 | module MODULE1 (
VAR2 ,
VAR5,
VAR4,
VAR6,
VAR9
);
output VAR2 ;
input VAR5;
input VAR4;
input VAR6;
input VAR9;
wire VAR1 ;
wire VAR3;
or VAR10 (VAR1 , VAR4, VAR5, VAR6 );
nand VAR8 (VAR3, VAR9, VAR1 );
buf VAR7 (VAR2 , VAR3 );
endmodule | apache-2.0 |
gbraad/minimig-de1 | minimig-src/j68/j68.v | 94,934 | module MODULE8
(
input rst, input clk, output VAR366, output VAR274, input VAR184, output [1:0] VAR24, output [31:0] address, input [15:0] VAR345, output [15:0] VAR23, output [2:0] VAR297, input [2:0] VAR304, output [3:0] VAR209, output [3:0] VAR200, output [15:0] VAR82, output [15:0] VAR100, output [31:0] VAR89, outpu... | gpl-3.0 |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Exponential/LUT_SHIFT.v | 3,287 | module MODULE1 #(parameter VAR1 = 32, parameter VAR6 = 5) (
input wire VAR5,
input wire VAR4,
input wire [VAR6-1:0] VAR2,
output reg [VAR1-1:0] VAR3
);
always @(posedge VAR5)
if (VAR4)
case (VAR2)
5'b00000: VAR3 <= 32'b00111111011111110000000000000000; 5'b00001: VAR3 <= 32'b00111111011111100000000000000000; 5'b00010: V... | gpl-3.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/encoder_axi_modules/encoder_axi_s_v1_0_S00_AXI.v | 16,118 | module MODULE1 #
(
parameter integer VAR1 = 32,
parameter integer VAR39 = 5
)
(
output wire [VAR1-1:0] VAR49,
output wire [VAR1-1:0] VAR16,
output wire [VAR1-1:0] VAR53,
output wire VAR25,
input wire VAR32,
input wire VAR4,
input wire VAR43,
input wire [VAR39-1 : 0] VAR42,
input wire [2 : 0] VAR29,
input wire VAR3,
out... | gpl-3.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/openMSP430_fpga.v | 36,843 | module MODULE1 (
VAR407,
VAR203,
VAR44,
VAR162,
VAR194,
VAR133,
VAR218,
VAR395,
VAR163,
VAR182,
VAR73,
VAR24,
VAR325,
VAR70,
VAR128,
VAR316,
VAR256,
VAR430,
VAR245,
VAR74,
VAR408,
VAR72,
VAR118,
VAR397,
VAR251,
VAR422,
VAR237,
VAR168,
VAR121,
VAR201,
VAR346,
VAR313,
VAR312,
VAR401,
VAR348,
VAR185,
VAR106,
VAR79,
VAR404... | bsd-3-clause |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rxr_engine_classic.v | 46,425 | module MODULE2
parameter VAR125 = 128,
parameter VAR204=10
)
(
input VAR60,
input VAR124,
input [VAR125-1:0] VAR49,
input VAR142,
input VAR82,
input [VAR66-1:0] VAR95,
input VAR130,
input [VAR66-1:0] VAR160,
input [VAR14-1:0] VAR139,
output [VAR125-1:0] VAR154,
output VAR85,
output [(VAR125/32)-1:0] VAR131,
output VAR5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4.blackbox.v | 1,281 | module MODULE1 (
VAR7,
VAR3,
VAR8,
VAR5,
VAR6
);
output VAR7;
input VAR3;
input VAR8;
input VAR5;
input VAR6;
supply1 VAR9;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
bkboggy/MIPS | MEM.v | 1,504 | module MODULE1(
input clk,
input VAR9,
input VAR18,
input VAR8,
input VAR21,
input [31:0] VAR12,
input [1:0] VAR13,
input [31:0] VAR14,
input [4:0] VAR20,
output VAR11,
output [1:0] VAR22,
output [31:0] VAR10,
output [31:0] VAR15,
output [4:0] VAR7);
wire [31:0] VAR3;
VAR19 VAR2(.clk(clk), .VAR8(VAR8), .VAR21(VAR21),
.... | mit |
travisg/cpu | rtl/cpu/nopipeline/cpu.v | 9,241 | module MODULE1(
input clk,
input rst,
output VAR14,
output VAR81,
output reg [29:0] VAR30,
input [31:0] VAR28,
output [31:0] VAR4,
output [31:0] VAR42
);
assign VAR4 = (VAR81 && !VAR14) ? VAR43 : 32'VAR6;
assign VAR42 = VAR50;
reg [29:0] VAR50;
reg [29:0] VAR7;
reg [3:0] VAR63;
always @(VAR63 or VAR43 or VAR48 or VAR68... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p.behavioral.pp.v | 1,805 | module MODULE1 (
VAR6 ,
VAR12 ,
VAR11,
VAR2,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR12 ;
input VAR11;
input VAR2;
input VAR9 ;
input VAR8 ;
wire VAR1 ;
wire VAR7;
buf VAR5 (VAR1 , VAR12 );
VAR10 VAR3 (VAR7, VAR1, VAR11, VAR2);
buf VAR4 (VAR6 , VAR7 );
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_fmul.v | 2,798 | module MODULE1(VAR31, VAR19,
VAR14, VAR22, VAR12,
VAR5, VAR13, VAR3,
VAR17, VAR6, VAR10);
parameter VAR28 = 32;
parameter VAR7 = 6;
parameter VAR18 = 64;
input VAR31, VAR19;
input [VAR28-1:0] VAR14;
input [VAR28-1:0] VAR5;
input VAR22, VAR13;
output VAR12, VAR3;
output [VAR28-1:0] VAR17;
output VAR6;
input VAR10;
reg [... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_CURRENTSTATE.v | 1,913 | module MODULE1 (
address,
clk,
VAR4,
VAR6,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 2: 0] VAR4;
input VAR6;
wire VAR2;
wire [ 2: 0] VAR1;
wire [ 2: 0] VAR5;
reg [ 31: 0] VAR3;
assign VAR2 = 1;
assign VAR5 = {3 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | gpl-3.0 |
jotego/jt51 | hdl/filter/jt51_interpol.v | 3,666 | module MODULE1(
input clk, input rst,
input VAR16,
input signed [15:0] VAR14,
input signed [15:0] VAR31,
input signed [15:0] VAR24,
input signed [15:0] VAR10,
output signed [15:0] VAR19,
output signed [15:0] VAR2,
output VAR26
);
parameter VAR30 = 7'd111;
reg [15:0] VAR22, VAR4, VAR28, VAR7;
reg VAR29;
reg VAR6;
reg [2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp_2.v | 2,615 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR8 ,
VAR13 ,
VAR12 ,
VAR4 ,
VAR10,
VAR9 ,
VAR5 ,
VAR2 ,
VAR1
);
output VAR3 ;
output VAR7 ;
input VAR8 ;
input VAR13 ;
input VAR12 ;
input VAR4 ;
input VAR10;
input VAR9 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
VAR11 VAR6 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR13(VAR13),
.VAR12(VA... | apache-2.0 |
marqs85/ossc | rtl/ossc.v | 11,464 | module MODULE1 (
input VAR144,
input VAR135,
inout VAR56,
inout VAR86,
input [1:0] VAR84,
input [7:0] VAR171,
input [7:0] VAR38,
input [7:0] VAR16,
input VAR141,
input VAR129,
input VAR162,
input VAR69,
output VAR117,
output reg [7:0] VAR53,
output reg [7:0] VAR43,
output reg [7:0] VAR49,
output reg VAR87,
output reg V... | gpl-3.0 |
everskar2013/PentiumX | Hardware/Code/irq_controller.v | 6,136 | module MODULE1(
VAR21, VAR2,
VAR12,
VAR19,
VAR20, VAR16,
VAR3, VAR5,
VAR4, VAR11,
VAR27, VAR1,
VAR8, VAR10,
VAR7, VAR14,
VAR23, VAR18,
VAR6, VAR25,
VAR9, VAR24
);
input VAR21, VAR2;
output wire [VAR26 - 1: 0]
VAR12;
input wire VAR19;
input VAR16;
output VAR20;
input VAR3;
output VAR5;
input VAR4;
output VAR11;
input VA... | mit |
andykarpov/radio-86rk-wxeda | src/video/rk_video.v | 3,903 | module MODULE1(
input clk,
output VAR27,
output VAR2,
output VAR9,
output VAR45,
output VAR38,
output [4:0] VAR44,
output [5:0] VAR24,
output [4:0] VAR16,
input[3:0] VAR1,
input[6:0] VAR33,
input VAR28,
input VAR26,
input VAR50
);
reg[1:0] state;
reg[10:0] VAR31;
reg[10:0] VAR47;
reg[10:0] VAR10;
reg[1:0] VAR32;
reg[2:... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o41a/sky130_fd_sc_hd__o41a_2.v | 2,411 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR3 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR8,
VAR9,
VAR12 ,
VAR1
);
output VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR12 ;
input VAR1 ;
VAR6 VAR7 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_acv_ldc.v | 3,417 | module MODULE1
(
VAR17,
VAR25,
VAR24,
VAR39,
VAR10,
VAR14,
VAR2,
VAR8,
VAR41
);
parameter VAR20 = "";
parameter VAR5 = 0;
parameter VAR1 = "false";
parameter VAR33 = "false";
input VAR17;
input VAR25;
input VAR24;
input [VAR20-1:0] VAR39;
output VAR10;
output VAR14;
output VAR2;
output VAR8;
output VAR41;
wire VAR37;
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.pp.blackbox.v | 1,351 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR2 ,
VAR4,
VAR8,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.v | 2,174 | module MODULE2 (
VAR6,
VAR3 ,
VAR1 ,
VAR5 ,
VAR2
);
output VAR6;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
VAR4 VAR7 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6,
VAR3
);
output VAR6;
input VAR3 ;
supply1 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
VAR4 VAR7 (
.... | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_sysid_qsys_0.v | 1,412 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1411627075 : 0;
endmodule | mit |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/mux.v | 1,554 | module MODULE1(VAR3, VAR2, VAR5, VAR9, VAR6, VAR8, VAR4, VAR1, VAR7, out);
output reg [15:0] out;
input [15:0] VAR3, VAR2, VAR5, VAR9, VAR6, VAR8, VAR4, VAR1;
input [2:0] VAR7;
always@(VAR3 or VAR2 or VAR5 or VAR9 or VAR6 or VAR8 or VAR4 or VAR1 or VAR7) begin
case(VAR7)
0: out = VAR3;
1: out = VAR2;
2: out = VAR5;
3: ... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_SEQ_SRAM_TT_201020.v | 73,337 | module MODULE1 (VAR7, VAR26, VAR13, VAR15, VAR5);
output VAR7;
input VAR26, VAR13, VAR15, VAR5;
reg VAR3;
wire VAR18, VAR17, VAR6, VAR12;
wire VAR1, VAR10, VAR4;
not (VAR1, VAR18);
VAR21 (VAR4, VAR12, VAR1, VAR6, VAR17);
VAR20 (VAR10, VAR3, VAR12, VAR1, VAR6, VAR17, VAR4);
buf (VAR7, VAR10);
wire VAR23, VAR19, VAR28;
w... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o.behavioral.v | 1,567 | module MODULE1 (
VAR9 ,
VAR1,
VAR3,
VAR13,
VAR4,
VAR2
);
output VAR9 ;
input VAR1;
input VAR3;
input VAR13;
input VAR4;
input VAR2;
supply1 VAR14;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR7 ;
wire VAR11 ;
wire VAR10;
and VAR8 (VAR11 , VAR13, VAR1, VAR3 );
or VAR12 (VAR10, VAR11, VAR2, VAR4);
buf VAR15 (VAR9 , VAR10 );
e... | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_sb_fifo.v | 4,883 | module MODULE1(
VAR9, VAR13, VAR16, VAR15, VAR8, VAR12, VAR6, VAR17
);
parameter VAR3 = 68;
parameter VAR11 = VAR14;
parameter VAR7 = VAR4;
input VAR9; input VAR13; input [VAR3-1:0] VAR16; input VAR15; input VAR8; output [VAR3-1:0] VAR12; output VAR6; output VAR17;
reg [VAR3-1:0] VAR5 [VAR7-1:0];
reg [VAR3-1:0] VAR12;
... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_26.v | 18,571 | module MODULE3 (
clk,
reset,
VAR158,
VAR38,
VAR20,
VAR15,
VAR10
);
parameter VAR16 = 18;
parameter VAR8 = 26;
parameter VAR157 = 13;
localparam VAR53 = 27;
input clk;
input reset;
input VAR158;
input VAR38;
input [VAR16-1:0] VAR20; output VAR15;
output [VAR16-1:0] VAR10;
localparam VAR155 = 18; localparam VAR56 = 36; l... | mit |
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