repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
HarmonInstruments/hififo | hdl/xadc.v | 2,234 | module MODULE1
(
input VAR2,
input write,
input [63:0] din,
output reg [16:0] dout = 0
);
reg [1:0] state = 0;
reg [2:0] VAR22 = 0;
reg [23:0] VAR11;
reg VAR5 = 0;
wire [15:0] VAR10;
wire VAR14;
always @ (posedge VAR2)
begin
VAR22 <= VAR22 + 1'b1;
dout[16] <= state != 0;
state <= write ? 2'd1 :
(state == 1) && (VAR22 =... | gpl-3.0 |
hanyazou/vivado-ws | playpen/dvi2vga_nofilter/dvi2vga_nofilter.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v | 2,494 | module MODULE1
(VAR3,
VAR26,
VAR16,
VAR14,
VAR18,
VAR10,
VAR33,
VAR20,
VAR29,
VAR11,
reset,
VAR36,
VAR32,
VAR22,
VAR19,
VAR7);
input VAR3;
input VAR26;
input [2:0]VAR16;
input [2:0]VAR14;
input VAR18;
inout VAR10;
inout VAR33;
output [0:0]VAR20;
output [0:0]VAR29;
output [3:0]VAR11;
input reset;
output [4:0]VAR36;
outp... | mit |
cr88192/bgbtech_bjx1core | srvcore/MemTile2.v | 13,630 | module MODULE1(
VAR47,
reset,
VAR89,
VAR45,
VAR82,
VAR20,
VAR10,
VAR92,
VAR101,
VAR75,
VAR87,
VAR95,
VAR31,
VAR61,
VAR103,
VAR76,
VAR7
);
input VAR47; input reset;
input VAR89; input VAR45; input[2:0] VAR82;
input[63:0] VAR20;
input[63:0] VAR92;
output[63:0] VAR10;
input VAR101; input[47:0] VAR75;
output[63:0] VAR87;
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ebufn/sky130_fd_sc_ls__ebufn.symbol.v | 1,333 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR1
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/bv-288/search_engine.v | 8,269 | module MODULE1(
clk,
reset,
VAR3,
VAR4,
VAR38,
VAR32,
VAR21,
VAR37,
VAR33,
VAR14,
VAR23,
VAR27
);
input clk;
input reset;
input VAR3;
input [71:0] VAR4;
output wire VAR38;
output wire [35:0] VAR32;
input VAR21;
input VAR37;
input [31:0] VAR33;
input VAR14;
output reg VAR23;
output reg [31:0] VAR27;
reg VAR17[0:7];
reg ... | apache-2.0 |
kyzhai/NUNY | src/hardware/bach_new.v | 6,415 | module MODULE1 (
address,
VAR7,
VAR30);
input [11:0] address;
input VAR7;
output [11:0] VAR30;
tri1 VAR7;
wire [11:0] VAR13;
wire [11:0] VAR30 = VAR13[11:0];
VAR32 VAR26 (
.VAR40 (address),
.VAR52 (VAR7),
.VAR45 (VAR13),
.VAR19 (1'b0),
.VAR39 (1'b0),
.VAR44 (1'b1),
.VAR28 (1'b0),
.VAR16 (1'b0),
.VAR27 (1'b1),
.VAR51 (1... | gpl-2.0 |
devinacker/sd2snes | verilog/sd2sneslite/address.v | 1,668 | module MODULE1(
input VAR4,
input [23:0] VAR8, output [23:0] VAR5, output VAR1, output VAR6, output VAR7, input [23:0] VAR9,
input [23:0] VAR3
);
wire [23:0] VAR2;
assign VAR7 = ((!VAR8[22] & VAR8[15])
|(VAR8[22]));
assign VAR6 = (!VAR8[22]
& &VAR8[21:20]
& &VAR8[14:13]
& !VAR8[15]
);
assign VAR2 = (VAR6
? 24'hFF0000 +... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.behavioral.pp.v | 2,224 | module MODULE1 (
VAR1 ,
VAR13 ,
VAR7 ,
VAR5 ,
VAR6 ,
VAR19 ,
VAR4,
VAR20,
VAR14 ,
VAR18
);
output VAR1 ;
input VAR13 ;
input VAR7 ;
input VAR5 ;
input VAR6 ;
input VAR19 ;
input VAR4;
input VAR20;
input VAR14 ;
input VAR18 ;
wire VAR3 ;
wire VAR17 ;
wire VAR11 ;
wire VAR12;
and VAR10 (VAR3 , VAR5, VAR13, VAR7 );
and VA... | apache-2.0 |
plindstroem/oh | elink/hdl/erx_remap.v | 2,429 | module MODULE1 (
VAR2, VAR1,
clk, reset, VAR10, VAR16, VAR9,
VAR15, VAR17, VAR22
);
parameter VAR21 = 32;
parameter VAR14 = 32;
parameter VAR5 = 104;
parameter VAR7 = 12'h808;
input clk;
input reset;
input VAR10;
input [VAR5-1:0] VAR16;
input [1:0] VAR9; input [11:0] VAR15; input [11:0] VAR17; input [31:0] VAR22;
outpu... | gpl-3.0 |
zeruniverse/Multiple-cycle_CPU | ISE project/regfile.v | 1,201 | module MODULE1 (VAR11, VAR1, VAR3,VAR9, VAR5, clk, VAR2, VAR8, VAR7,VAR6,VAR10);
input clk,VAR5,VAR2; input [4:0] VAR11, VAR1, VAR9,VAR6; input [31:0] VAR3; output wire [31:0] VAR8, VAR7,VAR10; reg [31:0] MODULE1 [0:31];
reg [5:0] VAR4;
assign VAR8=MODULE1[VAR11];
assign VAR7=MODULE1[VAR1];
assign VAR10=MODULE1[VAR6];
... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | ImaDRAM.v | 9,634 | module MODULE1 (
VAR28,
VAR32,
VAR50,
VAR40,
VAR16,
VAR53,
VAR55);
input [7:0] VAR28;
input VAR32;
input VAR50;
input [13:0] VAR40;
input [13:0] VAR16;
input VAR53;
output [7:0] VAR55;
tri1 VAR53;
wire [7:0] VAR47;
wire [7:0] VAR55 = VAR47[7:0];
VAR5 VAR6 (
.VAR33 (VAR53),
.VAR54 (VAR32),
.VAR57 (VAR50),
.VAR36 (VAR16)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.pp.symbol.v | 1,335 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR7 ,
input VAR1 ,
output VAR5 ,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a_2.v | 2,317 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR6 ,
VAR10,
VAR7
);
output VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR6 ;
input VAR10;
input VAR7;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.symbol.v | 1,341 | module MODULE1 (
input VAR4 ,
input VAR5 ,
input VAR7,
output VAR6
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
dhesant/elec4320 | Lab3/cpu.v | 3,492 | module MODULE1(VAR59, reset, VAR10, in, VAR1, VAR63, VAR64, VAR43, VAR6, VAR25, out, VAR19, VAR35);
input VAR59,reset,VAR10,VAR35;
input [15:0] in;
output VAR19;
output [2:0] VAR1;
output [15:0] VAR64, VAR43, VAR25, out;
output [11:0] VAR63, VAR6;
wire [15:0] VAR45, VAR41, VAR55;
wire clk;
reg [11:0] VAR6;
reg VAR13, V... | mit |
zeruniverse/Multiple-cycle_CPU | ISE project/mccomp.v | 1,316 | module MODULE1 (
input wire VAR7,rst,clk,
input wire [1:0] VAR15,
input wire [4:0] VAR27,
output wire VAR3,
output wire [5:0] VAR10,
output wire [3:0] VAR21,
output wire [7:0] VAR28
);
wire VAR8,reset,VAR29,VAR26;
wire [31:0] VAR16,VAR25,alu,VAR1,VAR4,VAR2,VAR6,VAR13,VAR12;
wire [2:0] VAR17;
reg [15:0] VAR18,VAR5=0;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp.behavioral.v | 2,946 | module MODULE1 (
VAR8 ,
VAR14 ,
VAR6 ,
VAR29 ,
VAR17 ,
VAR27 ,
VAR22
);
output VAR8 ;
output VAR14 ;
input VAR6 ;
input VAR29 ;
input VAR17 ;
input VAR27 ;
input VAR22;
supply1 VAR19;
supply0 VAR28;
supply1 VAR15 ;
supply0 VAR18 ;
wire VAR30 ;
wire VAR20 ;
wire VAR24 ;
reg VAR1 ;
wire VAR12 ;
wire VAR26 ;
wire VAR13 ;
... | apache-2.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/RegisterFile.v | 5,260 | module MODULE1(
input[31:0] VAR5,
output reg[31:0] VAR18,
output reg[31:0] VAR6,
input[4:0] VAR38, input[4:0] VAR24,
input VAR34, input clk, input sel );
reg [31:0] VAR9;
reg [31:0] VAR11;
reg [31:0] VAR8;
reg [31:0] VAR35;
reg [31:0] VAR27;
reg [31:0] VAR26;
reg [31:0] VAR3;
reg [31:0] VAR32;
reg [31:0] VAR10;
reg [31... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ecc/ecc_merge_enc.v | 5,627 | module MODULE1
parameter VAR10 = 100,
parameter VAR20 = 64,
parameter VAR23 = 72,
parameter VAR22 = 4,
parameter VAR19 = 1,
parameter VAR26 = 64,
parameter VAR18 = 72,
parameter VAR14 = 8
)
(
VAR17, VAR13,
clk, rst, VAR9, VAR25, VAR12, VAR7, VAR3
);
input clk;
input rst;
input [4*VAR20-1:0] VAR9;
input [4*VAR26/8-1:0] ... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/example/VCU118/fpga_1g/rtl/fpga.v | 16,582 | module MODULE1 (
input wire VAR26,
input wire VAR210,
input wire reset,
input wire VAR123,
input wire VAR110,
input wire VAR132,
input wire VAR80,
input wire VAR84,
input wire [3:0] VAR52,
output wire [7:0] VAR212,
input wire VAR34,
input wire VAR146,
output wire VAR137,
output wire VAR122,
input wire VAR200,
input wir... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.pp.symbol.v | 1,575 | module MODULE1 (
input VAR10 ,
output VAR7 ,
output VAR3 ,
input VAR6,
input VAR1 ,
input VAR11 ,
input VAR2 ,
input VAR5 ,
input VAR9 ,
input VAR4 ,
input VAR8 ,
input VAR12
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/rtl/jbi.v | 54,320 | module MODULE1 (
VAR372, VAR254, VAR102, VAR221,
VAR145, VAR83, VAR111, VAR297,
VAR247, VAR338, VAR105, VAR9,
VAR16, VAR200, VAR224,
VAR97, VAR243, VAR53,
VAR114, VAR18, VAR311,
VAR19, VAR345, VAR31, VAR378,
VAR123, VAR293, VAR91,
VAR309, VAR248, VAR230, VAR121,
VAR104, VAR324, VAR225, VAR120,
VAR133, VAR96, VAR228,
VA... | gpl-2.0 |
asicguy/gplgpu | hdl/de_temp/ded_pix_cache.v | 36,630 | module MODULE1
(
input VAR175, input VAR234, input VAR122, input [27:0] VAR152, input [27:0] VAR238, input [27:0] VAR26, input [11:0] VAR101, input [11:0] VAR213, input [11:0] VAR35, input VAR163,
input [3:0] VAR200, input VAR16,
input VAR260, input VAR173, input VAR55, input [31:0] VAR33, input [31:0] VAR106, input VA... | gpl-3.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_blender.v | 8,061 | module MODULE1(VAR37, VAR30,
VAR13, VAR46, VAR44, VAR41, VAR21,
VAR10, VAR24, VAR40, VAR3, VAR39, VAR6, VAR18, VAR34, VAR4, VAR11, VAR15, VAR12, VAR26, VAR9, VAR19, VAR7, VAR8, VAR45, VAR38, VAR31 );
parameter VAR17 = 16;
input VAR37;
input VAR30;
input VAR13;
input [31:2] VAR46;
input [VAR17-1:0] VAR44;
input [VAR17-1... | gpl-3.0 |
ptracton/wb_soc_template | rtl/system_controller/system_controller_altera.v | 1,848 | module MODULE1 (
VAR7, VAR2, VAR1,
VAR11, VAR4
) ;
input wire VAR11;
input wire VAR4;
output wire VAR7;
output reg VAR2;
output wire VAR1;
wire VAR13;
VAR8 VAR9(
.VAR10(VAR4),
.VAR5(VAR11),
.VAR3(VAR7),
.VAR6(VAR13)
);
reg [3:0] VAR12;
assign VAR1 = ~VAR2;
always @(posedge VAR11)
if (VAR4 | ~VAR13) begin
VAR2 <= 1;
VAR... | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Karat/MUL_FPU_FUNCIONAL_v1/MUL_FPU_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Mult/FPU_Multiplication_Function.v | 8,367 | module MODULE1
input wire clk,
input wire rst,
input wire VAR115,
input wire VAR95,
input wire [VAR48-1:0] VAR99,
input wire [VAR48-1:0] VAR5,
input wire [1:0] VAR75,
output wire VAR53,
output wire VAR23,
output wire ready,
output wire [VAR48-1:0] VAR4
);
wire VAR87;
wire VAR109; wire VAR57;
wire VAR24; wire VAR93; wir... | gpl-3.0 |
sam-falvo/kestrel | cores/KCP53K/cpu2/bench/verilog/integration.v | 5,168 | module MODULE1();
reg [11:0] VAR1;
reg VAR74;
reg VAR50, VAR21, VAR9;
reg [31:0] VAR24;
wire VAR69;
wire [63:0] VAR22, VAR32;
wire [63:0] VAR105, VAR90;
wire VAR11, VAR95, VAR19, VAR107;
wire VAR14, VAR43, VAR65, VAR103;
wire VAR101, VAR17, VAR51, VAR108;
wire [4:0] VAR31, VAR36, VAR30;
wire [63:0] VAR110;
wire [2:0] V... | mpl-2.0 |
MForever78/CPUFly | ipcore_dir/dist_mem_gen_v7_2.v | 3,972 | module MODULE1(
VAR33,
VAR8
);
input [13 : 0] VAR33;
output [31 : 0] VAR8;
VAR37 #(
.VAR29(14),
.VAR21("0"),
.VAR2(16384),
.VAR36("VAR30"),
.VAR44(0),
.VAR32(0),
.VAR48(0),
.VAR38(0),
.VAR11(0),
.VAR35(0),
.VAR55(0),
.VAR25(0),
.VAR14(0),
.VAR15(0),
.VAR9(0),
.VAR50(0),
.VAR43(0),
.VAR51(0),
.VAR46(1),
.VAR39(0),
.VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.behavioral.v | 1,607 | module MODULE1 (
VAR2 ,
VAR1,
VAR11,
VAR12,
VAR16
);
output VAR2 ;
input VAR1;
input VAR11;
input VAR12;
input VAR16;
supply1 VAR4;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR5 ;
wire VAR13 ;
wire VAR10 ;
wire VAR14;
or VAR7 (VAR13 , VAR11, VAR1 );
or VAR15 (VAR10 , VAR16, VAR12 );
and VAR6 (VAR14, VAR13, VAR10);
buf VAR3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.v | 2,329 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR3 ,
VAR8,
VAR1 ,
VAR6 ,
VAR10 ,
VAR4
);
output VAR7 ;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR1 ;
input VAR6 ;
input VAR10 ;
input VAR4 ;
VAR2 VAR5 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4.behavioral.pp.v | 1,837 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR8 ,
VAR5 ,
VAR13 ,
VAR3,
VAR7,
VAR10 ,
VAR12
);
output VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR13 ;
input VAR3;
input VAR7;
input VAR10 ;
input VAR12 ;
wire VAR14 ;
wire VAR15;
and VAR6 (VAR14 , VAR4, VAR8, VAR5, VAR13 );
VAR11 VAR1 (VAR15, VAR14, VAR3, VAR7);
buf VAR9 (... | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/data_read.v | 86,570 | module MODULE1(VAR107,
VAR223,
VAR166,
VAR316,
VAR74,
VAR329,
VAR27,
VAR89,
VAR126,
VAR197,
VAR323,
VAR334,
VAR214,
VAR39,
VAR9,
VAR96,
VAR55,
VAR95,
VAR68,
VAR28,
VAR315,
VAR125,
VAR188,
VAR108,
VAR265,
VAR136,
VAR70,
VAR295,
VAR306,
VAR198,
VAR86,
VAR302,
VAR78,
VAR90,
VAR209,
VAR135,
VAR57,
VAR185,
VAR72,
VAR232,
VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21o/sky130_fd_sc_hs__a21o_4.v | 2,121 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR4 ,
VAR7 ,
VAR6,
VAR5
);
output VAR2 ;
input VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR5;
VAR1 VAR3 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2 ,
VAR8,
VAR4,
VAR7
);
output VAR2 ;
input VAR8;
input VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3.blackbox.v | 1,254 | module MODULE1 (
VAR4,
VAR2,
VAR1,
VAR5
);
output VAR4;
input VAR2;
input VAR1;
input VAR5;
supply1 VAR7;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Iuliiapl/schoolMIPS | src/sm_top.v | 1,890 | module MODULE2
(
input VAR17,
input VAR12,
input [ 3:0 ] VAR10,
input VAR25,
output clk,
input [ 4:0 ] VAR1,
output [31:0 ] VAR5
);
wire [ 3:0 ] VAR6;
wire enable;
wire [ 4:0 ] addr;
MODULE1 #(.VAR11(4)) VAR8(VAR17, VAR10, VAR6);
MODULE1 #(.VAR11(1)) VAR19(VAR17, VAR25, enable);
MODULE1 #(.VAR11(5)) VAR22(VAR17, VAR1, ... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/yacc/ram32x32_xilinx.v | 1,347 | module MODULE1 (
VAR18,
VAR4,
VAR3,
VAR5,
VAR10,
VAR20,
VAR16,
VAR6);
input [31:0] VAR18;
input [4:0] VAR4;
input [4:0] VAR3;
input [4:0] VAR5;
input VAR10;
input VAR20;
output [31:0] VAR16;
output [31:0] VAR6;
VAR13 VAR17( .VAR9(VAR4),
.VAR15(VAR3),
.VAR12(VAR20),
.VAR11(VAR20),
.VAR14(VAR18),
.VAR7(32'h00000000),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver/sky130_fd_sc_lp__busdriver.symbol.v | 1,348 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR2
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22a/sky130_fd_sc_hd__o22a.symbol.v | 1,363 | module MODULE1 (
input VAR1,
input VAR9,
input VAR8,
input VAR2,
output VAR3
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2b/sky130_fd_sc_hdll__and2b.pp.blackbox.v | 1,295 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR3 ,
VAR4,
VAR7,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR4;
input VAR7;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0_phy.v | 30,278 | module MODULE1 (
VAR49,
VAR40,
VAR53,
VAR47,
VAR80,
VAR75,
VAR17,
VAR59,
VAR84,
VAR74,
VAR11,
VAR65,
VAR95,
VAR22,
VAR87,
VAR4,
VAR31,
VAR92,
VAR32,
VAR73,
VAR85,
VAR7,
VAR24,
VAR6,
VAR60,
VAR30,
VAR39,
VAR55,
VAR8,
VAR12,
VAR96,
VAR26,
VAR77,
VAR19,
VAR71,
VAR37,
VAR2,
VAR68,
VAR76,
VAR54,
VAR70,
VAR14,
VAR10,
VAR16,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ba/sky130_fd_sc_ls__o21ba.symbol.v | 1,386 | module MODULE1 (
input VAR1 ,
input VAR3 ,
input VAR2,
output VAR5
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_dly_ctrl.v | 23,027 | module MODULE1 #
(
parameter VAR48 = 100, parameter VAR75 = 64, parameter VAR32 = 3, parameter VAR59 = 8, parameter VAR42 = 1, parameter VAR33 = 5, parameter VAR31 = "VAR36", parameter VAR61 = "VAR36", parameter VAR54 = "VAR81", parameter VAR11 = 4, parameter VAR30 = 4, parameter VAR10 = 0, parameter VAR88 = 0, paramet... | lgpl-3.0 |
ShepardSiegel/ocpi | rtl/mkBiasWorker4B.v | 57,925 | module MODULE1(VAR134,
VAR103,
VAR121,
VAR290,
VAR28,
VAR156,
VAR10,
VAR262,
VAR339,
VAR68,
VAR142,
VAR299,
VAR159,
VAR203,
VAR77,
VAR46,
VAR220,
VAR145,
VAR92,
VAR137,
VAR288,
VAR305,
VAR255,
VAR214,
VAR170,
VAR238,
VAR166,
VAR53,
VAR195,
VAR228,
VAR4,
VAR47);
parameter [0 : 0] VAR225 = 1'b0;
input VAR134;
input VAR10... | lgpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nvme/nvme_host_ctrl_8lane-1.0.0/pcie_hcmd_sq.v | 12,768 | module MODULE1 # (
parameter VAR163 = 128,
parameter VAR106 = 36
)
(
input VAR60,
input VAR134,
input [VAR106-1:2] VAR128,
input [7:0] VAR147,
input [7:0] VAR156,
input [7:0] VAR63,
input [7:0] VAR4,
input [7:0] VAR12,
input [7:0] VAR152,
input [7:0] VAR55,
input [7:0] VAR101,
input [7:0] VAR114,
input [7:0] VAR56,
out... | gpl-3.0 |
aquaxis/FPGAMAG18 | src/fmrv32im_max10.v | 9,351 | module MODULE1
parameter VAR44 = "../../VAR114/VAR73.VAR45"
)
(
input VAR1,
output [3:0] VAR87
);
wire VAR68;
assign VAR68 = VAR1;
wire VAR107;
assign VAR107 = 1'b1;
wire [31:0] VAR72;
assign VAR72 = 32'd0;
wire [15:0] VAR121;
wire [3:0] VAR135;
wire [2:0] VAR144;
wire VAR90;
wire VAR12;
wire [31:0] VAR52;
wire [3:0] V... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/mcm_16.v | 44,303 | module MODULE1(
clk,
rst,
VAR426,
VAR72,
VAR361,
VAR198,
VAR357,
VAR436,
VAR168,
VAR16,
VAR105,
VAR1,
VAR199,
VAR82,
VAR62,
VAR405,
VAR342,
VAR385,
VAR202,
VAR167,
VAR73,
VAR382,
VAR323,
VAR131,
VAR25,
VAR306,
VAR348,
VAR236,
VAR352,
VAR337,
VAR123,
VAR178,
VAR368,
VAR392,
VAR76
);
input clk;
input rst;
input VAR426;
i... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_p/sky130_fd_sc_hd__udp_dff_p.symbol.v | 1,252 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
Sponk/mips86 | platform/basys2/src/Display.v | 1,415 | module MODULE1
parameter VAR4 = 16)
(
input wire clk,
input wire [15:0] VAR8,
output reg [6:0] VAR6,
output wire [3:0] VAR7
);
reg [3:0] VAR2 = 4'b0111;
assign VAR7 = VAR2;
wire [3:0] VAR3[0:3];
assign VAR3[3] = VAR8[15:12];
assign VAR3[2] = VAR8[11:8];
assign VAR3[1] = VAR8[7:4];
assign VAR3[0] = VAR8[3:0];
reg [1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxtp/sky130_fd_sc_ls__edfxtp.behavioral.v | 2,153 | module MODULE1 (
VAR18 ,
VAR12,
VAR4 ,
VAR16
);
output VAR18 ;
input VAR12;
input VAR4 ;
input VAR16 ;
supply1 VAR13;
supply0 VAR8;
supply1 VAR11 ;
supply0 VAR20 ;
wire VAR9 ;
reg VAR3 ;
wire VAR15 ;
wire VAR6 ;
wire VAR21;
wire VAR2 ;
wire VAR19 ;
wire VAR5 ;
VAR7 VAR1 (VAR2, VAR9, VAR15, VAR6 );
VAR10 VAR14 (VAR9 , V... | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_load_store_unit.v | 13,807 | module MODULE1 (
input clk, input rst, input [31:0] VAR22, output reg [31:0] VAR1, input [31:0] VAR41, input [31:0] VAR12, input VAR27, input VAR21, input VAR40, input VAR32, input VAR11, output reg [31:0] VAR33, input [31:0] VAR10, input VAR39, input VAR6, output [31:0] VAR28, output [3:0] VAR5, output VAR18, input [3... | mit |
sh-chris110/chris | FPGA/Math/Qsys/custom_math.v | 1,957 | module MODULE1 (
input wire [7:0] VAR2, input wire VAR15, output wire [31:0] VAR4, input wire VAR14, input wire [31:0] VAR9, output wire VAR1, input wire VAR7, input wire VAR3, output wire VAR10, output wire [7:0] VAR8, output wire VAR11, input wire VAR6, input wire [31:0] VAR5, output wire VAR12, output wire [31:0] VA... | gpl-2.0 |
googleinterns/hw-fuzzing | third_party/aes_128/aes_128.v | 2,719 | module MODULE2(clk, state, VAR49, out);
input clk;
input [127:0] state, VAR49;
output [127:0] out;
reg [127:0] VAR43, VAR56;
wire [127:0] VAR53, VAR10, VAR38, VAR40, VAR59, VAR65, VAR1, VAR31, VAR11,
VAR63, VAR34, VAR37, VAR7, VAR39, VAR62, VAR8, VAR61, VAR18,
VAR29, VAR45, VAR54, VAR25, VAR3, VAR41, VAR36, VAR42, VAR2... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_NIOS_CPU_jtag_debug_module_wrapper.v | 10,470 | module MODULE1 (
VAR46,
VAR3,
clk,
VAR2,
VAR33,
VAR27,
VAR15,
VAR38,
VAR10,
VAR8,
VAR30,
VAR35,
VAR1,
VAR49,
VAR44,
VAR45,
VAR60,
VAR52,
VAR39,
VAR59,
VAR48,
VAR4,
VAR54,
VAR40,
VAR21,
VAR26,
VAR18,
VAR11,
VAR36,
VAR58,
VAR23,
VAR43,
VAR31,
VAR12,
VAR14,
VAR17
)
;
output [ 37: 0] VAR48;
output VAR4;
output VAR54;
outpu... | gpl-2.0 |
AmeerAbdelhadi/Multiported-RAM | mpram_reg.v | 5,037 | module MODULE1
localparam VAR16 = VAR9(VAR4); integer VAR3;
reg [VAR1-1:0] VAR17 [0:VAR4-1]; VAR7
if (VAR10)
for (VAR3=0; VAR3<VAR4; VAR3=VAR3+1) VAR17[VAR3] = {VAR1{1'b0}};
else
if (VAR12 != "")
always @(posedge clk) begin
for (VAR3=1; VAR3<=VAR13; VAR3=VAR3+1)
if (VAR15[VAR3-1])
end
if (VAR11) VAR17[VAR8[VAR3*VAR16-1... | bsd-3-clause |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/reset_extender.v | 3,511 | module MODULE1
(input VAR9,
input VAR11,
input VAR13,
output VAR16,
output VAR21);
localparam VAR5 = VAR6(VAR7);
localparam VAR8 = 1 << VAR5;
localparam VAR24 = 4;
wire [VAR5:0] VAR20;
wire [VAR24:0] VAR14;
assign VAR21 = VAR14 != 0;
assign VAR16 = VAR14[VAR24];
counter
.VAR12 (VAR8),
.VAR4 (VAR8 - VAR7)
)
VAR18
( .VAR... | gpl-3.0 |
marqs85/de2-vd | i2c_opencores/i2c_opencores.v | 1,972 | module MODULE1
(
VAR15, VAR2, VAR13, VAR6, VAR17,
VAR14, VAR11, VAR19, VAR16,
VAR10, VAR5
);
input VAR15; input VAR2;
input [2:0] VAR13; input [7:0] VAR6; output [7:0] VAR17; input VAR14; input VAR11; output VAR19; output VAR16;
inout VAR10; inout VAR5;
wire VAR3; wire VAR7;
wire VAR18;
wire VAR10;
wire VAR20;
assign V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai_lp.v | 2,337 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR6 ,
VAR8,
VAR3,
VAR7,
VAR1 ,
VAR10
);
output VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR3;
input VAR7;
input VAR1 ;
input VAR10 ;
VAR9 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.functional.v | 1,859 | module MODULE1 (
VAR1,
VAR5,
VAR8 ,
VAR13 ,
VAR2
);
input VAR1;
input VAR5;
output VAR8 ;
input VAR13 ;
input VAR2 ;
wire VAR8 VAR3 ;
wire VAR11 ;
wire VAR10;
not VAR7 (VAR3 , VAR13 );
and VAR6 (VAR11 , VAR3, VAR2 );
VAR4 VAR9 (VAR10, VAR11, VAR1, VAR5);
buf VAR12 (VAR8 , VAR10 );
endmodule | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/3-execution/alu.v | 1,620 | module MODULE1 #(parameter VAR5 = 32)
(
input wire signed [VAR5-1:0] VAR1,
input wire signed [VAR5-1:0] VAR4,
input wire [3:0] VAR3,
output wire [VAR5-1:0] VAR2,
output wire VAR6
);
assign VAR2 = (VAR3 == 4'b0000) ? VAR1 + VAR4 : (VAR3 == 4'b0001) ? VAR1 - VAR4 : (VAR3 == 4'b0010) ? VAR1 & VAR4 : (VAR3 == 4'b0011) ? VA... | gpl-3.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/start_for_CvtColowdI.v | 3,003 | module MODULE1 (
clk,
VAR17,
VAR7,
VAR14,
VAR8);
parameter VAR5 = 32'd1;
parameter VAR6 = 32'd2;
parameter VAR25 = 32'd3;
input clk;
input [VAR5-1:0] VAR17;
input VAR7;
input [VAR6-1:0] VAR14;
output [VAR5-1:0] VAR8;
reg[VAR5-1:0] VAR4 [0:VAR25-1];
integer VAR10;
always @ (posedge clk)
begin
if (VAR7)
begin
for (VAR10=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4/sky130_fd_sc_ls__and4_1.v | 2,242 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR11 ,
VAR7 ,
VAR10 ,
VAR5,
VAR2,
VAR4 ,
VAR9
);
output VAR3 ;
input VAR6 ;
input VAR11 ;
input VAR7 ;
input VAR10 ;
input VAR5;
input VAR2;
input VAR4 ;
input VAR9 ;
VAR8 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.... | apache-2.0 |
cpulabs/mist1032sa | src/core/l1_instruction/l1_instruction_cache.v | 11,652 | module MODULE1(
input wire VAR75,
input wire VAR30,
input wire VAR6,
input wire VAR60,
output wire VAR5,
input wire VAR52,
output wire [1:0] VAR17,
output wire [31:0] VAR69,
input wire VAR1,
output wire VAR53,
input wire VAR51,
input wire [63:0] VAR68,
input wire [27:0] VAR26,
input wire VAR71,
output wire VAR36,
input... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o_2.v | 2,337 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR3,
VAR11,
VAR6 ,
VAR5
);
output VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR3;
input VAR11;
input VAR6 ;
input VAR5 ;
VAR10 VAR7 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s_1.v | 2,030 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR5,
VAR3
);
output VAR2 ;
input VAR4 ;
input VAR5;
input VAR3;
VAR1 VAR6 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
supply1 VAR5;
supply0 VAR3;
VAR1 VAR6 (
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
tugrulyatagan/RISC-processor | xilinx_processor/subroutine_stack.v | 1,262 | module MODULE1(
input VAR1,
input VAR4,
input VAR7,
input [11:0] VAR6,
output reg [11:0] VAR5
);
reg [11:0] VAR8 [7:0];
reg [2:0] VAR3;
integer VAR2; | gpl-2.0 |
bgamari/timetag-fpga | fx2_bidir.v | 5,002 | module MODULE1(
VAR32, VAR8, VAR13, VAR10, VAR28,
VAR38, VAR34, VAR6, VAR30,
VAR18, VAR2, VAR4,
VAR14, VAR9,
VAR15, VAR3, VAR37, VAR33
);
input [7:0] VAR18;
input VAR2;
output VAR4;
output [7:0] VAR14;
output VAR9;
input [7:0] VAR15;
input VAR3;
output VAR37;
input VAR33;
input VAR32;
output VAR34; inout [7:0] VAR8;
ou... | gpl-3.0 |
marqs85/ossc | rtl/videogen.v | 5,452 | module MODULE1 (
input VAR28,
input VAR6,
input VAR9,
input [1:0] VAR36,
output reg [7:0] VAR12,
output reg [7:0] VAR15,
output reg [7:0] VAR4,
output reg VAR3,
output reg VAR2,
output reg VAR21,
output reg [9:0] VAR7,
output reg [9:0] VAR13
);
parameter VAR33 = 10'd62;
parameter VAR17 = 10'd60;
parameter VAR18 = 10'd7... | gpl-3.0 |
mballance/wb_dma | rtl/wb_dma_ch_arb.v | 50,454 | module MODULE1(clk, rst, req, VAR33, VAR22);
input clk;
input rst;
input [30:0] req; output [4:0] VAR33; input VAR22;
parameter [4:0]
VAR17 = 5'h0,
VAR7 = 5'h1,
VAR28 = 5'h2,
VAR14 = 5'h3,
VAR15 = 5'h4,
VAR9 = 5'h5,
VAR34 = 5'h6,
VAR27 = 5'h7,
VAR6 = 5'h8,
VAR16 = 5'h9,
VAR30 = 5'ha,
VAR4 = 5'hb,
VAR29 = 5'hc,
VAR11 = ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.symbol.v | 1,364 | module MODULE1 (
input VAR6 ,
output VAR4 ,
output VAR5 ,
input VAR1
);
supply1 VAR3;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Multi Cycle CPU/Multi Cycle CPU.srcs/sources_1/new/MultiState.v | 1,288 | module MODULE1(
input clk,
input rst,
input [5:0] VAR10,
output [2:0] state
);
reg [2:0] VAR6;
assign state = VAR6;
always@(posedge clk) begin
if (rst == 0) begin
VAR6 = 3'VAR2;
end else begin
case (VAR6)
3'VAR2: VAR6 = 3'VAR4;
3'VAR4: begin
if (VAR10[5:3] == 3'VAR9) begin VAR6 = 3'VAR2;
end else begin VAR6 = 3'VAR5;
e... | mit |
eda-globetrotter/MarcheProcessor | src/cpu.v | 5,152 | module MODULE1(
clk,
reset,
VAR42, VAR39, VAR34, VAR8, VAR17, VAR53, VAR31 );
input clk, reset;
input [0:31] VAR42; input [0:127] VAR34;
output [0:31] VAR39; output [0:127] VAR8; output [0:21] VAR17; output VAR53, VAR31;
wire [0:31] VAR39;
wire [0:31] VAR49, VAR32, VAR24;
wire [0:4] VAR27, VAR57;
wire [0:1] VAR25, VAR6... | mit |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_ss_422to444.v | 5,031 | module MODULE1 (
clk,
VAR8,
VAR17,
VAR9,
VAR18,
VAR10);
parameter VAR6 = 0;
parameter VAR4 = 16;
localparam VAR15 = VAR4 - 1;
input clk;
input VAR8;
input [VAR15:0] VAR17;
input [15:0] VAR9;
output [VAR15:0] VAR18;
output [23:0] VAR10;
reg VAR7 = 'd0;
reg VAR14 = 'd0;
reg [VAR15:0] VAR16 = 'd0;
reg VAR3 = 'd0;
reg [7:0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2b/sky130_fd_sc_hdll__and2b.behavioral.pp.v | 1,954 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR4 ,
VAR14,
VAR5,
VAR15 ,
VAR11
);
output VAR6 ;
input VAR9 ;
input VAR4 ;
input VAR14;
input VAR5;
input VAR15 ;
input VAR11 ;
wire VAR7 ;
wire VAR8 ;
wire VAR1;
not VAR12 (VAR7 , VAR9 );
and VAR10 (VAR8 , VAR7, VAR4 );
VAR13 VAR3 (VAR1, VAR8, VAR14, VAR5);
buf VAR2 (VAR6 , VAR1 );
end... | apache-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/ram_controller_phy.v | 30,627 | module MODULE1 (
VAR71,
VAR11,
VAR92,
VAR18,
VAR34,
VAR76,
VAR13,
VAR5,
VAR24,
VAR42,
VAR2,
VAR80,
VAR79,
VAR22,
VAR72,
VAR32,
VAR77,
VAR51,
VAR8,
VAR41,
VAR59,
VAR75,
VAR1,
VAR28,
VAR88,
VAR65,
VAR12,
VAR10,
VAR7,
VAR60,
VAR20,
VAR82,
VAR48,
VAR19,
VAR25,
VAR57,
VAR27,
VAR45,
VAR83,
VAR98,
VAR73,
VAR29,
VAR56,
VAR23,
... | gpl-2.0 |
The-OpenROAD-Project/asap7 | asap7sc7p5t_27/Verilog/asap7sc7p5t_INVBUF_SRAM_TT_201020.v | 17,322 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.functional.v | 1,105 | module MODULE1 ();
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_8-parallel/src/dramcon.v | 8,664 | module MODULE1(input wire VAR72,
input wire VAR77,
input wire VAR69,
input wire [1:0] VAR27, input wire [31:0] VAR38, input wire [31:0] VAR22, input wire [VAR6-1:0] VAR63, output wire VAR9, output reg [VAR6-1:0] VAR64, output reg VAR14, output wire VAR51, output wire VAR32, output wire VAR60, inout wire [VAR39] VAR45,
... | mit |
defparam/snes-hook | verilog/snes_hook.v | 6,520 | module MODULE1 (
input clk,
input VAR26,
input [7:0] addr,
inout [7:0] VAR31,
input VAR15,
input VAR7,
input VAR30,
input VAR28,
output reg VAR13,
output reg VAR1,
input VAR6,
input VAR14,
output reg VAR9,
output VAR8,
output reg [3:0] VAR12
);
reg VAR2;
wire VAR20;
reg VAR32;
reg [7:0] VAR22;
reg [7:0] VAR5;
reg VAR23... | gpl-3.0 |
merckhung/zet | cores/fmlbrg/rtl/fmlbrg_datamem.v | 2,062 | module MODULE1 #(
parameter VAR5 = 8
) (
input VAR15,
input [VAR5-1:0] VAR17,
input [1:0] VAR8,
input [15:0] VAR6,
output [15:0] dout,
input [VAR5-1:0] VAR1,
output [15:0] VAR10
);
reg [7:0] VAR16[0:(1 << VAR5)-1];
reg [7:0] VAR2[0:(1 << VAR5)-1];
wire [7:0] VAR3;
wire [7:0] VAR9;
wire [7:0] VAR7;
wire [7:0] VAR11;
wir... | gpl-3.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_output1.v | 2,214 | module MODULE1 (
address,
VAR7,
clk,
VAR8,
VAR4,
VAR9,
VAR5,
VAR3
)
;
output [ 31: 0] VAR5;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR8;
input VAR4;
input [ 31: 0] VAR9;
wire VAR6;
reg [ 31: 0] VAR1;
wire [ 31: 0] VAR5;
wire [ 31: 0] VAR2;
wire [ 31: 0] VAR3;
assign VAR6 = 1;
assign V... | mit |
tymonx/hdl-xlibcores | hdl/ipc/ipc_fifo.v | 5,219 | module MODULE1(
input VAR4,
input VAR6,
input VAR2,
input [VAR15-1:0] VAR16,
input VAR10,
output reg [VAR15-1:0] VAR19,
output reg VAR23,
output VAR25,
output VAR12,
output [VAR21-1:0] VAR7
);
parameter VAR13 = 256;
parameter VAR20 = 0;
parameter VAR15 = 8;
parameter VAR21 = VAR22(VAR13);
localparam VAR8 = 2**VAR21;
lo... | bsd-3-clause |
lkesteloot/alice | alice4/fpga/Alice4-DE0/Alice4.v | 16,975 | module MODULE1
(
input VAR15, input VAR21, input [2:0] VAR20, output [6:0] VAR7, output VAR83, output [6:0] VAR75, output VAR31, output [6:0] VAR79, output VAR13, output [6:0] VAR37, output VAR103, output [9:0] VAR67, inout [15:0] VAR127, output [12:0] VAR35, output VAR52, output VAR51, output VAR128, output VAR5, outp... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.behavioral.v | 1,564 | module MODULE1 (
VAR14 ,
VAR4,
VAR2,
VAR8,
VAR13
);
output VAR14 ;
input VAR4;
input VAR2;
input VAR8;
input VAR13;
supply1 VAR6;
supply0 VAR12;
supply1 VAR11 ;
supply0 VAR3 ;
wire VAR10 ;
wire VAR7;
or VAR9 (VAR10 , VAR2, VAR4 );
nand VAR5 (VAR7, VAR13, VAR10, VAR8);
buf VAR1 (VAR14 , VAR7 );
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/rtl/clock.v | 13,315 | module MODULE1
(
input wire VAR20,
input wire VAR124,
input wire VAR11,
output wire VAR26,
output wire VAR102,
output wire VAR3,
output wire VAR62,
output wire VAR10,
output wire VAR43,
output wire VAR144
);
wire VAR56;
wire VAR52;
wire VAR4;
wire VAR23;
wire VAR85;
wire VAR92;
wire VAR36;
wire VAR140;
wire VAR164;
wir... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_sideband.v | 73,536 | module MODULE1
VAR10 = 3,
VAR33 = 2, VAR156 = 1,
VAR144 = 4,
VAR150 = 1,
VAR149 = 1, VAR19 = 3,
VAR2 = 4,
VAR38 = 2,
VAR153 = 2,
VAR60 = 0,
VAR84 = 10,
VAR172 = 13,
VAR196 = 10,
VAR134 = 10,
VAR124 = 10,
VAR142 = 6,
VAR197 = 16,
VAR92 = 6,
VAR154 = 4,
VAR21 = 2 )
(
VAR143,
VAR66,
VAR169,
VAR175,
VAR81,
VAR160,
VAR183,
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.pp.blackbox.v | 1,351 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR7 ,
VAR8 ,
VAR1,
VAR3,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR8 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/sword.v | 6,367 | module MODULE1 (
address,
VAR18,
VAR32);
input [14:0] address;
input VAR18;
output [15:0] VAR32;
tri1 VAR18;
wire [15:0] VAR11;
wire [15:0] VAR32 = VAR11[15:0];
VAR14 VAR3 (
.VAR51 (address),
.VAR38 (VAR18),
.VAR17 (VAR11),
.VAR10 (1'b0),
.VAR13 (1'b0),
.VAR5 (1'b1),
.VAR33 (1'b0),
.VAR43 (1'b0),
.VAR41 (1'b1),
.VAR46 ... | gpl-2.0 |
azonenberg/antikernel-ipcores | device_abstraction/BidirectionalBuffer.v | 4,091 | module MODULE1 #(
parameter VAR9 = 1,
parameter VAR7 = 1
) (
output wire[VAR9-1:0] VAR4,
input wire[VAR9-1:0] VAR11,
inout wire[VAR9-1:0] VAR6,
input wire VAR8
);
genvar VAR1;
generate
for(VAR1=0; VAR1<VAR9; VAR1 = VAR1+1) begin: VAR2
VAR5 VAR12(
.VAR3(VAR11[VAR1]),
.VAR14(VAR6[VAR1]),
.VAR10(VAR4[VAR1]),
.VAR13(VAR7 ?... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd1/sky130_fd_sc_hs__clkdlyinv5sd1.blackbox.v | 1,287 | module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_tt.v | 6,119 | module MODULE1(
clk, rst, VAR8,
VAR11, VAR6, VAR20, VAR3, VAR12,
VAR17
);
input clk; input rst; input VAR8; input VAR11; input VAR6; input [31:0] VAR20; input [31:0] VAR3; output [31:0] VAR12; output VAR17;
reg [31:0] VAR21; else
wire [31:0] VAR21; VAR13
reg [31:0] VAR10; else
wire [31:0] VAR10; VAR13
wire VAR24; wire ... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/encoder_ip_prj/encoder_ip_prj.srcs/sources_1/ip/mult_gen_1/mult_gen_1_stub.v | 1,249 | module MODULE1(VAR2, VAR3, VAR1)
;
input [11:0]VAR2;
input [13:0]VAR3;
output [32:0]VAR1;
endmodule | gpl-3.0 |
kevintownsend/R3 | verilog/column_counter.v | 1,760 | module MODULE1(
input reset,
input clk,
input VAR1,
output VAR9,
input [31:0] VAR3,
output [31:0] VAR11,
output [4:0] VAR8
);
reg VAR4;
reg [31:0] VAR6;
reg [4:0] counter;
reg [5:0] VAR2;
reg [4:0] VAR10;
reg [31:0] VAR7;
always @(posedge clk) begin
if(reset) begin
VAR2 <= 0;
VAR4 <= 0;
end else begin
VAR4 <= 0;
if(VAR... | mit |
lvd2/zxevo | fpga/base_trdemu/trunk/video/video_sync_v.v | 5,421 | module MODULE1(
input wire clk,
input wire VAR2, input wire VAR14,
input wire VAR20,
input wire VAR9,
input wire [ 1:0] VAR12,
output reg VAR33,
output reg VAR32,
output reg VAR3,
output reg VAR35 );
localparam VAR15 = 9'd00;
localparam VAR29 = 9'd08;
localparam VAR34 = 9'd11;
localparam VAR6 = 9'd32;
localparam VAR27 ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.behavioral.v | 2,557 | module MODULE1( VAR6, VAR7, VAR2, VAR3 );
input VAR7, VAR6, VAR2;
output VAR3;
VAR5 VAR1(.VAR6(VAR6),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3));
VAR5 VAR4(.VAR6(VAR6),.VAR7(VAR7),.VAR2(VAR2),.VAR3(VAR3)); | apache-2.0 |
cpulabs/mist1032isa | src/primitive/altera/ram_512bit_16word/ram_512bit_16word.v | 9,570 | module MODULE1 (
VAR19,
VAR7,
VAR18,
VAR41,
VAR17,
VAR51,
VAR39);
input [63:0] VAR19;
input VAR7;
input [511:0] VAR18;
input [3:0] VAR41;
input [3:0] VAR17;
input VAR51;
output [511:0] VAR39;
tri1 [63:0] VAR19;
tri1 VAR7;
tri0 VAR51;
wire [511:0] VAR20;
wire [511:0] VAR39 = VAR20[511:0];
VAR2 VAR52 (
.VAR38 (VAR17),
.V... | bsd-2-clause |
deepakcu/maestro | fpga/DE4_Ethernet_0/pll.v | 4,079 | module MODULE1 (
address,
VAR9,
clk,
read,
VAR18,
write,
VAR17,
VAR16,
VAR11,
VAR1,
VAR4
)
;
output VAR16;
output VAR11;
output [ 15: 0] VAR1;
output VAR4;
input [ 2: 0] address;
input VAR9;
input clk;
input read;
input VAR18;
input write;
input [ 15: 0] VAR17;
wire VAR12;
wire VAR3;
wire VAR16;
wire VAR11;
wire VAR13;... | apache-2.0 |
maijohnson/comp3601_blue_15s2 | AudioController/bpm_from_interval.v | 9,137 | module MODULE1(
input [31:0] counter, input wire [7:0] VAR1, output wire [7:0] VAR2 );
assign VAR2 = (counter < 32'd23529 ) ? 254 : (counter < 32'd23622 ) ? 253 : (counter < 32'd23715 ) ? 252 : (counter < 32'd23809 ) ? 251 :
(counter < 32'd23904 ) ? 250 :
(counter < 32'd24000 ) ? 249 :
(counter < 32'd24096 ) ? 248 :
(c... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b_4.v | 2,245 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR10 ,
VAR1 ,
VAR3,
VAR4,
VAR8 ,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR10 ;
input VAR1 ;
input VAR3;
input VAR4;
input VAR8 ;
input VAR2 ;
VAR9 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sa1/cheat.v | 12,249 | module MODULE1(
input clk,
input [7:0] VAR30,
input [23:0] VAR20,
input [7:0] VAR7,
input VAR35,
input VAR18,
input VAR26,
input VAR17,
input VAR55,
input VAR21,
input VAR52,
input VAR15,
input VAR48,
input VAR45,
input VAR66,
input VAR40,
input [2:0] VAR33,
input VAR44,
input [31:0] VAR19,
output [7:0] VAR67,
output V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4.pp.blackbox.v | 1,376 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4 ,
VAR11 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR9,
VAR6,
VAR10 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR11 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR9;
input VAR6;
input VAR10 ;
input VAR8 ;
endmodule | apache-2.0 |
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