repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_12.behavioral.v | 1,175 | module MODULE1( VAR5, VAR1, VAR6 );
input VAR5, VAR1;
output VAR6;
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6));
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b.pp.symbol.v | 1,325 | module MODULE1 (
input VAR3 ,
input VAR4 ,
output VAR6 ,
input VAR2 ,
input VAR5,
input VAR1,
input VAR7
);
endmodule | apache-2.0 |
somethingnew2-0/CS552-CPU | ExecuteForwarding.v | 2,105 | module MODULE1(VAR16, VAR13, VAR6, VAR10, VAR7, VAR4, VAR3, VAR1, VAR12, VAR24, VAR14, VAR17, VAR25, VAR23, VAR11, VAR9, VAR20, VAR8, VAR22, VAR18, VAR15, VAR5, VAR2);
input [15:0] VAR16, VAR13, VAR3, VAR12, VAR25, VAR11, VAR20, VAR8;
input [3:0] VAR6, VAR10, VAR7, VAR14, VAR22;
input VAR4, VAR1, VAR24, VAR17, VAR23, V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.blackbox.v | 1,391 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR2 ,
VAR10 ,
VAR3 ,
VAR6
);
output VAR8 ;
input VAR4 ;
input VAR2 ;
input VAR10 ;
input VAR3 ;
input VAR6;
supply1 VAR1;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/verilog/convolve_kernel_fbkb.v | 1,946 | module MODULE1
VAR22 = 0,
VAR19 = 5,
VAR15 = 32,
VAR26 = 32,
VAR2 = 32
)(
input wire clk,
input wire reset,
input wire VAR1,
input wire [VAR15-1:0] VAR8,
input wire [VAR26-1:0] VAR12,
output wire [VAR2-1:0] dout
);
wire VAR10;
wire VAR6;
wire VAR13;
wire [31:0] VAR11;
wire VAR17;
wire [31:0] VAR7;
wire VAR21;
wire [31:... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_startup/spi_clgen.v | 5,136 | module MODULE1 (VAR9, rst, VAR8, enable, VAR7, VAR3, posedge, negedge);
parameter VAR5 = 2;
parameter VAR6 = 1;
parameter VAR10 = 1;
input VAR9; input rst; input enable; input VAR8; input VAR7; output VAR3; output posedge; output negedge;
reg VAR3;
reg posedge;
reg negedge;
reg [VAR5-1:0] VAR1; wire VAR4; wire VAR2;
as... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/top/N2x0/capture_ddrlvds.v | 1,674 | module MODULE1
(input clk,
input VAR4,
input VAR23,
input [VAR29-1:0] VAR3,
input [VAR29-1:0] VAR28,
output reg [(2*VAR29)-1:0] out);
wire [VAR29-1:0] VAR24;
wire VAR25;
wire [(2*VAR29)-1:0] VAR34;
reg [(2*VAR29)-1:0] VAR13;
VAR14 #(.VAR18("VAR5"), .VAR17("VAR6"))
VAR32 (.VAR20(VAR25), .VAR16(VAR4), .VAR21(VAR23));
gen... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/channel_adapter/master_0_b2p_adapter.v | 1,510 | module MODULE1 (
input clk,
input VAR10,
output reg VAR9,
input VAR2,
input [ 7: 0] VAR6,
input [ 7: 0] VAR8,
input VAR4,
input VAR7,
input VAR5,
output reg VAR11,
output reg [ 7: 0] VAR3,
output reg VAR12,
output reg VAR13
);
reg VAR1;
always @* begin
VAR9 = VAR5;
VAR11 = VAR2;
VAR3 = VAR6;
VAR12 = VAR4;
VAR13 = VAR7;... | mit |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/usb_core/usb_121pll/usb_121pll_0002.v | 2,235 | module MODULE1(
input wire VAR27,
input wire rst,
output wire VAR36,
output wire VAR8,
output wire VAR64
);
VAR55 #(
.VAR40("false"),
.VAR7("20.0 VAR35"),
.VAR47("VAR21"),
.VAR11(2),
.VAR30("60.000000 VAR35"),
.VAR38("0 VAR20"),
.VAR50(50),
.VAR12("60.000000 VAR35"),
.VAR5("8333 VAR20"),
.VAR39(50),
.VAR70("0 VAR35"),
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.symbol.v | 1,389 | module MODULE1 (
input VAR4,
input VAR6,
input VAR2,
input VAR8,
input VAR7,
output VAR5
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR10 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/phy/prbs_gen.v | 5,781 | module MODULE1 #
(
parameter VAR7 = 4
)
(
input clk,
input VAR6,
input rst,
output [VAR7-1:0] VAR9
);
localparam VAR11 = 0;
reg [VAR7 - 1:0] VAR2;
reg [VAR7 - 1:0] VAR4;
reg [3:0] VAR10;
reg VAR1, VAR5;
integer VAR3;
always @ (posedge clk)
begin
if (rst )
VAR4 <= {{VAR7-1{1'b0}},1'b1};
end
else if (VAR6) begin
if ( VAR... | lgpl-3.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201010_abus3/wasca/synthesis/submodules/wasca_performance_counter_0.v | 5,070 | module MODULE1 (
address,
VAR18,
clk,
VAR17,
write,
VAR16,
VAR19
)
;
output [ 31: 0] VAR19;
input [ 2: 0] address;
input VAR18;
input clk;
input VAR17;
input write;
input [ 31: 0] VAR16;
wire VAR14;
reg [ 63: 0] VAR15;
reg [ 63: 0] VAR9;
wire VAR3;
wire VAR12;
wire VAR10;
wire VAR6;
wire [ 31: 0] VAR5;
reg [ 31: 0] VAR... | gpl-2.0 |
rkrajnc/minimig-mist | rtl/cache/CacheBlockRAM.v | 10,770 | module MODULE1 (
VAR8,
VAR25,
VAR4,
VAR16,
VAR6,
VAR52,
VAR9,
VAR64,
VAR57);
input [8:0] VAR8;
input [8:0] VAR25;
input VAR4;
input [17:0] VAR16;
input [17:0] VAR6;
input VAR52;
input VAR9;
output [17:0] VAR64;
output [17:0] VAR57;
tri1 VAR4;
tri0 VAR52;
tri0 VAR9;
wire [17:0] VAR62;
wire [17:0] VAR36;
wire [17:0] VAR6... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/bist/prcfg_adc.v | 6,030 | module MODULE1 (
clk,
VAR20,
VAR11,
VAR5,
VAR28,
VAR8,
VAR15,
VAR6,
VAR10,
VAR17,
VAR24
);
localparam VAR26 = 8'hA1;
parameter VAR7 = 0;
input clk;
input [31:0] VAR20;
output [31:0] VAR11;
input VAR5;
input VAR28;
input [31:0] VAR8;
output VAR15;
output VAR6;
output VAR10;
output [31:0] VAR17;
input VAR24;
reg VAR6;
re... | gpl-3.0 |
alankarkotwal/lca-processor | misc/mux.v | 1,221 | module MODULE2(VAR7, VAR6, VAR3, VAR5, VAR4, VAR1, VAR9, VAR2, VAR8, out);
output reg [15:0] out;
input [15:0] VAR7, VAR6, VAR3, VAR5, VAR4, VAR1, VAR9, VAR2;
input [2:0] VAR8;
always@(VAR7 or VAR6 or VAR3 or VAR5 or VAR4 or VAR1 or VAR9 or VAR2 or VAR8) begin
case(VAR8)
0: out = VAR7;
1: out = VAR6;
2: out = VAR3;
3: ... | gpl-2.0 |
peteasa/oh | src/common/hdl/oh_clockdiv.v | 4,553 | module MODULE1
(
input clk, input VAR11, input VAR25, input VAR15, input [7:0] VAR7, input [15:0] VAR26, input [15:0] VAR23, output VAR17, output VAR10, output VAR31, output VAR8, output VAR2, output VAR3, output VAR28 );
reg [7:0] counter;
reg VAR19;
reg VAR5;
reg VAR24;
reg [2:0] period;
wire VAR29;
wire [3:0] VAR21;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.functional.pp.v | 2,146 | module MODULE1 (
VAR10,
VAR9,
VAR12 ,
VAR6,
VAR4,
VAR8 ,
VAR17
);
input VAR10;
input VAR9;
output VAR12 ;
input VAR6;
input VAR4;
input VAR8 ;
input VAR17 ;
wire VAR17 VAR1 ;
wire VAR17 VAR15 ;
wire VAR14 ;
wire VAR5;
and VAR7 (VAR1 , VAR8, VAR17 );
nor VAR13 (VAR15 , VAR6, VAR4 );
nor VAR11 (VAR14 , VAR15, VAR1 );
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.functional.v | 1,225 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
wire VAR3;
not VAR4 (VAR3, VAR2 );
buf VAR5 (VAR1 , VAR3 );
endmodule | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_2-parallel/src/vivado_ip_dram/ui/mig_7series_v2_3_ui_cmd.v | 11,340 | module MODULE1 #
(
parameter VAR52 = 100,
parameter VAR11 = 33,
parameter VAR13 = 3,
parameter VAR37 = 12,
parameter VAR40 = 5,
parameter VAR33 = 2,
parameter VAR38 = 16,
parameter VAR36 = 4,
parameter VAR10 = "VAR55"
)
(
VAR34, VAR20, VAR18, VAR25, VAR9, VAR39, VAR28, VAR53, VAR51,
VAR4, VAR12, VAR22,
rst, clk, VAR30,... | mit |
MeshSr/onetswitch45 | ons45-app21-ref_switch/vivado/onets_7045_4x_ref_switch/ip/ref_switch_core/src/core/onet_core_logic.v | 28,719 | module MODULE1(
input clk, input reset,
input VAR217,
output VAR113,
input [31:0] VAR192,
input VAR42,
input VAR178,
input [3:0] VAR188,
output VAR43,
output VAR75,
output [31:0] VAR7,
output VAR104,
output VAR215,
output [3:0] VAR276,
input VAR24,
input VAR157,
output VAR263,
input [31:0] VAR63,
input VAR218,
input VA... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai.symbol.v | 1,394 | module MODULE1 (
input VAR1,
input VAR7,
input VAR8 ,
input VAR6 ,
output VAR9
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp_1.v | 2,337 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR1 ,
VAR5,
VAR10 ,
VAR2 ,
VAR7 ,
VAR3
);
output VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR5;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR3 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.pp.symbol.v | 1,339 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR6 ,
input VAR1 ,
output VAR3 ,
input VAR5,
input VAR4
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_parallel_in_serial_out_dynamic.v | 2,868 | module MODULE1
,parameter VAR9(VAR37)
,parameter VAR35 = VAR10(VAR37)
)
(input VAR30
,input VAR22
,input VAR34
,input [VAR35-1:0] VAR25
,input [VAR37-1:0][VAR33-1:0] VAR28
,output VAR32
,output VAR8
,output VAR13
,output [VAR33-1:0] VAR26
,input VAR21
);
logic VAR23;
logic [VAR35-1:0] VAR4;
logic [VAR37-1:0][VAR33-1:0]... | bsd-3-clause |
chaohu/Daily-Learning | Digital-Logic/lab/lab4/lab4_3/lab4_3_1/lab4_3_1.srcs/sources_1/new/lab4_3_1.v | 1,387 | module MODULE1(
input VAR3,clk,
output reg [3:0] VAR1
);
reg [1:0] state,VAR7;
parameter VAR4 = 2'b00,VAR6 = 2'b01,VAR2 = 2'b11,VAR5 = 2'b10;
begin
begin
begin
end
begin | mit |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilogOrig/Top-harness-augmented-k-means.v | 1,734 | module MODULE1;
reg clk = 0;
reg reset = 1; | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_rsqrt.v | 2,297 | module MODULE1(VAR5, VAR22,
VAR24, VAR21, VAR12,
VAR4, VAR6, VAR11);
parameter VAR27 = 32;
parameter VAR19 = 11;
parameter VAR26 = 64;
input VAR5, VAR22;
input [VAR27-1:0] VAR24;
input VAR21;
output VAR12;
output [VAR27-1:0] VAR4;
output VAR6;
input VAR11;
reg [VAR19-1:0] VAR25;
wire [VAR27-1:0] VAR7;
wire VAR13;
wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd/sky130_fd_sc_hdll__tapvgnd.functional.pp.v | 1,238 | module MODULE1 (
VAR2,
VAR1,
VAR3 ,
VAR4
);
input VAR2;
input VAR1;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/round_robin_arb.v | 7,530 | module MODULE1
parameter VAR10 = 100,
parameter VAR16 = 3
)
(
VAR15, VAR1,
clk, rst, req, VAR4, VAR17, VAR9
);
input clk;
input rst;
input [VAR16-1:0] req;
wire [VAR16-1:0] VAR20;
reg [VAR16*2-1:0] VAR3;
always @(VAR20)
VAR3 = {VAR20, VAR20};
reg [VAR16*2-1:0] VAR19;
always @(req) VAR19 = {req, req};
reg [VAR16-1:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp.functional.pp.v | 2,700 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR17 ,
VAR1 ,
VAR16 ,
VAR14 ,
VAR3,
VAR24 ,
VAR12 ,
VAR23 ,
VAR25 ,
VAR13
);
output VAR5 ;
input VAR4 ;
input VAR17 ;
input VAR1 ;
input VAR16 ;
input VAR14 ;
input VAR3;
input VAR24 ;
input VAR12 ;
input VAR23 ;
input VAR25 ;
input VAR13 ;
wire VAR20 ;
wire VAR9 ;
wire VAR19 ;
wire VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.functional.v | 1,532 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR4 ;
input VAR8;
wire VAR3;
VAR2 VAR5 VAR6 (VAR3 , VAR4, VAR8 );
buf VAR1 (VAR7 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.behavioral.v | 1,873 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR10
);
output VAR7 ;
input VAR2 ;
input VAR10;
supply1 VAR1;
supply0 VAR14;
supply1 VAR9 ;
supply0 VAR12 ;
wire VAR5 ;
reg VAR6 ;
wire VAR8;
wire VAR3 ;
VAR13 VAR11 (VAR5 , VAR3, VAR8, VAR6, VAR1, VAR14);
buf VAR4 (VAR7 , VAR5 );
endmodule | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v | 8,727 | module MODULE1 #
(
parameter VAR17 = 100,
parameter VAR13 = 3636,
parameter VAR3 = 3,
parameter VAR14 = 3,
parameter VAR10 = "VAR1"
)
(
input clk,
input rst,
input VAR6,
output reg [VAR14-1:0] VAR27,
output reg VAR2,
output reg VAR21,
output reg VAR25,
output reg VAR30,
output VAR29
);
localparam VAR11 = 63;
localparam... | mit |
svenstaro/uni-projekt | verilog/c25Board.v | 2,272 | module MODULE1 (
clk, reset, VAR16, VAR8, VAR39, VAR58, VAR51, VAR41, VAR46, VAR7, VAR10, VAR30, VAR45, VAR4, VAR14, VAR1, VAR60, VAR31, VAR9, VAR55, VAR36,
);
input clk;
input VAR33;
input [3:0] VAR16;
output [3:0] VAR8;
wire [3:0] VAR8;
input VAR39;
output VAR58;
wire VAR58;
wire VAR25;
wire [15:0] VAR35;
wire [31:0]... | gpl-3.0 |
webmaster442/prog-elektonikak | Kodok/Verilog/03-1.v | 1,211 | module MODULE1(VAR2, VAR3, select);
output VAR2;
input [31:0] VAR3;
input [5:0] select;
wire VAR2;
wire [31:0] VAR3;
wire [5:0] select;
assign VAR2 =
(select == 5'h00) ? VAR3[0] :
(select == 5'h01) ? VAR3[1] :
(select == 5'h02) ? VAR3[2] :
(select == 5'h03) ? VAR3[3] :
(select == 5'h04) ? VAR3[4] :
(select == 5'h05) ? ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b_2.v | 2,318 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR5 ,
VAR11 ,
VAR2 ,
VAR3,
VAR9,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR10 ;
input VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR3;
input VAR9;
input VAR4 ;
input VAR6 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.behavioral.v | 2,879 | module MODULE1 (
VAR23,
VAR12 ,
VAR31 ,
VAR13 ,
VAR25 ,
VAR20 ,
VAR19 ,
VAR14
);
input VAR23;
input VAR12 ;
input VAR31 ;
output VAR13 ;
input VAR25 ;
input VAR20 ;
input VAR19 ;
input VAR14 ;
wire VAR6 ;
wire VAR18 ;
wire VAR11 ;
wire VAR2 ;
reg VAR15 ;
wire VAR26 ;
wire VAR7 ;
wire VAR5 ;
wire VAR21;
wire VAR30 ;
wir... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/acl_fp_custom_normalize.v | 4,186 | module MODULE1(
VAR14, VAR15,
VAR22, VAR27, VAR6,
VAR1, VAR5, VAR16, VAR19,
enable, VAR12);
parameter VAR25 = 1;
parameter VAR8 = 0;
parameter VAR23 = 1;
parameter VAR11 = 0;
input VAR14, VAR15;
input VAR1, VAR5;
output VAR16, VAR19;
input enable;
input [27:0] VAR22;
input [8:0] VAR27; input VAR6;
output [31:0] VAR12;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv_1.v | 1,868 | module MODULE1 (
VAR4 ,
VAR6 ,
VAR5,
VAR3
);
output VAR4 ;
input VAR6 ;
input VAR5;
input VAR3;
VAR2 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4,
VAR6
);
output VAR4;
input VAR6;
supply1 VAR5;
supply0 VAR3;
VAR2 VAR1 (
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.behavioral.v | 2,113 | module MODULE1( VAR10, VAR3, VAR8 );
input VAR10, VAR3;
output VAR8;
reg VAR6;
VAR11 VAR1(.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR6(VAR6));
VAR11 VAR9(.VAR10(VAR10),.VAR3(VAR3),.VAR8(VAR8),.VAR6(VAR6));
not VAR4(VAR5,VAR3);
buf VAR2(VAR7,VAR3); | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/ball_small/ball_small_stub.v | 1,295 | module MODULE1(VAR4, VAR3, VAR5, VAR1, VAR2)
;
input VAR4;
input [0:0]VAR3;
input [9:0]VAR5;
input [11:0]VAR1;
output [11:0]VAR2;
endmodule | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rotate.v | 3,076 | module MODULE1
parameter VAR8 = "VAR1",
parameter VAR4 = 4
)
(
input [VAR4-1:0] VAR9,
input [VAR2(VAR4)-1:0] VAR11,
output [VAR4-1:0] VAR7
);
wire [2*VAR4-1:0] VAR5;
wire [2*VAR4-1:0] VAR3;
wire [2*VAR4-1:0] VAR10;
wire [2*VAR4-1:0] VAR6;
assign VAR3 = {VAR9,VAR9};
assign VAR5 = {VAR9,VAR9};
assign VAR6 = VAR3 << VAR11... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/PIO_EP.v | 10,482 | module MODULE1 (
clk,
VAR77,
VAR72,
VAR57,
VAR69,
VAR28,
VAR4,
VAR76,
VAR6,
VAR12,
VAR79,
VAR34,
VAR14,
VAR37,
VAR46,
VAR33,
VAR22,
VAR53,
VAR48,
VAR9
);
input clk;
input VAR77;
output [63:0] VAR72;
output [7:0] VAR57;
output [127:0] VAR72;
output [1:0] VAR57;
output VAR69;
output VAR28;
output VAR4;
input VAR76;
input... | lgpl-3.0 |
bangonkali/sram | i2c_slave.v | 2,564 | module MODULE1 (
VAR13,
VAR12,
VAR14,
VAR4,
VAR18,
state,
VAR7
);
inout VAR13;
input VAR12;
wire VAR11;
reg VAR9;
reg VAR16;
input [6:0] VAR14;
output reg [6:0] VAR18;
reg [7:0] VAR15;
output reg VAR7;
reg [2:0] counter;
output reg [2:0] state;
output reg [7:0] VAR4;
assign VAR11 = VAR13;
assign VAR13 = VAR9 ? VAR16: 1... | mit |
mindrobots/P8X32A_Emulation | P8X32A_BeMicroCV/hub.v | 7,955 | module MODULE1
(
input VAR6,
input VAR43,
input VAR14,
input [7:0] VAR3,
input VAR50,
input VAR13,
input VAR17,
input [1:0] VAR16,
input [15:0] VAR12,
input [31:0] VAR7,
output reg [31:0] VAR22,
output VAR41,
output [7:0] VAR46,
output reg [7:0] VAR25,
output [7:0] VAR1,
output [27:0] VAR34,
output reg [7:0] VAR23
);
r... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.functional.pp.v | 1,837 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR2 ,
VAR7 ,
VAR15 ,
VAR10,
VAR6,
VAR5 ,
VAR1
);
output VAR11 ;
input VAR3 ;
input VAR2 ;
input VAR7 ;
input VAR15 ;
input VAR10;
input VAR6;
input VAR5 ;
input VAR1 ;
wire VAR9 ;
wire VAR4;
and VAR12 (VAR9 , VAR3, VAR2, VAR7, VAR15 );
VAR14 VAR8 (VAR4, VAR9, VAR10, VAR6);
buf VAR13 (VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.pp.symbol.v | 1,518 | module MODULE1 (
input VAR9 ,
output VAR3 ,
output VAR11 ,
input VAR6 ,
input VAR10 ,
input VAR8 ,
input VAR7 ,
input VAR4 ,
input VAR1,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_8.behavioral.pp.v | 1,069 | module MODULE1( VAR1, VAR4 );
inout VAR1, VAR4;
VAR2 VAR5(.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR3(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/afifo.v | 6,341 | module MODULE1 #
(
parameter VAR23 = 100,
parameter VAR16 = 32,
parameter VAR9 = 16,
parameter VAR7 = 4,
parameter VAR4 = 1 )
(
input VAR33,
input rst,
input VAR35,
input [VAR16-1:0] VAR11,
input VAR22,
input VAR17,
output [VAR16-1:0] VAR26,
output reg VAR31,
output reg VAR28,
output reg VAR38
);
reg [VAR16-1:0] VAR3 [... | lgpl-3.0 |
joseluisquiroga/bj-actor-model | hlang/hgen_net/vlg_fnd/pakout.v | 1,685 | module MODULE1
VAR32=VAR7,
VAR15=VAR1,
VAR18=VAR24,
VAR5=VAR9,
VAR29=VAR2
)(
);
parameter VAR22 = VAR12;
parameter VAR25 = VAR27;
localparam VAR34 = ((VAR3 / VAR32) + 1);
localparam VAR28 = (((VAR8(VAR15)-1) >= 0)?(VAR8(VAR15)-1):(0));
localparam VAR31 = (((VAR8(VAR34)-1) >= 0)?(VAR8(VAR34)-1):(0));
reg [0:0] VAR4 = VA... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_AV_Config.v | 15,606 | module MODULE1 (
clk,
reset,
address,
VAR12,
read,
write,
VAR46,
VAR15,
VAR17,
VAR74,
irq,
VAR30,
VAR1
);
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] VAR12;
input read;
input write;
input [31: 0] VAR46;
inout VAR15;
output reg [31: 0] VAR17;
output VAR74;
output irq;
output VAR30;
output VAR1;
localpar... | gpl-2.0 |
davidjabon/Verilog | Binary_to_BCD/binary_to_BCD_ten_bit.v | 1,519 | module MODULE1(
input [9:0] in,
output [3:0] VAR29,
output [3:0] VAR24,
output [3:0] VAR41,
output VAR23
);
wire [3:0] VAR1,VAR13,VAR19,VAR36,VAR4,VAR16,VAR11,VAR37,VAR10,VAR8,VAR31,VAR9;
wire [3:0] VAR40,VAR20,VAR28,VAR32,VAR17,VAR7,VAR5,VAR6,VAR39,VAR34,VAR18,VAR27;
assign VAR40 = {1'b0,in[9:7]};
assign VAR20 = {VAR1... | gpl-2.0 |
jhol/butterflylogic | rtl/eia232.v | 4,083 | module MODULE1 #(
parameter [31:0] VAR3 = 100000000,
parameter [31:0] VAR23 = 28,
parameter [31:0] VAR36 = 115200,
parameter VAR33 = VAR3 / VAR23 )(
input wire VAR4,
input wire reset,
input wire [1:0] VAR35, input wire VAR8, input wire [31:0] VAR14, input wire VAR17, output wire VAR11, output wire [39:0] VAR12,
output ... | gpl-2.0 |
cr88192/bgbtech_bjx1core | smalltst/compdec/ModFbCc.v | 9,403 | module MODULE1(VAR64, reset,
VAR18, VAR4, VAR24, VAR22, VAR35,
VAR49, VAR17, VAR3);
input VAR64;
input reset;
input[9:0] VAR18;
input[9:0] VAR4;
output[7:0] VAR24;
output[7:0] VAR22;
output[7:0] VAR35;
output[13:0] VAR49;
input[31:0] VAR17;
input[31:0] VAR3;
reg[9:0] VAR50;
reg[9:0] VAR34;
reg[7:0] VAR65;
reg[7:0] VAR5... | mit |
sh-chris110/chris | FPGA/chris.sdram.ok/db/ip/soc_design/submodules/soc_design_niosII_core_cpu_debug_slave_wrapper.v | 9,640 | module MODULE1 (
VAR53,
VAR45,
clk,
VAR31,
VAR39,
VAR21,
VAR12,
VAR37,
VAR56,
VAR38,
VAR24,
VAR26,
VAR10,
VAR54,
VAR4,
VAR2,
VAR49,
VAR14,
VAR9,
VAR47,
VAR36,
VAR43,
VAR51,
VAR27,
VAR35,
VAR44,
VAR52,
VAR41,
VAR1,
VAR55,
VAR40,
VAR6,
VAR13
)
;
output [ 37: 0] VAR36;
output VAR43;
output VAR51;
output VAR27;
output VAR3... | gpl-2.0 |
mogorschampion/VGA_animated_object | pixelGeneration.v | 2,114 | module MODULE1(clk, rst, VAR8, VAR12, VAR4, VAR1, VAR6, VAR13);
input clk, rst;
input [3:0] VAR8;
input [2:0] VAR12;
input [9:0] VAR4, VAR1;
input VAR6;
output reg [2:0] VAR13;
wire VAR3, VAR5;
localparam VAR11 = 640;
localparam VAR15 = 480;
localparam VAR9 = 40;
localparam VAR14 = 5;
wire [9:0] VAR19, VAR18, VAR20, VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp.functional.pp.v | 2,192 | module MODULE1 (
VAR12 ,
VAR6,
VAR2 ,
VAR13 ,
VAR18 ,
VAR11 ,
VAR3 ,
VAR16
);
output VAR12 ;
input VAR6;
input VAR2 ;
input VAR13 ;
input VAR18 ;
input VAR11 ;
input VAR3 ;
input VAR16 ;
wire VAR15 ;
wire VAR8 ;
wire VAR14;
not VAR5 (VAR15 , VAR6 );
VAR9 VAR4 VAR10 (VAR8 , VAR2, VAR13, VAR15, , VAR18, VAR11);
buf VAR17... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_ready_and_link_async_to_wormhole.v | 6,819 | module MODULE1
,parameter VAR26(VAR8 )
,parameter VAR5 = 2
,parameter int VAR18[VAR5:0] = '{5, 4, 0}
,parameter VAR26(VAR29 )
,localparam VAR27 = VAR25(VAR7)
,localparam VAR11 = VAR25(VAR8)
,localparam VAR10 = VAR18[VAR5]
)
( input VAR2
,input VAR19
,input [VAR27-1:0] VAR15
,output [VAR27-1:0] VAR9
,input [VAR10-1:0] V... | bsd-3-clause |
jamesbowman/swapforth | j1a/verilog/j1.v | 4,076 | module MODULE1(
input wire clk,
input wire VAR6,
output wire VAR13,
output wire VAR9,
output wire [15:0] VAR12,
output wire VAR39,
output wire [VAR11-1:0] dout,
input wire [VAR11-1:0] VAR8,
output wire [12:0] VAR14,
input wire [15:0] VAR23);
reg [3:0] VAR31, VAR40; reg [VAR11-1:0] VAR34, VAR28; reg VAR35;
reg [12:0] VA... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo_cascade.v | 2,556 | module MODULE1
(input clk, input reset, input VAR3,
input [VAR22-1:0] VAR26,
input VAR27,
output VAR24,
output [VAR22-1:0] VAR19,
output VAR25,
input VAR17,
output [15:0] VAR28,
output [15:0] VAR7);
wire [VAR22-1:0] VAR15, VAR21;
wire VAR6, VAR5, VAR18, VAR10;
wire [4:0] VAR14, VAR9, VAR4, VAR8;
wire [15:0] VAR16, VAR1... | gpl-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_nios2_qsys_0_cpu_debug_slave_wrapper.v | 10,470 | module MODULE1 (
VAR5,
VAR41,
clk,
VAR31,
VAR25,
VAR9,
VAR37,
VAR45,
VAR38,
VAR21,
VAR35,
VAR30,
VAR43,
VAR51,
VAR8,
VAR42,
VAR2,
VAR22,
VAR29,
VAR55,
VAR56,
VAR40,
VAR13,
VAR10,
VAR44,
VAR53,
VAR15,
VAR4,
VAR18,
VAR12,
VAR23,
VAR7,
VAR59,
VAR32,
VAR39,
VAR47
)
;
output [ 37: 0] VAR56;
output VAR40;
output VAR13;
outpu... | gpl-3.0 |
rkrajnc/minimig-mist | bench/ps2mouse/ps2mouse_ctrl.v | 6,437 | module MODULE1 (
input wire clk,
input wire reset,
inout wire VAR32,
inout wire VAR22
);
reg [ 8-1:0] VAR31;
reg [ 8-1:0] VAR30;
reg [ 8-1:0] VAR10;
reg VAR12;
reg VAR19;
reg VAR13;
reg VAR25;
wire VAR21;
reg [ 2-1:0] VAR33;
reg [ 3-1:0] VAR3;
reg [11-1:0] VAR23;
reg [12-1:0] VAR14;
reg [16-1:0] VAR5;
reg [ 3-1:0] VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.blackbox.v | 1,550 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6 ,
VAR5,
VAR4 ,
VAR7 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR5;
input VAR4 ;
input VAR7 ;
input VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fill/sky130_fd_sc_ms__fill.functional.pp.v | 1,147 | module MODULE1 (
VAR3,
VAR4,
VAR2 ,
VAR1
);
input VAR3;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
kwantam/multiexp-a5gx | verilog/table_control.v | 4,503 | module MODULE1 #( parameter VAR33 = 40
)
( input clk
, input VAR29
, input [26:0] VAR37 , input [14:0] VAR4
, input [2:0] VAR44
, output [26:0] VAR15
, output [26:0] VAR22
, output [26:0] VAR13
, input [1:0] VAR16
, output VAR45
);
localparam VAR43 = VAR6(VAR33);
wire [26:0] VAR32 [2:0];
assign VAR15 = VAR32[0];
assign... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0p/sky130_fd_sc_hd__lpflow_inputiso0p.functional.v | 1,399 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR2 ;
input VAR1;
wire VAR3;
not VAR4 (VAR3, VAR1 );
and VAR6 (VAR5 , VAR2, VAR3 );
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_tx_if.v | 5,257 | module MODULE1 #
(
parameter VAR7 = 64,
parameter VAR6 = 2,
parameter VAR1 = 0,
parameter VAR4 = 0,
parameter VAR2 = 0,
parameter VAR3 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR7-1:0] VAR10,
input wire [VAR6-1:0] VAR9,
output wire [VAR7-1:0] VAR5,
output wire [VAR6-1:0] VAR11,
input wire VAR8
); | mit |
KorotkiyEugene/Netmaker_vc_router_syn_quartus | NW_matrix_arbiter.v | 6,604 | module MODULE2 (state, VAR21, VAR28);
parameter VAR15=4;
input [VAR15*VAR15-1:0] state;
input [VAR15-1:0] VAR21;
output [VAR15*VAR15-1:0] VAR28;
genvar VAR10,VAR26;
generate
for (VAR10=0; VAR10<VAR15; VAR10=VAR10+1) begin:VAR3
for (VAR26=0; VAR26<VAR15; VAR26=VAR26+1) begin:VAR17
assign VAR28[VAR26*VAR15+VAR10]= (state... | gpl-2.0 |
P3Stor/P3Stor | pcie/core/gtx_rx_valid_filter_v6.v | 11,721 | module MODULE1 #(
parameter VAR21 = 28
)
(
output [1:0] VAR15,
output [15:0] VAR33,
output VAR39,
output VAR18,
output [ 2:0] VAR71,
output VAR30,
input [1:0] VAR3,
input [15:0] VAR58,
input VAR72,
input VAR20,
input [ 2:0] VAR44,
input VAR34,
input VAR74,
input VAR54,
input VAR12,
input VAR2
);
parameter VAR4 = 1;
par... | gpl-2.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_pl_input_port.v | 3,474 | module MODULE1(VAR28, VAR7, VAR17, VAR21, VAR2,
VAR24, VAR22,
VAR27, VAR11,
clk, VAR10);
parameter VAR19 = 4;
parameter VAR13 = 8;
input clk, VAR10;
input [VAR19-1:0] VAR28;
input [VAR19-1:0] VAR7;
input VAR8 VAR17 [VAR19-1:0];
output VAR8 VAR21 [VAR19-1:0];
output VAR1 VAR2 [VAR19-1:0];
output [VAR19-1:0] VAR24 [VAR19... | gpl-2.0 |
manu3193/ControladorElevadorTDD | Temporizador.v | 4,172 | module MODULE1( clk, VAR4, VAR1, VAR2);
input clk, VAR4, VAR1;
output VAR2;
reg[3:0] VAR5 = 4'b0; localparam VAR3=7; reg VAR2=0;
always @(posedge clk) begin
VAR2<=0;
if(VAR1)
VAR5 <=0;
end
else begin
if (VAR4) begin
if(VAR5==VAR3-1) begin
VAR2<=1'b1;
VAR5 <=0;
end
else begin
VAR5 <= VAR5+1;
end
end
end
end
endmodule | mit |
takeshineshiro/fpga_linear_128 | CoarseDelay_bb.v | 5,130 | module MODULE1 (
address,
VAR2,
VAR1);
input [2:0] address;
input VAR2;
output [63:0] VAR1;
endmodule | mit |
Canaan-Creative/MM | verilog/superkdf9/components/lm32_top/lm32_interrupt.v | 10,925 | module MODULE1 (
VAR36,
VAR6,
VAR12,
VAR37,
VAR28,
VAR16,
VAR13,
VAR4,
VAR31,
VAR1,
VAR17,
VAR38,
VAR26,
VAR33
);
parameter VAR39 = VAR29;
input VAR36; input VAR6;
input [VAR39-1:0] VAR12;
input VAR37;
input VAR28; input VAR16; else
input VAR13; VAR5
input VAR4; VAR9 VAR30
input VAR31; VAR5
input [VAR8] VAR1; input [VA... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_lh/sky130_fd_sc_hvl__lsbufhv2hv_lh.functional.v | 1,278 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
buf VAR3 (VAR1 , VAR2 );
endmodule | apache-2.0 |
GREO/GNU-Radio | usrp/fpga/sdr_lib/cordic_stage.v | 1,799 | module MODULE1( VAR9, reset, enable, VAR4,VAR8,VAR3,VAR12,VAR11,VAR2,VAR1);
parameter VAR7 = 16;
parameter VAR6 = 16;
parameter VAR5 = 1;
input VAR9;
input reset;
input enable;
input [VAR7-1:0] VAR4,VAR8;
input [VAR6-1:0] VAR3;
input [VAR6-1:0] VAR12;
output [VAR7-1:0] VAR11,VAR2;
output [VAR6-1:0] VAR1;
wire VAR10 = ~... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf.symbol.v | 1,236 | module MODULE1 (
input VAR5,
output VAR3
);
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch3/FSM_input_enable.v | 3,813 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR9,
output reg VAR12,
output wire VAR2,
output reg VAR1
);
parameter [3:0] VAR6 = 3'd0,
VAR7 = 3'd1,
VAR4 = 3'd2,
VAR14 = 3'd3,
VAR8 = 3'd4,
VAR3= 3'd5,
VAR11 = 3'd6,
VAR5 = 3'd7;
reg [2:0] VAR10, VAR13;
always @(posedge clk, posedge rst)
if(rst)
VAR10 <= VAR... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/master_0.v | 1,780 | module MODULE1 (
input wire VAR8, input wire VAR11, output wire [31:0] VAR10, input wire [31:0] VAR15, output wire VAR2, output wire VAR12, output wire [31:0] VAR9, input wire VAR6, input wire VAR3, output wire [3:0] VAR4, output wire VAR5 );
VAR13 #(
.VAR1 (0),
.VAR7 (50000),
.VAR14 (2)
) VAR16 (
.VAR8 (VAR8), .VAR11 ... | apache-2.0 |
open-fpga-nvm/open-nvm-source | fpga/NAND/uart_rx.v | 3,889 | module MODULE1(
input clk,
input rst,
input VAR7,
output [7:0] VAR13,
output VAR11
);
reg [8:0] VAR4;
assign VAR13[7:0] = VAR4[8:1];
reg VAR10;
assign VAR11 = VAR10;
reg [9:0] VAR2;
reg [3:0] VAR5;
reg VAR1;
reg [9:0] VAR12;
reg [9:0] VAR3;
always@(posedge clk) begin
if(rst)
begin
VAR1 <= VAR6;
VAR10 <= 0;
end
else
beg... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_0_axi4_tg.v | 18,550 | module MODULE1 #(
parameter VAR1 = 4, parameter VAR104 = 32, parameter VAR13 = 32,
parameter VAR96 = 0, parameter VAR68 = 0,
parameter VAR60 = 0,
parameter VAR102 = 32'hFFFFFFFF,
parameter VAR63 = 32'hFFFFD000,
parameter VAR16 = 32'h00002000,
parameter VAR14 = 40,
parameter VAR46 = 40,
parameter VAR99 = 0,
parameter VA... | mit |
yunqu/PYNQ | boards/ip/boolean_generator_1.1/src/input_mux.v | 1,808 | module MODULE1 # (parameter VAR1 = 24) (
input [4:0] sel,
input [VAR1-1:0] VAR3,
output reg VAR2
);
always @(sel, VAR3)
case(sel)
5'h00 : VAR2 = VAR3[0];
5'h01 : VAR2 = VAR3[1];
5'h02 : VAR2 = VAR3[2];
5'h03 : VAR2 = VAR3[3];
5'h04 : VAR2 = VAR3[4];
5'h05 : VAR2 = VAR3[5];
5'h06 : VAR2 = VAR3[6];
5'h07 : VAR2 = VAR3[7]... | bsd-3-clause |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/v/firdecim_m2_n50.v | 25,329 | module MODULE1
(
VAR8, VAR35,
VAR73, VAR6, VAR68, VAR64
);
parameter VAR93 = 16;
parameter VAR77 = 32;
parameter VAR86 = 32;
output reg signed [(VAR77-1):0] VAR8;
output reg VAR35;
input VAR73; input VAR6;
input VAR68;
input signed [(VAR93-1):0] VAR64;
reg [5:0] VAR17;
reg [5:0] VAR45;
reg [4:0] VAR36;
reg [4:0] VAR43;... | gpl-2.0 |
cpulabs/mist1032isa | src/mist1032isa.v | 19,115 | module MODULE1(
input wire VAR287,
input wire VAR1,
input wire VAR19,
input wire VAR37,
output wire VAR211,
input wire VAR202,
output wire VAR191,
input wire VAR240,
output wire [1:0] VAR102, output wire [3:0] VAR84,
output wire VAR158, output wire [31:0] VAR224,
output wire [31:0] VAR238,
input wire VAR4,
output wire ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_isolatch_pp_pkg_s/sky130_fd_sc_hs__udp_isolatch_pp_pkg_s.symbol.v | 1,479 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR4,
input VAR3 ,
input VAR2 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s2s/sky130_fd_sc_ms__dlymetal6s2s.symbol.v | 1,355 | module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_nios2_gen2_0.v | 5,779 | module MODULE1 (
input wire clk, input wire VAR25, input wire VAR23, output wire [31:0] VAR21, output wire [3:0] VAR14, output wire VAR1, input wire [31:0] VAR7, input wire VAR11, output wire VAR20, output wire [31:0] VAR3, output wire VAR26, output wire [29:0] VAR24, output wire VAR10, input wire [31:0] VAR8, input wi... | gpl-3.0 |
martinmiranda14/Digitales | Lab_6/project_5/project_5.srcs/sources_1/new/teclado.v | 5,484 | module MODULE1(
input [7:0] VAR12,
output reg [4:0] VAR18,
output reg [2:0] VAR21,
output [7:0] VAR1
);
localparam VAR17 = 3'd1;
localparam VAR25 = 3'd2;
localparam VAR9 = 3'd3;
localparam VAR24 = 3'd4;
localparam VAR23 = 8'h45;
localparam VAR19 = 8'h16;
localparam VAR11 = 8'h1E;
localparam VAR4 = 8'h26;
localparam VAR... | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/gsu_umult.v | 4,361 | module MODULE1 (
VAR4,
VAR19,
VAR11);
input [7:0] VAR4;
input [7:0] VAR19;
output [15:0] VAR11;
wire [15:0] VAR17;
wire [15:0] VAR11 = VAR17[15:0];
VAR1 VAR2 (
.VAR4 (VAR4),
.VAR19 (VAR19),
.VAR11 (VAR17),
.VAR8 (1'b0),
.VAR7 (1'b1),
.VAR6 (1'b0),
.VAR5 (1'b0),
.sum (1'b0));
VAR2.VAR13 = "VAR16=5",
VAR2.VAR10 = "VAR15... | gpl-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/ddram_controller.v | 2,492 | module MODULE1 #(
parameter VAR13 = 4'h0
) (
input VAR32,
input VAR14,
input VAR4,
input [13:0] VAR40,
input VAR5,
input [31:0] VAR46,
output [31:0] VAR34,
input [VAR2-1:0] VAR35,
input VAR22,
input VAR25,
output VAR19,
input [3:0] VAR1,
input [31:0] VAR28,
output [31:0] VAR23,
output VAR3,
output VAR18,
output VAR38,
... | lgpl-3.0 |
Tao-J/nexys3MIPSSoC | Counter_3channel.v | 1,133 | module MODULE1(input clk,
input rst,
input VAR10,
input VAR2,
input VAR5,
input VAR3,
input [31:0] VAR9,
input [1:0] VAR8,
output VAR1,
output VAR4,
output VAR6,
output [31:0] VAR7
);
endmodule | gpl-3.0 |
DeadWitcher/amber-de0-nano | hw/vlog/system/timer_module.v | 15,776 | module MODULE1 #(
parameter VAR41 = 32,
parameter VAR57 = 4
)(
input VAR64,
input [31:0] VAR1,
input [VAR57-1:0] VAR63,
input VAR16,
output [VAR41-1:0] VAR9,
input [VAR41-1:0] VAR60,
input VAR6,
input VAR54,
output VAR29,
output VAR12,
output [2:0] VAR34
);
reg [15:0] VAR30 = 'd0; reg [15:0] VAR47 = 'd0; reg [15:0] VAR... | lgpl-2.1 |
rohit91/novena-sd-fpga | novena-sd.srcs/sources_1/ip/clk_wiz_v3_5_0/bclk_dll/example_design/bclk_dll_exdes.v | 5,155 | module MODULE1
parameter VAR16 = 100
)
( input VAR14,
input VAR8,
output [1:1] VAR12,
output VAR22,
input VAR5,
output VAR19
);
localparam VAR10 = 16;
wire VAR7 = !VAR19 || VAR5 || VAR8;
reg VAR18;
reg VAR20;
reg VAR1;
reg VAR17;
wire VAR9;
wire clk;
reg [VAR10-1:0] counter;
VAR6 VAR13
(.VAR11 (VAR13),
.VAR4 (VAR14));
... | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_1/affine_block_ieee754_fp_multiplier_1_1_stub.v | 1,338 | module MODULE1(VAR1, VAR3, VAR2)
;
input [31:0]VAR1;
input [31:0]VAR3;
output [31:0]VAR2;
endmodule | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Framebuffer.v | 4,275 | module MODULE1 (
address,
VAR34,
VAR16,
VAR46,
clk,
VAR30,
VAR54,
VAR1,
reset,
VAR29,
write,
VAR20,
VAR23,
VAR35,
VAR25,
VAR43
)
;
output [ 7: 0] VAR25;
output [ 7: 0] VAR43;
input [ 18: 0] address;
input [ 18: 0] VAR34;
input VAR16;
input VAR46;
input clk;
input VAR30;
input VAR54;
input VAR1;
input reset;
input VAR29... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_lsu_ctrl.v | 35,288 | module MODULE1(
input VAR8,
input VAR27,
output VAR103,
output VAR144, input VAR25, output [VAR209-1:0] VAR168,
output [VAR137 -1:0] VAR9,
output VAR124 , output VAR200, output [VAR142 -1:0] VAR85,
output VAR255,
output VAR65,
input VAR33, output VAR222, input [VAR142-1:0] VAR62, input VAR75, input [VAR209-1:0] VAR147,... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/cdp/ddio_out_1.v | 4,804 | module MODULE1 (
VAR10,
VAR24,
VAR19,
VAR6,
VAR15);
input VAR10;
input VAR24;
input VAR19;
input VAR6;
output VAR15;
tri0 VAR10;
wire [0:0] VAR17;
wire [0:0] VAR5 = VAR17[0:0];
wire VAR15 = VAR5;
wire VAR1 = VAR24;
wire VAR18 = VAR1;
wire VAR3 = VAR19;
wire VAR14 = VAR3;
VAR4 VAR2 (
.VAR6 (VAR6),
.VAR24 (VAR18),
.VAR10... | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_38.v | 27,569 | module MODULE4 (
clk,
reset,
VAR64,
VAR188,
VAR116,
VAR81,
VAR132
);
parameter VAR71 = 18;
parameter VAR183 = 38;
parameter VAR113 = 19;
localparam VAR85 = 45;
input clk;
input reset;
input VAR64;
input VAR188;
input [VAR71-1:0] VAR116; output VAR81;
output [VAR71-1:0] VAR132;
localparam VAR26 = 18; localparam VAR118 =... | mit |
wgml/sysrek | rgb2hsv/ipcore_dir/mul10.v | 26,635 | module MODULE1 (
clk, VAR58, VAR48, VAR32
);
input clk;
input [9 : 0] VAR58;
input [9 : 0] VAR48;
output [19 : 0] VAR32;
wire \VAR96/VAR42 ;
wire \VAR96/VAR95 ;
wire \VAR33/VAR13 ;
wire \VAR33/VAR50 ;
wire \VAR33/VAR97<17>VAR20 ;
wire \VAR33/VAR97<16>VAR20 ;
wire \VAR33/VAR97<15>VAR20 ;
wire \VAR33/VAR97<14>VAR20 ;
wir... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf.functional.v | 1,522 | module MODULE1 (
VAR7,
VAR1
);
output VAR7;
input VAR1;
wire VAR4;
wire VAR2 ;
wire VAR5 ;
buf VAR3 (VAR4, VAR1 );
VAR6 VAR8 (VAR7 , VAR4, VAR2, VAR5);
endmodule | apache-2.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ob_de2_70.v | 7,267 | module MODULE1 (
VAR8,
VAR17
);
parameter VAR9 = 9'h01A;
parameter VAR18 = 9'h01A;
parameter VAR4 = 9'h07B;
parameter VAR16 = 9'h07B;
parameter VAR2 = 9'h0F8;
parameter VAR6 = 9'h006;
parameter VAR5 = 9'h000;
parameter VAR15 = 9'h001;
parameter VAR7 = 9'h002;
parameter VAR1 = 9'h001;
input [ 5: 0] VAR8;
output [26: 0] ... | mit |
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