repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
rqou/openfpga | hdl/xc2c-model/XC2CBitstream.v | 10,088 | module MODULE1(
VAR15,
VAR8,
VAR4, VAR18, VAR14,
VAR24, VAR25, VAR13,
VAR20, VAR6,
VAR10, VAR1,
VAR11, VAR23,
VAR26, VAR19,
VAR17, VAR3, VAR21, VAR7, VAR9
);
parameter VAR2 = 0;
parameter VAR5 = 0;
parameter VAR22 = 0;
input wire VAR15;
input wire VAR8;
input wire VAR4;
input wire[VAR2-1:0] VAR18;
output reg[VAR22-1:0]... | lgpl-2.1 |
prernaa/CPUVerilog | control.v | 5,300 | module MODULE1(
VAR28,
VAR17,
VAR1,
VAR25,
VAR10,
VAR26,
VAR4,
VAR16,
VAR3,
VAR32,
VAR6,
VAR19,
VAR5,
VAR11,
VAR20,
VAR9,
);
input[3:0] VAR28;
output reg VAR17;
output reg VAR1;
output reg[2:0] VAR25;
output reg VAR10;
output reg VAR26;
output reg VAR4;
output reg VAR16;
output reg VAR3;
output reg VAR32;
output reg VA... | mit |
borti4938/sd2snes | verilog/sd2snes_obc1/msu.v | 5,513 | module MODULE1(
input VAR44,
input enable,
input [13:0] VAR37,
input [7:0] VAR40,
input VAR16,
input [2:0] VAR10,
input [7:0] VAR31,
output [7:0] VAR8,
input VAR9,
input VAR1,
input VAR3,
output [7:0] VAR25,
output [7:0] VAR2,
output VAR19,
output [31:0] VAR14,
output [15:0] VAR15,
input [5:0] VAR43,
input [5:0] VAR39,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_psa_pp_pkg_s/sky130_fd_sc_hs__udp_dlatch_psa_pp_pkg_s.blackbox.v | 1,519 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR1 ,
VAR3,
VAR4 ,
VAR8 ,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR3;
input VAR4 ;
input VAR8 ;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/Video_System_Color_Space_Converter.v | 8,848 | module MODULE1 (
clk,
reset,
VAR8,
VAR18,
VAR21,
VAR5,
VAR29,
VAR3,
VAR15,
VAR25,
VAR6,
VAR27,
VAR4,
VAR33
);
parameter VAR10 = 23;
parameter VAR30 = 23;
parameter VAR13 = 1;
parameter VAR2 = 1;
input clk;
input reset;
input [VAR10: 0] VAR8;
input VAR18;
input VAR21;
input [VAR13:0] VAR5;
input VAR29;
input VAR3;
outpu... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_acl_kernel_interface_mm_interconnect_0.v | 61,932 | module MODULE1 (
input wire VAR110, input wire VAR289, input wire VAR359, input wire [29:0] VAR317, output wire VAR400, input wire [0:0] VAR95, input wire [3:0] VAR368, input wire VAR122, output wire [31:0] VAR326, output wire VAR327, input wire VAR84, input wire [31:0] VAR101, output wire [29:0] VAR28, output wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3_4.v | 2,174 | module MODULE2 (
VAR1 ,
VAR10 ,
VAR4 ,
VAR9 ,
VAR5,
VAR8,
VAR2 ,
VAR7
);
output VAR1 ;
input VAR10 ;
input VAR4 ;
input VAR9 ;
input VAR5;
input VAR8;
input VAR2 ;
input VAR7 ;
VAR3 VAR6 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn.symbol.v | 1,368 | module MODULE1 (
input VAR8 ,
output VAR6 ,
output VAR1 ,
input VAR3
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
donnaware/AGC | rtl/de0/modules/ng_SCL.v | 4,404 | module MODULE1(
input VAR29, input VAR11, input VAR6, output VAR18, output VAR2, output VAR15 );
wire VAR32 = VAR11;
reg [ 3:0] VAR4; always @(posedge VAR29 or negedge VAR32) if(!VAR32) VAR4 <= 4'h0; else if(VAR7) VAR4 <= 4'h0; else if(VAR14) VAR4 <= VAR4 + 4'd1;
wire VAR7 = VAR4[0] & VAR4[3]; wire VAR14 = VAR6;
reg [1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.v | 2,441 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR5 ,
VAR10 ,
VAR7,
VAR2 ,
VAR8 ,
VAR9 ,
VAR11
);
output VAR3 ;
output VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR7;
input VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR11 ;
VAR4 VAR1 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR9(VAR9),
... | apache-2.0 |
iori-yja/ball_detector | balldetector.v | 3,521 | module MODULE2(
input VAR10,
input VAR11,
input VAR40,
input VAR75,
output VAR20,
input [7:0] VAR38,
input VAR66,
output VAR61,
input VAR36,
input VAR52,
output [7:0] VAR64,
output VAR5,
inout VAR45,
output VAR35,
input VAR1,
input VAR78,
output [9:0] VAR19
);
wire write;
wire [15:0] VAR65;
wire VAR24;
wire VAR58;
wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp.pp.blackbox.v | 1,273 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3,
VAR4,
VAR6 ,
VAR2
);
output VAR1 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_1_cycles/integracion_fisica/front_end/source/subRecursiveKOA_1c.v | 5,506 | module MODULE1
(
input wire [VAR10-1:0] VAR7,
input wire [VAR10-1:0] VAR17,
output wire [2*VAR10-1:0] VAR27
);
generate
if (VAR10 <= 8) begin : VAR15
VAR13 #(.VAR10(VAR10))
VAR31 (
.VAR7(VAR7),
.VAR17(VAR17),
.VAR27(VAR27)
);
end else begin : VAR28
reg [2*VAR10-1:0] VAR6;
wire [1:0] VAR18;
wire [3:0] VAR20;
assign VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR2 ,
VAR5 ,
VAR1,
VAR7,
VAR4 ,
VAR3
);
output VAR6 ;
input VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
vancemiller/verilog-stopwatch | fsm.v | 2,665 | module MODULE1(input clk, VAR4, VAR14, VAR12,
output reg VAR15, reg VAR18
);
reg [3:0] state = VAR8, VAR11;
parameter VAR8 = 4'b0000, VAR3 = 4'b0001, VAR5 = 4'b0010, VAR7 = 4'b0011,
VAR19 = 4'b0100, VAR6 = 4'b0101, VAR1 = 4'b0110, VAR13 = 4'b0111,
VAR16 = 4'b1000, VAR2 = 4'b1001, VAR17 = 4'b1010, VAR10 = 4'b1011;
alway... | mit |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_onchip_memory2_0.v | 3,036 | module MODULE1 (
address,
VAR25,
VAR17,
clk,
VAR7,
reset,
VAR16,
write,
VAR8,
VAR6
)
;
parameter VAR20 = "MODULE1.VAR1";
output [ 31: 0] VAR6;
input [ 14: 0] address;
input [ 3: 0] VAR25;
input VAR17;
input clk;
input VAR7;
input reset;
input VAR16;
input write;
input [ 31: 0] VAR8;
wire VAR14;
wire [ 31: 0] VAR6;
wire... | gpl-3.0 |
cornell-zhang/datuner | designs/quartus/processor/hex_to_seven_seg.v | 1,207 | module MODULE1(VAR6, VAR5);
input [3:0] VAR6;
output [6:0] VAR5;
reg [6:0] VAR5;
wire [3:0] VAR8;
assign VAR8 = VAR6;
reg [3:0] VAR8;
VAR4 VAR2(
.in(VAR6[0]),
.out(VAR8[0])
);
VAR4 VAR1(
.in(VAR6[1]),
.out(VAR8[1])
);
VAR4 VAR3(
.in(VAR6[2]),
.out(VAR8[2])
);
VAR4 VAR7(
.in(VAR6[3]),
.out(VAR8[3])
);
always @ (VAR8)
be... | bsd-3-clause |
ShepardSiegel/ocpi | rtl/mkTLPSerializer.v | 18,849 | module MODULE1(VAR44,
VAR138,
VAR127,
VAR58,
VAR140,
VAR97,
VAR72,
VAR107,
VAR112,
VAR47,
VAR133,
VAR38,
VAR117,
VAR68,
VAR114);
input [15 : 0] VAR44;
input VAR138;
input VAR127;
input [152 : 0] VAR58;
input VAR140;
output VAR97;
input VAR72;
output [152 : 0] VAR107;
output VAR112;
input VAR47;
output [58 : 0] VAR133;
... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/LZD_syn.v | 5,982 | module MODULE3 ( VAR26, VAR39 );
input [25:0] VAR26;
output [4:0] VAR39;
wire VAR54, VAR37, VAR4, VAR117, VAR91, VAR79, VAR121, VAR56, VAR22, VAR63, VAR43, VAR111, VAR135, VAR42, VAR112, VAR153,
VAR126, VAR141, VAR81, VAR106, VAR72, VAR86, VAR88, VAR105, VAR47, VAR139, VAR136, VAR83, VAR98, VAR19,
VAR95, VAR16, VAR96, ... | gpl-3.0 |
EC-Chen/nthu.astroplan | divider.v | 1,232 | module MODULE1(
reset,
out,
clk
);
output out;
input clk;
input reset;
parameter VAR4 = 5;
parameter VAR5 = 2;
reg[31:0] VAR6;
reg VAR2;
wire VAR1;
wire VAR3,VAR7;
always@(posedge clk or negedge reset)
begin
if(reset == 0)
VAR6 <= 0;
end
else if(VAR6 == VAR4)
VAR6 <= 1;
else
VAR6 <= VAR6 + 1;
end
assign VAR3 = (VAR6 ==... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcin/sky130_fd_sc_lp__fahcin.functional.pp.v | 2,782 | module MODULE1 (
VAR17,
VAR16 ,
VAR1 ,
VAR22 ,
VAR13 ,
VAR21,
VAR10,
VAR25 ,
VAR6
);
output VAR17;
output VAR16 ;
input VAR1 ;
input VAR22 ;
input VAR13 ;
input VAR21;
input VAR10;
input VAR25 ;
input VAR6 ;
wire VAR27 ;
wire VAR24 ;
wire VAR3 ;
wire VAR23 ;
wire VAR2 ;
wire VAR20 ;
wire VAR7 ;
wire VAR28;
not VAR11 (V... | apache-2.0 |
rkrajnc/minimig-de1 | lib/altera/cycloneii_atoms.v | 230,557 | module MODULE1(
primitive VAR6 (VAR7, VAR15, VAR12, VAR4, VAR18, VAR22, VAR20);
input VAR12;
input VAR18;
input VAR22;
input VAR4;
input VAR15;
input VAR20;
output VAR7; reg VAR7;
VAR2 VAR7 = 1'b0;
VAR11
(??) ? ? 1 1 ? : ? : -; VAR13 ? ? 1 1 ? : ? : -; 1 1 (01) 1 1 ? : ? : 1; 1 1 (01) 1 VAR13 ? : ? : 1;
1 1 ? 1 VAR13 ?... | gpl-3.0 |
c4puter/bridge-hdl | top/c4-0/bridge.v | 7,853 | module MODULE1 (
inout [7:0] VAR45,
input VAR91,
input VAR166,
input VAR34,
output VAR58,
output VAR74,
inout [31:0] VAR176,
output VAR147,
input VAR88,
input VAR189,
input [1:0] VAR97,
output [1:0] VAR30,
output [1:0] VAR121,
output VAR12,
input VAR86,
inout [31:0] VAR186,
input [3:0] VAR168,
output [3:0] VAR180,
inpu... | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_gsu/main_tf.v | 3,054 | module MODULE1;
reg VAR21;
reg [23:0] VAR14;
reg VAR42;
reg VAR2;
reg VAR24;
reg VAR27;
reg VAR20;
reg VAR36;
reg VAR7;
reg VAR30;
reg VAR32;
reg [3:0] VAR6;
wire VAR16;
wire VAR34;
wire VAR28;
wire [22:0] VAR38;
wire VAR29;
wire VAR13;
wire VAR11;
wire VAR3;
wire VAR25;
wire [18:0] VAR5;
wire VAR1;
wire VAR31;
wire VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.pp.symbol.v | 1,409 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR4,
input VAR6 ,
input VAR2 ,
input VAR1 ,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai_4.v | 2,329 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR1,
VAR10,
VAR3,
VAR4 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR10;
input VAR3;
input VAR4 ;
input VAR8 ;
VAR6 VAR5 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 ... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/qpsk/QPSK_Modulator_Baseband.v | 2,014 | module MODULE1
(
VAR5,
VAR8,
VAR10
);
input [7:0] VAR5; output signed [15:0] VAR8; output signed [15:0] VAR10;
parameter signed [15:0] VAR9 = 23170; parameter signed [15:0] VAR13 = -23170; parameter signed [15:0] VAR14 = 23170; parameter signed [15:0] VAR1 = -23170; parameter signed [15:0] VAR7 = 23170; parameter signe... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap.pp.symbol.v | 1,186 | module MODULE1 (
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v | 2,077 | module MODULE1
(input VAR21
, input VAR14
, input [VAR16-1:0] VAR10
, input [VAR16-1:0] VAR6
, input [VAR16-1:0] VAR12
, output [VAR16-1:0] VAR5
, input VAR19
, output VAR23
, output [VAR16-1:0] VAR15
);
wire [VAR16-1:0] VAR4, VAR11, VAR1, VAR8;
VAR18 #(.VAR26(VAR16)) VAR2 (.VAR21, .VAR14, .VAR13(VAR1), .VAR27(VAR4));
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.symbol.v | 1,374 | module MODULE1 (
input VAR2,
input VAR6,
input VAR7,
input VAR3,
input VAR5,
output VAR9
);
supply1 VAR10;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
sabertazimi/hust-lab | digitalLogic/design/clock_design/src/clock.v | 3,946 | module MODULE1
(
input VAR3,
input VAR48,
input enable,
input reset,
input [2:0] VAR14,
input [2:0] VAR23,
input VAR45,
input VAR41,
output VAR22,
output [(VAR52-1):0] VAR51,
output [7:0] VAR2,
output [7:0] VAR38
);
wire [(VAR37-1):0] VAR34, VAR16, VAR21;
wire VAR7, VAR36, VAR25;
wire VAR6;
wire [(VAR37-1):0] VAR53;
wi... | mit |
bluespec/Flute | builds/Flute_RV64GC_MSU_WB_L1_L2_verilator_tohost/Verilog_RTL/mkI_MMU_Cache.v | 87,548 | module MODULE1(VAR196,
VAR248,
VAR190,
VAR224,
VAR194,
VAR322,
VAR145,
VAR371,
valid,
addr,
VAR269,
VAR295,
VAR198,
VAR118,
VAR8,
VAR374,
VAR257,
VAR291,
VAR46,
VAR38,
VAR116,
VAR92,
VAR390,
VAR241,
VAR275,
VAR197,
VAR363,
VAR115,
VAR337,
VAR139,
VAR142,
VAR266,
VAR128,
VAR109,
VAR56,
VAR238,
VAR318,
VAR260,
VAR274,
VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2.behavioral.pp.v | 1,774 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR13 ,
VAR12,
VAR8,
VAR7 ,
VAR9
);
output VAR11 ;
input VAR1 ;
input VAR13 ;
input VAR12;
input VAR8;
input VAR7 ;
input VAR9 ;
wire VAR6 ;
wire VAR10;
or VAR3 (VAR6 , VAR13, VAR1 );
VAR5 VAR4 (VAR10, VAR6, VAR12, VAR8);
buf VAR2 (VAR11 , VAR10 );
endmodule | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/m26_rx/m26_rx_ch.v | 2,883 | module MODULE1
(
input wire VAR2,
input wire VAR8,
input wire VAR3,
input wire VAR16,
output reg VAR6,
output reg VAR4,
output reg [15:0] VAR13,
output reg VAR5,
output reg VAR7
);
reg [15:0] VAR10;
always @(posedge VAR8)
VAR10[15:0] <= {VAR10[14:0], VAR3};
reg [17:0] VAR9;
always @(posedge VAR8)
VAR9[17:0] <= {VAR16, ... | bsd-3-clause |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/i2c_slave.v | 24,519 | module MODULE1 (
input wire VAR73, input wire VAR6,
output reg VAR48,
input wire clk, input wire VAR50, input wire [7:0] VAR71,
output reg VAR68,
output wire [7:0] VAR52, output wire [7:0] VAR21,
output wire [7:0] VAR32,
output wire [7:0] VAR44,
output wire [7:0] VAR55,
output wire [7:0] VAR47,
input wire [7:0] VAR28, ... | apache-2.0 |
Pylonight/MIPS-CPU | cpu/CPU_MIPS.v | 4,359 | module MODULE1(
output [15 : 0] VAR52,
output [7 : 0] VAR69,
output [5 : 0] VAR27,
input clk,
input VAR42,
input rst,
output VAR38
);
assign VAR52 = VAR67;
wire [2 : 0] state;
wire [5 : 0] VAR2;
reg [3 : 0] VAR39;
reg VAR38; reg [26 : 0] VAR25;
always @(posedge clk or negedge rst)
begin
if (rst == 0)
begin
VAR25 = 0;
e... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.behavioral.pp.v | 2,184 | module MODULE1 (
VAR5 ,
VAR6,
VAR2,
VAR11 ,
VAR4 ,
VAR15,
VAR12,
VAR10 ,
VAR17
);
output VAR5 ;
input VAR6;
input VAR2;
input VAR11 ;
input VAR4 ;
input VAR15;
input VAR12;
input VAR10 ;
input VAR17 ;
wire VAR19 ;
wire VAR18 ;
wire VAR8 ;
wire VAR16;
nand VAR7 (VAR19 , VAR2, VAR6 );
or VAR14 (VAR18 , VAR4, VAR11 );
nan... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.behavioral.pp.v | 1,333 | module MODULE1( VAR1, VAR5, VAR4, VAR6, VAR3, VAR2 );
input VAR6, VAR4, VAR1;
inout VAR3, VAR2;
output VAR5;
VAR8 VAR9(.VAR1(VAR1),.VAR5(VAR5),.VAR4(VAR4),.VAR6(VAR6),.VAR3(VAR3),.VAR2(VAR2));
VAR8 VAR7(.VAR1(VAR1),.VAR5(VAR5),.VAR4(VAR4),.VAR6(VAR6),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and4b/sky130_fd_sc_ls__and4b.symbol.v | 1,323 | module MODULE1 (
input VAR8,
input VAR6 ,
input VAR7 ,
input VAR2 ,
output VAR9
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.behavioral.v | 1,539 | module MODULE1 (
VAR1 ,
VAR3,
VAR7,
VAR13,
VAR10
);
output VAR1 ;
input VAR3;
input VAR7;
input VAR13;
input VAR10;
supply1 VAR8;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR9 ;
wire VAR2 ;
wire VAR11;
and VAR5 (VAR2 , VAR3, VAR7 );
or VAR14 (VAR11, VAR2, VAR10, VAR13);
buf VAR12 (VAR1 , VAR11 );
endmodule | apache-2.0 |
google/bigspicy | example_inputs/fp_multiplier/fp_multiplier.synth.v | 46,723 | module MODULE1(VAR79, VAR49, VAR6);
wire 000;
wire 001;
wire 002;
wire 003;
wire 004;
wire 005;
wire 006;
wire 007;
wire 008;
wire 009;
wire 010;
wire 011;
wire 012;
wire 013;
wire 014;
wire 015;
wire 016;
wire 017;
wire 018;
wire 019;
wire 020;
wire 021;
wire 022;
wire 023;
wire 024;
wire 025;
wire 026;
wire 027;
wire... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.behavioral.v | 3,096 | module MODULE1( VAR8, VAR1, VAR6, VAR5, VAR7 );
input VAR1, VAR5, VAR6;
output VAR7, VAR8;
VAR4 VAR3(.VAR8(VAR8),.VAR1(VAR1),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7));
VAR4 VAR2(.VAR8(VAR8),.VAR1(VAR1),.VAR6(VAR6),.VAR5(VAR5),.VAR7(VAR7)); | apache-2.0 |
crespum/N64-controller-FPGA | divM.v | 1,269 | module MODULE1(input wire VAR6, output wire VAR5);
parameter VAR3 = 12;
localparam VAR4 = VAR2(VAR3);
reg [VAR4-1:0] VAR1 = 0;
always @(posedge VAR6)
if (VAR1 == VAR3 - 1)
VAR1 <= 0;
else
VAR1 <= VAR1 + 1;
assign VAR5 = VAR1[VAR4-1];
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv.functional.pp.v | 1,937 | module MODULE1 (
VAR8 ,
VAR11 ,
VAR7 ,
VAR5 ,
VAR12,
VAR9 ,
VAR6
);
output VAR8 ;
input VAR11 ;
input VAR7 ;
input VAR5 ;
input VAR12;
input VAR9 ;
input VAR6 ;
wire VAR2;
wire VAR10 ;
VAR13 VAR1 (VAR2, VAR11, VAR12, VAR5 );
buf VAR4 (VAR10 , VAR2 );
VAR13 VAR3 (VAR8 , VAR10, VAR7, VAR5);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xnor2/sky130_fd_sc_ms__xnor2_4.v | 2,132 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR1 ,
VAR8,
VAR2,
VAR7 ,
VAR9
);
output VAR3 ;
input VAR4 ;
input VAR1 ;
input VAR8;
input VAR2;
input VAR7 ;
input VAR9 ;
VAR5 VAR6 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR3,
VAR4,
VAR1
);
output VAR3;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe.behavioral.pp.v | 1,191 | module MODULE1 (
VAR3,
VAR4,
VAR2 ,
VAR1
);
input VAR3;
input VAR4;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrbp/sky130_fd_sc_hvl__dfrbp_1.v | 2,449 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR2,
VAR3 ,
VAR10 ,
VAR7 ,
VAR8
);
output VAR6 ;
output VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR2;
input VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR8 ;
VAR11 VAR5 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd_snickerdoodle/gcd_snickerdoodle.srcs/sources_1/bd/gcd_zynq_snick/ip/gcd_zynq_snick_gcd_0_0/synth/gcd_zynq_snick_gcd_0_0.v | 9,003 | module MODULE1 (
VAR2,
VAR7,
VAR16,
VAR4,
VAR23,
VAR15,
VAR17,
VAR18,
VAR1,
VAR14,
VAR8,
VAR13,
VAR22,
VAR3,
VAR21,
VAR9,
VAR11,
VAR19,
VAR5,
interrupt
);
input wire [5 : 0] VAR2;
input wire VAR7;
output wire VAR16;
input wire [31 : 0] VAR4;
input wire [3 : 0] VAR23;
input wire VAR15;
output wire VAR17;
output wire [1 ... | mit |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo.v | 13,707 | module MODULE1(
rst,
VAR94,
VAR402,
din,
VAR156,
VAR198,
dout,
VAR115,
VAR426
);
input rst;
input VAR94;
input VAR402;
input [31 : 0] din;
input VAR156;
input VAR198;
output [31 : 0] dout;
output VAR115;
output VAR426;
VAR105 #(
.VAR297(0),
.VAR265(0),
.VAR60(0),
.VAR291(0),
.VAR394(0),
.VAR413(0),
.VAR135(0),
.VAR391(... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_xfer_status.v | 5,208 | module MODULE1 (
VAR10,
VAR21,
VAR14,
VAR5,
VAR13,
VAR18);
parameter VAR7 = 8;
localparam VAR11 = VAR7 - 1;
input VAR10;
input VAR21;
output [VAR11:0] VAR14;
input VAR5;
input VAR13;
input [VAR11:0] VAR18;
reg VAR1 = 'd0;
reg VAR3 = 'd0;
reg VAR16 = 'd0;
reg [ 5:0] VAR15 = 'd0;
reg VAR4 = 'd0;
reg [VAR11:0] VAR19 = 'd0... | gpl-3.0 |
AngelTerrones/MUSB | Hardware/musb/musb_cpzero.v | 32,596 | module MODULE1(
input clk,
input VAR134, input VAR57, input VAR29, input VAR116, input VAR11, input VAR22, input [4:0] VAR101, input [2:0] select, input [31:0] VAR54, input VAR79, input VAR44, output reg [31:0] VAR122, output VAR92, input [4:0] VAR124, input rst, input VAR114, input VAR139, input VAR106, input VAR13, i... | mit |
Elphel/x353 | memctrl353/mcontr353.v | 51,610 | module MODULE3(
VAR151, VAR93, VAR70,
VAR14, VAR18,
VAR113, VAR36, VAR145, VAR102, VAR90, VAR147, VAR74, VAR57, VAR25, VAR6, VAR19, do, VAR148, VAR178,
VAR16, VAR80, VAR26, VAR142, VAR139, VAR29, VAR170,
VAR23, VAR37, VAR140, VAR195, VAR121, VAR186,
VAR183, VAR91, VAR5, VAR30, VAR78, VAR116, VAR144, VAR100, VAR110,
VAR... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/niosII_system/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR2,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input address;
input VAR2;
input VAR1;
wire [ 31: 0] VAR3;
assign VAR3 = address ? 1423170505 : 0;
endmodule | gpl-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_dc_ram.v | 5,592 | module MODULE1(
clk, rst,
VAR7, VAR9, VAR2,
addr, en, VAR11, VAR1, VAR15
);
parameter VAR6 = VAR17;
parameter VAR8 = VAR14;
input clk;
input rst;
input [VAR8-1:0] addr;
input en;
input [3:0] VAR11;
input [VAR6-1:0] VAR1;
output [VAR6-1:0] VAR15;
input VAR7;
input [VAR13 - 1:0] VAR2; output VAR9;
assign VAR15 = {VAR6{1'... | apache-2.0 |
cospan/prometheus_fpga | rtl/fx3_bus_in_path.v | 4,214 | module MODULE1 (
input clk,
input rst,
input VAR14,
input [23:0] VAR2,
output VAR11,
output VAR15,
output VAR16,
input VAR4,
output VAR10,
output VAR8
);
localparam VAR18 = 4'h0;
localparam VAR9 = 4'h1;
localparam VAR17 = 4'h2;
localparam VAR1 = 4'h3;
reg [3:0] state;
reg [3:0] VAR7;
reg [23:0] VAR13;
reg [1:0] VAR12;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2_8.v | 2,097 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR8,
VAR7,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR1 ;
VAR9 VAR2 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR5,
VAR6
);
output VAR3;
... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ip/block_design_auto_pc_0/synth/block_design_auto_pc_0.v | 13,166 | module MODULE1 (
VAR76,
VAR48,
VAR92,
VAR71,
VAR14,
VAR94,
VAR17,
VAR109,
VAR78,
VAR82,
VAR16,
VAR9,
VAR23,
VAR64,
VAR89,
VAR30,
VAR45,
VAR111,
VAR91,
VAR42,
VAR57,
VAR15,
VAR90,
VAR36,
VAR106,
VAR65,
VAR4,
VAR52,
VAR56,
VAR61,
VAR72,
VAR32,
VAR110,
VAR10,
VAR20,
VAR93,
VAR33,
VAR34,
VAR7,
VAR31,
VAR77,
VAR21,
VAR67,
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbuf/sky130_fd_sc_lp__lsbuf.pp.blackbox.v | 1,330 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR1,
VAR4 ,
VAR6 ,
VAR3,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR8 ;
input VAR1;
input VAR4 ;
input VAR6 ;
input VAR3;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlclkp/sky130_fd_sc_hvl__sdlclkp_1.v | 2,270 | module MODULE2 (
VAR9,
VAR2 ,
VAR3,
VAR1 ,
VAR7,
VAR4,
VAR10 ,
VAR5
);
output VAR9;
input VAR2 ;
input VAR3;
input VAR1 ;
input VAR7;
input VAR4;
input VAR10 ;
input VAR5 ;
VAR8 VAR6 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn_2.v | 2,018 | module MODULE1 (
VAR2 ,
VAR4,
VAR6 ,
VAR3,
VAR7
);
input VAR2 ;
input VAR4;
output VAR6 ;
input VAR3;
input VAR7;
VAR1 VAR5 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR2 ,
VAR4,
VAR6
);
input VAR2 ;
input VAR4;
output VAR6 ;
supply1 VAR3;
supply0 VAR7;
VAR1 VAR5 (
... | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/contadorprueba/anteconmutador.v | 1,171 | module MODULE1 (
input clk,
input [7:0] VAR2,
input VAR5,
output reg [3:0] VAR7,
output reg [3:0] VAR3,
output reg [3:0] VAR1,
output reg VAR8,
output reg VAR10,
output reg VAR6
);
reg [7:0] VAR4;
reg VAR9;
begin
begin
begin
begin
begin
end
begin
begin
end
begin
begin
begin
begin
begin
begin | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_4.behavioral.pp.v | 3,792 | module MODULE1( VAR16, VAR28, VAR24, VAR11, VAR19, VAR20 );
input VAR16, VAR28, VAR24;
inout VAR19, VAR20;
output VAR11;
reg VAR3;
VAR1 VAR22(.VAR16(VAR16),.VAR28(VAR28),.VAR24(VAR24),.VAR11(VAR11),.VAR19(VAR19),.VAR20(VAR20),.VAR3(VAR3));
VAR1 VAR27(.VAR16(VAR16),.VAR28(VAR28),.VAR24(VAR24),.VAR11(VAR11),.VAR19(VAR19)... | apache-2.0 |
GSejas/Karatsuba_FPU | FPGA_FLOW/Cordic/CORDIC_FUNCIONAL_Viv/CORDIC_FUNCIONAL_Viv.srcs/sources_1/imports/Floating-Point-Unit-master/Coprocesador_CORDIC_RTL/sine_cosine_CORDIC/CORDIC_Arch2.v | 20,039 | module MODULE1 #(parameter VAR77 = 32, parameter VAR154 = 8, parameter VAR85 = 23, parameter VAR116=26, parameter VAR135 = 5)/*#(parameter VAR77 = 64, parameter VAR154 = 11, parameter VAR85 = 52, parameter VAR116 = 55, parameter VAR135 = 6) (
input wire clk, input wire rst, input wire VAR117, input wire VAR5, input wir... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | viterbi/z.v | 2,085 | module MODULE1();
integer VAR1;
reg clk;
reg VAR2[0:13];
always begin
clk = 0;
clk = 1; end
begin
begin | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/phy_dqs_iob.v | 12,410 | module MODULE1 #
(
parameter VAR4 = 100, parameter VAR52 = "VAR77", parameter VAR88 = 300.0, parameter VAR35 = "VAR90", parameter VAR33 = "VAR96", parameter VAR69 = "VAR79" )
(
input VAR98, input clk, input VAR2, input VAR131, input rst, input VAR136, input [4:0] VAR13, input [3:0] VAR56, input [3:0] VAR74, input [1:0]... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dff_nsr/sky130_fd_sc_lp__udp_dff_nsr.blackbox.v | 1,345 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR5,
VAR3,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR5;
input VAR3;
input VAR2 ;
endmodule | apache-2.0 |
mdsalman729/flexpret_project | src/uart/Reverse.v | 5,129 | module MODULE1(VAR3, VAR6);
parameter VAR2 = 32,
VAR1 = 1,
VAR7 = VAR2;
localparam VAR5 = VAR1 * VAR7;
input [VAR2-1:0] VAR3;
output [VAR2-1:0] VAR6;
genvar VAR8;
generate for(VAR8 = 0; VAR8 < VAR2; VAR8 = VAR8 + 1) begin:VAR4
assign VAR6[VAR8] = VAR3[((VAR7 - 1 - ((VAR8 % VAR5) / VAR1)) * VAR1) + ((VAR8 % VAR5) % VAR1... | bsd-3-clause |
OpenSoCPlus/hight_crypto_core | rtl/KEY_SCHED.v | 5,739 | module MODULE1(
VAR32 ,
clk ,
VAR26 ,
VAR13 ,
VAR23 ,
VAR31 ,
VAR27 ,
VAR3
);
input VAR32 ;
input clk ;
input[127:0] VAR26 ;
input VAR13 ;
input VAR23 ;
input[4:0] VAR31 ;
input VAR27 ;
output[31:0] VAR3 ;
reg[7:0] VAR15 ;
reg[7:0] VAR19 ;
reg[7:0] VAR14 ;
reg[7:0] VAR6 ;
wire[7:0] VAR29 ;
wire[7:0] VAR17 ;
wire[7:0] V... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/buf/sky130_fd_sc_ms__buf_1.v | 1,993 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR1,
VAR2,
VAR8 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR1;
input VAR2;
input VAR8 ;
input VAR3 ;
VAR6 VAR5 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR4,
VAR7
);
output VAR4;
input VAR7;
supply1 VAR1;
supply0 VAR2;... | apache-2.0 |
csturton/wirepatch | system/hardware/cores/ddr2/xilinx_ddr2.v | 6,290 | module MODULE1
(
input [31:0] VAR52,
input [1:0] VAR29,
input [2:0] VAR63,
input VAR48,
input [31:0] VAR53,
input [3:0] VAR25,
input VAR21,
input VAR57,
output VAR38,
output VAR14,
output VAR1,
output [31:0] VAR36,
input [31:0] VAR66,
input [1:0] VAR43,
input [2:0] VAR31,
input VAR32,
input [31:0] VAR20,
input [3:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb.pp.blackbox.v | 1,359 | module MODULE1 (
VAR4 ,
VAR9 ,
VAR3 ,
VAR8 ,
VAR2 ,
VAR1,
VAR5,
VAR7 ,
VAR6
);
output VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR5;
input VAR7 ;
input VAR6 ;
endmodule | apache-2.0 |
ILoveSpeccy/Aeon-Lite | cores/korvet/src/cpu/cpu8080.v | 62,443 | module MODULE2(addr, VAR75, VAR126, VAR47, VAR122, VAR59, VAR46, VAR85, VAR89, VAR70, reset, VAR96, VAR53);
output [15:0] addr;
input [7:0] VAR75;
output [7:0] VAR126;
output VAR47;
output VAR122;
output VAR59;
output VAR46;
input VAR85;
output VAR89;
input VAR70;
input reset;
input VAR96;
input VAR53;
reg VAR47;
reg V... | gpl-3.0 |
LSaldyt/qnp | output/vs/var17_multi.v | 1,380 | module MODULE1 (VAR13, VAR5, VAR4, VAR18, VAR19, VAR23, VAR3, VAR8, VAR10, VAR2, VAR6, VAR9, VAR17, VAR22, VAR21, VAR11, VAR1, valid);
input VAR13, VAR5, VAR4, VAR18, VAR19, VAR23, VAR3, VAR8, VAR10, VAR2, VAR6, VAR9, VAR17, VAR22, VAR21, VAR11, VAR1;
output valid;
wire [8:0] VAR14 = 9'd120;
wire [8:0] VAR12 = 9'd60;
w... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_power_hvc_wpadv2/sky130_fd_io__top_power_hvc_wpadv2.pp.blackbox.v | 1,903 | module MODULE1 (
VAR14 ,
VAR5 ,
VAR11 ,
VAR3 ,
VAR17 ,
VAR8,
VAR7 ,
VAR2 ,
VAR6 ,
VAR9 ,
VAR1 ,
VAR12 ,
VAR16 ,
VAR13 ,
VAR10 ,
VAR15 ,
VAR4
);
inout VAR14 ;
inout VAR5 ;
inout VAR11 ;
inout VAR3 ;
inout VAR17 ;
inout VAR8;
inout VAR7 ;
inout VAR2 ;
inout VAR6 ;
inout VAR9 ;
inout VAR1 ;
inout VAR12 ;
inout VAR16 ;
ino... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_cm16x40.v | 14,121 | module MODULE1(
dout, VAR22, VAR32, VAR47,
VAR11, din, VAR19, VAR44, VAR5, VAR12, VAR41, VAR23,
VAR40, VAR27, VAR18, VAR17, VAR51
);
input [15:0] VAR11 ; input [39:0] din; input VAR19; input VAR44; input [15:0] VAR5; input VAR12;
output [39:0] dout;
input VAR41; input [39:8] VAR23; output [15:0] VAR22 ;
output [15:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo.behavioral.pp.v | 2,043 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR10 ,
VAR2,
VAR5,
VAR9,
VAR15 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR10 ;
input VAR2;
input VAR5;
input VAR9;
input VAR15 ;
input VAR3 ;
wire VAR12 ;
wire VAR14 ;
wire VAR13;
nand VAR6 (VAR12 , VAR10, VAR4 );
nand VAR16 (VAR14 , VAR2, VAR12 );
VAR11 VAR7 (VAR13, VAR14, VAR5, VAR9... | apache-2.0 |
jairov4/accel-oil | solution_spartan3/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_9.v | 1,746 | module MODULE2(clk, VAR18, VAR21, VAR6, VAR11);
input clk;
input VAR18;
input[8 - 1 : 0] VAR21; input[6 - 1 : 0] VAR6; output[14 - 1 : 0] VAR11;
reg[8 - 1 : 0] VAR7;
reg[6 - 1 : 0] VAR19;
wire [14 - 1 : 0] VAR5;
reg[14 - 1 : 0] VAR22;
reg[14 - 1 : 0] VAR8;
reg[14 - 1 : 0] VAR20;
reg[14 - 1 : 0] VAR4;
reg[14 - 1 : 0] VA... | lgpl-3.0 |
tommythorn/yari | shared/rtl/soclib/blockram.v | 3,008 | module MODULE1
(input wire VAR14
,input wire rst
,output VAR25
,input [1:0] VAR18
,input [29:0] VAR17
,input VAR27
,input VAR23
,input [31:0] VAR21
,input [3:0] VAR9
,output [31:0] VAR7
,output reg [1:0] VAR6 = 0
);
parameter VAR28 = 2;
parameter VAR31 = 18; parameter VAR8 = "";
parameter VAR22 = 1 << VAR28;
wire sel =... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/CS_bak/synthesis/submodules/altera_up_video_scaler_multiply_width.v | 6,273 | module MODULE1 (
clk,
reset,
VAR7,
VAR2,
VAR1,
VAR18,
VAR15,
VAR13,
VAR14,
VAR10,
VAR6,
VAR20,
VAR8,
VAR19
);
parameter VAR17 = 15; parameter VAR11 = 15;
parameter VAR12 = 0;
input clk;
input reset;
input [VAR17: 0] VAR7;
input [VAR11: 0] VAR2;
input VAR1;
input VAR18;
input VAR15;
input VAR13;
output VAR14;
output reg... | mit |
acapola/opendev | songpa/logical_connection.v | 2,155 | module MODULE2 #(
parameter VAR8 = 32'hC1B269AE, parameter VAR5 = 10
)(
input wire [31:0] VAR13,
input wire [VAR5-1:0] VAR16,
output wire [VAR5-1:0] VAR14
);
MODULE1 #(
.VAR5(VAR5),
.VAR1(32),
.VAR12(8)
) VAR7 (
.VAR18(VAR13),
.VAR19(VAR8),
.VAR16(VAR16),
.VAR14(VAR14)
);
endmodule
module MODULE1 #(
parameter VAR5 = 10... | mit |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.srcs/sources_1/bd/block_design/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_addr_decoder.v | 11,632 | module MODULE1 #
(
parameter VAR43 = "none",
parameter integer VAR40 = 2, parameter integer VAR20 = 1, parameter integer VAR30 = 1, parameter integer VAR2 = 32, parameter integer VAR14 = 0, parameter integer VAR51 = 1, parameter integer VAR23 = 0, parameter [VAR40*VAR30*64-1:0] VAR42 = {VAR40*VAR30*64{1'b1}},
parameter... | gpl-3.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/div_uu.v | 5,689 | module MODULE1(clk, VAR15, VAR13, VAR21, VAR12, VAR16, VAR11, VAR19);
parameter VAR9 = 16;
parameter VAR4 = VAR9 /2;
input clk; input VAR15;
input [VAR9 -1:0] VAR13; input [VAR4 -1:0] VAR21; output [VAR4 -1:0] VAR12; output [VAR4 -1:0] VAR16; output VAR11;
output VAR19;
reg [VAR4-1:0] VAR12;
reg [VAR4-1:0] VAR16;
reg V... | gpl-3.0 |
cospan/prometheus_fpga | rtl/slave_fifo/prometheus_fx3_loopback.v | 6,550 | module MODULE1(
input VAR30,
input VAR40,
input VAR24,
input VAR33,
input VAR28,
input VAR12,
input VAR9,
input [31:0]VAR14,
output VAR6,
output VAR35,
output VAR11,
output VAR34,
output [31:0] VAR42
);
reg [1:0] VAR1;
reg VAR7;
wire [31:0] VAR36;
reg VAR43;
reg VAR41;
reg VAR21;
reg VAR23;
reg [3:0]VAR37;
reg [3:0]VAR... | gpl-3.0 |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_ssw_hp.v | 8,657 | module MODULE1(
VAR130,
VAR127,
VAR35,
VAR78,
VAR124,
VAR44,
VAR157,
VAR2,
VAR66,
VAR12,
VAR100,
VAR142,
VAR121,
VAR56,
VAR104,
VAR95,
VAR109,
VAR26,
VAR149,
VAR24,
VAR159,
VAR34,
VAR103,
VAR55,
VAR117,
VAR13,
VAR67,
VAR25,
VAR20,
VAR18,
VAR131,
VAR105,
VAR107,
VAR98,
VAR134,
VAR102,
VAR42,
VAR50,
VAR75,
VAR114,
VAR146... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap.behavioral.pp.v | 1,172 | module MODULE1 (
VAR1,
VAR2,
VAR3 ,
VAR4
);
input VAR1;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
Tommydag/CAN-Bus-Controller | Ttx_container.v | 1,973 | module MODULE1(
output reg VAR18,
output VAR11,
input VAR9,
input VAR20,
input[10:0] address,
input clk,
input VAR13,
input rst,
input [63:0] VAR8,
input VAR5
);
parameter VAR10 = 2'h0, VAR14 = 2'h1, VAR7 = 2'h2;
assign VAR2 =1;
reg VAR15 = 0;
reg[1:0] VAR16=0, VAR6=0, VAR4 = 0;
reg[31:0] VAR1 = 0;
wire VAR3;
VAR19 VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfxtp/sky130_fd_sc_hdll__sdfxtp_1.v | 2,361 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR9,
VAR4,
VAR5 ,
VAR2
);
output VAR11 ;
input VAR10 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR9;
input VAR4;
input VAR5 ;
input VAR2 ;
VAR7 VAR3 (
.VAR11(VAR11),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/up_xfer_status.v | 4,651 | module MODULE1 #(
parameter VAR18 = 8) (
input VAR7,
input VAR19,
output [(VAR18-1):0] VAR5,
input VAR3,
input VAR16,
input [(VAR18-1):0] VAR15);
reg VAR13 = 'd0;
reg VAR8 = 'd0;
reg VAR17 = 'd0;
reg [ 5:0] VAR21 = 'd0;
reg VAR6 = 'd0;
reg [(VAR18-1):0] VAR2 = 'd0;
reg [(VAR18-1):0] VAR12 = 'd0;
reg VAR4 = 'd0;
reg VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22ai/sky130_fd_sc_ms__o22ai.behavioral.pp.v | 2,159 | module MODULE1 (
VAR15 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR12 ,
VAR17,
VAR9,
VAR4 ,
VAR8
);
output VAR15 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR12 ;
input VAR17;
input VAR9;
input VAR4 ;
input VAR8 ;
wire VAR19 ;
wire VAR6 ;
wire VAR14 ;
wire VAR13;
nor VAR7 (VAR19 , VAR3, VAR12 );
nor VAR16 (VAR6 , VAR1, VAR2 );
or V... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_mm_interconnect_2.v | 56,935 | module MODULE1 (
input wire VAR249, input wire VAR96, input wire VAR248, input wire [31:0] VAR124, output wire VAR243, input wire [4:0] VAR253, input wire [31:0] VAR181, input wire VAR225, output wire [255:0] VAR342, output wire VAR143, input wire VAR21, input wire [255:0] VAR130, output wire [26:0] VAR266, output wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxbp/sky130_fd_sc_hd__sedfxbp.pp.symbol.v | 1,518 | module MODULE1 (
input VAR6 ,
output VAR7 ,
output VAR3 ,
input VAR8 ,
input VAR9 ,
input VAR2 ,
input VAR1 ,
input VAR4 ,
input VAR5,
input VAR10,
input VAR11
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv.pp.blackbox.v | 1,225 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5,
VAR4,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR1 ;
input VAR5;
input VAR4;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de3d/der_reg_15.v | 6,456 | module MODULE1
(
input VAR12, VAR19, input VAR7, input [12:0] VAR48, input [31:0] VAR6, input [31:0] VAR30, input [11:0] VAR18, input [11:0] VAR24, input [3:0] VAR44, input [3:0] VAR9, input [4:0] VAR26, input VAR2, input [1:0] VAR23, input [2:0] VAR49, input [31:0] VAR41, input [31:0] VAR35, input [3:0] VAR27, input [... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/image_filter_CONTROL_BUS_if.v | 8,779 | module MODULE1
VAR61 = 5,
VAR5 = 32
)(
input wire VAR17,
input wire VAR33,
input wire [VAR61-1:0] VAR47,
input wire VAR31,
output wire VAR58,
input wire [VAR5-1:0] VAR19,
input wire [VAR5/8-1:0] VAR2,
input wire VAR24,
output wire VAR28,
output wire [1:0] VAR11,
output wire VAR1,
input wire VAR14,
input wire [VAR61-1:0... | gpl-3.0 |
ZiCog/xoro | rtl/prng.v | 1,054 | module MODULE1 (
input wire clk,
input wire VAR5,
input wire enable,
input wire VAR9,
output wire VAR2,
input wire VAR1,
input wire [3:0] VAR8,
input wire [31:0] VAR11,
input wire [31:0] VAR6,
output wire [31:0] VAR12
);
wire [63:0] VAR14;
reg VAR3;
reg VAR7;
reg [31:0] VAR13;
VAR4 MODULE1(
.VAR10(VAR5),
.clk(VAR3),
.o... | mit |
asicguy/gplgpu | hdl/mc_graph/mc_crt.v | 7,000 | module MODULE1
(
input VAR18,
input VAR32,
input VAR23,
input VAR20,
input VAR14,
input VAR11,
input [20:0] VAR24,
input [4:0] VAR34,
input [11:0] VAR30,
input [9:0] VAR4,
input [11:0] VAR29,
output reg VAR6,
output reg VAR25,
output reg [4:0] VAR1,
output reg [20:0] VAR26
);
reg VAR15;
reg [20:0] VAR7;
reg [11:0] VAR2... | gpl-3.0 |
lvd2/ngs | fpga/obsolete/fpgaD_release/main.v | 9,556 | module MODULE1(
VAR30, VAR112,
VAR119, VAR11,
VAR129,
VAR155, VAR89,
VAR82, VAR8, VAR157, VAR128, VAR54, VAR27, VAR148, VAR86, VAR104, VAR61,
VAR55, VAR64, VAR42, VAR15, VAR29, VAR44, VAR147, VAR21, VAR80, VAR91, VAR43, VAR7,
VAR106, VAR40, VAR39, VAR77, VAR20, VAR125, VAR38, VAR116, VAR53, VAR122, VAR111, VAR83, VAR14... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gtp_pipe_drp.v | 11,773 | module MODULE1 #
(
parameter VAR14 = 2'd1, parameter VAR11 = 1'd0
)
(
input VAR27,
input VAR28,
input VAR12,
input VAR32,
input [15:0] VAR20,
input VAR39,
output [ 8:0] VAR31,
output VAR3,
output [15:0] VAR15,
output VAR13,
output VAR1,
output [ 2:0] VAR22
);
reg VAR34;
reg VAR25;
reg [15:0] VAR38;
reg VAR26;
reg VAR18... | gpl-3.0 |
OSCES/OSCES | src/bsp/fpga/src/MemMux.v | 1,580 | module MODULE1
(
input VAR12,
inout wire [ 7:0] VAR11 ,
input wire [18:0] VAR15 ,
input wire VAR14 ,
input wire VAR21 ,
input wire VAR19 ,
output wire [ 7:0] VAR6 ,
input wire [18:0] VAR9 ,
input wire VAR2 ,
input wire VAR20 ,
input wire VAR4 ,
inout wire [ 7:0] VAR5,
output wire [18:0] VAR13,
output wire VAR16 ,
outpu... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9250/axi_ad9250.v | 9,716 | module MODULE1 (
VAR57,
VAR17,
VAR79,
VAR2,
VAR109,
VAR69,
VAR28,
VAR62,
VAR50,
VAR5,
VAR74,
VAR36,
VAR110,
VAR6,
VAR88,
VAR45,
VAR91,
VAR15,
VAR53,
VAR96,
VAR35,
VAR101,
VAR59,
VAR32,
VAR9,
VAR37,
VAR89,
VAR39,
VAR108,
VAR13,
VAR18,
VAR73);
parameter VAR55 = 0;
parameter VAR66 = 0;
parameter VAR46 = "VAR44";
input VAR... | gpl-3.0 |
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