repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
alan4186/Hardware-CNN | DE2_115_CAMERA/v/SEG7_LUT_8.v | 2,219 | module MODULE1 ( VAR18,VAR12,VAR2,VAR10,VAR9,VAR8,VAR17,VAR1,VAR15 );
input [31:0] VAR15;
output [6:0] VAR18,VAR12,VAR2,VAR10,VAR9,VAR8,VAR17,VAR1;
VAR5 VAR3 ( VAR18,VAR15[3:0] );
VAR5 VAR13 ( VAR12,VAR15[7:4] );
VAR5 VAR4 ( VAR2,VAR15[11:8] );
VAR5 VAR14 ( VAR10,VAR15[15:12] );
VAR5 VAR7 ( VAR9,VAR15[19:16] );
VAR5 VA... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_us_0/synth/design_1_auto_us_0.v | 16,097 | module MODULE1 (
VAR45,
VAR27,
VAR5,
VAR6,
VAR9,
VAR69,
VAR94,
VAR47,
VAR40,
VAR57,
VAR30,
VAR26,
VAR54,
VAR22,
VAR43,
VAR18,
VAR87,
VAR32,
VAR25,
VAR50,
VAR56,
VAR72,
VAR19,
VAR46,
VAR29,
VAR35,
VAR81,
VAR80,
VAR91,
VAR60,
VAR37,
VAR70,
VAR12,
VAR75,
VAR85,
VAR4,
VAR31,
VAR64,
VAR83,
VAR48,
VAR39,
VAR93,
VAR11,
VAR76,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.blackbox.v | 1,224 | module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | Sobel/ip/Sobel/vfabric_multiport_counter.v | 7,362 | module MODULE1(
VAR51, VAR35, VAR13, VAR50,
VAR44, VAR47, VAR49, VAR58,
VAR39, VAR5,
VAR59, VAR70, VAR78,
VAR74, VAR62, VAR61,
VAR31, VAR53, VAR16,
VAR46, VAR21, VAR54,
VAR48, VAR27, VAR68,
VAR32, VAR8, VAR63,
VAR22, VAR65, VAR69,
VAR33, VAR77, VAR23,
VAR15, VAR42, VAR12,
VAR14, VAR67, VAR20,
VAR34, VAR2, VAR71
);
para... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.blackbox.v | 1,222 | module MODULE1 (
VAR1
);
input VAR1;
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,028 | module MODULE1
(
VAR15,
VAR19,
VAR18) ;
input [0:0] VAR15;
output [0:0] VAR19;
output [0:0] VAR18;
wire [0:0] VAR3;
wire [0:0] VAR6;
wire [0:0] VAR31;
wire [0:0] VAR32;
wire [0:0] VAR30;
wire [0:0] VAR2;
wire [0:0] VAR27;
wire [0:0] VAR24;
wire [0:0] VAR26;
wire [0:0] VAR8;
VAR5 VAR17
(
.VAR23(VAR2),
.VAR28(VAR3[0:0]),... | mit |
kmod/processor | ipcore_dir/dcm.v | 5,473 | module MODULE1
( input VAR44,
output VAR18
);
VAR2 VAR42
(.VAR15 (VAR1),
.VAR28 (VAR44));
wire VAR14;
wire VAR9;
wire VAR38;
wire VAR37;
VAR20
.VAR46 (20),
.VAR33 (2),
.VAR45 ("VAR21"),
.VAR16 (10.0),
.VAR8 ("VAR40"),
.VAR23 ("1X"),
.VAR11 ("VAR19"),
.VAR39 (0),
.VAR7 ("VAR21"))
VAR5
(.VAR44 (VAR1),
.VAR10 (VAR9),
.VAR... | mit |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_img_1_data_stream_2_V.v | 3,017 | module MODULE1 (
clk,
VAR11,
VAR26,
VAR27,
VAR6);
parameter VAR8 = 32'd8;
parameter VAR18 = 32'd1;
parameter VAR19 = 32'd2;
input clk;
input [VAR8-1:0] VAR11;
input VAR26;
input [VAR18-1:0] VAR27;
output [VAR8-1:0] VAR6;
reg[VAR8-1:0] VAR24 [0:VAR19-1];
integer VAR21;
always @ (posedge clk)
begin
if (VAR26)
begin
for (... | gpl-3.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/qlf_k6n10/ffs_map.v | 4,108 | module \VAR30 (VAR7, VAR8, VAR11);
input VAR7;
input VAR8;
output VAR11;
parameter VAR6 = 1'VAR13;
VAR4 VAR33 (.VAR11(VAR11), .VAR7(VAR7), .VAR8(VAR8));
endmodule
module \VAR31 (VAR7, VAR8, VAR2, VAR11);
input VAR7;
input VAR8;
input VAR2;
output VAR11;
parameter VAR6 = 1'VAR13;
VAR29 VAR33 (.VAR11(VAR11), .VAR7(VAR7),... | apache-2.0 |
antmicro/yosys | passes/sat/example.v | 1,190 | module MODULE4(VAR7, VAR8);
input [15:0] VAR7;
output VAR8;
wire VAR12 = VAR7 > 12345;
wire VAR17 = VAR7 < 12345;
assign VAR8 = !VAR12 && !VAR17;
endmodule
module MODULE3(VAR7, VAR8);
input [3:0] VAR7;
output VAR8;
reg [1:0] VAR20, VAR19;
always @* begin
casex (VAR7)
16'VAR3:
VAR20 <= 1;
16'VAR13:
VAR20 <= 2;
16'VAR6:
... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.behavioral.pp.v | 2,321 | module MODULE1 (
VAR15 ,
VAR3 ,
VAR11 ,
VAR9 ,
VAR5 ,
VAR12,
VAR6,
VAR8 ,
VAR20
);
output VAR15 ;
output VAR3 ;
input VAR11 ;
input VAR9 ;
input VAR5 ;
input VAR12;
input VAR6;
input VAR8 ;
input VAR20 ;
wire VAR2 ;
reg VAR18 ;
wire VAR21 ;
wire VAR19 ;
wire VAR14;
wire VAR10 ;
wire VAR22 ;
wire VAR4 ;
VAR1 VAR16 (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221oi/sky130_fd_sc_lp__a221oi.blackbox.v | 1,403 | module MODULE1 (
VAR9 ,
VAR4,
VAR10,
VAR6,
VAR8,
VAR2
);
output VAR9 ;
input VAR4;
input VAR10;
input VAR6;
input VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi_2.v | 2,261 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR1,
VAR8,
VAR9 ,
VAR5
);
output VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR1;
input VAR8;
input VAR9 ;
input VAR5 ;
VAR10 VAR3 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxbp/sky130_fd_sc_hvl__sdfxbp.behavioral.v | 2,389 | module MODULE1 (
VAR19 ,
VAR8,
VAR11,
VAR10 ,
VAR4,
VAR14
);
output VAR19 ;
output VAR8;
input VAR11;
input VAR10 ;
input VAR4;
input VAR14;
supply1 VAR15;
supply0 VAR7;
supply1 VAR12 ;
supply0 VAR18 ;
wire VAR26 ;
wire VAR3 ;
reg VAR13 ;
wire VAR1 ;
wire VAR23 ;
wire VAR25 ;
wire VAR2 ;
wire VAR17;
wire VAR22;
wire VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o.behavioral.v | 1,585 | module MODULE1 (
VAR3 ,
VAR15,
VAR6,
VAR2,
VAR5,
VAR10
);
output VAR3 ;
input VAR15;
input VAR6;
input VAR2;
input VAR5;
input VAR10;
supply1 VAR11;
supply0 VAR12;
supply1 VAR13 ;
supply0 VAR8 ;
wire VAR4 ;
wire VAR14;
and VAR1 (VAR4 , VAR15, VAR6 );
or VAR9 (VAR14, VAR5, VAR2, VAR4, VAR10);
buf VAR7 (VAR3 , VAR14 );
e... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_4.v | 1,995 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR7,
VAR1,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR7;
input VAR1;
input VAR3 ;
input VAR8 ;
VAR6 VAR2 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
supply1 VAR7;
supply0 VAR1;... | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/xor_32.v | 1,115 | module MODULE1(
input [31:0] VAR3,
input [31:0] VAR4,
output reg [31:0] VAR2,
input VAR1
);
always @(posedge VAR1)
begin
VAR2 <= VAR3 ^ VAR4;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv.behavioral.pp.v | 1,748 | module MODULE1 (
VAR11 ,
VAR12 ,
VAR4,
VAR7,
VAR5 ,
VAR9
);
output VAR11 ;
input VAR12 ;
input VAR4;
input VAR7;
input VAR5 ;
input VAR9 ;
wire VAR8 ;
wire VAR6;
not VAR2 (VAR8 , VAR12 );
VAR10 VAR1 (VAR6, VAR8, VAR4, VAR7);
buf VAR3 (VAR11 , VAR6 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu9t5v0__latrnq_4.behavioral.pp.v | 2,914 | module MODULE1( VAR24, VAR1, VAR3, VAR20, VAR13, VAR27 );
input VAR3, VAR24, VAR1;
inout VAR13, VAR27;
output VAR20;
reg VAR10;
VAR18 VAR4(.VAR24(VAR24),.VAR1(VAR1),.VAR3(VAR3),.VAR20(VAR20),.VAR13(VAR13),.VAR27(VAR27),.VAR10(VAR10));
VAR18 VAR22(.VAR24(VAR24),.VAR1(VAR1),.VAR3(VAR3),.VAR20(VAR20),.VAR13(VAR13),.VAR27(... | apache-2.0 |
slongfield/StereoCensus | verilog/lib/fifo.v | 1,392 | module MODULE1#(
parameter VAR4=1,
parameter VAR3=1
) (
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR6,
output wire [VAR4-1:0] VAR2
);
reg [VAR4-1:0] VAR9[VAR3];
assign VAR2 = VAR9[VAR3-1];
VAR10#(VAR4) VAR8(clk, rst, VAR6, VAR9[0]);
genvar VAR7;
generate
for (VAR7 = 0; VAR7 < VAR3-1; VAR7++) begin : VAR5
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.pp.symbol.v | 1,352 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR2 ,
output VAR7 ,
input VAR8 ,
input VAR6,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
ultraembedded/riscv | top_cache_axi/src_v/riscv_top.v | 9,345 | module MODULE1
parameter VAR161 = 0
,parameter VAR8 = 0
,parameter VAR143 = 32'hffffffff
)
(
input VAR32
,input VAR37
,input VAR27
,input VAR10
,input VAR60
,input [ 1:0] VAR135
,input [ 3:0] VAR98
,input VAR120
,input VAR130
,input [ 31:0] VAR126
,input [ 1:0] VAR127
,input [ 3:0] VAR48
,input VAR136
,input VAR106
,in... | bsd-3-clause |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_hdmi_tx.v | 12,618 | module MODULE1 (
VAR7,
VAR16,
VAR3,
VAR34,
VAR1,
VAR31,
VAR65,
VAR22,
VAR71,
VAR12,
VAR42,
VAR69,
VAR78,
VAR27,
VAR41,
VAR21,
VAR80,
VAR9,
VAR52,
VAR64,
VAR67,
VAR2,
VAR19,
VAR37,
VAR32,
VAR11,
VAR40,
VAR5,
VAR45,
VAR48,
VAR50,
VAR35,
VAR46,
VAR61,
VAR60);
localparam VAR87 = 32'h00040063;
parameter VAR53 = 0;
input VAR... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_thrfsm.v | 7,178 | module MODULE1(
VAR34, VAR28,
VAR1, VAR16, VAR20, VAR4, VAR6, VAR15,
VAR24, VAR23, VAR22, VAR17, VAR33,
VAR2, VAR3, clk, VAR30, VAR13, reset
);
input VAR1, VAR16, VAR20, VAR4, VAR6, VAR15, VAR2,
VAR24, VAR22,
VAR23,
VAR17;
input VAR33, VAR3;
input clk, VAR30, VAR13, reset;
output VAR34;
output [4:0] VAR28;
reg [4:0] VA... | gpl-2.0 |
ILoveSpeccy/Aeon-Lite | cores/atari800xl/src/components/hq_dac.v | 3,053 | module MODULE1
(
input reset,
input clk,
input VAR1,
input [19:0] VAR12,
output reg VAR14
);
wire [23:0] VAR10;
wire [23:0] VAR3;
wire [23:0] VAR15;
reg [23:0] VAR9;
assign VAR10 = { {4{VAR12[19]}}, VAR12 };
assign VAR3 = VAR10 - VAR2;
assign VAR15 = { {3{VAR3[23]}}, VAR3[22:2] } + VAR9;
always @(posedge reset or posed... | gpl-3.0 |
Alexoner/RiscCPU | cputop.v | 6,720 | module MODULE1(
reg VAR4,VAR8;
reg [(3*8):0] VAR12; reg [12:0] VAR10,VAR11;
wire [7:0] VAR18;
wire [12:0] addr;
wire rd,wr,VAR16,VAR14,VAR7;
VAR15 VAR5 (.clk(VAR8),.reset(VAR4),.VAR16(VAR16),.rd(rd),
.wr(wr),.addr(addr),.VAR18(VAR18));
VAR3 VAR13 (.addr(addr[9:0]),.read(rd),.write(wr),.VAR1(VAR14),.VAR18(VAR18));
VAR2... | gpl-2.0 |
kyzhai/NUNY | src/hardware/exam_bb.v | 4,966 | module MODULE1 (
address,
VAR2,
VAR1);
input [11:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2.behavioral.pp.v | 1,792 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR7 ,
VAR13,
VAR6,
VAR10 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR7 ;
input VAR13;
input VAR6;
input VAR10 ;
input VAR3 ;
wire VAR11 ;
wire VAR4;
nand VAR8 (VAR11 , VAR7, VAR1 );
VAR5 VAR9 (VAR4, VAR11, VAR13, VAR6);
buf VAR12 (VAR2 , VAR4 );
endmodule | apache-2.0 |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_auto_us_1/synth/triangle_intersect_auto_us_1.v | 10,521 | module MODULE1 (
VAR37,
VAR91,
VAR63,
VAR85,
VAR27,
VAR73,
VAR22,
VAR100,
VAR78,
VAR15,
VAR54,
VAR67,
VAR33,
VAR102,
VAR77,
VAR55,
VAR28,
VAR18,
VAR71,
VAR34,
VAR96,
VAR98,
VAR52,
VAR64,
VAR75,
VAR43,
VAR87,
VAR31,
VAR41,
VAR8,
VAR17,
VAR7,
VAR72,
VAR36,
VAR95,
VAR59,
VAR92,
VAR56,
VAR60,
VAR29
);
input wire VAR37;
inp... | mit |
binary-logic/vj-uart | rtl/DE0_Comm.v | 2,456 | module MODULE1(
input VAR12,
input VAR14,
output [7:0] VAR8
);
wire VAR3, VAR6;
wire VAR13;
assign VAR8 = {7'b0,VAR13};
VAR16 VAR11 (
.VAR7 ( VAR12 ),
.VAR4 ( VAR3 ),
.VAR14( VAR14 ),
.VAR14(),
.VAR9 ( )
);
reset reset(
.VAR17( VAR3 ),
.VAR15( VAR6 )
);
VAR13 hb(
.VAR17( VAR3 ),
.VAR2( VAR6 ),
.VAR5( VAR13 )
);
VAR10 V... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/crt_misc.v | 5,182 | module MODULE1
(
input VAR22,
input VAR16,
input VAR13,
input VAR11,
input VAR4, input VAR6, input VAR14, input [15:0] VAR18, input [5:0] VAR9, input [7:0] VAR1, input VAR27, input VAR29, input VAR10, input VAR8, input VAR2, input [15:0] VAR23,
output [7:0] VAR17,
output [7:0] VAR5,
output [7:0] VAR26,
output reg [7:0]... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_52.v | 32,962 | module MODULE5 (
clk,
reset,
VAR32,
VAR48,
VAR278,
VAR294,
VAR183
);
parameter VAR119 = 18;
parameter VAR164 = 52;
parameter VAR233 = 26;
localparam VAR96 = 53;
input clk;
input reset;
input VAR32;
input VAR48;
input [VAR119-1:0] VAR278; output VAR294;
output [VAR119-1:0] VAR183;
localparam VAR201 = 18; localparam VAR2... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9680/axi_ad9680_pnmon.v | 9,954 | module MODULE1 (
VAR7,
VAR4,
VAR8,
VAR13,
VAR11);
input VAR7;
input [55:0] VAR4;
output VAR8;
output VAR13;
input [ 3:0] VAR11;
reg [55:0] VAR10 = 'd0;
reg [55:0] VAR5 = 'd0;
wire [55:0] VAR16;
function [55:0] VAR9;
input [55:0] din;
reg [55:0] dout;
begin
dout[55] = din[22] ^ din[17];
dout[54] = din[21] ^ din[16];
dou... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4_2.v | 2,258 | module MODULE2 (
VAR10 ,
VAR3 ,
VAR9 ,
VAR4 ,
VAR7 ,
VAR6,
VAR8,
VAR5 ,
VAR2
);
output VAR10 ;
input VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR8;
input VAR5 ;
input VAR2 ;
VAR11 VAR1 (
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.symbol.v | 1,308 | module MODULE1 (
input VAR5,
input VAR8,
input VAR6,
output VAR2
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.v | 2,020 | module MODULE1 (
VAR7,
VAR6 ,
VAR2 ,
VAR1 ,
VAR3
);
input VAR7;
input VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
VAR5 VAR4 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE1 ();
supply1 VAR7;
supply1 VAR6 ;
supply0 VAR2 ;
supply1 VAR1 ;
supply0 VAR3 ;
VAR5 VAR4 ();
endmodul... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2_1.v | 1,990 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR1 ,
VAR5,
VAR2
);
output VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR5;
input VAR2;
VAR4 VAR6 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR3,
VAR7,
VAR1
);
output VAR3;
input VAR7;
input VAR1;
supply1 VAR5;
supply0 VAR2;
VAR4 VAR6 (
.... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361.v | 13,664 | module MODULE1 (
VAR118,
VAR55,
VAR96,
VAR155,
VAR91,
VAR153,
VAR101,
VAR45,
VAR71,
VAR188,
VAR173,
VAR177,
VAR114,
clk,
VAR147,
VAR174,
VAR1,
VAR31,
VAR54,
VAR79,
VAR58,
VAR42,
VAR17,
VAR189,
VAR157,
VAR116,
VAR144,
VAR27,
VAR95,
VAR14,
VAR158,
VAR73,
VAR3,
VAR150,
VAR50,
VAR123,
VAR10,
VAR149,
VAR34,
VAR6,
VAR36,
VAR... | mit |
545/Atari7800 | core/ag_6502/trunk/fighter/ag_keyb.v | 8,054 | module MODULE4(input clk, input in, output reg out);
always @(posedge clk) begin
out <= in;
end
endmodule
module MODULE1(VAR4, VAR8, VAR21, VAR2, VAR23, VAR18);
input wire VAR4, VAR8;
output reg[7:0] VAR21 = 0;
output reg VAR2 = 0, VAR23 = 0, VAR18 = 0;
reg[10:0] VAR9 = 11'b11111111111;
wire[10:0] VAR3 = {VAR8, VAR9[10... | gpl-2.0 |
lloves/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_COUNT_TO_64.v | 2,648 | module MODULE1(clk, rst, VAR3, VAR1, VAR2);
input clk, rst, VAR3, VAR1;
output [5:0] VAR2;
wire [5:0] VAR4;
reg [5:0] VAR2;
always@(posedge clk or posedge rst)
begin
if(rst == 1'b1)
VAR2 = 6'h00;
end
else
begin
case({VAR3,VAR1})
2'b00: VAR2 = VAR4;
2'b01: VAR2 = VAR4;
2'b10: VAR2 = VAR4 - 1;
2'b11: VAR2 = VAR4 + 1;
def... | bsd-2-clause |
peteasa/oh | src/common/hdl/oh_8b10b_decode.v | 5,782 | module MODULE1(
input clk, input VAR15,
input [9:0] VAR20,
output reg VAR18, output reg [7:0] VAR11, output reg VAR3, output reg VAR12 );
wire [5:0] VAR9;
wire [3:0] VAR4;
reg [9:0] VAR10;
reg [4:0] VAR2;
reg [2:0] VAR19;
reg VAR1;
reg VAR8;
wire [2:0] VAR22;
wire [2:0] VAR21;
wire [7:0] VAR13;
wire VAR25;
wire VAR16;
... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_tx/MAC_tx_addr_add.v | 5,860 | module MODULE1 (
VAR4 ,
VAR24 ,
VAR1 ,
VAR22 ,
VAR12 ,
VAR3 ,
VAR6 ,
VAR23
);
input VAR4 ;
input VAR24 ;
input VAR22 ;
input VAR1 ;
output [7:0] VAR12 ;
input [7:0] VAR3 ;
input [2:0] VAR6 ;
input VAR23 ;
reg [2:0] VAR5;
wire[2:0] VAR2;
wire[7:0] din;
wire[7:0] dout;
wire VAR16;
reg VAR15;
reg VAR17;
always @ (posedge ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.blackbox.v | 1,344 | module MODULE1 (
VAR5 ,
VAR7,
VAR4 ,
VAR9,
VAR6
);
output VAR5 ;
input VAR7;
input VAR4 ;
input VAR9;
input VAR6;
supply1 VAR8;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/fei4_rx/receiver_logic.v | 7,247 | module MODULE1 #(
parameter VAR96 = 10
) (
input wire VAR68,
input wire VAR56,
input wire VAR30,
input wire VAR25,
input wire VAR48,
input wire VAR31,
input wire read,
output wire [23:0] VAR60,
output wire VAR88,
output reg VAR14,
output wire VAR24,
output reg [7:0] VAR64,
output reg [7:0] VAR90,
output reg [15:0] VAR5... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.behavioral.pp.v | 2,509 | module MODULE1 (
VAR10 ,
VAR21 ,
VAR11 ,
VAR20 ,
VAR14 ,
VAR3 ,
VAR8,
VAR7,
VAR1 ,
VAR6
);
output VAR10 ;
output VAR21 ;
input VAR11 ;
input VAR20 ;
input VAR14 ;
input VAR3 ;
input VAR8;
input VAR7;
input VAR1 ;
input VAR6 ;
wire VAR15 ;
wire VAR4 ;
reg VAR18 ;
wire VAR22 ;
wire VAR2;
wire VAR16;
wire VAR23;
wire VAR2... | apache-2.0 |
campsandrew/ECE-474A-Program-1 | Modules/CIRCUIT4.v | 1,107 | module MODULE1(VAR22, VAR16, VAR17, VAR13, VAR12, VAR10, VAR14, VAR2, VAR20, VAR45, VAR38, VAR5, VAR35, VAR49, VAR26, VAR44, VAR43, VAR37, final);
input VAR43, VAR37;
input [7:0] VAR22, VAR16, VAR17, VAR13, VAR12, VAR10, VAR14, VAR2, VAR20, VAR45, VAR38, VAR5, VAR35, VAR49, VAR26, VAR44;
output [31:0] final;
wire [31:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4bb/sky130_fd_sc_hs__nand4bb.pp.symbol.v | 1,307 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR7 ,
input VAR1 ,
output VAR2 ,
input VAR3,
input VAR5
);
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_system_ila_0_0/zynq_design_1_system_ila_0_0_stub.v | 2,521 | module MODULE1(clk, VAR12, VAR17,
VAR16, VAR5, VAR11, VAR10,
VAR2, VAR13, VAR14, VAR7,
VAR3, VAR15, VAR9, VAR1,
VAR8, VAR4, VAR6, VAR18)
;
input clk;
input [8:0]VAR12;
input VAR17;
input VAR16;
input [31:0]VAR5;
input [3:0]VAR11;
input VAR10;
input VAR2;
input [1:0]VAR13;
input VAR14;
input VAR7;
input [8:0]VAR3;
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.functional.pp.v | 1,998 | module MODULE1 (
VAR16 ,
VAR8 ,
VAR4 ,
VAR5 ,
VAR2,
VAR13,
VAR6 ,
VAR14
);
output VAR16 ;
input VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR13;
input VAR6 ;
input VAR14 ;
wire VAR11 ;
wire VAR15 ;
wire VAR3;
or VAR1 (VAR11 , VAR4, VAR8 );
and VAR9 (VAR15 , VAR11, VAR5 );
VAR7 VAR12 (VAR3, VAR15, VAR2, VAR13);... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core.v | 4,788 | module MODULE1 (
VAR3, VAR11, VAR18, VAR21, VAR8, VAR9,
VAR10, VAR2, VAR4, VAR1, VAR25, VAR13,
VAR27, VAR15, VAR16, VAR12, VAR20, VAR24,
VAR6, VAR7, VAR14
);
parameter VAR19 = 32;
parameter VAR17 = 32;
parameter VAR5 = 1;
parameter VAR22 = 1;
output [VAR17-1:2] VAR13; output [31:0] VAR25; output [3:0] VAR1; output VAR4... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2/sky130_fd_sc_lp__or2_1.v | 2,075 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8 ,
VAR6,
VAR7,
VAR9 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR6;
input VAR7;
input VAR9 ;
input VAR4 ;
VAR2 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR1,
VAR5,
VAR8
);
output VAR1;
... | apache-2.0 |
vipinkmenon/scas | hw/fpga/ipcore_dir/track_fifo.v | 13,827 | module MODULE1(
VAR266,
VAR228,
VAR286,
VAR85,
VAR410,
VAR329,
VAR217,
VAR374
);
input VAR266;
input VAR228;
input VAR286;
output VAR85;
input [7 : 0] VAR410;
output VAR329;
input VAR217;
output [7 : 0] VAR374;
VAR96 #(
.VAR160(0),
.VAR389(2),
.VAR99(0),
.VAR154(0),
.VAR310(0),
.VAR318(0),
.VAR151(0),
.VAR340(32),
.VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.behavioral.pp.v | 1,164 | module MODULE1( VAR4, VAR5, VAR1, VAR6 );
input VAR4;
inout VAR1, VAR6;
output VAR5;
VAR3 VAR2(.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6));
VAR3 VAR7(.VAR4(VAR4),.VAR5(VAR5),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b.symbol.v | 1,325 | module MODULE1 (
input VAR6 ,
input VAR4 ,
input VAR1 ,
input VAR7,
output VAR5
);
supply1 VAR9;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/bell_bb.v | 4,974 | module MODULE1 (
address,
VAR1,
VAR2);
input [14:0] address;
input VAR1;
output [15:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/tart_dcm.v | 10,461 | module MODULE1
(
input VAR55, input VAR16,
output VAR23, output VAR46, output VAR43, output VAR27, output VAR19, output VAR18 );
wire [7:0] VAR54;
wire VAR37, VAR51, VAR42, VAR41, VAR59, VAR22, VAR9;
wire VAR29;
wire VAR6;
wire VAR28;
assign VAR19 = VAR45 && VAR11;
VAR30
) VAR39
( .VAR53(VAR55),
.VAR56(VAR37)
);
VAR58
... | lgpl-3.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/36950b996c10e220/design_1_processing_system7_0_0_stub.v | 5,443 | module MODULE1(VAR55, VAR73, VAR65, VAR5, VAR58,
VAR6, VAR46, VAR57, VAR31,
VAR9, VAR19, VAR36, VAR14,
VAR23, VAR10, VAR54, VAR63, VAR25,
VAR72, VAR26, VAR70, VAR3, VAR47,
VAR42, VAR2, VAR61, VAR15, VAR37,
VAR7, VAR43, VAR68, VAR66, VAR20,
VAR38, VAR11, VAR12, VAR52, VAR21,
VAR18, VAR62, VAR30, VAR59,
VAR56, VAR69, VAR... | mit |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_lsu_cappuccino.v | 26,804 | module MODULE1
parameter VAR74 = "VAR150",
parameter VAR51 = 32,
parameter VAR20 = 5,
parameter VAR89 = 9,
parameter VAR53 = 2,
parameter VAR149 = 32,
parameter VAR157 = "VAR150",
parameter VAR138 = "VAR150",
parameter VAR97 = "VAR150",
parameter VAR156 = 6,
parameter VAR93 = 1,
parameter VAR33 = "VAR37",
parameter VAR... | mit |
peteasa/oh | src/common/hdl/oh_standby.v | 1,734 | module MODULE1 #( parameter VAR7 = 5, parameter VAR6 = 5) (
input VAR2, input VAR16, input [VAR6-1:0] VAR18, input VAR4, output VAR10 );
reg [VAR7-1:0] VAR9;
reg VAR1;
wire VAR15;
wire VAR12;
wire [VAR6-1:0] VAR14;
wire VAR8;
VAR17 #(.VAR3(VAR6))
VAR17 (.out (VAR14[VAR6-1:0]),
.clk (VAR2),
.VAR16 (VAR16),
.in (VAR18[VA... | mit |
cybero/Verilog | src/UART + checker module/rtl/uart_tx.v | 2,524 | module MODULE1
parameter VAR8 = 8, VAR5 = 16 )
(
input wire clk,
input wire reset,
input wire [7:0] VAR21,
input wire VAR13,
input wire VAR7,
output reg VAR16,
output wire VAR18
);
localparam [1:0]
VAR17 = 2'b00,
VAR15 = 2'b01,
VAR6 = 2'b10,
VAR3 = 2'b11;
reg [1:0] VAR10, VAR2;
reg [3:0] VAR14, VAR4;
reg [2:0] VAR1, VA... | mit |
csail-csg/recycle-bsv-lib | src/v/EHRU_8.v | 3,545 | module MODULE1 (
VAR17,
VAR24,
VAR26,
VAR3,
VAR29,
VAR18,
VAR33,
VAR6,
VAR11,
VAR21,
VAR35,
VAR2,
VAR32,
VAR31,
VAR36,
VAR20,
VAR5,
VAR34,
VAR9,
VAR22,
VAR19,
VAR37,
VAR10,
VAR25,
VAR15
);
parameter VAR1 = 1;
parameter VAR30 = 0;
input VAR17;
output [VAR1-1:0] VAR24;
input [VAR1-1:0] VAR26;
input VAR3;
output [VAR1-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi.symbol.v | 1,389 | module MODULE1 (
input VAR9,
input VAR6,
input VAR7,
input VAR5,
input VAR10,
output VAR3
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
lab1-ufba/Genius | rom_dispv_bb.v | 5,051 | module MODULE1 (
address,
VAR1,
VAR2);
input [5:0] address;
input VAR1;
output [5:0] VAR2;
tri1 VAR1;
endmodule | gpl-3.0 |
lokisz/openzcore | pippo-riscv/rtl/verilog/imx_uocm.v | 1,363 | module MODULE1(
clk,
VAR2, VAR5, VAR4,
addr, VAR8, VAR10
);
parameter VAR1 = VAR6; parameter VAR7 = VAR11;
input clk;
input VAR2;
input VAR4;
input VAR5;
input [VAR1-1:0] addr;
input [VAR7-1:0] VAR8;
output [VAR7-1:0] VAR10;
reg [VAR7-1:0] VAR3 [(1<<VAR1)-1:0] ;
reg [VAR1-1:0] VAR9; | gpl-2.0 |
lbl-cal/StanfordNoC | router/src/rtr_op_ctrl_mac.v | 11,749 | module MODULE1
(clk, reset, VAR31, VAR94, VAR49, VAR42,
VAR22, VAR25, VAR69, VAR76, VAR87,
VAR72, VAR23, VAR55);
parameter VAR52 = 32;
parameter VAR91 = 4;
parameter VAR66 = 5;
parameter VAR95 = VAR65;
parameter VAR3 = VAR4;
parameter VAR85 = 1;
parameter VAR81 = VAR10;
parameter VAR74 = 0;
parameter VAR73 = VAR39;
par... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2_1.v | 2,223 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR9 ,
VAR2 ,
VAR7,
VAR4,
VAR3 ,
VAR8
);
output VAR6 ;
input VAR1 ;
input VAR9 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR8 ;
VAR10 VAR5 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (... | apache-2.0 |
AngelTerrones/Antares | Hardware/verilog/antares_memwb_register.v | 2,879 | module MODULE1 (
input clk, input rst, input [31:0] VAR8, input [31:0] VAR13, input [4:0] VAR7, input VAR5, input VAR4, input VAR3,
input VAR12, input VAR10, output reg [31:0] VAR11, output reg [31:0] VAR2, output reg [4:0] VAR6, output reg VAR1, output reg VAR9 );
always @(posedge clk) begin
VAR11 <= (rst) ? 32'b0 : (... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp.functional.pp.v | 1,947 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR13,
VAR10,
VAR16 ,
VAR5
);
output VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR13;
input VAR10;
input VAR16 ;
input VAR5 ;
wire VAR9 ;
wire VAR11;
VAR4 VAR8 (VAR11, VAR9, VAR6, VAR3 );
VAR15 VAR1 VAR14 (VAR9 , VAR11, VAR7, , VAR13, VAR10);
buf VAR12 (VAR2 , VAR9... | apache-2.0 |
silent-observer/RCPU | CPU/source/RAM.v | 7,455 | module MODULE1 (
input wire rst,
input wire clk,
input wire[31:0] VAR69,
input wire[15:0] write,
input wire VAR71,
output wire[15:0] read,
input wire VAR22,
input wire[1:0] VAR16,
input wire[1:0] VAR19,
output wire ready,
output wire[10:0] VAR6,
output wire[15:0] VAR13,
input wire[3:0] VAR24,
output wire[31:0] VAR33, V... | mit |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/ip/BIOS_ROM/BIOS_ROM_stub.v | 1,388 | module MODULE1(VAR3, VAR5, VAR1, VAR2, VAR6, VAR4)
;
input VAR3;
input VAR5;
input [0:0]VAR1;
input [11:0]VAR2;
input [7:0]VAR6;
output [7:0]VAR4;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv_4.v | 2,036 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR2,
VAR4,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR8 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR1 ;
VAR6 VAR3 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR2;
supply0 VAR4;... | apache-2.0 |
linuxbest/lzs | encode/bench/verilog/data.v | 4,134 | module MODULE1(
clk, rst, VAR58, VAR49, VAR18, VAR16, VAR34, VAR2,
VAR43, VAR17
);
parameter VAR25 = 20;
parameter VAR22 = 512;
parameter VAR41 = "../../../../VAR56/01";
parameter VAR60 = 1;
parameter VAR44 = 20;
parameter VAR5 = 5;
output clk, rst, VAR58, VAR49, VAR18, VAR16;
output [63:0] VAR34;
output [VAR25-1:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfstp/sky130_fd_sc_hvl__dfstp.behavioral.pp.v | 2,307 | module MODULE1 (
VAR5 ,
VAR17 ,
VAR21 ,
VAR10,
VAR20 ,
VAR8 ,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR17 ;
input VAR21 ;
input VAR10;
input VAR20 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
wire VAR6 ;
wire VAR15 ;
reg VAR11 ;
wire VAR22 ;
wire VAR7 ;
wire VAR12;
wire VAR14 ;
wire VAR1 ;
not VAR19 (VAR15 , VAR12 );
VAR9 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/maj3/sky130_fd_sc_ms__maj3.functional.pp.v | 2,186 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR10 ,
VAR7 ,
VAR6,
VAR3,
VAR16 ,
VAR20
);
output VAR1 ;
input VAR12 ;
input VAR10 ;
input VAR7 ;
input VAR6;
input VAR3;
input VAR16 ;
input VAR20 ;
wire VAR15 ;
wire VAR14 ;
wire VAR13 ;
wire VAR4 ;
wire VAR8;
or VAR9 (VAR15 , VAR10, VAR12 );
and VAR18 (VAR14 , VAR15, VAR7 );
and VAR1... | apache-2.0 |
UviDTE-UviSpace/UviSpace | DE1-SoC/FPGA_Design/uvispace_top.v | 27,611 | module MODULE1(
inout VAR98,
output VAR141,
input VAR39,
output VAR230,
input VAR152,
inout VAR225,
inout VAR246,
output VAR213,
inout VAR45,
output VAR170,
input VAR268,
input VAR283,
input VAR121,
input VAR301,
output [12:0] VAR286, output [1:0] VAR304, output VAR229, output VAR150, output VAR408, output VAR15, inout... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/fei4_rx/fei4_rx_core.v | 7,033 | module MODULE1 #(
parameter VAR32 = 10,
parameter VAR63 = 0,
parameter VAR37 = 32
) (
input wire VAR50,
input wire VAR27,
input wire VAR66,
input wire VAR15,
output reg VAR58,
output reg VAR74,
output reg VAR81,
input wire VAR72,
input wire VAR18,
output wire VAR71,
output wire [31:0] VAR29,
output wire VAR1,
output wi... | bsd-3-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_clkgen_v1_00_a/hdl/verilog/cf_clkgen.v | 13,841 | module MODULE1 (
VAR18,
clk,
VAR9,
VAR7,
VAR60,
VAR41,
VAR91,
VAR93,
VAR33,
VAR30);
parameter VAR98 = 'd0;
parameter VAR28 = 'h0;
parameter VAR47 = 'h1;
parameter VAR71 = 'h2;
parameter VAR68 = 'h3;
parameter VAR54 = 'h4;
input VAR18;
output clk;
input VAR9;
input VAR7;
input VAR60;
input VAR41;
input [ 4:0] VAR91;
inp... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_CKINVDC_RVT_SS_210930.v | 11,788 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_convert_with_rounding.v | 11,095 | module MODULE1(VAR19, VAR9, VAR42, VAR5, VAR22, VAR1, VAR36, VAR26, enable);
parameter VAR33 = 1;
parameter VAR27 = 0;
parameter VAR12 = 1;
input VAR19;
input enable, VAR9;
input [31:0] VAR42;
output [31:0] VAR5;
input VAR22, VAR36;
output VAR26, VAR1;
wire VAR24;
wire [7:0] VAR30;
wire [22:0] VAR10;
wire [23:0] VAR31;... | mit |
borti4938/sd2snes | verilog/sd2snes_base/dac.v | 7,312 | module MODULE1(
input VAR53,
input VAR46,
input VAR54,
input[10:0] VAR41,
input[7:0] VAR24,
input[7:0] VAR4,
input VAR18,
input [2:0] VAR34,
input [8:0] VAR47,
input VAR26,
input reset,
input VAR43,
output VAR48,
output VAR25,
output VAR22,
output VAR6,
output VAR13
);
reg[8:0] VAR52;
reg[8:0] VAR21;
wire[8:0] VAR3 = V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtn/sky130_fd_sc_ls__dfrtn.symbol.v | 1,431 | module MODULE1 (
input VAR5 ,
output VAR7 ,
input VAR1,
input VAR4
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/var14_multi.v | 1,201 | module MODULE1 (VAR16, VAR4, VAR14, VAR20, VAR8, VAR17, VAR1, VAR15, VAR11, VAR6, VAR12, VAR19, VAR7, VAR2, valid);
input VAR16, VAR4, VAR14, VAR20, VAR8, VAR17, VAR1, VAR15, VAR11, VAR6, VAR12, VAR19, VAR7, VAR2;
output valid;
wire [7:0] VAR13 = 8'd120;
wire [7:0] VAR3 = 8'd60;
wire [7:0] VAR10 = 8'd60;
wire [7:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a_1.v | 2,248 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR3 ,
VAR4 ,
VAR6,
VAR10,
VAR7 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR6;
input VAR10;
input VAR7 ;
input VAR1 ;
VAR2 VAR9 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipitc131_IS2Vid_calculate_mode.v | 3,972 | module MODULE1(
input [3:0] VAR38,
input VAR34,
input VAR23,
input [15:0] VAR2,
input [15:0] VAR51,
input [15:0] VAR8,
input [15:0] VAR25,
input [15:0] VAR42,
input [15:0] VAR5,
input [15:0] VAR33,
input [15:0] VAR9,
input [15:0] VAR11,
input [15:0] VAR26,
input [15:0] VAR4,
input [15:0] VAR6,
input [15:0] VAR16,
input... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_2.behavioral.v | 1,802 | module MODULE1( VAR5, VAR8, VAR3, VAR1, VAR7 );
input VAR3, VAR5, VAR1, VAR7;
output VAR8;
VAR2 VAR4(.VAR5(VAR5),.VAR8(VAR8),.VAR3(VAR3),.VAR1(VAR1),.VAR7(VAR7));
VAR2 VAR6(.VAR5(VAR5),.VAR8(VAR8),.VAR3(VAR3),.VAR1(VAR1),.VAR7(VAR7)); | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/SpecialCases.v | 6,454 | module MODULE1(
input [31:0] VAR3,
input [31:0] VAR9,
input [31:0] VAR26,
input [1:0] VAR25,
input VAR2,
input VAR12,
input [7:0] VAR7,
input reset,
input VAR30,
output reg [1:0] VAR16 = 1'b00,
output reg [32:0] VAR6,
output reg [32:0] VAR10,
output reg [35:0] VAR8,
output reg [35:0] VAR27,
output reg [31:0] VAR28,
out... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai.functional.pp.v | 2,159 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR12 ,
VAR11 ,
VAR6 ,
VAR15,
VAR8,
VAR10 ,
VAR13
);
output VAR5 ;
input VAR2 ;
input VAR12 ;
input VAR11 ;
input VAR6 ;
input VAR15;
input VAR8;
input VAR10 ;
input VAR13 ;
wire VAR7 ;
wire VAR9 ;
wire VAR17 ;
wire VAR19;
nor VAR16 (VAR7 , VAR11, VAR6 );
nor VAR3 (VAR9 , VAR2, VAR12 );
o... | apache-2.0 |
cliffordwolf/yosys | techlibs/intel/cyclone10lp/cells_map.v | 3,442 | module \VAR22 (input VAR15, output VAR12);
VAR19 VAR10 (.VAR16(VAR12), .VAR9(VAR15), .VAR5(1'b0));
endmodule
module \VAR18 (input VAR15, output VAR12);
VAR14 VAR10 (.VAR16(VAR12), .VAR9(VAR15), .VAR17(1'b1));
endmodule
module MODULE1 (VAR6, VAR24);
parameter VAR7 = 0;
parameter VAR1 = 0;
input [VAR7-1:0] VAR6;
output V... | isc |
hydai/Verilog-Practice | DigitalDesign/Final/final/final_101062124/Processor.v | 5,592 | module MODULE1 (
output reg [31:0] VAR50,
output reg [31:0] VAR42,
output reg [31:0] address,
output reg VAR38,
output reg VAR49,
input [31:0] VAR46,
input [31:0] VAR14,
input clk,
input VAR44
);
reg [31:0] VAR20, counter, VAR23, VAR34, VAR5;
reg [31:0] VAR6[0:31];
reg VAR13;
wire [31:0] VAR15, VAR54, VAR43, VAR27, VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.pp.symbol.v | 1,291 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR8 ,
output VAR5,
output VAR6 ,
input VAR1 ,
input VAR3,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_pwm8_core.v | 12,343 | module MODULE1(
input VAR185,
input reset,
input VAR30,
input [31:0] VAR64,
output [31:0] VAR188,
input VAR184,
input [31:0] VAR86,
output [31:0] VAR39,
input VAR124,
input [31:0] VAR96,
output [31:0] VAR79,
input VAR177,
input [7:0] VAR182,
output [7:0] VAR43,
input VAR105,
input [7:0] VAR27,
output [7:0] VAR58,
input... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_126.v | 1,468 | module MODULE2 (
VAR8,
VAR1
);
input [31:0] VAR8;
output [31:0]
VAR1;
wire [31:0]
VAR13,
VAR11,
VAR6,
VAR4,
VAR3,
VAR5,
VAR2,
VAR7;
assign VAR13 = VAR8;
assign VAR2 = VAR3 - VAR5;
assign VAR11 = VAR13 << 8;
assign VAR6 = VAR13 + VAR11;
assign VAR3 = VAR6 + VAR4;
assign VAR7 = VAR2 << 7;
assign VAR5 = VAR13 << 5;
assign... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b.functional.pp.v | 1,924 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR3 ,
VAR12,
VAR7,
VAR10 ,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR3 ;
input VAR12;
input VAR7;
input VAR10 ;
input VAR5 ;
wire VAR13 ;
wire VAR1 ;
wire VAR2;
not VAR15 (VAR13 , VAR3 );
or VAR14 (VAR1 , VAR13, VAR6 );
VAR11 VAR9 (VAR2, VAR1, VAR12, VAR7);
buf VAR4 (VAR8 , VAR2 );
end... | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram2_m/altera_avalon_st_bytes_to_packets_171/synth/altera_avalon_st_bytes_to_packets.v | 8,088 | module MODULE1
parameter VAR18 = 0 )
(
input clk,
input VAR3,
input VAR19,
output reg VAR17,
output reg [7: 0] VAR6,
output reg [VAR10-1: 0] VAR13,
output reg VAR12,
output reg VAR15,
output reg VAR11,
input VAR8,
input [7: 0] VAR14
);
reg VAR7, VAR4, VAR5;
wire VAR20, VAR21, VAR2, VAR1, VAR9;
wire [7:0] VAR16;
assign ... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/premuat3.v | 15,024 | module MODULE1(
VAR74,
VAR113,
VAR94 ,
VAR41 ,
VAR96 ,
VAR19 ,
VAR99 ,
VAR31 ,
VAR107 ,
VAR32 ,
VAR116 ,
VAR30 ,
VAR102,
VAR117,
VAR112,
VAR90,
VAR72,
VAR52,
VAR121,
VAR29,
VAR87,
VAR16,
VAR22,
VAR50,
VAR70,
VAR15,
VAR9,
VAR76,
VAR38,
VAR114,
VAR103,
VAR57,
VAR82,
VAR71,
o0 ,
o1 ,
o2 ,
o3 ,
o4 ,
o5 ,
o6 ,
o7 ,
VAR34 ,
... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/common/prcfg_bb.v | 3,391 | module MODULE1 (
input clk,
input [31:0] VAR11,
output [31:0] VAR14,
input [31:0] VAR20,
output [31:0] VAR6,
output VAR9,
input VAR7,
input [63:0] VAR10,
input VAR2,
input VAR3,
output VAR16,
output [63:0] VAR8,
output VAR18,
input VAR12,
input VAR13,
input [63:0] VAR15,
output VAR17,
output VAR5,
output VAR1,
output [... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab1/Lab1-Project/TF_EECS301_Lab1_TopLevel.v | 8,555 | module MODULE1();
reg VAR7;
reg [3:0] VAR3;
wire [9:0] VAR8;
wire [6:0] VAR4;
wire [6:0] VAR10;
wire [6:0] VAR6;
wire [6:0] VAR11;
wire [6:0] VAR9;
wire [6:0] VAR2;
localparam VAR5 = 50000000; localparam VAR1 = ((1.0 / VAR5) * 1000000000.0) / 2.0;
begin
begin
begin
end
begin
end | mit |
hoangt/NOCulator | hring/hw/buffered/src/c_xor_nto1.v | 2,269 | module MODULE1
(VAR9, VAR3);
parameter VAR8 = 2;
parameter VAR1 = 1;
input [0:VAR1*VAR8-1] VAR9;
output [0:VAR1-1] VAR3;
wire [0:VAR1-1] VAR3;
generate
genvar VAR4;
for(VAR4 = 0; VAR4 < VAR1; VAR4 = VAR4 + 1)
begin:VAR7
wire [0:VAR8-1] VAR5;
genvar VAR6;
for(VAR6 = 0; VAR6 < VAR8; VAR6 = VAR6 + 1)
begin:VAR2
assign VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4.behavioral.pp.v | 1,837 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR14 ,
VAR9 ,
VAR7 ,
VAR12,
VAR11,
VAR4 ,
VAR13
);
output VAR3 ;
input VAR6 ;
input VAR14 ;
input VAR9 ;
input VAR7 ;
input VAR12;
input VAR11;
input VAR4 ;
input VAR13 ;
wire VAR1 ;
wire VAR10;
and VAR15 (VAR1 , VAR6, VAR14, VAR9, VAR7 );
VAR8 VAR2 (VAR10, VAR1, VAR12, VAR11);
buf VAR5 ... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_fpu_post_norm_div.v | 9,773 | module MODULE1
(
VAR40,
VAR1,
VAR38,
VAR12,
VAR42,
VAR61,
VAR6,
VAR45,
VAR22,
VAR47
);
parameter VAR51 = 32;
parameter VAR46 = 0; parameter VAR11 = 11; parameter VAR48 = 23;
parameter VAR17 = 8;
parameter VAR26 = 31'd0;
parameter VAR20 = 31'b1111111100000000000000000000000;
parameter VAR14 = 31'b11111111100000000000000... | mit |
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