repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
DeadBugEngineering/myHDL_shenanigans | ssd1306_8x64bit_driver/font/rom.v | 3,213 | module MODULE1 (
dout,
addr
);
output [7:0] dout;
reg [7:0] dout;
input [6:0] addr;
always @(addr) begin: VAR1
case (addr)
0: dout = 0;
1: dout = 8;
2: dout = 28;
3: dout = 28;
4: dout = 28;
5: dout = 28;
6: dout = 28;
7: dout = 8;
8: dout = 0;
9: dout = 120;
10: dout = 14;
11: dout = 7;
12: dout = 3;
13: dout = 1;
14:... | lgpl-2.1 |
asicguy/gplgpu | hdl/ramdac_sp/ram_blk.v | 2,444 | module MODULE1
(
input VAR9,
input write,
input [8:0] VAR8,
input [7:0] VAR10,
input VAR16,
input [8:0] VAR17,
output [7:0] VAR11,
output [7:0] VAR6
);
VAR13 VAR18
(
.VAR3 (VAR9),
.VAR15 (write),
.VAR2 (VAR8),
.VAR5 (VAR10),
.VAR14 (VAR16),
.VAR19 (1'b0),
.VAR1 (VAR17),
.VAR7 (8'b0),
.VAR12 (VAR6),
.VAR4 (VAR11)
);
end... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/riffa_wrapper_vc707.v | 37,847 | module MODULE1
parameter VAR178 = 128,
parameter VAR330 = 256,
parameter VAR86 = 8
)
(
input [VAR178-1:0] VAR345,
input [(VAR178/8)-1:0] VAR119,
input VAR111,
input VAR353,
output VAR287,
input [VAR45-1:0] VAR210,
output VAR342,
output VAR145,
output [VAR178-1:0] VAR4,
output [(VAR178/8)-1:0] VAR177,
output VAR181,
out... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_1/zqynq_lab_1_design_auto_pc_1_stub.v | 4,404 | module MODULE1(VAR26, VAR23, VAR10, VAR21,
VAR20, VAR13, VAR16, VAR32, VAR40, VAR39,
VAR47, VAR42, VAR49, VAR15, VAR28, VAR35,
VAR9, VAR30, VAR5, VAR7, VAR27, VAR43,
VAR38, VAR6, VAR2, VAR1, VAR51, VAR50,
VAR31, VAR25, VAR53, VAR3, VAR17, VAR14,
VAR4, VAR34, VAR22, VAR46, VAR24, VAR44,
VAR48, VAR37, VAR29, VAR52, VAR18... | mit |
alexforencich/hdg2000 | fpga/lib/dsp/rtl/i2s_rx.v | 3,292 | module MODULE1 #
(
parameter VAR1 = 16
)
(
input wire clk,
input wire rst,
input wire VAR11,
input wire VAR10,
input wire VAR7,
output wire [VAR1-1:0] VAR12,
output wire [VAR1-1:0] VAR18,
output wire VAR13,
input wire VAR6
);
reg [VAR1-1:0] VAR15 = 0;
reg [VAR1-1:0] VAR14 = 0;
reg VAR16 = 0;
reg VAR8 = 0;
reg [VAR1-1:0... | mit |
ppnipuna/EDAC_ASIC_Design | rtl/decoder.v | 2,852 | module MODULE1#(parameter VAR17 = 8, VAR22 = 4)(
VAR9, VAR3,VAR7,clk,
VAR18, VAR4,VAR6);
localparam VAR8 = VAR17;
localparam VAR23 = VAR22;
input wire clk, VAR7, VAR3;
input wire [VAR8+VAR23:1] VAR9;
output reg VAR4;
output reg VAR6;
output reg [VAR8:1] VAR18;
reg [VAR23-1:1] VAR2; reg [VAR8+VAR23:1] VAR5,VAR13;
reg [V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai.functional.v | 1,592 | module MODULE1 (
VAR12 ,
VAR4,
VAR2,
VAR5,
VAR1,
VAR6
);
output VAR12 ;
input VAR4;
input VAR2;
input VAR5;
input VAR1;
input VAR6;
wire VAR8 ;
wire VAR13 ;
wire VAR10;
or VAR3 (VAR8 , VAR1, VAR5 );
or VAR11 (VAR13 , VAR2, VAR4 );
nand VAR9 (VAR10, VAR13, VAR8, VAR6);
buf VAR7 (VAR12 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_2.v | 2,711 | module MODULE2 (
VAR13 ,
VAR1 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR4,
VAR9 ,
VAR11 ,
VAR12 ,
VAR7
);
output VAR13 ;
output VAR1 ;
input VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR4;
input VAR9 ;
input VAR11 ;
input VAR12 ;
input VAR7 ;
VAR6 VAR3 (
.VAR13(VAR13),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21bo/sky130_fd_sc_hdll__a21bo.functional.v | 1,491 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR8 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR5;
wire VAR7 ;
wire VAR9;
nand VAR4 (VAR7 , VAR8, VAR3 );
nand VAR2 (VAR9, VAR5, VAR7);
buf VAR1 (VAR6 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlclkp/sky130_fd_sc_hd__dlclkp_2.v | 2,154 | module MODULE1 (
VAR2,
VAR9,
VAR4 ,
VAR5,
VAR7,
VAR3 ,
VAR8
);
output VAR2;
input VAR9;
input VAR4 ;
input VAR5;
input VAR7;
input VAR3 ;
input VAR8 ;
VAR1 VAR6 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR2,
VAR9,
VAR4
);
output VAR2;
inpu... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/source/GDA_St_N8_M8_P4.v | 3,250 | module MODULE1(
input [7:0] VAR24,
input [7:0] VAR4,
output [8:0] VAR26
);
wire [2:0] VAR46, VAR52, VAR3, VAR51, VAR16, VAR100, VAR72, VAR2;
wire VAR77,VAR6,VAR1,VAR62,VAR94,VAR78,VAR76,VAR74,VAR54,VAR104,VAR61,VAR48,VAR88,VAR45,VAR98,VAR84,VAR102,VAR30,VAR96,VAR67,VAR36;
wire VAR21,VAR81,VAR91,VAR19,VAR66,VAR25,VAR99,... | gpl-3.0 |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_zbroji_0_0/synth/ZynqDesign_zbroji_0_0.v | 7,708 | module MODULE1 (
VAR2,
VAR5,
VAR23,
VAR13,
VAR8,
VAR11,
VAR22,
VAR9,
VAR3,
VAR14,
VAR20,
VAR16,
VAR1,
VAR18,
VAR7,
VAR17,
VAR4,
interrupt,
VAR15,
VAR10
);
input wire [5 : 0] VAR2;
input wire VAR5;
output wire VAR23;
input wire [31 : 0] VAR13;
input wire [3 : 0] VAR8;
input wire VAR11;
output wire VAR22;
output wire [1 ... | mit |
mdsalman729/flexpret_project | fpga/atlys/4tf-16i-16d/top.v | 5,169 | module MODULE1(
input clk,
input VAR56,
input[7:0] VAR17,
output[7:0] VAR61
);
wire VAR51;
wire VAR20;
wire[11:0] VAR59;
wire VAR2;
wire[31:0] VAR55;
wire[11:0] VAR48;
wire VAR25;
wire VAR41;
wire VAR13;
wire VAR10;
wire VAR23;
wire[31:0] VAR47;
wire[31:0] VAR46;
wire[31:0] VAR49;
wire[7:0] VAR64;
wire[7:0] VAR12;
wire... | bsd-3-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/common/rtl/iobdg_findfirst.v | 2,885 | module MODULE1 (
VAR1,
VAR4
);
parameter VAR5 = 64;
input [VAR5-1:0] VAR4;
output [VAR5-1:0] VAR1;
reg [VAR5-1:0] VAR1;
reg [VAR5-1:0] VAR2;
integer VAR3;
always @(VAR4 or VAR2)
begin
VAR2[0] = VAR4[0];
VAR1[0] = VAR4[0];
for (VAR3=1; VAR3<VAR5; VAR3=VAR3+1)
begin
VAR2[VAR3] = VAR4[VAR3] | VAR2[VAR3-1];
VAR1[VAR3] = VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pp.symbol.v | 1,464 | module MODULE1 (
input VAR5 ,
output VAR3 ,
input VAR7,
input VAR4 ,
input VAR1 ,
input VAR10 ,
input VAR8 ,
input VAR9 ,
input VAR6 ,
input VAR2
);
endmodule | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/DM9000A.v | 2,505 | module MODULE1 (
input wire VAR14, input wire VAR13, inout wire [15:0] VAR10, output wire VAR9, output wire VAR2, output wire VAR15, output wire VAR17, output wire VAR7, output wire VAR5, input wire VAR19, input wire [15:0] VAR16, input wire VAR3, input wire VAR12, input wire VAR6, input wire VAR11, output wire [15:0] ... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp1/models/fifo_1c_1k.v | 1,544 | module MODULE1 ( VAR19, VAR13, VAR6, VAR18, VAR17, VAR9, VAR7,
VAR4, VAR14, VAR12, VAR10, VAR1, VAR3);
parameter VAR15 = 32;
parameter VAR11 = 1024;
input [31:0] VAR19;
input VAR13;
input VAR6;
input VAR18;
input VAR17;
input VAR9;
output [31:0] VAR7;
output VAR4;
output VAR14;
output [9:0] VAR12;
output VAR10;
output ... | gpl-2.0 |
Marcoslz22/Tercer_Proyecto | control_digitos.v | 3,757 | module MODULE1
(
input [7:0] VAR17,
input [3:0]VAR10,
input [3:0]VAR9,
input [3:0]VAR14,
input VAR7,
input VAR2,
input wire clk,
input wire [3:0] VAR16,
input [3:0] VAR4,
output reg [3:0] VAR11, VAR15, VAR8, VAR1, VAR12, VAR13, VAR6, VAR3, VAR5
);
always @(posedge clk)
if (~VAR7)
if (VAR2)
case (VAR4)
4'b0000: VAR11<=V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.behavioral.pp.v | 1,237 | module MODULE1 (
VAR3,
VAR2,
VAR4 ,
VAR1
);
input VAR3;
input VAR2;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
MarcoVogt/basil | firmware/modules/seq_gen/seq_gen_core.v | 8,749 | module MODULE1
parameter VAR22 = 16,
parameter VAR2 = 16384,
parameter VAR1 = 16 )(
VAR33,
VAR42,
VAR23,
VAR45,
VAR39,
VAR24,
VAR17,
VAR48,
VAR38,
VAR36
);
localparam VAR31 = 2;
input wire VAR33;
input wire VAR42;
input wire [VAR22-1:0] VAR23;
input wire [7:0] VAR45;
input wire VAR39;
input wire VAR24;
output reg [7:0]... | bsd-3-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/cabac_ctx_state_2p_7x64.v | 2,376 | module MODULE1(
clk ,
VAR5 ,
VAR19 ,
VAR2 ,
VAR13 ,
VAR18 ,
VAR1
);
input clk ; input VAR5 ; input [5:0] VAR19 ; input VAR2 ; input [5:0] VAR13 ; input [6:0] VAR18 ;
output [6:0] VAR1 ;
VAR8 #(.VAR3(6), .VAR6(7))
VAR10 (
.VAR4 ( clk ),
.VAR11 ( ~VAR5 ),
.VAR17 ( VAR19 ),
.VAR15 ( VAR1 ),
.VAR7 ( clk ),
.VAR12 ( ~VAR2 )... | gpl-3.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/example_design/PIO.v | 5,942 | module MODULE1 #(
parameter VAR17 = 64,
parameter VAR15 = VAR17 / 8, parameter VAR10 = 1
)(
input VAR7,
input VAR11,
input VAR6,
input VAR14,
output [VAR17-1:0] VAR18,
output [VAR15-1:0] VAR28,
output VAR29,
output VAR25,
output VAR9,
input [VAR17-1:0] VAR13,
input [VAR15-1:0] VAR12,
input VAR26,
input VAR2,
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_g/sky130_fd_sc_hdll__udp_pwrgood_pp_g.symbol.v | 1,293 | module MODULE1 (
input VAR3 ,
output VAR2,
input VAR1
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/system/synthesis/submodules/system_acl_iface_acl_kernel_clk.v | 35,319 | module MODULE1 (
output wire VAR104, input wire VAR236, output wire VAR243, output wire [31:0] VAR131, output wire VAR229, input wire [0:0] VAR136, input wire [31:0] VAR256, input wire [10:0] VAR69, input wire VAR53, input wire VAR95, input wire [3:0] VAR50, input wire VAR93, output wire VAR15, output wire VAR31, input... | mit |
anguslin/RISC | datapath.v | 1,511 | module MODULE1(clk, VAR8, VAR29, VAR2, VAR31, VAR26, VAR1, VAR6, VAR28, VAR4, VAR23, VAR22, write, VAR30, VAR9, VAR17, VAR19, VAR13, VAR33);
input clk, VAR2, VAR31, write, VAR1, VAR6, VAR4, VAR23;
input [2:0] VAR8, VAR22;
input [1:0] VAR26, VAR28, VAR29;
input [15:0] VAR30, VAR9, VAR17;
output [2:0] VAR19;
output [15:0... | mit |
rfotino/consolite-hardware | proj/ipcore_dir/s6_lpddr_ram/user_design/rtl/mcb_controller/mcb_soft_calibration_top.v | 12,394 | module MODULE1 # (
parameter VAR63 = 10'h512, parameter VAR26 = "VAR72", parameter VAR30 = 1'b0, parameter VAR3 = 1'b0, parameter VAR51 = 1'b0, parameter VAR59 = "VAR89", parameter VAR7 = "VAR21" )
(
input wire VAR2, input wire VAR5, input wire VAR83, output wire VAR32, input wire VAR40, input wire VAR92,
input wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR9 ,
VAR8,
VAR5,
VAR1 ,
VAR2 ,
VAR7,
VAR4,
VAR6 ,
VAR3
);
output VAR9 ;
input VAR8;
input VAR5;
input VAR1 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
skarpenko/ultiparc | rtl/src/cpu/uparc_memory_access.v | 5,492 | module MODULE1(
clk,
VAR41,
VAR40,
VAR8,
VAR9,
VAR34,
VAR21,
VAR3,
VAR25,
VAR42,
VAR11,
VAR36,
VAR44,
VAR15,
VAR10,
VAR18,
VAR43,
VAR5,
VAR33,
VAR35,
VAR38,
VAR29,
VAR4,
VAR30,
VAR14
);
localparam [3:0] VAR20 = 4'b0000;
localparam [3:0] VAR19 = 4'b1000;
localparam [3:0] VAR17 = 4'b1001;
localparam [3:0] VAR7 = 4'b1010;... | bsd-2-clause |
Marcoslz22/Tercer_Proyecto | MUX_DECO_FF.v | 1,112 | module MODULE1(
input rst,
input clk,
input VAR3,
input VAR9,
input VAR8,
input [7:0]VAR12,
input [7:0]VAR4,
input [7:0]VAR11,
input [7:0] VAR13,
input [7:0]VAR6,
input [7:0]VAR14,
input [7:0]VAR7,
output [7:0]VAR10
);
wire [7:0]VAR15;
VAR5 VAR5 (
.VAR12(VAR12),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR15(VAR15),
.VA... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/pcie_clocking.v | 8,428 | module MODULE1 #
( parameter VAR26 = 2, parameter VAR54 = 1 )
(
input VAR49,
input VAR16,
input rst,
output VAR15,
output VAR17,
output VAR37,
output VAR23,
output VAR31,
input VAR34
);
wire VAR44;
wire VAR10;
wire VAR60;
wire VAR62;
wire VAR53;
wire VAR2;
wire VAR33;
wire VAR41;
wire VAR52;
wire [15:0] VAR18;
reg [7:0... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/led_pio.v | 2,132 | module MODULE1 (
address,
VAR2,
clk,
VAR4,
VAR9,
VAR8,
VAR3,
VAR7
)
;
output [ 7: 0] VAR3;
output [ 31: 0] VAR7;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR4;
input VAR9;
input [ 31: 0] VAR8;
wire VAR6;
reg [ 7: 0] VAR5;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR1;
wire [ 31: 0] VAR7;
assign VAR6 = 1;
assign VAR1 ... | mit |
hydai/Verilog-Practice | DigitalDesign/hw4_FIFO/fifo_t.v | 3,437 | module MODULE1;
parameter period = 20;
parameter delay = 2;
VAR2 VAR1 (
);
always #(period/2) clk = ~clk;
begin
begin
begin
begin | mit |
tloinuy/opencpi-opencv | opencpi/hdl/apps/mkOCApp-noADC-3w.v | 21,272 | module MODULE1(VAR126,
VAR141,
VAR161,
VAR112,
VAR111,
VAR55,
VAR22,
VAR30,
VAR119,
VAR57,
VAR152,
VAR6,
VAR243,
VAR200,
VAR123,
VAR186,
VAR130,
VAR7,
VAR11,
VAR174,
VAR220,
VAR115,
VAR95,
VAR158,
VAR16,
VAR249,
VAR244,
VAR83,
VAR235,
VAR18,
VAR260,
VAR61,
VAR54,
VAR58,
VAR33,
VAR248,
VAR56,
VAR177,
VAR101,
VAR91,
VAR2... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or3/gf180mcu_fd_sc_mcu9t5v0__or3_2.behavioral.v | 1,245 | module MODULE1( VAR4, VAR7, VAR2, VAR5 );
input VAR4, VAR7, VAR2;
output VAR5;
VAR1 VAR3(.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR5(VAR5));
VAR1 VAR6(.VAR4(VAR4),.VAR7(VAR7),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
rbesenczi/real-time-traffic-analyzer | src/traffic_analyser_Vivado_2014_4/traffic_analyser_Vivaldo_2014_4.srcs/sources_1/bd/design_1/ip/design_1_auto_pc_1/synth/design_1_auto_pc_1.v | 10,688 | module MODULE1 (
VAR4,
VAR102,
VAR69,
VAR57,
VAR49,
VAR37,
VAR95,
VAR7,
VAR92,
VAR101,
VAR9,
VAR77,
VAR41,
VAR64,
VAR51,
VAR2,
VAR47,
VAR89,
VAR62,
VAR10,
VAR22,
VAR105,
VAR5,
VAR115,
VAR63,
VAR40,
VAR70,
VAR85,
VAR79,
VAR14,
VAR84,
VAR83,
VAR56,
VAR100,
VAR86,
VAR18,
VAR42,
VAR28,
VAR34
);
input wire VAR4;
input wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2_1.v | 2,119 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR3,
VAR4,
VAR2 ,
VAR6
);
output VAR5 ;
input VAR8 ;
input VAR3;
input VAR4;
input VAR2 ;
input VAR6 ;
VAR7 VAR1 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply1 VAR3;
supply0 VAR4;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd3/sky130_fd_sc_ls__clkdlyinv3sd3.behavioral.v | 1,440 | module MODULE1 (
VAR4,
VAR9
);
output VAR4;
input VAR9;
supply1 VAR8;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR7 ;
wire VAR3;
not VAR5 (VAR3, VAR9 );
buf VAR2 (VAR4 , VAR3 );
endmodule | apache-2.0 |
CeesWolfs/ceespu | src/ceespu_memory_bus.v | 1,222 | module MODULE1(
input VAR6,
input [15:0] VAR5,
input [31:0] VAR7,
input [31:0] VAR10,
input [7:0] VAR2,
output VAR9,
output VAR8,
output reg [31:0] VAR4
);
reg VAR3;
reg VAR1;
assign VAR9 = (VAR5[15:11] == 5'b1111?);
always @(posedge VAR6) begin
if (VAR5 == 65528) begin
VAR1 <= 1;
end
else if (VAR5[15:11] == 5'b1111?) ... | mit |
hanw/sonic-lite | hw/verilog/si570/si570_controller.v | 4,922 | module MODULE1 (
input wire VAR11, input wire VAR48, input wire VAR39, input wire [2:0] VAR33, output wire VAR5, output wire VAR40,
inout wire VAR45,
output wire [7:0] VAR6,
output wire VAR31
);
wire [6:0] VAR34;
wire [7:0] VAR37;
wire [7:0] VAR16;
wire VAR20;
wire VAR12;
wire VAR47;
wire VAR26;
wire VAR21;
wire VAR13;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp_2.v | 2,154 | module MODULE2 (
VAR5,
VAR6,
VAR1 ,
VAR7,
VAR2,
VAR4 ,
VAR9
);
output VAR5;
input VAR6;
input VAR1 ;
input VAR7;
input VAR2;
input VAR4 ;
input VAR9 ;
VAR3 VAR8 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR5,
VAR6,
VAR1
);
output VAR5;
inpu... | apache-2.0 |
AlvaroNaranjo/Embedded-Systems-Design | Automatic_Pet_Feeder/src/run_clock.v | 1,667 | module MODULE1 (VAR4, VAR13, VAR8, VAR1, VAR11, VAR2, VAR10, VAR6,
VAR12, VAR14, VAR5, VAR7, VAR9, VAR3);
input VAR13, VAR4;
input [3:0] VAR8, VAR1, VAR11, VAR2, VAR10, VAR6;
output reg [3:0] VAR12, VAR14, VAR5, VAR7, VAR9, VAR3;
always @ (posedge VAR13, negedge VAR4)
begin
if (~VAR4)
begin
VAR12 <= VAR8; VAR14 <= VAR1... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/synth/OpenSSD2_NVMeHostController_0_0.v | 14,071 | module MODULE1 (
VAR10,
VAR64,
VAR66,
VAR42,
VAR67,
VAR4,
VAR9,
VAR55,
VAR39,
VAR86,
VAR83,
VAR49,
VAR62,
VAR1,
VAR31,
VAR13,
VAR41,
VAR2,
VAR7,
VAR29,
VAR81,
VAR46,
VAR25,
VAR47,
VAR43,
VAR26,
VAR56,
VAR77,
VAR18,
VAR76,
VAR48,
VAR36,
VAR12,
VAR63,
VAR23,
VAR38,
VAR44,
VAR91,
VAR45,
VAR87,
VAR59,
VAR69,
VAR34,
VAR30,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tapvgnd2/sky130_fd_sc_hdll__tapvgnd2.pp.blackbox.v | 1,271 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/stage3.v | 6,354 | module MODULE1 (
address,
VAR2,
VAR29);
input [11:0] address;
input VAR2;
output [11:0] VAR29;
tri1 VAR2;
wire [11:0] VAR17;
wire [11:0] VAR29 = VAR17[11:0];
VAR49 VAR10 (
.VAR48 (address),
.VAR23 (VAR2),
.VAR33 (VAR17),
.VAR6 (1'b0),
.VAR36 (1'b0),
.VAR40 (1'b1),
.VAR28 (1'b0),
.VAR35 (1'b0),
.VAR1 (1'b1),
.VAR9 (1'b1... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_phy_bb.v | 4,961 | module MODULE1 (
VAR79,
VAR3,
VAR28,
VAR51,
VAR45,
VAR49,
VAR67,
VAR72,
VAR54,
VAR9,
VAR41,
VAR39,
VAR14,
VAR4,
VAR64,
VAR24,
VAR76,
VAR20,
VAR32,
VAR19,
VAR46,
VAR44,
VAR5,
VAR34,
VAR29,
VAR69,
VAR22,
VAR2,
VAR80,
VAR33,
VAR43,
VAR73,
VAR47,
VAR52,
VAR1,
VAR25,
VAR16,
VAR21,
VAR53,
VAR40,
VAR61,
VAR57,
VAR58,
VAR11,
V... | lgpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/m26_rx/m26_rx.v | 1,864 | module MODULE1 #(
parameter VAR8 = 16'h0000,
parameter VAR22 = 16'h0000,
parameter VAR30 = 16,
parameter VAR7 = 0,
parameter VAR16 = 0
) (
input wire VAR23,
input wire [VAR30-1:0] VAR26,
inout wire [7:0] VAR4,
input wire VAR2,
input wire VAR3,
input wire VAR29,
input wire VAR1,
input wire VAR14,
input wire [1:0] VAR5,
... | bsd-3-clause |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/board/SGDMA_dispatcher/dispatcher.v | 16,653 | module MODULE1 (
clk,
reset,
VAR53,
VAR16,
VAR52,
VAR103,
VAR38,
VAR50,
VAR32,
VAR57,
VAR46,
VAR54, VAR83,
VAR96,
VAR51,
VAR56, VAR33, VAR87,
VAR104,
VAR80,
VAR84,
VAR82,
VAR79,
VAR27,
VAR19,
VAR55,
VAR77,
VAR2,
VAR26,
VAR45,
VAR90,
VAR97,
VAR63
);
function integer VAR72;
input integer VAR31;
begin
VAR31 = VAR31-1;
for... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.symbol.v | 1,233 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
endmodule | apache-2.0 |
yaqwsx/MandelbrotFPGA | VGA_Audio_PLL.v | 17,267 | module MODULE1 (
VAR86,
VAR55,
VAR70,
VAR71,
VAR64);
input VAR86;
input VAR55;
output VAR70;
output VAR71;
output VAR64;
wire [5:0] VAR19;
wire [0:0] VAR67 = 1'h0;
wire [2:2] VAR46 = VAR19[2:2];
wire [1:1] VAR52 = VAR19[1:1];
wire [0:0] VAR56 = VAR19[0:0];
wire VAR70 = VAR56;
wire VAR71 = VAR52;
wire VAR64 = VAR46;
wir... | mit |
AngelTerrones/MUSB | Hardware/musb/musb_core.v | 37,072 | module MODULE1#(
parameter VAR237 = 1, parameter VAR52 = 1, parameter VAR248 = 1 )(
input clk,
input VAR87,
output VAR228, input [4:0] VAR168, input VAR85, input [31:0] VAR138, input VAR38, input VAR165, output [31:0] VAR174, output [3:0] VAR268, output VAR143, input [31:0] VAR9, input VAR2, input VAR101, output [31:0]... | mit |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,039 | module MODULE1
(
VAR20,
VAR9,
VAR15) ;
input [0:0] VAR20;
output [0:0] VAR9;
output [0:0] VAR15;
wire [0:0] VAR1;
wire [0:0] VAR12;
wire [0:0] VAR35;
wire [0:0] VAR13;
wire [0:0] VAR16;
wire [0:0] VAR17;
wire [0:0] VAR2;
wire [0:0] VAR21;
wire [0:0] VAR32;
wire [0:0] VAR28;
VAR4 VAR24
(
.VAR22(VAR17),
.VAR34(VAR1[0:0])... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.pp.symbol.v | 1,380 | module MODULE1 (
input VAR4 ,
input VAR5 ,
input VAR9 ,
input VAR3 ,
output VAR6 ,
input VAR1 ,
input VAR2,
input VAR8,
input VAR7
);
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Design-of-various-multiplier-Array-Booth-Wallace--master/Wallace Tree Multiplier/Wallace Tree multiplier.v | 5,373 | module MODULE3(VAR75,VAR2,VAR135);
input [7:0] VAR75,VAR2;
output [15:0] VAR135;
wire [6:0] VAR48;
wire [7:0] VAR141,VAR45,VAR131,VAR161,VAR71,VAR147,VAR77,VAR153,VAR60;
wire [6:0] VAR151,VAR26,VAR158,VAR64,VAR114,VAR62;
wire [7:0] VAR36,VAR112,VAR110,VAR130,VAR84,VAR159,VAR176;
wire VAR1;
and VAR19(VAR135[0],VAR2[0],V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2_4.v | 2,117 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR8 ,
VAR2,
VAR1,
VAR3 ,
VAR7
);
output VAR9 ;
input VAR6 ;
input VAR8 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR7 ;
VAR4 VAR5 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR9,
VAR6,
VAR8
);
output VAR9;
... | apache-2.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/SyncBit.v | 3,272 | module MODULE1 (
VAR1,
VAR5,
VAR11,
VAR7,
VAR10,
VAR12
);
parameter VAR4 = 1'b0;
input VAR1;
input VAR5;
input VAR7;
input VAR10;
input VAR11;
output VAR12;
reg VAR2;
reg VAR8, VAR6;
assign VAR12 = VAR6 ;
always @(posedge VAR1 or negedge VAR5)
begin
if (VAR5 ==0)
begin
VAR2 <= VAR3 VAR4 ;
end else
begin
if ( V... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_ctrl.v | 4,540 | module MODULE1 (
clk ,
VAR18 ,
VAR16 ,
VAR12 ,
VAR4 ,
VAR11 ,
VAR3 ,
VAR2 ,
VAR15 ,
VAR10 ,
VAR1
);
input [1-1:0] clk ; input [1-1:0] VAR18 ; input [1-1:0] VAR16 ; output [1-1:0] VAR12 ; output VAR4 ;
output [1-1:0] VAR11 ; output [1-1:0] VAR3 ; input [1-1:0] VAR2 ; output [1-1:0] VAR15 ; output [2-1:0] VAR10 ; input [... | gpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/coe_tlb.v | 14,668 | module MODULE1 (
clk ,
VAR39 ,
VAR34 ,
VAR41 ,
VAR38 ,
VAR36 ,
VAR56 ,
VAR6 ,
VAR13 ,
VAR57 ,
VAR35 ,
VAR40 ,
VAR55 ,
VAR26 ,
VAR45 ,
VAR28 ,
VAR52 ,
VAR1 ,
VAR19 ,
VAR61
);
localparam VAR47 = 2'b00 ,
VAR18 = 2'b01 ,
VAR29 = 2'b10 ,
VAR12 = 2'b11 ;
localparam VAR2 = 0 ,
VAR51 = 1 ;
input clk ;
input VAR39 ;
input VAR34... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b.functional.v | 1,393 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR4;
wire VAR3 ;
wire VAR8;
not VAR5 (VAR3 , VAR7 );
and VAR1 (VAR8, VAR3, VAR4 );
buf VAR2 (VAR6 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32o/sky130_fd_sc_ms__a32o.behavioral.v | 1,676 | module MODULE1 (
VAR12 ,
VAR10,
VAR3,
VAR14,
VAR8,
VAR15
);
output VAR12 ;
input VAR10;
input VAR3;
input VAR14;
input VAR8;
input VAR15;
supply1 VAR13;
supply0 VAR11;
supply1 VAR5 ;
supply0 VAR17 ;
wire VAR2 ;
wire VAR16 ;
wire VAR9;
and VAR6 (VAR2 , VAR14, VAR10, VAR3 );
and VAR7 (VAR16 , VAR8, VAR15 );
or VAR1 (VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.functional.v | 1,468 | module MODULE1 (
VAR8 ,
VAR3,
VAR6,
VAR9,
VAR10
);
output VAR8 ;
input VAR3;
input VAR6;
input VAR9;
input VAR10;
wire VAR7 ;
wire VAR4;
or VAR5 (VAR7 , VAR6, VAR3 );
nand VAR2 (VAR4, VAR10, VAR7, VAR9);
buf VAR1 (VAR8 , VAR4 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/eeba0a9c/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v | 8,785 | module MODULE1 #
(
parameter VAR30 = "none",
parameter integer VAR35 = 1,
parameter integer VAR18 = 32,
parameter integer VAR20 = 32,
parameter integer VAR19 = 0,
parameter integer VAR41 = 1,
parameter integer VAR21 = 1,
parameter integer VAR27 = 1
)
(
input wire VAR5,
input wire VAR12,
input wire VAR4,
input wire VAR8... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3/alt_ddrx_controller.v | 75,916 | module MODULE1 # (
parameter
VAR339 = "VAR119",
VAR343 = 3,
VAR58 = 25,
VAR158 = 32,
VAR392 = "VAR60",
VAR382 = 2,
VAR312 = 1,
VAR360 = VAR382,
VAR390 = VAR382,
VAR146 = 13, VAR355 = 13, VAR278 = 10, VAR272 = 3, VAR145 = 1,
VAR163 = 8,
VAR326 = 1,
VAR216 = 2,
VAR31 = 2, VAR341 = 10,
VAR366 = 4,
VAR247 = 4,
VAR371 = 8,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.pp.symbol.v | 1,291 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR4 ,
input VAR6 ,
output VAR3 ,
input VAR9 ,
input VAR2,
input VAR7,
input VAR1
);
endmodule | apache-2.0 |
jayrandez/Processor | vga.v | 1,329 | module MODULE1(
VAR31,
VAR30,
VAR28,
VAR1,
VAR3,
VAR8,
VAR6,
VAR10,
VAR35,
VAR9
);
input wire VAR31;
input wire[3:0] VAR1;
input wire[3:0] VAR3;
input wire[3:0] VAR8;
input wire[11:0] VAR6;
input wire[7:0] VAR10;
input wire VAR35;
output wire VAR30;
output wire VAR28;
output wire[7:0] VAR9;
wire VAR14;
wire[9:0] VAR22;... | apache-2.0 |
Murailab-arch/magukara | cores/measure/rtl/measure_core.v | 16,189 | module MODULE1 # (
parameter VAR39 = {8'd10, 8'd0, 8'd21, 8'd105},
VAR99 = 128'h37760000000000210000000000000105,
VAR96 = 48'h003776000101
) (
input VAR16,
input VAR73,
input VAR70,
input VAR77,
input [31:0] VAR34,
output [7:0] VAR30,
output VAR67,
input VAR26,
input [7:0] VAR80,
input VAR98,
input VAR59,
output reg [3... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/upd77c25_datrom.v | 9,258 | module MODULE1 (
VAR46,
VAR25,
VAR41,
VAR36,
VAR10,
VAR55);
input VAR46;
input [15:0] VAR25;
input [10:0] VAR41;
input [10:0] VAR36;
input VAR10;
output [15:0] VAR55;
tri1 VAR46;
tri0 VAR10;
wire [15:0] VAR44;
wire [15:0] VAR55 = VAR44[15:0];
VAR51 VAR35 (
.VAR9 (VAR36),
.VAR22 (VAR41),
.VAR45 (VAR46),
.VAR39 (VAR25),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver.functional.pp.v | 1,799 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR7,
VAR12,
VAR1 ,
VAR8
);
output VAR4 ;
input VAR3 ;
input VAR7;
input VAR12;
input VAR1 ;
input VAR8 ;
wire VAR9 ;
wire VAR6;
buf VAR5 (VAR9 , VAR3 );
VAR11 VAR2 (VAR6, VAR9, VAR7, VAR12);
buf VAR10 (VAR4 , VAR6 );
endmodule | apache-2.0 |
desirajusantosh/FIFO | synchronous_fifo.v | 1,174 | module MODULE1(VAR2, VAR10, VAR8, VAR7, VAR5, VAR4, VAR6, rst);
parameter VAR9 = 16;
parameter VAR13 = 16;
parameter VAR11 = 5;
input VAR2;
input VAR10;
input VAR8;
input rst;
input [VAR9 - 1 : 0] VAR4;
output VAR7;
output VAR5;
output [VAR9 - 1 : 0] VAR6;
wire VAR7;
wire VAR5;
reg [VAR9 - 1 : 0 ] memory [0 : VAR13 - 1... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/slaveSendpacket.v | 8,821 | module MODULE1 (VAR11, VAR14, VAR21, VAR41, VAR23, VAR24, VAR43, clk, VAR2, VAR10, VAR16, rst, VAR17, VAR31);
input [3:0] VAR11;
input VAR41;
input VAR23;
input clk;
input [7:0] VAR2;
input VAR10;
input rst;
input VAR31;
output [7:0] VAR14;
output [7:0] VAR21;
output VAR24;
output VAR43;
output VAR16;
output VAR17;
wir... | gpl-3.0 |
martinmiranda14/Digitales | Lab5/DD.v | 3,330 | module MODULE1
(
input clk, input VAR9, input [31:0] in, output reg VAR10, output reg [31:0] VAR3 );
localparam VAR1 = 'b001;
localparam VAR8 = 'b010;
localparam VAR4 = 'b100;
reg [2:0] state, VAR5;
reg [31:0] VAR2, VAR7;
reg [31:0] VAR6;
localparam VAR11 = 32;
reg [5:0] counter, VAR12;
always @(*) begin
VAR5 = state;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai_1.v | 2,352 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR7 ,
VAR11 ,
VAR8,
VAR3,
VAR4 ,
VAR9
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR7 ;
input VAR11 ;
input VAR8;
input VAR3;
input VAR4 ;
input VAR9 ;
VAR6 VAR10 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s2s/sky130_fd_sc_ls__dlymetal6s2s_1.v | 2,157 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR3,
VAR8,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR2 ;
input VAR3;
input VAR8;
input VAR4 ;
input VAR6 ;
VAR5 VAR1 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7,
VAR2
);
output VAR7;
input VAR2;
supply1 VAR3;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR3,
VAR6,
VAR1 ,
VAR5
);
output VAR2 ;
input VAR4 ;
input VAR3;
input VAR6;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/fir_lp_15kHz/fir_lp_15kHz_stub.v | 1,495 | module MODULE1(VAR3, VAR5, VAR4, VAR1, VAR2, VAR6)
;
input VAR3;
input VAR5;
output VAR4;
input [15:0]VAR1;
output VAR2;
output [47:0]VAR6;
endmodule | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/vesa_tpg/vesa_tpg.v | 5,947 | module MODULE1(
VAR31,
reset,
VAR27,
VAR13,
VAR35,
VAR43,
VAR6,
VAR1 );
parameter VAR48 = 8;
input VAR31;
input reset;
input VAR27;
output VAR13;
output [VAR48*3-1:0] VAR35;
output VAR43;
output VAR6;
wire [1:0] VAR4;
input [2:0] VAR1;
assign VAR4 = 0;
parameter VAR40=1920;
parameter VAR25=1080;
localparam VAR5=3;
loca... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_pr/sky130_fd_sc_ms__udp_dff_pr.symbol.v | 1,317 | module MODULE1 (
input VAR3 ,
output VAR1 ,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3.blackbox.v | 1,212 | module MODULE1 (
VAR2,
VAR3,
VAR4,
VAR5
);
output VAR2;
input VAR3;
input VAR4;
input VAR5;
supply1 VAR6;
supply0 VAR1;
endmodule | apache-2.0 |
jotego/jt51 | hdl/filter/jt51_sincf.v | 1,342 | module MODULE1 #(parameter VAR2=1, VAR5=5)
(
input clk,
input [VAR2-1:0] din,
output reg [VAR5-1:0] dout
);
reg [VAR2-1:0] VAR3[23:0];
genvar VAR1;
generate
for (VAR1=23; VAR1>0; VAR1=VAR1-1) begin: VAR4
always @(posedge clk)
VAR3[VAR1] <= VAR3[VAR1-1];
end
endgenerate
always @(posedge clk) begin
VAR3[0] <= din;
dout <... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/hif.v | 10,883 | module MODULE1
(
input VAR84,
input VAR39,
input VAR92,
input VAR57,
input VAR24,
input VAR22,
input VAR83,
input [22:0] VAR18, input [3:0] VAR71, input VAR20, input VAR102, input VAR54, input VAR3, input VAR41,
input VAR59, input VAR10, input VAR46, input VAR67, input VAR91, input VAR85,
input VAR34,
input VAR42,
inpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31oi/sky130_fd_sc_lp__a31oi.functional.pp.v | 2,038 | module MODULE1 (
VAR16 ,
VAR6 ,
VAR4 ,
VAR8 ,
VAR7 ,
VAR11,
VAR3,
VAR5 ,
VAR1
);
output VAR16 ;
input VAR6 ;
input VAR4 ;
input VAR8 ;
input VAR7 ;
input VAR11;
input VAR3;
input VAR5 ;
input VAR1 ;
wire VAR12 ;
wire VAR10 ;
wire VAR17;
and VAR15 (VAR12 , VAR8, VAR6, VAR4 );
nor VAR9 (VAR10 , VAR7, VAR12 );
VAR13 VAR14... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v2_0_ecc_merge_enc.v | 5,947 | module MODULE1
parameter VAR27 = 100,
parameter VAR7 = 64,
parameter VAR17 = 72,
parameter VAR21 = 4,
parameter VAR6 = 1,
parameter VAR3 = 64,
parameter VAR24 = 72,
parameter VAR14 = 8,
parameter VAR20 = 4
)
(
VAR23, VAR11,
clk, rst, VAR28, VAR10, VAR22, VAR15, VAR13
);
input clk;
input rst;
input [2*VAR20*VAR7-1:0] VA... | bsd-2-clause |
mbus/mbus | mbus/verilog/no_pwr_gating_yesheng/mbus_ctrl_layer_wrapper.v | 2,726 | module MODULE1
(
input VAR31,
input VAR23,
input VAR5,
input VAR10,
output VAR11,
output VAR26,
input [VAR34-1:0] VAR4,
input [VAR32-1:0] VAR25,
input VAR19,
input VAR8,
input VAR13,
output VAR29,
output [VAR34-1:0] VAR33,
output [VAR32-1:0] VAR16,
output VAR27,
input VAR21,
output VAR12,
output VAR9,
output VAR17,
out... | apache-2.0 |
gr0bi42/BTCMiner | fpga/miner130.v | 3,235 | module MODULE1 (clk, reset, VAR2, VAR8, VAR16, VAR12, VAR9);
parameter VAR7 = 32'd0;
parameter VAR24 = 32'd1;
input clk, reset;
input [255:0] VAR2;
input [95:0] VAR8;
output reg [31:0] VAR16, VAR12, VAR9;
reg [31:0] VAR15;
wire [255:0] VAR11;
reg [7:0] VAR18 = 8'd0;
reg VAR5 = 1'b0;
reg VAR22;
reg VAR17, VAR25, VAR6, V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_12.behavioral.v | 1,106 | module MODULE1( VAR3, VAR5 );
input VAR3;
output VAR5;
VAR2 VAR4(.VAR3(VAR3),.VAR5(VAR5));
VAR2 VAR1(.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s_1.v | 2,033 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR6,
VAR1
);
output VAR5 ;
input VAR4 ;
input VAR6;
input VAR1;
VAR3 VAR2 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR6;
supply0 VAR1;
VAR3 VAR2 (
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xnor3/sky130_fd_sc_hd__xnor3.pp.symbol.v | 1,295 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR3 ,
output VAR2 ,
input VAR7 ,
input VAR6,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_ecc_encoder.v | 9,895 | module MODULE1 #
( parameter
VAR19 = 40,
VAR8 = 8,
VAR31 = 0,
VAR28 = 7,
VAR6 = 7,
VAR32 = 1
)
(
VAR25,
VAR4,
VAR29,
VAR22,
VAR33,
VAR12,
VAR9,
VAR10,
VAR20
);
localparam VAR16 = (VAR19 > 8) ? (VAR19 - VAR8) : (VAR19);
input VAR25;
input VAR4;
input [VAR28 - 1 : 0] VAR29;
input [VAR6 - 1 : 0] VAR22;
input [VAR32 - 1 : ... | gpl-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/SD_CLK.v | 2,113 | module MODULE1 (
address,
VAR2,
clk,
VAR1,
VAR9,
VAR8,
VAR6,
VAR5
)
;
output VAR6;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR1;
input VAR9;
input [ 31: 0] VAR8;
wire VAR4;
reg VAR7;
wire VAR6;
wire VAR3;
wire [ 31: 0] VAR5;
assign VAR4 = 1;
assign VAR3 = {1 {(address == 0)}} & VAR7;
a... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_bs_fsdq_2x.v | 1,877 | module MODULE1 (
VAR1,
VAR3, VAR6
);
output [2:0] VAR1;
input [2:0] VAR3;
input VAR6;
supply1 VAR7;
VAR12 VAR11 (
.VAR4 (VAR1[0]),
.VAR2 (VAR3[0]),
.VAR5 (VAR6),
.VAR9 (VAR7)
);
VAR12 VAR8 (
.VAR4 (VAR1[1]),
.VAR2 (VAR3[1]),
.VAR5 (VAR6),
.VAR9 (VAR7)
);
VAR12 VAR10 (
.VAR4 (VAR1[2]),
.VAR2 (VAR3[2]),
.VAR5 (VAR6),
.VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.symbol.v | 1,369 | module MODULE1 (
input [15:0] VAR5,
output VAR2,
input [15:0] VAR1
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_dataid_manager.v | 41,379 | module MODULE1
parameter
VAR91 = 8,
VAR90 = 1,
VAR56 = 1,
VAR111 = 6,
VAR47 = 1,
VAR119 = 4,
VAR71 = 7,
VAR105 = 5,
VAR55 = 2,
VAR83 = 0
)
(
VAR22,
VAR125,
VAR84,
VAR25,
VAR99,
VAR70,
VAR123,
VAR14,
VAR116,
VAR53,
VAR42,
VAR89,
VAR113,
VAR33,
VAR49,
VAR8,
VAR102,
VAR73,
VAR19,
VAR32,
VAR20,
VAR30,
VAR79,
VAR43,
VAR80,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.functional.pp.v | 2,231 | module MODULE1 (
VAR14 ,
VAR6,
VAR4,
VAR17 ,
VAR1 ,
VAR5,
VAR12,
VAR15 ,
VAR11
);
output VAR14 ;
input VAR6;
input VAR4;
input VAR17 ;
input VAR1 ;
input VAR5;
input VAR12;
input VAR15 ;
input VAR11 ;
wire VAR13 ;
wire VAR16 ;
wire VAR9 ;
wire VAR3;
and VAR2 (VAR13 , VAR17, VAR1 );
nor VAR10 (VAR16 , VAR6, VAR4 );
or V... | apache-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/serial_io.v | 3,361 | module MODULE1
( input VAR8,
input VAR10,
input VAR12,
input enable,
input reset,
inout wire VAR9,
output reg [6:0] VAR21,
output reg [31:0] VAR19,
output wire VAR2,
input wire [31:0] VAR15,
input wire [31:0] VAR6,
input wire [31:0] VAR18,
input wire [31:0] VAR5,
input wire [31:0] VAR14,
input wire [31:0] VAR13,
input ... | gpl-3.0 |
cpulabs/mist1032isa | src/core/pipeline_control/pipeline_control_irq_return.v | 5,042 | module MODULE1(
input wire VAR42,
input wire VAR1,
input wire VAR14,
input wire [31:0] VAR7,
input wire [31:0] VAR44,
input wire [31:0] VAR21,
input wire [31:0] VAR9,
input wire VAR26,
output wire VAR5,
output wire VAR20,
output wire [31:0] VAR41,
output wire VAR25,
output wire VAR8,
input wire VAR19,
output wire [1:0]... | bsd-2-clause |
kyzhai/NUNY | src/hardware/exam.v | 6,341 | module MODULE1 (
address,
VAR41,
VAR24);
input [11:0] address;
input VAR41;
output [11:0] VAR24;
tri1 VAR41;
wire [11:0] VAR34;
wire [11:0] VAR24 = VAR34[11:0];
VAR51 VAR32 (
.VAR5 (address),
.VAR48 (VAR41),
.VAR42 (VAR34),
.VAR26 (1'b0),
.VAR35 (1'b0),
.VAR52 (1'b1),
.VAR17 (1'b0),
.VAR22 (1'b0),
.VAR15 (1'b1),
.VAR43... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2o/sky130_fd_sc_hs__a2bb2o.behavioral.pp.v | 2,132 | module MODULE1 (
VAR2,
VAR10,
VAR11 ,
VAR4,
VAR14,
VAR13 ,
VAR6
);
input VAR2;
input VAR10;
output VAR11 ;
input VAR4;
input VAR14;
input VAR13 ;
input VAR6 ;
wire VAR6 VAR16 ;
wire VAR6 VAR1 ;
wire VAR9 ;
wire VAR15;
and VAR12 (VAR16 , VAR13, VAR6 );
nor VAR17 (VAR1 , VAR4, VAR14 );
or VAR8 (VAR9 , VAR1, VAR16 );
VAR7... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_port_buffer_32.v | 3,739 | module MODULE1 #(
parameter VAR6 = 9'd32,
parameter VAR12 = 512,
parameter VAR14 = VAR2((2**VAR2(VAR12))+1)
)
(
input VAR22,
input VAR3,
input [VAR6-1:0] VAR5, input VAR20, output [VAR14-1:0] VAR4,
output [VAR6-1:0] VAR8, input VAR9 );
reg VAR21=0, VAR21=0;
reg [VAR6-1:0] VAR11={VAR6{1'd0}}, VAR11={VAR6{1'd0}};
wire [V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a.behavioral.v | 1,662 | module MODULE1 (
VAR3 ,
VAR10,
VAR11,
VAR6,
VAR9,
VAR14
);
output VAR3 ;
input VAR10;
input VAR11;
input VAR6;
input VAR9;
input VAR14;
supply1 VAR15;
supply0 VAR13;
supply1 VAR7 ;
supply0 VAR1 ;
wire VAR2 ;
wire VAR12 ;
wire VAR5;
or VAR16 (VAR2 , VAR9, VAR6 );
or VAR4 (VAR12 , VAR11, VAR10 );
and VAR17 (VAR5, VAR2, V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/phy_rdlvl.v | 84,382 | module MODULE1 #
(
parameter VAR101 = 100, parameter VAR36 = 2, parameter VAR62 = 3333, parameter VAR71 = 64, parameter VAR85 = 3, parameter VAR4 = 8, parameter VAR141 = 8, parameter VAR122 = 1, parameter VAR148 = "VAR9", parameter VAR67 = "VAR17", parameter VAR124 = "VAR167" )
(
input clk,
input rst,
input VAR55,
outp... | lgpl-3.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_dds.v | 3,866 | module MODULE1 (
clk,
VAR10,
VAR13,
VAR15,
VAR5,
VAR6,
VAR16);
input clk;
input VAR10;
input [15:0] VAR13;
input [15:0] VAR15;
input [15:0] VAR5;
input [15:0] VAR6;
output [15:0] VAR16;
reg [15:0] VAR8 = 'd0;
reg [15:0] VAR16 = 'd0;
reg [15:0] VAR3 = 'd0;
reg [15:0] VAR9 = 'd0;
wire [15:0] VAR4;
wire [15:0] VAR14;
alwa... | lgpl-3.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.