repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/common/rtl/jbi_1r1w_16x160.v | 3,462 | module MODULE1 (
dout,
VAR27, VAR1, VAR16, din, VAR26, VAR14, VAR8, VAR19, VAR22,
VAR4, VAR15
);
input VAR27;
input VAR1;
input [3:0] VAR16;
input [159:0] din;
input VAR26;
input VAR14;
input [3:0] VAR8;
output [159:0] dout;
input VAR19;
input VAR22;
input VAR4;
input VAR15;
wire [159:0] VAR21;
wire [159:0] VAR20;
wire... | gpl-2.0 |
kDaniu/miaow | src/verilog/rtl/tracemon/vgpr_contention_tracker.v | 9,285 | module MODULE1
(
clk, rst, VAR40, VAR21,
VAR73, VAR90, VAR78,
VAR3, VAR56, VAR79,
VAR13, VAR7, VAR24,
VAR61, VAR19, VAR32,
VAR2, VAR74, VAR91, VAR36,
VAR33, VAR50, VAR10,
VAR37, VAR34, VAR54,
VAR75, VAR41, VAR6,
VAR26, VAR52, VAR93,
VAR95, VAR59, VAR20, VAR89, VAR76,
VAR16, VAR45, VAR1,
VAR30, VAR77, VAR47,
VAR28, VAR4... | bsd-3-clause |
carstenbru/fpga-log | spartanmc/hardware/pwm/src/pwm_output_stage.v | 1,316 | module MODULE1 (clk, reset, sel, VAR5, VAR8, VAR6);
parameter VAR1 = 32;
parameter VAR4 = 2'b00; parameter VAR9 = 2'b01;
parameter VAR3 = 2'b10;
input clk;
input reset;
input sel;
input [1:0] VAR5;
input [VAR1-1:0] VAR8;
output VAR6;
reg [VAR1-1:0] VAR2;
reg [VAR1-1:0] VAR7;
reg [VAR1-1:0] counter;
assign VAR6 = (count... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi_1.v | 2,366 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR11 ,
VAR5 ,
VAR3 ,
VAR8,
VAR9,
VAR10 ,
VAR6
);
output VAR2 ;
input VAR7 ;
input VAR11 ;
input VAR5 ;
input VAR3 ;
input VAR8;
input VAR9;
input VAR10 ;
input VAR6 ;
VAR4 VAR1 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai.functional.v | 1,442 | module MODULE1 (
VAR8 ,
VAR5,
VAR9,
VAR2
);
output VAR8 ;
input VAR5;
input VAR9;
input VAR2;
wire VAR1 ;
wire VAR4;
or VAR3 (VAR1 , VAR9, VAR5 );
nand VAR6 (VAR4, VAR2, VAR1 );
buf VAR7 (VAR8 , VAR4 );
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/or1200/or1200_xcv_ram32x8d.v | 10,023 | module MODULE1
(
VAR43,
VAR6,
VAR2,
VAR12,
VAR30,
VAR28,
VAR32
);
output [7:0] VAR43;
output [7:0] VAR6;
input [4:0] VAR2;
input [4:0] VAR30;
input [7:0] VAR12;
input VAR28;
input VAR32;
wire [7:0] VAR8;
wire [7:0] VAR15;
wire [7:0] VAR18;
wire [7:0] VAR38;
wire VAR22 ;
wire VAR42 ;
assign VAR43 = VAR30[4] ? VAR18 : VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.blackbox.v | 1,395 | module MODULE1 (
VAR6 ,
VAR8,
VAR3,
VAR10,
VAR5,
VAR2
);
output VAR6 ;
input VAR8;
input VAR3;
input VAR10;
input VAR5;
input VAR2;
supply1 VAR7;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.symbol.v | 1,357 | module MODULE1 (
input VAR1,
output VAR5
);
supply1 VAR4;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.blackbox.v | 1,334 | module MODULE1 (
VAR1 ,
VAR3,
VAR8,
VAR5
);
output VAR1 ;
input VAR3;
input VAR8;
input VAR5;
supply1 VAR6;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_1/synth/zqynq_lab_1_design_auto_pc_1.v | 12,851 | module MODULE1 (
VAR42,
VAR73,
VAR2,
VAR70,
VAR79,
VAR98,
VAR62,
VAR107,
VAR93,
VAR96,
VAR112,
VAR113,
VAR38,
VAR22,
VAR35,
VAR82,
VAR66,
VAR15,
VAR32,
VAR4,
VAR5,
VAR50,
VAR102,
VAR7,
VAR94,
VAR10,
VAR47,
VAR101,
VAR57,
VAR88,
VAR68,
VAR55,
VAR53,
VAR39,
VAR67,
VAR12,
VAR31,
VAR65,
VAR80,
VAR85,
VAR8,
VAR44,
VAR25,
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3.behavioral.pp.v | 2,186 | module MODULE1 (
VAR20 ,
VAR18 ,
VAR12 ,
VAR3 ,
VAR19,
VAR5,
VAR4 ,
VAR13
);
output VAR20 ;
input VAR18 ;
input VAR12 ;
input VAR3 ;
input VAR19;
input VAR5;
input VAR4 ;
input VAR13 ;
wire VAR16 ;
wire VAR17 ;
wire VAR7 ;
wire VAR11 ;
wire VAR1;
or VAR15 (VAR16 , VAR12, VAR18 );
and VAR9 (VAR17 , VAR16, VAR3 );
and VA... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_set_0_0/synth/zc702_set_0_0.v | 11,121 | module MODULE1 (
VAR69,
VAR52,
VAR9,
VAR48,
VAR61,
VAR3,
VAR1,
VAR29,
VAR67,
VAR33,
VAR49,
VAR24,
VAR14,
VAR7,
VAR53,
VAR54,
VAR41,
VAR20,
VAR55,
VAR25,
VAR60,
VAR17,
VAR31,
VAR56,
VAR58,
VAR18,
VAR68,
VAR40,
VAR8,
VAR22,
VAR23,
VAR63,
VAR26,
VAR62,
VAR35,
VAR11,
VAR5,
VAR21,
VAR64,
VAR59,
VAR32,
VAR36,
VAR34,
VAR57,
V... | mit |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/wrapper/usbHostCyc2Wrap.v | 5,008 | module MODULE1(
VAR30,
VAR24,
VAR18,
VAR26,
VAR14,
VAR23,
VAR29,
VAR8,
irq,
VAR17,
VAR13,
VAR19,
VAR27,
VAR11
);
input VAR30;
input VAR24;
input [7:0] VAR18;
input [7:0] VAR26;
output [7:0] VAR14;
input VAR23;
input VAR29;
output VAR8;
output irq;
input VAR17;
inout VAR13 ;
inout VAR19 ;
output VAR27 ;
output VAR11 ;
w... | gpl-3.0 |
AloriumTechnology/XLR8Float | extras/rtl/openxlr8.v | 15,095 | module MODULE1
parameter VAR40 = 1;
logic [VAR40-1:0][VAR26-1:0] VAR63;
logic [VAR40-1:0][VAR26-1:0] VAR8;
logic [VAR40-1:0][VAR26-1:0] VAR5;
logic [VAR40-1:0][VAR26-1:0] VAR22;
wire [7:0] VAR57;
wire VAR53;
wire [31:0] VAR16;
wire [31:0] VAR68;
wire [7:0] VAR56;
wire [31:0] VAR65;
wire [31:0] VAR32;
wire [31:0] VAR34;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4/sky130_fd_sc_hd__nor4_2.v | 2,275 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR5 ,
VAR1 ,
VAR10,
VAR3,
VAR11 ,
VAR2
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR5 ;
input VAR1 ;
input VAR10;
input VAR3;
input VAR11 ;
input VAR2 ;
VAR6 VAR7 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4b/sky130_fd_sc_hdll__or4b.functional.v | 1,410 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR8 ,
VAR10 ,
VAR6
);
output VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR6;
wire VAR1 ;
wire VAR3;
not VAR5 (VAR1 , VAR6 );
or VAR7 (VAR3, VAR1, VAR10, VAR8, VAR2);
buf VAR4 (VAR9 , VAR3 );
endmodule | apache-2.0 |
binary-logic/vj-uart | rtl/jtag_uart.v | 5,584 | module MODULE1(
input VAR37,
input VAR21,
input VAR12,
input [7:0] VAR40,
input VAR25,
output [7:0] VAR22,
output VAR14,
output VAR33,
output VAR20,
output VAR41
);
wire
[1:0] VAR29, VAR27;
wire
VAR46,
VAR34,
VAR43,
VAR28,
VAR48,
VAR16,
VAR44;
wire [7:0] VAR11; reg [7:0] VAR49 = 0; reg VAR3; reg VAR39; reg [1:0] VAR10;... | gpl-3.0 |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/hps_sdram_p0_acv_hard_addr_cmd_pads.v | 9,223 | module MODULE1(
VAR87,
VAR123,
VAR113,
VAR108,
VAR51,
VAR36,
VAR34,
VAR74,
VAR83,
VAR61,
VAR66,
VAR95,
VAR19,
VAR64,
VAR111,
VAR18,
VAR52,
VAR107,
VAR56,
VAR10,
VAR76,
VAR94,
VAR85,
VAR90,
VAR4,
VAR104,
VAR101,
VAR62,
VAR91
);
parameter VAR9 = "";
parameter VAR67 = "";
parameter VAR72 = "";
parameter VAR103 = "";
param... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.functional.v | 1,964 | module MODULE1 (
VAR7,
VAR1,
VAR9 ,
VAR8 ,
VAR3 ,
VAR5
);
input VAR7;
input VAR1;
output VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR5;
wire VAR2 ;
wire VAR11 ;
wire VAR13;
nand VAR6 (VAR2 , VAR3, VAR8 );
nand VAR14 (VAR11 , VAR5, VAR2 );
VAR4 VAR10 (VAR13, VAR11, VAR7, VAR1);
buf VAR12 (VAR9 , VAR13 );
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v | 3,593 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR5 ,
input wire VAR2 ,
output wire VAR9 ,
input wire VAR3 ,
output wire VAR11 ,
input wire VAR6 ,
output wire VAR4 ,
input wire VAR13 ,
output wire VAR10
);
localparam VAR14 = 2'b00;
localparam VAR12 = 2'b01;
localparam VAR1 = 2'b10;
localparam VAR7 = 2... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/lr_old_IPV4.v | 2,328 | module MODULE1(clk, VAR1,VAR18, VAR25, VAR15, VAR3, reset);
input clk;
input [13:2] VAR1;
input [13:2] VAR18;
input [31:0] VAR25;
output [31:0] VAR15;
input [3:0] VAR3;
input reset;
VAR17 VAR22(
.VAR29 (VAR1[13:2]),
.VAR28 (VAR18[13:2]),
.VAR10 (clk),
.VAR4 (VAR25[3:0]),
.VAR11 (VAR3[0]),
.VAR19 (VAR15[3:0])
);
VAR17 ... | mit |
Vadman97/ImageAES | des/DES/decrypt.v | 7,928 | module MODULE1(
input [63:0] VAR16,
input [63:0] VAR4,
output reg [63:0] VAR31,
output VAR9,
input clk,
input reset,
input enable,
input ack
);
reg [7:0] VAR19[7:0], VAR33[7:0], VAR14[7:0];
reg [10:0] state;
reg [55:0] VAR48; reg [15:0] VAR17[27:0], VAR37[27:0]; reg [15:0] VAR39[47:0]; reg [7:0] VAR35[31:0], VAR7[31:0]... | gpl-3.0 |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/ipcore_dir/Clock70HMz.v | 5,632 | module MODULE1
( input VAR26,
output VAR49,
input VAR2,
output VAR41
);
VAR23 VAR39
(.VAR28 (VAR11),
.VAR45 (VAR26));
wire VAR50;
wire VAR36;
wire [7:0] VAR29;
wire VAR21;
wire VAR6;
wire VAR9;
VAR25
.VAR27 (10),
.VAR15 (7),
.VAR33 ("VAR4"),
.VAR10 (10.0),
.VAR35 ("VAR46"),
.VAR48 ("1X"),
.VAR5 ("VAR31"),
.VAR1 (0),
.V... | mit |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/verilog/feedforward_p_uOut.v | 1,713 | module MODULE1 (VAR7, VAR10, VAR11, VAR13, VAR18, VAR12, VAR15, VAR8, clk);
parameter VAR2 = 32;
parameter VAR4 = 8;
parameter VAR1 = 140;
input[VAR4-1:0] VAR7;
input VAR10;
input[VAR2-1:0] VAR11;
input VAR13;
output reg[VAR2-1:0] VAR18;
input[VAR4-1:0] VAR12;
input VAR15;
output reg[VAR2-1:0] VAR8;
input clk;
reg [VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn_4.v | 2,150 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR9,
VAR1,
VAR8,
VAR7 ,
VAR2
);
output VAR3 ;
input VAR6 ;
input VAR9;
input VAR1;
input VAR8;
input VAR7 ;
input VAR2 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR6 ,
VAR9
);
output VAR3 ;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_2.behavioral.v | 1,101 | module MODULE1( VAR4, VAR1 );
input VAR4;
output VAR1;
VAR2 VAR5(.VAR4(VAR4),.VAR1(VAR1));
VAR2 VAR3(.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a222oi/sky130_fd_sc_hd__a222oi.functional.v | 1,735 | module MODULE1 (
VAR3 ,
VAR10,
VAR13,
VAR16,
VAR8,
VAR2,
VAR15
);
output VAR3 ;
input VAR10;
input VAR13;
input VAR16;
input VAR8;
input VAR2;
input VAR15;
wire VAR1 ;
wire VAR7 ;
wire VAR4 ;
wire VAR14;
nand VAR11 (VAR1 , VAR13, VAR10 );
nand VAR12 (VAR7 , VAR8, VAR16 );
nand VAR5 (VAR4 , VAR15, VAR2 );
and VAR9 (VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai_4.v | 2,202 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR1,
VAR6,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR2;
VAR3 VAR8 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5 ,
VAR7 ,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR4 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb.blackbox.v | 1,326 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR4 ,
VAR7,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR6;
supply1 VAR8;
supply0 VAR9;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2_1.v | 2,097 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR6 ,
VAR1,
VAR4,
VAR8 ,
VAR5
);
output VAR9 ;
input VAR2 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR8 ;
input VAR5 ;
VAR7 VAR3 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR9,
VAR2,
VAR6
);
output VAR9;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or3/sky130_fd_sc_ms__or3.behavioral.v | 1,361 | module MODULE1 (
VAR8,
VAR3,
VAR1,
VAR11
);
output VAR8;
input VAR3;
input VAR1;
input VAR11;
supply1 VAR10;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR7;
or VAR9 (VAR7, VAR1, VAR3, VAR11 );
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and3b/sky130_fd_sc_hdll__and3b.functional.pp.v | 1,981 | module MODULE1 (
VAR7 ,
VAR14 ,
VAR1 ,
VAR13 ,
VAR5,
VAR6,
VAR15 ,
VAR12
);
output VAR7 ;
input VAR14 ;
input VAR1 ;
input VAR13 ;
input VAR5;
input VAR6;
input VAR15 ;
input VAR12 ;
wire VAR2 ;
wire VAR9 ;
wire VAR4;
not VAR10 (VAR2 , VAR14 );
and VAR16 (VAR9 , VAR13, VAR2, VAR1 );
VAR11 VAR8 (VAR4, VAR9, VAR5, VAR6);... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab1/adders_prj/solution2/syn/verilog/adders.v | 2,022 | module MODULE1 (
VAR9,
VAR7,
VAR3,
VAR11,
VAR10,
VAR12
);
parameter VAR4 = 2'd1;
parameter VAR1 = 2'd2;
input VAR9;
input VAR7;
input [31:0] VAR3;
input [31:0] VAR11;
input [31:0] VAR10;
output [31:0] VAR12;
wire [31:0] VAR5;
reg [31:0] VAR6;
reg [1:0] VAR8;
wire VAR14;
wire VAR13;
reg [1:0] VAR2; | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.pp.blackbox.v | 1,436 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR4 ,
VAR10,
VAR3,
VAR7 ,
VAR8
);
output VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR4 ;
input VAR10;
input VAR3;
input VAR7 ;
input VAR8 ;
endmodule | apache-2.0 |
INTI-CMNB/Lattuino_IP_Core | FPGA/lattuino_1_v/wb_dev_intercon.v | 2,870 | module MODULE1
(
output [7:0] VAR40,
output VAR35,
input [7:0] VAR25,
input VAR33,
input [7:0] VAR12,
input VAR30,
input VAR38,
input [7:0] VAR42,
input VAR5,
output [7:0] VAR15,
output VAR21,
output [0:0] VAR20,
output VAR10,
input [7:0] VAR26,
input VAR11,
output [7:0] VAR14,
output VAR17,
output [0:0] VAR41,
output ... | gpl-2.0 |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/OSERDESE2.v | 3,100 | module MODULE1 (
VAR14, VAR19, VAR18, VAR15, VAR6, VAR25, VAR8,
VAR12, VAR40, VAR30, VAR4, VAR31, VAR35, VAR24, VAR9, VAR10, VAR27, VAR37, VAR5, VAR1,
VAR29, VAR39, VAR36, VAR16, VAR22, VAR26, VAR11
);
parameter VAR20=0;
parameter VAR34=0;
parameter VAR28=0;
parameter VAR7=0;
parameter VAR21=0;
parameter VAR17=0;
param... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21a/sky130_fd_sc_ms__o21a.behavioral.v | 1,508 | module MODULE1 (
VAR6 ,
VAR4,
VAR11,
VAR10
);
output VAR6 ;
input VAR4;
input VAR11;
input VAR10;
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR7 ;
wire VAR12 ;
wire VAR8;
or VAR2 (VAR12 , VAR11, VAR4 );
and VAR13 (VAR8, VAR12, VAR10 );
buf VAR9 (VAR6 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.v | 2,154 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR5 ,
VAR4 ,
VAR8,
VAR1 ,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR1 ;
input VAR2 ;
VAR3 VAR7 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR6,
VAR9
);
output VAR6;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver/sky130_fd_sc_lp__busdriver.pp.symbol.v | 1,342 | module MODULE1 (
input VAR6 ,
output VAR7 ,
input VAR4,
input VAR3 ,
input VAR1,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/prcfg/qpsk/qpsk_mod.v | 3,386 | module MODULE1 (
clk,
VAR8,
VAR4,
VAR18,
VAR10
);
input clk;
input [ 1:0] VAR8;
input VAR4;
output [15:0] VAR18;
output [15:0] VAR10;
wire [15:0] VAR5;
wire [15:0] VAR1;
wire [15:0] VAR12;
wire [15:0] VAR9;
assign VAR18 = VAR12;
assign VAR10 = VAR9;
VAR15 VAR20 (
.VAR2({6'b0, VAR8}),
.VAR11(VAR5),
.VAR16(VAR1)
);
VAR17... | gpl-3.0 |
secworks/uart | src/rtl/uart_core.v | 15,075 | module MODULE1(
input wire clk,
input wire VAR48,
input wire [15 : 0] VAR27,
input wire [3 : 0] VAR44,
input wire [1 : 0] VAR13,
input wire VAR11,
output wire VAR4,
output wire VAR69,
output [7 : 0] VAR65,
input wire VAR54,
input wire VAR19,
input wire [7 : 0] VAR23,
output wire VAR35
);
localparam VAR70 = 0;
localpara... | bsd-2-clause |
Koheron/zynq-sdk | fpga/cores/redp_adc_v1_0/redp_adc.v | 1,186 | module MODULE1 #
(
)
(
input [ 14-1: 0] VAR7 , input [ 14-1: 0] VAR9 , input VAR8 ,
output [ 2-1: 0] VAR4 , output VAR1 ,
output [ 14-1: 0] VAR5 , output [ 14-1: 0] VAR2 , input VAR10 );
assign VAR1 = 1'b1 ;
assign VAR4 = 2'b10;
reg [14-1: 0] VAR3 ;
reg [14-1: 0] VAR6 ;
always @(posedge VAR8) begin
VAR3 <= VAR7[14-1:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2.functional.v | 1,305 | module MODULE1 (
VAR6,
VAR3,
VAR2
);
output VAR6;
input VAR3;
input VAR2;
wire VAR4;
xnor VAR5 (VAR4, VAR3, VAR2 );
buf VAR1 (VAR6 , VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi.blackbox.v | 1,403 | module MODULE1 (
VAR5 ,
VAR1,
VAR7,
VAR9,
VAR3,
VAR8
);
output VAR5 ;
input VAR1;
input VAR7;
input VAR9;
input VAR3;
input VAR8;
supply1 VAR6;
supply0 VAR10;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
gigglesninja/digital-system-design | Lab4/ipcore_dir/mult12x12l2.v | 12,370 | module MODULE1 (
clk, VAR94, VAR80, VAR111
);
input clk;
output [23 : 0] VAR94;
input [11 : 0] VAR80;
input [11 : 0] VAR111;
wire \VAR60/VAR96 ;
wire \VAR60/VAR26 ;
wire \VAR60/VAR109 ;
wire \VAR60/VAR22 ;
wire \VAR60/VAR119 ;
wire \VAR60/VAR1 ;
wire \VAR60/VAR118 ;
wire \VAR60/VAR31 ;
wire \VAR60/VAR88 ;
wire \VAR60/V... | gpl-2.0 |
vvk/sysrek | uart_echo/UART_Tx.v | 1,570 | module MODULE1(
input VAR3,
input [7:0]VAR8,
input VAR5,
input VAR10,
output VAR11,
output reg VAR14 = 1'b1
);
parameter VAR1 = 1000000;
parameter VAR6 = 9600;
localparam VAR9 = VAR1/(VAR6*2);
reg [VAR13(VAR9)-1:0]VAR4 = 0;
reg VAR2;
reg VAR7 = 1'b0;
reg [9:0]VAR12 = 10'h3FF;
reg [3:0]counter = 0;
assign VAR11 = VAR12[... | gpl-2.0 |
DSDL2016/project2 | source/synthesizer/VGA_Audio_PLL.v | 11,461 | module MODULE1 (
VAR40,
VAR43,
VAR59,
VAR45,
VAR49);
input VAR40;
input VAR43;
output VAR59;
output VAR45;
output VAR49;
wire [5:0] VAR15;
wire [0:0] VAR11 = 1'h0;
wire [2:2] VAR27 = VAR15[2:2];
wire [1:1] VAR16 = VAR15[1:1];
wire [0:0] VAR3 = VAR15[0:0];
wire VAR59 = VAR3;
wire VAR45 = VAR16;
wire VAR49 = VAR27;
wire ... | mit |
r2t2sdr/r2t2 | fpga/modules/cores/axis_packetizer_v1_0/src/axis_packetizer.v | 1,856 | module MODULE1 #
(
parameter integer VAR13 = 32,
parameter integer VAR8 = 32
)
(
input wire VAR1,
input wire VAR6,
input wire [VAR8-1:0] VAR11,
output wire VAR14,
input wire [VAR13-1:0] VAR9,
input wire VAR12,
input wire VAR17,
output wire [VAR13-1:0] VAR10,
output wire VAR19,
output wire VAR16
);
reg [VAR8-1:0] VAR5, ... | gpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2_ctrl_module/ddr2_ctrl_input.v | 7,569 | module MODULE1(
VAR47,
VAR48,
VAR25,
VAR50,
VAR44,
VAR36,
VAR32,
VAR18,
VAR52,
VAR34,
VAR7,
VAR21,
VAR41,
VAR2,
VAR5,
VAR22,
VAR37,
VAR26,
VAR17,
VAR31
);
input VAR47;
input VAR48;
input VAR50;
input VAR25;
output[25:0] VAR44;
output VAR32;
output VAR36;
output VAR7;
output[31:0] VAR18;
output[3:0] VAR52;
output[3:0] V... | apache-2.0 |
fredyamalves/Collision-detection-for-a-CPU-FPGA-heterogeneous-System | Verilog design/dCalcVectorLength3.v | 3,320 | module MODULE1
(
input VAR38,
input [31:0] VAR7,
input [31:0] VAR6,
input [31:0] VAR39,
input [31:0] b1,
input [31:0] VAR46,
input [31:0] VAR15,
input VAR4,
output reg [31:0] VAR35,
output reg VAR45
);
wire VAR44;
wire [31:0] VAR34;
wire VAR40;
wire VAR17;
wire VAR29;
wire VAR12;
wire [31:0] VAR43;
wire VAR14;
wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.pp.blackbox.v | 1,342 | module MODULE1 (
VAR2,
VAR3 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR7,
VAR5,
VAR9 ,
VAR4
);
output VAR2;
output VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR7;
input VAR5;
input VAR9 ;
input VAR4 ;
endmodule | apache-2.0 |
Kipsora/MIPS-CPU | source/machine/machine.v | 2,033 | module MODULE1(
input wire VAR12,
input wire reset
);
wire[VAR22] VAR18;
wire[VAR1] VAR11;
wire VAR6;
wire VAR17;
wire[VAR22] VAR3;
wire[VAR13] VAR26;
wire[VAR1] VAR27;
wire[VAR1] VAR21;
wire VAR2;
VAR9 VAR24(
.VAR12(VAR12),
.reset(reset),
.VAR10(VAR11),
.VAR21(VAR21),
.VAR18(VAR18),
.VAR6(VAR6),
.VAR17(VAR17),
.VAR26(... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_1024x32.v | 11,971 | module MODULE1(
VAR50, VAR52, VAR9,
clk, rst, VAR48, VAR36, VAR53, addr, VAR33, VAR27
);
parameter VAR10 = 10;
parameter VAR46 = 32;
input VAR50;
input [VAR23 - 1:0] VAR9;
output VAR52;
input clk; input rst; input VAR48; input VAR36; input VAR53; input [VAR10-1:0] addr; input [VAR46-1:0] VAR33; output [VAR46-1:0] VAR27... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/triple_speed_ethernet-library/altera_tse_pcs.v | 7,088 | module MODULE1 (
VAR28, VAR45, VAR1, VAR13, VAR18, VAR34, VAR6, VAR5, VAR29,
VAR52,
VAR19,
VAR40,
VAR10,
VAR46,
VAR3,
VAR25,
VAR17,
VAR39,
VAR36,
VAR32,
VAR47,
VAR31,
VAR30,
VAR7,
VAR9,
VAR48,
VAR50,
VAR44,
VAR51,
VAR2,
VAR11,
VAR27,
VAR24,
VAR37,
VAR26,
VAR21,
VAR8,
VAR49,
VAR15,
VAR16,
VAR14,
VAR20,
VAR41,
VAR42);
pa... | apache-2.0 |
cathalmccabe/PYNQ | boards/ip/audio_direct_1.1/src/audio_direct_path.v | 1,091 | module MODULE1(
input wire VAR17,
input wire VAR1,
input wire VAR7,
output wire VAR14,
output wire VAR4,
output wire VAR6,
output wire VAR12
);
wire VAR13;
wire [15:0] VAR5;
reg VAR8;
reg [15:0] VAR3;
assign VAR12 = VAR8;
VAR2 VAR15 (
.clk(VAR17),
.en(VAR1),
.dout(VAR5),
.VAR14(VAR14),
.VAR11(VAR7)
);
always @(posedge ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.pp.symbol.v | 1,286 | module MODULE1 (
input VAR8 ,
input VAR5 ,
input VAR2 ,
output VAR4 ,
input VAR7 ,
input VAR1,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_one_fifo.v | 1,354 | module MODULE1 #(parameter VAR1(VAR9)
)
(input VAR8
, input VAR7
, output VAR13 , input [VAR9-1:0] VAR11 , input VAR17
, output VAR15 , output[VAR9-1:0] VAR14 , input VAR6 );
logic VAR2;
assign VAR13 = ~VAR2;
assign VAR15 = VAR2;
VAR5 #(.VAR9(1)) VAR12
(.VAR8
,.VAR7
,.VAR11(VAR2 ? ~VAR6: VAR17)
,.VAR14(VAR2)
);
VAR3 #(... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.blackbox.v | 1,232 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
supply1 VAR3;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
ncos/Xilinx-Verilog | INTERFACES/src/ARINC429/transmitter.v | 3,172 | module MODULE1 (
input clk, output wire VAR3, input [1:0] VAR14, output wire VAR25, input [7:0] VAR7, output wire VAR13, input [22:0]VAR15, output wire VAR21, input VAR20, output reg VAR1 = 0, output wire VAR10, output reg VAR12 = 0, output wire VAR9, output reg VAR6 = 0, output reg[5:0]VAR22 = 0, output reg VAR28 = 0,... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R1_P4_syn.v | 2,433 | module MODULE1 ( VAR59, VAR72, VAR32 );
input [7:0] VAR59;
input [7:0] VAR72;
output [8:0] VAR32;
wire VAR63, VAR53, VAR51, VAR77, VAR18, VAR64, VAR7,
VAR27, VAR2, VAR44, VAR17, VAR5, VAR81, VAR80, VAR74, VAR79, VAR50, VAR40, VAR37, VAR16, VAR15;
VAR52 VAR9 ( .VAR35(VAR72[1]), .VAR22(VAR59[1]), .VAR42(VAR63), .VAR48(
V... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_axi_basic_rx_pipeline.v | 26,730 | module MODULE1 #(
parameter VAR81 = 128, parameter VAR10 = "VAR27", parameter VAR78 = 1,
parameter VAR42 = (VAR81 == 128) ? 2 : 1, parameter VAR39 = VAR81 / 8 ) (
output reg [VAR81-1:0] VAR54, output reg VAR15, input VAR38, output [VAR39-1:0] VAR12, output VAR35, output reg [21:0] VAR61,
input [VAR81-1:0] VAR84, input ... | gpl-3.0 |
medav/conware | prototype/hw/axis2buffer.v | 2,269 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR5 = 4,
parameter VAR17 = 4
)(
clk,
VAR16,
VAR6,
VAR3,
VAR8,
VAR4,
VAR7,
VAR9,
VAR14,
VAR12,
VAR11
);
input clk;
input VAR16;
input [VAR13-1:0] VAR6;
input [VAR13-1:0] VAR3;
input [VAR13-1:0] VAR8;
input VAR4;
input VAR9;
output VAR7;
output [VAR5*VAR17-1:0] VAR14;
ou... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn_1.v | 2,312 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR2 ,
VAR9,
VAR8 ,
VAR7 ,
VAR1 ,
VAR6
);
output VAR5 ;
output VAR10 ;
input VAR2 ;
input VAR9;
input VAR8 ;
input VAR7 ;
input VAR1 ;
input VAR6 ;
VAR3 VAR4 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MOD... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_1.behavioral.v | 3,306 | module MODULE1( VAR6, VAR9, VAR4, VAR5, VAR7, VAR1 );
input VAR1, VAR7, VAR9, VAR6, VAR5;
output VAR4;
VAR3 VAR2(.VAR6(VAR6),.VAR9(VAR9),.VAR4(VAR4),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1));
VAR3 VAR8(.VAR6(VAR6),.VAR9(VAR9),.VAR4(VAR4),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr2/rtl/pad_ddr2.v | 11,619 | module MODULE1(VAR175 ,VAR27 ,VAR143 ,
VAR76 ,VAR112 ,VAR3 ,VAR142 ,
VAR136 ,VAR120 ,VAR48 ,VAR4 ,VAR41 ,VAR191
,VAR68 ,VAR185 ,VAR202 ,VAR57 ,VAR212
,VAR35 ,VAR30 ,VAR8 ,VAR116 ,
VAR171 ,VAR24 ,VAR58 ,
VAR188 ,VAR109 ,VAR34 ,
VAR198 ,VAR199 ,VAR84 ,VAR157 ,VAR20
,VAR206 ,VAR106 ,VAR193 ,VAR52 ,
VAR79 ,VAR26 ,VAR135 ,V... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/db_top_ram.v | 4,308 | module MODULE1(
VAR12 ,
VAR10 ,
VAR16 ,
VAR20 ,
VAR13 ,
VAR18 ,
VAR19 ,
VAR21 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR3 ,
VAR6 ,
VAR8
);
parameter VAR11 = 128 ;
parameter VAR1 = 5 ;
input VAR12 ; input VAR10 ; input VAR16 ; input VAR20 ; input [VAR1-1:0] VAR13; input [VAR11-1:0] VAR19; output [VAR11-1:0] VAR18;
input VAR21 ; input V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o.symbol.v | 1,394 | module MODULE1 (
input VAR3,
input VAR7,
input VAR9,
input VAR5,
input VAR4,
output VAR1
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR10 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
alexforencich/verilog-uart | example/ATLYS/fpga/rtl/sync_reset.v | 1,615 | module MODULE1 #(
parameter VAR3=2 )(
input wire clk,
input wire rst,
output wire VAR2
);
reg [VAR3-1:0] VAR1 = {VAR3{1'b1}};
assign VAR2 = VAR1[VAR3-1];
always @(posedge clk or posedge rst) begin
if (rst)
VAR1 <= {VAR3{1'b1}};
end
else
VAR1 <= {VAR1[VAR3-2:0], 1'b0};
end
endmodule | mit |
trander1/Queues-and-Adders | Verilog Files/RCA_bit16.v | 1,356 | module MODULE1(
output reg [15:0] VAR2,
output reg VAR16,
input [15:0]VAR4, VAR14
);
reg VAR15;
task VAR18(
output reg sum,VAR8,
input VAR13,VAR3,VAR15
);
reg VAR11, VAR7, VAR19;
begin
VAR19 = VAR13 ^ VAR3;
sum = VAR19 ^ VAR15;
VAR7 = VAR13 & VAR3;
VAR11 = VAR19 & VAR15;
VAR8 = VAR11 | VAR7;
end
endtask
task VAR17(
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21bai/sky130_fd_sc_ms__o21bai.behavioral.pp.v | 2,174 | module MODULE1 (
VAR18 ,
VAR10 ,
VAR9 ,
VAR2,
VAR13,
VAR16,
VAR14 ,
VAR11
);
output VAR18 ;
input VAR10 ;
input VAR9 ;
input VAR2;
input VAR13;
input VAR16;
input VAR14 ;
input VAR11 ;
wire VAR1 ;
wire VAR15 ;
wire VAR7 ;
wire VAR6;
not VAR8 (VAR1 , VAR2 );
or VAR4 (VAR15 , VAR9, VAR10 );
nand VAR12 (VAR7 , VAR1, VAR15... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T29-tristate/tristate1.v | 1,074 | module MODULE1 (
input wire clk, output wire VAR7);
parameter VAR6 = VAR5;
wire VAR9;
reg VAR8;
always @(posedge clk)
VAR8 <= 1'b1;
assign VAR7 = (VAR9) ? VAR8 : 1'VAR4;
VAR1 #(VAR6)
VAR2 (
.VAR3(clk),
.VAR10(VAR9)
);
endmodule | gpl-2.0 |
zhijian-liu/mips-cpu | src/cpu/latch/latch_id_ex.v | 2,180 | module MODULE1(
input VAR15 ,
input reset ,
input [ 5:0] VAR3 ,
input [31:0] VAR22 ,
output reg [31:0] VAR24 ,
input [ 7:0] VAR11 ,
output reg [ 7:0] VAR14 ,
input [ 2:0] VAR21 ,
output reg [ 2:0] VAR9 ,
input [31:0] VAR5 ,
output reg [31:0] VAR13 ,
input [31:0] VAR1 ,
output reg [31:0] VAR7 ,
input VAR6 ,
output reg V... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch3/integracion_fisica/front_end/db/SINGLE/FPU_Add_Subtract_Function_syn.v | 45,201 | module MODULE2 ( clk, rst, VAR194, VAR304, VAR273,
VAR370, VAR300, VAR50, VAR55, VAR216,
VAR72, VAR200, VAR234, VAR316, VAR34, VAR406,
VAR8, VAR99, VAR178, VAR244, VAR53, VAR155,
VAR334, VAR231, ready, VAR51 );
output [1:0] VAR53;
input clk, rst, VAR194, VAR304, VAR273, VAR370,
VAR300, VAR50;
output VAR55, VAR216, VAR7... | gpl-3.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/rs232_timer.v | 3,480 | module MODULE1(
clk,
VAR1, VAR4,
VAR9,
VAR10,
state
);
input clk;
input VAR1;
input VAR4;
input VAR9;
output reg VAR10;
output reg [VAR12-1:0] state;
reg [VAR6-1:0] counter; reg VAR5;
always @(posedge clk or negedge VAR1) begin
if (~VAR1)
begin
state <= #VAR11 VAR3;
counter <= #VAR11 VAR6'h0;
VAR10 <= #VAR11 0;
VAR5 <=... | gpl-2.0 |
Sajid3/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/sd_brams.v | 1,393 | module MODULE1 #(
parameter VAR6 = 32,
parameter VAR3 = 7
) (
input wire VAR4,
input wire VAR11,
input wire [VAR3-1:0] VAR1,
input wire [VAR6-1:0] VAR9,
output reg [VAR6-1:0] VAR12,
input wire VAR8,
input wire VAR10,
input wire [VAR3-1:0] VAR7,
input wire [VAR6-1:0] VAR5,
output reg [VAR6-1:0] VAR13
);
reg [VAR6-1:0] V... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_cu_binari_mv.v | 12,065 | module MODULE1(
VAR40 ,
VAR61 ,
VAR5 ,
VAR44 ,
VAR21 ,
VAR14 ,
VAR67 ,
VAR53 ,
VAR25 ,
VAR15 ,
VAR54 ,
VAR18 ,
VAR39 ,
VAR47 ,
VAR34 ,
VAR72 ,
VAR6 ,
VAR46 ,
VAR24 ,
VAR22 ,
VAR63 ,
VAR17 ,
VAR43 ,
VAR66 ,
VAR58 ,
VAR51 ,
VAR28 ,
VAR12 ,
VAR50 ,
VAR49 ,
VAR75
);
input [(4*VAR16+5):0] VAR40 ;
output [10:0] VAR61 ;
outpu... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.behavioral.v | 1,902 | module MODULE1 (
VAR14 ,
VAR16 ,
VAR9 ,
VAR8
);
output VAR14 ;
output VAR16 ;
input VAR9 ;
input VAR8;
supply1 VAR1;
supply0 VAR11;
supply1 VAR3 ;
supply0 VAR10 ;
wire VAR5 ;
wire VAR4;
wire VAR6 ;
reg VAR12 ;
VAR13 VAR2 (VAR5 , VAR6, VAR4, VAR12, VAR1, VAR11);
buf VAR15 (VAR14 , VAR5 );
not VAR7 (VAR16 , VAR5 );
endmo... | apache-2.0 |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/db/adc_sclk_altpll.v | 4,176 | module MODULE1
(
clk,
VAR41) ;
output [4:0] clk;
input [1:0] VAR41;
tri0 [1:0] VAR41;
wire [4:0] VAR29;
wire VAR11;
VAR15 VAR39
(
.VAR27(),
.clk(VAR29),
.VAR7(),
.VAR32(VAR11),
.VAR12(VAR11),
.VAR41(VAR41),
.VAR18(),
.VAR4(),
.VAR31(),
.VAR40(),
.VAR35(),
.VAR25()
,
.VAR3(1'b0),
.VAR42(1'b0),
.VAR24(1'b0),
.VAR14(1'b1)... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/16-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_mc_phy.v | 88,862 | module MODULE1
parameter VAR86 = 4'b1111,
parameter VAR437 = 4'b0000,
parameter VAR53 = 4'b0000,
parameter VAR139 = 4'b0000,
parameter VAR19 = 4'b0000,
parameter VAR22 = 4'hc,
parameter VAR10 = 4'hf,
parameter VAR117 = 4'hf,
parameter VAR112 = 4'hf,
parameter VAR77 = 4'hf,
parameter VAR134 = 0,
parameter VAR252 = "VAR1... | mit |
sudov/options-accel | vhls-dut-template/fifo.prj/sol/syn/verilog/dut.v | 3,182 | module MODULE1 (
VAR14,
VAR5,
VAR13,
VAR1,
VAR3,
VAR12,
VAR16,
VAR8
);
input VAR14;
input VAR5;
input [31:0] VAR13;
input VAR1;
output VAR3;
output [31:0] VAR12;
input VAR16;
output VAR8;
reg VAR3;
reg VAR8;
reg [31:0] VAR20 = 32'b00000000000000000000000000000000;
reg [0:0] VAR11 = 1'b0;
reg VAR2;
wire [31:0] VAR17;
re... | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_pps_counter_v1_0/axis_pps_counter.v | 1,361 | module MODULE1 #
(
parameter integer VAR6 = 32,
parameter integer VAR12 = 32
)
(
input wire VAR1,
input wire VAR3,
input wire VAR11,
output wire [VAR6-1:0] VAR9,
output wire VAR4
);
reg [VAR12-1:0] VAR8, VAR5;
reg VAR2, VAR10;
reg [2:0] VAR13;
wire VAR7;
always @(posedge VAR1)
begin
if(~VAR3)
begin
VAR8 <= {(VAR12){1'b... | mit |
Franderg/Ascensor | manejo_memoria.v | 10,733 | module MODULE1(
input clk,
input rst,
input VAR11,
input VAR6,
input [1:0] VAR1,
input [1:0] VAR8, input [3:0] VAR5, output reg [3:0] VAR2 );
reg [3:0] VAR9 [0:11];
reg [4:0] VAR10 = 11;
integer VAR3 = 0;
reg VAR7 = 0;
reg VAR4 = 0;
begin
begin
end
begin
end
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
b... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_2.functional.v | 1,264 | module MODULE1( VAR8, VAR11, VAR6, VAR2 );
input VAR2, VAR6, VAR8;
output VAR11;
wire VAR9;
not VAR3( VAR9, VAR2 );
wire VAR12;
not VAR5( VAR12, VAR6 );
wire VAR1;
and VAR4( VAR1, VAR9, VAR12 );
wire VAR13;
not VAR7( VAR13, VAR8 );
or VAR10( VAR11, VAR1, VAR13 );
endmodule | apache-2.0 |
efabless/openlane | designs/jpeg_encoder/src/dct_mac.v | 4,454 | module MODULE1(clk, VAR7, VAR5, din, VAR4, VAR2);
parameter VAR8 = 8;
parameter VAR9 = 16;
parameter VAR3 = VAR8 + VAR9; parameter VAR1 = VAR3 +3;
input clk; input VAR7; input VAR5; input [VAR8-1:0] din; input [VAR9-1:0] VAR4; output [VAR1-1:0] VAR2; reg [VAR1 -1:0] VAR2;
wire [VAR3-1:0] VAR10;
wire [VAR3-1:0] VAR6;
re... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3_lp.v | 2,182 | module MODULE2 (
VAR8 ,
VAR4 ,
VAR7 ,
VAR3 ,
VAR5,
VAR1,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR10 ;
input VAR9 ;
VAR2 VAR6 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_8.behavioral.pp.v | 1,236 | module MODULE1( VAR6, VAR1, VAR7, VAR2, VAR8 );
input VAR6, VAR1;
inout VAR2, VAR8;
output VAR7;
VAR5 VAR4(.VAR6(VAR6),.VAR1(VAR1),.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8));
VAR5 VAR3(.VAR6(VAR6),.VAR1(VAR1),.VAR7(VAR7),.VAR2(VAR2),.VAR8(VAR8)); | apache-2.0 |
fallen/milkymist-mmu | cores/minimac2/rtl/minimac2_ctlif.v | 3,354 | module MODULE1 #(
parameter VAR2 = 4'h0
) (
input VAR14,
input VAR21,
input [13:0] VAR29,
input VAR25,
input [31:0] VAR8,
output reg [31:0] VAR24,
output VAR32,
output VAR17,
output [1:0] VAR30,
input [1:0] VAR22,
input [10:0] VAR18,
input [10:0] VAR7,
output VAR23,
input VAR26,
output reg [10:0] VAR27,
output reg VAR3... | lgpl-3.0 |
andres-erbsen/sha3-verilog-mirror | low_throughput_core/rtl/round.v | 5,101 | module MODULE1(in, VAR24, out);
input [1599:0] in;
input [63:0] VAR24;
output [1599:0] out;
wire [63:0] VAR20[4:0][4:0];
wire [63:0] VAR9[4:0];
wire [63:0] VAR2[4:0][4:0], VAR7[4:0][4:0], VAR8[4:0][4:0], VAR16[4:0][4:0], VAR5[4:0][4:0];
genvar VAR1, VAR23;
generate
for(VAR23=0; VAR23<5; VAR23=VAR23+1)
begin : VAR22
for... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4_m.v | 2,441 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR9 ,
VAR12 ,
VAR10 ,
VAR8 ,
VAR7 ,
VAR11,
VAR4,
VAR1 ,
VAR13
);
output VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR12 ;
input VAR10 ;
input VAR8 ;
input VAR7 ;
input VAR11;
input VAR4;
input VAR1 ;
input VAR13 ;
VAR6 VAR5 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR10(VAR1... | apache-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_data_rec_fifo.v | 13,697 | module MODULE1(
rst,
VAR122,
VAR395,
din,
VAR28,
VAR339,
dout,
VAR119,
VAR201,
VAR154,
VAR120,
VAR182,
VAR232,
VAR240
);
input rst;
input VAR122;
input VAR395;
input [127 : 0] din;
input VAR28;
input VAR339;
output [255 : 0] dout;
output VAR119;
output VAR201;
output VAR154;
output VAR120;
output [9 : 0] VAR182;
output... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_gtx_cpllpd_ovrd.v | 4,128 | module MODULE1 (
input VAR4,
output VAR2,
output VAR5
);
reg [95:0] VAR3 = 96'hFFFFFFFFFFFFFFFFFFFFFFFF;
reg [127:0] VAR1 = 128'h000000000000000000000000000000FF;
always @(posedge VAR4)
begin
VAR3 <= {VAR3[94:0], 1'b0};
VAR1 <= {VAR1[126:0], 1'b0};
end
assign VAR2 = VAR3[95];
assign VAR5 = VAR1[127];
endmodule | gpl-3.0 |
peteasa/oh | src/common/hdl/oh_pwr_isohi.v | 1,025 | module MODULE1 #(parameter VAR2 = 1 )
(
input VAR4, input [VAR2-1:0] in, output [VAR2-1:0] out );
localparam VAR3 = VAR6;
generate
if(VAR3)
begin : VAR7
VAR5 VAR1 [VAR2-1:0] (.VAR4(VAR4),
.in(in[VAR2-1:0]),
.out(out[VAR2-1:0]));
end
else
begin : VAR8
assign out[VAR2-1:0] = {(VAR2){VAR4}} | in[VAR2-1:0];
end
endgenerate... | mit |
SymbiFlow/yosys-symbiflow-plugins | ql-qlf-plugin/qlf_k6n10/arith_map.v | 2,075 | module MODULE1(
module 80quicklogicalu (VAR27, VAR20, VAR25, VAR12, VAR19, VAR29, VAR5);
parameter VAR1 = 0;
parameter VAR21 = 0;
parameter VAR33 = 1;
parameter VAR30 = 1;
parameter VAR6 = 1;
input [VAR33-1:0] VAR27;
input [VAR30-1:0] VAR20;
output [VAR6-1:0] VAR19, VAR29;
input VAR25, VAR12;
output [VAR6-1:0] VAR5;
wi... | isc |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_pclk_align.v | 9,641 | module MODULE1
(
rst,
VAR4,
VAR15,
VAR1,
VAR47,
VAR18,
VAR33,
VAR20,
VAR44,
VAR31,
VAR30,
VAR10,
VAR34,
VAR14,
VAR21
);
input rst;
input VAR4;
input [7:0] VAR15;
input VAR1;
input VAR47;
input VAR18;
input VAR33;
input VAR31;
output VAR20;
output VAR44;
output VAR30;
output VAR10;
output VAR34;
input VAR14;
output VAR2... | mit |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_reg.v | 7,839 | module MODULE1(
input rst,
input clk, input [7:0] din,
input VAR33,
input VAR108,
input VAR41,
input VAR63,
input VAR65,
input VAR117,
input VAR51,
input VAR71,
input VAR93,
input VAR110,
input VAR80,
input [1:0] VAR57, input [2:0] VAR70,
input VAR52,
input VAR74,
output reg VAR105,
output [1:0] VAR29,
output [2:0] VAR... | gpl-3.0 |
alan4186/ParCNN | Hardware/v/nh_shift_reg_ctrl.v | 1,517 | module MODULE1(
input VAR16,
input reset,
input VAR15,
input [VAR20:0] VAR13,
output VAR4,
output [(VAR22*VAR14)-1:0] VAR12
);
wire [VAR20:0] VAR23 [VAR1-1:0];
wire [(VAR14*2)-1:0] VAR10;
reg [VAR20:0] VAR7 [VAR1-1:0][VAR1-1:0];
assign VAR4 = VAR10[0];
genvar VAR18;
genvar VAR6;
generate
for (VAR6=0; VAR6<VAR1-1; VAR6=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.behavioral.v | 3,349 | module MODULE1 (
VAR24 ,
VAR21 ,
VAR5 ,
VAR12 ,
VAR22 ,
VAR15 ,
VAR20 ,
VAR11
);
output VAR24 ;
output VAR21 ;
input VAR5 ;
input VAR12 ;
input VAR22 ;
input VAR15 ;
input VAR20 ;
input VAR11;
supply1 VAR6;
supply0 VAR25;
supply1 VAR16 ;
supply0 VAR7 ;
wire VAR1 ;
wire VAR8 ;
wire VAR27 ;
reg VAR13 ;
wire VAR38 ;
wire ... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/txr_engine_classic.v | 16,488 | parameter VAR30 = 1,
parameter VAR110 = 0,
parameter VAR128 = 64,
parameter VAR75 = 10,
parameter VAR96 = "VAR106")
( input VAR87,
input VAR44, output VAR38,
input [VAR9-1:0] VAR28,
input VAR126,
output [VAR116-1:0] VAR47,
output VAR46,
output VAR115,
output [VAR125(VAR116/32)-1:0] VAR80,
output VAR56,
output [VAR125(V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbp/sky130_fd_sc_ms__dfbbp.symbol.v | 1,467 | module MODULE1 (
input VAR9 ,
output VAR3 ,
output VAR2 ,
input VAR10,
input VAR1 ,
input VAR5
);
supply1 VAR7;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu9t5v0__dffsnq_1.behavioral.v | 3,726 | module MODULE1( VAR4, VAR15, VAR18, VAR3 );
input VAR4, VAR15, VAR18;
output VAR3;
reg VAR28;
VAR29 VAR20(.VAR4(VAR4),.VAR15(VAR15),.VAR18(VAR18),.VAR3(VAR3),.VAR28(VAR28));
VAR29 VAR16(.VAR4(VAR4),.VAR15(VAR15),.VAR18(VAR18),.VAR3(VAR3),.VAR28(VAR28));
not VAR17(VAR6,VAR15);
and VAR13(VAR32,VAR18,VAR6);
and VAR10(VAR2... | apache-2.0 |
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