repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy.v | 30,433 | module MODULE1 (
VAR76,
VAR13,
VAR32,
VAR85,
VAR20,
VAR56,
VAR59,
VAR55,
VAR58,
VAR21,
VAR33,
VAR35,
VAR45,
VAR36,
VAR98,
VAR50,
VAR39,
VAR92,
VAR9,
VAR42,
VAR29,
VAR61,
VAR10,
VAR105,
VAR94,
VAR7,
VAR16,
VAR63,
VAR51,
VAR37,
VAR88,
VAR67,
VAR26,
VAR34,
VAR69,
VAR62,
VAR93,
VAR72,
VAR83,
VAR31,
VAR44);
input [23:0] VAR... | lgpl-3.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/intra/ram_lcu_row_32x64.v | 4,125 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR13 ,
VAR14 ,
VAR4 ,
VAR21 ,
VAR9 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR12 ,
VAR19 ,
VAR7 ,
VAR15
);
parameter VAR11=32;
parameter VAR20=6;
input VAR1; input VAR6; input VAR13; input VAR14; input [VAR20-1:0] VAR4; input [VAR11-1:0] VAR9; output [VAR11-1:0] VAR21;
input VAR8; input VAR3; input VAR2;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd1/sky130_fd_sc_ls__clkdlyinv3sd1.pp.blackbox.v | 1,344 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3,
VAR2,
VAR6 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
klaNath/synth1 | lj24tx.v | 1,394 | module MODULE1(
input wire clk,
input wire VAR9,
output reg VAR10,
input wire VAR4,
input wire [31:0] VAR8,
output wire VAR6,
output wire VAR1,
output wire VAR2);
reg [5:0] VAR5;
reg [31:0] VAR3, VAR7;
assign VAR1 = ~clk & VAR9;
assign VAR6 = ~VAR5[4] & VAR9;
assign VAR2 = (VAR5[5] == 0)? VAR3[31] : VAR7[31];
always @(... | lgpl-3.0 |
asicguy/gplgpu | hdl/vga/sm_crt_ffwr_rd.v | 14,750 | module MODULE1
(
input VAR13,
input VAR23,
input VAR34,
input VAR18,
input VAR89,
input VAR108,
input VAR10,
input VAR37,
input VAR60,
input VAR80,
input VAR3,
input VAR26,
input VAR31,
input VAR50,
input VAR55,
input VAR7,
input VAR6,
input VAR100,
input VAR2,
input VAR62,
input VAR69,
input VAR93,
input VAR75,
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2.functional.pp.v | 1,792 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR13 ,
VAR6,
VAR4,
VAR5 ,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR13 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR1 ;
wire VAR10 ;
wire VAR12;
nand VAR2 (VAR10 , VAR13, VAR7 );
VAR9 VAR11 (VAR12, VAR10, VAR6, VAR4);
buf VAR8 (VAR3 , VAR12 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/buf/sky130_fd_sc_hd__buf_4.v | 1,993 | module MODULE2 (
VAR7 ,
VAR8 ,
VAR3,
VAR2,
VAR4 ,
VAR6
);
output VAR7 ;
input VAR8 ;
input VAR3;
input VAR2;
input VAR4 ;
input VAR6 ;
VAR5 VAR1 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR7,
VAR8
);
output VAR7;
input VAR8;
supply1 VAR3;
supply0 VAR2;... | apache-2.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/pp3/cells_map.v | 1,265 | module \VAR20 (
VAR3,
VAR1,
VAR18,
VAR21,
VAR9,
VAR12,
VAR6,
VAR14,
VAR17,
VAR5,
VAR11,
VAR19
);
input VAR3, VAR1, VAR18, VAR21, VAR9, VAR12, VAR6, VAR14, VAR17, VAR5, VAR11;
output VAR19;
VAR13 VAR16 (
.VAR3 (VAR3),
.VAR1 (VAR1),
.VAR18 (VAR18),
.VAR21 (VAR21),
.VAR9 (VAR9),
.VAR12 (VAR12),
.VAR6 (VAR6),
.VAR14 (VAR14... | apache-2.0 |
asicguy/gplgpu | hdl/altera_rams/ram_32x32_dp_be_bb.v | 8,942 | module MODULE1 (
VAR10,
VAR9,
VAR1,
VAR2,
VAR4,
VAR3,
VAR7,
VAR8,
VAR5,
VAR11,
VAR6);
input [4:0] VAR10;
input [4:0] VAR9;
input [3:0] VAR1;
input VAR2;
input VAR4;
input [31:0] VAR3;
input [31:0] VAR7;
input VAR8;
input VAR5;
output [31:0] VAR11;
output [31:0] VAR6;
tri1 [3:0] VAR1;
tri1 VAR2;
tri0 VAR8;
tri0 VAR5;
en... | gpl-3.0 |
cjbrigato/kigiv-for-proxmark3 | fpga/fpga_hf.v | 6,554 | module MODULE1(
input VAR24, output VAR69, input VAR63, input VAR23,
input VAR12, input VAR46, input VAR83,
output VAR34, output VAR67,
output VAR96, output VAR21, output VAR50, output VAR95,
input [7:0] VAR101, output VAR65, output VAR99,
output VAR62, output VAR94, input VAR20, output VAR13,
input VAR56, input VAR28,... | gpl-2.0 |
AndreaCorallo/KPU | rtl/wishbone/master/wb_master.v | 22,858 | module MODULE1 (
input clk,
input rst,
output reg VAR70,
input VAR12,
input VAR61,
input [31:0] VAR17,
input [31:0] VAR47,
input [31:0] VAR20,
input [27:0] VAR46,
input VAR66,
output reg VAR73 = 0,
output reg [31:0] VAR4 = 32'h0,
output reg [31:0] VAR36 = 32'h0,
output reg [31:0] VAR58 = 32'h0,
output wire [27:0] VAR69... | gpl-3.0 |
bluespec/Flute | src_bsc_lib_RTL/RevertReg.v | 1,451 | module MODULE1(VAR5, VAR2, VAR6, VAR3);
parameter VAR1 = 1;
parameter VAR4 = { VAR1 {1'b0} } ;
input VAR5;
input VAR3;
input [VAR1 - 1 : 0] VAR6;
output [VAR1 - 1 : 0] VAR2;
assign VAR2 = VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.pp.symbol.v | 1,340 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR3 ,
input VAR9 ,
output VAR1 ,
input VAR4 ,
input VAR7,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_2.behavioral.v | 1,718 | module MODULE1( VAR5, VAR10, VAR11 );
input VAR10, VAR5;
output VAR11;
reg VAR8;
VAR2 VAR9(.VAR5(VAR5),.VAR10(VAR10),.VAR11(VAR11),.VAR8(VAR8));
VAR2 VAR7(.VAR5(VAR5),.VAR10(VAR10),.VAR11(VAR11),.VAR8(VAR8));
not VAR4(VAR3,VAR10);
buf VAR1(VAR6,VAR10); | apache-2.0 |
iamllama/EE2020 | ee2020.srcs/sources_1/new/arb.v | 2,744 | module MODULE1(
input VAR37,
input VAR28,
output[11:0] VAR24,
output[11:0] VAR15
);
reg[63:0] VAR10 = 1000;
reg[63:0] VAR30 = 1000;
wire VAR12;
wire[7:0] VAR41;
wire VAR34;
VAR38 VAR3(VAR37, VAR28, VAR12, VAR41, VAR34);
reg VAR1 = 1;
reg[15:0] VAR8 = 0;
reg[7:0] VAR21 = 0;
reg[1:0] VAR14 = 0;
reg[31:0] VAR6 = 0;
reg[31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tap/sky130_fd_sc_ls__tap.behavioral.v | 1,152 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/slam_init.v | 119,970 | module MODULE1 () ;
integer VAR4;
wire VAR8 ;
| gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2.functional.v | 1,244 | module MODULE1 (
VAR4,
VAR6,
VAR2
);
output VAR4;
input VAR6;
input VAR2;
wire VAR5;
or VAR3 (VAR5, VAR2, VAR6 );
buf VAR1 (VAR4 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a_4.v | 2,348 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR3 ,
VAR11 ,
VAR4 ,
VAR6,
VAR10,
VAR1 ,
VAR7
);
output VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR11 ;
input VAR4 ;
input VAR6;
input VAR10;
input VAR1 ;
input VAR7 ;
VAR2 VAR9 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.... | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_custom_align.v | 20,070 | module MODULE1( VAR79, VAR42,
VAR57, VAR12, VAR83,
VAR14, VAR71, VAR37,
VAR56, VAR55, VAR8,
VAR22, VAR49, VAR25,
VAR20, VAR10, VAR13, VAR41,
enable);
parameter VAR64 = 1;
parameter VAR19 = 0;
parameter VAR73 = 1;
parameter VAR36 = 0;
parameter VAR6 = 1;
parameter VAR72 = 1;
input VAR79, VAR42;
input [26:0] VAR57;
input... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/verilog/convolve_kernel_control_s_axi.v | 9,024 | module MODULE1
VAR54 = 4,
VAR16 = 32
)(
input wire VAR19,
input wire VAR17,
input wire VAR35,
input wire [VAR54-1:0] VAR48,
input wire VAR57,
output wire VAR42,
input wire [VAR16-1:0] VAR46,
input wire [VAR16/8-1:0] VAR49,
input wire VAR34,
output wire VAR53,
output wire [1:0] VAR14,
output wire VAR2,
input wire VAR5,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.v | 2,221 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR9,
VAR6 ,
VAR5 ,
VAR8 ,
VAR7
);
output VAR4 ;
input VAR3 ;
input VAR9;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR7 ;
VAR1 VAR2 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR4 ,
VAR3 ,
VAR9
);
output VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.behavioral.pp.v | 1,200 | module MODULE1 (
VAR3,
VAR5 ,
VAR1 ,
VAR2 ,
VAR4
);
input VAR3;
input VAR5 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
ptracton/pmodacl2 | soc/uart_pb/pb_uart.v | 3,809 | module MODULE1 (
VAR14, VAR36, interrupt,
clk, reset, VAR19, VAR27, VAR13, VAR12, VAR35
) ;
input clk;
input reset;
input VAR19;
output VAR14;
input [7:0] VAR27;
input [7:0] VAR13;
output [7:0] VAR36;
input VAR12;
input VAR35;
output interrupt;
parameter VAR31 = 8'h00;
wire VAR22; wire VAR33; wire enable; wire [15:0] V... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_43.v | 28,347 | module MODULE2 (
clk,
reset,
VAR251,
VAR65,
VAR51,
VAR157,
VAR76
);
parameter VAR11 = 18;
parameter VAR185 = 43;
parameter VAR215 = 22;
localparam VAR68 = 44;
input clk;
input reset;
input VAR251;
input VAR65;
input [VAR11-1:0] VAR51; output VAR157;
output [VAR11-1:0] VAR76;
localparam VAR218 = 18; localparam VAR41 = 3... | mit |
jairov4/accel-oil | solution_kintex7/syn/verilog/bitset_next.v | 19,429 | module MODULE1 (
VAR116,
VAR19,
VAR72,
VAR37,
VAR53,
VAR108,
VAR91,
VAR99,
VAR46,
VAR88,
VAR65
);
input VAR116;
input VAR19;
input [31:0] VAR72;
input [7:0] VAR37;
input [7:0] VAR53;
input [31:0] VAR108;
output [7:0] VAR91;
output [7:0] VAR99;
output [31:0] VAR46;
output [0:0] VAR88;
input VAR65;
wire [4:0] VAR13;
reg ... | lgpl-3.0 |
Koheron/zynq-sdk | fpga/cores/averager_counter_v1_0/averager_counter.v | 2,538 | module MODULE1 #
(
parameter integer VAR5 = 13,
parameter integer VAR10 = 19
)
(
input wire VAR15,
input wire VAR7,
input wire [VAR5-1:0] VAR2,
input wire clk,
input wire VAR3,
input wire VAR4,
output reg ready,
output reg VAR18,
output reg [VAR10-1:0] VAR11,
output reg [VAR10-1:0] VAR14,
output reg VAR1,
output reg VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.blackbox.v | 1,418 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR10 ,
VAR1 ,
VAR2 ,
VAR8
);
output VAR6 ;
input VAR3 ;
input VAR10 ;
input VAR1 ;
input VAR2 ;
input VAR8;
supply1 VAR5;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3.behavioral.v | 1,361 | module MODULE1 (
VAR4,
VAR5,
VAR3,
VAR9
);
output VAR4;
input VAR5;
input VAR3;
input VAR9;
supply1 VAR10;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR11 ;
wire VAR6;
or VAR1 (VAR6, VAR3, VAR5, VAR9 );
buf VAR7 (VAR4 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi.pp.symbol.v | 1,396 | module MODULE1 (
input VAR7 ,
input VAR2 ,
input VAR5 ,
input VAR1 ,
input VAR4 ,
output VAR9 ,
input VAR3 ,
input VAR10,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/e_transmit/hdl/e_tx_arbiter.v | 4,182 | module MODULE1 (
VAR8, VAR15, VAR25, VAR11, VAR7,
VAR14, VAR13, VAR24, VAR12,
VAR3,
clk, reset, VAR1, VAR19, VAR9, VAR6,
VAR10, VAR23, VAR18, VAR17, VAR16
);
input clk;
input reset;
input [102:0] VAR1;
output VAR8;
input VAR19;
input [102:0] VAR9;
output VAR15;
input VAR6;
input [102:0] VAR10;
output VAR25;
input VAR23... | gpl-3.0 |
boylansr/Prop_Muse | P1V/P8X32A_Emulation/P8X32A_BeMicroCV/cog_alu.v | 5,059 | module MODULE1
(
input [5:0] VAR3,
input [31:0] VAR24,
input [31:0] VAR14,
input [8:0] VAR21,
input VAR18,
input VAR32,
input VAR5,
input [31:0] VAR16,
input VAR11,
output wr,
output [31:0] VAR9,
output VAR8,
output VAR26
);
wire [31:0] VAR15 = { VAR14[0], VAR14[1], VAR14[2], VAR14[3], VAR14[4], VAR14[5], VAR14[6], VAR... | gpl-3.0 |
makestuff/swled | fifo/verilog/fifo_rtl.v | 6,163 | module MODULE1(
input wire VAR12,
input wire VAR39,
input wire[6:0] VAR17,
input wire[7:0] VAR24, input wire VAR33, output wire VAR20,
output wire[7:0] VAR3, output wire VAR23, input wire VAR46,
output wire[7:0] VAR30, output wire[3:0] VAR8, output wire[7:0] VAR1, input wire[7:0] VAR47 );
wire[3:0] VAR32;
wire[15:0] VA... | gpl-3.0 |
jeasonstudio/DataStructureHomework | JIZU/regFile.v | 1,861 | module MODULE2(
VAR9,VAR2.VAR24,clk,reset VAR19,VAR15,VAR4,VAR22
);
output [31:0] VAR9,VAR2;
input [31:0] VAR24;
input clk,reset,VAR19;
input [4:0] VAR15,VAR4,VAR22;
wire [31:0] VAR8,VAR28;
wire [31:0] VAR14[31:0];
MODULE1 MODULE5(VAR8,VAR15);
assign VAR28[0] = VAR8[0]& VAR19;
assign VAR28[1] = VAR8[1]& VAR19;
assign V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22o/sky130_fd_sc_hs__a22o.functional.pp.v | 2,052 | module MODULE1 (
VAR12,
VAR13,
VAR8 ,
VAR9 ,
VAR15 ,
VAR17 ,
VAR10
);
input VAR12;
input VAR13;
output VAR8 ;
input VAR9 ;
input VAR15 ;
input VAR17 ;
input VAR10 ;
wire VAR10 VAR16 ;
wire VAR10 VAR3 ;
wire VAR6 ;
wire VAR4;
and VAR2 (VAR16 , VAR17, VAR10 );
and VAR7 (VAR3 , VAR9, VAR15 );
or VAR5 (VAR6 , VAR3, VAR16 )... | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_s00_regslice_1/synth/zc702_s00_regslice_1.v | 14,866 | module MODULE1 (
VAR93,
VAR22,
VAR29,
VAR103,
VAR24,
VAR39,
VAR28,
VAR60,
VAR25,
VAR70,
VAR51,
VAR21,
VAR85,
VAR9,
VAR82,
VAR52,
VAR112,
VAR97,
VAR74,
VAR67,
VAR68,
VAR66,
VAR45,
VAR54,
VAR59,
VAR104,
VAR8,
VAR90,
VAR55,
VAR91,
VAR44,
VAR20,
VAR36,
VAR87,
VAR23,
VAR7,
VAR80,
VAR64,
VAR3,
VAR107,
VAR89,
VAR84,
VAR56,
VA... | mit |
combinatorylogic/soc | backends/small1/hw/soc/logipi/spi.v | 3,915 | module MODULE1(
input clk,
input reset,
input VAR23,
input VAR1,
input VAR4,
output VAR6,
input [31:0] VAR22,
output VAR14, output VAR7, input VAR12,
output reg [31:0] VAR25,
output reg VAR28, input VAR20, output reg VAR21
);
reg [2:0] VAR19;
always @(posedge clk) VAR19 <= {VAR19[1:0], VAR4};
wire VAR16 = (VAR19[2:1]==... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_1/zynq_design_1_axi_gpio_0_1_stub.v | 2,357 | module MODULE1(VAR9, VAR14, VAR19,
VAR8, VAR17, VAR10, VAR15, VAR1, VAR3,
VAR16, VAR12, VAR11, VAR7, VAR5, VAR13,
VAR18, VAR4, VAR6, VAR2, VAR20)
;
input VAR9;
input VAR14;
input [8:0]VAR19;
input VAR8;
output VAR17;
input [31:0]VAR10;
input [3:0]VAR15;
input VAR1;
output VAR3;
output [1:0]VAR16;
output VAR12;
input VA... | mit |
borti4938/sd2snes | verilog/sd2snes_cx4/main.v | 23,504 | module MODULE1(
output [22:0] VAR207,
output VAR243,
input VAR38,
output VAR343,
input VAR277,
output [21:0] VAR207,
output VAR249,
output VAR320,
output VAR151,
output VAR202,
output VAR331,
input VAR39,
input VAR60,
input [23:0] VAR49,
input VAR165,
input VAR77,
input VAR352,
inout [7:0] VAR112,
input VAR190,
input V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o_4.v | 2,339 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR1,
VAR2,
VAR6 ,
VAR3
);
output VAR9 ;
input VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR2;
input VAR6 ;
input VAR3 ;
VAR8 VAR11 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR... | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/verif/mesh_3x3/packet_source.v | 28,612 | module MODULE1
(clk, reset, VAR72, VAR119, VAR108, VAR117, VAR184, VAR97, VAR127, VAR99);
parameter VAR104 = 0;
parameter VAR27 = 1000;
parameter VAR45 = 25;
parameter VAR31 = 32;
parameter VAR89 = 0;
parameter VAR80 = VAR160;
parameter VAR77 = 32;
parameter VAR90 = 2;
parameter VAR5 = 2;
localparam VAR67 = VAR161(VAR5... | gpl-2.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/hal.v | 16,369 | module MODULE1(
input wire VAR23, output wire clk, output wire reset,
input wire VAR18,
input wire VAR142,
output wire [ 31: 0] VAR103,
input wire [ 31: 0] VAR32,
input wire [ 25: 0] VAR47,
output wire VAR98,
output wire [ 1: 0] VAR174,
output wire [ 1: 0] VAR12,
output wire [ 12: 0] VAR175,
output wire [ 2: 0] VAR136,... | gpl-2.0 |
ShepardSiegel/ocpi | scripts/auguste/v6_mig37_patch20110411.v | 23,807 | module MODULE1 #
(
parameter VAR9 = 200,
parameter VAR60 = "VAR158",
parameter VAR99 = 6, parameter VAR2 = 1,
parameter VAR188 = 3,
parameter VAR157 = 2,
parameter VAR184 = 2500,
parameter VAR72 = "VAR152",
parameter VAR174 = "VAR149",
parameter VAR53 = "VAR149",
parameter VAR183 = 1,
parameter VAR175 = 3,
parameter VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.pp.blackbox.v | 1,173 | module MODULE1 (
VAR2,
VAR4,
VAR1 ,
VAR3
);
input VAR2;
input VAR4;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/Cache/L1/Distributed_RAM.v | 1,194 | module MODULE1(
VAR4,
VAR2,
VAR5,
VAR8,
VAR7
);
parameter VAR1 = 8;
parameter VAR10 = 8;
parameter VAR6 = 256;
input VAR4;
input VAR2;
input [VAR1-1:0]VAR5;
input [VAR10-1:0]VAR8;
output [VAR10-1:0]VAR7;
reg [VAR10-1:0] VAR9 [VAR6-1:0];
integer VAR3; | lgpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/bv-288/calculate_countid.v | 1,599 | module MODULE1(
clk,
reset,
VAR5,
VAR12,
VAR11,
VAR3
);
parameter VAR7 = 64;
parameter VAR2 = 6;
input clk;
input reset;
input VAR5;
input [VAR7-1:0] VAR12;
output wire VAR11;
output wire [VAR2-1:0] VAR3;
wire [VAR2-1:0] VAR9[0:VAR2];
wire [VAR2-1:0] VAR13[0:VAR2];
wire VAR17[0:VAR2];
wire [VAR7-1:0] VAR18[0:VAR2];
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/einvn/sky130_fd_sc_hvl__einvn.blackbox.v | 1,284 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR1
);
output VAR2 ;
input VAR6 ;
input VAR1;
supply1 VAR7;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_serdes_1sgx_x4_15625.v | 19,866 | module MODULE1 (
VAR107,
VAR30,
VAR69,
VAR111,
VAR59,
VAR16,
VAR112,
VAR4,
VAR121,
VAR38,
VAR50,
VAR22,
VAR53,
VAR82,
VAR54,
VAR37,
VAR12,
VAR115,
VAR85,
VAR68);
input [0:0] VAR107;
input [0:0] VAR30;
input [0:0] VAR69;
input [0:0] VAR111;
input [3:0] VAR59;
input [3:0] VAR16;
input [3:0] VAR112;
input [3:0] VAR4;
inpu... | mit |
DougFirErickson/parallella-hw | fpga/src/stubs/hdl/fifo_async_103x32.v | 1,697 | module MODULE1(rst, VAR5, VAR7, din, VAR6, VAR1, dout, VAR4, VAR2, VAR3)
;
input rst;
input VAR5;
input VAR7;
input [102:0]din;
input VAR6;
input VAR1;
output [102:0]dout;
output VAR4;
output VAR2;
output VAR3;
assign VAR2 =1'b0;
assign VAR3 =1'b0;
assign dout[102:0] =103'b0;
assign VAR4 =1'b0;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp.functional.v | 1,206 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2
);
output VAR4 ;
input VAR3 ;
input VAR2;
notif1 VAR1 (VAR4 , VAR3, VAR2 );
endmodule | apache-2.0 |
cynngah/virtualsynthesizer | bigasfuckram.v | 7,272 | module MODULE1 (
address,
VAR6,
VAR2,
VAR16,
VAR27);
input [4:0] address;
input VAR6;
input [26:0] VAR2;
input VAR16;
output [26:0] VAR27;
tri1 VAR6;
wire [26:0] VAR20;
wire [26:0] VAR27 = VAR20[26:0];
VAR30 VAR13 (
.VAR41 (address),
.VAR4 (VAR6),
.VAR54 (VAR2),
.VAR10 (VAR16),
.VAR40 (VAR20),
.VAR24 (1'b0),
.VAR8 (1'b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.behavioral.v | 1,140 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_hl_isowell_tap/sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.pp.blackbox.v | 1,579 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR3,
VAR6 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR5 ;
input VAR3;
input VAR6 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.symbol.v | 1,485 | module MODULE1 (
input VAR4 ,
output VAR8 ,
output VAR1 ,
input VAR10,
input VAR9 ,
input VAR6
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_wishbone.v | 71,467 | module MODULE1
(
VAR295, VAR110, VAR119,
VAR26, VAR202, VAR61,
VAR297,
VAR5,
VAR74, VAR214, VAR65,
VAR204, VAR157, VAR269,
VAR127, VAR2, VAR9,
VAR167, VAR96,
VAR161, VAR6, VAR113, VAR274, VAR40,
VAR125, VAR253, VAR218, VAR171, VAR121,
VAR178,
VAR227, VAR168, VAR199, VAR104, VAR237, VAR212,
VAR12,
VAR179, VAR229, VAR207... | gpl-2.0 |
fpgaminer/Open-Source-FPGA-Bitcoin-Miner | cores/unoptimized/sha256_transform.v | 5,140 | module MODULE2 #(
parameter VAR27 = 6'd4
) (
input clk,
input VAR36,
input [5:0] VAR18,
input [255:0] VAR11,
input [511:0] VAR1,
output reg [255:0] VAR3
);
localparam VAR23 = {
32'h428a2f98, 32'h71374491, 32'hb5c0fbcf, 32'he9b5dba5,
32'h3956c25b, 32'h59f111f1, 32'h923f82a4, 32'hab1c5ed5,
32'hd807aa98, 32'h12835b01, 32'... | gpl-3.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/6d1e8401c16773dd/mul_16_32_stub.v | 1,313 | module MODULE1(VAR1, VAR3, VAR4, VAR2)
;
input VAR1;
input [15:0]VAR3;
input [31:0]VAR4;
output [47:0]VAR2;
endmodule | bsd-3-clause |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/synthesis/spw_light.v | 69,929 | module MODULE1 (
output wire VAR63, input wire VAR1, input wire VAR23, output wire [1:0] VAR159, input wire [1:0] VAR195, input wire VAR4, input wire VAR193, input wire VAR216, input wire VAR154, output wire VAR24, output wire VAR95, output wire [12:0] VAR244, output wire [2:0] VAR209, output wire VAR302, output wire V... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/cam_ram_block.v | 5,514 | module MODULE1 (
clk,rst,
VAR3,VAR19,VAR4,VAR1,ready,
VAR5,VAR22
);
parameter VAR20 = 7;
parameter VAR16 = 5;
parameter VAR13 = (1<<VAR16);
input clk,rst,VAR1;
input [VAR16-1:0] VAR3;
input [VAR20-1:0] VAR19,VAR4;
input [VAR20-1:0] VAR5;
output [VAR13-1:0] VAR22;
wire [VAR13-1:0] VAR22;
output ready;
reg ready;
reg [VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i_lp.v | 2,222 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR7,
VAR3,
VAR8 ,
VAR10
);
output VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR8 ;
input VAR10 ;
VAR2 VAR6 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_fetchvertex.v | 5,688 | module MODULE1(
input VAR9,
input VAR43,
input VAR18,
output reg VAR57,
output [31:0] VAR32,
output [2:0] VAR10,
output VAR11,
output reg VAR50,
input VAR22,
input [31:0] VAR14,
input [6:0] VAR39,
input [6:0] VAR34,
input [28:0] VAR12,
input signed [11:0] VAR5,
input signed [11:0] VAR37,
input [10:0] VAR44,
input [10:0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b_2.v | 2,254 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR7 ,
VAR6 ,
VAR2,
VAR1,
VAR9 ,
VAR8
);
output VAR3 ;
input VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR2;
input VAR1;
input VAR9 ;
input VAR8 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/OCDP.v | 11,528 | module MODULE1 # (
parameter integer VAR24 = 32,
parameter integer VAR6 = 1,
parameter integer VAR18 = 1,
parameter integer VAR35 = 1 )
(
input [15 : 0] VAR15,
input VAR2,
input VAR4,
input [2 : 0] VAR25,
input VAR37,
input [3 : 0] VAR30,
input [31 : 0] VAR40,
input [31 : 0] VAR22,
output [1 : 0] VAR36,
output [31 : 0]... | lgpl-3.0 |
spesialstyrker/boula | src/bridge.v | 17,070 | module MODULE1(
input wire VAR53,
input wire [81:0] VAR23,
output wire VAR10,
inout wire VAR91,
output wire [VAR67 - 1:0] VAR93,
output wire [2:0] VAR35,
output wire [VAR26 - 1:0] VAR68,
output wire VAR3,
output wire VAR16,
input wire VAR24,
input wire [VAR26 - 1:0] VAR37,
input wire VAR34,
input wire [1:0] VAR38,
outp... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/top/mem_pipo_dp.v | 19,652 | module MODULE1 (
clk ,
VAR60 ,
VAR23 ,
VAR40 ,
VAR67 ,
VAR74 ,
VAR69 ,
VAR9 ,
VAR3 ,
VAR66 ,
VAR5 ,
VAR41 ,
VAR17 ,
VAR51 ,
VAR39 ,
VAR31 ,
VAR38 ,
VAR18 ,
VAR61 ,
VAR97 ,
VAR87 ,
VAR45 ,
VAR72 ,
VAR36 ,
VAR21
);
localparam VAR6 = 2'b00,
VAR68 = 2'b01,
VAR12 = 2'b10,
VAR46 = 2'b11;
input clk ; input VAR60 ;
input VAR23... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb_2.v | 2,325 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR8 ,
VAR9 ,
VAR3 ,
VAR1,
VAR5,
VAR7 ,
VAR4
);
output VAR11 ;
input VAR6 ;
input VAR8 ;
input VAR9 ;
input VAR3 ;
input VAR1;
input VAR5;
input VAR7 ;
input VAR4 ;
VAR2 VAR10 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mac_phy_10g.v | 6,925 | module MODULE1 #
(
parameter VAR20 = 64,
parameter VAR35 = (VAR20/8),
parameter VAR4 = (VAR20/32),
parameter VAR12 = 1,
parameter VAR67 = 1,
parameter VAR18 = 64,
parameter VAR54 = 4'h6,
parameter VAR81 = 16'h6666,
parameter VAR46 = 0,
parameter VAR78 = 96,
parameter VAR10 = VAR46,
parameter VAR3 = 16,
parameter VAR13 ... | mit |
ridecore/ridecore | src/fpga/alloc_issue_ino.v | 2,397 | module MODULE1 #(
parameter VAR18 = 2,
parameter VAR11 = 4
)
(
input wire clk,
input wire reset,
input wire [1:0] VAR23,
input wire [VAR11-1:0] VAR10,
input wire [VAR11-1:0] VAR13,
input wire [VAR11-1:0] VAR3,
input wire VAR1,
input wire VAR4,
input wire VAR16,
input wire VAR28,
output reg [VAR18-1:0] VAR7,
output wire... | bsd-3-clause |
kyzhai/NUNY | src/hardware/bg_bb.v | 4,946 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [23:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/debounce.v | 1,229 | module MODULE1(VAR1, VAR3, clk);
output VAR1; input VAR3; input clk;
reg [3:0] VAR2;
always @(posedge clk) begin
VAR2[3:1] <= VAR2[2:0];
VAR2[0] <= VAR3;
end
assign VAR1 = ((VAR2 == 4'b0000) ? 1'b0 : 1'b1);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv3sd2/sky130_fd_sc_ls__clkdlyinv3sd2.pp.blackbox.v | 1,344 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR6,
VAR4,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pipe_sync.v | 27,163 | module MODULE1 #
(
parameter VAR9 = "VAR99", parameter VAR71 = "VAR13", parameter VAR91 = "VAR102", parameter VAR66 = 0, parameter VAR105 = 0, parameter VAR89 = 1, parameter VAR55 = 3, parameter VAR19 = 0, parameter VAR38 = 0
)
(
input VAR12,
input VAR47,
input VAR27,
input VAR11,
input VAR22,
input VAR48,
input VAR108... | mit |
cambridgehackers/jregexp | regex-matchers/regex-matcher.v | 2,049 | module MODULE1(clk,
VAR1,
VAR14,
VAR10,
VAR16,
VAR8,
VAR2,
VAR3);
input clk, VAR1;
input [7:0] VAR14, VAR16;
input VAR10, VAR8;
output [7:0] VAR2;
output VAR3;
reg [7:0] VAR4;
wire [7:0] VAR9, VAR11;
wire [7:0] VAR13;
wire VAR6;
assign VAR9 = VAR15(VAR14);
assign VAR11 = VAR7(VAR4);
assign VAR13 = VAR5(VAR11, VAR9);
as... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.blackbox.v | 1,247 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR3;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_1/ghrd_10as066n2_avlmm_pr_freeze_bridge_1_bb.v | 2,895 | module MODULE1 (
input wire VAR10, input wire VAR26, output wire VAR30, input wire VAR18, output wire VAR3, input wire VAR20, input wire [31:0] VAR21, input wire [3:0] VAR1, input wire [31:0] VAR22, output wire [31:0] VAR17, input wire [2:0] VAR27, output wire VAR2, input wire VAR19, input wire VAR29, output wire [1:0]... | mit |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/Natural-Logarithm/LINEALIZADOR.v | 5,513 | module MODULE1 #(parameter VAR40 = 32)(
input wire VAR10, input wire [VAR40-1:0] VAR32, input wire VAR9, input wire VAR20, output wire VAR23, output wire VAR14,
output wire VAR45,
output wire VAR37,
output wire VAR48, output wire VAR51, output wire VAR26, output wire VAR21, output wire VAR29, output wire VAR15, output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.blackbox.v | 1,276 | module MODULE1 (
VAR2 ,
VAR1,
VAR7
);
output VAR2 ;
input VAR1;
input VAR7 ;
supply1 VAR5;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
sergev/vak-opensource | hardware/verilog/d-flop-rtl/dflop.v | 1,415 | module MODULE1;
reg VAR4; reg VAR1;
wire VAR3; wire VAR2; wire VAR8, VAR7, VAR5, VAR6; | apache-2.0 |
SiLab-Bonn/pyBAR | firmware/lx9/src/fei4_rx/receiver_logic.v | 6,771 | module MODULE1
parameter VAR34 = 10
)
(
input wire VAR62,
input wire VAR50,
input wire VAR37,
input wire VAR4,
input wire VAR35,
input wire VAR19,
input wire VAR61,
input wire read,
output wire [23:0] VAR70,
output wire VAR12,
output wire VAR11,
output wire VAR73,
output reg [7:0] VAR21,
output reg [7:0] VAR57,
output ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bushold0/sky130_fd_sc_lp__bushold0.pp.symbol.v | 1,403 | module MODULE1 (
inout VAR6 ,
input VAR4,
input VAR3 ,
input VAR2 ,
input VAR1 ,
input VAR5
);
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/hpdmc.v | 6,431 | module MODULE1 #(
parameter VAR77 = 4'h0,
parameter VAR59 = 26,
parameter VAR50 = 9
) (
input VAR45,
input VAR8,
input VAR3,
input VAR44,
input VAR25,
input [13:0] VAR14,
input VAR35,
input [31:0] VAR75,
output [31:0] VAR53,
input [VAR59-1:0] VAR62,
input VAR61,
input VAR19,
output VAR9,
input [7:0] VAR51,
input [63:0]... | lgpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/getpacket.v | 12,697 | module MODULE1 (VAR36, VAR55, VAR38, VAR71, VAR2, VAR61, VAR17, VAR63, VAR54, VAR74, VAR25, clk, VAR24, rst);
input [7:0] VAR36;
input VAR55;
input VAR71;
input [7:0] VAR63;
input VAR74; input clk;
input VAR24;
input rst;
output [7:0] VAR38;
output VAR2;
output VAR61;
output [7:0] VAR17;
output [3:0] VAR54;
output VAR2... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/ll_axis_bridge.v | 1,964 | module MODULE1 #
(
parameter VAR4 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR3,
input wire VAR10,
input wire VAR6,
input wire VAR7,
output wire VAR9,
output wire [VAR4-1:0] VAR8,
output wire VAR2,
input wire VAR5,
output wire VAR1
);
assign VAR8 = VAR3;
assign VAR2 = ~VAR7;
assign VAR1 = ~VAR6;
as... | mit |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_clockgen.v | 5,391 | module MODULE1(VAR9, VAR1, VAR11, VAR6, VAR3, VAR4);
parameter VAR10=1;
input VAR9; input VAR1; input [7:0] VAR11;
output VAR4; output VAR6; output VAR3;
reg VAR4;
reg [7:0] VAR7;
wire VAR2;
wire [7:0] VAR5;
wire [7:0] VAR8;
assign VAR8[7:0] = (VAR11[7:0]<2)? 8'h02 : VAR11[7:0]; assign VAR5[7:0] = (VAR8[7:0]>>1) - 1'b1... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_4.functional.pp.v | 3,028 | module MODULE1( VAR2, VAR13, VAR3, VAR6, VAR36, VAR21, VAR31, VAR33, VAR4 );
input VAR21, VAR31, VAR6, VAR36, VAR13, VAR3;
inout VAR33, VAR4;
output VAR2;
wire VAR7;
not VAR17( VAR7, VAR21 );
wire VAR14;
not VAR27( VAR14, VAR6 );
wire VAR20;
not VAR18( VAR20, VAR13 );
wire VAR8;
and VAR10( VAR8, VAR7, VAR14, VAR20 );
w... | apache-2.0 |
parallella/oh | common/hdl/oh_delay.v | 1,039 | module MODULE1 #(parameter VAR5 = 1, parameter VAR1 = 1 )
(
input [VAR5-1:0] in, input clk, output [VAR5-1:0] out );
reg [VAR5-1:0] VAR3[VAR1-1:0];
genvar VAR2;
generate
always @ (posedge clk)
VAR3[0]<=in[VAR5-1:0];
for(VAR2=1;VAR2<VAR1;VAR2=VAR2+1) begin: VAR4
always @ (posedge clk)
VAR3[VAR2]<=VAR3[VAR2-1];
end
endge... | mit |
theapi/de0-nano | pong/vga_driver.v | 3,777 | module MODULE1 (
VAR13,
VAR21,
VAR1,
VAR6,
VAR3,
VAR20,
VAR16,
VAR18,
VAR15,
VAR17
);
input VAR13;
input VAR21;
input [2:0] VAR1; output [10:0] VAR6;
output [10:0] VAR3;
output VAR20;
output VAR16;
output VAR18;
output VAR15;
output VAR17;
reg [10:0] VAR2; reg [10:0] VAR9; reg VAR12;
wire VAR11 = (VAR2 == 975);
reg [9:... | mit |
kevintownsend/spMatrixHelp | verilog/pattern_decoder.v | 14,966 | module MODULE1(rst, clk, VAR85, VAR68, VAR3, req, VAR27, VAR7, VAR53, VAR107, VAR93, VAR86, VAR51, VAR18);
parameter VAR16=32;
parameter VAR24=48;
parameter VAR33=64;
parameter VAR104=4;
parameter VAR31=VAR19(VAR104);
input rst;
input clk;
input VAR85;
input [VAR31-1:0] VAR68;
input [VAR33-1:0] VAR3;
output reg req;
in... | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_xbar_1/system_xbar_1_stub.v | 3,544 | module MODULE1(VAR20, VAR18, VAR32, VAR24,
VAR11, VAR23, VAR31, VAR15, VAR1, VAR10,
VAR25, VAR4, VAR26, VAR9, VAR5, VAR12,
VAR22, VAR14, VAR29, VAR28, VAR40, VAR38,
VAR34, VAR3, VAR30, VAR39, VAR27, VAR33,
VAR37, VAR17, VAR35, VAR6, VAR16, VAR36,
VAR21, VAR13, VAR19, VAR8, VAR2, VAR7)
;
input VAR20;
input VAR18;
input ... | apache-2.0 |
jhol/butterflylogic | lib/xilinx/ODDR2.v | 4,920 | module MODULE1 (VAR19, VAR21, VAR1, VAR20, VAR10, VAR7, VAR17, VAR12);
output VAR19;
input VAR21;
input VAR1;
input VAR20;
input VAR10;
input VAR7;
tri0 VAR16 = VAR11.VAR16;
input VAR17;
input VAR12;
parameter VAR5 = "VAR3";
parameter VAR4 = 1'b0;
parameter VAR13 = "VAR9";
pullup VAR8 (VAR20);
pulldown VAR2 (VAR17);
pu... | gpl-2.0 |
chasingegg/Computer_Systems | CS334_computer organization lab/source/lab4_register/register.v | 1,310 | module MODULE1(VAR10, VAR2,VAR3, VAR6,VAR4,VAR7,VAR5,VAR8);
input VAR10;
input [25:21] VAR2;
input [20:16] VAR3;
input [4:0] VAR6;
input [31:0] VAR4;
input VAR7;
output [31:0] VAR5;
output [31:0] VAR8;
reg[31:0] VAR1[31:0];
reg[31:0] VAR5;
reg[31:0] VAR8;
integer VAR9; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2.behavioral.v | 1,366 | module MODULE1 (
VAR4,
VAR5,
VAR2
);
output VAR4;
input VAR5;
input VAR2;
supply1 VAR1;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR9 ;
wire VAR10;
nand VAR8 (VAR10, VAR2, VAR5 );
buf VAR3 (VAR4 , VAR10 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.symbol.v | 1,295 | module MODULE1 (
input VAR4,
input VAR1,
output VAR5
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/mii_mgmt.v | 4,240 | module MODULE1
parameter VAR43=2500)
(input clk,
input [0:4] VAR22,
input [0:4] addr,
input [15:0] VAR7,
output [15:0] VAR17,
input req,
input VAR14,
output ack,
output VAR28,
inout VAR41);
localparam VAR36 = 8;
wire [VAR36-1:0] VAR16;
wire [VAR36-1:0] VAR24 = VAR16 + 1'b1;
VAR40 #(VAR36) VAR25
(.VAR39(clk), .VAR5(VAR2... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_2.functional.pp.v | 1,027 | module MODULE1( VAR12, VAR19, VAR16, VAR15, VAR18, VAR17, VAR14, VAR13 );
input VAR12, VAR19, VAR15, VAR16, VAR17, VAR14, VAR13;
output VAR18;
not VAR4( VAR5, VAR12 );
not VAR1( VAR6, VAR15 );
not VAR10( VAR3, VAR16 );
not VAR11( VAR2, VAR19 );
VAR8( VAR9, VAR3, VAR6, VAR5, VAR2, VAR13 );
not VAR7( VAR18, VAR9 );
endmo... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/ddr2/alt_ddrx_rank_monitor.v | 45,423 | module MODULE1 #
( parameter
VAR29 = 2,
VAR137 = 4,
VAR27 = 16, VAR16 = 3, VAR61 = "VAR18",
VAR149 = 2,
VAR111 = 1,
VAR43 = 4,
VAR50 = 4,
VAR167 = 8,
VAR146 = 0,
VAR122 = 4,
VAR80 = 3,
VAR48 = 4,
VAR90 = 10,
VAR71 = 4,
VAR100 = 5,
VAR130 = 6,
VAR118 = 3,
VAR36 = 5,
VAR181 = 4,
VAR77 = 4,
VAR105 = 3,
VAR150 = 5,
VAR125 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ai/sky130_fd_sc_hdll__o21ai.symbol.v | 1,357 | module MODULE1 (
input VAR1,
input VAR4,
input VAR6,
output VAR5
);
supply1 VAR7;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand2/sky130_fd_sc_hd__nand2_4.v | 2,097 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR8,
VAR1,
VAR7 ,
VAR9
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR8;
input VAR1;
input VAR7 ;
input VAR9 ;
VAR3 VAR5 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR4,
VAR2,
VAR6
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.pp.symbol.v | 1,322 | module MODULE1 (
input VAR6 ,
output VAR2 ,
input VAR4 ,
input VAR3,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_ctl_pad.v | 4,539 | module MODULE1(
VAR23, VAR26,
VAR16,
VAR15, VAR17, VAR27, VAR7, VAR8, VAR21,
VAR3, VAR19, VAR1, VAR5, VAR4, VAR12,
clk, VAR18, VAR22, VAR10
);
input VAR10; input [8:1] VAR22; input [8:1] VAR18; input clk; input VAR12; input VAR4; input VAR5; input VAR1; input VAR19; input VAR3; input VAR21; input VAR8; input VAR7; inpu... | gpl-2.0 |
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