repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gclk_center_3inv.v | 1,590 | module MODULE1(VAR2 ,VAR11 ,VAR8 ,VAR7 ,
VAR6 ,VAR1 );
output VAR2 ;
output VAR11 ;
output VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
VAR3 VAR5 (
.VAR9 (VAR11 ),
.VAR10 (VAR6 ) );
VAR3 VAR4 (
.VAR9 (VAR2 ),
.VAR10 (VAR7 ) );
VAR3 VAR12 (
.VAR9 (VAR8 ),
.VAR10 (VAR1 ) );
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtp/sky130_fd_sc_ls__dlrtp.behavioral.v | 2,290 | module MODULE1 (
VAR7 ,
VAR18,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR18;
input VAR5 ;
input VAR1 ;
supply1 VAR11;
supply0 VAR20;
supply1 VAR22 ;
supply0 VAR13 ;
wire VAR10 ;
reg VAR2 ;
wire VAR14 ;
wire VAR12 ;
wire VAR21 ;
wire VAR4;
wire VAR3 ;
wire VAR19 ;
wire VAR6 ;
wire VAR15 ;
not VAR8 (VAR10 , VAR4 );
VAR17 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap.functional.pp.v | 1,138 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
545/Atari7800 | Atari7800/Atari7800.srcs/sources_1/imports/NMOS/cpu.v | 33,463 | module MODULE1( clk, reset, VAR60, VAR177, VAR99, VAR89, VAR12, VAR193, VAR48, VAR55, VAR139);
input clk; input reset; output reg [15:0] VAR60; input [7:0] VAR177; output [7:0] VAR99; output VAR89; input VAR12; input VAR193; input VAR48;
output [15:0] VAR55;
output reg VAR139;
assign VAR55 = VAR75;
reg [15:0] VAR149; r... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu9t5v0__dffrsnq_1.behavioral.pp.v | 8,945 | module MODULE1( VAR69, VAR90, VAR28, VAR51, VAR50, VAR47, VAR66 );
input VAR69, VAR90, VAR51, VAR28;
inout VAR47, VAR66;
output VAR50;
reg VAR87;
VAR15 VAR18(.VAR69(VAR69),.VAR90(VAR90),.VAR28(VAR28),.VAR51(VAR51),.VAR50(VAR50),.VAR47(VAR47),.VAR66(VAR66),.VAR87(VAR87));
VAR15 VAR32(.VAR69(VAR69),.VAR90(VAR90),.VAR28(V... | apache-2.0 |
javierbrito29/papiGB | rtl/io.v | 2,912 | module MODULE1
(
input wire VAR4,
input wire VAR27,
input wire [5:0] VAR21, output wire [5:0] VAR26, output wire VAR9 );
wire [5:0] VAR6;
wire [5:0] VAR22;
wire [5:0] VAR25;
wire [5:0] VAR12;
wire [5:0] VAR5;
wire [5:0] VAR16;
wire [5:0] VAR23;
reg [5:0] VAR28;
VAR8 # ( 6 ) VAR24
(
.VAR4(VAR4),
.VAR27(VAR27),
.VAR15(1'... | gpl-2.0 |
dailypips/miaow | src/verilog/rtl/issue/barrier_wait.v | 4,798 | module MODULE1
(
VAR33, VAR34, VAR19,
VAR1, VAR8,
clk, rst, VAR25, VAR17, VAR36,
VAR18, VAR11, VAR38
);
input clk,rst;
input VAR25, VAR17;
input [VAR7-1:0] VAR36;
input [31:0] VAR18;
input [VAR7-1:0] VAR11;
input [3:0] VAR38;
wire VAR4;
output VAR33;
output [VAR7-1:0] VAR34;
output [VAR13-1:0] VAR19;
output [VAR13-1:0]... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.functional.v | 1,494 | module MODULE1( VAR12, VAR9, VAR15, VAR2, VAR14 );
input VAR14, VAR2, VAR9, VAR12;
output VAR15;
wire VAR10;
not VAR6( VAR10, VAR14 );
wire VAR16;
not VAR8( VAR16, VAR2 );
wire VAR1;
and VAR3( VAR1, VAR10, VAR16 );
wire VAR17;
not VAR4( VAR17, VAR9 );
wire VAR13;
not VAR11( VAR13, VAR12 );
wire VAR18;
and VAR7( VAR18, ... | apache-2.0 |
cpulabs/mist1032sa | src/core/execute/old_execute/logic.v | 3,005 | module MODULE1
parameter VAR15 = 32
)
(
input [4:0] VAR13,
input [VAR15-1:0] VAR4,
input [VAR15-1:0] VAR8,
output [VAR15-1:0] VAR6,
output VAR12,
output VAR14,
output VAR3,
output VAR9,
output VAR1
);
wire [31:0] VAR2;
assign VAR2 = VAR5(VAR13, VAR4, VAR8);
function [VAR15-1 : 0] VAR5;
input [4 : 0] VAR7;
input [VAR15-... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a.behavioral.v | 1,635 | module MODULE1 (
VAR17 ,
VAR15,
VAR4,
VAR3,
VAR7,
VAR2
);
output VAR17 ;
input VAR15;
input VAR4;
input VAR3;
input VAR7;
input VAR2;
supply1 VAR11;
supply0 VAR5;
supply1 VAR12 ;
supply0 VAR13 ;
wire VAR9 ;
wire VAR16 ;
wire VAR14;
or VAR8 (VAR9 , VAR4, VAR15, VAR3 );
or VAR6 (VAR16 , VAR2, VAR7 );
and VAR10 (VAR14, VA... | apache-2.0 |
tommythorn/yari | shared/rtl/soclib/rs232in.v | 2,229 | module MODULE1
( input wire VAR6,
input wire VAR3,
output reg VAR8 = 0,
output reg [7:0] VAR9 = 0);
parameter VAR13 = 57600;
parameter VAR10 = 25000000;
parameter period = (VAR10 + VAR13/2) / VAR13;
reg [16:0] VAR11 = 0;
wire [31:0] VAR1 = period - 2;
wire [31:0] VAR4 = (3 * period) / 2 - 2;
reg [ 7:0] VAR12 = 0;
reg [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.pp.symbol.v | 1,280 | module MODULE1 (
input VAR7 ,
input VAR5 ,
input VAR2 ,
output VAR3 ,
input VAR1 ,
input VAR8,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_1.behavioral.v | 18,884 | module MODULE1( VAR24, VAR271, VAR228, VAR61, VAR241, VAR122 );
input VAR61, VAR228, VAR24, VAR241, VAR271;
output VAR122;
reg VAR94;
VAR138 VAR156(.VAR24(VAR24),.VAR271(VAR271),.VAR228(VAR228),.VAR61(VAR61),.VAR241(VAR241),.VAR122(VAR122),.VAR94(VAR94));
VAR138 VAR211(.VAR24(VAR24),.VAR271(VAR271),.VAR228(VAR228),.VAR... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_clkgn_shadreg.v | 43,743 | module MODULE1 (
VAR226, VAR95, VAR228,
VAR52, VAR74, VAR11,
VAR232, VAR88, VAR160,
VAR42, VAR185, VAR178,
VAR17, VAR101, VAR39,
VAR102, VAR152, VAR125,
VAR164, VAR116, VAR96, VAR231,
VAR200, VAR77, VAR186, VAR235,
VAR92, VAR85, VAR40,
VAR135, VAR157, VAR67, VAR192,
VAR158, VAR12, VAR119,
VAR70, VAR100, VAR177, VAR154,... | gpl-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_stream_to_vector_converter.v | 5,000 | module MODULE1(
VAR11, VAR5, VAR1,
VAR13, VAR4, VAR8,
VAR14, VAR16, VAR15, VAR2);
parameter VAR9 = 32;
input VAR11, VAR5, VAR1, VAR14, VAR15;
input [VAR9-1:0] VAR13;
output [VAR9-1:0] VAR4;
output [VAR9-1:0] VAR8;
output VAR16;
output VAR2;
reg [VAR9-1:0] VAR10 ;
reg VAR7;
wire VAR12;
always@(posedge VAR5 or negedge VA... | mit |
Jam-G/MIPS | EX.v | 4,531 | module MODULE3(
input [31:0] VAR46,
input [31:0] VAR40,
input [1:0] VAR16,
input VAR49,
input VAR21,
input [3:0] VAR67,
input [1:0] VAR29,
input VAR64,
input [1:0] VAR43,
input [31:0] VAR38,
input [31:0] VAR34,
input [4:0] VAR28,VAR22,VAR45,
input [31:0] VAR50,
input [4:0] VAR13,
input [7:0] VAR51,
input [7:0] VAR32,
i... | lgpl-3.0 |
SymbiFlow/prjxray-experiments-archive-2017 | clb_bused/top.v | 1,645 | module MODULE2(input clk, VAR13, VAR9, output do);
localparam integer VAR5 = 256;
localparam integer VAR20 = 256;
reg [VAR5-1:0] din;
wire [VAR20-1:0] dout;
reg [VAR5-1:0] VAR11;
reg [VAR20-1:0] VAR10;
always @(posedge clk) begin
VAR11 <= {VAR11, VAR9};
VAR10 <= {VAR10, VAR11[VAR5-1]};
if (VAR13) begin
din <= VAR11;
VA... | isc |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu7t5v0__xnor2_2.behavioral.v | 1,429 | module MODULE1( VAR6, VAR4, VAR1 );
input VAR4, VAR6;
output VAR1;
VAR5 VAR3(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1));
VAR5 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/controller/bank_common.v | 17,377 | module MODULE1 #
(
parameter VAR4 = 100,
parameter VAR57 = 2,
parameter VAR19 = 1,
parameter VAR103 = 4,
parameter VAR53 = 2,
parameter VAR9 = 0,
parameter VAR8 = 44,
parameter VAR31 = 2,
parameter VAR42 = 4,
parameter VAR80 = 5, parameter VAR105 = 64
)
(
VAR65, VAR55, VAR86, VAR96,
VAR82, VAR54, VAR110, VAR40, VAR61,
... | lgpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/tx_data_send.v | 2,908 | module MODULE1(
input VAR3,
input VAR7,
input VAR1,
input VAR2,
input VAR8,
input [7:0] VAR12,
input VAR14,
input [8:0] VAR13,
input VAR17,
input VAR10,
output reg [8:0] VAR11,
output reg [8:0] VAR15,
output reg VAR5,
output reg VAR9,
output reg [7:0] VAR4,
output reg VAR6
);
wire VAR16;
assign VAR16 = (VAR17 & VAR10)?... | gpl-3.0 |
YosysHQ/yosys | techlibs/intel/max10/cells_map.v | 2,318 | module \VAR1 (input VAR22, output VAR12);
VAR15 VAR10 (.VAR4(VAR12), .VAR8(VAR22), .VAR24(1'b0));
endmodule
module \VAR7 (input VAR22, output VAR12);
VAR19 VAR10 (.VAR4(VAR12), .VAR8(VAR22), .VAR18(1'b1));
endmodule
module MODULE1 (VAR23, VAR9);
parameter VAR20 = 0;
parameter VAR6 = 0;
input [VAR20-1:0] VAR23;
output V... | isc |
anderson1008/NOCulator | hring/hw/bless_mc/rcMC.v | 2,468 | module MODULE2(
VAR26,
VAR28
);
input [VAR14-1:0] VAR26;
output [VAR29-1:0] VAR28;
assign VAR28 [0] = |(VAR26 & VAR20);
assign VAR28 [1] = |(VAR26 & VAR15);
assign VAR28 [2] = |(VAR26 & VAR16);
assign VAR28 [3] = |(VAR26 & VAR31);
assign VAR28 [4] = |(VAR26 & VAR12);
endmodule
module MODULE2(
VAR26,
VAR25, VAR28
);
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.functional.pp.v | 2,336 | module MODULE1 (
VAR8 ,
VAR16 ,
VAR5 ,
VAR4 ,
VAR19 ,
VAR13,
VAR10 ,
VAR17 ,
VAR14 ,
VAR6
);
output VAR8 ;
output VAR16 ;
input VAR5 ;
input VAR4 ;
input VAR19 ;
input VAR13;
input VAR10 ;
input VAR17 ;
input VAR14 ;
input VAR6 ;
wire VAR2;
wire VAR3 ;
wire VAR15 ;
wire VAR18;
not VAR1 (VAR2 , VAR13 );
not VAR12 (VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tapvgnd2/sky130_fd_sc_ms__tapvgnd2.functional.v | 1,104 | module MODULE1 ();
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_auto_pc_1/synth/zc702_auto_pc_1.v | 15,722 | module MODULE1 (
VAR106,
VAR21,
VAR14,
VAR91,
VAR56,
VAR40,
VAR73,
VAR58,
VAR89,
VAR71,
VAR88,
VAR19,
VAR24,
VAR5,
VAR68,
VAR77,
VAR20,
VAR33,
VAR27,
VAR79,
VAR31,
VAR96,
VAR17,
VAR67,
VAR44,
VAR37,
VAR15,
VAR63,
VAR98,
VAR1,
VAR86,
VAR61,
VAR102,
VAR57,
VAR93,
VAR41,
VAR104,
VAR76,
VAR51,
VAR26,
VAR99,
VAR100,
VAR75,
... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_iqctl.v | 18,300 | module MODULE1
(
VAR1, VAR88, VAR85, VAR48,
VAR7, VAR44, VAR10,
VAR28, VAR67, VAR103, VAR70,
VAR52,
VAR57, VAR59, VAR6, VAR98, VAR69, VAR91,
VAR95, VAR104, VAR3
) ;
input VAR57;
input VAR59;
input VAR6;
input VAR98;
input VAR69;
input VAR91;
input VAR95;
input VAR104; input VAR3;
output VAR1;
output VAR88;
output [3:0]... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_regfile_2clock.v | 3,929 | module MODULE1
(input VAR22,
input VAR4,
input VAR6,
input VAR18,
input [15:0] VAR24,
input [3:0] VAR26,
input [31:0] VAR20,
output [31:0] VAR23,
output VAR2,
input VAR16,
input VAR5,
output reg [31:0] VAR12,
output reg [31:0] VAR13,
output reg [31:0] VAR3,
output reg [31:0] VAR10,
output reg [31:0] VAR9,
output reg [3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probe_p/sky130_fd_sc_hdll__probe_p.behavioral.v | 1,368 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR4;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR8 ;
wire VAR9;
buf VAR2 (VAR9, VAR5 );
buf VAR7 (VAR3 , VAR9 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_dirrep.v | 12,267 | module MODULE1(
VAR40, VAR41, VAR65, VAR42,
VAR39, VAR59, VAR43,
VAR62, VAR20, VAR12,
VAR30, VAR29, VAR2, VAR47,
VAR55, VAR50, VAR38,
VAR36, VAR51, VAR9,
VAR57, VAR5, VAR34, VAR44,
VAR27, VAR54, VAR17,
VAR66, VAR58, VAR69,
VAR16, VAR28, VAR24,
VAR6, VAR22,
VAR63, VAR18,
VAR53, VAR26,
VAR33, VAR70,
VAR68, VAR74, VAR75,
... | gpl-2.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/data_path_rst.v | 3,258 | module MODULE1( VAR14,
clk,
reset,
VAR19,
VAR1,
VAR18,
VAR17,
VAR2,
VAR11,
VAR6,
VAR8 );
input VAR14;
input reset;
input VAR19;
input VAR1;
input VAR18;
input clk;
output VAR17;
output VAR2;
output VAR11;
output VAR6;
output VAR8;
wire VAR20 ;
wire VAR4;
assign VAR20 = ~ clk;
assign VAR4 = ~ VAR14;
VAR16 VAR5 (.VAR12(V... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_impctl_dtl_sclk.v | 4,236 | module MODULE1(VAR23 ,VAR22 ,VAR35 ,VAR12 ,VAR25 ,VAR32 ,
VAR18 );
output VAR22 ;
output VAR35 ;
output VAR12 ;
input VAR23 ;
input VAR25 ;
input VAR32 ;
input VAR18 ;
wire [2:0] VAR30 ;
wire [3:0] VAR4 ;
wire [3:0] VAR24 ;
wire VAR39 ;
wire VAR42 ;
wire VAR37 ;
wire VAR49 ;
wire VAR45 ;
wire VAR51 ;
wire VAR34 ;
wire ... | gpl-2.0 |
bigeagle/riffa | fpga/xilinx/zc706/ZC706_Gen2x4If64/hdl/ZC706Gen2x4If64.v | 20,956 | module MODULE1
parameter VAR182 = 4,
parameter VAR107 = 64,
parameter VAR144 = 256,
parameter VAR131 = 5
)
(output [(VAR182 - 1) : 0] VAR90,
output [(VAR182 - 1) : 0] VAR79,
input [(VAR182 - 1) : 0] VAR52,
input [(VAR182 - 1) : 0] VAR161,
output [3:0] VAR137,
input VAR154,
input VAR30,
input VAR9
);
wire VAR171;
wire V... | bsd-3-clause |
drom/quark | v/tail_length.v | 1,742 | module MODULE1 (VAR2, VAR1);
input [3:0] VAR2;
output [3:0] VAR1;
reg [3:0] VAR1;
reg VAR3;
always @ (VAR2)
begin
VAR1 = {
(VAR2 == 4'b0011),
(VAR2 == 4'b0010),
(VAR2 == 4'b0001),
((VAR2 | 4'b0101) == 4'b1101) | ((VAR2 | 4'b1100) == 4'b1100)
};
end
endmodule | mit |
SiLab-Bonn/pyBAR | firmware/mio3/src/mmc3_top.v | 11,740 | module MODULE1(
input wire VAR12,
input wire VAR100, input wire VAR46, input wire VAR14, input wire VAR53, output wire VAR50, output wire VAR107, inout wire [31:0] VAR49,
input wire VAR67,
input wire VAR62,
input wire VAR140,
output wire [8:1] VAR28,
output wire [3:0] VAR135,
output wire VAR144,
input wire VAR64,
input... | bsd-3-clause |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.srcs/sources_1/bd/block_design/ip/block_design_auto_pc_1/synth/block_design_auto_pc_1.v | 9,973 | module MODULE1 (
VAR12,
VAR101,
VAR88,
VAR42,
VAR40,
VAR29,
VAR84,
VAR112,
VAR20,
VAR65,
VAR55,
VAR53,
VAR64,
VAR50,
VAR51,
VAR48,
VAR41,
VAR33,
VAR5,
VAR59,
VAR16,
VAR35,
VAR47,
VAR39,
VAR104,
VAR74,
VAR82,
VAR99,
VAR98,
VAR100,
VAR45,
VAR76,
VAR117
);
input wire VAR12;
input wire VAR101;
input wire [31 : 0] VAR88;
in... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbp/sky130_fd_sc_ls__sdfbbp.behavioral.v | 3,323 | module MODULE1 (
VAR33 ,
VAR28 ,
VAR4 ,
VAR22 ,
VAR5 ,
VAR15 ,
VAR23 ,
VAR1
);
output VAR33 ;
output VAR28 ;
input VAR4 ;
input VAR22 ;
input VAR5 ;
input VAR15 ;
input VAR23 ;
input VAR1;
supply1 VAR2;
supply0 VAR8;
supply1 VAR36 ;
supply0 VAR25 ;
wire VAR30 ;
wire VAR29 ;
wire VAR35 ;
reg VAR7 ;
wire VAR38 ;
wire VAR... | apache-2.0 |
dcsun88/ntpserver-fpga | cpu/ip/cpu_auto_pc_0/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v | 6,140 | module MODULE1 #
(
parameter integer VAR15 = 4,
parameter integer VAR31 = 32
)
(
input wire clk ,
input wire reset ,
output wire [VAR15-1:0] VAR39 ,
output wire [VAR31-1:0] VAR34 ,
output wire [1:0] VAR23 ,
output wire VAR12 ,
output wire VAR1 ,
input wire VAR38 ,
input wire [VAR31-1:0] VAR33 ,
input wire [1:0] VAR8 ,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2_1.v | 2,075 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR9 ,
VAR8,
VAR6,
VAR4 ,
VAR7
);
output VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR8;
input VAR6;
input VAR4 ;
input VAR7 ;
VAR1 VAR3 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR5,
VAR2,
VAR9
);
output VAR5;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4_1.v | 2,275 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR11 ,
VAR10 ,
VAR2 ,
VAR4,
VAR8,
VAR9 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR11 ;
input VAR10 ;
input VAR2 ;
input VAR4;
input VAR8;
input VAR9 ;
input VAR5 ;
VAR7 VAR6 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.... | apache-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/verilog/ANN_AXILiteS_s_axi.v | 12,898 | module MODULE1
VAR45 = 6,
VAR55 = 32
)(
input wire VAR17,
input wire VAR76,
input wire VAR30,
input wire [VAR45-1:0] VAR78,
input wire VAR12,
output wire VAR64,
input wire [VAR55-1:0] VAR71,
input wire [VAR55/8-1:0] VAR43,
input wire VAR36,
output wire VAR70,
output wire [1:0] VAR39,
output wire VAR77,
input wire VAR7,... | gpl-3.0 |
eda-globetrotter/MarcheProcessor | processor/alu_andy.v | 174,364 | module MODULE1(VAR5,VAR4,VAR7,VAR1,VAR6,VAR8,VAR3);
output [0:127] VAR8;
input [0:127] VAR5;
input [0:127] VAR4;
input [0:2] VAR7;
input [0:1] VAR1;
input [0:4] VAR6;
input [15:0] VAR3;
reg [0:127] VAR8;
always @(VAR5 or VAR4 or VAR7 or VAR1 or VAR6 or VAR3)
begin
case(VAR6)
begin
case(VAR7)
case(VAR2)
begin
case(VAR4[... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/eth_miim.v | 16,634 | module MODULE1
(
VAR59,
VAR50,
VAR35,
VAR20,
VAR3,
VAR52,
VAR1,
VAR16,
VAR17,
VAR36,
VAR44,
VAR2,
VAR58,
VAR60,
VAR24,
VAR41,
VAR40,
VAR30,
VAR25,
VAR42,
VAR9
);
input VAR59; input VAR50; input [7:0] VAR35; input [15:0] VAR3; input [4:0] VAR52; input [4:0] VAR1; input VAR20; input VAR16; input VAR17; input VAR36; outpu... | apache-2.0 |
wgml/sysrek | skin_color_segm/centroid.v | 2,489 | module MODULE1 #
(
parameter [9:0] VAR28 = 720,
parameter [9:0] VAR20 = 576
)
(
input clk,
input VAR6,
input rst,
input VAR4,
input VAR19,
input VAR14,
input VAR37,
output [9:0] VAR33,
output [9:0] VAR18,
output [9:0] VAR42,
output [9:0] VAR30
);
reg [9:0] VAR8 = 0;
reg [9:0] VAR24 = 0;
wire VAR35;
wire VAR1;
delay #
(... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai221/gf180mcu_fd_sc_mcu9t5v0__oai221_1.functional.v | 1,676 | module MODULE1( VAR6, VAR1, VAR19, VAR3, VAR20, VAR15 );
input VAR15, VAR20, VAR1, VAR6, VAR3;
output VAR19;
wire VAR17;
not VAR10( VAR17, VAR15 );
wire VAR2;
not VAR21( VAR2, VAR20 );
wire VAR4;
and VAR13( VAR4, VAR17, VAR2 );
wire VAR8;
not VAR12( VAR8, VAR1 );
wire VAR5;
not VAR9( VAR5, VAR6 );
wire VAR11;
and VAR7(... | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_axi_basic_top.v | 10,999 | module MODULE1 #(
parameter VAR15 = 128, parameter VAR24 = "VAR30", parameter VAR5 = "VAR39", parameter VAR42 = "VAR39", parameter VAR36 = 1,
parameter VAR49 = (VAR15 == 128) ? 2 : 1, parameter VAR53 = VAR15 / 8 ) (
input [VAR15-1:0] VAR61, input VAR40, output VAR8, input [VAR53-1:0] VAR7, input VAR11, input [3:0] VAR2... | mit |
teknohog/rautanoppa | Nexys2/hwrandom.v | 1,352 | module MODULE1 (VAR13, VAR1, reset, VAR6, VAR15, VAR10);
module MODULE1 (VAR13, VAR1, reset);
input reset;
input VAR13;
wire clk;
output VAR1;
parameter VAR14 = 50000000;
VAR11 VAR2 (.VAR16(VAR13), .VAR17(clk));
parameter VAR5 = 131;
wire [31:0] VAR9;
VAR7 #(.VAR5(VAR5), .VAR14(VAR14)) VAR12 (.clk(clk), .VAR1(VAR1), .r... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp1/toplevel/mrfm/mrfm_proc.v | 4,321 | module MODULE1 (input VAR47, input reset, input enable,
input [6:0] VAR43, input [31:0] VAR59, input VAR37,
input [15:0] VAR30, output wire [15:0] VAR42, output wire VAR6,
output wire [15:0] VAR67, output wire [15:0] VAR60,
output wire [15:0] VAR21, output wire [15:0] VAR61,
output wire VAR12, output wire [63:0] VAR44)... | gpl-2.0 |
alexforencich/verilog-ethernet | example/HXT100G/fpga/rtl/gth_i2c_init.v | 18,423 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR10,
output wire VAR16,
output wire VAR9,
output wire VAR7,
output wire VAR11,
output wire VAR5,
output wire VAR6,
input wire VAR15,
output wire [7:0] VAR3,
output wire VAR4,
input wire VAR8,
output wire VAR14,
output wire VAR12,
input wire VAR1
);
lo... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.blackbox.v | 1,266 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR4;
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_019bits.v | 1,917 | module MODULE2 (
clk,
VAR34, VAR6, VAR30, VAR32, VAR13, VAR24, VAR12, VAR29,
sum,
);
input clk;
input [VAR3+0-1:0] VAR34, VAR6, VAR30, VAR32, VAR13, VAR24, VAR12, VAR29;
output [VAR3 :0] sum;
reg [VAR3 :0] sum;
wire [VAR3+3-1:0] VAR22;
wire [VAR3+2-1:0] VAR9, VAR23;
wire [VAR3+1-1:0] VAR33, VAR18, VAR10, VAR21;
reg [VA... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/sctag/rtl/sctag_dirl_buf.v | 3,392 | module MODULE1(
VAR9, VAR14, VAR18, VAR7,
VAR1, VAR11, VAR5,
VAR15,
VAR6, VAR12, VAR2, VAR8, VAR17,
VAR4, VAR10, VAR13, VAR16,
VAR3
);
input VAR6; input VAR12; input [7:0] VAR2; input [1:0] VAR8; input [3:0] VAR17; input [5:0] VAR4; input [1:0] VAR10; input [3:0] VAR13; input [32:0] VAR16; input VAR3;
output [7:0] VAR9... | gpl-2.0 |
aquaxis/FPGAMAG18 | fmrv32im-artya7.madd33/fmrv32im-artya7.srcs/sources_1/bd/fmrv32im_artya7/ipshared/e954/src/fmrv32im_dbussel.v | 3,330 | module MODULE1
(
output VAR32,
input VAR33,
input [3:0] VAR20,
input [31:0] VAR34,
input [31:0] VAR11,
output [31:0] VAR14,
output VAR27,
input VAR13,
output VAR28,
output [3:0] VAR18,
output [31:0] VAR3,
output [31:0] VAR19,
input [31:0] VAR29,
input VAR6,
input VAR22,
output VAR10,
output [3:0] VAR4,
output [31:0] VA... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | spi_master/spi_master.v | 5,685 | module MODULE1 (clk, rst, VAR8, VAR27, VAR13, VAR7, VAR29, VAR17, VAR30, VAR28, VAR21, VAR25, VAR12);
input clk;
input rst;
input VAR8;
input VAR27;
input VAR13; input[7:0] VAR7;
output VAR29; output VAR17; output VAR30; output VAR28;
output[7:0] VAR21;
output VAR25;
output VAR12;
parameter VAR20 = 3;
localparam VAR24 ... | mit |
donnaware/TabX1 | rtl/tabx1/ps2_mouse.v | 16,197 | module MODULE3(
input VAR66, input reset,
inout VAR35, inout VAR60, output reg [8:0] VAR48, output reg [8:0] VAR56, output reg [1:0] VAR17, output reg [2:0] VAR50, output ready, output VAR14 );
parameter VAR53 = 5000; parameter VAR64 = 100000; parameter VAR19 = 17; parameter VAR41 = 25000000; parameter VAR11 = 28; wire... | gpl-3.0 |
Sajid3/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/common.v | 1,512 | module MODULE2 #(parameter VAR1 = 1) (
input wire [VAR1-1:0] VAR7, output reg [VAR1-1:0] VAR6, input wire clk );
reg [VAR1-1:0] VAR4;
always @(posedge clk)
{VAR6, VAR4} <= {VAR4, VAR7};
endmodule
module MODULE1 #(parameter VAR1 = 1) (
input wire [VAR1-1:0] VAR7, output reg [VAR1-1:0] VAR6, input wire clk, output wire V... | apache-2.0 |
azonenberg/antikernel-ipcores | clock/crossing/SwitchDebouncer.v | 5,341 | module MODULE1 #(
parameter VAR10 = 0
) (
input wire clk,
input wire din,
output reg dout = VAR10,
output reg VAR6 = 0,
output reg VAR15 = 0
);
parameter VAR14 = 'h1023;
localparam VAR12 = VAR11(VAR14);
wire VAR2;
VAR7 #(
.VAR8(0)
) VAR16 (
.VAR5(clk),
.din(din),
.VAR13(clk),
.dout(VAR2)
);
reg[VAR12-1:0] VAR1 = 0;
reg... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.functional.v | 1,545 | module MODULE1 (
VAR2 ,
VAR5,
VAR11,
VAR7,
VAR6
);
output VAR2 ;
input VAR5;
input VAR11;
input VAR7;
input VAR6;
wire VAR12 ;
wire VAR4 ;
wire VAR1;
nand VAR9 (VAR12 , VAR11, VAR5 );
nand VAR8 (VAR4 , VAR6, VAR7 );
and VAR3 (VAR1, VAR12, VAR4);
buf VAR10 (VAR2 , VAR1 );
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/bench/verilog/ram_16x8k_dp.v | 2,898 | module MODULE1 (
VAR3,
VAR6,
VAR5,
VAR24,
VAR7,
VAR22,
VAR16,
VAR18,
VAR17,
VAR13,
VAR25,
VAR8
);
input VAR3;
input VAR6;
input [1 : 0] VAR5;
input [12 : 0] VAR24;
input [15 : 0] VAR7;
output [15 : 0] VAR22;
input VAR16;
input VAR18;
input [1 : 0] VAR17;
input [12 : 0] VAR13;
input [15 : 0] VAR25;
output [15 : 0] VAR8;... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_chip/bsg_rocket/bsg_chip_rocket.v | 4,364 | module MODULE1 #(
parameter VAR43 = 4
, parameter VAR19 = 8
, parameter VAR30 = 0
, parameter VAR50 = 0
, parameter VAR53 = 100
, parameter VAR47 = 5'b00000
, parameter VAR59 = 2
, parameter VAR9 = 0
)
(
input VAR18
, input VAR8
, input VAR36
, input [VAR43-1:0] VAR27 , input [VAR43-1:0] VAR46
, input [VAR19-1:0] VAR56... | bsd-3-clause |
sgq995/rc4-de0-nano-soc | fpga/hps/soc_system/synthesis/submodules/soc_system_dipsw_pio.v | 4,506 | module MODULE1 (
address,
VAR12,
clk,
VAR8,
VAR9,
VAR10,
VAR14,
irq,
VAR1
)
;
output irq;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR12;
input clk;
input [ 3: 0] VAR8;
input VAR9;
input VAR10;
input [ 31: 0] VAR14;
wire VAR4;
reg [ 3: 0] VAR7;
reg [ 3: 0] VAR15;
wire [ 3: 0] VAR13;
reg [ 3: 0] VAR11;
wire VA... | mit |
asicguy/gplgpu | hdl/vga/sm_cpuwr.v | 4,420 | module MODULE1
(
input VAR1,
input VAR7,
input VAR6,
input VAR13,
input VAR17,
input VAR10,
output reg VAR22,
output VAR3,
output VAR4,
output VAR16,
output reg VAR24,
output VAR21,
output reg VAR25
);
reg [2:0] VAR5;
reg [2:0] VAR11;
reg VAR15;
reg VAR20;
reg VAR23;
wire VAR14;
wire VAR9;
parameter VAR8 = 3'b000,
VAR1... | gpl-3.0 |
neale/CS-program | 474-VLSI/Lab_ADC/db/Display_PLL_altpll.v | 4,553 | module MODULE1
(
VAR3,
clk,
VAR4,
VAR7) ;
input VAR3;
output [4:0] clk;
input [1:0] VAR4;
output VAR7;
tri0 VAR3;
tri0 [1:0] VAR4;
reg VAR2;
wire [4:0] VAR1;
wire VAR6;
wire VAR5; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtn/sky130_fd_sc_lp__dfrtn.functional.pp.v | 2,024 | module MODULE1 (
VAR16 ,
VAR6 ,
VAR15 ,
VAR13,
VAR12 ,
VAR4 ,
VAR1 ,
VAR7
);
output VAR16 ;
input VAR6 ;
input VAR15 ;
input VAR13;
input VAR12 ;
input VAR4 ;
input VAR1 ;
input VAR7 ;
wire VAR11 ;
wire VAR10 ;
wire VAR5;
not VAR8 (VAR10 , VAR13 );
not VAR2 (VAR5, VAR6 );
VAR17 VAR3 VAR9 (VAR11 , VAR15, VAR5, VAR10, , ... | apache-2.0 |
jakubfi/mera400f | src/alu.v | 1,878 | module MODULE1(
input VAR15,
input [0:15] VAR12,
input [0:15] VAR23,
input VAR33,
input VAR27, VAR16,
input VAR30, VAR21,
input VAR36, VAR18,
output [0:15] VAR34,
output VAR28,
output VAR29,
output VAR7
);
wor VAR35;
wire [3:0] VAR19, VAR11;
wire [3:1] VAR2;
wire [3:0] VAR4;
wire VAR29;
VAR8 VAR10(
.VAR12(VAR12[0:3]),
... | gpl-2.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/mi_nios_cpu_jtag_debug_module_wrapper.v | 10,109 | module MODULE1 (
VAR46,
VAR14,
clk,
VAR47,
VAR26,
VAR24,
VAR32,
VAR12,
VAR43,
VAR9,
VAR54,
VAR17,
VAR15,
VAR51,
VAR41,
VAR49,
VAR55,
VAR16,
VAR22,
VAR34,
VAR45,
VAR19,
VAR58,
VAR3,
VAR39,
VAR52,
VAR25,
VAR37,
VAR8,
VAR18,
VAR6,
VAR31,
VAR2,
VAR27,
VAR40,
VAR28
)
;
output [ 37: 0] VAR45;
output VAR19;
output VAR58;
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311oi/sky130_fd_sc_hd__a311oi.behavioral.v | 1,581 | module MODULE1 (
VAR1 ,
VAR14,
VAR11,
VAR4,
VAR5,
VAR7
);
output VAR1 ;
input VAR14;
input VAR11;
input VAR4;
input VAR5;
input VAR7;
supply1 VAR15;
supply0 VAR12;
supply1 VAR2 ;
supply0 VAR13 ;
wire VAR3 ;
wire VAR9;
and VAR10 (VAR3 , VAR4, VAR14, VAR11 );
nor VAR6 (VAR9, VAR3, VAR5, VAR7);
buf VAR8 (VAR1 , VAR9 );
en... | apache-2.0 |
ptracton/pmodacl2 | behavioral/adxl362/adxl362_regs.v | 4,903 | module MODULE1 (
VAR14, VAR4, VAR5, VAR6,
VAR1, VAR2, VAR17, VAR19, VAR10,
VAR11, VAR8, VAR16, VAR13,
VAR9, write, address, VAR20, VAR15, VAR7, VAR12,
VAR18, VAR3
) ;
input wire VAR9;
input wire write;
input wire [5:0] address;
input wire [7:0] VAR20;
output reg [7:0] VAR14;
output reg [10:0] VAR4 =0;
output reg [7:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221o/sky130_fd_sc_hd__a221o_1.v | 2,444 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR9 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR4,
VAR8,
VAR10 ,
VAR2
);
output VAR12 ;
input VAR5 ;
input VAR9 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR4;
input VAR8;
input VAR10 ;
input VAR2 ;
VAR11 VAR6 (
.VAR12(VAR12),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_8.behavioral.pp.v | 1,069 | module MODULE1( VAR2, VAR4 );
inout VAR2, VAR4;
VAR3 VAR5(.VAR2(VAR2),.VAR4(VAR4));
VAR3 VAR1(.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/hostController/softransmit.v | 7,576 | module MODULE1 (VAR29, VAR18, VAR7, VAR19, VAR9, clk, rst, VAR20, VAR8, VAR27, VAR3, VAR6);
input VAR29; input VAR7;
input [15:0] VAR9;
input clk;
input rst;
input VAR20;
input VAR27;
output VAR18; output VAR19; output VAR8;
output VAR3;
input VAR6;
wire VAR29;
reg VAR18, VAR2;
wire VAR7;
reg VAR19, VAR4;
wire [15:0] V... | gpl-3.0 |
cwilkens/ecen4024-microphone-array | microphone-array/microphone-array.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_stub.v | 1,261 | module MODULE1(VAR3, VAR1, reset, VAR2)
;
input VAR3;
output VAR1;
input reset;
output VAR2;
endmodule | mit |
Raamakrishnan/MyProc | MyProc2/WB.v | 1,635 | module MODULE1 (
input clk,
input wire [VAR2 - 1:0] VAR14,
input wire [VAR2 - 3:0] VAR6,
input wire [VAR2 - 1:0] VAR19,
output reg VAR15,
output wire [VAR2 - 1:0] VAR13,
output wire [VAR2 - 3:0] VAR9,
output reg [VAR1 - 1:0] VAR17,
output reg [VAR2 - 1:0] VAR5,
output reg VAR3,
output reg [1:0] VAR18 );
wire [5:0] VAR8... | mit |
dtysky/FPGA-Imaging-Library | Generator/WindowGenerator/HDL/WindowGenerator.srcs/sources_1/new/WindowGenerator.v | 6,334 | module MODULE1(
clk,
VAR2,
VAR1,
VAR5,
VAR15,
VAR12,
VAR14
);
parameter[0 : 0] VAR10 = 0;
parameter[3 : 0] VAR4 = 3;
parameter[3: 0] VAR9 = 8;
parameter[2 : 0] VAR11 = VAR4 >> 1;
input clk;
input VAR2;
input VAR1;
input [VAR9 * VAR4 - 1 : 0] VAR5;
output VAR15;
output[VAR9 * VAR4 * VAR4 - 1 : 0] VAR12;
output VAR14;
re... | lgpl-2.1 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_plic_top.v | 6,276 | module MODULE1(
input clk,
input VAR48,
input VAR44,
output VAR77,
input [32-1:0] VAR63,
input VAR19,
input [32-1:0] VAR69,
output VAR71,
input VAR57,
output [32-1:0] VAR26,
input VAR53,
input VAR33,
input VAR12,
input VAR29,
input VAR51,
input VAR7,
input VAR45,
input VAR14,
input VAR18,
input VAR54,
input VAR32,
inpu... | apache-2.0 |
JakeMercer/mac | rgmii.v | 1,699 | module MODULE1
(
input wire reset,
input wire VAR2,
output wire [3:0] VAR16,
output wire [3:0] VAR11,
output wire VAR7,
output wire VAR12,
output wire VAR6,
input wire [3:0] VAR19,
input wire [3:0] VAR21,
input wire VAR4,
input wire VAR20,
input wire VAR10,
input wire VAR9,
input wire [7:0] VAR5,
input wire VAR3,
outpu... | mit |
omicronns/studies-sys-rek | de1-soc-proc/ip/alu_add.v | 4,578 | module MODULE1 (
VAR1,
VAR4,
VAR18);
input [7:0] VAR1;
input [7:0] VAR4;
output [7:0] VAR18;
wire [7:0] VAR20;
wire [7:0] VAR18 = VAR20[7:0];
VAR13 VAR15 (
.VAR1 (VAR1),
.VAR4 (VAR4),
.VAR18 (VAR20)
,
.VAR11 (),
.VAR5 (),
.VAR14 (),
.VAR2 (),
.VAR21 (),
.VAR7 (),
.VAR8 ()
);
VAR15.VAR3 = "VAR17",
VAR15.VAR10 = "VAR24=... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp_2.v | 2,289 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR10 ,
VAR3,
VAR2 ,
VAR1 ,
VAR7 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR10 ;
input VAR3;
input VAR2 ;
input VAR1 ;
input VAR7 ;
input VAR4 ;
VAR9 VAR6 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
pollow/Multi_Cycle_CPU | top.v | 1,334 | module MODULE1;
reg VAR9;
reg [3:0] VAR5;
reg [7:0] VAR2;
wire [7:0] VAR6;
wire [7:0] VAR7;
wire [3:0] VAR8;
VAR1 VAR4 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8)
);
integer VAR3; | gpl-3.0 |
jmesmon/trifles | verilog/hw5/p28.v | 1,087 | module MODULE1 #(parameter VAR11 = 8, VAR12 = 5)
(output [VAR11-1:0] VAR2, VAR3, input [VAR11-1:0]VAR7,
input [VAR12-1:0] VAR8, VAR1, VAR9,
input VAR13, clk);
parameter VAR4 = 2**VAR12;
reg [VAR11-1:0] VAR10 [VAR4-1:0];
assign VAR2 = VAR10[VAR8];
assign VAR3 = VAR10[VAR1];
always @(posedge clk)
if (VAR13)
VAR10[VAR9] <... | gpl-3.0 |
sehugg/8bitworkshop | presets/verilog/cpu_platform.v | 4,839 | module MODULE1(clk, reset, VAR18, VAR24,
VAR10, VAR27,
VAR1, VAR14,
VAR13);
input clk, reset;
input VAR10, VAR27;
input [7:0] VAR1;
input [7:0] VAR14;
output VAR18, VAR24;
output [3:0] VAR13;
wire VAR15;
wire [8:0] VAR28;
wire [8:0] VAR25;
wire [15:0] VAR5;
reg [15:0] VAR16;
reg VAR20;
reg [15:0] VAR26;
reg [5:0] VAR30... | gpl-3.0 |
velizarefremov/MIPS | Part 4/Verilog Code/cpu_behav.v | 4,336 | module MODULE1
(
output [15:0] VAR38, output [15:0] VAR61, input clk,
input rst
);
reg [15:0] VAR43; reg [15:0] VAR60;
wire [15:0] VAR56;
reg [15:0] VAR27;
wire [15:0] VAR21; wire [15:0] VAR23; wire [15:0] VAR4;
wire [15:0] VAR11;
wire [4:0] VAR20;
wire [15:0] VAR48;
wire [15:0] VAR22;
wire [15:0] VAR54;
wire [15:0] VA... | gpl-2.0 |
monotone-RK/FACE | MCSoC-15/4-way/ise/ipcore_dir/dram/user_design/rtl/phy/mig_7series_v1_9_ddr_phy_dqs_found_cal.v | 51,392 | module MODULE1 #
(
parameter VAR65 = 100, parameter VAR121 = 2, parameter VAR18 = 5, parameter VAR137 = "0",
parameter VAR68 = 5, parameter VAR52 = "VAR7", parameter VAR122 = 1, parameter VAR97 = 3, parameter VAR109 = 8, parameter VAR1 = 8, parameter VAR38 = "VAR22", parameter VAR14 = "VAR59", parameter VAR129 = 3, par... | mit |
gbraad/minimig-de1 | rtl/minimig/Gayle.v | 11,828 | module MODULE2
(
input clk,
input reset,
input [23:1] VAR17,
input [15:0] VAR55,
output [15:0] VAR64,
input rd,
input VAR32,
input VAR22,
input VAR59, input VAR42, output irq,
output VAR61, input [1:0] VAR16,
output VAR3,
output VAR38,
input [2:0] VAR39,
input [15:0] VAR5,
output [15:0] VAR56,
input VAR63,
input VAR1,
... | gpl-3.0 |
combinatorylogic/soc | backends/small1/hw/rtl/vgatop.v | 1,153 | module MODULE2(input clk,
input [12:0] VAR17,
input [7:0] VAR3,
input VAR19,
input [12:0] VAR9,
output reg [7:0] VAR12);
reg [7:0] VAR18[0:(3*2048)-1];
always @(posedge clk)
begin
if (VAR19) begin
VAR18[VAR17] <= VAR3;
end
VAR12 <= VAR18[VAR9];
end
endmodule
module MODULE1(input clk, input rst,
input VAR1,
output VAR10... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.blackbox.v | 1,359 | module MODULE1 (
VAR3 ,
VAR6,
VAR4,
VAR7,
VAR5,
VAR1
);
output VAR3 ;
input VAR6;
input VAR4;
input VAR7;
input VAR5;
input VAR1;
supply1 VAR2;
supply0 VAR8;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_div.v | 15,122 | module MODULE1 (
VAR127, VAR12, VAR116, VAR64,
VAR94, VAR59, VAR102,
VAR78, VAR49, VAR53,
VAR73, VAR14, VAR1,
VAR122, VAR106, VAR28,
VAR97, VAR25,
VAR126, VAR24,
VAR134, VAR104, VAR74,
VAR115, VAR13, VAR128,
VAR50, VAR7, VAR92, VAR88, VAR22,
VAR89, VAR46, VAR6,
VAR98, VAR47, VAR65,
VAR34, VAR16, VAR54,
VAR110, VAR83, V... | gpl-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_static_regblk.v | 12,512 | module MODULE1
parameter VAR23 = 32,
parameter VAR59 = 3,
parameter VAR17 = 1
) (
input VAR102 ,
input VAR1 ,
input VAR62 ,
input VAR3 ,
input [VAR17-1:0] VAR36 ,
input [31:0] VAR60 ,
input VAR77 ,
output VAR111 ,
input VAR20 ,
input [VAR23-1:0] VAR39 ,
input [VAR23/8-1:0] VAR94 ,
input VAR95 ,
output VAR81 ,
output [V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxbp/sky130_fd_sc_lp__sdfxbp.symbol.v | 1,434 | module MODULE1 (
input VAR5 ,
output VAR3 ,
output VAR7,
input VAR6,
input VAR9,
input VAR1
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
JY-Kim/CA2016 | Sources/EXMEM.v | 1,176 | module MODULE1
(
input VAR8,
input VAR2,
input [31:0] VAR5,
input [2:0] VAR14,
input [1:0] VAR11,
input [31:0] VAR6,
input [31:0] VAR10,
input [4:0] VAR12,
output reg [31:0] VAR7,
output reg [2:0] VAR4,
output reg [1:0] VAR1,
output reg [31:0] VAR9,
output reg [31:0] VAR13,
output reg [4:0] VAR3
);
always @( posedge VA... | mit |
sh-chris110/chris | FPGA/Math/Qsys/nios_design/synthesis/submodules/nios_design_pll_0.v | 2,080 | module MODULE1(
input wire VAR43,
input wire rst,
output wire VAR57,
output wire VAR50
);
VAR66 #(
.VAR28("false"),
.VAR64("100.0 VAR54"),
.VAR30("VAR40"),
.VAR21(1),
.VAR32("100.000000 VAR54"),
.VAR4("0 VAR42"),
.VAR22(50),
.VAR34("0 VAR54"),
.VAR71("0 VAR42"),
.VAR25(50),
.VAR55("0 VAR54"),
.VAR24("0 VAR42"),
.VAR68(... | gpl-2.0 |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/main.v | 23,342 | module MODULE1(
VAR60, VAR36, VAR64, VAR54,
VAR89,
VAR168, VAR43,
VAR146, VAR141,
VAR95, VAR106,
VAR87,
VAR6,
VAR142,
VAR117,
VAR134,
VAR147,
VAR26,
VAR163,
VAR172,
VAR113,
VAR105,
VAR20,
VAR158,
VAR1, VAR183,
VAR143, VAR129,
VAR91, VAR14,
VAR109, VAR69,
VAR70,
VAR132,
VAR71,
VAR56,
VAR164,
VAR107
);
input VAR60; outpu... | gpl-2.0 |
kyzhai/NUNY | src/hardware/five_new2.v | 6,400 | module MODULE1 (
address,
VAR42,
VAR10);
input [9:0] address;
input VAR42;
output [11:0] VAR10;
tri1 VAR42;
wire [11:0] VAR38;
wire [11:0] VAR10 = VAR38[11:0];
VAR35 VAR5 (
.VAR11 (address),
.VAR27 (VAR42),
.VAR4 (VAR38),
.VAR16 (1'b0),
.VAR2 (1'b0),
.VAR6 (1'b1),
.VAR24 (1'b0),
.VAR29 (1'b0),
.VAR21 (1'b1),
.VAR15 (1'... | gpl-2.0 |
brianbennett/fpga_nes | hw/src/cmn/vga_sync/vga_sync.v | 4,997 | module MODULE1
(
input wire clk, output wire VAR14, output wire VAR4, output wire en, output wire [9:0] VAR27, output wire [9:0] VAR3, output wire [9:0] VAR17, output wire [9:0] VAR6 );
localparam VAR23 = 640; localparam VAR1 = 16; localparam VAR18 = 96; localparam VAR13 = 48; localparam VAR25 = 480; localparam VAR2 = ... | bsd-2-clause |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_tx_pipeline.v | 22,539 | module MODULE1 #(
parameter VAR2 = 128, parameter VAR25 = "VAR4", parameter VAR21 = 1,
parameter VAR50 = (VAR2 == 128) ? 2 : 1, parameter VAR35 = VAR2 / 8 ) (
input [VAR2-1:0] VAR29, input VAR12, output VAR55, input [VAR35-1:0] VAR62, input VAR22, input [3:0] VAR33,
output [VAR2-1:0] VAR1, output VAR23, output VAR39, o... | gpl-2.0 |
CMCammarano/EE-454-Portable-Ultrasound | Implementation/Vivado/EE454_Final_Project.srcs/sources_1/m_port_ultra_processor_array.v | 1,528 | module MODULE1 (
input clk,
input VAR4,
input VAR9,
input [8191:0] VAR10,
output [4095:0] VAR12,
output [4095:0] VAR2,
output [7:0] VAR13,
output [7:0] VAR1
);
wire [4095:0] VAR18;
wire [4095:0] VAR5;
wire [8:0] VAR8;
wire [8:0] VAR11;
VAR16 VAR7 (
.clk (clk),
.VAR4 (VAR4),
.VAR9 (VAR9),
.VAR14 (VAR18),
.VAR17 (VAR8),
... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x1_125/example_design/PIO_TO_CTRL.v | 3,942 | module MODULE1 (
clk,
VAR2,
VAR3,
VAR1,
VAR6,
VAR4
);
input clk;
input VAR2;
input VAR3;
input VAR1;
input VAR6;
output VAR4;
reg VAR5;
reg VAR4;
always @ ( posedge clk or negedge VAR2 ) begin
if (!VAR2 ) begin
VAR5 <= 0;
end else begin
if (!VAR5 && VAR3)
VAR5 <= 1'b1;
end
else if (VAR1)
VAR5 <= 1'b0;
end
end
always @ ... | lgpl-3.0 |
ad510/ee201l_cpu | DataMemory.v | 1,851 | module MODULE1 (VAR5, VAR6, VAR10, addr, VAR7, VAR8);
parameter VAR4 = 8;
parameter VAR3 = 256;
input VAR5;
input VAR6, VAR10;
input [VAR4-1:0] VAR7;
input [7:0] addr;
output [VAR4-1:0] VAR8;
reg [VAR4-1:0] VAR2;
reg [VAR4-1 : 0] memory[VAR3-1 : 0];
always @ (posedge VAR5)
begin : VAR1
VAR2 <= 100'VAR9;
if (VAR10)
begi... | mit |
The-OpenROAD-Project/asap7 | asap7sc7p5t_28/Verilog/asap7sc7p5t_SEQ_LVT_TT_220101.v | 81,234 | module MODULE1 (VAR16, VAR12, VAR22, VAR23, VAR14);
output VAR16;
input VAR12, VAR22, VAR23, VAR14;
reg VAR27;
wire VAR19, VAR8, VAR1, VAR24;
wire VAR28, VAR11, VAR10;
wire VAR17, VAR13;
not (VAR28, VAR19);
not (VAR17, VAR8);
not (VAR10, VAR1);
VAR15 (VAR13, VAR24, VAR28, VAR17, VAR10);
VAR25 (VAR11, VAR27, VAR24, VAR2... | bsd-3-clause |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_cmd_gen.v | 20,913 | module MODULE1
VAR12 = 4,
VAR40 = 5,
VAR39 = 2,
VAR61 = 2,
VAR75 = 16,
VAR46 = 12,
VAR58 = 3,
VAR1 = 2,
VAR68 = 33,
VAR3 = 6,
VAR49 = 4,
VAR67 = 8,
VAR24 = 8,
VAR22 = 12,
VAR80 = 2,
VAR35 = 1
)
(
VAR47,
VAR70,
VAR26,
VAR23,
VAR20,
VAR4,
VAR72,
VAR16,
VAR27,
VAR37,
VAR30,
VAR33,
VAR54,
VAR8,
VAR42,
VAR76,
VAR51,
VAR43,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.behavioral.pp.v | 1,176 | module MODULE1 (
VAR2,
VAR4,
VAR3 ,
VAR1
);
input VAR2;
input VAR4;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
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