repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_usr_addr_fifo.v | 4,755 | module MODULE1 #
(
parameter VAR40 = 2,
parameter VAR8 = 10,
parameter VAR13 = 0,
parameter VAR32 = 14
)
(
input VAR42,
input VAR7,
input VAR25,
input [2:0] VAR31,
input [30:0] VAR33,
input VAR39,
input VAR16,
output [2:0] VAR18,
output [30:0] VAR3,
output VAR9,
output VAR24
);
wire [35:0] VAR27;
reg VAR34;
always @(po... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_physical_2.v | 19,311 | module MODULE1(
input VAR183,
input reset,
output VAR5,
input VAR218,
output VAR239,
output VAR22,
input VAR168,
output VAR212,
output VAR20,
input VAR194,
output VAR163,
output VAR213,
input VAR12,
output VAR143,
output VAR8,
output VAR174,
input [11:0] VAR86,
input VAR123,
input VAR222,
input [1:0] VAR48,
input VAR20... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai_2.v | 2,345 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5 ,
VAR4,
VAR6,
VAR7,
VAR1 ,
VAR2
);
output VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR7;
input VAR1 ;
input VAR2 ;
VAR3 VAR10 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
V... | apache-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT_FIRSQ/MULT_FIRSQ.v | 4,013 | module MODULE1 (
VAR16,
VAR14);
input [29:0] VAR16;
output [59:0] VAR14;
wire [59:0] VAR6;
wire [59:0] VAR14 = VAR6[59:0];
VAR11 VAR5 (
.VAR7 (VAR16),
.VAR14 (VAR6),
.VAR9 (1'b0),
.VAR1 (1'b1),
.VAR15 (1'b1));
VAR5.VAR4 = 30,
VAR5.VAR12 = "VAR13",
VAR5.VAR3 = 0,
VAR5.VAR2 = "VAR10",
VAR5.VAR8 = 60;
endmodule | gpl-2.0 |
carstenbru/fpga-log | spartanmc/hardware/uart_light/src/uart_light.v | 3,884 | module MODULE1
parameter VAR24 = 5,
parameter VAR12 = 5,
parameter VAR21 = 15,
parameter VAR7 = 4,
parameter VAR11 = 0,
parameter VAR27 = 0,
parameter VAR28 = 6,
parameter VAR13 = 3,
parameter VAR2 = 8
)(
input wire reset,
input wire VAR10,
input wire VAR18,
input wire [VAR2-1:0] VAR14,
output wire VAR25,
output wire V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.functional.pp.v | 1,867 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR3,
VAR10,
VAR6 ,
VAR12
);
output VAR2 ;
input VAR11 ;
input VAR3;
input VAR10;
input VAR6 ;
input VAR12 ;
wire VAR9 ;
wire VAR1;
not VAR4 (VAR9 , VAR11 );
VAR8 VAR7 (VAR1, VAR9, VAR3, VAR10);
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/new/SHDScheduler.v | 2,976 | module MODULE1 #(parameter VAR4 = 128, VAR25 = 8) (
input clk,
input rst,
output VAR23,
input[VAR4 - 1:0] VAR26,
input VAR20,
input VAR21,
input[VAR25 - 1:0] VAR13,
output[VAR25 - 1:0] VAR22,
output[VAR25*VAR4 - 1:0] VAR8
);
reg[VAR4 - 1:0] VAR10;
reg VAR1 = 0;
wire VAR16;
reg VAR12;
always@(posedge clk) begin
if(rst) ... | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/ip_dram/controller/mig_7series_v2_3_arb_row_col.v | 18,940 | module MODULE1 #
(
parameter VAR91 = 100,
parameter VAR31 = "1T",
parameter VAR101 = 5,
parameter VAR48 = "VAR38",
parameter VAR5 = 4,
parameter VAR67 = 2,
parameter VAR12 = 37500, parameter VAR49 = 12500, parameter VAR9 = 6 )
(
VAR64, VAR18, VAR32, VAR72, VAR78, VAR61,
VAR14, VAR39, VAR1,
VAR74, VAR51, VAR20, VAR52, V... | mit |
merckhung/zet | cores/ps2/rtl/ps2_mouse_nofifo.v | 2,006 | module MODULE1 (
input clk,
input reset,
input [7:0] VAR7, input write,
output [7:0] VAR4, output irq,
output VAR5,
output VAR16,
output VAR10,
inout VAR9,
inout VAR8
);
wire VAR11;
wire VAR6;
VAR3 VAR12 (
.clk (clk),
.reset (reset),
.VAR14 (VAR7),
.VAR2 (write),
.VAR13 (VAR4),
.VAR1 (irq),
.VAR5 (VAR5),
.VAR15 (VAR16)... | gpl-3.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/cdp/rgmii_gmii.v | 4,325 | module MODULE1
(
VAR33,
VAR18,
VAR23,
VAR4,
VAR21,
VAR6,
VAR1,
VAR8,
VAR28,
VAR39,
VAR11,
VAR24,
VAR14,
VAR40,
VAR5,
VAR17
);
input VAR17;
input VAR33;
input VAR8;
input VAR5;
output [3:0] VAR18;
output VAR23;
output VAR4;
input [3:0] VAR21;
input VAR6;
input VAR1;
input [7:0] VAR28;
input VAR39;
input VAR11;
output [7... | apache-2.0 |
TokiSeven/schoolMIPS | board/marsohod_3/ram_2port.back.v | 11,902 | module MODULE1
(
input [(VAR32-1):0] VAR56, VAR19,
input [(VAR36-1):0] VAR26, VAR11,
input VAR67, VAR69, clk,
output reg [(VAR32-1):0] VAR68, VAR30
);
reg [VAR32-1:0] VAR54[2**VAR36-1:0];
always @ (posedge clk)
begin
if (VAR67)
begin
VAR54[VAR26] <= VAR56;
VAR68 <= VAR56;
end
else
begin
VAR68 <= VAR54[VAR26];
end
end
a... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai_0.v | 2,329 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR9,
VAR3,
VAR10,
VAR7 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR9;
input VAR3;
input VAR10;
input VAR7 ;
input VAR1 ;
VAR2 VAR4 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE2 ... | apache-2.0 |
Digilent/vivado-library | ip/Pmods/PmodAQS_v1_0/src/PmodAQS.v | 9,435 | module MODULE1
(VAR9,
VAR15,
VAR90,
VAR71,
VAR43,
VAR38,
VAR85,
VAR133,
VAR89,
VAR116,
VAR7,
VAR137,
VAR108,
VAR155,
VAR142,
VAR148,
VAR29,
VAR46,
VAR28,
VAR123,
VAR136,
VAR84,
VAR10,
VAR76,
VAR31,
VAR62,
VAR50,
VAR3,
VAR150,
VAR112,
VAR39,
VAR65,
VAR13,
VAR1,
VAR14,
VAR8,
VAR141,
VAR72,
VAR36,
VAR67,
VAR154,
VAR6,
VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_1.functional.v | 1,557 | module MODULE1( VAR12, VAR14, VAR19, VAR5 );
input VAR14, VAR12, VAR19;
output VAR5;
wire VAR17;
and VAR15( VAR17, VAR14, VAR12, VAR19 );
wire VAR3;
not VAR11( VAR3, VAR12 );
wire VAR9;
not VAR16( VAR9, VAR19 );
wire VAR8;
and VAR6( VAR8, VAR3, VAR9, VAR14 );
wire VAR13;
not VAR2( VAR13, VAR14 );
wire VAR7;
and VAR18( ... | apache-2.0 |
nlsynth/nli | lib/fp/fp16rmul.v | 1,844 | module MODULE1(
input clk,
input rst,
input [15:0] VAR11,
input [15:0] VAR16,
output VAR26,
output [4:0] VAR2,
output [4:0] VAR1,
output [11:0] VAR10);
wire VAR12;
wire VAR21;
wire [4:0] VAR5;
wire [4:0] VAR8;
wire [9:0] VAR19;
wire [9:0] VAR13;
wire [10:0] VAR3;
wire [10:0] VAR9;
wire [21:0] VAR15;
wire [11:0] VAR6;
a... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_qdp1.v | 71,000 | module MODULE1 (
VAR371, VAR149, VAR182, VAR376, VAR27,
VAR358, VAR214, VAR312,
VAR198, VAR220, VAR306,
VAR37, VAR370, VAR356,
VAR307, VAR377, VAR363, VAR257,
VAR161, VAR236, VAR124, VAR287,
VAR51, VAR254, VAR47,
VAR123, VAR273, VAR332, VAR276,
VAR127, VAR24, VAR344,
VAR191, VAR122, VAR21,
VAR175, VAR110, VAR10,
VAR294... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_1.functional.v | 1,494 | module MODULE1( VAR3, VAR12, VAR1, VAR8, VAR15 );
input VAR8, VAR15, VAR12, VAR3;
output VAR1;
wire VAR17;
not VAR2( VAR17, VAR8 );
wire VAR6;
not VAR4( VAR6, VAR15 );
wire VAR13;
and VAR9( VAR13, VAR17, VAR6 );
wire VAR18;
not VAR7( VAR18, VAR12 );
wire VAR10;
not VAR16( VAR10, VAR3 );
wire VAR14;
and VAR11( VAR14, VA... | apache-2.0 |
praveendath92/securePUF | ipcore_dir/TemperatureMonitor/example_design/TemperatureMonitor_exdes.v | 4,010 | module MODULE1(
VAR9, VAR5, VAR10, VAR15, VAR7, VAR3, VAR16, VAR6, VAR12);
input VAR6;
input VAR12;
input [6:0] VAR9;
input VAR5;
input VAR10;
input [15:0] VAR15;
input VAR7;
output [15:0] VAR3;
output VAR16;
wire VAR8;
wire [2:0] VAR4;
wire VAR13;
wire VAR14;
wire VAR11;
assign VAR8 = 0;
VAR1
VAR2 (
.VAR9(VAR9[6:0]),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.functional.v | 1,254 | module MODULE1 (
VAR2,
VAR6,
VAR5
);
output VAR2;
input VAR6;
input VAR5;
wire VAR1;
nor VAR4 (VAR1, VAR6, VAR5 );
buf VAR3 (VAR2 , VAR1 );
endmodule | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_sdram_0.v | 23,882 | module MODULE1 (
clk,
rd,
VAR76,
wr,
VAR84,
VAR71,
VAR23,
VAR33,
VAR52,
VAR51
)
;
output VAR71;
output VAR23;
output VAR33;
output VAR52;
output [ 61: 0] VAR51;
input clk;
input rd;
input VAR76;
input wr;
input [ 61: 0] VAR84;
wire VAR71;
wire VAR23;
wire VAR33;
reg [ 1: 0] VAR66;
reg [ 61: 0] VAR18;
reg [ 61: 0] VAR68... | mit |
peteasa/oh | src/common/hdl/oh_mux4.v | 1,205 | module MODULE1 #(parameter VAR8 = 1 ) (
input VAR6,
input VAR3,
input VAR7,
input VAR9,
input [VAR8-1:0] VAR5,
input [VAR8-1:0] VAR2,
input [VAR8-1:0] VAR4,
input [VAR8-1:0] VAR10,
output [VAR8-1:0] out );
assign out[VAR8-1:0] = ({(VAR8){VAR9}} & VAR10[VAR8-1:0] |
{(VAR8){VAR7}} & VAR4[VAR8-1:0] |
{(VAR8){VAR3}} & VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.pp.blackbox.v | 1,406 | module MODULE1 (
VAR3 ,
VAR5,
VAR9 ,
VAR6 ,
VAR2,
VAR10 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR5;
input VAR9 ;
input VAR6 ;
input VAR2;
input VAR10 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2b/sky130_fd_sc_hd__or2b.blackbox.v | 1,266 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR2 ;
input VAR7;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp.blackbox.v | 1,261 | module MODULE1 (
VAR6,
VAR2 ,
VAR4 ,
VAR5
);
input VAR6;
input VAR2 ;
output VAR4 ;
output VAR5;
supply1 VAR1;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21ai/sky130_fd_sc_hvl__o21ai.pp.symbol.v | 1,356 | module MODULE1 (
input VAR4 ,
input VAR7 ,
input VAR2 ,
output VAR3 ,
input VAR6 ,
input VAR5,
input VAR1,
input VAR8
);
endmodule | apache-2.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_dmmu.v | 14,182 | module MODULE1
parameter VAR40 = "VAR9",
parameter VAR1 = 32,
parameter VAR46 = 6,
parameter VAR67 = 1
)
(
input clk,
input rst,
input VAR39,
input [VAR1-1:0] VAR90,
input [VAR1-1:0] VAR47,
output reg [VAR1-1:0] VAR57,
output reg VAR60,
input VAR74,
input VAR3,
input VAR68,
output reg VAR56,
output VAR86,
output reg VA... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi_1.v | 2,361 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR5 ,
VAR2,
VAR10,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR10;
input VAR9 ;
input VAR7 ;
VAR3 VAR11 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR... | apache-2.0 |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_b_downsizer.v | 10,782 | module MODULE1 #
(
parameter VAR24 = "none",
parameter integer VAR34 = 1
)
(
input wire VAR8,
input wire VAR7,
input wire VAR6,
input wire VAR28,
input wire [8-1:0] VAR27,
output wire VAR9,
input wire [VAR34-1:0] VAR36,
output wire [VAR34-1:0] VAR33,
output wire [2-1:0] VAR21,
output wire VAR13,
input wire VAR17,
input... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_1.behavioral.pp.v | 2,623 | module MODULE1( VAR9, VAR7, VAR8, VAR3, VAR5, VAR2 );
input VAR7, VAR9, VAR8;
inout VAR5, VAR2;
output VAR3;
VAR4 VAR6(.VAR9(VAR9),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2));
VAR4 VAR1(.VAR9(VAR9),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR5(VAR5),.VAR2(VAR2)); | apache-2.0 |
Kumikomi/openreroc_gyrosensor | hardware/src/sensor_ctl.v | 2,959 | module MODULE1(
input [0:0] clk,
input VAR15,
input [31:0] VAR11,
input [0:0] VAR4,
input [0:0] VAR17,
output [31:0] VAR30,
output [0:0] VAR10,
output [0:0] VAR20,
input [0:0] VAR24,
output [0:0] VAR34,
output [0:0] VAR18,
output [0:0] VAR37
);
parameter VAR5 = 0,
VAR42 = 1,
VAR43 = 2,
VAR27 = 3,
VAR3 = 4,
VAR19 = 5,
V... | bsd-3-clause |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_AV_Config.v | 15,603 | module MODULE1 (
clk,
reset,
address,
VAR33,
read,
write,
VAR6,
VAR35,
VAR1,
VAR4,
irq,
VAR18,
VAR40
);
input clk;
input reset;
input [ 1: 0] address;
input [ 3: 0] VAR33;
input read;
input write;
input [31: 0] VAR6;
inout VAR35;
output reg [31: 0] VAR1;
output VAR4;
output irq;
output VAR18;
output VAR40;
localparam V... | gpl-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/config_switch1.v | 4,368 | module MODULE1(VAR40, VAR31, VAR4,
VAR16, VAR22, VAR36,
VAR26, VAR28, VAR30,
VAR27);
parameter VAR42 = 1;
parameter VAR3 = 59;
parameter VAR5 = 20;
parameter VAR17 = 20;
parameter VAR13 = 1;
parameter VAR38 = 20;
parameter VAR23 = "VAR39";
input VAR40, VAR31, VAR4;
input [VAR5*VAR42-1:0] VAR16;
input [VAR5-1:0] VAR22;
... | mit |
csturton/wirepatch | system/hardware/cores/uart16550/rtl/verilog/uart_regs.v | 29,069 | module MODULE1 (clk,
VAR78, VAR68, VAR63, VAR2, VAR60, VAR118,
VAR64,
VAR17, VAR89,
VAR158, VAR143, VAR71, VAR58, VAR27, VAR75, VAR151, VAR113, VAR39, VAR115, VAR8,
VAR45, VAR55, VAR162
, VAR127
);
input clk;
input VAR78;
input [VAR132-1:0] VAR68;
input [7:0] VAR63;
output [7:0] VAR2;
input VAR60;
input VAR118;
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr_4.v | 2,265 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR6,
VAR2 ,
VAR4 ,
VAR9 ,
VAR8
);
output VAR3 ;
input VAR7 ;
input VAR6;
input VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR8 ;
VAR5 VAR1 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR3,
VAR7
);
output VAR3;
inpu... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_NTNU/integracion_fisica/front_end/source/sig_register_file.v | 3,017 | module MODULE1(VAR7, VAR17, VAR14, VAR10, VAR12, VAR2,
VAR19,
VAR15, VAR3, VAR8, VAR21);
parameter VAR18 = 'd32;
parameter VAR20 = 32'd0; parameter VAR11 = 32'd1; parameter VAR23 = 32'd2; parameter VAR1 = 32'd128; parameter VAR13 = 32'd127; parameter VAR5 = 32'd5; parameter VAR16 = 32'd6; parameter VAR22 = 32'h20000000... | gpl-3.0 |
unihd-cag/openhmc | rtl/hmc_controller/tx/tx_crc_combine.v | 16,350 | module MODULE1 #(
parameter VAR27 = 2,
parameter VAR24 = 4,
parameter VAR30 = 512
) (
input wire clk,
input wire VAR43,
input wire [VAR24-1:0] VAR45,
input wire [VAR24-1:0] VAR13,
input wire [VAR30-1:0] VAR26,
output wire [VAR30-1:0] VAR8
);
integer if; integer VAR4; integer VAR25;
genvar VAR40, VAR46;
wire [128-1:0] V... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_round_robin_1_to_n.v | 1,549 | module MODULE1 #(parameter VAR9(VAR11 )
,parameter VAR3 = 2)
(input VAR19
, input VAR4
, input VAR15
, output VAR10
, output [VAR3-1:0] VAR21
, input [VAR3-1:0] VAR16
);
if (VAR3 == 1)
begin: VAR1
assign VAR21 = VAR15;
assign VAR10 = VAR16;
end
else
begin: VAR20
wire [VAR13(VAR3)-1:0] VAR2;
wire VAR12 = VAR15 & VAR10;
... | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/board/mem_splitter/acl_iface_ll_fifo.v | 3,348 | module MODULE1(clk, reset, VAR3, write, VAR2, read, VAR8, VAR5);
parameter VAR12 = 32;
parameter VAR10 = 32;
input clk;
input reset;
input [VAR12-1:0] VAR3;
input write;
output [VAR12-1:0] VAR2;
input read;
output VAR8;
output VAR5;
reg [VAR10:0] VAR1;
reg [VAR10:0] VAR16 ;
reg [VAR10-1:0][VAR12-1:0] VAR4;
wire VAR14; ... | mit |
sergeykhbr/riscv_vhdl | vhdl/rtl/rocketlib/behav_srams.v | 5,587 | module MODULE1(
input VAR9,
input [5:0] VAR7,
input VAR10,
input [87:0] VAR11,
input [3:0] VAR3,
input VAR2,
input [5:0] VAR12,
input VAR6,
output [87:0] VAR5
);
reg [5:0] VAR1;
reg [87:0] VAR8 [63:0];
integer VAR4; | apache-2.0 |
airin711/Verilog-caches | 4way_4word.v | 18,453 | module MODULE1(clk,
rst,
VAR34,
VAR21,
VAR27,
VAR46,
VAR38,
VAR6,
VAR50,
VAR25,
VAR16,
VAR59,
VAR44,
VAR48,
VAR49,
VAR12,
VAR2,
VAR41,
VAR5,
VAR17,
VAR32,
VAR47,
VAR42,
VAR57);
parameter VAR29 = 14;
input wire clk, rst;
input wire [24:0] VAR34;
input wire [3:0] VAR21;
input wire [31:0] VAR27;
input wire VAR46, VAR38;
o... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu7t5v0__aoi211_1.behavioral.pp.v | 1,868 | module MODULE1( VAR8, VAR7, VAR3, VAR6, VAR1, VAR2, VAR5 );
input VAR3, VAR8, VAR6, VAR1;
inout VAR2, VAR5;
output VAR7;
VAR9 VAR4(.VAR8(VAR8),.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5));
VAR9 VAR10(.VAR8(VAR8),.VAR7(VAR7),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/altera_avalon_st_idle_remover.v | 2,628 | module MODULE1 (
input clk,
input VAR4,
output reg VAR7,
input VAR2,
input [7: 0] VAR9,
input VAR5,
output reg VAR6,
output reg [7: 0] VAR10
);
reg VAR3;
wire VAR8, VAR1;
assign VAR1 = (VAR9 == 8'h4a);
assign VAR8 = (VAR9 == 8'h4d);
always @(posedge clk or negedge VAR4) begin
if (!VAR4) begin
VAR3 <= 0;
end else begin
... | gpl-2.0 |
hj3938/FPGA-Imaging-Library | InOut/VGA640x480/srcs/VGA640x480.v | 3,529 | module MODULE1(
VAR15,
VAR19,
VAR2,
VAR14,
VAR18,
VAR12,
VAR13,
VAR1,
VAR16
);
input VAR15;
input VAR19;
input [15 : 0] VAR2;
output reg[4:0] VAR14;
output reg[5:0] VAR18;
output reg[4:0] VAR12;
output reg VAR13;
output reg VAR1;
output [16:0] VAR16;
reg[9:0] VAR5;
reg[9:0] VAR10;
reg[16:0] address;
reg VAR3;
parameter... | lgpl-2.1 |
chipsalliance/Cores-SweRV-EL2 | design/dmi/rvjtag_tap.v | 7,077 | module MODULE1 #(
parameter VAR25 = 7
)
(
input VAR6,
input VAR38,
input VAR46,
input VAR12,
output reg VAR21,
output VAR51,
output [31:0] VAR17,
output [VAR25-1:0] VAR30,
output VAR19,
output VAR16,
input [31:0] VAR44,
input [1:0] VAR54,
output reg VAR49,
output reg VAR8,
input [2:0] VAR33,
input [1:0] VAR48,
input [3... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.symbol.v | 1,203 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
nyaxt/dmix | lcdc.v | 5,539 | module MODULE2(
input wire clk, input wire rst,
output wire [8:0] VAR8,
output wire [6:0] VAR31,
output wire VAR44,
output wire VAR17,
output wire VAR38,
input wire [5:0] VAR20,
input wire [5:0] VAR24,
input wire [5:0] VAR18,
input wire VAR19,
output wire [5:0] VAR9,
output wire [5:0] VAR39,
output wire [5:0] VAR32,
ou... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/ea58857b9a21c64b/zqynq_lab_1_design_xbar_1_stub.v | 5,752 | module MODULE1(VAR6, VAR44, VAR29, VAR73,
VAR45, VAR70, VAR35, VAR50, VAR30, VAR69,
VAR32, VAR41, VAR59, VAR57, VAR56, VAR14,
VAR63, VAR2, VAR66, VAR43, VAR12, VAR8, VAR61,
VAR52, VAR18, VAR47, VAR46, VAR5, VAR24,
VAR65, VAR42, VAR68, VAR54, VAR67, VAR34, VAR74,
VAR28, VAR55, VAR11, VAR53, VAR27, VAR26,
VAR71, VAR10, V... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_system/synthesis/submodules/niosII_system_sysid_qsys_0.v | 1,415 | module MODULE1 (
address,
VAR3,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR3;
input VAR2;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1423167773 : 0;
endmodule | gpl-2.0 |
olofk/oh | elink/hdl/erx.v | 8,725 | module MODULE1 (
VAR37, VAR52, VAR42, VAR17,
VAR10, VAR1, VAR57, VAR12, VAR46,
VAR34, VAR2, VAR19, VAR15, timeout,
VAR27, VAR24,
VAR53, VAR23, VAR16, VAR21, VAR28, VAR9,
VAR50, VAR6, VAR58, VAR54, VAR11,
VAR30, VAR55, VAR44, VAR14
);
parameter VAR29 = 32;
parameter VAR35 = 32;
parameter VAR8 = 104;
parameter VAR36 = 6;... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/axi_nes.v | 17,619 | module MODULE1 #(
parameter VAR16 = 8,
parameter VAR80 = 32,
parameter VAR94 = 24,
parameter VAR101 = (VAR80 / 8),
parameter VAR41 = 1,
parameter VAR155 = 1,
parameter VAR54 = 100000000,
parameter VAR52 = 60,
parameter VAR6 = 480,
parameter VAR112 = 272,
parameter VAR83 = 112,
parameter VAR43 = 6,
parameter VAR146 = 0
... | mit |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_decode.v | 52,826 | module MODULE1(
input [VAR353-1:0] VAR149,
input [VAR270-1:0] VAR135,
input VAR12,
input VAR170, input VAR38, input VAR354,
input VAR369,
output VAR438,
output VAR274,
output VAR485,
output VAR145,
output VAR428,
output [VAR252-1:0] VAR280,
output [VAR252-1:0] VAR359,
output [VAR252-1:0] VAR172,
output [VAR148-1:0] VAR... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_4.behavioral.v | 2,309 | module MODULE1( VAR1, VAR2, VAR3, VAR8, VAR6 );
input VAR6, VAR8, VAR3, VAR1;
output VAR2;
VAR4 VAR5(.VAR1(VAR1),.VAR2(VAR2),.VAR3(VAR3),.VAR8(VAR8),.VAR6(VAR6));
VAR4 VAR7(.VAR1(VAR1),.VAR2(VAR2),.VAR3(VAR3),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
azonenberg/openfpga | hdl/xc2c-model/ThreeStageSynchronizer.v | 4,480 | module MODULE1(
input wire VAR12,
input wire din,
input wire VAR16,
output wire dout
);
parameter VAR4 = 1;
wire VAR14; wire VAR8;
wire VAR10;
generate
if(!VAR4)
assign VAR14 = din;
else
VAR2 VAR5 (.VAR11(VAR14), .VAR3(VAR12), .VAR13(1'b1), .VAR6(1'b0), .VAR9(din));
endgenerate
VAR2 VAR1 (.VAR11(VAR8), .VAR3(VAR16), .V... | lgpl-2.1 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_ifqctl.v | 72,174 | module MODULE1(
VAR210, VAR356, VAR231,
VAR437, VAR312, VAR294,
VAR83, VAR391, VAR56,
VAR416, VAR95, VAR458,
VAR130, VAR351, VAR5,
VAR432, VAR199, VAR110,
VAR182, VAR400,
VAR275, VAR93,
VAR404, VAR201, VAR150,
VAR357, VAR257, VAR13, VAR317,
VAR291, VAR18, VAR240,
VAR73, VAR108, VAR446,
VAR336, VAR65, VAR107,
VAR299, VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31oi/sky130_fd_sc_ms__a31oi_2.v | 2,350 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR6 ,
VAR3 ,
VAR8 ,
VAR11,
VAR1,
VAR2 ,
VAR9
);
output VAR7 ;
input VAR10 ;
input VAR6 ;
input VAR3 ;
input VAR8 ;
input VAR11;
input VAR1;
input VAR2 ;
input VAR9 ;
VAR4 VAR5 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR2(VAR2),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or3/sky130_fd_sc_ls__or3.symbol.v | 1,268 | module MODULE1 (
input VAR4,
input VAR2,
input VAR1,
output VAR6
);
supply1 VAR8;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/initial_dram.v | 3,637 | module MODULE1(
reset,
clk,
VAR9,
VAR16, VAR5, VAR17 );
input reset;
input clk;
input VAR9;
input VAR16;
output [VAR18-1:0] VAR5;
output [7:0] VAR17;
reg [VAR18-1:0] VAR5;
reg [7:0] VAR17;
reg [2:0]state;
reg [VAR1-1:0]VAR14;
reg [7:0] enable;
reg [23:0] VAR6;
reg [VAR20-1:0] VAR8;
parameter VAR7 =3'b000;
parameter VAR... | gpl-2.0 |
natsutan/NPU | fpga_implement/npu8/src/q_mul8.v | 2,318 | module MODULE1
(
input VAR25,
input VAR1,
input VAR31,
input [7:0] VAR5,
input [7:0] VAR15,
input [7:0] VAR12,
input [7:0] VAR8,
input VAR29,
input VAR32,
output VAR23,
output [7:0] VAR21,
input [31:0] VAR2,
input [31:0] VAR30,
input [31:0] VAR10,
input [31:0] VAR26,
input [31:0] VAR18,
output [15:0] VAR20,
output [15:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah_1.v | 2,283 | module MODULE1 (
VAR1,
VAR2 ,
VAR3 ,
VAR6 ,
VAR7 ,
VAR5,
VAR11,
VAR4 ,
VAR10
);
output VAR1;
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR5;
input VAR11;
input VAR4 ;
input VAR10 ;
VAR8 VAR9 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR... | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/soc_system_master_non_sec.v | 21,639 | module MODULE1 #(
parameter VAR13 = 0,
parameter VAR18 = 50000,
parameter VAR44 = 2
) (
input wire VAR28, input wire VAR7, output wire [31:0] VAR12, input wire [31:0] VAR17, output wire VAR43, output wire VAR48, output wire [31:0] VAR16, input wire VAR34, input wire VAR1, output wire [3:0] VAR3, output wire VAR11 );
wi... | gpl-3.0 |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_ch_rf.v | 16,440 | module MODULE2( clk, rst,
VAR15, VAR79, VAR67, VAR13, VAR68, VAR74,
VAR3, VAR57, VAR34, VAR58, VAR80, irq,
VAR10, VAR38, VAR89, VAR36,
VAR69, VAR66,
VAR12, VAR29, VAR6, VAR49,
VAR86, VAR47, VAR8, VAR87,
VAR39, VAR56, VAR46, VAR35,
VAR44, VAR28,
VAR31
);
parameter [4:0] VAR25 = 5'h0; parameter [0:0] VAR82 = 1'b1; parame... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode.blackbox.v | 1,197 | module MODULE1 ();
supply1 VAR3;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.behavioral.pp.v | 1,969 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR3 ,
VAR6,
VAR2,
VAR8 ,
VAR11
);
output VAR7 ;
input VAR12 ;
input VAR3 ;
input VAR6;
input VAR2;
input VAR8 ;
input VAR11 ;
wire VAR15 ;
wire VAR10 ;
wire VAR5;
not VAR1 (VAR15 , VAR12 );
and VAR13 (VAR10 , VAR15, VAR3 );
VAR9 VAR4 (VAR5, VAR10, VAR6, VAR2);
buf VAR14 (VAR7 , VAR5 );
... | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/nextRC.v | 2,726 | module MODULE1(
VAR4,
VAR2,
VAR13,
VAR24,
VAR5
);
input VAR13;
input [VAR15-1:0] VAR4;
input [VAR10-1:0] VAR2;
input [VAR18-1:0] VAR24;
output [VAR22 * 4 -1:0] VAR5;
wire [VAR18 - 2:0] VAR7, VAR23, VAR9, VAR1;
assign VAR7 = (VAR24 == 4) ? 2'd0 : ((VAR24 + 2'd1) % 4);
assign VAR23 = (VAR24 == 4) ? 2'd1 : ((VAR24 + 2'd2)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.behavioral.v | 1,302 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR8;
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR2 ;
notif1 VAR7 (VAR6 , VAR4, VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv.behavioral.v | 1,666 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR2,
VAR9
);
output VAR7 ;
input VAR6 ;
input VAR2;
input VAR9;
wire VAR10 ;
wire VAR3;
not VAR4 (VAR10 , VAR6 );
VAR5 VAR8 (VAR3, VAR10, VAR2, VAR9);
buf VAR1 (VAR7 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_4.v | 2,278 | module MODULE2 (
VAR8,
VAR1 ,
VAR4,
VAR9 ,
VAR7,
VAR3,
VAR10 ,
VAR6
);
output VAR8;
input VAR1 ;
input VAR4;
input VAR9 ;
input VAR7;
input VAR3;
input VAR10 ;
input VAR6 ;
VAR2 VAR5 (
.VAR8(VAR8),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.pp.symbol.v | 1,357 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR4 ,
input VAR3,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
subailong/miaow | src/verilog/rtl/wavepool/wavepool_controller.v | 1,939 | module MODULE1 (
VAR12,
VAR20,
VAR35,
VAR34,
VAR23,
VAR16,
VAR7,
VAR3,
VAR9,
VAR19,
VAR21,
VAR5,
VAR28,
VAR6,
VAR24,
VAR1,
VAR31,
VAR30,
VAR18,
clk,
rst
);
input [5:0] VAR12;
input VAR20;
input VAR35;
output [39:0] VAR34;
input [5:0] VAR23;
input VAR16;
output [39:0] VAR7;
input [5:0] VAR3;
input VAR9;
input [5:0] VAR1... | bsd-3-clause |
wyvernSemi/lm32fpga | HDL/rtl/USB_JTAG.v | 4,001 | module MODULE2 ( VAR21, VAR13, VAR12,
VAR18, VAR2, VAR7,VAR3,
VAR4, VAR11, VAR5, VAR6);
input [7:0] VAR21;
input VAR12, VAR7, VAR3;
output reg [7:0] VAR18;
output reg VAR13, VAR2;
input VAR11, VAR5, VAR6;
output VAR4;
wire [7:0] VAR8;
wire VAR15, VAR14;
reg VAR19, VAR9;
reg VAR10;
MODULE1 MODULE1 (VAR8, VAR14, VAR11, V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtn/sky130_fd_sc_ls__sdfrtn.functional.pp.v | 2,348 | module MODULE1 (
VAR16 ,
VAR21 ,
VAR12 ,
VAR6 ,
VAR19 ,
VAR1,
VAR10 ,
VAR9 ,
VAR22 ,
VAR14
);
output VAR16 ;
input VAR21 ;
input VAR12 ;
input VAR6 ;
input VAR19 ;
input VAR1;
input VAR10 ;
input VAR9 ;
input VAR22 ;
input VAR14 ;
wire VAR5 ;
wire VAR7 ;
wire VAR20 ;
wire VAR13;
not VAR11 (VAR7 , VAR1 );
not VAR4 (VAR2... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_auto_pc_2/synth/OpenSSD2_auto_pc_2.v | 13,148 | module MODULE1 (
VAR58,
VAR40,
VAR54,
VAR106,
VAR89,
VAR99,
VAR14,
VAR35,
VAR83,
VAR91,
VAR41,
VAR68,
VAR36,
VAR107,
VAR26,
VAR72,
VAR22,
VAR88,
VAR52,
VAR39,
VAR67,
VAR71,
VAR70,
VAR13,
VAR47,
VAR24,
VAR46,
VAR28,
VAR55,
VAR76,
VAR98,
VAR74,
VAR90,
VAR17,
VAR45,
VAR66,
VAR59,
VAR93,
VAR56,
VAR2,
VAR12,
VAR16,
VAR78,
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp_4.v | 2,184 | module MODULE2 (
VAR1,
VAR2 ,
VAR5 ,
VAR7 ,
VAR3 ,
VAR4
);
input VAR1;
input VAR2 ;
input VAR5 ;
output VAR7 ;
input VAR3 ;
input VAR4 ;
VAR6 VAR8 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR1,
VAR2 ,
VAR5 ,
VAR7
);
input VAR1;
input VAR2 ;
input VAR5 ... | apache-2.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/channelizer/checkpoint256/sysgen/channelizer_256.v | 37,191 | module MODULE16 (
input [32-1:0] VAR235,
output [16-1:0] VAR221,
output [16-1:0] VAR3
);
wire [16-1:0] VAR193;
wire [16-1:0] VAR250;
wire [32-1:0] VAR45;
wire [16-1:0] VAR59;
wire [16-1:0] VAR181;
assign VAR221 = VAR193;
assign VAR3 = VAR250;
assign VAR45 = VAR235;
VAR78 VAR105 (
.clk(1'b0),
.VAR5(1'b0),
.VAR26(1'b0),
... | gpl-3.0 |
fbelavenuto/msx1fpga | src/audio/jt51/jt51_lfo_lfsr.v | 1,224 | module MODULE1 #(parameter VAR4=220 )(
input rst,
input clk,
input VAR3,
output out
);
reg [18:0] VAR1;
assign out = VAR1[18];
reg VAR5;
always @(posedge clk) begin : VAR2
if( rst ) begin
VAR1 <= VAR4[18:0];
VAR5 <= 1'b0;
end
else begin
VAR5 <= VAR3;
if( VAR5 != VAR3 ) begin
VAR1[18:1] <= VAR1[17:0];
VAR1[0] <= ^{VAR1[... | gpl-3.0 |
idgaf/Verilog_codes | Ex3.1/main.v | 1,122 | module MODULE1(VAR12,VAR14,VAR8,VAR4,VAR5,VAR17,VAR15,VAR1,VAR10,VAR21,VAR20);
input wire [3:0]VAR21;
input wire [17:0]VAR10;
output wire [6:0]VAR12;
output wire [6:0]VAR14;
output wire [6:0]VAR8;
output wire [6:0]VAR4;
output wire [6:0]VAR5;
output wire [6:0]VAR17;
output wire [6:0]VAR15;
output wire [6:0]VAR1;
output... | mit |
jameshegarty/rigel | generators/hardfloat/source/compareRecFN.v | 4,382 | module
MODULE1#(parameter VAR8 = 3, parameter VAR13 = 3) (
input [(VAR8 + VAR13):0] VAR28,
input [(VAR8 + VAR13):0] VAR17,
input VAR25,
output VAR16,
output VAR22,
output VAR5,
output VAR23,
output [4:0] VAR34
);
wire VAR32, VAR37, VAR1, VAR20;
wire signed [(VAR8 + 1):0] VAR10;
wire [VAR13:0] VAR35;
VAR2#(VAR8, VAR13)
... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/ipshared/ENCLab/NVMeHostController_v2_0_0/ba7abda2/src/pcie_cntl_slave.v | 6,480 | module MODULE1 # (
parameter VAR21 = 128,
parameter VAR48 = 36
)
(
input VAR12,
input VAR50,
output VAR19,
output VAR56,
input VAR32,
input [VAR21-1:0] VAR65,
output VAR63,
output [7:0] VAR47,
output [15:0] VAR16,
output [11:2] VAR11,
output [11:0] VAR38,
output [6:0] VAR59,
output [63:0] VAR22,
input VAR40,
output VAR... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9122/axi_ad9122.v | 10,025 | module MODULE1 (
VAR59,
VAR66,
VAR24,
VAR122,
VAR49,
VAR64,
VAR7,
VAR70,
VAR63,
VAR110,
VAR135,
VAR43,
VAR114,
VAR68,
VAR26,
VAR35,
VAR125,
VAR129,
VAR76,
VAR126,
VAR38,
VAR37,
VAR82,
VAR95,
VAR41,
VAR34,
VAR87,
VAR36,
VAR44,
VAR103,
VAR39,
VAR54,
VAR100,
VAR18,
VAR136,
VAR19,
VAR15,
VAR84);
parameter VAR128 = 0;
param... | gpl-3.0 |
kkalavantavanich/SD2017 | crcGenMaster.v | 3,872 | /* VAR14 VAR6 VAR33 VAR32 VAR1 VAR24 VAR28.
* VAR39 VAR35 VAR27 use/VAR18/VAR41 in VAR42 VAR5 VAR23 this VAR3 VAR10 VAR25 VAR20 VAR12.
* VAR17: VAR7:
module MODULE1 # (
parameter VAR2 = 40,
parameter VAR9 = 7
)(
clk, VAR37, VAR26, VAR21, VAR4, VAR40, state );
input clk;
input VAR37;
input [VAR2 - 1:0] VAR26;
input [VAR... | mit |
kulp/tenyr | hw/verilog/tmds.v | 1,498 | module MODULE1(
input VAR13,
input VAR3, VAR14, VAR25, VAR4,
output [3:0] VAR12
);
wire VAR16;
wire VAR18;
reg VAR11;
VAR5 VAR8(.VAR13, .VAR17(VAR18), .VAR9(VAR16));
always @(posedge VAR16)
VAR11 <= VAR3;
wire [9:0] VAR24, VAR19;
MODULE2 MODULE2(.clk(VAR16), .VAR11, .VAR6(2'b00) , .VAR4, .VAR7(VAR24));
MODULE2 MODULE1(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2.symbol.v | 1,357 | module MODULE1 (
input VAR4,
output VAR6
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/iobs_new.v | 1,285 | module MODULE1 (
VAR26,
VAR12,
VAR1, VAR32,
VAR14,
VAR35,
VAR21,
VAR7,
VAR29,
VAR8,
VAR22,
VAR31,
VAR6,
VAR16,
VAR9,
VAR5,
VAR23,
VAR10,
VAR28,
VAR38,
VAR20,
VAR4,
VAR15,
VAR13,
VAR17
);
input VAR26;
input VAR12;
input VAR1;
input VAR32;
input VAR14;
input VAR35;
input VAR21;
input VAR7;
input VAR29;
input VAR8;
input ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.v | 2,398 | module MODULE1 (
VAR6 ,
VAR8,
VAR10,
VAR4 ,
VAR5 ,
VAR2,
VAR3,
VAR9 ,
VAR11
);
output VAR6 ;
input VAR8;
input VAR10;
input VAR4 ;
input VAR5 ;
input VAR2;
input VAR3;
input VAR9 ;
input VAR11 ;
VAR7 VAR1 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR11(... | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/apu/apu_frame_counter.v | 3,983 | module MODULE1
(
input VAR11, input VAR8, input VAR9, input VAR3, input [1:0] VAR6, input VAR7, output reg VAR4, output reg VAR13, output reg VAR12 );
reg [14:0] VAR10, VAR5;
reg VAR1, VAR14;
reg VAR15, VAR2;
always @(posedge VAR11)
begin
if (VAR8)
begin
VAR10 <= 15'h0000;
VAR1 <= 1'b0;
VAR15 <= 1'b0;
end
else
begin
VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.behavioral.pp.v | 3,372 | module MODULE1( VAR8, VAR1, VAR7, VAR5, VAR4, VAR6, VAR11, VAR3 );
input VAR4, VAR6, VAR7, VAR1, VAR5;
inout VAR11, VAR3;
output VAR8;
VAR10 VAR2(.VAR8(VAR8),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5),.VAR4(VAR4),.VAR6(VAR6),.VAR11(VAR11),.VAR3(VAR3));
VAR10 VAR9(.VAR8(VAR8),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5),.VAR4(VAR4),.VA... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | mem/memory.v | 8,109 | module MODULE1 ( clk,
rst,
VAR57,
VAR31,
VAR22,
VAR51,
VAR49,
VAR2,
VAR44,
VAR65,
VAR27,
VAR41,
VAR58,
VAR60,
VAR9,
VAR20,
VAR48,
VAR53,
VAR15,
VAR42,
VAR1,
VAR38,
VAR23,
VAR67,
VAR10,
VAR19,
VAR17,
VAR63,
VAR37,
VAR24,
VAR45,
VAR61,
VAR26,
VAR13,
VAR25,
VAR64,
VAR40
);
input clk;
input rst;
input [1:0] VAR57;
input [1... | apache-2.0 |
camacazio/icestick_JSTK2_ORGB | source/SPImode0.v | 7,444 | module MODULE1(
VAR5,
VAR1,
VAR10,
VAR17,
VAR6,
VAR7,
VAR12,
VAR14,
VAR11
);
input VAR5; input VAR1; input VAR10; input [7:0] VAR17; input VAR6; output VAR7; output VAR12; output VAR14; output [7:0] VAR11;
wire VAR7;
wire VAR12;
wire [7:0] VAR11;
reg VAR14;
parameter [1:0] VAR2 = 2'd0,
VAR3 = 2'd1,
VAR15 = 2'd2,
VAR16 ... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_1.behavioral.pp.v | 3,700 | module MODULE1( VAR5, VAR7, VAR16, VAR8, VAR3, VAR27 );
input VAR5, VAR7, VAR16;
inout VAR3, VAR27;
output VAR8;
reg VAR17;
VAR19 VAR26(.VAR5(VAR5),.VAR7(VAR7),.VAR16(VAR16),.VAR8(VAR8),.VAR3(VAR3),.VAR27(VAR27),.VAR17(VAR17));
VAR19 VAR4(.VAR5(VAR5),.VAR7(VAR7),.VAR16(VAR16),.VAR8(VAR8),.VAR3(VAR3),.VAR27(VAR27),.VAR1... | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/priority_encoder.v | 3,062 | module MODULE1 #
(
parameter VAR10 = 4,
parameter VAR9 = "VAR16"
)
(
input wire [VAR10-1:0] VAR8,
output wire VAR13,
output wire [VAR12(VAR10)-1:0] VAR15,
output wire [VAR10-1:0] VAR2
);
parameter VAR7 = 2**VAR12(VAR10);
parameter VAR4 = VAR7/2;
generate
if (VAR10 == 2) begin
assign VAR13 = |VAR8;
if (VAR9 == "VAR16") ... | mit |
elegabriel/myzju | junior1/CA/mips_pipeline2/code/alu.v | 1,882 | module MODULE1(VAR4,VAR2,VAR3,VAR1
);
input wire [31:0] VAR4,VAR2;
input wire [4:0] VAR3;
output reg [31:0] VAR1;
always @*
begin
case(VAR3)
5'd0: begin
VAR1=VAR4+VAR2;
end
5'd1: begin
VAR1=VAR4-VAR2;
end
5'd2: begin
VAR1=VAR4&VAR2;
end
5'd3: begin
VAR1=VAR4|VAR2;
end
5'd6: begin
VAR1=VAR2<<VAR4;
end
5'd10: begin
VAR1=... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa.blackbox.v | 1,293 | module MODULE1 (
VAR6,
VAR4 ,
VAR5 ,
VAR3 ,
VAR2
);
output VAR6;
output VAR4 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
supply1 VAR9;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfstp/sky130_fd_sc_ls__sdfstp.pp.blackbox.v | 1,434 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR9 ,
VAR2 ,
VAR1 ,
VAR3,
VAR4 ,
VAR8 ,
VAR6 ,
VAR10
);
output VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR1 ;
input VAR3;
input VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b_1.v | 2,229 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR5 ,
VAR9,
VAR1,
VAR4 ,
VAR10
);
output VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR9;
input VAR1;
input VAR4 ;
input VAR10 ;
VAR7 VAR8 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms6/common/fmcomms6_spi.v | 3,787 | module MODULE1 (
VAR5,
VAR13,
VAR7,
VAR8,
VAR12);
input [ 2:0] VAR5;
input VAR13;
input VAR7;
output VAR8;
inout VAR12;
reg [ 5:0] VAR3 = 'd0;
reg VAR16 = 'd0;
reg VAR14 = 'd0;
wire VAR4;
wire VAR9;
assign VAR4 = & VAR5;
assign VAR9 = VAR14 & ~VAR4;
always @(posedge VAR13 or posedge VAR4) begin
if (VAR4 == 1'b1) begin
... | gpl-3.0 |
secworks/siphash | src/rtl/siphash_core.v | 15,100 | module MODULE1(
input wire clk,
input wire VAR31,
input wire VAR41,
input wire VAR57,
input wire VAR56,
input wire VAR10,
input wire [3 : 0] VAR46,
input wire [3 : 0] VAR40,
input wire [127 : 0] VAR65,
input wire [63 : 0] VAR68,
output wire ready,
output wire [127 : 0] VAR28,
output wire VAR27
);
localparam VAR8 = 3'h0... | bsd-2-clause |
mballance/wb_dma | rtl/wb_dma_pri_enc_sub.v | 5,042 | module MODULE1(valid, VAR7, VAR2);
parameter [3:0] VAR4 = 4'b0000;
parameter [1:0] VAR5 = 2'd0;
input valid;
input [2:0] VAR7;
output [7:0] VAR2;
wire [7:0] VAR2;
reg [7:0] VAR3;
reg [7:0] VAR8;
reg [7:0] VAR6;
reg [7:0] VAR1;
assign VAR2 = VAR4[0] ? VAR3 : 8'h0;
always @(VAR5 or VAR8 or VAR6 or VAR1)
case(VAR5) 2'd0: ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22a/sky130_fd_sc_hvl__o22a.pp.blackbox.v | 1,389 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR9,
VAR4,
VAR2 ,
VAR6
);
output VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR9;
input VAR4;
input VAR2 ;
input VAR6 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/user_logic.v | 8,143 | module MODULE1 (
VAR20,
VAR4,
VAR40,
VAR7,
VAR50,
VAR5,
VAR39,
VAR26,
VAR6,
VAR44,
VAR27,
VAR13,
VAR28,
VAR10,
VAR49,
VAR38,
VAR33,
VAR2,
VAR21,
VAR18,
VAR45,
VAR15,
VAR9,
VAR12,
VAR30,
VAR36,
VAR37,
VAR35,
VAR1,
VAR24,
VAR46,
VAR25,
VAR14,
VAR31,
VAR47);
parameter VAR3 = 32;
parameter VAR19 = 32;
parameter VAR23 = 0;
... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_12.behavioral.v | 1,098 | module MODULE1( VAR1, VAR2 );
input VAR1;
output VAR2;
VAR5 VAR4(.VAR1(VAR1),.VAR2(VAR2));
VAR5 VAR3(.VAR1(VAR1),.VAR2(VAR2)); | apache-2.0 |
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