repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2/sky130_fd_sc_ms__mux2.functional.v | 1,508 | module MODULE1 (
VAR3 ,
VAR1,
VAR8,
VAR6
);
output VAR3 ;
input VAR1;
input VAR8;
input VAR6 ;
wire VAR4;
VAR2 VAR7 (VAR4, VAR1, VAR8, VAR6 );
buf VAR5 (VAR3 , VAR4);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.v | 2,333 | module MODULE2 (
VAR9 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR8 ,
VAR5,
VAR11,
VAR6 ,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR8 ;
input VAR5;
input VAR11;
input VAR6 ;
input VAR1 ;
VAR7 VAR3 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR6(VAR6),
.... | apache-2.0 |
timvideos/HDMI2USB-jahanzeb-firmware | hdl/hdmi/dvi_encoder_top.v | 5,411 | module MODULE1 (
input wire VAR49, input wire VAR33, input wire VAR44, input wire VAR18, input wire VAR12, input wire [7:0] VAR50, input wire [7:0] VAR26, input wire [7:0] VAR48, input wire VAR38, input wire VAR5, input wire VAR20, output wire [3:0] VAR32,
output wire [3:0] VAR14);
wire [9:0] VAR1 ;
wire [9:0] VAR31 ;
... | bsd-2-clause |
cwilkens/fpga-hero-ii | fpga-hero-ii.srcs/sources_1/new/MusicHero.v | 22,082 | module MODULE1(VAR103, VAR27, VAR29, VAR43, VAR64, VAR107,
VAR100,
VAR89, VAR72, VAR93,
VAR3, VAR2, VAR83, VAR105, VAR61, VAR57, VAR87, VAR73, VAR65, VAR66);
input VAR89;
input VAR72;
input VAR93;
input VAR103;
reg clk;
input VAR100;
output VAR27; output VAR29; output [11:0] VAR43;
wire [7:0] VAR80;
wire [7:0] VAR95;
o... | mit |
mballance/oc_wb_ip | rtl/wb_dma/bench/verilog/wb_slv_model.v | 5,018 | module MODULE1(clk, rst, VAR7, din, dout, VAR3, VAR8, sel, VAR12, ack, VAR13, VAR10);
input clk, rst;
input [31:0] VAR7, din;
output [31:0] dout;
input VAR3, VAR8;
input [3:0] sel;
input VAR12;
output ack, VAR13, VAR10;
parameter VAR4 = 13;
parameter VAR6 = (1<<VAR4)-1;
reg [31:0] VAR14[VAR6:0];
wire VAR9, VAR2;
wire [... | apache-2.0 |
mbus/mbus | layer_controller_v1/verilog/layer_wrapper.v | 8,616 | module MODULE1(
VAR139,
VAR26,
VAR153,
VAR69,
VAR66,
VAR68,
VAR12,
VAR57
);
parameter VAR129 = 64; parameter VAR34 = 64;
parameter VAR82 = 20'hccccc;
parameter VAR146 =24;
parameter VAR97 = 128;
parameter VAR103 = 32; parameter VAR161 = 32; parameter VAR93 = 65536;
parameter VAR147 = 8;
input VAR139;
input VAR26;
input... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32a/sky130_fd_sc_hd__o32a.pp.symbol.v | 1,390 | module MODULE1 (
input VAR4 ,
input VAR10 ,
input VAR7 ,
input VAR9 ,
input VAR3 ,
output VAR5 ,
input VAR6 ,
input VAR8,
input VAR1,
input VAR2
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.behavioral.pp.v | 2,030 | module MODULE1( VAR4, VAR1, VAR7, VAR5, VAR6, VAR8, VAR9 );
input VAR5, VAR7, VAR4, VAR6;
inout VAR8, VAR9;
output VAR1;
VAR10 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR8(VAR8),.VAR9(VAR9));
VAR10 VAR3(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR8(VAR8),.VAR9(VAR9)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcon/sky130_fd_sc_ms__fahcon.behavioral.v | 1,829 | module MODULE1 (
VAR1,
VAR18 ,
VAR11 ,
VAR17 ,
VAR16
);
output VAR1;
output VAR18 ;
input VAR11 ;
input VAR17 ;
input VAR16 ;
supply1 VAR12;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR2 ;
wire VAR19 ;
wire VAR21 ;
wire VAR7 ;
wire VAR3 ;
wire VAR5;
xor VAR13 (VAR19 , VAR11, VAR17, VAR16 );
buf VAR10 (VAR18 , VAR19 );
nor ... | apache-2.0 |
catompiler/fpgalibs | bin2bcd/bin2bcd.v | 2,812 | module MODULE1(input wire[3:0] VAR3, output reg[3:0] VAR12);
always @(VAR3) begin
case (VAR3)
4'b0101: VAR12 <= 4'b1000;
4'b0110: VAR12 <= 4'b1001;
4'b0111: VAR12 <= 4'b1010;
4'b1000: VAR12 <= 4'b1011;
4'b1001: VAR12 <= 4'b1100;
4'b1010: VAR12 <= 4'b1101;
4'b1011: VAR12 <= 4'b1110;
4'b1100: VAR12 <= 4'b1111;
default: V... | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/submodules/system_acl_iface_hps_hps_io.v | 6,777 | module MODULE1 (
output wire [14:0] VAR33, output wire [2:0] VAR2, output wire VAR34, output wire VAR25, output wire VAR18, output wire VAR4, output wire VAR43, output wire VAR15, output wire VAR30, output wire VAR19, inout wire [31:0] VAR23, inout wire [3:0] VAR13, inout wire [3:0] VAR11, output wire VAR35, output wir... | mit |
Elphel/x393_sata | host/oob.v | 23,947 | module MODULE2 #(
parameter VAR55 = 4,
parameter VAR39 = 1 )
(
output reg [11:0] VAR94,
input wire clk, input wire rst, input wire VAR81,
input wire VAR132,
input wire VAR65,
output wire VAR67,
output wire VAR91,
output wire VAR34,
output wire VAR23, input wire VAR109,
output wire VAR11, input wire VAR59,
output wire V... | gpl-3.0 |
miamiasheep/nctu-dlab-99 | online2B/TrafficLight.v | 1,150 | module MODULE1(
input VAR14, VAR7, VAR8,
output reg [1:0] VAR2, VAR11
);
localparam VAR9 = 3'd0;
localparam VAR5 = 3'd1;
localparam VAR3 = 3'd2;
localparam VAR10 = 3'd3;
localparam VAR6 = 3'd4;
localparam VAR4 = 2'd0;
localparam VAR13 = 2'd1;
localparam VAR12 = 2'd2;
reg [2:0] state, VAR1;
always @(posedge VAR7)
begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.symbol.v | 1,276 | module MODULE1 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/aurora_lane_4byte.v | 10,261 | module MODULE1
(
VAR24,
VAR41,
VAR66,
VAR38,
VAR47,
VAR26,
VAR3,
VAR37,
VAR63,
VAR40,
VAR57,
VAR56,
VAR61,
VAR6,
VAR15,
VAR44,
VAR11,
VAR36,
VAR39,
VAR25,
VAR9,
VAR62,
VAR33,
VAR35,
VAR14,
VAR10,
VAR8,
VAR51,
VAR53,
VAR5,
VAR16,
VAR45,
VAR7,
VAR19,
VAR18,
VAR1,
VAR46,
VAR21,
VAR43
);
input [31:0] VAR24; input [3:0] VAR... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor2/sky130_fd_sc_hdll__xnor2.pp.symbol.v | 1,312 | module MODULE1 (
input VAR5 ,
input VAR3 ,
output VAR1 ,
input VAR7 ,
input VAR6,
input VAR2,
input VAR4
);
endmodule | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/DOUBLE/FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6_FSM_Add_Subtract_syn.v | 6,153 | module MODULE2 ( clk, rst, VAR112, VAR154, VAR165,
VAR136, VAR88, VAR43, VAR116, VAR70,
VAR68, VAR184, VAR106, VAR63, VAR126, VAR1,
VAR77, VAR29, VAR181, VAR33, VAR141, VAR85,
VAR73, VAR185, VAR79, ready );
output [1:0] VAR141;
input clk, rst, VAR112, VAR154, VAR165, VAR136,
VAR88, VAR43;
output VAR116, VAR70, VAR68, V... | gpl-3.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_uartlite_0_0/system_axi_uartlite_0_0_stub.v | 2,273 | module MODULE1(VAR13, VAR1, interrupt,
VAR4, VAR12, VAR19, VAR2, VAR7, VAR17,
VAR9, VAR18, VAR10, VAR5, VAR16, VAR15,
VAR6, VAR20, VAR14, VAR11, VAR21, VAR3, VAR8)
;
input VAR13;
input VAR1;
output interrupt;
input [3:0]VAR4;
input VAR12;
output VAR19;
input [31:0]VAR2;
input [3:0]VAR7;
input VAR17;
output VAR9;
output... | apache-2.0 |
AloriumTechnology/XLR8LFSR | extras/rtl/openxlr8.v | 15,511 | module MODULE1
parameter VAR10 = 1;
logic [VAR10-1:0][VAR27-1:0] VAR11;
logic [VAR10-1:0][VAR27-1:0] VAR13;
logic [VAR10-1:0][VAR27-1:0] VAR17;
logic [VAR10-1:0][VAR27-1:0] VAR28;
logic [7:0] VAR21;
logic VAR33;
logic VAR3;
logic VAR30;
VAR35
.VAR14 (VAR4),
.VAR7 (VAR8),
.VAR22 (VAR20),
.VAR12 (8)
)
VAR23
( .VAR24 (VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfsbp/sky130_fd_sc_hdll__sdfsbp.behavioral.pp.v | 2,973 | module MODULE1 (
VAR16 ,
VAR23 ,
VAR9 ,
VAR7 ,
VAR31 ,
VAR18 ,
VAR1,
VAR6 ,
VAR25 ,
VAR4 ,
VAR22
);
output VAR16 ;
output VAR23 ;
input VAR9 ;
input VAR7 ;
input VAR31 ;
input VAR18 ;
input VAR1;
input VAR6 ;
input VAR25 ;
input VAR4 ;
input VAR22 ;
wire VAR33 ;
wire VAR27 ;
wire VAR30 ;
reg VAR26 ;
wire VAR32 ;
wire V... | apache-2.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/mod_rom.v | 1,223 | module MODULE1(rst, clk, VAR3, VAR5, VAR2, VAR7, VAR8, din, VAR10, dout);
input rst;
input clk;
input VAR3,VAR5;
input [31:0] VAR2, VAR7;
input [1:0] VAR8;
input [31:0] din;
output [31:0] VAR10, dout;
wire [31:0] VAR1, VAR6;
assign VAR10 = VAR1;
assign dout = VAR6;
VAR9 VAR4(clk,clk,1'b1,1'b1,VAR2[10:2],VAR7[10:2],VAR1... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9625/axi_ad9625_channel.v | 5,828 | module MODULE1 (
VAR12,
VAR25,
VAR31,
VAR14,
VAR61,
VAR60,
VAR40,
VAR35,
VAR23,
VAR48,
VAR54,
VAR43,
VAR6,
VAR20,
VAR45,
VAR9,
VAR39,
VAR4,
VAR65);
input VAR12;
input VAR25;
input [191:0] VAR31;
input VAR14;
output [255:0] VAR61;
output VAR60;
output VAR40;
output VAR35;
output VAR23;
input VAR48;
input VAR54;
input VA... | gpl-3.0 |
alan4186/16bit-Processor | register_file.v | 3,871 | module MODULE1
(
input clk, rst, VAR2,
input [3:0] VAR52, VAR14, VAR33, VAR7,
input [15:0] VAR18,
output reg [15:0] VAR3, VAR17, VAR22
);
wire VAR29, VAR48, VAR36, VAR54, VAR53, VAR56, VAR23, VAR57, VAR19, VAR40, VAR21, VAR15, VAR6, VAR8, VAR43, VAR35;
wire [15:0] VAR13, VAR11, VAR1, VAR34, VAR46, VAR25, VAR26, VAR45, ... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_jesd_cntrl.v | 7,716 | module MODULE1 (
VAR24,
VAR17,
VAR10,
VAR19,
VAR18,
VAR7,
VAR13,
VAR21,
VAR4,
VAR2,
VAR5,
VAR9);
input VAR24;
input VAR17;
input [31:0] VAR10;
input [ 3:0] VAR19;
input [ 3:0] VAR18;
input [ 3:0] VAR7;
input VAR13;
input VAR21;
output VAR4;
output VAR2;
output [ 4:0] VAR5;
output [55:0] VAR9;
localparam VAR14 = 4'h0;
l... | mit |
natsutan/NPU | fpga_implement/npu8/src/cpu_if.v | 6,754 | module MODULE1
(
input VAR16,
input VAR11,
input [7:0] VAR4,
output reg [31:0] VAR2,
input VAR19,
input VAR6,
input [31:0] VAR27,
output reg VAR3,
output reg VAR26,
output reg VAR34,
input VAR37,
output reg [1:0] VAR36, output reg [1:0] VAR38,
output reg [1:0] VAR24,
output reg [1:0] VAR10,
output reg VAR5,
output reg ... | bsd-3-clause |
trun/fpgaboy | src/gb/interrupt.v | 3,903 | module MODULE1 (
input wire VAR31,
input wire reset,
input wire VAR11,
input wire VAR23,
output wire VAR9,
input wire [4:0] VAR14,
output reg [4:0] VAR4,
output wire [7:0] VAR18,
input wire [15:0] VAR12,
input wire [7:0] VAR26,
output wire [7:0] VAR30,
input wire VAR29,
input wire VAR17,
input wire VAR22
);
wire[7:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv_1.v | 1,995 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR4,
VAR5,
VAR2 ,
VAR7
);
output VAR8 ;
input VAR6 ;
input VAR4;
input VAR5;
input VAR2 ;
input VAR7 ;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8,
VAR6
);
output VAR8;
input VAR6;
supply1 VAR4;
supply0 VAR5;... | apache-2.0 |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_dbg_hwbrk.v | 11,032 | module MODULE1 (
VAR47, VAR29, VAR36,
VAR50, VAR13, VAR3, VAR56, VAR12, VAR53, VAR44, VAR1, VAR5, VAR31, VAR30, VAR54, VAR58 );
output VAR47; output VAR29; output [15:0] VAR36;
input [3:0] VAR50; input [3:0] VAR13; input [15:0] VAR3; input [15:0] VAR56; input VAR12; input [1:0] VAR53; input [15:0] VAR44; input [15:0] V... | bsd-3-clause |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ipshared/xilinx.com/axi_register_slice_v2_1/hdl/verilog/axi_register_slice_v2_1_axi_register_slice.v | 18,652 | module MODULE1 #
(
parameter VAR90 = "VAR29",
parameter VAR57 = 0,
parameter integer VAR78 = 4,
parameter integer VAR101 = 32,
parameter integer VAR96 = 32,
parameter integer VAR77 = 0,
parameter integer VAR95 = 1,
parameter integer VAR93 = 1,
parameter integer VAR109 = 1,
parameter integer VAR119 = 1,
parameter intege... | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/mux.v | 5,119 | module MODULE2
parameter VAR4 = 4,
parameter VAR3 = 2,
parameter VAR11 = 32,
parameter VAR5 = "VAR1"
)
(
input [(VAR4)*VAR11-1:0] VAR10,
input [VAR3-1:0] VAR12,
output [VAR11-1:0] VAR7
);
generate
if(VAR5 == "VAR1") begin
MODULE1
.VAR4 (VAR4),
.VAR3 (VAR3),
.VAR11 (VAR11))
VAR6
(
.VAR7 (VAR7[VAR11-1:0]),
.VAR10 (VAR10[... | bsd-3-clause |
James534/Tempest | fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/DE0_Nano_SOPC_i2c_scl.v | 2,219 | module MODULE1 (
address,
VAR5,
clk,
VAR2,
VAR9,
VAR1,
VAR3,
VAR4
)
;
output VAR3;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR2;
input VAR9;
input [ 31: 0] VAR1;
wire VAR7;
reg VAR6;
wire VAR3;
wire VAR8;
wire [ 31: 0] VAR4;
assign VAR7 = 1;
assign VAR8 = {1 {(address == 0)}} & VAR6;
a... | mit |
bigeagle/riffa | fpga/riffa_hdl/channel.v | 21,216 | module MODULE1
parameter VAR9 = 128,
parameter VAR33 = 2, parameter VAR54 = VAR43((VAR9/32)+1)
)
(
input VAR3,
input VAR53,
input [2:0] VAR44, input [2:0] VAR2,
input [31:0] VAR13, input [VAR9-1:0] VAR64,
output VAR5, input VAR61, input VAR14, input VAR4,
output VAR68, input VAR63, input VAR56, input VAR69,
input VAR27... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/usdrx1/common/usdrx1_spi.v | 4,371 | module MODULE1 (
VAR13,
VAR15,
VAR14,
VAR5,
VAR11,
VAR3,
VAR2);
input [ 3:0] VAR13;
input VAR15;
input VAR14;
input VAR5;
output VAR11;
inout VAR3;
inout VAR2;
reg [ 5:0] VAR7 = 'd0;
reg VAR1 = 'd0;
reg VAR6 = 'd0;
wire [ 1:0] VAR8;
wire VAR16;
wire VAR4;
wire VAR12;
wire VAR10;
assign VAR8[1] = & VAR13;
assign VAR8[0]... | gpl-3.0 |
combinatorylogic/soc | backends/tiny1/hw/ice/ice40mem.v | 2,472 | module MODULE1(
output [1:0] VAR4,
input VAR11, VAR23, VAR9,
input [10:0] VAR30,
input VAR13, VAR34, VAR32,
input [10:0] VAR36,
input [1:0] VAR28, VAR25
);
parameter VAR26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter VAR22 = 256'h0000000000000000000000000000000000000000000000000000... | mit |
zhangly/azpr_cpu | rtl/top/rtl/clk_gen.v | 1,682 | module MODULE1 (
input wire VAR4, input wire VAR14,
output wire clk, output wire clk,
output wire VAR1 );
wire VAR12; wire VAR3;
assign VAR3 = (VAR14 == VAR9) ? VAR2 : VAR13;
assign VAR1 = ((VAR14 == VAR9) || (VAR12 == VAR13)) ?
VAR7 VAR10 (
.VAR8 (VAR4), .VAR11 (VAR3), .VAR6 (clk), .VAR5 (clk), .VAR12 (VAR12) );
endmo... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/response_generator.v | 3,347 | module MODULE1 (
input clk,
input VAR3,
input enable,
output reg VAR8,
input [VAR1-1:0] VAR9,
output reg [VAR1-1:0] VAR12,
input VAR6,
input VAR5,
output VAR10,
input VAR4,
output VAR11,
output [1:0] VAR13
);
parameter VAR1 = 3;
assign VAR13 = VAR2;
assign VAR11 = VAR5;
assign VAR10 = VAR9 != VAR12 && VAR8;
always @(po... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/nios_system_jtag_uart_0.v | 17,721 | module MODULE1 (
clk,
VAR7,
VAR12,
VAR19,
VAR14,
VAR1,
VAR17
)
;
output VAR19;
output [ 7: 0] VAR14;
output VAR1;
output [ 5: 0] VAR17;
input clk;
input [ 7: 0] VAR7;
input VAR12;
wire VAR19;
wire [ 7: 0] VAR14;
wire VAR1;
wire [ 5: 0] VAR17;
always @(posedge clk)
begin
if (VAR12)
("%VAR51", VAR7);
end
assign VAR17 = {... | gpl-3.0 |
jotego/jt12 | hdl/jt12_pg_comb.v | 2,568 | module MODULE1(
input [ 2:0] VAR26,
input [10:0] VAR21,
input [ 4:0] VAR8,
input [ 2:0] VAR19,
input [ 2:0] VAR4,
output [ 4:0] VAR16,
output signed [5:0] VAR13,
output [16:0] VAR18,
input [ 3:0] VAR15,
input [19:0] VAR11,
input VAR9,
input signed [5:0] VAR12,
input [16:0] VAR6,
output [19:0] VAR17,
output [ 9:0] VAR14... | gpl-3.0 |
dailypips/miaow | src/verilog/rtl/issue/mux_40xPARAMb_to_1xPARAMb.v | 2,764 | module MODULE1(
out,
in,
select );
parameter VAR1 = 12;
input[40*VAR1-1:0] in;
input[5:0] select;
output[VAR1-1:0] out;
reg[VAR1-1:0] out;
always @(in or select) begin
casex(select)
6'h00: out = in[1*VAR1-1:0*VAR1];
6'h01: out = in[2*VAR1-1:1*VAR1];
6'h02: out = in[3*VAR1-1:2*VAR1];
6'h03: out = in[4*VAR1-1:3*VAR1];
6'... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4_1.v | 2,242 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR8,
VAR9,
VAR3 ,
VAR11
);
output VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR9;
input VAR3 ;
input VAR11 ;
VAR1 VAR4 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR3(VAR3),
.VA... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_sort_4.v | 2,106 | module MODULE1 #(parameter VAR4(VAR3),
VAR6 = 4
, VAR1 = VAR3-1
, VAR5 = 0
)
(input [VAR3-1:0] VAR2 [VAR6-1:0]
, output [VAR3-1:0] VAR7 [VAR6-1:0]
); | bsd-3-clause |
rkrajnc/minimig-mist | rtl/minimig/agnus_blitter_barrelshifter.v | 2,492 | module MODULE1
(
input VAR5, input [3:0] VAR1, input [15:0] VAR6, input [15:0] VAR4, output [15:0] out );
wire [35:0] VAR7; wire [35:0] VAR3; reg [17:0] VAR2;
always @(VAR5 or VAR1)
case ({VAR5,VAR1[3:0]})
5'h00 : VAR2 = 18'h10000;
5'h01 : VAR2 = 18'h08000;
5'h02 : VAR2 = 18'h04000;
5'h03 : VAR2 = 18'h02000;
5'h04 : VA... | gpl-3.0 |
GREO/GNU-Radio | usrp/fpga/megacells/mylpm_addsub_bb.v | 1,607 | module MODULE1 (
VAR5,
VAR3,
VAR2,
VAR1,
VAR4);
input VAR5;
input [15:0] VAR3;
input [15:0] VAR2;
input VAR1;
output [15:0] VAR4;
endmodule | gpl-3.0 |
wgml/sysrek | skin_color_segm/ipcore_dir/summator_add.v | 16,438 | module MODULE2 (
VAR83, VAR134, VAR180, VAR85
);
input VAR83;
input [27 : 0] VAR134;
input [9 : 0] VAR180;
output [27 : 0] VAR85;
wire \VAR32/VAR61 ;
wire \VAR32/VAR84 ;
wire \VAR32/VAR31 ;
wire \VAR32/VAR155 ;
wire \VAR32/VAR184 ;
wire \VAR32/VAR86 ;
wire \VAR32/VAR104 ;
wire \VAR32/VAR40 ;
wire \VAR32/VAR135 ;
wire \... | gpl-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_pcie/source/PCIeGen2x8If128_gt_common.v | 7,321 | module MODULE1 #(
parameter VAR58 = "VAR19", parameter VAR38 = "VAR56", parameter VAR9 = "2.1", parameter VAR1 = "VAR59", parameter VAR30 = 0 )
(
input VAR7,
input VAR52,
input VAR21,
input VAR12,
input VAR2,
input VAR53,
input VAR26,
input VAR10,
input VAR5,
output [5:0] VAR31,
output [8:0] VAR22,
output VAR55,
output... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_acv_ldc.v | 3,427 | module MODULE1
(
VAR27,
VAR17,
VAR44,
VAR32,
VAR20,
VAR12,
VAR28,
VAR8,
VAR38
);
parameter VAR22 = "";
parameter VAR19 = 0;
parameter VAR7 = "false";
parameter VAR11 = "false";
input VAR27;
input VAR17;
input VAR44;
input [VAR22-1:0] VAR32;
output VAR20;
output VAR12;
output VAR28;
output VAR8;
output VAR38;
wire VAR21... | gpl-3.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/m_req_upload.v | 8,278 | module MODULE1( clk,
rst,
VAR34,
VAR7,
VAR46,
VAR49,
VAR25,
VAR27,
VAR5,
VAR1,
VAR13,
VAR20,
VAR52,
VAR19
);
input clk;
input rst;
input VAR34;
input VAR7;
input VAR46;
input [3:0] VAR49;
input [3:0] VAR25;
input [15:0] VAR27;
input [15:0] VAR5;
input [15:0] VAR1;
output [1:0] VAR13;
output [15:0] VAR20;
output [1:0] V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4/sky130_fd_sc_hdll__and4_4.v | 2,258 | module MODULE2 (
VAR10 ,
VAR9 ,
VAR3 ,
VAR4 ,
VAR5 ,
VAR6,
VAR8,
VAR7 ,
VAR11
);
output VAR10 ;
input VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR6;
input VAR8;
input VAR7 ;
input VAR11 ;
VAR2 VAR1 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.blackbox.v | 1,362 | module MODULE1 (
VAR4 ,
VAR6,
VAR5,
VAR7,
VAR8
);
output VAR4 ;
input VAR6;
input VAR5;
input VAR7;
input VAR8;
supply1 VAR3;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_best_delta_seg1.v | 10,071 | module MODULE1 (
VAR5,
VAR69,
VAR89,
VAR85,
VAR78,
VAR33,
VAR56,
VAR79,
VAR43,
VAR45,
VAR10,
VAR73,
VAR91,
VAR6
);
parameter VAR72 = 2'b11;
parameter VAR62 = 2'b1;
parameter VAR21 = 2'b00;
parameter VAR1 = 7'b1111111;
parameter VAR49 = 32'b10;
parameter VAR28 = 32'b11;
parameter VAR16 = 2'b10;
parameter VAR50 = 32'b100... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_4.behavioral.v | 1,098 | module MODULE1( VAR1, VAR3 );
input VAR1;
output VAR3;
VAR5 VAR2(.VAR1(VAR1),.VAR3(VAR3));
VAR5 VAR4(.VAR1(VAR1),.VAR3(VAR3)); | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPCG_Toggle_BNC_B_erase.v | 8,752 | module MODULE1
(
parameter VAR37 = 4
)
(
VAR3 ,
VAR11 ,
VAR25 ,
VAR16 ,
VAR13 ,
VAR12 ,
VAR32 ,
VAR27 ,
VAR1 ,
VAR15 ,
VAR9 ,
VAR34 ,
VAR4 ,
VAR7 ,
VAR35 ,
VAR23 ,
VAR21 ,
VAR14 ,
VAR18 ,
VAR2
);
input VAR3 ;
input VAR11 ;
input [5:0] VAR25 ;
input [4:0] VAR16 ;
input [4:0] VAR13 ;
input VAR12 ;
output VAR32 ;
input [V... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs.v | 33,046 | module MODULE1
parameter VAR37 = 13,
parameter VAR143 = 8,
parameter VAR125 = 2,
parameter VAR54 = 8,
parameter VAR144 = VAR32(VAR54),
parameter VAR145 = 11,
parameter VAR74 = VAR145-VAR32(VAR143)
)
(
VAR47,
VAR94,
VAR25,
VAR58,
VAR45,
VAR40,
VAR106,
VAR111,
VAR13,
VAR93,
VAR53,
VAR56,
VAR72,
VAR5,
VAR127,
VAR96,
VAR13... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21oi/sky130_fd_sc_hdll__a21oi.behavioral.pp.v | 2,026 | module MODULE1 (
VAR9 ,
VAR14 ,
VAR15 ,
VAR1 ,
VAR7,
VAR2,
VAR10 ,
VAR3
);
output VAR9 ;
input VAR14 ;
input VAR15 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR10 ;
input VAR3 ;
wire VAR13 ;
wire VAR16 ;
wire VAR12;
and VAR11 (VAR13 , VAR14, VAR15 );
nor VAR6 (VAR16 , VAR1, VAR13 );
VAR8 VAR4 (VAR12, VAR16, VAR7, VA... | apache-2.0 |
ThomasLee969/verilog-homework | exp3/freq_meter/siginput.v | 1,026 | module MODULE1(
input [1:0] VAR5, input VAR2, output VAR3 );
reg [20:0] state;
reg [20:0] VAR1;
reg VAR4;
assign VAR3 = VAR4;
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf.symbol.v | 1,262 | module MODULE1 (
input VAR6,
output VAR1
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
chasingegg/Computer_Systems | CS334_computer organization lab/source/lab3_Ctr/Ctr.v | 1,963 | module MODULE1(
input [5:0] VAR4,
output VAR8,
output VAR3,
output VAR7,
output VAR6,
output VAR9,
output VAR1,
output VAR5,
output [1:0] VAR10,
output VAR2
);
reg VAR8;
reg VAR3;
reg VAR7;
reg VAR6;
reg VAR9;
reg VAR1;
reg VAR5;
reg[1:0] VAR10;
reg VAR2;
always @(VAR4)
begin
case(VAR4)
6'b000010: begin
VAR8=0;
VAR3=0;... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_onchip_ram_top.v | 8,148 | module MODULE1 (
VAR18, VAR28,
VAR21, VAR5, VAR32, VAR3, VAR23, VAR14,
VAR15, VAR11, VAR40
);
parameter VAR34 = 13; localparam VAR24 = 11; localparam VAR6 = (1<<(VAR34-VAR24));
input VAR18;
input VAR28;
input [31:0] VAR21;
output [31:0] VAR5;
input [31:0] VAR32;
input [3:0] VAR3;
input VAR23;
input VAR14;
input VAR15;
... | gpl-2.0 |
zhijian-liu/mips-cpu | src/cpu/latch/latch_ex_mem.v | 3,017 | module MODULE1(
input VAR20 ,
input reset ,
input [ 5:0] VAR19 ,
input [31:0] VAR12 ,
output reg [31:0] VAR8 ,
input [ 7:0] VAR21 ,
output reg [ 7:0] VAR5 ,
input [31:0] VAR26 ,
output reg [31:0] VAR17 ,
input [31:0] VAR11 ,
output reg [31:0] VAR28 ,
input VAR22 ,
output reg VAR4 ,
input [ 4:0] VAR16 ,
output reg [ 4:0... | mit |
Elphel/x353 | control/cmd_sequencer.v | 11,645 | module MODULE1 (VAR33, VAR68, VAR53, VAR2, sync, VAR64, VAR42, VAR9, VAR39, VAR14); input VAR33;
input VAR68;
input [ 3:0] VAR53;
input [15:0] VAR2;
input sync;
output VAR64; input VAR42; output [ 7:0] VAR9; output [23:0] VAR39; output [2:0] VAR14;
reg [3:0] VAR70; reg [3:0] VAR41;
reg [15:0] VAR52;
reg [15:0] VAR27;
r... | gpl-3.0 |
bargei/NoC264 | NoC264_3x3/module_outport_encoder.v | 2,656 | module MODULE1(VAR1,
VAR2);
input [4 : 0] VAR1;
output [3 : 0] VAR2;
wire [3 : 0] VAR2;
assign VAR2 =
{ VAR1[0] || VAR1[1] ||
VAR1[2] ||
VAR1[3] ||
VAR1[4],
VAR1[0] ?
3'd0 :
(VAR1[1] ?
3'd1 :
(VAR1[2] ?
3'd2 :
(VAR1[3] ? 3'd3 : 3'd4))) } ;
endmodule | mit |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/Divide.v | 3,498 | module MODULE1(
input VAR1,
input reset,
input VAR8, input VAR3, input [31:0] VAR13,
input [31:0] VAR17,
output [31:0] VAR7,
output [31:0] VAR11,
output VAR10, input VAR12, input neg, input [31:0] VAR19, input [31:0] VAR4, input [31:0] VAR2,
output reg VAR16, output reg VAR18, output reg [31:0] VAR14, output reg [31:0]... | lgpl-3.0 |
bgamari/timetag-fpga | sample_multiplexer.v | 1,031 | module MODULE1(
clk,
VAR3, VAR7, VAR6,
VAR1, VAR4, VAR2
);
input clk;
input [47:0] VAR3;
input VAR7;
output VAR6;
input VAR2;
output [7:0] VAR1;
output VAR4;
wire [7:0] VAR1;
reg [1:0] state;
reg [2:0] VAR8;
VAR5 state = 0;
always @(posedge clk)
case (state)
0: if (VAR7)
begin
state <= 1;
VAR8 <= 0;
end
1: state <= 2;
... | gpl-3.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_mm_interconnect_0_avalon_st_adapter_006.v | 6,164 | module MODULE1 #(
parameter VAR23 = 18,
parameter VAR21 = 0,
parameter VAR24 = 18,
parameter VAR5 = 0,
parameter VAR10 = 0,
parameter VAR20 = 0,
parameter VAR11 = 1,
parameter VAR13 = 1,
parameter VAR4 = 0,
parameter VAR6 = 18,
parameter VAR25 = 0,
parameter VAR3 = 1,
parameter VAR2 = 0,
parameter VAR12 = 1,
parameter ... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/subRecursiveKOA.v | 4,959 | module MODULE1
(
input wire clk,
input wire [VAR4-1:0] VAR7,
input wire [VAR4-1:0] VAR11,
output wire [2*VAR4-1:0] VAR33
);
localparam integer VAR10 = VAR10;
generate
if (VAR4 <= VAR10) begin : VAR20
VAR5 #(.VAR4(VAR4))
VAR30 (
.clk(clk),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR33(VAR33)
);
end else begin : VAR14
reg [2*VAR4-1... | gpl-3.0 |
tfiwits/D-Clock | all_case.v | 1,638 | module MODULE1 (
VAR22,VAR21,VAR7,VAR16,VAR13,
rst,VAR24,VAR2,VAR27,VAR14,
VAR19,VAR25,
VAR11,VAR3,VAR10,VAR1,VAR6,VAR12,VAR26,VAR17,VAR9,VAR4,VAR8,VAR20,
VAR5,VAR18,VAR15,VAR23,
);
input VAR22,rst,VAR11,VAR3,VAR10,VAR5,VAR18;
input [1:0] VAR25;
output VAR21,VAR7,VAR16,VAR13;
output VAR24,VAR2,VAR27,VAR14;
output VAR1,... | gpl-2.0 |
azonenberg/yosys | techlibs/intel/cycloneive/cells_map.v | 4,669 | module \VAR10 (input VAR7, VAR30, output VAR16);
parameter VAR38="VAR9";
VAR4 #(.VAR15(VAR38)) VAR45 (.VAR1(VAR7), .VAR49(VAR16), .clk(VAR30), .VAR17(1'b1), .VAR11(1'b1), .VAR25(1'b1), .VAR39(1'b0), .VAR40(1'b0), .VAR37(1'b0), .VAR34(1'b0));
endmodule
module \VAR47 (input VAR7, VAR30, output VAR16);
parameter VAR38="VA... | isc |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution_OH/impl/ip/hdl/verilog/convolve_kernel_control_s_axi.v | 8,726 | module MODULE1
VAR8 = 4,
VAR40 = 32
)(
input wire VAR16,
input wire VAR1,
input wire VAR29,
input wire [VAR8-1:0] VAR17,
input wire VAR41,
output wire VAR23,
input wire [VAR40-1:0] VAR47,
input wire [VAR40/8-1:0] VAR30,
input wire VAR49,
output wire VAR53,
output wire [1:0] VAR2,
output wire VAR9,
input wire VAR43,
inp... | mit |
gajjanag/6111_Project | src/pixel_map_ident.v | 2,006 | module MODULE1(input clk,
input signed[67:0] VAR4,
input signed[68:0] VAR14,
input signed[78:0] VAR15,
input signed[67:0] VAR9,
input signed[68:0] VAR22,
input signed[78:0] VAR2,
input signed[58:0] VAR10,
input signed[59:0] VAR11,
input signed[70:0] VAR8,
input signed[78:0] VAR3,
input signed[78:0] VAR1,
input signed[7... | gpl-3.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_009.v | 1,465 | module MODULE2 (
VAR4,
VAR12
);
input [31:0] VAR4;
output [31:0]
VAR12;
wire [31:0]
VAR5,
VAR6,
VAR3,
VAR9,
VAR7,
VAR11,
VAR8,
VAR1;
assign VAR5 = VAR4;
assign VAR7 = VAR9 - VAR5;
assign VAR1 = VAR8 << 1;
assign VAR9 = VAR3 << 1;
assign VAR8 = VAR11 - VAR3;
assign VAR11 = VAR7 << 9;
assign VAR3 = VAR6 - VAR5;
assign VA... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c9b99754fd79eeaa/ip_design_xbar_0_stub.v | 3,589 | module MODULE1(VAR12, VAR19, VAR1, VAR17,
VAR7, VAR8, VAR27, VAR11, VAR20, VAR26,
VAR5, VAR30, VAR35, VAR16, VAR24, VAR34,
VAR28, VAR31, VAR13, VAR4, VAR33, VAR36,
VAR15, VAR21, VAR38, VAR40, VAR3, VAR22,
VAR6, VAR37, VAR29, VAR25, VAR32, VAR14,
VAR2, VAR23, VAR9, VAR18, VAR39, VAR10)
;
input VAR12;
input VAR19;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor3/sky130_fd_sc_lp__xnor3.functional.v | 1,300 | module MODULE1 (
VAR1,
VAR4,
VAR5,
VAR2
);
output VAR1;
input VAR4;
input VAR5;
input VAR2;
wire VAR7;
xnor VAR3 (VAR7, VAR4, VAR5, VAR2 );
buf VAR6 (VAR1 , VAR7 );
endmodule | apache-2.0 |
sirchuckalot/zet-ng | rtl/zet_core.v | 7,437 | module MODULE1 (
input clk,
input rst,
input [15:0] VAR81,
output [19:1] VAR44,
output [ 1:0] VAR10,
output VAR57,
output VAR13,
input VAR8,
output [19:0] VAR108,
input [15:0] VAR100,
output [15:0] VAR89,
output VAR21,
output VAR52,
output VAR96,
input VAR95,
output VAR70,
input VAR82,
output VAR90,
input [3:0] VAR56
)... | gpl-3.0 |
ptracton/pmodacl2 | soc/uart_pb/uart_rx6.v | 14,982 | module MODULE1 (
input VAR81,
input VAR55,
output [7:0] VAR24,
input VAR23,
output VAR68,
output VAR75,
output VAR49,
input VAR34,
input clk );
wire [3:0] VAR10;
wire [3:0] VAR28;
wire VAR61;
wire VAR30;
wire VAR22;
wire VAR59;
wire VAR100;
wire VAR102;
wire VAR76;
wire VAR77;
wire VAR60;
wire VAR37;
wire VAR51;
wire [... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_dtl_pad_r3.v | 14,687 | module MODULE1(VAR96 ,VAR11 ,VAR76 ,VAR45 ,VAR18 ,VAR101 ,
VAR88 ,VAR114 ,VAR93 ,VAR109 ,VAR61 ,VAR53 ,
VAR8 ,VAR103 ,VAR97 ,VAR14 ,VAR102 ,VAR72 ,VAR67 ,
VAR38 ,VAR104 ,VAR107 ,VAR43 ,VAR21 ,VAR70 ,VAR36 ,VAR54 ,VAR31 ,
VAR64 ,VAR94 ,VAR100 ,VAR105 ,VAR41 ,VAR10 ,
VAR59 ,ref ,VAR98 ,VAR48 ,VAR91 ,VAR81
,VAR5 ,VAR84 ,V... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeDE1SoC/Computer_System/synthesis/submodules/altera_up_video_dma_control_slave.v | 6,238 | module MODULE1 (
clk,
reset,
address,
VAR15,
read,
write,
VAR9,
VAR18,
VAR4,
VAR10,
VAR5
);
parameter VAR13 = 32'h00000000;
parameter VAR14 = 32'h00000000;
parameter VAR8 = 640; parameter VAR12 = 480;
parameter VAR2 = 16'h0809;
parameter VAR1 = 4'h7; parameter VAR3 = 2'h2; parameter VAR11 = 1'b1;
parameter VAR17 = 1'b1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbp/sky130_fd_sc_hd__sdfbbp.behavioral.pp.v | 3,364 | module MODULE1 (
VAR12 ,
VAR33 ,
VAR15 ,
VAR31 ,
VAR29 ,
VAR24 ,
VAR8 ,
VAR11,
VAR26 ,
VAR1 ,
VAR10 ,
VAR9
);
output VAR12 ;
output VAR33 ;
input VAR15 ;
input VAR31 ;
input VAR29 ;
input VAR24 ;
input VAR8 ;
input VAR11;
input VAR26 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
wire VAR38 ;
wire VAR25 ;
wire VAR36 ;
reg V... | apache-2.0 |
superibk/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/trng/rtl/verilog/wb_trng.v | 1,096 | module MODULE1 (
input VAR13,
input VAR14,
input [31:0] VAR4,
input [7:0] VAR10,
input VAR2,
input VAR3,
input VAR8,
input [2:0] VAR11,
input [1:0] VAR5,
output [7:0] VAR7,
output reg VAR12,
output VAR15,
output VAR16
);
wire valid = VAR3 & VAR8;
VAR6 VAR1 (
.clk(VAR13),
.en(valid),
.VAR9(VAR7)
);
always @(posedge VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_2.behavioral.pp.v | 1,244 | module MODULE1( VAR7, VAR6, VAR2, VAR5, VAR3 );
input VAR7, VAR6;
inout VAR5, VAR3;
output VAR2;
VAR8 VAR4(.VAR7(VAR7),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3));
VAR8 VAR1(.VAR7(VAR7),.VAR6(VAR6),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor2/sky130_fd_sc_ms__xor2.behavioral.pp.v | 1,814 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR10 ,
VAR5,
VAR1,
VAR2 ,
VAR3
);
output VAR8 ;
input VAR12 ;
input VAR10 ;
input VAR5;
input VAR1;
input VAR2 ;
input VAR3 ;
wire VAR11 ;
wire VAR7;
xor VAR13 (VAR11 , VAR10, VAR12 );
VAR9 VAR4 (VAR7, VAR11, VAR5, VAR1);
buf VAR6 (VAR8 , VAR7 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/ipcore_dir/chipscope_ila.v | 1,054 | module MODULE1(
VAR3,
VAR4,
VAR6,
VAR5,
VAR7,
VAR1,
VAR2) ;
inout [35 : 0] VAR3;
input VAR4;
input [7 : 0] VAR6;
input [31 : 0] VAR5;
input [39 : 0] VAR7;
input [3 : 0] VAR1;
input [25 : 0] VAR2;
endmodule | gpl-2.0 |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_ctrl_cappuccino.v | 55,205 | module MODULE1
parameter VAR295 = 32,
parameter VAR311 = {{(VAR295-13){1'b0}},
parameter VAR326 = "VAR323",
parameter VAR65 = "VAR323",
parameter VAR308 = "VAR323",
parameter VAR82 = "VAR124",
parameter VAR251 = 5,
parameter VAR18 = 9,
parameter VAR152 = 2,
parameter VAR176 = "VAR124",
parameter VAR38 = 6,
parameter VA... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.behavioral.v | 1,365 | module MODULE1 (
VAR4,
VAR8
);
output VAR4;
input VAR8;
supply1 VAR5;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR2 ;
wire VAR6;
buf VAR1 (VAR6, VAR8 );
buf VAR9 (VAR4 , VAR6 );
endmodule | apache-2.0 |
svofski/mahponk | src/vgascan.v | 4,413 | module MODULE1(clk, VAR1, VAR8, VAR10, VAR14, VAR6, VAR18, VAR11);
parameter VAR3 = 640; parameter VAR9 = 480;
input clk;
output VAR1;
output VAR8;
output reg[9:0] VAR10;
output reg[9:0] VAR14;
output VAR6;
output VAR18, VAR11;
reg[2:0] VAR16; reg[2:0] VAR7; reg[9:0] VAR12; reg[9:0] VAR17;
reg VAR19; reg VAR20; wire VA... | bsd-2-clause |
secworks/6502 | src/rtl/m6502_decoder.v | 5,540 | module MODULE1(
input wire [7 : 0] VAR10,
output wire [2 : 0] VAR6,
output wire [2 : 0] VAR18,
output wire [2 : 0] VAR5,
output wire [2 : 0] VAR13,
output wire [2 : 0] VAR16,
output wire VAR20,
output wire VAR27,
output wire VAR40
);
localparam VAR29 = 8'h00;
localparam VAR32 = 8'h18;
localparam VAR17 = 8'h38;
localpar... | bsd-2-clause |
azonenberg/antikernel-ipcores | math/CRC32_Ethernet.v | 9,028 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR2,
input wire[7:0] din,
output wire[31:0] VAR5);
reg[31:0] VAR3 = 0;
wire[31:0] VAR4 = ~VAR3;
assign VAR5 =
{
VAR4[24], VAR4[25], VAR4[26], VAR4[27],
VAR4[28], VAR4[29], VAR4[30], VAR4[31],
VAR4[16], VAR4[17], VAR4[18], VAR4[19],
VAR4[20], VAR4[21], VAR4[2... | bsd-3-clause |
nikhilghanathe/HLS-for-EMTF | verilog/sp_best_tracks.v | 57,932 | module MODULE1 (
VAR405,
VAR246,
VAR349,
VAR487,
VAR61,
VAR161,
VAR329,
VAR336,
VAR46,
VAR445,
VAR415,
VAR335,
VAR397,
VAR406,
VAR401,
VAR89,
VAR240,
VAR381,
VAR365,
VAR30,
VAR80,
VAR91,
VAR28,
VAR117,
VAR466,
VAR188,
VAR287,
VAR458,
VAR192,
VAR93,
VAR173,
VAR359,
VAR134,
VAR70,
VAR170,
VAR283,
VAR115,
VAR352,
VAR256,
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.behavioral.v | 1,452 | module MODULE1 (
VAR1 ,
VAR3,
VAR8
);
output VAR1 ;
input VAR3;
input VAR8 ;
supply1 VAR6;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR2 ;
wire VAR12 ;
wire VAR5;
not VAR11 (VAR12 , VAR8 );
or VAR9 (VAR5, VAR12, VAR3 );
buf VAR10 (VAR1 , VAR5 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/aemb/aeMB_ibuf.v | 5,388 | module MODULE1 (
VAR8, VAR14, VAR30, VAR22, VAR20, VAR31, VAR5, VAR21, VAR3, VAR33,
VAR25, VAR9, VAR35, VAR17, VAR18, VAR4, VAR34,
VAR27, VAR1, VAR13
);
output [15:0] VAR8;
output [4:0] VAR14, VAR30, VAR22;
output [10:0] VAR20;
output [5:0] VAR31;
output [31:0] VAR5;
output [31:0] VAR21;
output VAR3;
input VAR25;
input... | mit |
alexforencich/xfcp | lib/uart/rtl/uart_tx.v | 3,077 | module MODULE1 #
(
parameter VAR7 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR7-1:0] VAR5,
input wire VAR13,
output wire VAR3,
output wire VAR9,
output wire VAR2,
input wire [15:0] VAR10
);
reg VAR12 = 0;
reg VAR1 = 1;
reg VAR6 = 0;
reg [VAR7:0] VAR4 = 0;
reg [18:0] VAR8 = 0;
reg [3:0] VAR11 = 0;
assign VAR3... | mit |
hwstar/bdcmotor | root.v | 5,356 | module MODULE1(
input clk,
input VAR23,
input VAR19,
input VAR28,
input VAR21,
input VAR8,
input VAR12,
input VAR35,
input VAR1,
input [1:0] VAR17,
input [1:0] VAR36,
input [1:0] VAR30,
output VAR29,
output VAR9,
output VAR13,
output VAR26,
output VAR16,
output VAR25,
output VAR4,
output [1:0] VAR18,
output [3:0] VAR15... | gpl-2.0 |
jameshegarty/rigel | platform/camera2.0/vsrc/axi_master_write_stub.v | 1,763 | module MODULE1(
output VAR8,
output VAR13,
input VAR5,
output [31:0] VAR14,
output [1:0] VAR6,
output [3:0] VAR15,
output [1:0] VAR7,
output VAR3,
input VAR10,
output VAR4,
output [63:0] VAR12,
output [7:0] VAR11,
input VAR2,
output VAR9,
input [1:0] VAR1
);
assign VAR8 = 1'b0;
assign VAR13 = 1'b0;
assign VAR14 = 33'b0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3.functional.v | 1,344 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
wire VAR5;
not VAR1 (VAR5, VAR3 );
buf VAR4 (VAR2 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo.functional.pp.v | 2,043 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR14 ,
VAR7,
VAR5,
VAR15,
VAR3 ,
VAR16
);
output VAR9 ;
input VAR1 ;
input VAR14 ;
input VAR7;
input VAR5;
input VAR15;
input VAR3 ;
input VAR16 ;
wire VAR11 ;
wire VAR4 ;
wire VAR13;
nand VAR12 (VAR11 , VAR14, VAR1 );
nand VAR6 (VAR4 , VAR7, VAR11 );
VAR10 VAR8 (VAR13, VAR4, VAR5, VAR15... | apache-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkTop_HW_Side.v | 13,154 | module MODULE1(VAR39,
VAR86);
input VAR39;
input VAR86;
reg VAR89;
wire VAR119, VAR109;
reg [11 : 0] VAR17;
wire [11 : 0] VAR116;
wire VAR4;
wire [352 : 0] VAR72;
wire [255 : 0] VAR35;
wire VAR101,
VAR113,
VAR23,
VAR80;
wire [352 : 0] VAR67;
wire [255 : 0] VAR33;
wire [63 : 0] VAR47,
VAR28,
VAR65;
wire [7 : 0] VAR81,
V... | apache-2.0 |
calee0219/Course | DLAB/Lab07/ipcore_dir/sqrt.v | 24,857 | module MODULE2 (
clk, VAR34, VAR114
);
input clk;
output [4 : 0] VAR34;
input [7 : 0] VAR114;
wire VAR85;
wire VAR234;
wire VAR286;
wire VAR4;
wire VAR104;
wire VAR227;
wire VAR192;
wire VAR55;
wire VAR191;
wire VAR154;
wire VAR162;
wire VAR77;
wire VAR287;
wire VAR87;
wire VAR175;
wire VAR163;
wire VAR218;
wire VAR272... | mit |
rbarzic/arty-cm0-designstart | rtl/bytewrite_ram_32bits.v | 1,712 | module MODULE1 (clk, VAR4, addr, din, dout);
parameter VAR3 = 1024;
parameter VAR2 = 12;
parameter VAR9 = "VAR10.VAR8";
localparam VAR5 = 8;
localparam VAR7 = 4;
input clk;
input [VAR7-1:0] VAR4;
input [VAR2-1:0] addr;
input [VAR7*VAR5-1:0] din;
output reg [VAR7*VAR5-1:0] dout;
reg [VAR7*VAR5-1:0] VAR6 [VAR3-1:0];
inte... | gpl-2.0 |
mda-ut/Tempest | fpga/fpga_hw/top_level/RS232/Altera_UP_RS232_Out_Serializer.v | 5,092 | module MODULE1 (
clk,
reset,
VAR4,
VAR28,
VAR27,
VAR2
);
parameter VAR15 = 9;
parameter VAR17 = 9'd1;
parameter VAR29 = 9'd433;
parameter VAR16 = 9'd216;
parameter VAR7 = 11;
parameter VAR22 = 9;
input clk;
input reset;
input [VAR22:1] VAR4;
input VAR28;
output reg [7:0] VAR27;
output reg VAR2;
wire VAR12;
wire VAR1;
w... | mit |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_cpu_cpu_debug_slave_sysclk.v | 5,963 | module MODULE1 (
clk,
VAR26,
VAR20,
VAR23,
VAR27,
VAR10,
VAR11,
VAR7,
VAR6,
VAR12,
VAR17,
VAR14,
VAR22,
VAR13,
VAR30,
VAR21
)
;
output [ 37: 0] VAR10;
output VAR11;
output VAR7;
output VAR6;
output VAR12;
output VAR17;
output VAR14;
output VAR22;
output VAR13;
output VAR30;
output VAR21;
input clk;
input [ 1: 0] VAR26;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a32oi/sky130_fd_sc_ms__a32oi.behavioral.pp.v | 2,238 | module MODULE1 (
VAR5 ,
VAR16 ,
VAR4 ,
VAR1 ,
VAR11 ,
VAR3 ,
VAR9,
VAR10,
VAR7 ,
VAR2
);
output VAR5 ;
input VAR16 ;
input VAR4 ;
input VAR1 ;
input VAR11 ;
input VAR3 ;
input VAR9;
input VAR10;
input VAR7 ;
input VAR2 ;
wire VAR17 ;
wire VAR18 ;
wire VAR12 ;
wire VAR19;
nand VAR6 (VAR17 , VAR4, VAR16, VAR1 );
nand VAR... | apache-2.0 |
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