repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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asicguy/gplgpu | hdl/math/flt_div.v | 2,204 | module MODULE1
(
input clk,
input VAR10,
input [63:0] VAR6,
output [31:0] VAR11
);
wire [31:0] VAR5;
wire [31:0] VAR7;
VAR8 VAR3(.clk(clk), .VAR13(VAR6[31:0]), .VAR2(VAR7));
VAR9 #(32, 6) VAR1(.clk(clk), .din(VAR6[63:32]), .dout(VAR5));
VAR4 VAR12(clk, VAR10, VAR5, VAR7, VAR11);
endmodule | gpl-3.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In.v | 21,680 | module MODULE1 (
input wire VAR163, input wire VAR135, input wire VAR49, input wire [7:0] VAR72, input wire VAR56, input wire VAR53, input wire VAR97, output wire VAR173, output wire VAR18, output wire [31:0] VAR6, input wire VAR160, output wire VAR111, output wire [7:0] VAR136 );
wire VAR167; wire [7:0] VAR114; wire V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_4.functional.pp.v | 1,244 | module MODULE1( VAR3, VAR9, VAR8, VAR4, VAR1, VAR5 );
input VAR4, VAR3, VAR8;
inout VAR1, VAR5;
output VAR9;
wire VAR2;
not VAR10( VAR2, VAR4 );
wire VAR11;
not VAR13( VAR11, VAR3 );
wire VAR12;
not VAR6( VAR12, VAR8 );
or VAR7( VAR9, VAR2, VAR11, VAR12 );
endmodule | apache-2.0 |
18545/FPGA | FPGA.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_stub.v | 1,428 | module MODULE1(VAR1, VAR2, VAR4, VAR6, VAR5, VAR3, VAR7)
;
input VAR1;
input [0:0]VAR2;
input [18:0]VAR4;
input [11:0]VAR6;
input VAR5;
input [18:0]VAR3;
output [11:0]VAR7;
endmodule | mit |
jameshegarty/rigel | platform/verilator/RAMB16_S2_S2.v | 3,525 | module MODULE1(
input VAR36,
input VAR31,
input VAR63,
input VAR37,
input [12:0] VAR22,
input [1:0] VAR79,
output [1:0] VAR15,
input VAR2,
input VAR74,
input VAR11,
input VAR83,
input [12:0] VAR59,
input [1:0] VAR80,
output [1:0] VAR67);
parameter VAR39 = "VAR42";
parameter VAR75 = "VAR42";
parameter VAR16=256'd0;
para... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4/sky130_fd_sc_ms__nand4_2.v | 2,253 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR4 ,
VAR5 ,
VAR6 ,
VAR9,
VAR2,
VAR1 ,
VAR3
);
output VAR8 ;
input VAR7 ;
input VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR9;
input VAR2;
input VAR1 ;
input VAR3 ;
VAR11 VAR10 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(V... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_usr_top.v | 6,908 | module MODULE1 #
(
parameter VAR14 = 2,
parameter VAR6 = 0,
parameter VAR25 = 10,
parameter VAR9 = 72,
parameter VAR44 = 8,
parameter VAR28 = 144,
parameter VAR42 = 0,
parameter VAR13 = 9,
parameter VAR18 = 14
)
(
input VAR43,
input VAR36,
input VAR31,
input [VAR9-1:0] VAR7,
input [VAR9-1:0] VAR10,
input [VAR13-1:0] VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/edfxbp/sky130_fd_sc_lp__edfxbp.symbol.v | 1,448 | module MODULE1 (
input VAR2 ,
output VAR9 ,
output VAR7,
input VAR6 ,
input VAR5
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2.functional.pp.v | 1,783 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR9 ,
VAR5,
VAR8,
VAR2 ,
VAR1
);
output VAR11 ;
input VAR3 ;
input VAR9 ;
input VAR5;
input VAR8;
input VAR2 ;
input VAR1 ;
wire VAR6 ;
wire VAR12;
or VAR10 (VAR6 , VAR9, VAR3 );
VAR13 VAR4 (VAR12, VAR6, VAR5, VAR8);
buf VAR7 (VAR11 , VAR12 );
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/yf32/mlite_cpu.v | 14,275 | module MODULE1 (clk, VAR17, VAR109, VAR75, VAR25, VAR100,
VAR91, VAR108, VAR49);
input clk;
input VAR17;
input VAR109;
input [31:0] VAR100;
input VAR49;
output [31:0] VAR75;
output [31:0] VAR25;
output [ 3:0] VAR91;
output VAR108;
wire [31:0] VAR75;
wire [31:0] VAR25;
wire [ 3:0] VAR91;
wire VAR108;
wire [31:0] VAR39;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b.symbol.v | 1,307 | module MODULE1 (
input VAR3,
input VAR1 ,
input VAR6 ,
output VAR7
);
supply1 VAR2;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/freedm_bus/fb_rxstatem.v | 4,379 | module MODULE1 (VAR9, VAR6, VAR22, VAR18, VAR23, VAR11, VAR10, VAR1,VAR24,
VAR15, VAR14, VAR12, VAR3, VAR13, VAR28,
VAR4, VAR5, VAR2, VAR17, VAR20
);
input VAR9;
input VAR6;
input VAR22;
input VAR18;
input VAR23;
input VAR11;
input VAR10;
input VAR1;
input VAR24;
input VAR15;
input VAR14;
input VAR12;
output VAR3;
outp... | gpl-3.0 |
DeadWitcher/amber-de0-nano | hw/vlog/ethmac/eth_txstatem.v | 10,122 | module MODULE1 (VAR20, VAR1, VAR43, VAR24, VAR40, VAR41, VAR22,
VAR45, VAR17, VAR29, VAR13, VAR11, VAR27, VAR21,
VAR31, VAR15, VAR10, VAR35, VAR49, VAR33, VAR16,
VAR14, VAR25, VAR5, VAR4, VAR28, VAR18,
VAR44, VAR2, VAR3, VAR36, VAR46, VAR9,
VAR39, VAR37, VAR47, VAR6, VAR8, VAR30,
VAR42, VAR48, VAR23, VAR34, VAR26, VAR1... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi.behavioral.v | 2,307 | module MODULE1 (
VAR15 ,
VAR11 ,
VAR4 ,
VAR9 ,
VAR17 ,
VAR12 ,
VAR14 ,
VAR8,
VAR6
);
output VAR15 ;
input VAR11 ;
input VAR4 ;
input VAR9 ;
input VAR17 ;
input VAR12 ;
input VAR14 ;
input VAR8;
input VAR6;
wire VAR17 VAR2 ;
wire VAR17 VAR5 ;
wire VAR17 VAR19 ;
wire VAR20 ;
wire VAR3;
nand VAR21 (VAR2 , VAR4, VAR11 );
n... | apache-2.0 |
olajep/oh | src/emesh/hdl/emesh_if.v | 2,960 | module MODULE1 (
VAR5, VAR10, VAR11, VAR13,
VAR2, VAR26, VAR16,
VAR1, VAR9, VAR22,
VAR20, VAR7,
VAR17, VAR6, VAR18, VAR8,
VAR23, VAR15, VAR14, VAR24,
VAR21, VAR19, VAR25, VAR3
);
parameter VAR12 = 32;
parameter VAR4 = 2*VAR12+40;
input VAR17;
input [VAR4-1:0] VAR6;
output VAR5;
output VAR10;
output [VAR4-1:0] VAR11;
in... | mit |
Elphel/x393_sata | host/gtx_10x8dec.v | 5,539 | module MODULE1(
input wire rst,
input wire clk,
input wire [19:0] VAR31,
output wire [15:0] VAR6,
output wire [1:0] VAR7,
output wire [1:0] VAR19,
output wire [1:0] VAR39
);
wire [9:0] VAR18;
wire [9:0] VAR28;
assign VAR18 = VAR31[9:0];
assign VAR28 = VAR31[19:10];
wire [15:0] VAR44;
wire [15:0] VAR38;
wire [10:0] VAR2... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/src/memory/hdl/fifo_sync.v | 4,036 | module MODULE1
parameter VAR27 = 5,
parameter VAR31 = 16
)
(
input clk,
input reset,
input [VAR31-1:0] VAR10,
input VAR24,
input VAR20,
output wire [VAR31-1:0] VAR21,
output reg VAR32,
output reg VAR2
);
reg [VAR27-1:0] VAR28;
reg [VAR27-1:0] VAR33;
reg [VAR27-1:0] VAR8;
always @ ( posedge clk ) begin
if( reset )
begin... | gpl-3.0 |
Koheron/zynq-sdk | fpga/cores/axi_ctl_register_v1_0/axi_ctl_register.v | 4,441 | module MODULE1 #
(
parameter integer VAR49 = 1024,
parameter integer VAR13 = 32,
parameter integer VAR22 = 16
)
(
input wire VAR7,
input wire VAR21,
output wire [VAR49-1:0] VAR31,
input wire [VAR22-1:0] VAR3, input wire VAR45, output wire VAR17, input wire [VAR13-1:0] VAR47, input wire [VAR13/8-1:0] VAR6, input wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.pp.symbol.v | 3,088 | module MODULE1 (
input VAR6 ,
input [1:0] VAR2 ,
output [1:0] VAR12 ,
input [1:0] VAR9 ,
output [1:0] VAR30 ,
input [1:0] VAR22 ,
inout [1:0] VAR11 ,
inout [1:0] VAR33 ,
inout [1:0] VAR37 ,
inout [1:0] VAR4 ,
inout VAR21 ,
inout VAR19 ,
input [2:0] VAR8 ,
input [2:0] VAR32 ,
input VAR40 ,
input VAR16 ,
input [1:0] VAR3... | apache-2.0 |
shangdawei/proxmark3-lcd | fpga/hi_read_rx_xcorr.v | 5,407 | module MODULE1(
VAR6, VAR3, VAR28,
VAR21, VAR30, VAR27, VAR12, VAR26, VAR33,
VAR31, VAR23,
VAR2, VAR5, VAR20, VAR13,
VAR9, VAR22,
VAR10,
VAR8, VAR25, VAR29
);
input VAR6, VAR3, VAR28;
output VAR21, VAR30, VAR27, VAR12, VAR26, VAR33;
input [7:0] VAR31;
output VAR23;
input VAR20;
output VAR2, VAR5, VAR13;
input VAR9, VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv.blackbox.v | 1,238 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR6;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrtp/sky130_fd_sc_hvl__dfrtp.symbol.v | 1,399 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR6,
input VAR1
);
supply1 VAR5;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
peteasa/parallella-fpga | ohLocal/common/dv/dv_top_local.v | 3,390 | module MODULE1();
parameter VAR24 = 100;
parameter VAR29 = 1;
parameter VAR5 = 12;
parameter VAR1 = 32;
parameter VAR12 = 2*VAR1+40;
integer VAR32;
wire [VAR5-1:0] VAR35;
wire [VAR29*VAR29-1:0] VAR2;
wire VAR18;
wire VAR25;
wire VAR9;
wire [VAR29-1:0] VAR21;
wire [VAR29-1:0] VAR13;
wire [VAR29*VAR12-1:0] VAR10;
wire VA... | lgpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_mems.v | 18,170 | module MODULE1(
input VAR12,
output VAR38,
input [VAR104-1:0] VAR137,
input VAR111,
input [VAR320-1:0] VAR255,
input [VAR320/8-1:0] VAR358,
output VAR2,
input VAR298,
output VAR242,
output [VAR320-1:0] VAR238,
output VAR46,
input VAR142,
output [VAR104-1:0] VAR257,
output VAR132,
output [VAR320-1:0] VAR215,
output [VAR... | apache-2.0 |
mfkiwl/parallella-platform | hdl/axi_master.v | 11,272 | module MODULE1 (
VAR43, VAR25, VAR31, VAR12, VAR59, VAR10, VAR6, VAR21,
VAR41, VAR8, VAR50, VAR48, VAR26, VAR62, VAR35, VAR52, VAR5,
VAR27, VAR44, VAR57, VAR56, VAR34, VAR32, VAR16, VAR51,
VAR36, VAR1, VAR54,
VAR19, VAR37, VAR14,
VAR7, VAR20, VAR3, VAR28, VAR45,
VAR9, VAR29, reset, VAR39, VAR55, VAR11, VAR38, VAR13, VA... | gpl-3.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/altera_jtag_dc_streaming.v | 8,642 | module MODULE1 (
clk,
VAR48,
VAR15,
VAR25,
VAR9
);
input clk;
input VAR48;
input VAR15;
input VAR25;
output VAR9;
parameter VAR47 = 3;
reg VAR9;
wire VAR70;
reg VAR60;
VAR27 #(.VAR51(VAR47)) VAR64 (
.clk(clk),
.VAR48(VAR48),
.din(VAR15),
.dout(VAR70)
);
always @ (posedge clk or negedge VAR48)
if (~VAR48)
VAR60 <= 1'b0;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/tap/sky130_fd_sc_hdll__tap.behavioral.pp.v | 1,197 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/new/funciones_cursor.v | 2,174 | module MODULE1(
input [2:0] VAR1,
input [1:0] VAR4,
output reg [7:0] VAR3,
output reg VAR2
);
always @(*) begin
case ({VAR1,VAR4})
{3'd0 ,2'd0}: {VAR3,VAR2}={8'b0,1'b1};
{3'd1 ,2'd0}: {VAR3,VAR2}={8'b1,1'b1};
{3'd2 ,2'd0}: {VAR3,VAR2}={8'd2,1'b1};
{3'd3 ,2'd0}: {VAR3,VAR2}={8'd3,1'b1};
{3'd4 ,2'd0}: {VAR3,VAR2}={8'd16,... | apache-2.0 |
rkrajnc/minimig-de1 | lib/altera/cycloneive_atoms.v | 253,042 | module MODULE1(
primitive VAR7 (VAR3, VAR11, VAR16, VAR1, VAR2, VAR19, VAR5);
input VAR16;
input VAR2;
input VAR19;
input VAR1;
input VAR11;
input VAR5;
output VAR3; reg VAR3;
VAR17 VAR3 = 1'b0;
VAR18
(??) ? ? 1 1 ? : ? : -; VAR13 ? ? 1 1 ? : ? : -; 1 1 (01) 1 1 ? : ? : 1; 1 1 (01) 1 VAR13 ? : ? : 1;
1 1 ? 1 VAR13 ? : ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.blackbox.v | 1,407 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR6,
VAR8 ,
VAR9
);
output VAR1 ;
output VAR7 ;
input VAR6;
input VAR8 ;
input VAR9 ;
supply1 VAR5;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_wb_biu.v | 12,320 | module MODULE1(
clk, rst, VAR6,
VAR13, VAR21, VAR16, VAR39, VAR19, VAR30,
VAR44, VAR5, VAR15, VAR23, VAR9, VAR40,
VAR31,
VAR34, VAR42,
VAR43, VAR41, VAR14, VAR29, VAR35, VAR20, VAR36,
VAR18, VAR27, VAR38
);
parameter VAR17 = VAR8;
parameter VAR22 = VAR8;
input clk; input rst; input [1:0] VAR6;
input VAR13; input VAR21;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/conb/sky130_fd_sc_lp__conb_0.v | 2,042 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR1,
VAR7,
VAR2 ,
VAR5
);
output VAR3 ;
output VAR8 ;
input VAR1;
input VAR7;
input VAR2 ;
input VAR5 ;
VAR6 VAR4 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR3,
VAR8
);
output VAR3;
output VAR8;
supply1 VAR1;
supply0 VAR... | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/fsusb.v | 8,236 | module MODULE2
(input VAR87, input VAR120, input en, inout VAR14,
inout VAR55,
input VAR133, output VAR62,
output [7:0] VAR90,
output VAR95,
output VAR81);
localparam VAR57 = 4'd0;
localparam VAR29 = 4'd1;
localparam VAR96 = 4'd2;
localparam VAR37 = 4'd3;
localparam VAR135 = 4'd4;
localparam VAR65 = 4'd5;
localparam VA... | apache-2.0 |
lvd2/zxevo | fpga/baseconf/trunk/video/video_palframe.v | 4,042 | module MODULE1(
input wire clk,
input wire VAR14,
input wire VAR30,
input wire VAR27,
input wire VAR21,
input wire VAR37,
input wire VAR28,
input wire [ 3:0] VAR25,
input wire [ 3:0] VAR36,
input wire VAR33,
input wire VAR19,
input wire [ 1:0] VAR44,
input wire [ 2:0] VAR16,
input wire [ 2:0] VAR39,
input wire VAR4,
in... | gpl-3.0 |
esonghori/TinyGarbled | circuit_synthesis/knns_td/first_nns_seq_td.v | 1,460 | module MODULE1
(
parameter VAR26 = 15
)
(
clk,
rst,
VAR14,
VAR21,
VAR25
);
function integer VAR8;
input [31:0] VAR19;
reg [31:0] VAR16;
begin
VAR16 = VAR19;
for (VAR8=0; VAR16>0; VAR8=VAR8+1)
VAR16 = VAR16>>1;
end
endfunction
localparam VAR12 = VAR8(VAR26);
input clk;
input rst;
input [2*VAR26-1:0] VAR14, VAR21;
output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.functional.pp.v | 2,056 | module MODULE1 (
VAR8 ,
VAR3,
VAR4 ,
VAR6 ,
VAR11 ,
VAR2 ,
VAR16 ,
VAR9
);
output VAR8 ;
input VAR3;
input VAR4 ;
input VAR6 ;
input VAR11 ;
input VAR2 ;
input VAR16 ;
input VAR9 ;
wire VAR14 ;
wire VAR13;
wire VAR1 ;
not VAR5 (VAR14 , VAR3 );
not VAR10 (VAR13, VAR6 );
VAR12 VAR17 VAR15 (VAR1 , VAR4, VAR13, VAR14, , VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_2.behavioral.pp.v | 1,167 | module MODULE1( VAR5, VAR2, VAR7, VAR1 );
input VAR5;
inout VAR7, VAR1;
output VAR2;
VAR6 VAR3(.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1));
VAR6 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a_4.v | 2,339 | module MODULE2 (
VAR4 ,
VAR1 ,
VAR6 ,
VAR11 ,
VAR2 ,
VAR7,
VAR9,
VAR8 ,
VAR10
);
output VAR4 ;
input VAR1 ;
input VAR6 ;
input VAR11 ;
input VAR2 ;
input VAR7;
input VAR9;
input VAR8 ;
input VAR10 ;
VAR5 VAR3 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VA... | apache-2.0 |
cpulabs/mist1032sa | src/core/scheduler2/reservation_alu3_entry.v | 9,349 | module MODULE1(
input wire VAR1,
input wire VAR13,
input wire VAR37,
input wire VAR28,
input wire [4:0] VAR7,
input wire VAR57,
input wire VAR66,
input wire VAR22,
input wire VAR47,
input wire [31:0] VAR15,
input wire VAR55,
input wire VAR63,
input wire [31:0] VAR24,
input wire VAR23,
input wire [5:0] VAR10,
input wire... | bsd-2-clause |
jotego/jt51 | hdl/deprecated/jt51_sh2.v | 1,431 | module MODULE2 #(parameter VAR1=5, VAR4=32 )
(
input clk,
input en,
input VAR2,
input [VAR1-1:0] din,
output [VAR1-1:0] VAR8
);
genvar VAR5;
generate
for( VAR5=0; VAR5<VAR1; VAR5=VAR5+1) begin: VAR9
MODULE1 #(.VAR4(VAR4)) VAR6(
.clk ( clk ),
.en ( en ),
.VAR2 ( VAR2 ),
.din ( din[VAR5] ),
.VAR8 ( VAR8[VAR5])
);
end
end... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfrtp/sky130_fd_sc_hvl__sdfrtp.pp.symbol.v | 1,521 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR6,
input VAR4 ,
input VAR9 ,
input VAR3 ,
input VAR8 ,
input VAR10 ,
input VAR7 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4b/sky130_fd_sc_ls__nand4b.pp.symbol.v | 1,330 | module MODULE1 (
input VAR2 ,
input VAR9 ,
input VAR4 ,
input VAR5 ,
output VAR6 ,
input VAR8 ,
input VAR1,
input VAR7,
input VAR3
);
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/spi_master_kl/spi_master_kl.v | 6,585 | module MODULE1(
clk,VAR16,
VAR15,VAR11,VAR5,
VAR13,VAR8,VAR9,VAR25,VAR21,
VAR17
);
input clk;
input VAR16;
input VAR15;
output VAR11;
output VAR5;
output VAR17;
input VAR13;
output VAR9;
output VAR21;
input VAR8;
input VAR25;
reg[7:0] VAR18;
reg[7:0] VAR12;
reg[7:0] VAR7;
reg[4:0] VAR4;
reg VAR14;
reg VAR19;
reg VAR10;... | mit |
jacgoudsmit/P8X32A_Emulation | P8X32A_Nexys4/src/cog_vid.v | 4,939 | module MODULE1
(
input VAR18,
input VAR8,
input VAR32,
input VAR4,
input VAR16,
input [31:0] VAR3,
input [31:0] VAR15,
input [31:0] VAR24,
input [7:0] VAR33,
input VAR9,
output ack,
output [31:0] VAR21
);
reg [31:0] VAR6;
reg [31:0] VAR13;
always @(posedge VAR18 or negedge VAR32)
if (!VAR32)
VAR6 <= 32'b0;
else if (VAR... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/dbg_comm2.v | 11,924 | module MODULE1(VAR1, VAR2, VAR4, VAR5, VAR10);
parameter VAR9 = 1;
parameter VAR12 = 50;
output VAR1;
output VAR2;
output VAR4;
output VAR5;
input VAR10;
integer VAR14, VAR11;
reg [87:0] memory[0:0];
reg [87:0] VAR7;
reg VAR13;
reg VAR8;
reg VAR6;
reg VAR18;
reg VAR2;
reg VAR4;
reg VAR5;
reg VAR1;
wire VAR10;
reg VAR16... | gpl-3.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/wasca.v | 70,625 | module MODULE1 (
input wire [24:0] VAR77, input wire VAR229, inout wire [15:0] VAR44, input wire [2:0] VAR247, output wire VAR207, output wire VAR374, output wire VAR40, input wire [1:0] VAR76, input wire VAR202, output wire [12:0] VAR99, output wire [1:0] VAR356, output wire VAR58, output wire VAR390, output wire VAR2... | gpl-2.0 |
Daniel-Norman/FDPaint | joy_control.v | 1,073 | module MODULE1(
input VAR6,
input VAR5,
input VAR9,
input [7:0] VAR4,
output VAR1,
output reg VAR2,
output reg [39:0] VAR8
);
reg VAR1 = 1;
reg [2:0] VAR7 = 0;
reg [2:0] VAR3 = 0;
reg [39:0] VAR10 = 0;
always @(negedge VAR6)
begin
case(VAR7)
0 : begin
VAR1 <= 1;
VAR2 <= 0;
VAR10 <= 0;
VAR3 <= 0;
VAR7 <= VAR5 ? 1 : 0;
e... | mit |
alexforencich/verilog-ethernet | example/S10DX_DK/fpga_10g/rtl/axis2avst.v | 3,137 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR12 = (VAR4/8),
parameter VAR22 = (VAR4>8),
parameter VAR16 = VAR1(VAR12),
parameter VAR6 = 0
)
(
input wire clk,
input wire rst,
input wire [VAR4-1:0] VAR3,
input wire [VAR12-1:0] VAR25,
input wire VAR24,
output wire VAR23,
input wire VAR2,
input wire VAR19,
input wire... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.functional.v | 1,218 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR2;
notif0 VAR3 (VAR1 , VAR4, VAR2 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.functional.pp.v | 1,235 | module MODULE1( VAR2, VAR3, VAR11, VAR12, VAR9, VAR4 );
input VAR12, VAR11, VAR3;
inout VAR9, VAR4;
output VAR2;
wire VAR10;
not VAR6( VAR10, VAR12 );
wire VAR1;
not VAR7( VAR1, VAR11 );
wire VAR5;
not VAR13( VAR5, VAR3 );
and VAR8( VAR2, VAR10, VAR1, VAR5 );
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/e_transmit/hdl/e_transmit.v | 9,461 | module MODULE1(
VAR41, VAR57, VAR51,
VAR25, VAR63, VAR50,
VAR42, VAR49, VAR44, VAR1, VAR52, VAR32,
reset, VAR26, VAR42, VAR9, VAR28, VAR36,
VAR5, VAR56, VAR66, VAR60,
VAR18, VAR24, VAR43,
VAR10, VAR27, VAR7,
VAR12, VAR55, VAR14, VAR13
);
input reset;
input VAR26; input VAR42; input VAR9; input VAR28; input VAR36;
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.symbol.v | 1,248 | module MODULE1 (
input VAR4,
input VAR3,
input VAR2,
output VAR5
);
supply1 VAR6;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4b/sky130_fd_sc_lp__and4b.blackbox.v | 1,320 | module MODULE1 (
VAR3 ,
VAR9,
VAR6 ,
VAR1 ,
VAR7
);
output VAR3 ;
input VAR9;
input VAR6 ;
input VAR1 ;
input VAR7 ;
supply1 VAR2;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_top.v | 8,016 | module MODULE1 (
clk ,
VAR15 ,
VAR34 ,
VAR30 ,
VAR41 ,
VAR55 ,
VAR45 ,
VAR3 ,
VAR11 ,
VAR50 ,
VAR76 ,
VAR103 ,
VAR5 ,
VAR38 ,
VAR14 ,
VAR31 ,
VAR95 ,
VAR88 ,
VAR36 ,
VAR52 ,
VAR89 ,
VAR33 ,
VAR9 ,
VAR62 ,
VAR68 ,
VAR51 ,
VAR26 ,
VAR74 ,
VAR100 ,
VAR35 ,
VAR85 ,
VAR40 ,
VAR12 ,
VAR98 ,
VAR7 ,
VAR37 ,
VAR101 ,
VAR94 ,
VA... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/vrt/vita_rx_engine_glue.v | 4,214 | module MODULE1
parameter VAR6 = 0,
parameter VAR23 = 10,
parameter VAR4 = 0
)
(
input VAR9, input reset, input VAR12,
input VAR11, input [7:0] VAR1, input [31:0] VAR5,
input VAR25, input [7:0] VAR14, input [31:0] VAR20,
output VAR17,
output VAR26,
input VAR22,
output VAR3,
output VAR15,
output [VAR23-1:0] VAR2,
input [... | gpl-2.0 |
CospanDesign/vivado-ip-cores | ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/axi_pmod_tft.v | 18,501 | module MODULE1 #(
parameter VAR109 = 7,
parameter VAR5 = 32,
parameter VAR171 = (VAR5 / 8),
parameter VAR70 = 24,
parameter VAR75 = 1,
parameter VAR42 = 1,
parameter VAR123 = 480,
parameter VAR139 = 272,
parameter VAR40 = 10
)(
input clk,
input rst,
output VAR161,
output VAR50,
output VAR157,
output VAR114,
output VAR4... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha_4.v | 2,184 | module MODULE2 (
VAR9,
VAR7 ,
VAR8 ,
VAR5 ,
VAR2,
VAR1,
VAR4 ,
VAR3
);
output VAR9;
output VAR7 ;
input VAR8 ;
input VAR5 ;
input VAR2;
input VAR1;
input VAR4 ;
input VAR3 ;
VAR10 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/acl_ic_slave_wrp.v | 4,446 | module MODULE1 #(
parameter integer VAR7 = 32, parameter integer VAR24 = 4, parameter integer VAR18 = 32, parameter integer VAR1 = VAR7 / 8, parameter integer VAR2 = 1,
parameter integer VAR9 = 1, parameter integer VAR10 = 0, parameter integer VAR22 = 1 )
(
input VAR25,
input VAR14,
VAR6 VAR17,
input logic VAR26,
VAR15... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_4.behavioral.v | 2,557 | module MODULE1( VAR3, VAR2, VAR4, VAR1 );
input VAR2, VAR3, VAR4;
output VAR1;
VAR7 VAR5(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tap/sky130_fd_sc_hs__tap.pp.blackbox.v | 1,164 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
tommythorn/yari | shared/rtl/target/ML401/top.v | 4,346 | module MODULE1
(input VAR57
,input VAR31
,input VAR10
,output VAR33
);
parameter VAR58 = 100000000; parameter VAR30 = 9600;
parameter VAR34 = 2'd1;
parameter VAR46 = 2'd2;
parameter VAR9 = 2'd3;
wire VAR1;
assign VAR1 = VAR57;
wire reset = VAR31;
wire [ 7:0] VAR25;
wire VAR41;
wire VAR56;
wire [ 7:0] VAR8;
wire VAR18;
... | gpl-2.0 |
amartens/ratel | hdl/add.v | 1,431 | module MODULE1(VAR8, VAR18, VAR17);
parameter integer VAR3 = 9;
parameter integer VAR13 = 6;
parameter integer VAR20 = 9;
parameter integer VAR11 = 8;
localparam integer VAR14 = VAR3-VAR13;
localparam integer VAR4 = VAR20-VAR11;
localparam integer VAR15 = (VAR14 > VAR4) ? VAR14: VAR4;
localparam integer VAR16 = (VAR13 ... | gpl-3.0 |
shaform/ArkanoidOnVerilog | t_block_memory.v | 1,152 | module MODULE1;
reg VAR7;
reg reset;
reg enable;
reg [4:0] VAR11;
reg [4:0] VAR6;
reg [4:0] VAR5;
reg [4:0] VAR10;
reg [1:0] VAR1;
reg [1:0] VAR12;
wire [2:0] VAR2;
wire [2:0] VAR9;
wire VAR8;
VAR4 VAR3 (
.VAR7(VAR7),
.reset(reset),
.enable(enable),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.... | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/eth_phy_10g_rx_ber_mon.v | 3,258 | module MODULE1 #
(
parameter VAR1 = 2,
parameter VAR2 = 125000/6.4
)
(
input wire clk,
input wire rst,
input wire [VAR1-1:0] VAR4,
output wire VAR3
); | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cmn/fifo/fifo.v | 4,209 | module MODULE1
parameter VAR2 = 8,
parameter VAR16 = 3
)
(
input wire clk, input wire reset, input wire VAR9, input wire VAR15, input wire [VAR2-1:0] VAR19, output wire [VAR2-1:0] VAR3, output wire VAR13, output wire VAR12 );
reg [VAR16-1:0] VAR7;
wire [VAR16-1:0] VAR4;
reg [VAR16-1:0] VAR18;
wire [VAR16-1:0] VAR21;
re... | mit |
Des333/soc-fb | fpga/regfile_with_be.v | 2,485 | module MODULE1 #(
parameter VAR14 = 32,
parameter VAR18 = 32,
parameter VAR6 = 7,
parameter VAR12 = 8,
parameter VAR3 = 1
) (
input VAR21,
input VAR19,
input [VAR12-1:0] VAR13,
input VAR24,
input [1:0] VAR10,
input [VAR6-1:0] VAR1,
input [VAR12-1:0] VAR15 [VAR14-1:0],
output logic [VAR12-1:0] VAR5,
output logic [VAR12-... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/match/bv_9_12/match.v | 6,387 | module MODULE1(
clk,
reset,
VAR14,
VAR23,
VAR50,
VAR49,
VAR13,
VAR2,
VAR8,
VAR10,
VAR16,
VAR17,
VAR31,
VAR34
);
input clk;
input reset;
input VAR14;
input VAR23;
input [31:0] VAR50;
input VAR49;
output VAR13;
output [31:0] VAR2;
input VAR8;
input [107:0] VAR10;
output VAR16;
output[15:0] VAR17;
output VAR31;
output[351... | apache-2.0 |
ptracton/vscale_soc | rtl/verilog-arbiter/src/arbiter.v | 2,186 | module MODULE1
VAR2 = 6)
(input clk,
input rst,
input [VAR2-1:0] request,
output reg [VAR2-1:0] VAR3,
output reg VAR4
);
localparam VAR1 = 2*VAR2; | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_reconfig_3cgx.v | 21,690 | module MODULE1
(
address,
VAR26,
VAR2,
VAR24,
VAR30,
VAR28,
VAR4,
VAR45,
VAR7,
VAR42,
VAR19,
reset,
VAR32,
VAR47) ;
input [15:0] address;
output VAR26;
input [15:0] VAR2;
output [15:0] VAR24;
input VAR30;
output VAR28;
output VAR4;
output VAR45;
input VAR7;
input [8:0] VAR42;
input VAR19;
input reset;
input VAR32;
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_2.v | 1,995 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1,
VAR6,
VAR3 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR3 ;
input VAR8 ;
VAR5 VAR7 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbn/sky130_fd_sc_hs__dfbbn.blackbox.v | 1,415 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR7 ,
VAR8 ,
VAR1 ,
VAR6
);
output VAR2 ;
output VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR6;
supply1 VAR5;
supply0 VAR4;
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/esaxi.v | 20,615 | module MODULE1 (
VAR88, VAR116, VAR25, VAR31,
VAR38, VAR27, VAR59, VAR34, VAR49,
VAR51, VAR16, VAR21, VAR104,
VAR5, VAR14, VAR66, VAR99, VAR28,
VAR75, VAR69, VAR70, VAR58, VAR44, VAR50,
VAR115, VAR105, VAR39, VAR79, VAR45,
VAR11, VAR80, VAR114, VAR62, VAR46,
VAR53, VAR32, VAR4, VAR107, VAR94,
VAR108, VAR100, VAR90, VAR... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_usr_addr_fifo.v | 4,679 | module MODULE1 #
(
parameter VAR25 = 2,
parameter VAR20 = 10,
parameter VAR3 = 0,
parameter VAR30 = 14
)
(
input VAR4,
input VAR37,
input [2:0] VAR43,
input [30:0] VAR31,
input VAR2,
input VAR13,
output [2:0] VAR33,
output [30:0] VAR5,
output VAR23,
output VAR21
);
wire [35:0] VAR38;
reg VAR17;
always @(posedge VAR4)
V... | lgpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/verilog/FIFO_image_filter_img_0_data_stream_0_V.v | 3,017 | module MODULE1 (
clk,
VAR13,
VAR23,
VAR22,
VAR19);
parameter VAR3 = 32'd8;
parameter VAR5 = 32'd1;
parameter VAR26 = 32'd2;
input clk;
input [VAR3-1:0] VAR13;
input VAR23;
input [VAR5-1:0] VAR22;
output [VAR3-1:0] VAR19;
reg[VAR3-1:0] VAR7 [0:VAR26-1];
integer VAR25;
always @ (posedge clk)
begin
if (VAR23)
begin
for (V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.behavioral.pp.v | 1,568 | module MODULE1( VAR5, VAR2, VAR9, VAR1, VAR3, VAR6 );
input VAR2, VAR9;
inout VAR3, VAR6;
output VAR5, VAR1;
VAR7 VAR8(.VAR5(VAR5),.VAR2(VAR2),.VAR9(VAR9),.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6));
VAR7 VAR4(.VAR5(VAR5),.VAR2(VAR2),.VAR9(VAR9),.VAR1(VAR1),.VAR3(VAR3),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.functional.pp.v | 1,810 | module MODULE1 (
VAR2 ,
VAR10 ,
VAR6 ,
VAR11 ,
VAR12,
VAR4,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR10 ;
input VAR6 ;
input VAR11 ;
input VAR12;
input VAR4;
input VAR5 ;
input VAR8 ;
wire VAR7 ;
wire VAR1;
or VAR13 (VAR7 , VAR6, VAR10, VAR11 );
VAR3 VAR9 (VAR1, VAR7, VAR12, VAR4);
buf VAR14 (VAR2 , VAR1 );
endmodule | apache-2.0 |
kyzhai/NUNY | src/hardware/eight_new2_bb.v | 5,028 | module MODULE1 (
address,
VAR2,
VAR1);
input [9:0] address;
input VAR2;
output [11:0] VAR1;
tri1 VAR2;
endmodule | gpl-2.0 |
iAklis/teoca | EXPR3_DIGITAL/MAIN.v | 5,201 | module MODULE2(VAR12, VAR15, VAR11, VAR8, MODULE3, VAR1, VAR17, VAR14
);
input MODULE3;
input wire [2:0] VAR12;
input wire [2:0] VAR15;
input VAR11;
output reg [7:0] VAR1;
output wire [3:0] VAR17;
output reg [1:0] VAR8;
input wire VAR14;
wire [31:0] VAR2;
wire VAR13, VAR16;
wire [63:0] VAR6;
reg[31:0] VAR9,VAR10;
alway... | mit |
asicguy/gplgpu | hdl/bios_internal/bios_rom.v | 6,368 | module MODULE1 (
address,
VAR15,
VAR41);
input [13:0] address;
input VAR15;
output [15:0] VAR41;
tri1 VAR15;
wire [15:0] VAR4;
wire [15:0] VAR41 = VAR4[15:0];
VAR23 VAR52 (
.VAR2 (address),
.VAR50 (VAR15),
.VAR36 (VAR4),
.VAR51 (1'b0),
.VAR3 (1'b0),
.VAR8 (1'b1),
.VAR25 (1'b0),
.VAR19 (1'b0),
.VAR22 (1'b1),
.VAR16 (1'b... | gpl-3.0 |
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_new_sdram_controller_0.v | 24,225 | module MODULE1 (
clk,
rd,
VAR45,
wr,
VAR21,
VAR58,
VAR65,
VAR63,
VAR49,
VAR42
)
;
output VAR58;
output VAR65;
output VAR63;
output VAR49;
output [ 42: 0] VAR42;
input clk;
input rd;
input VAR45;
input wr;
input [ 42: 0] VAR21;
wire VAR58;
wire VAR65;
wire VAR63;
reg [ 1: 0] VAR33;
reg [ 42: 0] VAR17;
reg [ 42: 0] VAR69... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/e7bb0a4eba6cd7b1/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v | 3,875 | module MODULE1(VAR23, VAR4, VAR17,
VAR14, VAR2, VAR38, VAR37, VAR1, VAR25,
VAR47, VAR6, VAR43, VAR19, VAR32, VAR45,
VAR40, VAR18, VAR46, VAR27, VAR8, VAR3,
VAR31, VAR26, VAR16, VAR35, VAR13, VAR7,
VAR28, VAR5, VAR11, VAR33, VAR34, VAR12, VAR44,
VAR39, VAR42, VAR21, VAR24, VAR10, VAR41, VAR22,
VAR15, VAR30, VAR29, VAR9,... | mit |
hightoon/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_STATUS_OUT.v | 5,293 | module MODULE1( VAR15,
VAR10, VAR14, VAR3, VAR2, VAR6,
VAR11 );
input VAR15;
input VAR14;
input VAR10,
VAR3,
VAR2;
output VAR6;
reg VAR6;
output reg [1:0] VAR11;
parameter VAR9 = 2'b00;
parameter VAR1 = 2'b01;
parameter VAR8 = 2'b10;
parameter VAR13 = 2'b11;
reg [2:0] counter;
wire VAR5;
VAR12 VAR4(
.clk(VAR15),
.rst(1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd.behavioral.pp.v | 1,230 | module MODULE1 (
VAR4,
VAR2,
VAR1 ,
VAR3
);
input VAR4;
input VAR2;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
hongyunnchen/miaow | src/verilog/rtl/lsu/lsu_rd_stage_router.v | 6,741 | module MODULE1
(
VAR4, VAR23,
VAR6, VAR43,
VAR16, VAR5,
VAR7, VAR14, VAR24,
VAR36, VAR20, VAR1,
VAR33, VAR26, VAR27,
VAR34, VAR9, VAR42, VAR13,
VAR46, VAR30, VAR11,
VAR19, VAR39, VAR40, VAR32,
VAR22, VAR17, VAR2,
VAR28, VAR21
);
input VAR34;
input [11:0] VAR9;
input [11:0] VAR42;
input [11:0] VAR13;
input [11:0] VAR46;... | bsd-3-clause |
EliasLuiz/TCC | Leon3/lib/opencores/ge_1000baseX/clean_rst.v | 3,371 | module MODULE1(
input clk,
input VAR1,
output reg VAR3
);
reg VAR2;
always @(posedge clk, posedge VAR1)
begin
VAR2 <= (VAR1) ? 1 : 0;
VAR3 <= (VAR1) ? 1 : VAR2;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/fill/sky130_fd_sc_hdll__fill.pp.symbol.v | 1,183 | module MODULE1 (
input VAR3 ,
input VAR1,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/pcieCore/source/pcieCore_axi_basic_rx_pipeline.v | 26,667 | module MODULE1 #(
parameter VAR66 = 128, parameter VAR8 = "VAR13", parameter VAR2 = 1,
parameter VAR44 = (VAR66 == 128) ? 2 : 1, parameter VAR59 = VAR66 / 8 ) (
output reg [VAR66-1:0] VAR76, output reg VAR37, input VAR79, output [VAR59-1:0] VAR65, output VAR16, output reg [21:0] VAR21,
input [VAR66-1:0] VAR27, input VA... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Double_Range.v | 1,113 | module MODULE1
(
VAR1,
VAR2
);
input signed [31:0] VAR1; output signed [31:0] VAR2;
wire signed [31:0] VAR3;
assign VAR3 = {VAR1[31], VAR1[31:1]};
assign VAR2 = VAR3;
endmodule | gpl-3.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_800kHz/fir_lp_800kHz_stub.v | 1,499 | module MODULE1(VAR5, VAR3, VAR4, VAR1, VAR6, VAR2)
;
input VAR5;
input VAR3;
output VAR4;
input [31:0]VAR1;
output VAR6;
output [111:0]VAR2;
endmodule | gpl-2.0 |
jairov4/accel-oil | solution_spartan6/syn/verilog/nfa_get_initials.v | 11,391 | module MODULE1 (
VAR10,
VAR25,
VAR38,
VAR22,
VAR32,
VAR5,
VAR35,
VAR8,
VAR15,
VAR31,
VAR28,
VAR7,
VAR19,
VAR34,
VAR2,
VAR13,
VAR27,
VAR33
);
input VAR10;
input VAR25;
input VAR38;
output VAR22;
output VAR32;
output VAR5;
output VAR35;
input VAR8;
output VAR15;
input VAR31;
output VAR28;
output [31:0] VAR7;
input [31:0]... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.pp.symbol.v | 1,283 | module MODULE1 (
input VAR6 ,
output VAR5 ,
input VAR1 ,
input VAR4,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4/sky130_fd_sc_ms__and4.behavioral.v | 1,392 | module MODULE1 (
VAR6,
VAR9,
VAR11,
VAR1,
VAR3
);
output VAR6;
input VAR9;
input VAR11;
input VAR1;
input VAR3;
supply1 VAR10;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR12 ;
wire VAR2;
and VAR5 (VAR2, VAR9, VAR11, VAR1, VAR3 );
buf VAR8 (VAR6 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2_2.v | 2,203 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR5 ,
VAR7 ,
VAR6,
VAR9,
VAR4 ,
VAR8
);
output VAR3 ;
input VAR10 ;
input VAR5 ;
input VAR7 ;
input VAR6;
input VAR9;
input VAR4 ;
input VAR8 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
samyk/proxmark3 | fpga/lo_read.v | 2,959 | module MODULE1(
input VAR7, input [7:0] VAR17, input VAR15,
output VAR6, output VAR5,
output VAR16, output VAR10, output VAR4, output VAR1,
input [7:0] VAR11, output VAR13,
output VAR14, output VAR12, output VAR8,
output VAR3,
input VAR2
);
reg [7:0] VAR9;
always @(posedge VAR7)
begin
if((VAR17 == 8'd7) && !VAR15)
VAR9... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_mul_ll_hc_core.v | 21,661 | module MODULE1 #(
parameter integer VAR71 = 1 )
(
input logic VAR25,
input logic VAR103,
input logic VAR40,
input logic VAR7,
output logic VAR78,
output logic VAR73,
input logic enable,
input logic [31:0] VAR13,
input logic [31:0] VAR8,
output logic [31:0] VAR68
);
struct packed
{
logic VAR42, VAR51;
logic [7:0] VAR96,... | mit |
sorgelig/SAMCoupe_MIST | mouse.v | 2,669 | module MODULE1
(
input VAR4,
input VAR6,
input reset,
input [24:0] VAR5,
input rd,
output [4:0] dout
);
assign dout = {1'b1, VAR11};
reg [3:0] VAR10;
reg [11:0] VAR15,VAR13;
reg [11:0] VAR9,VAR8;
wire [11:0] VAR2 = {{4{VAR5[4]}},VAR5[15:8]};
wire [11:0] VAR14 = {{4{VAR5[5]}},VAR5[23:16]};
wire [11:0] VAR7 = VAR15 + VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_xres4v2/sky130_fd_io__top_xres4v2.symbol.v | 1,986 | module MODULE1 (
input VAR7 ,
input VAR11 ,
inout VAR14 ,
inout VAR18 ,
inout VAR5 ,
inout VAR4 ,
input VAR2,
input VAR19 ,
input VAR21 ,
input VAR22 ,
output VAR15 ,
inout VAR20 ,
output VAR13 ,
inout VAR25 ,
output VAR8
);
supply1 VAR16 ;
supply1 VAR23 ;
supply1 VAR10 ;
supply1 VAR24 ;
supply1 VAR17;
supply0 VAR3 ;
s... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/dma_queue/nf2_dma.v | 11,884 | module MODULE1
parameter VAR33 = 11,
parameter VAR25 = 32,
parameter VAR46=VAR25/8,
parameter VAR40=64,
parameter VAR23 = 32
)
(
input [VAR29-1:0] VAR19,
output VAR38,
input [VAR25-1:0] VAR56,
input [VAR46-1:0] VAR53,
output VAR50,
input [VAR25-1:0] VAR30,
input [VAR46-1:0] VAR35,
output VAR49,
input [VAR25-1:0] VAR5,
... | mit |
alonso193/proyecto1 | SD_host.v | 4,644 | module MODULE1 (VAR2,
VAR48,
VAR49,
VAR28,
VAR51,
VAR59,
VAR12,
VAR10,
VAR41,
VAR18,
VAR14,
VAR58,
VAR8,
VAR56,
VAR44,
VAR13,
VAR9,
VAR40,
VAR45,
VAR36,
VAR60,
VAR25,
VAR17);
input wire VAR2, VAR48;
input wire VAR8;
output wire VAR56;
output wire VAR44;
output wire VAR13;
output wire VAR9;
input wire VAR28;
output wire... | gpl-3.0 |
Ribeiro/sd2snes | verilog/sd2snes/srtc.v | 5,452 | module MODULE1(
input VAR19,
input VAR15,
input [3:0] VAR11,
output [7:0] VAR10,
input [59:0] VAR25,
output [59:0] VAR17,
input VAR18,
input VAR14,
input VAR16,
input enable,
output VAR3,
input reset,
output [4:0] VAR8,
output VAR7,
output [3:0] VAR22,
output [5:0] VAR23
);
reg [59:0] VAR21;
reg [59:0] VAR4;
assign VAR... | gpl-2.0 |
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