repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/round_reg.v | 1,403 | module MODULE1
parameter VAR1=0)
(input clk,
input [VAR6-1:0] in,
output reg [VAR1-1:0] out,
output reg [VAR6-VAR1:0] VAR2);
wire [VAR1-1:0] VAR3;
wire [VAR6-VAR1:0] VAR4;
VAR5 #(.VAR6(VAR6),.VAR1(VAR1)) VAR5 (.in(in),.out(VAR3), .VAR2(VAR4));
always @(posedge clk)
out <= VAR3;
always @(posedge clk)
VAR2 <= VAR4;
endmo... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrnq/gf180mcu_fd_sc_mcu7t5v0__latrnq_2.behavioral.v | 2,848 | module MODULE1( VAR25, VAR7, VAR19, VAR16 );
input VAR7, VAR25, VAR19;
output VAR16;
reg VAR13;
VAR15 VAR1(.VAR25(VAR25),.VAR7(VAR7),.VAR19(VAR19),.VAR16(VAR16),.VAR13(VAR13));
VAR15 VAR5(.VAR25(VAR25),.VAR7(VAR7),.VAR19(VAR19),.VAR16(VAR16),.VAR13(VAR13));
buf VAR4(VAR17,VAR19);
not VAR6(VAR18,VAR7);
and VAR2(VAR8,VAR... | apache-2.0 |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/register_table.v | 78,102 | module MODULE1(
input clk,
input rst,
output reg VAR15,
output reg [4:0] VAR118,
input [23:0] VAR127, input [23:0] VAR115,
output VAR184,
output reg VAR5,
output [31:0] VAR105,
output [31:0] VAR195,
output reg VAR153,
output [31:0] VAR35,
output [31:0] VAR129,
output reg VAR14,
output [31:0] VAR40,
output [31:0] VAR43,... | bsd-2-clause |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Position/TOP_Rotation_tst.v | 3,008 | module MODULE1;
reg clk;
reg rst;
reg [15:0] VAR2;
reg [15:0] VAR8;
reg [15:0] VAR11;
reg [31:0] VAR7;
reg enable;
reg [7:0] VAR4;
reg VAR1;
reg VAR9;
reg [31:0] VAR17;
wire VAR16;
wire [31:0] VAR5;
wire [31:0] VAR14;
wire [31:0] VAR3;
reg [15:0] VAR6;
reg [15:0] VAR10;
reg[8:0] VAR13;
VAR15 VAR12 (
.clk(clk),
.rst(rst... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4.functional.v | 1,312 | module MODULE1 (
VAR1,
VAR5,
VAR8,
VAR4,
VAR6
);
output VAR1;
input VAR5;
input VAR8;
input VAR4;
input VAR6;
wire VAR7;
nand VAR3 (VAR7, VAR6, VAR4, VAR8, VAR5 );
buf VAR2 (VAR1 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2oi/sky130_fd_sc_hd__a2bb2oi.behavioral.pp.v | 2,245 | module MODULE1 (
VAR17 ,
VAR9,
VAR14,
VAR7 ,
VAR15 ,
VAR16,
VAR12,
VAR8 ,
VAR5
);
output VAR17 ;
input VAR9;
input VAR14;
input VAR7 ;
input VAR15 ;
input VAR16;
input VAR12;
input VAR8 ;
input VAR5 ;
wire VAR13 ;
wire VAR4 ;
wire VAR2 ;
wire VAR19;
and VAR3 (VAR13 , VAR7, VAR15 );
nor VAR6 (VAR4 , VAR9, VAR14 );
nor V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.behavioral.v | 2,350 | module MODULE1 (
VAR17 ,
VAR9 ,
VAR16 ,
VAR3
);
output VAR17 ;
input VAR9 ;
input VAR16 ;
input VAR3;
supply1 VAR21;
supply0 VAR13;
supply1 VAR18 ;
supply0 VAR14 ;
wire VAR6 ;
wire VAR19 ;
wire VAR15 ;
reg VAR20 ;
wire VAR7 ;
wire VAR1;
wire VAR5 ;
wire VAR11 ;
wire VAR22 ;
wire VAR23 ;
not VAR12 (VAR19 , VAR1 );
not V... | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/gpio/gpio.v | 1,452 | module MODULE1 #(
parameter VAR8 = 16'h0000,
parameter VAR23 = 16'h0000,
parameter VAR13 = 16,
parameter VAR2 = 8,
parameter VAR3 = 0,
parameter VAR19 = 0
) (
input wire VAR4,
input wire VAR17,
input wire [VAR13-1:0] VAR16,
inout wire [7:0] VAR14,
input wire VAR6,
input wire VAR11,
inout wire [VAR2-1:0] VAR21
);
wire V... | bsd-3-clause |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/CPZero.v | 27,505 | module MODULE1(
input VAR6,
input VAR21, input VAR20, input VAR132,
input VAR19, input VAR138, input VAR102, input VAR111, input VAR119, input [4:0] VAR16, input [2:0] VAR12, input [31:0] VAR77, output reg [31:0] VAR10, output VAR93, output VAR104, input [4:0] VAR81, input reset, input VAR87, input VAR73, input VAR9, i... | lgpl-3.0 |
dbousias/RoachSweeper | Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemScore/MemScore_stub.v | 1,240 | module MODULE1(VAR1, clk, VAR2)
;
input [7:0]VAR1;
input clk;
output [11:0]VAR2;
endmodule | gpl-3.0 |
asicguy/gplgpu | hdl/crt_sp/crtregist.v | 11,674 | module MODULE1
(
input VAR44,
input VAR4,
input VAR32,
input VAR8,
input [3:0] VAR56,
input [31:0] VAR38,
input [7:2] VAR45, input VAR54,
input VAR28, input [11:0] VAR39,
input VAR57, input [20:0] VAR40,
output reg [31:0] VAR50,
output reg [7:0] VAR49,
output reg [11:0] VAR43,
output reg [13:0] VAR18,
output reg [13:0]... | gpl-3.0 |
Cognoscan/BoostDSP | verilog/src/smallFilters/SmallBpf.v | 3,894 | module MODULE1 #(
parameter VAR9 = 16, parameter VAR12 = 10, parameter VAR8 = 18, parameter VAR3 = 1 )
(
input clk, input rst, input en, input signed [VAR9-1:0] VAR5, output signed [VAR9-1:0] VAR7 );
reg signed [VAR9+VAR12-1:0] VAR10;
reg signed [VAR9+VAR8-1:0] VAR4;
reg signed [VAR9+1:0] VAR1;
wire signed [VAR9-1:0] V... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_chip/bsg_rocket/bsg_nonsynth_chipset_rocket_fsb.v | 8,351 | module MODULE1
, parameter VAR72=8
, parameter VAR110=5'b11111
, parameter VAR104 = 0
, parameter VAR22 = 1
, parameter VAR29 = 3
, parameter VAR42 = 6
, parameter VAR16 = 10
, parameter VAR51 = VAR16*VAR72
, parameter VAR30 = VAR51+4
)
(
input VAR49
, input VAR102
, input VAR121
, input [VAR127 - 1:0] VAR53 , input [V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.functional.pp.v | 2,068 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR16 ,
VAR12 ,
VAR3 ,
VAR2,
VAR15,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR4 ;
input VAR16 ;
input VAR12 ;
input VAR3 ;
input VAR2;
input VAR15;
input VAR9 ;
input VAR7 ;
wire VAR14 ;
wire VAR6 ;
wire VAR8;
or VAR10 (VAR14 , VAR16, VAR4 );
nand VAR17 (VAR6 , VAR3, VAR14, VAR12 );
VAR5 VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.behavioral.v | 1,581 | module MODULE1 (
VAR15 ,
VAR6,
VAR4,
VAR11,
VAR12,
VAR8
);
output VAR15 ;
input VAR6;
input VAR4;
input VAR11;
input VAR12;
input VAR8;
supply1 VAR3;
supply0 VAR7;
supply1 VAR9 ;
supply0 VAR2 ;
wire VAR10 ;
wire VAR1;
and VAR13 (VAR10 , VAR11, VAR6, VAR4 );
nor VAR5 (VAR1, VAR10, VAR12, VAR8);
buf VAR14 (VAR15 , VAR1 )... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkICAPWorker.v | 67,355 | module MODULE1(VAR327,
VAR269,
VAR260,
VAR214,
VAR378,
VAR324,
VAR438,
VAR279,
VAR103,
VAR108,
VAR360,
VAR183);
parameter VAR217 = "";
parameter [0 : 0] VAR250 = 1'b0;
input VAR327;
input VAR269;
input [2 : 0] VAR260;
input VAR214;
input [3 : 0] VAR378;
input [31 : 0] VAR324;
input [31 : 0] VAR438;
output [1 : 0] VAR27... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fa/sky130_fd_sc_ms__fa.symbol.v | 1,291 | module MODULE1 (
input VAR9 ,
input VAR5 ,
input VAR1 ,
output VAR8,
output VAR6
);
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
YosysHQ/yosys | techlibs/xilinx/brams_xc3sda_map.v | 5,591 | module MODULE1 (...);
parameter VAR124 = 0;
parameter VAR125 = "VAR39";
parameter VAR44 = "VAR65";
parameter VAR86 = 0;
parameter VAR2 = 1;
parameter VAR1 = 1;
parameter VAR26 = 1;
parameter VAR46 = "VAR116";
parameter VAR101 = 0;
parameter VAR31 = 0;
parameter VAR81 = 0;
parameter VAR69 = "VAR103";
parameter VAR110 = ... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai.symbol.v | 1,344 | module MODULE1 (
input VAR8,
input VAR7,
input VAR1,
input VAR5,
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR6;
endmodule | apache-2.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | contador_AD_MM_T_2dig.v | 4,716 | module MODULE1
(
input wire clk,
input wire reset,
input wire [3:0] VAR2,
input wire VAR1,
input wire VAR9,
output wire [7:0] VAR10
);
localparam VAR4 = 6; reg [VAR4-1:0] VAR5, VAR7;
wire [VAR4-1:0] VAR6;
reg [3:0] VAR3, VAR8;
always@(posedge clk, posedge reset)
begin
if(reset)
begin
VAR5 <= 6'b0;
end
else
begin
VAR5 <... | mit |
scalable-networks/ext | uhd/fpga/usrp2/models/IOBUF.v | 2,646 | module MODULE1 (VAR5, VAR9, VAR11, VAR10);
parameter VAR7 = "VAR2";
parameter integer VAR16 = 12;
parameter VAR13 = "0";
parameter VAR17 = "VAR15";
parameter VAR12 = "VAR4";
parameter VAR18 = "VAR6";
output VAR5;
inout VAR9;
input VAR11, VAR10;
wire VAR19;
or VAR8 (VAR19, VAR14, VAR10);
bufif0 VAR3 (VAR9, VAR11, VAR19)... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/verilog/convolve_kernel_fcud.v | 1,944 | module MODULE1
VAR12 = 8,
VAR1 = 5,
VAR11 = 32,
VAR4 = 32,
VAR8 = 32
)(
input wire clk,
input wire reset,
input wire VAR26,
input wire [VAR11-1:0] VAR19,
input wire [VAR4-1:0] VAR18,
output wire [VAR8-1:0] dout
);
wire VAR2;
wire VAR9;
wire VAR22;
wire [31:0] VAR24;
wire VAR23;
wire [31:0] VAR20;
wire VAR7;
wire [31:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.behavioral.pp.v | 1,868 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8,
VAR6,
VAR4 ,
VAR2
);
output VAR3 ;
input VAR5 ;
input VAR8;
input VAR6;
input VAR4 ;
input VAR2 ;
wire VAR7 ;
wire VAR1;
buf VAR12 (VAR7 , VAR5 );
VAR10 VAR9 (VAR1, VAR7, VAR8, VAR6);
buf VAR11 (VAR3 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1.behavioral.pp.v | 1,832 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR7,
VAR6,
VAR12 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR7;
input VAR6;
input VAR12 ;
input VAR4 ;
wire VAR11 ;
wire VAR8;
buf VAR1 (VAR11 , VAR9 );
VAR2 VAR10 (VAR8, VAR11, VAR7, VAR6);
buf VAR3 (VAR5 , VAR8 );
endmodule | apache-2.0 |
sachitkuhar/amba_ahb | combine.v | 3,841 | module MODULE1();
reg VAR1;
reg VAR5;
wire VAR2;
wire [3:0] VAR4;
wire [3:0] VAR3;
reg clk;
always@(posedge clk)
begin
assign VAR1 = ~VAR1;
assign VAR5 = ~VAR5;
end
always
assign clk = ~clk;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32a/sky130_fd_sc_hs__o32a.pp.symbol.v | 1,357 | module MODULE1 (
input VAR7 ,
input VAR3 ,
input VAR1 ,
input VAR6 ,
input VAR5 ,
output VAR8 ,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_byte_group_io.v | 19,753 | module MODULE1 #(
parameter VAR105 = 12'b111111111111,
parameter VAR161 = 12'b000000000000,
parameter VAR32 = "VAR166",
parameter VAR23 = "VAR113",
parameter VAR83 = 4,
parameter VAR1 = "VAR143",
parameter VAR5 = 00,
parameter VAR75 = "VAR48",
parameter VAR59 = 12,
parameter VAR3 = "VAR166"
)
(
input [9:0] VAR71,
outpu... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.functional.pp.v | 1,863 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR13 ,
VAR10,
VAR11,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR13 ;
input VAR10;
input VAR11;
input VAR2 ;
input VAR5 ;
wire VAR4 ;
wire VAR6;
VAR9 VAR8 (VAR4 , VAR3, VAR10, VAR11 );
VAR9 VAR12 (VAR6, VAR13, VAR10, VAR11 );
notif1 VAR7 (VAR1 , VAR4, VAR6);
endmodule | apache-2.0 |
jakubfi/mera400f | src/strobgen.v | 2,830 | module MODULE1(
input VAR17,
input VAR3, VAR2, VAR28, VAR30, VAR21,
input VAR14, VAR6, VAR12,
input VAR25, VAR1,
input VAR7,
input VAR31,
output VAR5,
output VAR26,
output VAR8,
output VAR33,
output VAR22,
output VAR20
);
localparam VAR27 = 3'd0;
localparam VAR16 = 3'd1;
localparam VAR18 = 3'd2;
localparam VAR10 = 3'd3... | gpl-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/whr_crossbar_mac.v | 3,198 | module MODULE1
(clk, reset, VAR7, VAR20, VAR19);
parameter VAR18 = 5;
parameter VAR11 = 5;
parameter VAR8 = 32;
parameter VAR10 = VAR9;
parameter VAR13 = VAR17;
input clk;
input reset;
input [0:VAR18*VAR11-1] VAR7;
input [0:VAR18*VAR8-1] VAR20;
output [0:VAR11*VAR8-1] VAR19;
wire [0:VAR11*VAR8-1] VAR19;
wire [0:VAR11*V... | mit |
olajep/oh | src/adi/hdl/library/util_axis_fifo/address_gray_pipelined.v | 4,567 | module MODULE1 #(
parameter VAR1 = 4
) (
input VAR6,
input VAR21,
input VAR14,
output reg VAR26,
output [VAR1-1:0] VAR3,
output reg [VAR1:0] VAR5,
input VAR8,
input VAR15,
output reg VAR16,
input VAR9,
output reg VAR12,
output [VAR1-1:0] VAR2,
output reg [VAR1:0] VAR23
);
localparam VAR20 = {1'b1,{VAR1{1'b0}}};
reg [VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbp/sky130_fd_sc_hs__dlxbp_1.v | 2,135 | module MODULE2 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR8,
VAR5,
VAR7
);
output VAR3 ;
output VAR6 ;
input VAR2 ;
input VAR8;
input VAR5;
input VAR7;
VAR1 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR3 ,
VAR6 ,
VAR2 ,
VAR8
);
output VAR3 ;
output VAR6 ;
input VAR... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_generic_reg_grp.v | 28,336 | module MODULE1
parameter VAR53 = VAR49,
parameter VAR19 = 8,
parameter VAR35 = VAR79(VAR19),
parameter VAR66 = 16,
parameter VAR6 = 0, parameter VAR12 = 0 )
(
input VAR3,
input [VAR35-1:0] VAR75,
output [VAR53-1:0] VAR73,
input VAR98,
input [VAR35-1:0] VAR94,
input [VAR66-1:0] VAR74,
output reg [VAR53-1:0] VAR90,
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbn/sky130_fd_sc_ms__sdfbbn.behavioral.v | 3,407 | module MODULE1 (
VAR5 ,
VAR15 ,
VAR22 ,
VAR39 ,
VAR16 ,
VAR9 ,
VAR28 ,
VAR30
);
output VAR5 ;
output VAR15 ;
input VAR22 ;
input VAR39 ;
input VAR16 ;
input VAR9 ;
input VAR28 ;
input VAR30;
supply1 VAR25;
supply0 VAR8;
supply1 VAR17 ;
supply0 VAR35 ;
wire VAR33 ;
wire VAR18 ;
wire VAR32 ;
wire VAR26 ;
reg VAR14 ;
wire... | apache-2.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/mod_interrupt.v | 2,230 | module MODULE1(rst, clk, VAR17, VAR5, VAR15, VAR18, VAR8, din, VAR9, dout, int, VAR1, VAR16, VAR7, VAR10);
input rst;
input clk;
input VAR17,VAR5;
input [31:0] VAR15, VAR18;
input [1:0] VAR8;
input [31:0] din;
output [31:0] VAR9, dout;
output int;
input VAR1;
input VAR16;
input VAR7;
input VAR10;
reg [31:1] VAR4;
reg [... | gpl-3.0 |
justingallagher/fpga-trace | design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/generic_baseblocks_v2_1/da89d453/hdl/verilog/generic_baseblocks_v2_1_carry_latch_and.v | 4,380 | module MODULE1 #
(
parameter VAR4 = "VAR13"
)
(
input wire VAR3,
input wire VAR11,
output wire VAR9
);
generate
if ( VAR4 == "VAR2" ) begin : VAR8
assign VAR9 = VAR3 & ~VAR11;
end else begin : VAR7
wire VAR12;
assign VAR12 = ~VAR11;
VAR5 VAR1
(
.VAR9(VAR9),
.VAR10(VAR3),
.VAR6(VAR12)
);
end
endgenerate
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.functional.v | 1,303 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR4;
bufif0 VAR2 (VAR3 , VAR1, VAR4 );
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/board/uniphy_status/uniphy_status.v | 3,827 | module MODULE1
parameter VAR5=32,
parameter VAR15=2
)
(
input clk,
input VAR29,
input VAR23,
output [VAR5-1:0] VAR13,
input VAR38,
input VAR2,
input VAR16,
input VAR24,
input VAR37,
input VAR28,
input VAR19,
input VAR14,
input VAR36,
input VAR27,
input VAR8,
input VAR31,
input VAR22,
input VAR10,
input VAR20,
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.functional.pp.v | 1,957 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR3,
VAR2,
VAR7,
VAR13 ,
VAR6
);
output VAR9 ;
input VAR11 ;
input VAR3;
input VAR2;
input VAR7;
input VAR13 ;
input VAR6 ;
wire VAR1 ;
wire VAR10;
VAR5 VAR8 (VAR1 , VAR11, VAR2, VAR7 );
VAR5 VAR4 (VAR10, VAR3, VAR2, VAR7 );
bufif0 VAR12 (VAR9 , VAR1, VAR10);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux4/sky130_fd_sc_hvl__mux4.blackbox.v | 1,343 | module MODULE1 (
VAR3 ,
VAR5,
VAR9,
VAR1,
VAR2,
VAR7,
VAR4
);
output VAR3 ;
input VAR5;
input VAR9;
input VAR1;
input VAR2;
input VAR7;
input VAR4;
supply1 VAR10;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR11 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.pp.symbol.v | 1,336 | module MODULE1 (
input VAR7 ,
output VAR8 ,
output VAR3 ,
input VAR1 ,
input VAR4 ,
input VAR6,
input VAR5,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso0p/sky130_fd_sc_lp__inputiso0p.functional.v | 1,357 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR2
);
output VAR4 ;
input VAR5 ;
input VAR2;
wire VAR6;
not VAR1 (VAR6, VAR2 );
and VAR3 (VAR4 , VAR5, VAR6 );
endmodule | apache-2.0 |
binary-logic/vj-uart | rtl/buffer_bb.v | 5,872 | module MODULE1 (
VAR1,
VAR4,
VAR6,
VAR2,
VAR7,
VAR8,
VAR9,
VAR5,
VAR3);
input VAR1;
input [7:0] VAR4;
input VAR6;
input VAR2;
input VAR7;
input VAR8;
output [7:0] VAR9;
output VAR5;
output VAR3;
tri0 VAR1;
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai22/gf180mcu_fd_sc_mcu7t5v0__oai22_4.behavioral.v | 2,309 | module MODULE1( VAR7, VAR8, VAR6, VAR5, VAR3 );
input VAR3, VAR5, VAR8, VAR7;
output VAR6;
VAR4 VAR2(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3));
VAR4 VAR1(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
Koheron/zynq-sdk | fpga/cores/psd_counter_v1_0/psd_counter.v | 1,232 | module MODULE1 #
(
parameter integer VAR8 = 256,
parameter integer VAR1 = 8,
parameter integer VAR9 = 2048,
parameter integer VAR11 = 11
)
(
input wire clk,
input wire VAR14,
input wire [32-1:0] VAR4,
output wire VAR10,
output wire [32-1:0] VAR13,
output reg [VAR1+1:0] addr,
output reg [VAR11-1:0] VAR6,
output reg VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.symbol.v | 1,297 | module MODULE1 (
input VAR4,
input VAR3 ,
output VAR5
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | rtl/bootloader/bootloader.v | 2,912 | module MODULE1
parameter VAR6 = 32,
parameter VAR19 = 20
)
(
input clk,
input VAR11,
output reg VAR13,
output reg [VAR19-1:0] VAR14,
input [VAR6-1:0] VAR18,
output reg VAR17,
output reg [VAR6-1:0] VAR4,
output reg [VAR19-1:0] VAR1,
output reg VAR5
);
localparam VAR16 = 0,
VAR15 = 1,
VAR9 = 2,
VAR8 = 3;
localparam VAR7 ... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9144/axi_ad9144_channel.v | 21,634 | module MODULE1 (
VAR46,
VAR26,
VAR34,
VAR43,
VAR28,
VAR27,
VAR61,
VAR18,
VAR56,
VAR68,
VAR13,
VAR15,
VAR53,
VAR42,
VAR9,
VAR1,
VAR23);
parameter VAR67 = 32'h0;
parameter VAR69 = 0;
input VAR46;
input VAR26;
output VAR34;
output [63:0] VAR43;
input [63:0] VAR28;
input VAR27;
input VAR61;
input VAR18;
input VAR56;
input ... | gpl-3.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_to_sw_sig.v | 1,933 | module MODULE1 (
address,
clk,
VAR4,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 1: 0] VAR4;
input VAR2;
wire VAR5;
wire [ 1: 0] VAR6;
wire [ 1: 0] VAR3;
reg [ 31: 0] VAR1;
assign VAR5 = 1;
assign VAR3 = {2 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR2)
begin
if (VAR2... | apache-2.0 |
boztalay/HighSchoolSeniorProject | FPGA Stuff/OZ4_Mandelbrot/Hardware/OZ4_Mandelbrot/ipcore_dir/FIFO30x16.v | 13,925 | module MODULE1(
rst,
VAR406,
VAR81,
din,
VAR63,
VAR198,
dout,
VAR312,
VAR265
);
input rst;
input VAR406;
input VAR81;
input [30 : 0] din;
input VAR63;
input VAR198;
output [30 : 0] dout;
output VAR312;
output VAR265;
VAR32 #(
.VAR302(0),
.VAR91(0),
.VAR290(0),
.VAR287(0),
.VAR386(0),
.VAR182(0),
.VAR83(0),
.VAR172(32),... | mit |
skarpenko/ultiparc | rtl/src/cpu/uparc_alu.v | 2,936 | module MODULE1(
VAR6,
VAR11,
VAR7,
VAR9,
VAR2
);
input wire [VAR1-1:0] VAR6;
input wire [VAR8-1:0] VAR11;
input wire [VAR8-1:0] VAR7;
output reg [VAR8-1:0] VAR9;
output wire VAR2;
wire [VAR8-1:0] VAR4;
wire [VAR8-1:0] VAR5;
wire [VAR8-1:0] VAR3;
assign VAR4 = (VAR6 != VAR10 ? VAR7 : (~VAR7) + 1);
assign VAR5 = VAR11 + ... | bsd-2-clause |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dwidth_converter_v2_1/hdl/verilog/axi_dwidth_converter_v2_1_axi4lite_downsizer.v | 14,621 | module MODULE1 #
(
parameter VAR34 = "none",
parameter integer VAR49 = 32,
parameter integer VAR4 = 1,
parameter integer VAR11 = 1
)
(
input wire VAR29,
input wire VAR35,
input wire [VAR49-1:0] VAR10,
input wire [3-1:0] VAR39,
input wire VAR17,
output wire VAR33,
input wire [64-1:0] VAR23,
input wire [64/8-1:0] VAR56,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp_2.v | 2,466 | module MODULE2 (
VAR12 ,
VAR11 ,
VAR3 ,
VAR2 ,
VAR8 ,
VAR7 ,
VAR4,
VAR10,
VAR9 ,
VAR6
);
output VAR12 ;
input VAR11 ;
input VAR3 ;
input VAR2 ;
input VAR8 ;
input VAR7 ;
input VAR4;
input VAR10;
input VAR9 ;
input VAR6 ;
VAR5 VAR1 (
.VAR12(VAR12),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | core/core_id_regfile.v | 1,593 | module MODULE1( clk,
rst,
VAR3,
VAR2,
VAR8,
VAR6,
VAR4,
VAR7,
VAR1
);
input clk;
input rst;
input [4:0] VAR3;
input [4:0] VAR2;
input VAR8;
input [4:0] VAR6;
input [31:0] VAR4;
output [31:0] VAR7;
output [31:0] VAR1;
reg [31:0] VAR5 [31:0];
always @ (posedge clk) begin
if (rst==1'b1) begin
if((VAR8==1'b1) && (VAR6!=32'... | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v | 1,741 | module MODULE1 (
VAR3
);
parameter VAR16 = 1;
parameter VAR15 = "VAR19";
input [VAR16-1:0] VAR3;
VAR5 VAR26 (
.VAR20 (VAR3),
.VAR21 ()
,
.VAR4 (),
.VAR12 (),
.VAR1 (),
.VAR9 (),
.VAR25 (),
.VAR27 (),
.VAR32 (),
.VAR18 (),
.VAR22 (),
.VAR11 (),
.VAR6 (),
.VAR23 (),
.VAR24 (),
.VAR29 (),
.VAR17 (),
.VAR34 (),
.VAR13 ()
)... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o_1.v | 2,347 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR10 ,
VAR8 ,
VAR6 ,
VAR9,
VAR4,
VAR3 ,
VAR5
);
output VAR7 ;
input VAR2 ;
input VAR10 ;
input VAR8 ;
input VAR6 ;
input VAR9;
input VAR4;
input VAR3 ;
input VAR5 ;
VAR11 VAR1 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/conbus/rtl/conbus_arb.v | 3,351 | module MODULE1(
input VAR3,
input VAR7,
input [6:0] req,
output [6:0] VAR2
);
parameter [6:0] VAR10 = 7'b0000001,
VAR1 = 7'b0000010,
VAR9 = 7'b0000100,
VAR8 = 7'b0001000,
VAR6 = 7'b0010000,
VAR4 = 7'b0100000,
VAR5 = 7'b1000000;
reg [6:0] state;
reg [6:0] VAR11;
assign VAR2 = state;
always @(posedge VAR3) begin
if(VAR7)... | lgpl-3.0 |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Exponential/LUT_Z.v | 6,161 | module MODULE1#(parameter VAR5 = 32, parameter VAR6 = 5) (
input wire VAR4,
input wire VAR3,
input wire [VAR6-1:0] VAR1,
output reg [VAR5-1:0] VAR2
);
always @(posedge VAR4)
if (VAR3)
case (VAR1)
5'b00000: VAR2 <= 32'b11000000010001111001000001010111; 5'b00001: VAR2 <= 32'b11000000001100010101001000001000; 5'b00010: VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.symbol.v | 1,361 | module MODULE1 (
input VAR6,
input VAR2,
input VAR4,
input VAR1,
output VAR9
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b_4.v | 2,229 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR9 ,
VAR8 ,
VAR5,
VAR3,
VAR6 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR5;
input VAR3;
input VAR6 ;
input VAR4 ;
VAR7 VAR10 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE2 (... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/rx_data_receive.v | 5,204 | module MODULE1(
input VAR18,
input VAR1,
input VAR15,
input VAR13,
input VAR22,
input VAR4,
input VAR10,
input VAR6,
input VAR12,
input VAR14,
input [2:0] VAR5,
input [2:0] VAR16,
input [8:0] VAR20,
output reg [1:0] VAR3,
output reg VAR23,
output reg VAR7,
output reg VAR11,
output reg VAR19,
output reg VAR21,
output re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4bb/sky130_fd_sc_lp__or4bb_4.v | 2,314 | module MODULE2 (
VAR2 ,
VAR3 ,
VAR7 ,
VAR6 ,
VAR5 ,
VAR4,
VAR8,
VAR1 ,
VAR10
);
output VAR2 ;
input VAR3 ;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR10 ;
VAR11 VAR9 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/wb_bus_writer.v | 2,157 | module MODULE1 (input VAR8,
output VAR12,
output reg [15:0] VAR2,
input [47:0] VAR7,
input VAR15,
input VAR9,
output [31:0] VAR1,
input VAR3,
output [15:0] VAR13,
output VAR4,
output [3:0] VAR11,
output VAR5,
output VAR10
);
reg [3:0] state;
assign VAR12 = (state != VAR14) && (&VAR7);
always @(posedge VAR15)
if(VAR9)
b... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o_2.v | 2,444 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR11 ,
VAR1 ,
VAR7 ,
VAR5,
VAR8,
VAR4 ,
VAR12
);
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR11 ;
input VAR1 ;
input VAR7 ;
input VAR5;
input VAR8;
input VAR4 ;
input VAR12 ;
VAR10 VAR9 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VA... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/hps_sdram_p0_acv_hard_memphy.v | 28,416 | module MODULE1 (
VAR14,
VAR114,
VAR218,
VAR25,
VAR105,
VAR110,
VAR251,
VAR144,
VAR77,
VAR33,
VAR187,
VAR38,
VAR101,
VAR21,
VAR58,
VAR160,
VAR24,
VAR177,
VAR191,
VAR230,
VAR162,
VAR131,
VAR126,
VAR138,
VAR210,
VAR76,
VAR6,
VAR165,
VAR28,
VAR68,
VAR53,
VAR93,
VAR238,
VAR35,
VAR72,
VAR150,
VAR119,
VAR125,
VAR166,
VAR167,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.blackbox.v | 1,292 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR5;
supply1 VAR4;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.v | 2,690 | module MODULE1
(input VAR15
, input VAR39
, input VAR34
, input VAR24
, output VAR38
);
wire [1:0] VAR28;
wire [8:0] VAR27;
assign VAR27[0] = VAR15;
VAR43 VAR23 (.VAR3(VAR27[0]), .VAR19(VAR27[1]) );
VAR43 VAR31 (.VAR3(VAR27[1]), .VAR19(VAR27[2]) );
VAR8 VAR35 (.VAR3(VAR27[1]), .VAR19() );
VAR43 VAR10 (.VAR3(VAR27[2]), ... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/conb/sky130_fd_sc_ls__conb.functional.v | 1,183 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
output VAR2;
pullup VAR3 (VAR1 );
pulldown VAR4 (VAR2 );
endmodule | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/system/ddr3_afifo.v | 6,433 | module MODULE1
parameter VAR18 = 30,
parameter VAR21 = 32
)
(
input VAR20,
input VAR23,
input VAR34, input [2:0] VAR33, input [VAR18-1:0] VAR15, output VAR19,
output VAR11, input VAR25, input [VAR21/8-1:0] VAR28, input [VAR21-1:0] VAR26, input [1:0] VAR32, output [VAR21-1:0] VAR4, output VAR30,
output VAR7, output [2:0... | lgpl-3.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/meter_lite.v | 11,748 | module MODULE1#(
parameter VAR35 = 64,
parameter VAR75=VAR35/8,
parameter VAR27 = 2
)(
input [VAR35-1:0] VAR87,
input [VAR75-1:0] VAR49,
input VAR34,
output VAR99,
output [VAR35-1:0] VAR40,
output [VAR75-1:0] VAR21,
output VAR76,
input VAR96,
input [31:0] VAR85,
input [31:0] VAR6,
input VAR61,
input VAR23,
output VAR68... | lgpl-2.1 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_crosspoint_64_4x4.v | 16,444 | module MODULE1 #
(
parameter VAR76 = 64,
parameter VAR68 = (VAR76/8)
)
(
input wire clk,
input wire rst,
input wire [VAR76-1:0] VAR25,
input wire [VAR68-1:0] VAR87,
input wire VAR49,
input wire VAR20,
input wire VAR39,
input wire [VAR76-1:0] VAR21,
input wire [VAR68-1:0] VAR17,
input wire VAR66,
input wire VAR58,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapmet1/sky130_fd_sc_ls__tapmet1_2.v | 1,912 | module MODULE1 (
VAR6,
VAR2,
VAR5 ,
VAR1
);
input VAR6;
input VAR2;
input VAR5 ;
input VAR1 ;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 ();
supply1 VAR6;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
VAR4 VAR3 ();
endmodule | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/sram_bb.v | 7,659 | module MODULE1 (
VAR2,
VAR4,
VAR6,
VAR1,
VAR3,
VAR7,
VAR5);
input VAR2;
input [71:0] VAR4;
input [9:0] VAR6;
input VAR1;
input [9:0] VAR3;
input VAR7;
output [71:0] VAR5;
tri1 VAR2;
tri1 VAR1;
tri0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_g/sky130_fd_sc_hdll__udp_pwrgood_pp_g.blackbox.v | 1,259 | module MODULE1 (
VAR1,
VAR3 ,
VAR2
);
output VAR1;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b_2.v | 2,218 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR8 ,
VAR10 ,
VAR7,
VAR1,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR4 ;
input VAR8 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR5 ;
input VAR2 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_classify.v | 1,513 | module MODULE1
, parameter VAR9(VAR2)
, parameter VAR17=(VAR5+VAR2+1)
, parameter VAR22=VAR17
)
(
input [VAR17-1:0] VAR12
, output [VAR22-1:0] VAR25
);
logic VAR13;
logic VAR7;
logic VAR15;
logic VAR1;
logic VAR20;
logic VAR18;
VAR4 #(
.VAR5(VAR5)
,.VAR2(VAR2)
) VAR10 (
.VAR12(VAR12)
,.VAR6(VAR13)
,.VAR14(VAR7)
,.VAR8(... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.v | 2,463 | module MODULE1 (
VAR2 ,
VAR9,
VAR1,
VAR11 ,
VAR3 ,
VAR8,
VAR4,
VAR6 ,
VAR7
);
output VAR2 ;
input VAR9;
input VAR1;
input VAR11 ;
input VAR3 ;
input VAR8;
input VAR4;
input VAR6 ;
input VAR7 ;
VAR5 VAR10 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VA... | apache-2.0 |
hakehuang/pycpld | ips/ip/i2c_master_subad/I2C_MASTER_SUBAD.v | 2,848 | module MODULE1(clk,VAR16,VAR2,VAR18,VAR9,VAR11,VAR8
);
input clk;
input VAR16;
input VAR9;
input VAR11;
reg VAR6,VAR1;
output VAR18;
output VAR8;
inout VAR2;
reg VAR15;
reg VAR8;
reg[7:0] VAR13;
reg[7:0] VAR14;
wire[7:0] VAR5;
reg[7:0] VAR3;
wire ack;
reg[7:0] VAR4[33:0];
reg[7:0] VAR17[33:0];
always @(posedge clk or n... | mit |
nsauzede/cpu86 | papilio2/ipcore_dir/clk32to40.v | 5,691 | module MODULE1
( input VAR28,
output VAR38
);
VAR21 VAR29
(.VAR42 (VAR1),
.VAR33 (VAR28));
wire VAR6;
wire VAR22;
wire [7:0] VAR10;
wire VAR24;
wire VAR19;
wire VAR46;
VAR41
.VAR45 (4),
.VAR32 (5),
.VAR20 ("VAR18"),
.VAR34 (31.25),
.VAR5 ("VAR11"),
.VAR4 ("VAR11"),
.VAR7 ("VAR25"),
.VAR9 (0),
.VAR23 ("VAR18"))
VAR40
(.... | gpl-2.0 |
vvk/sysrek | complex/complex.v | 1,050 | module MODULE1(
input [7:0] VAR6,
input [7:0] VAR7,
output out
);
wire [9:0] VAR2;
wire [4:0] VAR4;
genvar VAR3;
generate
for(VAR3 = 0; VAR3 < 8; VAR3 = VAR3 + 1)
begin: VAR5
assign VAR2[VAR3] = VAR6[VAR3] & VAR7[VAR3];
end
for(VAR3 = 0; VAR3 < 4; VAR3 = VAR3 + 1)
begin: VAR1
assign VAR4[VAR3] = VAR2[2 * VAR3] | VAR2[2... | gpl-2.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_charToTransmitter.v | 2,032 | module MODULE1 (
address,
clk,
VAR1,
VAR5,
VAR4
)
;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR1;
input VAR5;
wire VAR3;
wire [ 7: 0] VAR6;
wire [ 7: 0] VAR2;
reg [ 31: 0] VAR4;
assign VAR3 = 1;
assign VAR2 = {8 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR5)
begin
if (VAR5... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_4.functional.pp.v | 1,168 | module MODULE1( VAR14, VAR11, VAR6, VAR3, VAR5 );
input VAR11, VAR14;
inout VAR3, VAR5;
output VAR6;
wire VAR1;
not VAR9( VAR1, VAR14 );
wire VAR7;
and VAR4( VAR7, VAR1, VAR11 );
wire VAR13;
not VAR10( VAR13, VAR11 );
wire VAR8;
and VAR2( VAR8, VAR13, VAR14 );
or VAR12( VAR6, VAR7, VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.pp.blackbox.v | 1,464 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR11 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR10 ,
VAR3,
VAR8,
VAR6 ,
VAR7
);
output VAR1 ;
input VAR9 ;
input VAR11 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR10 ;
input VAR3;
input VAR8;
input VAR6 ;
input VAR7 ;
endmodule | apache-2.0 |
hwstar/Timestamper-FPGA | dpram.v | 1,986 | module MODULE1 #(
parameter VAR13 = 64,
parameter VAR8 = 6
) (
input wire VAR6,
input wire VAR10,
input wire [VAR8-1:0] VAR11,
input wire [VAR13-1:0] VAR2,
output reg [VAR13-1:0] VAR12,
input wire VAR5,
input wire VAR4,
input wire [VAR8-1:0] VAR1,
input wire [VAR13-1:0] VAR9,
output reg [VAR13-1:0] VAR3
);
reg [VAR13-1... | gpl-2.0 |
duttondj/DigitalDesignI-P3 | TopModule.v | 2,382 | module MODULE1(VAR2, VAR1, VAR12, VAR24, VAR13, VAR3, VAR22);
input VAR2;
input [5:0] VAR1;
input [1:0] VAR12;
output [0:6] VAR24, VAR13, VAR3, VAR22; wire enable;
wire [15:0] VAR20;
VAR8 VAR18 (.VAR11(VAR2), .reset(VAR12[0]), .VAR26(VAR12[1]), .VAR17(enable));
VAR7 VAR19 (.VAR11(VAR2), .enable(enable), .VAR14(VAR12[0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtp/sky130_fd_sc_ms__dfrtp.behavioral.v | 2,202 | module MODULE1 (
VAR3 ,
VAR21 ,
VAR4 ,
VAR19
);
output VAR3 ;
input VAR21 ;
input VAR4 ;
input VAR19;
supply1 VAR7;
supply0 VAR10;
supply1 VAR12 ;
supply0 VAR17 ;
wire VAR14 ;
wire VAR6 ;
reg VAR5 ;
wire VAR8 ;
wire VAR11;
wire VAR13 ;
wire VAR20 ;
wire VAR16 ;
wire VAR2 ;
not VAR9 (VAR6 , VAR11 );
VAR1 VAR15 (VAR14 , ... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.cache/ip/2017.2/708f145cb2a4886a/zynq_design_1_processing_system7_0_0_stub.v | 5,596 | module MODULE1(VAR44, VAR53,
VAR49, VAR25, VAR27, VAR9,
VAR68, VAR46, VAR20, VAR39,
VAR11, VAR5, VAR26, VAR55, VAR47,
VAR54, VAR34, VAR24, VAR15,
VAR70, VAR60, VAR69, VAR52, VAR71,
VAR58, VAR67, VAR48, VAR7, VAR36,
VAR63, VAR10, VAR33, VAR43, VAR1,
VAR21, VAR16, VAR19, VAR61,
VAR29, VAR38, VAR3, VAR66, VAR8,
VAR12, VAR... | mit |
miamiasheep/nctu-dlab-99 | online2A/TailLight.v | 1,064 | module MODULE1(
input reset, VAR9, VAR16, clk,
output VAR15, VAR3, VAR8, VAR2, VAR7, VAR5
);
parameter VAR12 = 3'b000;
parameter VAR11 = 3'b001;
parameter VAR14 = 3'b010;
parameter VAR1 = 3'b011;
parameter VAR4 = 3'b100;
parameter VAR6 = 3'b101;
parameter VAR10 = 3'b110;
reg [2:0] state, VAR13;
always @(posedge clk)
if... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_pcie_bram_7x.v | 8,982 | module MODULE1
parameter [3:0] VAR25 = 4'h1, parameter [5:0] VAR12 = 6'h08, parameter VAR22 = "VAR10", parameter VAR4 = 0, parameter VAR11 = 0 )
(
input VAR9, input VAR7,
input VAR19, input [12:0] VAR29, input [VAR11 - 1:0] VAR15,
input VAR17, input VAR26, input [12:0] VAR2,
output [VAR11 - 1:0] VAR20 );
localparam VAR... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/verilog/spree.v | 72,551 | module MODULE3 (
clk,
VAR100,
VAR232,
VAR126,
VAR286,
VAR78,
VAR208,
VAR219,
VAR145
);
input clk;
input VAR100;
input [31:0] VAR232;
input [31:0] VAR126;
input VAR286;
input [31:0] VAR78;
input [31:0] VAR208;
input VAR219;
output [31:0] VAR145;
wire VAR105;
wire VAR268;
wire VAR42;
wire VAR160;
wire VAR41;
wire VAR218;... | mit |
tugrulyatagan/RISC-processor | xilinx_processor/uart.v | 2,840 | module MODULE1 #
(
parameter VAR10 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR10-1:0] VAR14,
input wire VAR12,
output wire VAR5,
output wire [VAR10-1:0] VAR18,
output wire VAR21,
input wire VAR16,
input wire VAR13,
output wire VAR11,
output wire VAR20,
output wire VAR19,
output wire VAR3,
output wire VAR17,... | gpl-2.0 |
MeshSr/onetswitch45 | ons45-app52-ref_ofshw/vivado/onets_7045_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/wildcard_counter.v | 4,299 | module MODULE1
parameter VAR3=12,
parameter VAR5=16,
parameter VAR11=4
)
(
input clk,
input reset,
output VAR14,
input [VAR3-1:0]VAR4,
input VAR18,
input VAR12,
input [VAR11-1:0]VAR1,
input [VAR11-1:0] VAR7,
input VAR16,
output reg [31:0]VAR19,
output reg [31:0]VAR17
);
begin
reg [31:0]VAR20[VAR5-1:0];
reg [31:0]VAR2 [... | lgpl-2.1 |
javierbrito29/papiGB | rtl/interrupts.v | 2,411 | module MODULE1
(
input wire VAR11,
input wire VAR7,
input wire VAR9,
input wire [3:0] VAR13, input wire [7:0] VAR3,
output wire[7:0] VAR2,
output wire[7:0] VAR6,
input wire [7:0] VAR5,
output reg [7:0] VAR10
);
wire VAR8;
assign VAR8 = (VAR9 & VAR13 == 4'h0) ? 1'b1 : 1'b0;
VAR16 # ( 8 )VAR15(
VAR11, VAR7 , VAR8 , VAR3,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn_4.v | 2,374 | module MODULE2 (
VAR4 ,
VAR9,
VAR6 ,
VAR10 ,
VAR2 ,
VAR5 ,
VAR1 ,
VAR8
);
output VAR4 ;
input VAR9;
input VAR6 ;
input VAR10 ;
input VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR8 ;
VAR3 VAR7 (
.VAR4(VAR4),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.behavioral.pp.v | 1,863 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4 ,
VAR9,
VAR7,
VAR10 ,
VAR13
);
output VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR9;
input VAR7;
input VAR10 ;
input VAR13 ;
wire VAR12 ;
wire VAR11;
VAR2 VAR3 (VAR12 , VAR1, VAR9, VAR7 );
VAR2 VAR8 (VAR11, VAR4, VAR9, VAR7 );
notif1 VAR6 (VAR5 , VAR12, VAR11);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inputiso0p/sky130_fd_sc_hdll__inputiso0p.blackbox.v | 1,360 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR3
);
output VAR2 ;
input VAR7 ;
input VAR3;
supply1 VAR5;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.symbol.v | 1,433 | module MODULE1 (
input VAR1,
input VAR4,
input VAR2,
input VAR5,
input VAR3,
output VAR9
);
supply1 VAR8;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and4bb/sky130_fd_sc_hdll__and4bb.functional.v | 1,424 | module MODULE1 (
VAR5 ,
VAR6,
VAR3,
VAR8 ,
VAR1
);
output VAR5 ;
input VAR6;
input VAR3;
input VAR8 ;
input VAR1 ;
wire VAR4 ;
wire VAR7;
nor VAR10 (VAR4 , VAR6, VAR3 );
and VAR9 (VAR7, VAR4, VAR8, VAR1 );
buf VAR2 (VAR5 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.pp.symbol.v | 1,228 | module MODULE1 (
input VAR4 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvp/sky130_fd_sc_hd__einvp.pp.blackbox.v | 1,289 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR1 ,
VAR4,
VAR7,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR4;
input VAR7;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
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