repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
cafe-alpha/wascafe | v13/wasca_10m08scv4k_no_spi_20190420/wasca/synthesis/submodules/wasca_uart_0.v | 27,687 | module MODULE3 (
VAR99,
VAR18,
clk,
VAR16,
VAR21,
VAR8,
VAR30,
VAR48,
VAR71,
VAR56,
VAR1,
VAR44,
VAR11
)
;
output VAR56;
output VAR1;
output VAR44;
output VAR11;
input [ 15: 0] VAR99;
input VAR18;
input clk;
input VAR16;
input VAR21;
input VAR8;
input VAR30;
input [ 7: 0] VAR48;
input VAR71;
reg VAR45;
reg [ 15: 0] VAR... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_rams/dpram_256x32.v | 9,496 | module MODULE1 (
VAR53,
VAR7,
VAR14,
VAR20,
VAR9,
VAR43,
VAR50);
input [31:0] VAR53;
input [7:0] VAR7;
input VAR14;
input [7:0] VAR20;
input VAR9;
input VAR43;
output [31:0] VAR50;
wire [31:0] VAR27;
wire [31:0] VAR50 = VAR27[31:0];
VAR17 VAR29 (
.VAR24 (VAR43),
.VAR23 (VAR9),
.VAR54 (VAR14),
.VAR39 (VAR20),
.VAR38 (VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr_12.v | 2,118 | module MODULE1 (
VAR3 ,
VAR6,
VAR5 ,
VAR1 ,
VAR4
);
input VAR3 ;
input VAR6;
input VAR5 ;
input VAR1 ;
input VAR4 ;
VAR2 VAR7 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR3 ;
supply1 VAR6;
supply0 VAR5 ;
supply1 VAR1 ;
supply0 VAR4 ;
VAR2 VAR7 ();
endmodul... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2.behavioral.v | 1,684 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR11 ,
VAR7,
VAR10
);
output VAR8 ;
input VAR5 ;
input VAR11 ;
input VAR7;
input VAR10;
wire VAR1 ;
wire VAR6;
nand VAR2 (VAR1 , VAR11, VAR5 );
VAR3 VAR9 (VAR6, VAR1, VAR7, VAR10);
buf VAR4 (VAR8 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgndnovpb/sky130_fd_sc_ls__tapvgndnovpb.behavioral.v | 1,164 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/FIFO_image_filter_p_dst_cols_V_channel.v | 3,019 | module MODULE1 (
clk,
VAR16,
VAR22,
VAR21,
VAR13);
parameter VAR10 = 32'd12;
parameter VAR8 = 32'd2;
parameter VAR23 = 32'd3;
input clk;
input [VAR10-1:0] VAR16;
input VAR22;
input [VAR8-1:0] VAR21;
output [VAR10-1:0] VAR13;
reg[VAR10-1:0] VAR1 [0:VAR23-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR22)
begin
f... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap_2.v | 1,877 | module MODULE2 (
VAR6,
VAR5,
VAR2 ,
VAR3
);
input VAR6;
input VAR5;
input VAR2 ;
input VAR3 ;
VAR4 VAR1 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR6;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR3 ;
VAR4 VAR1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.pp.blackbox.v | 1,295 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1 ,
VAR4,
VAR2,
VAR5 ,
VAR7
);
output VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR7 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/fmlmeter/rtl/fmlmeter.v | 1,890 | module MODULE1 #(
parameter VAR5 = 4'h0
) (
input VAR13,
input VAR8,
input [13:0] VAR4,
input VAR11,
input [31:0] VAR2,
output reg [31:0] VAR10,
input VAR12,
input VAR14
);
reg VAR3;
reg VAR6;
always @(posedge VAR13) begin
VAR3 <= VAR12;
VAR6 <= VAR14;
end
reg en; reg [31:0] VAR7; reg [31:0] VAR1;
wire VAR9 = VAR4[13:1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn.functional.v | 1,942 | module MODULE1 (
VAR15 ,
VAR4 ,
VAR11,
VAR2 ,
VAR3
);
output VAR15 ;
output VAR4 ;
input VAR11;
input VAR2 ;
input VAR3 ;
wire VAR12 ;
wire VAR5;
wire VAR13 ;
not VAR6 (VAR12 , VAR11 );
not VAR10 (VAR5, VAR3 );
VAR14 VAR7 VAR8 (VAR13 , VAR2, VAR5, VAR12);
buf VAR9 (VAR15 , VAR13 );
not VAR1 (VAR4 , VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver/sky130_fd_sc_lp__busdriver.behavioral.pp.v | 1,885 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5,
VAR7,
VAR13,
VAR4 ,
VAR12
);
output VAR2 ;
input VAR1 ;
input VAR5;
input VAR7;
input VAR13;
input VAR4 ;
input VAR12 ;
wire VAR8 ;
wire VAR6;
VAR9 VAR3 (VAR8 , VAR1, VAR7, VAR13 );
VAR9 VAR10 (VAR6, VAR5, VAR7, VAR13 );
bufif0 VAR11 (VAR2 , VAR8, VAR6);
endmodule | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/picoblze/uart_clock.v | 10,062 | module MODULE1
( VAR23,
VAR27,
VAR9,
clk);
output VAR23;
input VAR27;
output VAR9;
input clk;
wire VAR23;
wire VAR27;
reg VAR9;
wire clk;
wire [9:0] address;
wire [17:0] VAR15;
wire [7:0] VAR2;
wire [7:0] VAR33;
reg [7:0] VAR13;
wire VAR26;
wire VAR25;
reg interrupt;
wire VAR16;
wire [7:0] VAR29;
reg [6:0] VAR3;
reg VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_1.behavioral.pp.v | 1,069 | module MODULE1( VAR4, VAR3 );
inout VAR4, VAR3;
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3));
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/endcap/gf180mcu_fd_sc_mcu9t5v0__endcap.behavioral.pp.v | 1,069 | module MODULE1( VAR2, VAR4 );
inout VAR2, VAR4;
VAR5 VAR3(.VAR2(VAR2),.VAR4(VAR4));
VAR5 VAR1(.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
mlab/pvs | hdl_harness/pace_catcher.v | 2,090 | module MODULE1
(
VAR7,
VAR6,
VAR8,
VAR3
);
input VAR7;
input VAR6;
input VAR8;
output VAR3;
parameter VAR2 = 15;
parameter VAR4 = 0;
parameter VAR1 = 1;
reg[15:0] VAR5 = 0;
reg state = 0;
always @(posedge VAR7) begin
case(state)
VAR4:
begin
state <= (VAR8) ? VAR1 : VAR4;
end
VAR1:
begin
state <= (VAR5 >= VAR2) ? VAR4 :... | gpl-3.0 |
SymbiFlow/fpga-tool-perf | src/axi-lite-reg/AxiPeriph.v | 32,503 | module MODULE1( input VAR24, input reset, input [4:0] VAR26, input VAR92, output VAR56, input [11:0] VAR6, input [31:0] VAR113, input VAR63, output VAR47, output VAR39, input VAR14, output [11:0] VAR104, input [4:0] VAR82, input VAR15, output VAR102, input [11:0] VAR86, output [31:0] VAR37, output VAR106, input VAR116,... | isc |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_div_exp_dp.v | 8,117 | module MODULE1 (
VAR11,
VAR29,
VAR52,
VAR21,
VAR57,
VAR53,
VAR13,
VAR46,
VAR12,
VAR34,
VAR10,
VAR14,
VAR20,
VAR1,
VAR9,
VAR43,
VAR30,
VAR47,
VAR40,
VAR25,
VAR42,
VAR5,
VAR28,
VAR39,
VAR32,
VAR36,
VAR6,
VAR17,
VAR41,
VAR4,
VAR19,
VAR16,
VAR55,
VAR59,
VAR37,
VAR15,
VAR45,
VAR60,
VAR8,
VAR61,
VAR24,
VAR44
);
input [62:52]... | gpl-2.0 |
rkrajnc/minimig-mist | rtl/minimig/paula_uart.v | 7,192 | module MODULE1 (
input wire clk,
input wire VAR13,
input wire reset,
input wire [ 8-1:0] VAR14,
input wire [ 16-1:0] VAR1,
output wire [ 16-1:0] VAR15,
input wire VAR34,
input wire VAR16,
output wire VAR17,
output wire VAR43,
output wire VAR41,
input wire VAR18
);
localparam VAR10 = 9'h030;
localparam VAR42 = 9'h018;
l... | gpl-3.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/proj_pointer_basic_hls_ip_integ/proj_pointer_basic_hls_ip_integ.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_2/design_1_processing_system7_0_2_stub.v | 5,171 | module MODULE1(VAR40, VAR61,
VAR35, VAR8, VAR37, VAR42,
VAR64, VAR13, VAR34, VAR2, VAR47,
VAR62, VAR17, VAR46, VAR4, VAR11,
VAR41, VAR23, VAR36, VAR51, VAR44,
VAR14, VAR45, VAR54, VAR63, VAR43,
VAR1, VAR18, VAR31, VAR57, VAR48,
VAR26, VAR19, VAR15, VAR28,
VAR16, VAR49, VAR29, VAR7, VAR59,
VAR38, VAR5, VAR22, VAR6, VAR3... | mit |
donnaware/AGC | rtl/de0/modules/ng_PRM.v | 6,791 | module MODULE1(
input VAR38, input [100:0] VAR49, input [ 5:0] VAR24, input [ 15:0] VAR34, input [ 15:0] VAR51, input [ 15:0] VAR13, input [ 15:0] VAR5, input [ 15:0] VAR15, input [ 15:0] VAR19, input [ 15:0] VAR18, input [ 15:0] VAR21, input [ 15:0] VAR20, input [ 15:0] VAR43, input [ 15:0] VAR10, output [ 15:0] VAR27... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.functional.v | 1,342 | module MODULE1 (
VAR2,
VAR5
);
output VAR2;
input VAR5;
wire VAR1;
buf VAR3 (VAR1, VAR5 );
buf VAR4 (VAR2 , VAR1 );
endmodule | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/ram_block.v | 3,395 | module MODULE1 (
clk,
VAR8,
VAR44,
VAR19,
VAR21,
VAR22
);
parameter VAR35 = 36;
parameter VAR23 = 7;
input clk;
input [VAR35-1:0] VAR8;
input [VAR23-1:0] VAR44;
input [VAR23-1:0] VAR19;
input VAR21;
output [VAR35-1:0] VAR22;
VAR50 VAR61 (
.VAR2 (VAR21),
.VAR52 (clk),
.VAR59 (VAR19),
.VAR26 (VAR44),
.VAR53 (VAR8),
.VAR3... | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/amber23/a23_barrel_shift.v | 16,319 | module MODULE1 (
input [31:0] VAR11,
input VAR7,
input [7:0] VAR9, input VAR5, input [1:0] VAR13,
output [31:0] VAR4,
output VAR12
);
wire [32:0] VAR8;
wire [32:0] VAR1;
wire [32:0] VAR3;
wire [32:0] VAR15;
assign VAR8 = VAR5 ? {VAR7, VAR11 } :
VAR9 == 8'VAR6 0 ? {VAR7, VAR11 } : VAR9 == 8'VAR6 1 ? {VAR11[31], VAR11[30... | lgpl-3.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/v_axi4s_vid_out_v3_0/49ac95ae/hdl/verilog/v_axi4s_vid_out_v3_0_out_sync.v | 16,855 | module MODULE1 #(
parameter VAR38 = 10, parameter VAR5 = 16,
parameter VAR47 = 0 )
(
input wire VAR46, input wire rst , input wire VAR10,
input wire VAR41, input wire VAR36, input wire VAR30, input wire [VAR38 -1:0] VAR23, input wire VAR12, input wire VAR1 , input wire VAR32, output reg VAR43, output reg VAR14,
input w... | gpl-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_sb.v | 7,149 | module MODULE1(
clk, rst,
VAR15,
VAR23, VAR21, VAR29, VAR28, VAR19, VAR37, VAR3,
VAR42, VAR24, VAR11,
VAR41, VAR45, VAR5, VAR43, VAR16, VAR9, VAR2,
VAR4, VAR35, VAR14
);
parameter VAR36 = VAR18;
parameter VAR17 = VAR18;
input clk; input rst;
input VAR15;
input [VAR36-1:0] VAR23; input [VAR17-1:0] VAR21; input VAR29; in... | mit |
Jbag/Uart_zhixin | design/Uart_rx.v | 2,435 | module MODULE1(
input clk, input VAR9, input VAR10, input [3:0] VAR4, input VAR2, output VAR8, output reg VAR6, output reg [7:0] VAR5 );
reg VAR3,VAR7;
always @(posedge clk or negedge VAR9)
if(!VAR9)
begin
VAR3 <= 1'b1;
VAR7 <= 1'b1;
end
else
begin
VAR3 <= VAR10;
VAR7 <= VAR3;
end
assign VAR8 = VAR7 & (~VAR3);
reg [7:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfsbp/sky130_fd_sc_hvl__sdfsbp.pp.symbol.v | 1,527 | module MODULE1 (
input VAR4 ,
output VAR5 ,
output VAR10 ,
input VAR8,
input VAR2 ,
input VAR7 ,
input VAR6 ,
input VAR3 ,
input VAR1 ,
input VAR11 ,
input VAR9
);
endmodule | apache-2.0 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/wasca_altpll_0.v | 10,902 | module MODULE1
(
VAR10,
VAR4,
VAR5,
VAR3) ;
input VAR10;
input VAR4;
input [0:0] VAR5;
output [0:0] VAR3;
tri0 VAR10;
tri1 VAR4;
reg [0:0] VAR8;
reg [0:0] VAR1;
reg [0:0] VAR7;
wire VAR6;
wire VAR2;
wire VAR9; | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b.functional.v | 1,381 | module MODULE1 (
VAR5 ,
VAR6,
VAR3 ,
VAR8
);
output VAR5 ;
input VAR6;
input VAR3 ;
input VAR8 ;
wire VAR1 ;
wire VAR4;
not VAR7 (VAR1 , VAR6 );
and VAR9 (VAR4, VAR8, VAR1, VAR3 );
buf VAR2 (VAR5 , VAR4 );
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_qpll_wrapper.v | 29,184 | module MODULE1 #
(
parameter VAR29 = "VAR108", parameter VAR55 = "VAR110", parameter VAR22 = "3.0", parameter VAR42 = "VAR131", parameter VAR95 = 0
)
(
input VAR40,
input VAR94,
output VAR78,
output VAR71,
output VAR81,
input VAR103,
input VAR34,
input VAR8,
input [ 7:0] VAR112,
input VAR130,
input [15:0] VAR118,
input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_4.v | 2,583 | module MODULE2 (
VAR7 ,
VAR9 ,
VAR10 ,
VAR4 ,
VAR1 ,
VAR3,
VAR11 ,
VAR5 ,
VAR8 ,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR3;
input VAR11 ;
input VAR5 ;
input VAR8 ;
input VAR2 ;
VAR6 VAR12 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/16-way_4-parallel/src/vivado_ip_dram/dram.v | 6,630 | module MODULE1 (
inout [63:0] VAR21,
inout [7:0] VAR24,
inout [7:0] VAR19,
output [15:0] VAR31,
output [2:0] VAR10,
output VAR28,
output VAR2,
output VAR11,
output VAR20,
output [0:0] VAR40,
output [0:0] VAR1,
output [0:0] VAR4,
output [0:0] VAR37,
output [7:0] VAR25,
output [0:0] VAR29,
input VAR30,
input VAR14,
input... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2bb2o/sky130_fd_sc_hd__a2bb2o.blackbox.v | 1,454 | module MODULE1 (
VAR4 ,
VAR3,
VAR1,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR3;
input VAR1;
input VAR5 ;
input VAR8 ;
supply1 VAR7;
supply0 VAR9;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.functional.v | 1,293 | module MODULE1 (
VAR6,
VAR4,
VAR1
);
output VAR6;
input VAR4;
input VAR1;
wire VAR3;
xor VAR2 (VAR3, VAR1, VAR4 );
buf VAR5 (VAR6 , VAR3 );
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_Video_DMA.v | 9,423 | module MODULE1 (
clk,
reset,
VAR32,
VAR14,
VAR28,
VAR18,
VAR24,
VAR9,
VAR20,
VAR17,
VAR19,
VAR4,
VAR31,
VAR10,
VAR38,
VAR12,
VAR23,
VAR29
);
parameter VAR26 = 15; parameter VAR11 = 0; parameter VAR40 = 320; parameter VAR7 = 240;
parameter VAR8 = 16; parameter VAR42 = 8; parameter VAR41 = 7;
parameter VAR39 = 15;
parame... | gpl-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CORESPI/4.2.116/rtl/vlog/core/spi_rf.v | 11,295 | module MODULE1 # (
parameter VAR6 = 8
)( input VAR3,
input VAR4,
input [6:0] VAR19,
input VAR5,
input VAR24,
input VAR17,
input [VAR6-1:0] VAR36,
output [VAR6-1:0] VAR11,
output interrupt,
input VAR34,
input VAR18,
input VAR9,
input VAR40,
input VAR23,
input VAR32,
input VAR12,
input VAR20,
input VAR44,
input VAR42,
in... | mit |
sergev/vak-opensource | hardware/verilator/t_inst.v | 3,655 | module MODULE1(
VAR30,
clk, VAR70
);
input clk;
input VAR70;
output VAR30; reg VAR30; VAR19 VAR30 = 0;
genvar VAR42;
wire VAR60; wire VAR28;
integer VAR20; reg VAR58,VAR68,VAR57,VAR62,VAR63;
wire VAR21,VAR46,VAR34,VAR1,VAR45;
wire VAR43,VAR72,VAR55,VAR47,VAR2;
reg [7:0] VAR51,VAR64,VAR71,VAR37,VAR8;
wire [7:0] VAR61,VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3/sky130_fd_sc_hd__nor3.behavioral.v | 1,405 | module MODULE1 (
VAR2,
VAR9,
VAR3,
VAR6
);
output VAR2;
input VAR9;
input VAR3;
input VAR6;
supply1 VAR4;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR10 ;
wire VAR1;
nor VAR11 (VAR1, VAR6, VAR9, VAR3 );
buf VAR8 (VAR2 , VAR1 );
endmodule | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/crash_pixel/crash_pixel_stub.v | 1,301 | module MODULE1(VAR1, VAR2, VAR5, VAR4, VAR3)
;
input VAR1;
input [0:0]VAR2;
input [11:0]VAR5;
input [11:0]VAR4;
output [11:0]VAR3;
endmodule | gpl-3.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/ip/Binary_VGA_Controller/hdl/VGA_Controller.v | 4,298 | module MODULE1( VAR30,
VAR9,
VAR20,
VAR29,
VAR6,
VAR10,
VAR21,
VAR15,
VAR25,
VAR36,
VAR37,
VAR40,
VAR34,
VAR38,
VAR11,
VAR13,
VAR4,
VAR3,
VAR14,
VAR7,
VAR1,
VAR2 );
output reg [19:0] VAR36;
output reg [9:0] VAR37;
output reg [9:0] VAR40;
input [3:0] VAR30;
input [9:0] VAR9;
input [9:0] VAR20;
input [9:0] VAR29;
input [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.behavioral.pp.v | 1,926 | module MODULE1 (
VAR12,
VAR7,
VAR5 ,
VAR4 ,
VAR13 ,
VAR6
);
input VAR12;
input VAR7;
output VAR5 ;
input VAR4 ;
input VAR13 ;
input VAR6 ;
wire VAR1 ;
wire VAR8 ;
wire VAR14;
or VAR11 (VAR1 , VAR13, VAR4 );
and VAR3 (VAR8 , VAR1, VAR6 );
VAR9 VAR2 (VAR14, VAR8, VAR12, VAR7);
buf VAR10 (VAR5 , VAR14 );
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_sysid_qsys_0.v | 1,424 | module MODULE1 (
address,
VAR1,
VAR3,
VAR2
)
;
output [ 31: 0] VAR2;
input address;
input VAR1;
input VAR3;
wire [ 31: 0] VAR2;
assign VAR2 = address ? 1425077675 : 0;
endmodule | gpl-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab4/Lab4-Project/BCD_Segment_Decoder.v | 2,164 | module MODULE1
parameter VAR4 = 1
)
(
input [VAR4*4-1:0] VAR2,
output reg [VAR4*7-1:0] VAR3,
input VAR1
);
begin
begin
begin | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/Booth_Multipliers-master/Src/Booth_Multiplier_1xA.v | 6,534 | module MODULE1 #(
parameter VAR9 = 16 )(
input VAR4, input VAR8,
input VAR2, input [(VAR9 - 1):0] VAR14, input [(VAR9 - 1):0] VAR17, output reg VAR13, output reg [(2*VAR9 - 1):0] VAR7 );
reg [4:0] VAR6; reg [1:0] VAR5; reg VAR3; reg [VAR9:0] VAR10; reg [VAR9:0] VAR15; reg VAR16; reg [VAR9:0] VAR11; wire [VAR9:0] VAR12;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.pp.blackbox.v | 1,403 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR2 ,
VAR4 ,
VAR6,
VAR1
);
output VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR2 ;
input VAR4 ;
input VAR6;
input VAR1;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/circ_buffer.v | 7,191 | module MODULE1 #
(
parameter VAR34 = 100,
parameter VAR20 = 5, parameter VAR21 = 1
)
(
output[VAR21-1:0] VAR8,
input [VAR21-1:0] VAR16,
input VAR27,
input VAR25,
input rst
);
localparam VAR12 = (VAR20-1)/2;
reg VAR35;
reg [VAR12:0] VAR9;
reg [2:0] VAR5;
reg VAR19;
reg VAR4;
reg [2:0] VAR28;
always @(posedge VAR27 or po... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N16_M4_P4_syn.v | 3,363 | module MODULE1 ( VAR24, VAR3, VAR56 );
input [15:0] VAR24;
input [15:0] VAR3;
output [16:0] VAR56;
wire VAR36, VAR61, VAR68, VAR19, VAR71,
VAR38, VAR48, VAR31, VAR11, VAR5,
VAR53, VAR63, VAR80, VAR30, VAR51,
VAR4, VAR35, VAR9, VAR74, VAR79, VAR17, VAR55, VAR1, VAR62, VAR28;
VAR25 VAR57 ( .VAR59(VAR24[1]), .VAR34(VAR3[1... | gpl-3.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/sys_aux_module/sys_aux_module.v | 6,235 | module MODULE1(
VAR7 , VAR6 , VAR10 , VAR8 );
input VAR7 ; input VAR6 ; input [07:00] VAR10 ; output [15:00] VAR8 ;
reg [09:00] VAR2 ; wire VAR5 ;
wire VAR11 ;
wire [07:00] VAR9 ;
wire [07:00] VAR4 ;
assign VAR5 = VAR7 ; assign VAR11 = VAR6 ; assign VAR9[07:00] = VAR10 ; assign VAR8[07:00] = VAR4 ; assign VAR8[15:08] =... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.symbol.v | 1,294 | module MODULE1 (
input VAR6,
output VAR3
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
mshaklunov/usb_devtrsac | rtl/usb_encoder.v | 5,134 | module MODULE1 (
input clk,
input VAR14,
input VAR6,
output reg VAR35,
output reg VAR18,
output reg VAR19,
input VAR37,
input VAR21,
input VAR28,
output VAR34,
input VAR22,
input VAR16
);
wire VAR8;
wire VAR7;
wire VAR4;
reg VAR3;
wire VAR10;
reg[17:0] counter;
reg[2:0] VAR1;
reg[3:0] VAR12;
localparam VAR31=4'd0,
VAR2... | mit |
Huyuwei/tvm | vta/hardware/intel/scripts/de10_nano_top.v | 5,101 | module MODULE1(
input VAR23,
input VAR33,
input VAR34,
inout VAR45,
output [14: 0] VAR17,
output [ 2: 0] VAR11,
output VAR42,
output VAR21,
output VAR14,
output VAR32,
output VAR18,
output [ 3: 0] VAR1,
inout [31: 0] VAR24,
inout [ 3: 0] VAR7,
inout [ 3: 0] VAR31,
output VAR8,
output VAR29,
output VAR6,
input VAR30,
ou... | apache-2.0 |
chriswynnyk/american-put-verilog | american_put_cyclone/src/DE2_70_Default.v | 24,663 | module MODULE1
(
VAR163, VAR217, VAR164, VAR33, VAR83, VAR94, VAR24, VAR153, VAR175, VAR151, VAR36, VAR220, VAR184, VAR210, VAR169, VAR95, VAR84, VAR147, VAR55, VAR72, VAR126, VAR26, VAR11, VAR146, VAR42, VAR215, VAR93, VAR180, VAR165, VAR37, VAR201, VAR86, VAR207, VAR136, VAR100, VAR185, VAR212, VAR142, VAR159, VAR63,... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_MinMax1.v | 1,726 | module MODULE1
(
VAR1,
VAR7,
VAR6,
VAR4
);
input signed [17:0] VAR1; input signed [17:0] VAR7; input signed [17:0] VAR6; output signed [17:0] VAR4;
wire signed [17:0] VAR5 [0:2]; wire signed [17:0] VAR3 [0:1]; wire signed [17:0] VAR2;
assign VAR5[0] = VAR1;
assign VAR5[1] = VAR7;
assign VAR5[2] = VAR6;
assign VAR3[0] =... | gpl-3.0 |
alexforencich/xfcp | lib/eth/example/NetFPGA_SUME/fpga/rtl/fpga.v | 19,091 | module MODULE1 (
input wire VAR202,
input wire VAR197,
input wire [1:0] VAR61,
output wire [1:0] VAR119,
output wire [1:0] VAR234,
output wire [1:0] VAR227,
output wire [1:0] VAR68,
output wire [1:0] VAR225,
inout wire VAR263,
inout wire VAR306,
output wire VAR323,
input wire VAR107,
input wire VAR265,
output wire VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.behavioral.v | 2,065 | module MODULE1 (
VAR1 ,
VAR11,
VAR12,
VAR5 ,
VAR7 ,
VAR2,
VAR10
);
output VAR1 ;
input VAR11;
input VAR12;
input VAR5 ;
input VAR7 ;
input VAR2;
input VAR10;
wire VAR7 VAR13 ;
wire VAR7 VAR8 ;
wire VAR3 ;
wire VAR16;
nand VAR4 (VAR13 , VAR12, VAR11 );
or VAR17 (VAR8 , VAR7, VAR5 );
and VAR9 (VAR3 , VAR13, VAR8 );
VAR14... | apache-2.0 |
sigilance/tera-computer | src/memory.v | 1,279 | module MODULE1 (VAR3, VAR2);
output [7:0] VAR3;
input [7:0] VAR2;
reg [7:0] VAR1 [0:255];
assign VAR3 = VAR1[VAR2]; | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.behavioral.pp.v | 2,186 | module MODULE1 (
VAR6 ,
VAR20 ,
VAR16 ,
VAR13 ,
VAR4,
VAR8,
VAR3 ,
VAR9
);
output VAR6 ;
input VAR20 ;
input VAR16 ;
input VAR13 ;
input VAR4;
input VAR8;
input VAR3 ;
input VAR9 ;
wire VAR1 ;
wire VAR18 ;
wire VAR7 ;
wire VAR17 ;
wire VAR5;
or VAR19 (VAR1 , VAR16, VAR20 );
and VAR10 (VAR18 , VAR1, VAR13 );
and VAR11 (... | apache-2.0 |
SymbiFlow/symbiflow-arch-defs | vpr/primitives.v | 6,905 | module MODULE2 #(
parameter VAR3=4,
parameter VAR2={2**VAR3{1'b0}}
) (
input [VAR3-1:0] in,
output out
);
assign out = VAR2[in];
endmodule
module MODULE1 #(
parameter VAR4=1'b0
) (
input VAR5,
input VAR6,
output reg VAR1
); | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.symbol.v | 1,381 | module MODULE1 (
input VAR2,
input VAR3,
input VAR10,
input VAR6,
input VAR1,
output VAR5
);
supply1 VAR9;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b.pp.symbol.v | 1,338 | module MODULE1 (
input VAR6 ,
input VAR2 ,
input VAR3 ,
input VAR4 ,
output VAR7 ,
input VAR8 ,
input VAR1,
input VAR5,
input VAR9
);
endmodule | apache-2.0 |
UA3MQJ/fpga-synth | modules/note_mono_array.v | 4,938 | module MODULE1(clk, rst, VAR7, VAR3, VAR17, VAR21, VAR9);
parameter VAR11 = 32;
parameter VAR5 = VAR11 - 1;
parameter VAR10 = (VAR11[7:7]==1'b1) ? 8 :
(VAR11[6:6]==1'b1) ? 7 :
(VAR11[5:5]==1'b1) ? 6 :
(VAR11[4:4]==1'b1) ? 5 :
(VAR11[3:3]==1'b1) ? 4 :
(VAR11[2:2]==1'b1) ? 3 :
(VAR11[1:1]==1'b1) ? 2 :
(VAR11[0:0]==1'b1) ... | gpl-3.0 |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_jsp_biu.v | 17,181 | module MODULE1
(
VAR3,
VAR40,
VAR92,
VAR75,
VAR69,
VAR58,
VAR81,
VAR98,
VAR20,
VAR95,
VAR35,
VAR9,
VAR82,
VAR107,
VAR89,
VAR16,
VAR11,
VAR53,
VAR5,
VAR83,
VAR74,
VAR30,
VAR54
);
input VAR3;
input VAR40;
input [7:0] VAR92; output [7:0] VAR75;
output [3:0] VAR58;
output [3:0] VAR69;
input VAR81;
input VAR98;
input VAR20;... | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/MicrofonoFIFO/Microfono.v | 1,498 | module MODULE1(clk, reset, VAR4, VAR8, VAR17, VAR24, VAR22, VAR5, VAR9, rd, wr, VAR27, VAR12);
input wire clk;
input wire reset;
input wire VAR4;
input wire VAR8;
output wire VAR17;
output wire VAR24;
input wire VAR22;
output wire VAR5;
output wire VAR9;
output wire rd;
output wire wr;
output wire VAR27;
output wire VA... | gpl-3.0 |
miamiasheep/nctu-dlab-99 | lab8/draw_symbols.v | 2,332 | module MODULE1(
input reset,
input [10:0] VAR10,
input [11:0] VAR5,
input VAR11,
input [8:0] VAR8,
input [8:0] VAR2,
output reg VAR9,
output reg VAR4,
output reg VAR6
);
wire [10:0] VAR3;
wire [11:0] VAR7;
assign VAR3 = (479-384)/2;
assign VAR7 = (639-384)/2;
wire VAR12;
wire [3:0] VAR1, VAR13;
reg [1:0] select;
always... | gpl-3.0 |
ProjectVault/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/trng/rtl/verilog/trng.v | 1,426 | module MODULE1 (
input clk,
input en,
output [7:0] VAR1
);
wire [7:0] VAR4, VAR3;
reg [7:0] VAR2, VAR5;
assign VAR4 = (en) ? ({ VAR4[6:0], VAR4[7] } ^ VAR4 ^ { VAR4[0], VAR4[7:1] } ^ 8'h80) : VAR4;
always @(posedge clk)
begin
VAR2 <= VAR4;
end
assign VAR3 = (VAR5 & 8'h96) ^ { VAR5[6:0], 1'b0 } ^ { 1'b0, VAR5[7:1] } ^ V... | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_cospi_s5.v | 1,184 | module MODULE1 (
enable,
VAR2,
VAR4,
VAR6);
input enable;
input VAR2;
input [31:0] VAR4;
output [31:0] VAR6;
wire [31:0] VAR8;
wire [31:0] VAR6 = VAR8[31:0];
VAR5 VAR7 (
.en (enable),
.VAR3(1'b0),
.clk(VAR2),
.VAR1(VAR4),
.VAR9(VAR8));
endmodule | mit |
ridecore/ridecore | src/fpga/dualport_ram.v | 1,814 | module MODULE1 #(
parameter VAR12 = 10,
parameter VAR9 = 2,
parameter VAR17 = 1024
)
(
input wire VAR7,
input wire [VAR12-1:0] VAR14,
output reg [VAR9-1:0] VAR2,
input wire [VAR9-1:0] VAR3,
input wire VAR1,
input wire VAR16,
input wire [VAR12-1:0] VAR5,
output reg [VAR9-1:0] VAR11,
input wire [VAR9-1:0] VAR6,
input wir... | bsd-3-clause |
Gurint/EPC-Gen2-RFID-Tag-Baseband-Processor | mem_if.v | 2,721 | module MODULE1
(
output reg VAR12,
output reg VAR5,
output reg [5:0]VAR7,
output VAR9,
input [18:0]addr,
input [15:0]VAR3,
input VAR11,
input VAR10
);
wire VAR2;
reg VAR4;
reg VAR1;
reg [3:0]VAR8;
reg [5:0]VAR6;
assign VAR9 = (addr == 19'h0)? 1'b1 : 1'b0;
assign VAR2 = ~VAR11;
always@(posedge VAR11 or negedge VAR10) be... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxbp/sky130_fd_sc_hs__edfxbp.behavioral.v | 2,074 | module MODULE1 (
VAR18 ,
VAR3 ,
VAR16 ,
VAR4 ,
VAR7 ,
VAR6,
VAR17
);
output VAR18 ;
output VAR3 ;
input VAR16 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR17;
wire VAR12 ;
reg VAR15 ;
wire VAR1 ;
wire VAR10 ;
wire VAR8;
wire VAR11 ;
wire VAR9 ;
VAR5 VAR14 (VAR12 , VAR1, VAR8, VAR10, VAR15, VAR6, VAR17);
assign VAR1... | apache-2.0 |
gralco/mojo-ide | Mojo IDE/base/mojo-v3/source/serial_tx.v | 1,935 | module MODULE1 #(
parameter VAR24 = 50,
parameter VAR22 = 6
)(
input clk,
input rst,
output VAR21,
input VAR6,
output VAR20,
input [7:0] VAR15,
input VAR23
);
localparam VAR3 = 2;
localparam VAR12 = 2'd0,
VAR13 = 2'd1,
VAR4 = 2'd2,
VAR18 = 2'd3;
reg [VAR22-1:0] VAR2, VAR8;
reg [2:0] VAR25, VAR14;
reg [7:0] VAR26, VAR5;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai.behavioral.pp.v | 2,060 | module MODULE1 (
VAR6,
VAR3,
VAR8 ,
VAR4 ,
VAR10 ,
VAR17 ,
VAR12
);
input VAR6;
input VAR3;
output VAR8 ;
input VAR4 ;
input VAR10 ;
input VAR17 ;
input VAR12 ;
wire VAR12 VAR14 ;
wire VAR12 VAR13 ;
wire VAR16 ;
wire VAR7;
nor VAR2 (VAR14 , VAR17, VAR12 );
nor VAR9 (VAR13 , VAR4, VAR10 );
or VAR1 (VAR16 , VAR13, VAR14 ... | apache-2.0 |
GLADICOS/AES128 | rtl/control_unit.v | 15,576 | module MODULE1
(
output reg [ 2:0] VAR77,
output reg [ 1:0] VAR22,
output reg [ 1:0] VAR11,
output reg [ 1:0] VAR63,
output reg [ 3:0] VAR52,
output reg [ 3:0] VAR29,
output [ 3:0] VAR100,
output reg VAR20,
output reg VAR56,
output reg VAR75,
output reg VAR102,
output reg VAR47,
output reg VAR12,
output VAR91,
output V... | lgpl-3.0 |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_SMP_HPS.v | 7,933 | module MODULE1 #(
parameter VAR15 = 0,
parameter VAR2 = 0
) (
output wire VAR13, input wire VAR31, output wire [11:0] VAR3, output wire [20:0] VAR56, output wire [3:0] VAR24, output wire [2:0] VAR39, output wire [1:0] VAR19, output wire [1:0] VAR43, output wire [3:0] VAR18, output wire [2:0] VAR51, output wire VAR37, i... | gpl-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/mem_window/mem_window.v | 2,569 | module MODULE1 (
clk,
reset,
VAR3,
VAR16,
VAR13,
VAR10,
VAR27,
VAR19,
VAR24,
VAR33,
VAR14,
VAR5,
VAR20,
VAR23,
VAR11,
VAR21,
VAR32,
VAR18,
VAR1,
VAR9,
VAR15,
VAR26,
VAR7
);
parameter VAR28 = 20;
parameter VAR17 = 32;
parameter VAR22 = 32;
parameter VAR8 = 1;
parameter VAR4 = 32;
localparam VAR30 = VAR2(VAR22);
localpar... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.pp.symbol.v | 1,351 | module MODULE1 (
input VAR5 ,
input VAR1 ,
input VAR7 ,
input VAR3 ,
output VAR8 ,
input VAR6 ,
input VAR2,
input VAR4,
input VAR9
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/ccx2mb_v1_00_a/hdl/verilog/mb2cpx_sm.v | 6,431 | module MODULE1 (
VAR18,
VAR26,
VAR15,
VAR28,
VAR1,
VAR27,
VAR23,
VAR29
);
parameter VAR19 = (((VAR14+3-1)/VAR22)+1);
parameter VAR7 = (VAR22 * VAR19) -
(VAR4+3);
parameter [2:0] VAR25 = VAR19 - 2;
parameter VAR8 = 0,
VAR17 = 1,
VAR30 = 2;
parameter VAR31 = 3'b001,
VAR24 = 3'b010,
VAR11 = 3'b100;
output VAR18;
output VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrtn/sky130_fd_sc_hd__sdfrtn.behavioral.pp.v | 2,993 | module MODULE1 (
VAR13 ,
VAR25 ,
VAR4 ,
VAR24 ,
VAR8 ,
VAR14,
VAR27 ,
VAR31 ,
VAR32 ,
VAR26
);
output VAR13 ;
input VAR25 ;
input VAR4 ;
input VAR24 ;
input VAR8 ;
input VAR14;
input VAR27 ;
input VAR31 ;
input VAR32 ;
input VAR26 ;
wire VAR30 ;
wire VAR12 ;
wire VAR28 ;
wire VAR7 ;
reg VAR20 ;
wire VAR33 ;
wire VAR23 ... | apache-2.0 |
funningboy/Verilog-Pli | example/hello.v | 1,407 | module MODULE1; | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/iface/ip/unpipeline/unpipeline.v | 1,333 | module MODULE1 #
(
parameter VAR20 = 256,
parameter VAR5 = 26,
parameter VAR1 = VAR5+VAR7(VAR20/8),
parameter VAR11 = 1,
parameter VAR4 = VAR20,
parameter VAR6 = 64
)
(
input clk,
input VAR17,
input [VAR5-1:0] VAR15, input [VAR20-1:0] VAR8,
input VAR9,
input VAR13,
input [VAR11-1:0] VAR10,
input [VAR4-1:0] VAR19,
outpu... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_16.behavioral.pp.v | 1,187 | module MODULE1( VAR3, VAR2, VAR5, VAR4 );
input VAR3;
inout VAR5, VAR4;
output VAR2;
VAR1 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR7(.VAR3(VAR3),.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/bus/bus_arbiter.v | 9,681 | module MODULE1(
input wire clk , input wire reset , input wire VAR4 , output reg VAR14 , input wire VAR17 , output reg VAR15 , input wire VAR7 , output reg VAR3 , input wire VAR6 , output reg VAR18 );
reg [01:00] VAR9 ;
always @(*) begin : VAR10
VAR14 = VAR2;
VAR15 = VAR2;
VAR3 = VAR2;
VAR18 = VAR2;
case(VAR9)
VAR14 = ... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/controller/bank_mach.v | 31,025 | module MODULE1 #
(
parameter VAR5 = 100,
parameter VAR6 = "VAR105",
parameter VAR7 = 3,
parameter VAR35 = 2,
parameter VAR26 = "8",
parameter VAR165 = 12,
parameter VAR178 = 4,
parameter VAR80 = 5,
parameter VAR2 = 8,
parameter VAR167 = "VAR68",
parameter VAR42 = "VAR125",
parameter VAR141 = "VAR125",
parameter VAR101 ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxbp/sky130_fd_sc_hd__sdfxbp.blackbox.v | 1,377 | module MODULE1 (
VAR2 ,
VAR9,
VAR5,
VAR3 ,
VAR7,
VAR10
);
output VAR2 ;
output VAR9;
input VAR5;
input VAR3 ;
input VAR7;
input VAR10;
supply1 VAR4;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_button_pio/altera_avalon_pio_171/synth/ghrd_10as066n2_button_pio_altera_avalon_pio_171_3t26uui.v | 4,807 | module MODULE1 (
address,
VAR14,
clk,
VAR12,
VAR10,
VAR13,
VAR9,
irq,
VAR1
)
;
output irq;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR14;
input clk;
input [ 3: 0] VAR12;
input VAR10;
input VAR13;
input [ 31: 0] VAR9;
wire VAR3;
reg [ 3: 0] VAR11;
reg [ 3: 0] VAR15;
wire [ 3: 0] VAR8;
reg [ 3: 0] VAR7;
wire V... | mit |
ckdur/mriscv_vivado_arty | mriscv_vivado.srcs/sources_1/new/AXI_DDR2.v | 4,974 | module MODULE1(
input VAR61, input VAR17, input VAR64,
input VAR67,
output VAR83,
input [32-1:0] VAR49,
input [3-1:0] VAR59,
input VAR35,
output VAR82,
input [32-1:0] VAR21,
input [4-1:0] VAR25,
output VAR65,
input VAR81,
input VAR22,
output VAR16,
input [32-1:0] VAR53,
input [3-1:0] VAR29,
output VAR11,
input VAR60,
o... | mit |
sabertazimi/hust-lab | verilog/labs/lab3/src/counters_8bit_with_T_ff.v | 1,533 | module MODULE1(
input VAR12,
input VAR3,
input VAR11,
output [7:0] VAR7
);
VAR4 VAR6 (.VAR12(VAR12), .VAR9(VAR3), .VAR14(VAR11), .VAR7(VAR7[0]));
VAR4 VAR2 (.VAR12(VAR12), .VAR9(VAR3 & VAR7[0]), .VAR14(VAR11), .VAR7(VAR7[1]));
VAR4 VAR8 (.VAR12(VAR12), .VAR9(VAR3 & VAR7[0] & VAR7[1]), .VAR14(VAR11), .VAR7(VAR7[2]));
VA... | mit |
sam-falvo/kestrel | cores/KCP53K/cpu2/rtl/verilog/decode.v | 5,411 | module MODULE1(
input VAR37,
input VAR7,
input [31:0] VAR34,
input VAR20,
input [63:0] VAR29,
input [63:0] VAR13,
input [4:0] VAR19,
input [4:0] VAR26,
input [63:0] VAR39,
input [63:0] VAR40,
output [63:0] VAR28,
output [63:0] VAR6,
output VAR22,
output VAR25,
output VAR14,
output VAR21,
output VAR35,
output VAR16,
out... | mpl-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkRISCV_MBox.v | 31,258 | module MODULE1(VAR105,
VAR103,
VAR164,
VAR37,
VAR35,
VAR104,
VAR89,
VAR145,
VAR106,
VAR31,
VAR52,
VAR183,
VAR28,
VAR128,
valid,
word);
input VAR105;
input VAR103;
input [3 : 0] VAR164;
input VAR37;
output VAR35;
input VAR104;
output VAR89;
input VAR145;
output VAR106;
input VAR31;
input [2 : 0] VAR52;
input [63 : 0] VA... | apache-2.0 |
drichmond/riffa | fpga/riffa_hdl/tx_port_buffer_64.v | 7,611 | module MODULE1 #(
parameter VAR3 = 9'd64,
parameter VAR16 = 512,
parameter VAR26 = VAR13((2**VAR13(VAR16))+1),
parameter VAR9 = 2,
parameter VAR38 = 2,
parameter VAR4 = 3,
parameter VAR43 = 3,
parameter VAR17 = 1
)
(
input VAR28,
input VAR29,
input VAR39, input [0:0] VAR46, input VAR47,
input [VAR3-1:0] VAR12, input VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlrtp/sky130_fd_sc_lp__srdlrtp.blackbox.v | 1,366 | module MODULE1 (
VAR6 ,
VAR4,
VAR8 ,
VAR10 ,
VAR5
);
output VAR6 ;
input VAR4;
input VAR8 ;
input VAR10 ;
input VAR5;
supply1 VAR7;
supply1 VAR9 ;
supply0 VAR2 ;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a22oi/sky130_fd_sc_hs__a22oi.functional.pp.v | 2,065 | module MODULE1 (
VAR17,
VAR16,
VAR7 ,
VAR10 ,
VAR9 ,
VAR4 ,
VAR14
);
input VAR17;
input VAR16;
output VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR4 ;
input VAR14 ;
wire VAR14 VAR13 ;
wire VAR14 VAR15 ;
wire VAR5 ;
wire VAR11;
nand VAR8 (VAR13 , VAR9, VAR10 );
nand VAR3 (VAR15 , VAR14, VAR4 );
and VAR12 (VAR5 , VAR13, VA... | apache-2.0 |
golfit/QcmCapBoardMain | CapBoardDecoder.v | 4,911 | module MODULE1(clk,VAR1,enable,VAR9,VAR6);
input clk; reg [3:0] VAR11; reg [3:0] VAR2;
input [5:0] VAR1;
reg [5:0] VAR4;
reg [5:0] VAR5;
reg [6:0] addr;
input enable;
input [6:0] VAR9;
output [3:0] VAR6;
reg [3:0] VAR3;
parameter VAR7=4;
parameter VAR10=2;
parameter VAR8=4'b1111; | mit |
dcsun88/ntpserver-fpga | cpu/ip/cpu_auto_pc_1/synth/cpu_auto_pc_1.v | 13,126 | module MODULE1 (
VAR8,
VAR18,
VAR49,
VAR94,
VAR77,
VAR54,
VAR66,
VAR3,
VAR79,
VAR5,
VAR58,
VAR22,
VAR1,
VAR42,
VAR69,
VAR104,
VAR78,
VAR7,
VAR74,
VAR95,
VAR81,
VAR45,
VAR29,
VAR68,
VAR80,
VAR67,
VAR83,
VAR112,
VAR88,
VAR61,
VAR37,
VAR36,
VAR87,
VAR64,
VAR82,
VAR89,
VAR27,
VAR48,
VAR43,
VAR109,
VAR114,
VAR99,
VAR21,
VAR... | gpl-3.0 |
Rmin1995/NoC | in_port.v | 1,395 | module MODULE1(VAR11, VAR2, VAR12, VAR21, VAR10, VAR19, reset);
parameter VAR7 = 16;
parameter VAR5 = 4;
output [0:VAR5-1] VAR11;
output [1:VAR6*VAR5] VAR2;
output [0:VAR5-1] VAR12;
input [1:VAR6] VAR21;
input [0:VAR5-1] VAR10;
input VAR19;
input reset;
wire [0:VAR5-1] VAR14;
wire [2:0] VAR15[7:0];
assign VAR15[0]=3'd0... | gpl-3.0 |
sh-chris110/chris | FPGA/uCos/system/synthesis/submodules/system_mm_interconnect_0_avalon_st_adapter_002.v | 6,164 | module MODULE1 #(
parameter VAR25 = 18,
parameter VAR2 = 0,
parameter VAR16 = 18,
parameter VAR19 = 0,
parameter VAR10 = 0,
parameter VAR7 = 0,
parameter VAR20 = 1,
parameter VAR8 = 1,
parameter VAR4 = 0,
parameter VAR14 = 18,
parameter VAR21 = 0,
parameter VAR6 = 1,
parameter VAR18 = 0,
parameter VAR15 = 1,
parameter ... | gpl-2.0 |
545/Atari7800 | new_atari/project_1/project_1.srcs/sources_1/ip/clock_divider/clock_divider.v | 4,245 | module MODULE1
(
input VAR5,
output VAR7,
output VAR6,
output VAR4,
input reset,
output VAR3
);
VAR2 VAR1
(
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.reset(reset),
.VAR3(VAR3)
);
endmodule | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_087.v | 1,530 | module MODULE1 (
VAR8,
VAR1
);
input [31:0] VAR8;
output [31:0]
VAR1;
wire [31:0]
VAR6,
VAR9,
VAR7,
VAR13,
VAR4,
VAR14,
VAR12,
VAR10,
VAR2;
assign VAR6 = VAR8;
assign VAR4 = VAR13 - VAR7;
assign VAR13 = VAR6 << 14;
assign VAR12 = VAR4 + VAR14;
assign VAR2 = VAR12 + VAR10;
assign VAR7 = VAR9 - VAR6;
assign VAR9 = VAR6 <... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.behavioral.v | 8,879 | module MODULE1( VAR11, VAR40, VAR36, VAR84, VAR43 );
input VAR11, VAR40, VAR84, VAR36;
output VAR43;
reg VAR16;
VAR46 VAR48(.VAR11(VAR11),.VAR40(VAR40),.VAR36(VAR36),.VAR84(VAR84),.VAR43(VAR43),.VAR16(VAR16));
VAR46 VAR88(.VAR11(VAR11),.VAR40(VAR40),.VAR36(VAR36),.VAR84(VAR84),.VAR43(VAR43),.VAR16(VAR16));
not VAR56(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.v | 2,196 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR5,
VAR8,
VAR2,
VAR3 ,
VAR1
);
output VAR7 ;
input VAR4 ;
input VAR5;
input VAR8;
input VAR2;
input VAR3 ;
input VAR1 ;
VAR6 VAR9 (
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR7 ,
VAR4 ,
VAR5
);
output VAR7 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai_4.v | 2,284 | module MODULE2 (
VAR7 ,
VAR5,
VAR6,
VAR2 ,
VAR3 ,
VAR8,
VAR9
);
output VAR7 ;
input VAR5;
input VAR6;
input VAR2 ;
input VAR3 ;
input VAR8;
input VAR9;
VAR1 VAR4 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR7 ,
VAR5,
VAR6,
VAR2 ,
VAR3
);
ou... | apache-2.0 |
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