repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd2/sky130_fd_sc_ms__clkdlyinv5sd2_1.v | 2,164 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR7,
VAR1,
VAR8 ,
VAR3
);
output VAR6 ;
input VAR4 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR3 ;
VAR5 VAR2 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6,
VAR4
);
output VAR6;
input VAR4;
supply1 VAR7;
supply0 VAR1;... | apache-2.0 |
grvmind/amber-cycloneiii | trunk/hw/vlog/amber25/a25_register_bank.v | 16,831 | module MODULE1 (
input VAR54,
input VAR29,
input VAR61,
input [1:0] VAR41, input [1:0] VAR17, input [3:0] VAR59, input VAR67,
input [3:0] VAR60,
input [3:0] VAR89,
input [3:0] VAR97,
input VAR19,
input [14:0] VAR33,
input [23:0] VAR24, input [31:0] VAR81,
input [31:0] VAR6,
input VAR3,
input [3:0] VAR85,
input [1:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3.behavioral.v | 1,693 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR8 ,
VAR3,
VAR9
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR3;
input VAR9;
wire VAR10 ;
wire VAR12;
or VAR6 (VAR10 , VAR5, VAR4, VAR8 );
VAR11 VAR1 (VAR12, VAR10, VAR3, VAR9);
buf VAR7 (VAR2 , VAR12 );
endmodule | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Upload/101062124_戴宏穎_Lab8/Timer.v | 1,183 | module MODULE1(
output reg [3:0]VAR3,
output reg [3:0]VAR2,
output VAR5,
input clk,
input VAR1
);
reg [3:0] VAR6, VAR4;
always @(posedge clk or negedge VAR1) begin
if (!VAR1) begin
VAR3 <= 4'd3;
VAR2 <= 4'd0;
end else begin
VAR3 <= VAR6;
VAR2 <= VAR4;
end
end
always @(*) begin
if (VAR3 == 4'd0 && VAR2 == 4'd0) begin
VA... | mit |
rkrajnc/minimig-mist | rtl/minimig/minimig.v | 29,982 | module MODULE1
(
input [23:1] VAR200, output [15:0] VAR190, input [15:0] VAR197, output [2:0] VAR42, input VAR156, input VAR198, input VAR145, input VAR266, output VAR232, output VAR20, input VAR216, input [31:0] VAR163, output wire VAR188, output [15:0] VAR181, input [15:0] VAR136, output [21:1] VAR272, output VAR113,... | gpl-3.0 |
parallella/oh | mio/hdl/mio_if.v | 4,402 | module MODULE1 (
VAR10, VAR11, VAR4,
clk, VAR19, VAR16, VAR7, VAR34, VAR27, VAR29, VAR15,
VAR3, VAR8
);
parameter VAR31 = 32; parameter VAR32 = 104; parameter VAR17 = 128;
input clk; input VAR19; input VAR7; input [4:0] VAR27; input VAR16; input [VAR31-1:0] VAR29; input [1:0] VAR2; output VAR10; output [VAR32-1:0] VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.behavioral.pp.v | 1,793 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR12,
VAR3,
VAR9 ,
VAR6
);
output VAR4 ;
input VAR7 ;
input VAR12;
input VAR3;
input VAR9 ;
input VAR6 ;
wire VAR1 ;
wire VAR10;
buf VAR11 (VAR1 , VAR7 );
VAR2 VAR5 (VAR10, VAR1, VAR12, VAR3);
buf VAR8 (VAR4 , VAR10 );
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_watchdog.v | 18,377 | module MODULE1 (
VAR98, VAR80, VAR85, VAR64, VAR3, VAR82,
VAR27, VAR72, VAR46, VAR16, VAR113, VAR34, VAR65, VAR25, VAR50, VAR73, VAR38, VAR55, VAR104, VAR60, VAR57, VAR20, VAR89, VAR48 );
output [15:0] VAR98; output VAR80; output VAR85; output VAR64; output VAR3; output VAR82;
input VAR27; input VAR72; input VAR46; inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp.functional.pp.v | 1,863 | module MODULE1 (
VAR12 ,
VAR11 ,
VAR2 ,
VAR6,
VAR8,
VAR9 ,
VAR1
);
output VAR12 ;
input VAR11 ;
input VAR2 ;
input VAR6;
input VAR8;
input VAR9 ;
input VAR1 ;
wire VAR7 ;
wire VAR13;
VAR3 VAR5 (VAR7 , VAR11, VAR6, VAR8 );
VAR3 VAR4 (VAR13, VAR2, VAR6, VAR8 );
notif1 VAR10 (VAR12 , VAR7, VAR13);
endmodule | apache-2.0 |
alexforencich/verilog-uart | rtl/uart_rx.v | 3,989 | module MODULE1 #
(
parameter VAR11 = 8
)
(
input wire clk,
input wire rst,
output wire [VAR11-1:0] VAR17,
output wire VAR7,
input wire VAR16,
input wire VAR6,
output wire VAR5,
output wire VAR15,
output wire VAR8,
input wire [15:0] VAR13
);
reg [VAR11-1:0] VAR3 = 0;
reg VAR18 = 0;
reg VAR2 = 1;
reg VAR4 = 0;
reg VAR10 ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/opencores/aemb/rtl/verilog/aeMB_core_BE.v | 1,841 | module MODULE1
parameter VAR17=0, parameter VAR33=0)
(input VAR26,
input VAR32,
output [VAR3-1:0] VAR5,
input [31:0] VAR8,
output VAR16,
output VAR21,
output [VAR24-1:0] VAR28,
output [31:0] VAR2,
input [31:0] VAR14,
input VAR11,
output [3:0] VAR23,
output VAR30,
input VAR31,
input VAR20);
wire [VAR3-1:0] VAR10;
wire [... | gpl-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_regfile_data.v | 2,264 | module MODULE1 (
address,
VAR3,
clk,
VAR7,
VAR2,
VAR9,
VAR4,
VAR6
)
;
output [ 31: 0] VAR4;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input VAR3;
input clk;
input VAR7;
input VAR2;
input [ 31: 0] VAR9;
wire VAR5;
reg [ 31: 0] VAR1;
wire [ 31: 0] VAR4;
wire [ 31: 0] VAR8;
wire [ 31: 0] VAR6;
assign VAR5 = 1;
assign V... | gpl-3.0 |
gajjanag/6111_Project | src/addr_map.v | 1,539 | module MODULE1(input[9:0] VAR2,
input[9:0] VAR1,
output[16:0] addr);
assign addr = (VAR1[9:1] << 8) + (VAR1[9:1] << 6) + (VAR2 >> 1);
endmodule | gpl-3.0 |
dingzh/piplined-MIPS-CPU | src/LAB5/Register.v | 1,255 | module MODULE1(
input VAR5,
input VAR2,
input [4:0] VAR1, input [4:0] VAR8,
input [4:0] VAR3, input [31:0] VAR11,
input reset,
output [31:0] VAR7,
output [31:0] VAR9,
output [31:0] VAR6,
output [31:0] VAR4
);
reg [31:0] VAR10[31:0];
begin
end | gpl-3.0 |
takeshineshiro/fpga_linear_128 | lf_bb.v | 2,128 | module MODULE1 (
clk,
VAR3,
VAR6,
VAR9,
VAR1,
VAR4,
VAR8,
VAR5,
VAR2,
VAR7);
input clk;
input VAR3;
input [14:0] VAR6;
input VAR9;
input VAR1;
input [1:0] VAR4;
output [30:0] VAR8;
output VAR5;
output VAR2;
output [1:0] VAR7;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai_1.v | 2,297 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR8 ,
VAR10 ,
VAR3 ,
VAR7 ,
VAR1,
VAR9
);
output VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR7 ;
input VAR1;
input VAR9;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
MForever78/CPUFly | ipcore_dir/Instruction_Memory.v | 3,975 | module MODULE1(
VAR7,
VAR19
);
input [11 : 0] VAR7;
output [31 : 0] VAR19;
VAR4 #(
.VAR43(12),
.VAR54("0"),
.VAR47(4096),
.VAR29("VAR30"),
.VAR42(0),
.VAR2(0),
.VAR27(0),
.VAR28(0),
.VAR15(0),
.VAR55(0),
.VAR5(0),
.VAR23(0),
.VAR11(0),
.VAR16(0),
.VAR13(0),
.VAR12(0),
.VAR41(0),
.VAR20(0),
.VAR26(1),
.VAR8(0),
.VAR21(0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.functional.v | 1,578 | module MODULE1 (
VAR4 ,
VAR6,
VAR1,
VAR12 ,
VAR7
);
output VAR4 ;
input VAR6;
input VAR1;
input VAR12 ;
input VAR7 ;
wire VAR9 ;
wire VAR8 ;
wire VAR3;
nand VAR10 (VAR9 , VAR1, VAR6 );
or VAR5 (VAR8 , VAR7, VAR12 );
nand VAR11 (VAR3, VAR9, VAR8);
buf VAR2 (VAR4 , VAR3 );
endmodule | apache-2.0 |
origintfj/riscv | rv32i/rtl/merlin_pfu.v | 8,222 | module MODULE1
parameter VAR49 = 0,
parameter VAR16 = 2, parameter VAR32 = { VAR39-2 {1'b0} }
)
(
input wire VAR30,
input wire VAR38,
input wire VAR10,
output wire VAR1,
output wire [1:0] VAR15,
output wire [VAR39-1:0] VAR57, output wire VAR55,
input wire VAR31,
input wire VAR2,
input wire [VAR39-1:0] VAR22,
output wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s4s/sky130_fd_sc_hs__dlymetal6s4s.behavioral.v | 1,760 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5,
VAR10
);
output VAR6 ;
input VAR1 ;
input VAR5;
input VAR10;
wire VAR3 ;
wire VAR4;
buf VAR8 (VAR3 , VAR1 );
VAR2 VAR7 (VAR4, VAR3, VAR5, VAR10);
buf VAR9 (VAR6 , VAR4 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_piano/zybo_petalinux_piano.srcs/sources_1/bd/block_design/ipshared/xilinx.com/processing_system7_bfm_v2_0/hdl/processing_system7_bfm_v2_0_regc.v | 2,200 | module MODULE1(
VAR31,
VAR11,
VAR39,
VAR24,
VAR27,
VAR1,
VAR8,
VAR26,
VAR25,
VAR34,
VAR21,
VAR36,
VAR14,
VAR7
);
input VAR31;
input VAR11;
input VAR39;
output VAR24;
input[31:0] VAR27;
output[1023:0] VAR1;
input[7:0] VAR8;
input [3:0] VAR26;
input VAR25;
output VAR34;
input[31:0] VAR21;
output[1023:0] VAR36;
input[7:0]... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/id_reg.v | 4,205 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR39] VAR43, input wire [VAR1] VAR33, input wire [VAR1] VAR5, input wire VAR37, input wire [VAR19] VAR2, input wire [VAR1] VAR31, input wire [VAR42] VAR40, input wire [VAR34] VAR18, input wire VAR17, input wire [VAR27] VAR7,
input wire VAR9, input wire VAR... | apache-2.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/jasons_v/MAC1.v | 6,167 | module MODULE1
(
VAR2, VAR4,
VAR1, VAR7, VAR14, VAR12, VAR16, VAR10
);
input VAR1 ; input VAR7 ;
input VAR14 ;
input VAR12 ;
input signed [(15):0] VAR16, VAR10 ;
output signed [(31):0] VAR2 ;
output VAR4 ;
reg signed [(31):0] VAR13 ;
reg signed [31:0] VAR9;
reg VAR3 ;
reg VAR5 ;
reg VAR15 ;
wire VAR4 ;
reg [3:0] VAR8 ;... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/cores/wb_altera_ddr_wrapper/rtl/verilog/bufram.v | 1,951 | module MODULE1 #(
parameter VAR8 = 3
)
(
input VAR1,
input [VAR8-1:0] VAR10,
input [3:0] VAR11,
input [31:0] VAR2,
output [31:0] VAR5,
input VAR4,
input [VAR8-1:0] VAR7,
input [3:0] VAR12,
input [31:0] VAR3,
output [31:0] VAR6
);
VAR9 #(
.VAR8(VAR8)
) VAR9 (
.VAR1 (VAR1),
.VAR10 (VAR10),
.VAR11 (VAR11),
.VAR2 (VAR2),
.... | gpl-2.0 |
plindstroem/oh | elink/hdl/esaxi.v | 17,066 | module MODULE1 (
VAR8, VAR3, VAR55, VAR43, VAR77,
VAR27, VAR31, VAR34, VAR102, VAR71,
VAR35, VAR54, VAR52, VAR11, VAR1,
VAR56,
VAR2, VAR53, VAR30, VAR37, VAR67,
VAR104, VAR65, VAR39, VAR70,
VAR107, VAR106, VAR13, VAR33,
VAR84, VAR21, VAR81, VAR42, VAR86,
VAR75, VAR41, VAR59, VAR60,
VAR93, VAR40, VAR29, VAR87,
VAR95, VA... | gpl-3.0 |
tugrulyatagan/RISC-processor | xilinx_processor/decode_unit.v | 11,355 | module MODULE1(
input [15:0] VAR6,
input [11:0] VAR2,
input [11:0] VAR19,
output reg [2:0] VAR3,
output reg [2:0] VAR5,
output reg [2:0] VAR1,
output reg VAR4,
output reg VAR17,
output reg [7:0] VAR10,
output reg [15:0] VAR14,
output reg VAR16,
output reg VAR11,
output reg VAR15,
output reg [3:0] VAR18,
output reg VAR1... | gpl-2.0 |
zeruniverse/Multiple-cycle_CPU | .v source code/mcmem.v | 5,500 | module MODULE1(
VAR56,
VAR49,
clk,
VAR26,
VAR40);
input [5 : 0] VAR56;
input [31 : 0] VAR49;
input clk;
input VAR26;
output [31 : 0] VAR40;
VAR1 #(
.VAR7(6),
.VAR54("0"),
.VAR14(64),
.VAR21("VAR31"),
.VAR18(1),
.VAR35(1),
.VAR45(0),
.VAR47(0),
.VAR58(0),
.VAR34(0),
.VAR16(0),
.VAR17(0),
.VAR20(0),
.VAR32(0),
.VAR38(0),... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2b/sky130_fd_sc_hs__nand2b.behavioral.pp.v | 1,833 | module MODULE1 (
VAR10,
VAR9,
VAR8 ,
VAR4 ,
VAR6
);
input VAR10;
input VAR9;
output VAR8 ;
input VAR4 ;
input VAR6 ;
wire VAR8 VAR1 ;
wire VAR7 ;
wire VAR5;
not VAR13 (VAR1 , VAR6 );
or VAR12 (VAR7 , VAR1, VAR4 );
VAR11 VAR2 (VAR5, VAR7, VAR10, VAR9);
buf VAR3 (VAR8 , VAR5 );
endmodule | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/niosii/synthesis/submodules/niosii_timer_ms.v | 6,280 | module MODULE1 (
address,
VAR15,
clk,
VAR20,
VAR9,
VAR8,
irq,
VAR26
)
;
output irq;
output [ 15: 0] VAR26;
input [ 2: 0] address;
input VAR15;
input clk;
input VAR20;
input VAR9;
input [ 15: 0] VAR8;
wire VAR22;
wire VAR29;
reg VAR28;
wire VAR17;
reg VAR3;
wire VAR10;
wire [ 31: 0] VAR2;
reg [ 31: 0] VAR23;
reg VAR16;
... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/38a92fb39758d0fa/ip_design_rst_ps7_0_100M_0_stub.v | 1,837 | module MODULE1(VAR5, VAR3, VAR10,
VAR4, VAR6, VAR7, VAR8, VAR9,
VAR1, VAR2)
;
input VAR5;
input VAR3;
input VAR10;
input VAR4;
input VAR6;
output VAR7;
output [0:0]VAR8;
output [0:0]VAR9;
output [0:0]VAR1;
output [0:0]VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlclkp/sky130_fd_sc_ls__dlclkp.pp.symbol.v | 1,270 | module MODULE1 (
input VAR2 ,
input VAR3,
output VAR7,
input VAR5 ,
input VAR6,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_base/mcu_cmd.v | 16,484 | module MODULE1(
input clk,
input VAR57,
input VAR7,
input [7:0] VAR27,
input [7:0] VAR39,
output [2:0] VAR11,
output reg VAR18 = 0,
output VAR14,
output reg VAR12 = 0,
input VAR60,
output [7:0] VAR63,
input [7:0] VAR9,
output [7:0] VAR66,
input [31:0] VAR5,
input [2:0] VAR54,
output [23:0] VAR13,
output [7:0] VAR37,
ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.symbol.v | 1,394 | module MODULE1 (
input VAR6,
input VAR4,
input VAR1,
input VAR8,
input VAR9,
output VAR2
);
supply1 VAR7;
supply0 VAR10;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
jas0n1ee/THU-DSD | FB/pll.v | 9,866 | module MODULE1
(
VAR6,
VAR3,
VAR4,
VAR1) ;
input VAR6;
input VAR3;
input [0:0] VAR4;
output [0:0] VAR1;
tri0 VAR6;
tri1 VAR3;
reg [0:0] VAR9;
reg [0:0] VAR2;
reg [0:0] VAR7;
wire VAR10;
wire VAR5;
wire VAR8; | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dram_dp.v | 32,047 | module MODULE1(
VAR47, VAR44, VAR68, VAR3,
VAR22, VAR11, VAR71, VAR1,
VAR40, VAR120, VAR58, VAR46,
clk, VAR76, VAR39, VAR90, VAR113,
VAR26, VAR56, VAR50,
VAR114, VAR2, VAR101, VAR73,
VAR6, VAR30, VAR17, VAR43,
VAR24, VAR94, VAR117,
VAR52, VAR96, VAR9, VAR54,
VAR19, VAR72, VAR74,
VAR63, VAR60, VAR102,
VAR29, VAR49, VAR1... | gpl-2.0 |
LordRafa/Sobel-FPGA | SISSources/V/RawaPro.v | 10,149 | module MODULE1 (
VAR33,
VAR76,
VAR124,
VAR109,
VAR142,
VAR29,
VAR58,
VAR133,
VAR65,
VAR1,
VAR88,
VAR68,
VAR111,
VAR7,
VAR72,
VAR148,
VAR89,
VAR104,
VAR95,
VAR87,
VAR44,
VAR98,
VAR138,
VAR145,
VAR122,
VAR97,
VAR91,
VAR52,
VAR63,
VAR50,
VAR81,
VAR144,
VAR45,
VAR75,
VAR14,
VAR129,
VAR48,
VAR108,
VAR40,
VAR67,
VAR143,
VAR2... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b_1.v | 2,218 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR4 ,
VAR5 ,
VAR9,
VAR1,
VAR2 ,
VAR3
);
output VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR5 ;
input VAR9;
input VAR1;
input VAR2 ;
input VAR3 ;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
cornell-zhang/datuner | designs/quartus/processor/adder.v | 1,138 | module MODULE1(VAR1, VAR13, VAR18, VAR15, VAR4, VAR21);
input [7:0] VAR1;
input [7:0] VAR13;
input VAR18;
output [7:0] VAR15;
output VAR4;
output VAR21;
wire VAR6;
wire VAR12;
wire VAR11;
wire VAR2;
wire VAR16;
wire VAR5;
wire VAR9;
VAR7 VAR20(
.VAR1(VAR1[0]),
.VAR13(VAR13[0]),
.VAR18(VAR18),
.VAR15(VAR15[0]),
.VAR4(VA... | bsd-3-clause |
maijohnson/comp3601_blue_15s2 | AudioController/tone_lut32.v | 3,030 | module MODULE1 (input [5:0] VAR33, output [15:0] VAR16);
parameter
VAR45 = 16'd23890,
VAR35 = 16'd22549,
VAR11 = 16'd21283,
VAR6 = 16'd20089,
VAR46 = 16'd18961,
VAR28 = 16'd17897,
VAR32 = 16'd16892,
VAR20 = 16'd15944,
VAR26 = 16'd15050,
VAR18 = 16'd14205,
VAR7 = 16'd13408,
VAR34 = 16'd12655,
VAR3 = 16'd11945,
VAR25 = 1... | mit |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_top.v | 11,715 | module MODULE1 (
VAR7,
VAR17, VAR41, VAR24, VAR20, VAR15, VAR22, VAR3, VAR47, VAR1,
VAR19,
VAR37, VAR16,
VAR18, VAR40, VAR38, VAR27, VAR8, VAR4
, VAR51
);
parameter VAR46 = VAR39;
parameter VAR2 = VAR48;
input VAR7;
input VAR17;
input [VAR2-1:0] VAR41;
input [VAR46-1:0] VAR24;
output [VAR46-1:0] VAR20;
input VAR15;
inp... | lgpl-2.1 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/pickle_40/bsg_mem/bsg_mem_1rw_sync.v | 2,868 | if (VAR2 == VAR33 && VAR35 == VAR32) \
begin: VAR7 \
VAR18 \
VAR36 \
(.VAR3 (VAR3) \
,.VAR11(VAR11) \
,.VAR25 (VAR25) \
,.VAR34 (VAR34) \
,.VAR17 (VAR17) \
,.VAR4 (VAR4) \
,.VAR30 (VAR30) \
); \
end: VAR7
module MODULE1 #( parameter VAR16(VAR35 )
, parameter VAR16(VAR2 )
, parameter VAR23 = VAR13(VAR2)
, parameter VAR2... | bsd-3-clause |
CeesWolfs/ceespu | src/ceespu_writeback.v | 2,192 | module MODULE1 (
input VAR7,
input VAR1,
input [1:0] VAR3,
input [2:0] VAR5,
input [13:0] VAR8,
input [31:0] VAR4,
input [31:0] VAR6,
output reg [31:0] VAR2
);
always @(*) begin
if (VAR3 == 2'b00) begin
VAR2 = VAR4;
end
else if (VAR3 == 2'b01) begin
if (VAR5 == 3'd0) begin
VAR2 = VAR6;
end
else if (VAR5 == 3'd1) begin
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xnor3/sky130_fd_sc_hdll__xnor3.symbol.v | 1,297 | module MODULE1 (
input VAR1,
input VAR3,
input VAR5,
output VAR7
);
supply1 VAR4;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_mask.v | 1,481 | module MODULE1(
input VAR2,
input VAR6,
output VAR9,
input VAR5,
output VAR12,
input signed [11:0] VAR7,
input signed [11:0] VAR14,
input signed [17:0] VAR8,
input signed [17:0] VAR3,
input [17:0] VAR11,
input [17:0] VAR17,
output reg VAR10,
input VAR16,
output reg signed [11:0] VAR15,
output reg signed [11:0] VAR13,
o... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu7t5v0__sdffrsnq_4.functional.pp.v | 1,804 | module MODULE1( VAR19, VAR14, VAR24, VAR30, VAR8, VAR26, VAR20, VAR17, VAR6, VAR21 );
input VAR30, VAR24, VAR26, VAR19, VAR8, VAR14, VAR17, VAR6, VAR21;
output VAR20;
not VAR13( VAR12, VAR26 );
not VAR7( VAR5, VAR8 );
wire VAR10;
not VAR28( VAR10, VAR24 );
wire VAR22;
not VAR9( VAR22, VAR19 );
wire VAR25;
and VAR3( VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux4/sky130_fd_sc_ms__mux4_2.v | 2,444 | module MODULE2 (
VAR7 ,
VAR13 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR3 ,
VAR2 ,
VAR11,
VAR8,
VAR5 ,
VAR12
);
output VAR7 ;
input VAR13 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR3 ;
input VAR2 ;
input VAR11;
input VAR8;
input VAR5 ;
input VAR12 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR13(VAR13),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o_1.v | 2,299 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR3 ,
VAR5,
VAR9
);
output VAR2 ;
input VAR8 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR3 ;
input VAR5;
input VAR9;
VAR6 VAR1 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
AngelTerrones/MUSB | Hardware/arbiter/arbiter.v | 5,671 | module MODULE1 #(
parameter VAR20 = 2
)(
input clk,
input rst,
input [32*VAR20-1:0] VAR15, input [32*VAR20-1:0] VAR7, input [4*VAR20-1:0] VAR10, input [VAR20-1 : 0] VAR22, output [31:0] VAR9, output [VAR20-1 : 0] VAR24, output [VAR20-1 : 0] VAR6, input [31:0] VAR1, input VAR11, input VAR16, output [31:0] VAR5, output [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21ai/sky130_fd_sc_hd__o21ai.blackbox.v | 1,334 | module MODULE1 (
VAR4 ,
VAR8,
VAR1,
VAR5
);
output VAR4 ;
input VAR8;
input VAR1;
input VAR5;
supply1 VAR3;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | DPWM.v | 4,261 | module MODULE1
(
input wire VAR34,
input wire VAR32,
input wire VAR25,
input wire VAR37,
input wire VAR10,
input wire VAR8,
output reg VAR11,
output reg VAR4,
output wire [3:0] VAR57,
output wire [7:0] VAR5
);
wire VAR28;
wire VAR46;
wire VAR49;
wire VAR22;
wire VAR52;
wire [3:0] VAR56;wire [3:0] VAR43;wire VAR17; wire... | apache-2.0 |
Elphel/x393_sata | x393/util_modules/pulse_cross_clock.v | 3,630 | module MODULE1#(
parameter VAR4=0 )(
input rst,
input VAR3,
input VAR5,
input VAR1, output VAR10,
output VAR7
);
localparam VAR2=VAR4 ? 1 : 0;
reg VAR6 = 0;
reg [2:0] VAR9 = 0;
reg VAR8 = 0;
assign VAR10=VAR9[2];
assign VAR7=VAR8; always @(posedge VAR3 or posedge rst) begin
if (rst) VAR6 <= 0;
end
else VAR6 <= VAR1 || ... | gpl-3.0 |
parallella/oh | xilibs/dv/IDDR.v | 1,690 | module MODULE1 (
VAR11, VAR15,
VAR10, VAR22, VAR19, VAR17, VAR5
);
parameter VAR2 = "VAR21";
parameter VAR1 = 1'b0;
parameter VAR23 = 1'b0;
parameter [0:0] VAR18 = 1'b0;
parameter [0:0] VAR3 = 1'b0;
parameter VAR8 = "VAR14";
localparam VAR7 = 0.1;
output VAR11; output VAR15; input VAR10; input VAR22; input VAR19; input... | mit |
bigeagle/riffa | fpga/altera/de5/DE5Gen3x4If128/hdl/DE5Gen3x4If128.v | 23,561 | module MODULE1
parameter VAR186 = 8,
parameter VAR102 = 128,
parameter VAR11 = 256,
parameter VAR125 = 5
)
(
output [7:0] VAR42,
input VAR55,
input VAR99,
input [VAR186-1:0] VAR27,
output [VAR186-1:0] VAR165,
input VAR44
);
wire VAR170;
wire VAR103;
wire [11:0] VAR100;
wire [31:0] VAR174;
wire VAR146;
wire VAR45;
wire ... | bsd-3-clause |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/interrupt.v | 7,145 | module MODULE1 #(
parameter VAR36 = 4'd12
)
(
input VAR31,
input VAR4,
input [VAR36-1:0] VAR8, input [VAR36-1:0] VAR17, input [VAR36-1:0] VAR7, input [VAR36-1:0] VAR2, input [VAR36-1:0] VAR18, input VAR35, input VAR22, input [31:0] VAR33, output [31:0] VAR24, output [31:0] VAR26, input VAR20, input VAR13, input VAR12, ... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/db/altera_mult_add_0kt2.v | 17,288 | module MODULE1
(
VAR251,
VAR284,
VAR232,
VAR240,
VAR206) ;
input VAR251;
input VAR284;
input [15:0] VAR232;
input [15:0] VAR240;
output [15:0] VAR206;
tri0 VAR251;
tri1 VAR284;
tri0 [15:0] VAR232;
tri0 [15:0] VAR240;
wire [15:0] VAR108;
VAR43 VAR247
(
.VAR251(VAR251),
.VAR218(),
.VAR284(VAR284),
.VAR232(VAR232),
.VAR24... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/RAMB16_S9_altera.v | 7,727 | module MODULE1 (
address,
VAR11,
VAR25,
VAR45,
VAR37,
VAR57);
input [10:0] address;
input VAR11;
input [7:0] VAR25;
input VAR45;
input VAR37;
output [7:0] VAR57;
wire [7:0] VAR65;
wire [7:0] VAR57 = VAR65[7:0];
VAR1 VAR13 (
.VAR4 (VAR37),
.VAR10 (VAR11),
.VAR26 (address),
.VAR66 (VAR45),
.VAR53 (VAR25),
.VAR56 (VAR65),... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.behavioral.v | 1,516 | module MODULE1 (
VAR5 ,
VAR10,
VAR3,
VAR7
);
output VAR5 ;
input VAR10;
input VAR3;
input VAR7;
supply1 VAR13;
supply0 VAR9;
supply1 VAR8 ;
supply0 VAR11 ;
wire VAR4 ;
wire VAR2;
or VAR12 (VAR4 , VAR3, VAR10 );
and VAR1 (VAR2, VAR4, VAR7 );
buf VAR6 (VAR5 , VAR2 );
endmodule | apache-2.0 |
kkalavantavanich/SD2017 | spiSend.v | 2,118 | /* VAR10 VAR28 VAR15 VAR12 VAR5 VAR20 VAR29.
* VAR6 VAR14 VAR13 use/VAR11/VAR18 in VAR25 VAR1 VAR23 this VAR27 VAR21 VAR2 VAR24 VAR26.
* VAR7: VAR19:
module MODULE1(
VAR17,
VAR16,
VAR4,
VAR3,
VAR8
);
parameter VAR32 = 6;
input VAR17;
input VAR16;
input [(VAR32 * 8) - 1:0] VAR4;
output VAR3;
output reg VAR8;
wire VAR16;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.blackbox.v | 1,354 | module MODULE1 (
VAR1 ,
VAR6,
VAR3,
VAR5,
VAR9
);
output VAR1 ;
input VAR6;
input VAR3;
input VAR5;
input VAR9;
supply1 VAR2;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o211a/sky130_fd_sc_lp__o211a.functional.v | 1,446 | module MODULE1 (
VAR2 ,
VAR3,
VAR4,
VAR1,
VAR6
);
output VAR2 ;
input VAR3;
input VAR4;
input VAR1;
input VAR6;
wire VAR10 ;
wire VAR7;
or VAR8 (VAR10 , VAR4, VAR3 );
and VAR9 (VAR7, VAR10, VAR1, VAR6);
buf VAR5 (VAR2 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1_1.v | 2,164 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR8,
VAR4,
VAR2 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR8;
input VAR4;
input VAR2 ;
input VAR6 ;
VAR7 VAR3 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
supply1 VAR8;
supply0 VAR4;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn_8.v | 2,148 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR1,
VAR5,
VAR8,
VAR2 ,
VAR3
);
output VAR7 ;
input VAR9 ;
input VAR1;
input VAR5;
input VAR8;
input VAR2 ;
input VAR3 ;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR7 ,
VAR9 ,
VAR1
);
output VAR7 ;... | apache-2.0 |
eda-globetrotter/PicenoDecoders | andy/design/generatedata.v | 2,823 | module MODULE1();
integer VAR1;
integer VAR3;
reg VAR2;
parameter VAR4 = 8'd255;
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbp/sky130_fd_sc_ms__dlxbp.pp.blackbox.v | 1,336 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR7 ,
VAR6,
VAR2,
VAR5,
VAR1 ,
VAR4
);
output VAR8 ;
output VAR3 ;
input VAR7 ;
input VAR6;
input VAR2;
input VAR5;
input VAR1 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b.pp.blackbox.v | 1,341 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR6,
VAR2,
VAR9 ,
VAR3
);
output VAR4 ;
input VAR5 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR6;
input VAR2;
input VAR9 ;
input VAR3 ;
endmodule | apache-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/id_stage.v | 6,563 | module MODULE1( input clk, rst,
input VAR35,
input [4:0] VAR55, input [31:0] VAR25, input [31:0] VAR56, VAR47,
input [1:0] VAR57, VAR15, input [31:0] VAR18, VAR1,
input VAR51,
input VAR24,
output [4:0] VAR32,
output [4:0] VAR44,
output [5:0] VAR39,
output reg [31:0] VAR3,
output reg [31:0] VAR7,
output reg [4:0] VAR16,... | mit |
meteorcloudy/CPU_verilog | alu.v | 1,890 | module MODULE1(VAR3,VAR1,VAR4,VAR2,VAR5,VAR6);
input[31:0] VAR3,VAR1;
input[3:0] VAR4;
input VAR2;
output VAR5;
reg VAR5;
output[31:0] VAR6;
reg[31:0] VAR6;
begin | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/ip_pid_controller/hdl/convert_type.v | 27,501 | module MODULE2 (VAR29, VAR44);
parameter signed [31:0] VAR6 = 4;
parameter signed [31:0] VAR19 = 1;
parameter signed [31:0] VAR12 = 4;
parameter signed [31:0] VAR22 = 1;
parameter signed [31:0] VAR20 = VAR40;
input [VAR6 - 1 : 0] VAR29;
output [VAR12 - 1 : 0] VAR44;
parameter signed [31:0] VAR26 = VAR22 - VAR19; wire [... | gpl-3.0 |
spike556/HuffmanCode | rtl model/sortnet/SortX16.v | 5,499 | module MODULE1 # (
parameter VAR46 = 18,
parameter VAR33 = 8
)(
input [VAR46-1:0] VAR10,
input [VAR46-1:0] VAR6,
input [VAR46-1:0] VAR63,
input [VAR46-1:0] VAR3,
input [VAR46-1:0] VAR61,
input [VAR46-1:0] VAR60,
input [VAR46-1:0] VAR62,
input [VAR46-1:0] VAR14,
input [VAR46-1:0] VAR44,
input [VAR46-1:0] VAR35,
input [V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_2.behavioral.pp.v | 1,311 | module MODULE1( VAR7, VAR5, VAR6, VAR9, VAR2, VAR8 );
input VAR7, VAR5, VAR6;
inout VAR2, VAR8;
output VAR9;
VAR3 VAR4(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR2(VAR2),.VAR8(VAR8));
VAR3 VAR1(.VAR7(VAR7),.VAR5(VAR5),.VAR6(VAR6),.VAR9(VAR9),.VAR2(VAR2),.VAR8(VAR8)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.blackbox.v | 1,382 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR5 ;
input VAR1;
supply1 VAR4;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
bluecmd/mexiko | rtl/orpsoc/wb_g18.v | 3,443 | module MODULE1 #(
parameter VAR35 = 67108864, parameter VAR18 = VAR12(VAR35/2),
parameter VAR21 = 32
) (
input VAR10,
input VAR19,
input [VAR21-1:0] VAR5,
input [31:0] VAR34,
input [3:0] VAR28,
input VAR23,
input [1:0] VAR27,
input [2:0] VAR4,
input VAR33,
input VAR22,
output VAR6,
output VAR3,
output [31:0] VAR1,
inou... | gpl-3.0 |
MartinMosbeck/NoCMonitor | buildCONNECT4x4/mkRouterInputArbitersRoundRobin.v | 37,229 | module MODULE1(VAR38,
VAR124,
VAR136,
VAR11,
VAR36,
VAR19,
VAR62,
VAR111,
VAR107,
VAR152,
VAR22,
VAR217,
VAR184,
VAR128,
VAR80,
VAR72,
VAR42);
input VAR38;
input VAR124;
input [4 : 0] VAR136;
output [4 : 0] VAR11;
input VAR36;
input [4 : 0] VAR19;
output [4 : 0] VAR62;
input VAR111;
input [4 : 0] VAR107;
output [4 : 0]... | gpl-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/miim/eth_outputcontrol.v | 6,412 | module MODULE1(VAR9, VAR10, VAR2, VAR15, VAR4, VAR3, VAR11, VAR6, VAR12, VAR5);
parameter VAR16 = 1;
input VAR9; input VAR10; input VAR3; input VAR11; input VAR2; input VAR15; input [6:0] VAR4; input VAR6;
output VAR12; output VAR5;
wire VAR13;
reg VAR14;
reg VAR1;
reg VAR5;
reg VAR8;
reg VAR7;
reg VAR12;
assign VAR13 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi_m.v | 2,349 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR10 ,
VAR4 ,
VAR11 ,
VAR7,
VAR1,
VAR8 ,
VAR5
);
output VAR9 ;
input VAR3 ;
input VAR10 ;
input VAR4 ;
input VAR11 ;
input VAR7;
input VAR1;
input VAR8 ;
input VAR5 ;
VAR2 VAR6 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR8(VAR8),
.... | apache-2.0 |
ffu/DSA-3.2.2 | usrp/fpga/megacells/accum32.v | 23,807 | module MODULE1
(
VAR60,
VAR76,
VAR57,
VAR82,
VAR13) ;
input VAR60;
input VAR76;
input VAR57;
input [31:0] VAR82;
output [31:0] VAR13;
wire [0:0] VAR10;
wire [0:0] VAR89;
wire [0:0] VAR16;
wire [0:0] VAR58;
wire [0:0] VAR39;
wire [0:0] VAR80;
wire [0:0] VAR66;
wire [0:0] VAR92;
wire [0:0] VAR90;
wire [0:0] VAR6;
wire [0... | gpl-3.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/ip/Erosion/acl_fp_acos_s5.v | 1,184 | module MODULE1 (
enable,
VAR8,
VAR6,
VAR3);
input enable;
input VAR8;
input [31:0] VAR6;
output [31:0] VAR3;
wire [31:0] VAR4;
wire [31:0] VAR3 = VAR4[31:0];
VAR1 VAR5 (
.en (enable),
.VAR9(1'b0),
.clk(VAR8),
.VAR2(VAR6),
.VAR7(VAR4));
endmodule | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_2_cycles/integracion_fisica/front_end/source/KOA.v | 5,939 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR33,
input wire [VAR21-1:0] VAR27,
input wire [VAR21-1:0] VAR22,
output reg [2*VAR21-1:0] VAR26
);
wire [1:0] VAR36;
wire [3:0] VAR29;
assign VAR36 = 2'b00;
assign VAR29 = 4'b0000;
wire [VAR21/2-1:0] VAR10;
wire [VAR21/2:0] VAR1;
wire [VAR21/2-3:0] VAR11;
wi... | gpl-3.0 |
HashRatio/mm-hashratio | verilog/superkdf9/components/sha/sha.v | 7,656 | module MODULE1(
input VAR44,
input VAR61,
input VAR19, input VAR64,
input VAR67,
input VAR30, input [2:0] VAR66, input [1:0] VAR27, input [4:0] VAR34,
input [31:0] VAR50,
input [3:0] VAR7,
output reg VAR36,
output VAR62, output VAR28, output [31:0] VAR21
);
assign VAR62 = 1'b0 ;
assign VAR28 = 1'b0 ;
always @ ( posedge... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221o/sky130_fd_sc_hs__a221o.behavioral.v | 2,093 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR13 ,
VAR10 ,
VAR12 ,
VAR4 ,
VAR9,
VAR17
);
output VAR1 ;
input VAR5 ;
input VAR13 ;
input VAR10 ;
input VAR12 ;
input VAR4 ;
input VAR9;
input VAR17;
wire VAR12 VAR6 ;
wire VAR12 VAR11 ;
wire VAR15 ;
wire VAR18;
and VAR16 (VAR6 , VAR10, VAR12 );
and VAR14 (VAR11 , VAR5, VAR13 );
or VAR... | apache-2.0 |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/axi_slave_rd.v | 12,766 | module MODULE1 (
VAR85, VAR21, VAR50, VAR78, VAR39, VAR72, VAR82,
VAR103, VAR108, VAR53,
VAR13, VAR49, VAR80,
VAR44,
VAR5, VAR16, reset, VAR1, VAR84, VAR27, VAR25, VAR59, VAR23,
VAR46, VAR19, VAR56, VAR37, VAR55,
VAR95, VAR51, VAR102,
VAR58, VAR40, VAR4,
VAR63
);
parameter VAR98 = 12; parameter VAR36 = 32; parameter VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai_1.v | 2,457 | module MODULE2 (
VAR3 ,
VAR12 ,
VAR1 ,
VAR5 ,
VAR8 ,
VAR10 ,
VAR6,
VAR7,
VAR4 ,
VAR11
);
output VAR3 ;
input VAR12 ;
input VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR10 ;
input VAR6;
input VAR7;
input VAR4 ;
input VAR11 ;
VAR2 VAR9 (
.VAR3(VAR3),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR6... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios/nios/synthesis/submodules/nios_altmemddr_0.v | 29,536 | module MODULE1 (
VAR106,
VAR102,
VAR13,
VAR49,
VAR51,
VAR43,
VAR10,
VAR97,
VAR31,
VAR73,
VAR12,
VAR78,
VAR54,
VAR35,
VAR28,
VAR77,
VAR30,
VAR32,
VAR87,
VAR34,
VAR26,
VAR11,
VAR96,
VAR41,
VAR59,
VAR91,
VAR93,
VAR4,
VAR86,
VAR7,
VAR100,
VAR16,
VAR64);
input [23:0] VAR106;
input VAR102;
input VAR13;
input VAR49;
input [31... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srdlstp/sky130_fd_sc_lp__srdlstp.blackbox.v | 1,366 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR10 ,
VAR9 ,
VAR7
);
output VAR3 ;
input VAR8 ;
input VAR10 ;
input VAR9 ;
input VAR7;
supply1 VAR1;
supply1 VAR4 ;
supply0 VAR5 ;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_image_filter_fh_0_0/synth/design_1_image_filter_fh_0_0.v | 10,217 | module MODULE1 (
VAR18,
VAR35,
VAR22,
VAR20,
VAR11,
VAR38,
VAR10,
VAR41,
VAR34,
VAR9,
VAR7,
VAR3,
VAR37,
VAR36,
VAR13,
VAR12,
VAR26,
VAR15,
VAR16,
interrupt,
VAR2,
VAR32,
VAR17,
VAR1,
VAR28,
VAR19,
VAR27,
VAR39,
VAR8,
VAR33,
VAR23,
VAR6,
VAR25,
VAR14,
VAR40,
VAR29,
VAR5,
VAR21
);
input wire [5 : 0] VAR18;
input wire VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a311o/sky130_fd_sc_hd__a311o_2.v | 2,437 | module MODULE2 (
VAR2 ,
VAR11 ,
VAR7 ,
VAR9 ,
VAR8 ,
VAR6 ,
VAR12,
VAR5,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR11 ;
input VAR7 ;
input VAR9 ;
input VAR8 ;
input VAR6 ;
input VAR12;
input VAR5;
input VAR4 ;
input VAR1 ;
VAR10 VAR3 (
.VAR2(VAR2),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR12(V... | apache-2.0 |
jouyang3/FMCW | DSP/Radar_DSP/FPGA/Individual Modules/FFT_Mag/FFT_Mag/magnitude.v | 1,231 | module MODULE3(
VAR25, VAR23, VAR26, VAR9, VAR13, VAR12);
input [11:0] VAR25, VAR23, VAR26, VAR9;
output [11:0] VAR13, VAR12;
wire [11:0] VAR11, VAR19, VAR2, VAR7;
wire [11:0] VAR15, VAR20, VAR14, VAR3;
MODULE1 MODULE4 (.in(VAR25), .out(VAR15));
MODULE1 MODULE5 (.in(VAR23), .out(VAR20));
MODULE1 MODULE3 (.in(VAR26), .o... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/BCHSharedKESforTiger4/src/d_KES_PE_DC_NMLodr.v | 4,525 | module MODULE1 (
input wire VAR5,
input wire VAR21,
input wire VAR13,
input wire VAR14,
input wire [VAR23-1:0] VAR20,
input wire [VAR23-1:0] VAR1,
output wire [VAR23-1:0] VAR18,
output wire [VAR23-1:0] VAR4
);
parameter [11:0] VAR3 = 12'b000000000000;
parameter [11:0] VAR16 = 12'b000000000001;
parameter VAR17 = 2'b01; ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a_2.v | 2,322 | module MODULE2 (
VAR7 ,
VAR11 ,
VAR1 ,
VAR10 ,
VAR9 ,
VAR3,
VAR4,
VAR6 ,
VAR5
);
output VAR7 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
input VAR9 ;
input VAR3;
input VAR4;
input VAR6 ;
input VAR5 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr.behavioral.v | 1,663 | module MODULE1 (
VAR2 ,
VAR3,
VAR8
);
output VAR2 ;
input VAR3;
input VAR8 ;
supply1 VAR5;
supply1 VAR13 ;
supply0 VAR9 ;
supply1 VAR4 ;
supply0 VAR11 ;
wire VAR12 ;
wire VAR10;
not VAR6 (VAR12 , VAR3 );
and VAR7 (VAR10, VAR12, VAR8 );
buf VAR1 (VAR2 , VAR10 );
endmodule | apache-2.0 |
cynngah/virtualsynthesizer | sound_files/Altera_UP_Clock_Edge.v | 6,370 | module MODULE1 (
clk,
reset,
VAR5,
VAR3,
VAR1
);
input clk;
input reset;
input VAR5;
output VAR3;
output VAR1;
wire VAR2;
reg VAR4;
reg VAR6;
always @(posedge clk)
VAR4 <= VAR5;
always @(posedge clk)
VAR6 <= VAR4;
assign VAR3 = VAR2 & VAR4;
assign VAR1 = VAR2 & VAR6;
assign VAR2 = VAR6 ^ VAR4;
endmodule | mit |
myriadrf/A2300 | hdl/wca/WcaReadByteReg.v | 1,710 | module MODULE1
(
input wire reset, input wire VAR14, input wire VAR9, input wire [7:0] in, output wire [7:0] VAR1, input wire [11:0] VAR5, inout wire [7:0] VAR4 );
parameter VAR13 = 0;
parameter VAR8 = 1'b0;
wire VAR15 = (VAR13 == VAR5[11:4]);
wire read = VAR15 & VAR5[3];
wire enable = VAR9 & (~VAR15 | VAR8);
VAR11 VAR... | gpl-2.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_alu.v | 12,191 | module MODULE1 (
VAR80, VAR42, VAR59, VAR16,
VAR31, VAR46, VAR68, VAR44, VAR30, VAR22, VAR9, VAR81, VAR65 );
output [15:0] VAR80; output [15:0] VAR42; output [3:0] VAR59; output [3:0] VAR16;
input VAR31; input VAR46; input [11:0] VAR68; input VAR44; input [7:0] VAR30; input [7:0] VAR22; input [15:0] VAR9; input [15:0] ... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v6es_gtx_x4_250/example_design/pci_exp_4_lane_64b_ep.v | 12,537 | module MODULE1 (
VAR86,
VAR62,
VAR89,
VAR98,
VAR14,
VAR37,
VAR94,
VAR56,
VAR55,
VAR44,
VAR69,
VAR21,
VAR3,
VAR42,
VAR50,
VAR32,
VAR97,
VAR46,
VAR1,
VAR73,
VAR59,
VAR31,
VAR78,
VAR72,
VAR85,
VAR51,
VAR75,
VAR7,
VAR74,
VAR15,
VAR77,
VAR39,
VAR84,
VAR6,
VAR8,
VAR71,
VAR68,
VAR81,
VAR27,
VAR34,
VAR16,
VAR76,
VAR36,
VAR96,
... | lgpl-3.0 |
sam-falvo/remex | example/rtl/TOP.v | 4,838 | module MODULE1(
input VAR107,
input VAR97,
output [18:0] VAR150,
inout [15:0] VAR7,
output VAR33,
output VAR52,
output VAR115,
output VAR70,
output VAR72,
output VAR15,
output VAR63,
output VAR60,
input VAR118
);
wire VAR86, VAR149;
wire [31:0] VAR109;
wire [63:0] VAR114, VAR11;
wire [63:0] VAR104, VAR4, VAR38;
wire VA... | mpl-2.0 |
tommythorn/yari | Icarus/rtl/logshiftright.v | 1,134 | module MODULE1(VAR3,
VAR4,
VAR7);
parameter VAR5 = "VAR6";
parameter VAR2 = 32;
parameter VAR1 = 5;
input wire [VAR1-1:0] VAR3;
input wire [VAR2-1 :0] VAR4;
output wire [VAR2-1 :0] VAR7;
assign VAR7 = VAR4 >> VAR3;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.functional.pp.v | 2,164 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR7 ,
VAR5 ,
VAR18 ,
VAR1,
VAR10,
VAR4 ,
VAR13
);
output VAR11 ;
input VAR9 ;
input VAR7 ;
input VAR5 ;
input VAR18 ;
input VAR1;
input VAR10;
input VAR4 ;
input VAR13 ;
wire VAR8 ;
wire VAR17 ;
wire VAR3 ;
wire VAR6;
nand VAR14 (VAR8 , VAR7, VAR9 );
nand VAR2 (VAR17 , VAR18, VAR5 );
an... | apache-2.0 |
pemsac/ANN_project | ANN_project.srcs/sources_1/bd/design_SWandHW_standalone/ip/design_SWandHW_standalone_auto_pc_1/synth/design_SWandHW_standalone_auto_pc_1.v | 15,783 | module MODULE1 (
VAR27,
VAR104,
VAR93,
VAR33,
VAR23,
VAR2,
VAR18,
VAR85,
VAR100,
VAR74,
VAR83,
VAR52,
VAR48,
VAR1,
VAR45,
VAR109,
VAR107,
VAR86,
VAR49,
VAR14,
VAR84,
VAR98,
VAR88,
VAR54,
VAR81,
VAR103,
VAR96,
VAR72,
VAR17,
VAR60,
VAR50,
VAR13,
VAR7,
VAR110,
VAR26,
VAR65,
VAR66,
VAR80,
VAR102,
VAR16,
VAR11,
VAR68,
VAR21... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2_2.v | 2,075 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR9 ,
VAR8,
VAR3,
VAR4 ,
VAR1
);
output VAR5 ;
input VAR6 ;
input VAR9 ;
input VAR8;
input VAR3;
input VAR4 ;
input VAR1 ;
VAR2 VAR7 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5,
VAR6,
VAR9
);
output VAR5;
... | apache-2.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_151_bits/rtl/rom.v | 14,783 | module MODULE1 (clk, addr, out);
input clk;
input [8:0] addr;
output reg [25:0] out;
always @(posedge clk)
case (addr)
0: out <= 26'h30c042;
1: out <= 26'h514045;
2: out <= 26'h61a041;
3: out <= 26'h71e041;
4: out <= 26'hc046;
5: out <= 26'h1603840;
6: out <= 26'h1702041;
7: out <= 26'h1717857;
8: out <= 26'h1817847;
9... | apache-2.0 |
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