repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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trivoldus28/pulsarch-verilog | design/sys/iop/sparc/spu/rtl/spu_maaddr.v | 35,040 | module MODULE1 (
VAR52,
VAR9,
VAR22,
VAR119,
VAR35,
VAR216,
VAR48,
VAR201,
VAR232,
VAR38,
VAR213,
VAR73,
VAR142,
VAR95,
VAR141,
VAR215,
VAR39,
VAR148,
VAR176,
VAR210,
VAR113,
VAR195,
VAR222,
VAR227,
VAR23,
VAR90,
VAR20,
VAR220,
VAR159,
VAR123,
VAR184,
VAR76,
VAR8,
VAR88,
VAR101,
VAR74,
VAR82,
VAR4,
VAR72,
VAR190,
VAR13... | gpl-2.0 |
jhol/butterflylogic | rtl/timer.v | 3,052 | module MODULE1 (
input wire clk,
input wire reset,
input wire VAR7,
input wire VAR2,
input wire [31:0] VAR11,
input wire VAR9,
input wire VAR3,
input wire VAR4,
input wire VAR1,
output reg VAR13
);
reg [35:0] MODULE1, VAR14;
reg [35:0] VAR8, VAR5; reg VAR10, VAR12;
reg VAR6;
begin
begin
begin
begin
begin
begin
begin | gpl-2.0 |
mistryalok/Zedboard | learning/training/MSD/s05/project_1/project_1.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.v | 11,129 | module MODULE1
(VAR4,
VAR20,
VAR47,
VAR62,
VAR18,
VAR43,
VAR63,
VAR64,
VAR16,
VAR11,
VAR82,
VAR22,
VAR68,
VAR70,
VAR60,
VAR2,
VAR6,
VAR25,
VAR44,
VAR66,
VAR79,
VAR75,
VAR59,
VAR26,
VAR45,
VAR67,
VAR49,
VAR53,
VAR24,
VAR31,
VAR77,
VAR8,
VAR74,
VAR13,
VAR61,
VAR55,
VAR83,
VAR48,
VAR10,
VAR9,
VAR34,
VAR17,
VAR23,
VAR41,
V... | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_wrlvl_off_delay.v | 8,955 | module MODULE1 #
(
parameter VAR18 = 100,
parameter VAR39 = 3636,
parameter VAR2 = 2,
parameter VAR41 = 4,
parameter VAR22= 46,
parameter VAR20 = 3,
parameter VAR23 = 8,
parameter VAR29 = 3
)
(
input clk,
input rst,
input VAR27,
input VAR40,
output reg [VAR20:0] VAR1,
output reg VAR13,
output reg VAR9,
output reg VAR43... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3b/sky130_fd_sc_hdll__or3b_4.v | 2,225 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR8 ,
VAR3 ,
VAR4,
VAR7,
VAR2 ,
VAR9
);
output VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR3 ;
input VAR4;
input VAR7;
input VAR2 ;
input VAR9 ;
VAR10 VAR5 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfstp/sky130_fd_sc_hvl__sdfstp.functional.pp.v | 2,421 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR1 ,
VAR15 ,
VAR19 ,
VAR23,
VAR18 ,
VAR7 ,
VAR16 ,
VAR2
);
output VAR13 ;
input VAR12 ;
input VAR1 ;
input VAR15 ;
input VAR19 ;
input VAR23;
input VAR18 ;
input VAR7 ;
input VAR16 ;
input VAR2 ;
wire VAR21 ;
wire VAR11 ;
wire VAR14 ;
wire VAR20;
not VAR6 (VAR11 , VAR23 );
VAR5 VAR3 (... | apache-2.0 |
alonso193/proyecto1 | CMD.v | 13,171 | module MODULE3 (VAR52, VAR12, VAR33, VAR10, VAR29, VAR51, VAR48, VAR2, VAR44, VAR26, VAR39, VAR42);
input wire VAR52, VAR12, VAR33, VAR39, VAR42;
input wire [31:0]VAR10;
input wire [5:0]VAR29;
output VAR51, VAR48, VAR44, VAR26;
output [127:0]VAR2;
wire VAR58;
wire VAR13;
wire VAR14;
wire VAR1;
wire VAR59;
wire [39:0]VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbn/sky130_fd_sc_ms__dfbbn.functional.pp.v | 2,336 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR17 ,
VAR14 ,
VAR7 ,
VAR15,
VAR11 ,
VAR2 ,
VAR9 ,
VAR6
);
output VAR5 ;
output VAR8 ;
input VAR17 ;
input VAR14 ;
input VAR7 ;
input VAR15;
input VAR11 ;
input VAR2 ;
input VAR9 ;
input VAR6 ;
wire VAR19;
wire VAR20 ;
wire VAR3 ;
wire VAR1;
not VAR22 (VAR19 , VAR15 );
not VAR4 (VAR20 , ... | apache-2.0 |
freecores/altor32 | rtl/cpu/altor32_writeback.v | 4,840 | module MODULE1
(
input VAR3 ,
input VAR18 ,
input [31:0] VAR1 ,
input [4:0] VAR22 ,
input [31:0] VAR9 ,
input [31:0] VAR15 ,
input [1:0] VAR2 ,
input VAR6 ,
input [63:0] VAR7 ,
output reg VAR13 ,
output reg [4:0] VAR16 ,
output reg [31:0] VAR17
);
reg [4:0] VAR8;
reg [31:0] VAR21;
reg [7:0] VAR19;
reg VAR23;
reg [1:0] ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi.blackbox.v | 1,427 | module MODULE1 (
VAR9 ,
VAR1,
VAR7,
VAR6,
VAR11,
VAR4,
VAR10
);
output VAR9 ;
input VAR1;
input VAR7;
input VAR6;
input VAR11;
input VAR4;
input VAR10;
supply1 VAR2;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/gpmc/gpmc_to_fifo.v | 6,572 | module MODULE1
(input [15:0] VAR7, input [VAR43:1] VAR41, input VAR23, input VAR45,
input clk, input reset, input VAR18, input VAR20,
output [17:0] VAR3, output VAR9, input VAR47,
output reg VAR42);
reg VAR6;
reg [VAR43:1] addr;
reg [VAR12:0] VAR46, VAR34;
localparam VAR27 = 0;
localparam VAR24 = 1;
reg [1:0] VAR15;
re... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_pps_receiver.v | 4,364 | module MODULE1 (
input clk,
input rst,
input VAR11,
input VAR16,
input VAR5,
output reg [31:0] VAR3,
output reg VAR15,
input VAR8,
output reg VAR7);
reg [ 2:0] VAR1 = 3'b0;
reg [ 2:0] VAR6 = 3'b0;
reg VAR2 = 1'b0;
reg VAR14 = 1'b0;
reg [31:0] VAR13 = 32'b0;
reg [31:0] VAR9 = 32'b0;
reg VAR10 = 1'b0;
wire VAR12;
wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor3b/sky130_fd_sc_hd__nor3b.blackbox.v | 1,331 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR6 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR5;
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_025.v | 1,361 | module MODULE2 (
VAR9,
VAR4
);
input [31:0] VAR9;
output [31:0]
VAR4;
wire [31:0]
VAR5,
VAR3,
VAR6,
VAR2,
VAR1;
assign VAR5 = VAR9;
assign VAR2 = VAR6 << 11;
assign VAR1 = VAR5 + VAR2;
assign VAR3 = VAR5 << 2;
assign VAR6 = VAR5 + VAR3;
assign VAR4 = VAR1;
endmodule
module MODULE1(
VAR9,
VAR4,
clk
);
input [31:0] VAR9;... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/yf32/mult.v | 11,971 | module MODULE1 (clk, reset, VAR52, VAR23, VAR60, VAR41, VAR34);
input clk;
input reset;
input [31:0] VAR52;
input [31:0] VAR23;
input [ 3:0] VAR60;
output [31:0] VAR41;
output VAR34;
wire [31:0] VAR41;
reg VAR34;
reg VAR1;
reg VAR19;
reg [ 5:0] VAR44;
reg [31:0] VAR37;
reg [63:0] VAR16;
reg [31:0] VAR48;
reg [33:0] VAR... | mit |
monotone-RK/FACE | IEICE-Trans/16-way/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,230 | module MODULE1(VAR48, VAR84, VAR46, VAR17, VAR74, VAR71, VAR5, VAR87, VAR64, VAR21, VAR3, VAR8, VAR20, VAR2, VAR85, VAR63, VAR81, VAR69, VAR86, VAR45, VAR83, VAR53, VAR75, VAR29, VAR37, VAR13, VAR9, VAR25, VAR32, VAR23, VAR36, VAR12, VAR22, VAR77, VAR55, VAR56, VAR57, VAR62, VAR4, VAR43, VAR78, VAR10, VAR31, VAR73, VAR... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/miim/eth_clockgen.v | 5,603 | module MODULE1(VAR6, VAR4, VAR11, VAR5, VAR8, VAR9);
parameter VAR7=1;
input VAR6; input VAR4; input [7:0] VAR11;
output VAR9; output VAR5; output VAR8;
reg VAR9;
reg [7:0] VAR10;
wire VAR3;
wire [7:0] VAR2;
wire [7:0] VAR1;
assign VAR1[7:0] = (VAR11[7:0]<2)? 8'h02 : VAR11[7:0]; assign VAR2[7:0] = (VAR1[7:0]>>1) -1;
al... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a41oi/sky130_fd_sc_hd__a41oi_4.v | 2,439 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR1 ,
VAR9 ,
VAR8 ,
VAR6 ,
VAR7,
VAR4,
VAR10 ,
VAR2
);
output VAR5 ;
input VAR12 ;
input VAR1 ;
input VAR9 ;
input VAR8 ;
input VAR6 ;
input VAR7;
input VAR4;
input VAR10 ;
input VAR2 ;
VAR11 VAR3 (
.VAR5(VAR5),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VA... | apache-2.0 |
sirchuckalot/zet | cores/hpdmc_sdr16/rtl/hpdmc_datactl.v | 4,824 | module MODULE1(
input VAR9,
input VAR5,
input read,
input write,
input [3:0] VAR6,
output reg VAR15,
output reg VAR8,
output [3:0] VAR20,
output reg ack,
output reg VAR21,
output VAR11,
input VAR14,
input [1:0] VAR4
);
reg [2:0] VAR12;
always @(posedge VAR9) begin
if(VAR5) begin
VAR12 <= 3'd0;
VAR15 <= 1'b1;
end else b... | gpl-3.0 |
Madh93/scpu | modules/vga_adapter/vga_adapter.v | 14,146 | module MODULE1(
VAR4,
VAR36,
VAR58,
VAR6, VAR56, VAR45,
VAR57,
VAR16,
VAR60,
VAR51,
VAR1,
VAR69,
VAR49,
VAR47);
parameter VAR65 = 1;
parameter VAR53 = "VAR13";
parameter VAR70 = "160x120";
parameter VAR11 = "VAR24.VAR31";
parameter VAR74 = "VAR61";
input VAR4;
input VAR36;
input [((VAR53 == "VAR61") ? (0) : (VAR65*3-1)... | mit |
jotego/jt51 | syn/xilinx/ym09/hdl/uart09.v | 2,375 | module MODULE1 #(parameter VAR38=10 )(
input wire clk,
input wire rst,
input wire VAR13,
output wire VAR12,
output wire [7:0] VAR20,
output wire VAR21,
input wire VAR16,
input wire [7:0] VAR34,
input wire [7:0] VAR7,
output wire [7:0] VAR11,
input wire VAR23,
input wire VAR32,
input wire VAR31,
output reg VAR26,
output... | gpl-3.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/channelizer/checkpoint256/sysgen/synth_reg_w_init.v | 2,358 | module MODULE2 (VAR5, VAR30, VAR16, clk, VAR20);
parameter VAR15 = 8;
parameter VAR29 = 0;
parameter [VAR15-1 : 0] VAR17 = 'b0000;
parameter VAR22 = 1;
input[VAR15 - 1:0] VAR5;
input VAR30, VAR16, clk;
output[VAR15 - 1:0] VAR20;
wire[(VAR22 + 1) * VAR15 - 1:0] VAR19;
wire .2 VAR24;
genvar VAR14;
generate
if (VAR22 == 0... | gpl-3.0 |
praveendath92/securePUF | source/ipcore_dependencies/eth_fifo_8.v | 8,202 | module MODULE1
(
VAR18, VAR53, VAR48, VAR35, VAR5, VAR14, VAR16, VAR39, VAR11,
VAR37, VAR45, VAR49, VAR41, VAR8, VAR19, VAR40, VAR51, VAR42,
VAR31, VAR21, VAR15, VAR25, VAR55, VAR54, VAR13, VAR30,
VAR2, VAR24, VAR20, VAR43, VAR9, VAR46, VAR47, VAR10 );
parameter VAR3 = 0;
input VAR18;
input VAR53;
input VAR48;
output [... | gpl-2.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/TECH/CLK_SWITCH.v | 3,463 | module MODULE1 (
input VAR1,
input VAR3,
input VAR2 ,
output VAR4
);
assign VAR4=VAR2?VAR3:VAR1;
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/altera_irq_bridge.v | 5,256 | module MODULE1
parameter VAR25 = 32
)
(
input clk,
input reset,
input [VAR25 - 1:0] VAR20,
output VAR8,
output VAR15,
output VAR34,
output VAR21,
output VAR13,
output VAR2,
output VAR26,
output VAR7,
output VAR16,
output VAR5,
output VAR6,
output VAR27,
output VAR33,
output VAR31,
output VAR12,
output VAR1,
output VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor3/sky130_fd_sc_hdll__nor3.blackbox.v | 1,296 | module MODULE1 (
VAR4,
VAR6,
VAR1,
VAR5
);
output VAR4;
input VAR6;
input VAR1;
input VAR5;
supply1 VAR7;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.behavioral.v | 8,998 | module MODULE1( VAR9, VAR17, VAR69, VAR40, VAR11 );
input VAR9, VAR17, VAR40, VAR69;
output VAR11;
reg VAR32;
VAR54 VAR89(.VAR9(VAR9),.VAR17(VAR17),.VAR69(VAR69),.VAR40(VAR40),.VAR11(VAR11),.VAR32(VAR32));
VAR54 VAR39(.VAR9(VAR9),.VAR17(VAR17),.VAR69(VAR69),.VAR40(VAR40),.VAR11(VAR11),.VAR32(VAR32));
not VAR80(VAR55,VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211o/sky130_fd_sc_hdll__a211o.pp.symbol.v | 1,380 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR3 ,
input VAR4 ,
output VAR9 ,
input VAR5 ,
input VAR8,
input VAR1,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.functional.v | 1,578 | module MODULE1 (
VAR9 ,
VAR3,
VAR1,
VAR5
);
output VAR9 ;
output VAR3;
input VAR1;
input VAR5 ;
wire VAR4;
VAR7 VAR2 VAR8 (VAR4 , VAR5, VAR1 );
buf VAR6 (VAR9 , VAR4 );
not VAR10 (VAR3 , VAR4 );
endmodule | apache-2.0 |
saisrivathsa/Image-Watermarking | Generation.v | 1,336 | module MODULE1(
input clk,
output [1:0] VAR12
);
parameter VAR2 = 8'b01101010;
wire [7:0] VAR10, VAR11;
wire [7:0] VAR13;
assign VAR12[1] = VAR10[1]^VAR10[0];
assign VAR12[0] = (VAR12[1]==1)? 0 : VAR10[0];
VAR4 #(VAR2[0]) VAR1(clk,VAR13[0],VAR10[0],VAR11[0]);
VAR4 #(VAR2[1]) VAR7(clk,VAR13[1],VAR10[1],VAR11[1]);
VAR4 #... | mit |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/ip/TARASIC_SPI_3WIRE/gsensor_fifo_bb.v | 6,302 | module MODULE1 (
VAR8,
VAR10,
VAR9,
VAR11,
VAR7,
VAR5,
VAR6,
VAR3,
VAR2,
VAR1,
VAR4);
input VAR8;
input [7:0] VAR10;
input VAR9;
input VAR11;
input VAR7;
input VAR5;
output [7:0] VAR6;
output VAR3;
output [3:0] VAR2;
output VAR1;
output [3:0] VAR4;
tri0 VAR8;
endmodule | gpl-2.0 |
8l/beri | cherilibs/trunk/BRAM2Load.v | 3,947 | module MODULE1(VAR10,
VAR17,
VAR4,
VAR16,
VAR5,
VAR8,
VAR6,
VAR3,
VAR15,
VAR14,
VAR21,
VAR23
);
parameter VAR22 = "";
parameter VAR13 = 0;
parameter VAR11 = 1;
parameter VAR9 = 1;
parameter VAR1 = 1;
parameter VAR20 = 0;
input VAR10;
input VAR17;
input VAR4;
input [VAR11-1:0] VAR16;
input [VAR9-1:0] VAR5;
output [VAR9-... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/altera_avalon_st_clock_crosser.v | 4,882 | module MODULE1(
VAR21,
VAR1,
VAR14,
VAR2,
VAR25,
VAR12,
VAR30,
VAR20,
VAR26,
VAR4
);
parameter VAR11 = 1;
parameter VAR13 = 8;
parameter VAR7 = 2;
parameter VAR18 = 2;
parameter VAR16 = 1;
localparam VAR29 = VAR11 * VAR13;
input VAR21;
input VAR1;
output VAR14;
input VAR2;
input [VAR29-1:0] VAR25;
input VAR12;
input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.behavioral.v | 1,572 | module MODULE1 (
VAR6 ,
VAR8,
VAR10,
VAR7,
VAR9,
VAR1
);
output VAR6 ;
input VAR8;
input VAR10;
input VAR7;
input VAR9;
input VAR1;
supply1 VAR4;
supply0 VAR13;
supply1 VAR3 ;
supply0 VAR12 ;
wire VAR5 ;
wire VAR15;
and VAR2 (VAR5 , VAR8, VAR10, VAR7, VAR9 );
nor VAR11 (VAR15, VAR1, VAR5 );
buf VAR14 (VAR6 , VAR15 );
e... | apache-2.0 |
cmos3511/cmos_linux | python/pj/proj/rtl/LP/cla.v | 4,991 | module MODULE4(VAR9,VAR23,VAR27,VAR3,VAR24,VAR10);
output VAR9,VAR23; output [3:0] VAR27; input [3:0] VAR3,VAR24; input VAR10;
wire [3:0] VAR5 = VAR3 | VAR24;
wire [3:0] VAR19 = VAR3 & VAR24;
wire VAR14 = VAR19[0] | VAR5[0]&VAR10;
wire VAR2 = VAR19[1] | VAR5[1]&VAR14;
wire VAR15 = VAR19[2] | VAR5[2]&VAR2;
wire [3:0] VA... | gpl-3.0 |
praveendath92/securePUF | source/puf_files/back_up/pdl_switch.v | 1,064 | module MODULE1(VAR10, VAR5, VAR2, VAR3, o1, o2);
input VAR10, VAR5;
input VAR2, VAR3;
output o1, o2;
VAR4 VAR8 (.VAR9(VAR10), .VAR1(o1), .VAR7(VAR2));
VAR4 VAR6 (.VAR9(VAR5), .VAR1(o2), .VAR7(VAR3));
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb.behavioral.v | 1,523 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR5 ,
VAR9,
VAR11
);
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR9;
input VAR11;
supply1 VAR6;
supply0 VAR7;
supply1 VAR10 ;
supply0 VAR8 ;
wire VAR14 ;
wire VAR2;
nor VAR12 (VAR14 , VAR1, VAR5 );
and VAR4 (VAR2, VAR14, VAR9, VAR11);
buf VAR13 (VAR3 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2.symbol.v | 1,266 | module MODULE1 (
input VAR1,
input VAR6,
output VAR2
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor3/sky130_fd_sc_ms__xor3.pp.blackbox.v | 1,322 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR8 ,
VAR5 ,
VAR3,
VAR7,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR3;
input VAR7;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf_16.v | 1,999 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR5,
VAR2,
VAR6 ,
VAR3
);
output VAR8 ;
input VAR7 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR3 ;
VAR1 VAR4 (
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR8,
VAR7
);
output VAR8;
input VAR7;
supply1 VAR5;
supply0 VAR2;... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_init_ctrl_7vx.v | 14,233 | module MODULE1 # (
parameter VAR24 = 100,
parameter VAR38 = "VAR16"
) (
input VAR20,
output VAR36, output VAR9, output VAR11, output VAR18,
input VAR47, input VAR31,
input VAR14, output VAR23, input VAR21, output VAR37,
input VAR5,
output [2:0] VAR28
);
localparam VAR42 = 3'b000;
localparam VAR4 = 3'b001;
localparam VA... | gpl-3.0 |
litex-hub/pythondata-cpu-lm32 | pythondata_cpu_lm32/verilog/rtl/lm32_mc_arithmetic.v | 10,282 | module MODULE1 (
VAR21,
VAR1,
VAR10,
VAR13,
VAR6,
VAR12,
VAR4,
VAR32,
VAR24,
VAR34,
VAR2,
VAR18,
VAR29,
VAR20,
VAR27
);
input VAR21; input VAR1; input VAR10; input VAR13; VAR33 VAR9
input VAR6; input VAR12; VAR22
input VAR4; VAR22
input VAR32; input VAR24; input VAR34; VAR22
input [VAR28] VAR2;
input [VAR28] VAR18;
out... | epl-1.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31o/sky130_fd_sc_ls__a31o.pp.symbol.v | 1,366 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR6 ,
input VAR9 ,
output VAR3 ,
input VAR5 ,
input VAR2,
input VAR7,
input VAR8
);
endmodule | apache-2.0 |
kevintownsend/R3 | verilog/cae_pers.v | 25,154 | module MODULE1 (
input VAR133,
input clk,
input VAR157,
input VAR52,
input VAR39,
input [1:0] VAR50,
input VAR124,
output VAR74,
output VAR167,
input [31:0] VAR211,
input [63:0] VAR218,
input VAR60,
output [17:0] VAR5,
output [15:0] VAR35,
output [63:0] VAR127,
output VAR96,
output VAR91,
output VAR145,
output VAR230, ... | mit |
freecores/altor32 | rtl/soc/soc.v | 7,323 | module MODULE1
(
VAR89,
VAR32,
VAR57,
VAR62,
VAR67,
VAR82,
VAR92,
VAR54,
VAR17,
VAR4
);
parameter [31:0] VAR22 = 12288;
parameter [31:0] VAR13 = 1;
parameter VAR21 = 1;
parameter VAR43 = "VAR19";
parameter VAR85 = "VAR19";
input VAR89 ;
input VAR32 ;
input [(VAR13 - 1):0] VAR57 ;
output VAR62 ;
input [31:0] VAR67 ;
inp... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4b/sky130_fd_sc_ms__or4b_4.v | 2,291 | module MODULE2 (
VAR3 ,
VAR1 ,
VAR10 ,
VAR8 ,
VAR11 ,
VAR4,
VAR2,
VAR7 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR10 ;
input VAR8 ;
input VAR11 ;
input VAR4;
input VAR2;
input VAR7 ;
input VAR5 ;
VAR9 VAR6 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.... | apache-2.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_1/hdl/verilog/feedforward_dmul_64ns_64ns_64_6_max_dsp.v | 1,933 | module MODULE1
VAR16 = 1,
VAR13 = 6,
VAR17 = 64,
VAR3 = 64,
VAR5 = 64
)(
input wire clk,
input wire reset,
input wire VAR25,
input wire [VAR17-1:0] VAR6,
input wire [VAR3-1:0] VAR19,
output wire [VAR5-1:0] dout
);
wire VAR1;
wire VAR21;
wire VAR15;
wire [63:0] VAR7;
wire VAR10;
wire [63:0] VAR18;
wire VAR4;
wire [63:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fill/sky130_fd_sc_hd__fill.blackbox.v | 1,166 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
UdayanSinha/Code_Blocks | Nios-2/Nios/practica4/mi_nios/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,705 | module MODULE1 (
clk,
reset,
VAR3,
VAR16,
VAR11,
VAR4,
VAR8,
VAR6
);
parameter VAR14 = 1;
parameter VAR5 = 8;
parameter VAR9 = 1;
localparam VAR7 = VAR14 * VAR5;
input clk;
input reset;
output VAR3;
input VAR16;
input [VAR7-1:0] VAR11;
input VAR4;
output VAR8;
output [VAR7-1:0] VAR6;
reg VAR15;
reg VAR12;
reg [VAR7-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_0.v | 2,097 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR8 ,
VAR6,
VAR1,
VAR2 ,
VAR9
);
output VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR6;
input VAR1;
input VAR2 ;
input VAR9 ;
VAR7 VAR3 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR4,
VAR5,
VAR8
);
output VAR4;
... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_xbar_0/synth/design_1_xbar_0.v | 27,150 | module MODULE1 (
VAR67,
VAR36,
VAR15,
VAR22,
VAR56,
VAR53,
VAR61,
VAR29,
VAR58,
VAR2,
VAR122,
VAR20,
VAR13,
VAR88,
VAR125,
VAR38,
VAR90,
VAR42,
VAR113,
VAR104,
VAR118,
VAR62,
VAR52,
VAR23,
VAR39,
VAR4,
VAR50,
VAR14,
VAR106,
VAR76,
VAR28,
VAR10,
VAR72,
VAR93,
VAR25,
VAR99,
VAR3,
VAR82,
VAR40,
VAR95,
VAR132,
VAR1,
VAR16,... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4SharedKES_0_0/synth/OpenSSD2_Tiger4SharedKES_0_0.v | 10,903 | module MODULE1 (
VAR17,
VAR14,
VAR44,
VAR6,
VAR25,
VAR32,
VAR7,
VAR45,
VAR21,
VAR1,
VAR23,
VAR24,
VAR19,
VAR13,
VAR10,
VAR2,
VAR49,
VAR46,
VAR3,
VAR27,
VAR50,
VAR4,
VAR36,
VAR31,
VAR38,
VAR16,
VAR35,
VAR28,
VAR15,
VAR34,
VAR11,
VAR48,
VAR22,
VAR30,
VAR42,
VAR47,
VAR18,
VAR43,
VAR29,
VAR40,
VAR33,
VAR37
);
input wire VA... | gpl-3.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/Fblock.v | 1,223 | module MODULE1(
input [31:0] VAR12,
input [59:0] VAR3,
output [31:0] VAR7,
input VAR11
);
wire [47:0] VAR10;
wire [47:0] VAR6;
VAR8 VAR1(VAR12, VAR10);
VAR9 VAR5(VAR10, VAR3, VAR6, VAR11);
VAR4 VAR2(VAR6, VAR7);
endmodule | gpl-3.0 |
mbus/mbus | mbus_example/verilog/rstdtctr.v | 1,255 | module MODULE1
(
VAR1
);
output reg VAR1; | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_altmemddr_0_example_driver.v | 31,008 | module MODULE1 (
clk,
VAR66,
VAR9,
VAR82,
VAR1,
VAR64,
VAR42,
VAR87,
VAR77,
VAR33,
VAR18,
VAR90,
VAR26,
VAR50,
VAR89,
VAR19,
VAR83,
VAR76,
VAR88
)
;
output [ 1: 0] VAR64;
output [ 3: 0] VAR42;
output VAR87;
output [ 9: 0] VAR77;
output VAR33;
output VAR18;
output [ 13: 0] VAR90;
output [ 2: 0] VAR26;
output [ 31: 0] VA... | gpl-3.0 |
ShepardSiegel/ocpi | scripts/auguste/bram/BRAM1.v | 2,704 | module MODULE1(VAR6,
VAR3,
VAR4,
VAR5,
VAR10,
VAR12
);
parameter VAR13 = 0;
parameter VAR11 = 1;
parameter VAR2 = 1;
parameter VAR1 = 1;
input VAR6;
input VAR3;
input VAR4;
input [VAR11-1:0] VAR5;
input [VAR2-1:0] VAR10;
output [VAR2-1:0] VAR12;
reg [VAR2-1:0] VAR7[0:VAR1-1];
reg [VAR11-1:0] VAR14;
reg [VAR2-1:0] VAR8;... | lgpl-3.0 |
cpulabs/hdl_square_root | src/square_root32_element.v | 2,029 | module MODULE1 #(
parameter VAR19 = 4,
parameter VAR15 = 1
)(
input wire VAR3,
input wire VAR5,
input wire VAR16,
output wire VAR11,
input wire [VAR19/2-1:0] VAR6,
input wire [31:0] VAR1,
output wire VAR9,
input wire VAR17,
output wire [VAR19/2-1:0] VAR8,
output wire [31:0] VAR10
);
function [VAR19/2-1:0] VAR13;
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4.behavioral.pp.v | 1,861 | module MODULE1 (
VAR15,
VAR1,
VAR2 ,
VAR14 ,
VAR12 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR13
);
input VAR15;
input VAR1;
output VAR2 ;
input VAR14 ;
input VAR12 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR13 ;
wire VAR4 ;
wire VAR8;
VAR9 VAR16 (VAR4 , VAR14, VAR12, VAR7, VAR6, VAR3, VAR13 );
VAR11 VAR10 (VAR8, VAR4, VAR15, VA... | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_rst_clk_wiz_1_100M_0/system_rst_clk_wiz_1_100M_0_stub.v | 1,808 | module MODULE1(VAR7, VAR10, VAR2,
VAR8, VAR6, VAR4, VAR1, VAR3,
VAR9, VAR5)
;
input VAR7;
input VAR10;
input VAR2;
input VAR8;
input VAR6;
output VAR4;
output [0:0]VAR1;
output [0:0]VAR3;
output [0:0]VAR9;
output [0:0]VAR5;
endmodule | apache-2.0 |
seyedmaysamlavasani/GorillaPP | apps/multiProtocolNpu/build/synthesis/asic/FreePDK45/osu_soc/ref_design/Synthesis/basic_components.v | 2,024 | module MODULE1 (sum, VAR4, VAR17, VAR5, VAR19, VAR13);
output sum;
output VAR4;
output VAR17;
input VAR5;
input VAR19;
input VAR13;
xor VAR16(sum, VAR5, VAR19, VAR13);
and VAR20(VAR4, VAR5, VAR19);
or o1(VAR17, VAR5, VAR19);
endmodule
module MODULE5 (VAR26, VAR21, clk, reset);
output [16:0] VAR26;
input [16:0] VAR21;
i... | bsd-3-clause |
twlostow/dsi-shield | hdl/rtl/hpdmc/hpdmc_datactl.v | 3,570 | module MODULE1(
input VAR1,
input VAR6,
input read,
input write,
input [3:0] VAR18,
output reg VAR14,
output reg VAR15,
output [3:0] VAR3,
output reg VAR5,
output VAR17,
input VAR13,
input [1:0] VAR8
);
reg [2:0] VAR4;
always @(posedge VAR1) begin
if(VAR6) begin
VAR4 <= 3'd0;
VAR14 <= 1'b1;
end else begin
if(read) begi... | lgpl-3.0 |
omicronns/studies-sys-rek | de1-soc/src/lbp/lbp.v | 4,356 | module MODULE1 #(
parameter VAR7 = 3,
parameter VAR27 = 12,
parameter VAR33 = 800
)(
input VAR2,
input [7:0] VAR17,
input [7:0] VAR6,
input [7:0] VAR22,
input VAR28,
input VAR25,
input VAR19,
input VAR32,
output [7:0] VAR4,
output VAR21,
output VAR26,
output VAR13,
output VAR16
);
wire [7:0] VAR34;
wire VAR29;
wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai.functional.pp.v | 2,212 | module MODULE1 (
VAR18 ,
VAR12 ,
VAR5 ,
VAR9 ,
VAR16 ,
VAR1 ,
VAR19,
VAR6,
VAR3 ,
VAR4
);
output VAR18 ;
input VAR12 ;
input VAR5 ;
input VAR9 ;
input VAR16 ;
input VAR1 ;
input VAR19;
input VAR6;
input VAR3 ;
input VAR4 ;
wire VAR15 ;
wire VAR14 ;
wire VAR11 ;
wire VAR8;
or VAR10 (VAR15 , VAR16, VAR9 );
or VAR7 (VAR14... | apache-2.0 |
CospanDesign/sdio-device | rtl/phy/sdio_phy.v | 7,892 | module MODULE1 (
input rst,
input VAR23,
input VAR30,
input VAR22,
input VAR32,
input VAR31,
output VAR38,
output reg VAR53,
output reg VAR64,
output reg VAR49,
output reg [5:0] VAR33,
output reg [31:0] VAR40,
input VAR10,
input [39:0] VAR59,
input [7:0] VAR45,
input VAR11,
output reg VAR18,
input VAR54,
input VAR60,
o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.pp.blackbox.v | 1,423 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR8,
VAR7,
VAR9 ,
VAR3
);
output VAR10 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR8;
input VAR7;
input VAR9 ;
input VAR3 ;
endmodule | apache-2.0 |
kyflores/ice-mc | rtl/cordic.v | 2,708 | module MODULE1(
clk,
VAR12, VAR2, VAR15, VAR1,
VAR11
);
parameter VAR14 = 16;
parameter VAR13 = 32;
parameter VAR10 = "../VAR3/VAR8.VAR7";
input clk;
input signed[VAR14-1:0] VAR12, VAR2;
input signed[VAR13-1:0] VAR15;
output signed[VAR14-1:0] VAR1, VAR11;
reg signed[VAR14-1:0] VAR9[VAR14:0]; reg signed[VAR14-1:0] VAR4[... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl_1.v | 2,343 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2 ,
VAR7 ,
VAR6,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR7 ;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR8 VAR9 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1,
VAR4
);
output VAR1;
inpu... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/usbSlaveControl.v | 14,805 | module MODULE1(
VAR44,
VAR55,
VAR5,
VAR73,
VAR87, VAR9, VAR181,
VAR66, VAR83, VAR143,
VAR163, VAR33,
VAR183,
VAR63, VAR43,
VAR195, VAR81,
VAR2,
VAR31,
VAR1,
VAR182,
VAR122,
VAR109,
VAR102,
VAR23,
VAR37,
VAR175,
VAR8,
VAR112,
VAR103,
VAR120,
VAR57,
VAR24,
VAR126,
VAR151,
VAR145,
VAR134,
VAR61,
VAR35,
VAR3,
VAR144,
VAR36... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_cmos2_pad_up.v | 2,546 | module MODULE1(VAR10 ,VAR25 ,VAR21 ,VAR30 ,VAR29, VAR12 );
output VAR21 ;
input VAR10 ;
input VAR25 ;
input VAR29 ;
inout VAR30 ;
input VAR12 ;
supply1 VAR18 ;
supply0 VAR26 ;
wire VAR8 ;
wire VAR24 ;
wire VAR7 ;
wire VAR4 ;
wire VAR17 ;
wire VAR19 ;
VAR1 VAR16 (
.VAR8 (VAR8 ),
.VAR21 (VAR21 ),
.VAR9 (VAR26 ),
.VAR23 (... | gpl-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab1/Lab1-Project/EECS301_Lab1_TopLevel.v | 2,352 | module MODULE1
(
input VAR4,
output [9:0] VAR6,
output [6:0] VAR2, output [6:0] VAR12, output [6:0] VAR13, output [6:0] VAR10, output [6:0] VAR5, output [6:0] VAR7,
input [3:0] VAR3
);
reg [3:0] VAR8;
always @(posedge VAR4)
begin
VAR8 <= ~VAR3;
end
reg VAR11;
always @(posedge VAR4)
begin
VAR11 <= &VAR8;
end
assign VAR6... | mit |
hoglet67/CoPro6502 | src/NextZ80/NextZ80CPU.v | 50,979 | module MODULE1
(
input wire[7:0] VAR93,
output wire[7:0] VAR6,
output wire[15:0] VAR62,
output reg VAR3,
output reg VAR30,
output reg VAR16,
output reg VAR67,
output reg VAR54,
input wire VAR26,
input wire VAR58,
input wire VAR108,
input wire VAR66,
input wire VAR40
);
reg [9:0] VAR69 = 0; wire [7:0] VAR57;
wire [7:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.symbol.v | 1,314 | module MODULE1 (
input VAR1 ,
output VAR7 ,
input VAR4
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn.behavioral.v | 1,764 | module MODULE1 (
VAR2 ,
VAR6,
VAR3 ,
VAR5,
VAR8
);
input VAR2 ;
input VAR6;
output VAR3 ;
input VAR5;
input VAR8;
wire VAR9 ;
wire VAR11;
VAR10 VAR4 (VAR9 , VAR2, VAR5, VAR8 );
VAR10 VAR1 (VAR11, VAR6, VAR5, VAR8 );
bufif0 VAR7 (VAR3 , VAR9, VAR11);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.pp.blackbox.v | 3,707 | module MODULE1 (
VAR25 ,
VAR4 ,
VAR14 ,
VAR20 ,
VAR24 ,
VAR21 ,
VAR33 ,
VAR19 ,
VAR22 ,
VAR10 ,
VAR17 ,
VAR26,
VAR36 ,
VAR11 ,
VAR23 ,
VAR5 ,
VAR41 ,
VAR39 ,
VAR1 ,
VAR18 ,
VAR7 ,
VAR28 ,
VAR2 ,
VAR12 ,
VAR38 ,
VAR34 ,
VAR37 ,
VAR35 ,
VAR16 ,
VAR15 ,
VAR9 ,
VAR30 ,
VAR32 ,
VAR13 ,
VAR27 ,
VAR31 ,
VAR8 ,
VAR6 ,
VAR3 ,
V... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_qmem_top.v | 13,643 | module MODULE1(
clk, rst,
VAR2, VAR70, VAR6,
VAR51,
VAR59,
VAR21,
VAR66,
VAR47,
VAR25,
VAR46,
VAR61,
VAR9,
VAR26,
VAR24,
VAR38,
VAR71,
VAR54,
VAR20,
VAR74,
VAR73,
VAR68,
VAR13,
VAR1,
VAR15,
VAR5,
VAR31,
VAR53,
VAR33,
VAR67,
VAR10,
VAR22,
VAR37,
VAR27,
VAR63,
VAR78,
VAR8,
VAR50,
VAR17,
VAR75,
VAR65,
VAR34,
VAR64,
VAR40,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR12 ,
VAR14 ,
VAR15 ,
VAR9 ,
VAR7 ,
VAR3 ,
VAR2,
VAR18,
VAR19 ,
VAR13
);
output VAR12 ;
output VAR14 ;
input VAR15 ;
input VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR2;
input VAR18;
input VAR19 ;
input VAR13 ;
wire VAR1 ;
wire VAR16;
VAR5 VAR11 (VAR16, VAR9, VAR7, VAR3 );
VAR6 VAR8 VAR10 (VAR1 , VAR16... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb_1.v | 2,323 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR8 ,
VAR10 ,
VAR1 ,
VAR7,
VAR3,
VAR11 ,
VAR6
);
output VAR9 ;
input VAR5 ;
input VAR8 ;
input VAR10 ;
input VAR1 ;
input VAR7;
input VAR3;
input VAR11 ;
input VAR6 ;
VAR4 VAR2 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR11(VAR11),
.... | apache-2.0 |
yanhongwang/ColorImage | BackwardSpace/BackwardSpace.v | 4,401 | module MODULE1(
input[ VAR5 - 1 : 0 ]VAR2,
input signed[ VAR5 - 1 : 0 ]VAR15,
input signed[ VAR5 - 1 : 0 ]VAR25,
output reg[ VAR5 - 1 : 0 ]VAR29,
output reg[ VAR5 - 1 : 0 ]VAR7,
output reg[ VAR5 - 1 : 0 ]VAR21
);
reg[ VAR5 - 1 : 0 ]VAR17;
reg[ VAR5 - 1 : 0 ]VAR20;
reg[ VAR5 - 1 : 0 ]VAR30;
reg[ VAR5 - 1 : 0 ]VAR1;
reg[... | mit |
m13253/riscade | hdl/src/top.v | 4,760 | module MODULE1(clk, rst, VAR16, VAR3, VAR25, VAR20);
input clk;
input rst;
output[7:0] VAR16;
output[7:0] VAR3;
output VAR25, VAR20;
tri1 VAR25, VAR20;
wire[7:0] VAR16;
wire[7:0] VAR3;
memory memory(
.clk(clk), .rst(rst),
.VAR14(VAR25), .VAR68(VAR20),
.VAR16(VAR16),
.VAR3(VAR3)
);
wire[7:0] VAR42[5:0], VAR10[5:0];
tri1... | mit |
erevejach14/Arquitectura | ROM.srcs/sources_1/new/ROM.v | 3,491 | module MODULE1(input clk,
input wire [8:0] addr,
output reg [7:0] VAR1);
reg [7:0] VAR2 [0:127];
always @(negedge clk) begin
VAR1 <= VAR2[addr];
end | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,589 | module MODULE1 (
VAR49,
VAR33,
clk,
VAR7,
VAR44,
VAR5,
VAR36,
VAR38,
VAR22,
VAR12,
VAR13,
VAR52,
VAR4,
VAR25,
VAR35,
VAR43,
VAR41,
VAR14,
VAR39,
VAR34,
VAR9,
VAR6,
VAR19,
VAR40,
VAR32,
VAR54,
VAR15,
VAR8,
VAR20,
VAR11,
VAR17,
VAR27,
VAR29
)
;
output [ 37: 0] VAR9;
output VAR6;
output VAR19;
output VAR40;
output VAR32;
... | gpl-3.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/SD_DAT.v | 2,631 | module MODULE1 (
address,
VAR7,
clk,
VAR9,
VAR10,
VAR6,
VAR3,
VAR11
)
;
inout VAR3;
output [ 31: 0] VAR11;
input [ 1: 0] address;
input VAR7;
input clk;
input VAR9;
input VAR10;
input [ 31: 0] VAR6;
wire VAR3;
wire VAR2;
reg VAR8;
wire VAR1;
reg VAR12;
wire VAR5;
reg [ 31: 0] VAR11;
assign VAR2 = 1;
assign VAR5 = ({1 {... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_alu_dpath.v | 17,294 | module MODULE1(
input VAR144,
input VAR124 ,
input VAR31 ,
input VAR57 ,
input VAR38 ,
input VAR122 ,
input VAR54 ,
input VAR68 ,
input VAR56 ,
input VAR133 ,
input VAR134,
input VAR123 ,
input [VAR55-1:0] VAR15,
input [VAR55-1:0] VAR125,
output [VAR55-1:0] VAR105,
input VAR12,
input [VAR55-1:0] VAR50,
input [VAR55-1:0... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/traffic_gen/data_prbs_gen.v | 4,609 | module MODULE1 #
(
parameter VAR2 = 100,
parameter VAR11 = "VAR12",
parameter VAR4 = 32, parameter VAR1 = 32
)
(
input VAR8,
input VAR7,
input VAR6,
input [31:0] VAR14,
input VAR5, input [VAR4 - 1:0] VAR15,
output [VAR4 - 1:0] VAR3 );
reg [VAR4 - 1 :0] VAR13;
reg [VAR4 :1] VAR10;
integer VAR9;
always @ (posedge VAR8)
b... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand4/gf180mcu_fd_sc_mcu7t5v0__nand4_2.functional.v | 1,390 | module MODULE1( VAR6, VAR3, VAR1, VAR5, VAR7 );
input VAR1, VAR7, VAR3, VAR5;
output VAR6;
wire VAR13;
not VAR14( VAR13, VAR1 );
wire VAR11;
not VAR10( VAR11, VAR7 );
wire VAR8;
not VAR9( VAR8, VAR3 );
wire VAR4;
not VAR12( VAR4, VAR5 );
or VAR2( VAR6, VAR13, VAR11, VAR8, VAR4 );
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/uart16550/rtl/verilog/uart_rfifo.v | 11,025 | module MODULE1 (clk,
VAR9, VAR30, VAR23,
VAR35, VAR11, VAR13,
VAR18,
VAR20,
VAR10,
VAR16
);
parameter VAR21 = VAR17;
parameter VAR7 = VAR33;
parameter VAR40 = VAR27;
parameter VAR39 = VAR46;
input clk;
input VAR9;
input VAR35;
input VAR11;
input [VAR21-1:0] VAR30;
input VAR10;
input VAR16;
output [VAR21-1:0] VAR23;
out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi_1.v | 2,457 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR10 ,
VAR4 ,
VAR12,
VAR11,
VAR3 ,
VAR2
);
output VAR9 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR12;
input VAR11;
input VAR3 ;
input VAR2 ;
VAR5 VAR7 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR12(... | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaPortRead.v | 2,411 | module MODULE1(
input wire reset,
input wire VAR14,
input wire VAR12, input wire VAR11, output wire [31:0] VAR20,
output wire VAR3, output wire VAR1,
output wire VAR17, output wire VAR21,
inout [31:0] VAR6, input wire [(VAR10+2):0] VAR5, output wire [1:0] VAR16 );
parameter VAR13 = 0;
parameter VAR10 = 2;
wire VAR18 = ... | gpl-2.0 |
zhelnio/mil1553-spi | src/board/DE0/DE0_TOP.v | 10,678 | module MODULE1
(
VAR35, VAR25, VAR81, VAR80, VAR64, VAR63, VAR24, VAR75, VAR2, VAR71, VAR87, VAR68, VAR9, VAR40, VAR90, VAR7, VAR72, VAR41, VAR37, VAR77, VAR18, VAR66, VAR33, VAR23, VAR58, VAR61, VAR98, VAR45, VAR53, VAR59, VAR8, VAR22, VAR76, VAR17, VAR49, VAR14, VAR52, VAR11, VAR95, VAR28, VAR4, VAR56, VAR6, VAR32, V... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_example_top.v | 7,594 | module MODULE1 (
VAR47,
VAR53,
VAR23,
VAR28,
VAR21,
VAR20,
VAR8,
VAR18,
VAR74,
VAR33,
VAR50,
VAR72,
VAR7,
VAR5,
VAR41,
VAR65,
VAR22,
VAR46,
VAR25,
VAR9,
VAR34
)
;
output [ 12: 0] VAR23;
output [ 2: 0] VAR28;
output VAR21;
output [ 0: 0] VAR20;
inout [ 0: 0] VAR8;
inout [ 0: 0] VAR18;
output [ 0: 0] VAR74;
output [ 0: 0... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvn/sky130_fd_sc_ls__einvn_8.v | 2,150 | module MODULE1 (
VAR1 ,
VAR8 ,
VAR6,
VAR4,
VAR2,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR8 ;
input VAR6;
input VAR4;
input VAR2;
input VAR5 ;
input VAR3 ;
VAR7 VAR9 (
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR1 ,
VAR8 ,
VAR6
);
output VAR1 ;... | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/Final/single_cycle/risc_t.v | 9,546 | module MODULE1;
parameter VAR8 = 32;
parameter VAR42 = 32;
parameter VAR24 = 2048;
parameter VAR28 = 7;
parameter VAR30 = 5;
parameter VAR29 = 15;
parameter period = 20;
parameter delay = 1;
parameter VAR38 = "01gcdplain-VAR43.VAR51";
parameter VAR32 = "01gcdplain-VAR3.VAR51";
parameter VAR48 = "VAR36.VAR46";
parameter... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_6sig_x2_async.v | 8,721 | module MODULE1(VAR27 ,VAR49 ,
VAR59 ,VAR112 ,VAR30 ,VAR73 ,VAR33
,VAR10 ,VAR80 ,VAR118 ,VAR104 ,VAR102 ,VAR90 ,
VAR116 ,VAR53 ,VAR61 ,VAR107 ,VAR37
,VAR8 ,VAR38 ,VAR84 ,VAR65 ,VAR121 ,VAR115 ,
VAR43 ,VAR51 ,VAR110 ,VAR89 ,
VAR34 ,VAR106 ,
VAR25 ,VAR70 ,VAR2 , VAR29,
VAR26 ,VAR87 ,VAR24 ,
VAR68 ,VAR1 ,VAR42 ,VAR55 ,VAR1... | gpl-2.0 |
titorgalaxy/Titor | rtl/verilog/core/ALU.v | 3,987 | module MODULE1 (
VAR7,
VAR34,
VAR4,
VAR51,
VAR19,
VAR27,
VAR23,
VAR38
);
output reg [VAR45-1:0] VAR7;
input [VAR45-1:0] VAR34;
input [VAR45-1:0] VAR4;
input [VAR36-1:0] VAR51;
input [VAR45-1:0] VAR19;
input [VAR45-1:0] VAR27;
output reg [VAR45-1:0] VAR23;
output reg [VAR45-1:0] VAR38;
reg [(2*VAR45)-1:0] VAR46;
reg VAR... | gpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/3-execution/alu_control.v | 2,372 | module MODULE1(
input [5:0] VAR3,
input [5:0] VAR1,
output wire [3:0] VAR2
);
assign VAR2 = (VAR3 == 6'b000100) ? 4'b0001 : (VAR3 == 6'b000101) ? 4'b0001 : (VAR3 == 6'b001000) ? 4'b0000 : (VAR3 == 6'b001010) ? 4'b0110 : (VAR3 == 6'b001100) ? 4'b0010 : (VAR3 == 6'b001101) ? 4'b0011 : (VAR3 == 6'b001110) ? 4'b0100 : (VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31oi/sky130_fd_sc_hd__a31oi.symbol.v | 1,369 | module MODULE1 (
input VAR8,
input VAR9,
input VAR5,
input VAR1,
output VAR7
);
supply1 VAR3;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_custom_add_ll_hc.v | 1,742 | module MODULE1(VAR4, VAR12, VAR1, VAR2, VAR9, VAR14, VAR3, VAR11, VAR13);
input VAR4, VAR12;
input VAR14, VAR11;
output VAR3, VAR13;
input [31:0] VAR1;
input [31:0] VAR2;
output [31:0] VAR9;
VAR15 VAR8(
.VAR4(VAR4),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR14(VAR14),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR13(... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtn/sky130_fd_sc_hdll__dlrtn.functional.pp.v | 2,053 | module MODULE1 (
VAR16 ,
VAR15,
VAR14 ,
VAR6 ,
VAR11 ,
VAR1 ,
VAR4 ,
VAR8
);
output VAR16 ;
input VAR15;
input VAR14 ;
input VAR6 ;
input VAR11 ;
input VAR1 ;
input VAR4 ;
input VAR8 ;
wire VAR17;
wire VAR2 ;
wire VAR7;
not VAR3 (VAR17 , VAR15 );
not VAR9 (VAR2 , VAR6 );
VAR5 VAR12 VAR10 (VAR7 , VAR14, VAR2, VAR17, , V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a_1.v | 2,248 | module MODULE2 (
VAR9 ,
VAR2 ,
VAR3 ,
VAR10 ,
VAR5,
VAR6,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR2 ;
input VAR3 ;
input VAR10 ;
input VAR5;
input VAR6;
input VAR7 ;
input VAR1 ;
VAR8 VAR4 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_reset_sync.v | 1,937 | module MODULE1(
VAR1,
clk,
VAR6
);
parameter VAR4 = 4;
parameter VAR5 = 1;
input VAR1;
input clk;
output [VAR5-1:0] VAR6;
reg [VAR4+VAR5-2:0] VAR3 ;
generate
genvar VAR7;
for (VAR7=0; VAR7<VAR4+VAR5-1; VAR7=VAR7+1)
begin: VAR2
always @(posedge clk or negedge VAR1)
begin
if (~VAR1)
VAR3[VAR7] <= 1'b0;
end
else
begin
if ... | gpl-3.0 |
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