repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
theapi/nand2tetris_fpga | hack/rtl/verilog/frame_buffer.v | 4,683 | module MODULE1(
input clk,
input [15:0] VAR1,
input [7:0] VAR7, input [14:0] VAR20, input [15:0] VAR27, input [15:0] VAR30, input [15:0] VAR15, input [15:0] VAR32,
input [10:0] VAR19, input [10:0] VAR17,
output [23:0] VAR23, output [12:0] VAR13
);
reg [2:0] out;
wire [4:0] VAR25;
wire [15:0] VAR16;
wire [31:0] VAR12;
a... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N20_R5_P5_with_recovery_syn.v | 4,845 | module MODULE1 ( clk, VAR113, VAR91, VAR16, VAR89,
VAR34, VAR18, VAR111 );
input [19:0] VAR113;
input [19:0] VAR91;
output [20:0] VAR16;
input clk;
output VAR89, VAR34, VAR18, VAR111;
wire VAR124, VAR2, VAR127, VAR84, VAR47,
VAR105, VAR31, VAR74, VAR4, VAR49, VAR102, VAR13, VAR28, VAR71, VAR21, VAR95, VAR88, VAR118, VA... | gpl-3.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/branch_predictor.v | 2,182 | module MODULE1
(
input [VAR1-1:0] VAR3,
input [VAR1-1:0] VAR20,
input VAR42,
input [VAR1-1:0] VAR9,
output VAR47,
output [VAR1-1:0] VAR11,
output [VAR1-1:0] VAR24
);
wire [5:0] VAR10;
wire [5:0] VAR14;
wire [15:0] VAR5;
wire [25:0] VAR30;
wire VAR15, VAR41, VAR38, VAR44, VAR12;
wire [VAR1-1:0] VAR34;
decoder decoder (
... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_013.v | 1,527 | module MODULE1 (
VAR10,
VAR4
);
input [31:0] VAR10;
output [31:0]
VAR4;
wire [31:0]
VAR8,
VAR3,
VAR9,
VAR7,
VAR14,
VAR6,
VAR2,
VAR5,
VAR13;
assign VAR8 = VAR10;
assign VAR9 = VAR3 - VAR8;
assign VAR3 = VAR8 << 10;
assign VAR13 = VAR2 + VAR5;
assign VAR5 = VAR9 << 2;
assign VAR14 = VAR7 - VAR8;
assign VAR7 = VAR8 << 6;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o311ai/sky130_fd_sc_hs__o311ai_1.v | 2,308 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR1 ,
VAR5 ,
VAR3 ,
VAR2 ,
VAR8,
VAR10
);
output VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR5 ;
input VAR3 ;
input VAR2 ;
input VAR8;
input VAR10;
VAR9 VAR4 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
ThomasLee969/verilog-homework | big_homework/cpu/ALUControl.v | 1,272 | module MODULE1(VAR11, VAR7, VAR4, VAR3);
input [3:0] VAR11;
input [5:0] VAR7;
output reg [4:0] VAR4;
output VAR3;
parameter VAR6 = 5'b00000;
parameter VAR9 = 5'b00001;
parameter VAR10 = 5'b00010;
parameter VAR5 = 5'b00110;
parameter VAR15 = 5'b00111;
parameter VAR13 = 5'b01100;
parameter VAR2 = 5'b01101;
parameter VAR8... | mit |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | Erosion/ip/Erosion/acl_fp_custom_add_ll.v | 1,632 | module MODULE1(VAR13, enable, VAR6, VAR3, VAR4, VAR8);
input VAR13, enable, VAR6;
input [31:0] VAR3;
input [31:0] VAR4;
output [31:0] VAR8;
VAR9 VAR12(
.VAR13(VAR13),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(),
.VAR1(),
.VAR15(),
.VAR11(),
.enable(enable));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.behavioral.pp.v | 2,655 | module MODULE1 (
VAR28 ,
VAR29 ,
VAR4 ,
VAR21 ,
VAR25 ,
VAR13 ,
VAR2 ,
VAR1,
VAR19
);
output VAR28 ;
output VAR29 ;
input VAR4 ;
input VAR21 ;
input VAR25 ;
input VAR13 ;
input VAR2 ;
input VAR1;
input VAR19;
wire VAR26 ;
reg VAR9 ;
wire VAR16 ;
wire VAR10 ;
wire VAR7;
wire VAR20;
wire VAR6;
wire VAR23 ;
wire VAR11 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb.functional.v | 1,891 | module MODULE1 (
VAR3,
VAR4,
VAR11 ,
VAR7 ,
VAR15 ,
VAR1 ,
VAR8
);
input VAR3;
input VAR4;
output VAR11 ;
input VAR7 ;
input VAR15 ;
input VAR1 ;
input VAR8 ;
wire VAR8 VAR12 ;
wire VAR2 ;
wire VAR14;
nor VAR13 (VAR12 , VAR7, VAR15 );
and VAR6 (VAR2 , VAR12, VAR1, VAR8 );
VAR9 VAR10 (VAR14, VAR2, VAR3, VAR4);
buf VAR5 ... | apache-2.0 |
LSaldyt/qnp | output/vs/opt_var23_multi.v | 40,772 | module MODULE1(VAR11, VAR1, VAR3, VAR21, VAR12, VAR6, VAR19, VAR5, VAR8, VAR20, VAR9, VAR23, VAR13, VAR10, VAR15, VAR17, VAR2, VAR7, VAR22, VAR16, VAR14, VAR4, VAR18, valid);
wire 0000;
wire 0001;
wire 0002;
wire 0003;
wire 0004;
wire 0005;
wire 0006;
wire 0007;
wire 0008;
wire 0009;
wire 0010;
wire 0011;
wire 0012;
wi... | mit |
archlabo/Frix | fpga/nexys4_ddr/rtl/clock/clk_wiz_0.v | 4,303 | module MODULE1
(
input VAR1,
output VAR2,
output VAR4,
output VAR6,
output VAR5
);
VAR3 VAR7
(
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule | bsd-2-clause |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_schist.v | 5,658 | module MODULE1(
input wire VAR91, input wire VAR38, input wire VAR19, input wire VAR83, input wire VAR112, input wire VAR4, input wire VAR22, output wire [7:0] VAR107, output wire [7:0] VAR14,
input wire [7:0] VAR17,
input wire [7:0] VAR106,
output wire [2:0] VAR75,
input wire VAR41,
input wire VAR50,
input wire VAR33,... | lgpl-3.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_broadcast.v | 7,399 | module MODULE1 #
(
parameter VAR24 = 4,
parameter VAR33 = 8,
parameter VAR20 = (VAR33>8),
parameter VAR4 = (VAR33/8),
parameter VAR47 = 1,
parameter VAR41 = 0,
parameter VAR37 = 8,
parameter VAR21 = 0,
parameter VAR22 = 8,
parameter VAR12 = 1,
parameter VAR1 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR33-1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o32ai/sky130_fd_sc_hd__o32ai_2.v | 2,441 | module MODULE2 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR6 ,
VAR10 ,
VAR5 ,
VAR12,
VAR2,
VAR7 ,
VAR1
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR6 ;
input VAR10 ;
input VAR5 ;
input VAR12;
input VAR2;
input VAR7 ;
input VAR1 ;
VAR3 VAR11 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR12(V... | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkLedN210.v | 3,279 | module MODULE1(VAR12,
VAR5,
VAR10,
VAR13,
VAR7,
VAR16);
input VAR12;
input VAR5;
input [4 : 0] VAR10;
input VAR13;
output VAR7;
output [4 : 0] VAR16;
wire [4 : 0] VAR16;
wire VAR7;
reg VAR1;
wire VAR4, VAR3;
reg [31 : 0] VAR14;
wire [31 : 0] VAR18;
wire VAR8;
reg [4 : 0] VAR2;
wire [4 : 0] VAR9;
wire VAR20;
reg [4 : 0]... | lgpl-3.0 |
subleleks/hardware | top.v | 1,657 | module MODULE1(
input VAR52,
input [3:0] VAR39,
input [17:0] VAR50,
output [8:0] VAR27,
output [17:0] VAR9,
output [6:0] VAR13,
output [6:0] VAR25,
output [6:0] VAR29,
output [6:0] VAR14,
output [6:0] VAR48,
output [6:0] VAR32,
output [6:0] VAR23,
output [6:0] VAR53,
inout [35:0] VAR44
);
wire VAR43;
VAR2 VAR15(
.VAR11... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.pp.symbol.v | 1,525 | module MODULE1 (
input VAR9 ,
output VAR1 ,
input VAR7,
input VAR3 ,
input VAR6 ,
input VAR8 ,
input VAR4 ,
input VAR2 ,
input VAR10 ,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.functional.pp.v | 1,844 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR4 ,
VAR12 ,
VAR14,
VAR9,
VAR7 ,
VAR3
);
output VAR1 ;
input VAR6 ;
input VAR4 ;
input VAR12 ;
input VAR14;
input VAR9;
input VAR7 ;
input VAR3 ;
wire VAR2 ;
wire VAR8;
nor VAR10 (VAR2 , VAR12, VAR6, VAR4 );
VAR13 VAR5 (VAR8, VAR2, VAR14, VAR9);
buf VAR11 (VAR1 , VAR8 );
endmodule | apache-2.0 |
tommythorn/yari | shared/rtl/altera/cyclone/logshiftright.v | 4,062 | module MODULE1 (
VAR9,
VAR5,
VAR3);
input [4:0] VAR9;
input [31:0] VAR5;
output [31:0] VAR3;
wire [31:0] VAR6;
wire VAR10 = 1'h1;
wire [31:0] VAR3 = VAR6[31:0];
VAR14 VAR7 (
.VAR9 (VAR9),
.VAR1 (VAR10),
.VAR5 (VAR5),
.VAR3 (VAR6));
VAR7.VAR12 = "VAR13",
VAR7.VAR11 = "VAR2",
VAR7.VAR4 = 32,
VAR7.VAR8 = 5;
endmodule | gpl-2.0 |
borti4938/n64rgb | advancedRGBmod/firmware/rtl/n64adv_top.v | 5,144 | module MODULE1 (
VAR44,
VAR8,
VAR38,
VAR24,
VAR47,
VAR29,
VAR62,
VAR43,
VAR54,
VAR63,
VAR49,
VAR26,
VAR64, VAR10,
VAR61, VAR12, VAR42, VAR39, VAR37
);
parameter [3:0] VAR13 = 4'd1;
parameter [7:0] VAR59 = 8'd67;
input VAR44;
input VAR8;
input [VAR15-1:0] VAR38;
input VAR24;
input VAR47;
inout VAR29;
output VAR62;
outpu... | gpl-3.0 |
kernelpanics/Grad | CORDIC-Natural-Logarithm/Verilog/UART/Transmisor.v | 2,491 | module MODULE1#(parameter VAR12=8, VAR11=16)(
input wire clk, reset,
input wire VAR2, VAR3,
input wire [7:0] din,
output reg VAR1=0,
output wire VAR19
);
localparam [1:0]
VAR15 = 2'b00,
VAR4 = 2'b01,
VAR7 = 2'b10,
VAR9 = 2'b11;
reg [1:0] VAR16=0, VAR20=0;
reg [3:0] VAR10=0, VAR17=0;
reg [2:0] VAR13=0, VAR6=0;
reg [7:0]... | gpl-3.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_pixelq_op_0_0/synth/tutorial_pixelq_op_0_0.v | 10,168 | module MODULE1 (
VAR29,
VAR26,
VAR9,
VAR32,
VAR33,
VAR34,
VAR23,
VAR40,
VAR3,
VAR20,
VAR2,
VAR38,
VAR17,
VAR11,
VAR18,
VAR37,
VAR1,
interrupt,
VAR28,
VAR7,
VAR21,
VAR5,
VAR15,
VAR22,
VAR25,
VAR6,
VAR14,
VAR12,
VAR8,
VAR24,
VAR36,
VAR35,
VAR19,
VAR39,
VAR4,
VAR13,
VAR16,
VAR10
);
input wire [4 : 0] VAR29;
input wire VAR... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_DATA_I.v | 2,169 | module MODULE1 (
address,
VAR1,
clk,
VAR5,
VAR6,
VAR9,
VAR3,
VAR4
)
;
output [ 8: 0] VAR3;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR5;
input VAR6;
input [ 31: 0] VAR9;
wire VAR8;
reg [ 8: 0] VAR7;
wire [ 8: 0] VAR3;
wire [ 8: 0] VAR2;
wire [ 31: 0] VAR4;
assign VAR8 = 1;
assign VAR2 ... | gpl-3.0 |
RobotClubKut/RobotClubRepeat | UART-HUB/UART-HUB.cydsn/CRC_UART_v0_1/CRC_UART_v0_1.v | 61,827 | module MODULE1
(
input wire VAR84,
input wire reset,
input wire enable,
input wire VAR119
);
localparam VAR63 = 7'd8;
localparam VAR26 = 7'd16;
localparam VAR47 = 7'd24;
localparam VAR132 = 7'd32;
localparam VAR98 = 7'd40;
localparam VAR74 = 7'd48;
localparam VAR77 = 7'd56;
localparam VAR123 = 7'd64;
parameter [6:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxbp/sky130_fd_sc_ms__edfxbp_1.v | 2,375 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR4 ,
VAR10 ,
VAR11 ,
VAR7,
VAR2,
VAR8 ,
VAR3
);
output VAR5 ;
output VAR9 ;
input VAR4 ;
input VAR10 ;
input VAR11 ;
input VAR7;
input VAR2;
input VAR8 ;
input VAR3 ;
VAR1 VAR6 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
... | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/lm32_wrap.v | 5,115 | module MODULE1 (VAR64,
VAR31,
interrupt,
VAR11,
VAR3,
VAR44,
VAR50,
VAR51,
VAR23,
VAR18,
VAR32
);
input VAR64;
input VAR31;
input [VAR56] interrupt;
input VAR11;
output [31:0] VAR51;
input [31:0] VAR50;
output [31:0] VAR3;
output VAR44;
output VAR18;
output [3:0] VAR23;
output VAR32;
wire VAR10;
wire [31:0] VAR59;
wire... | gpl-3.0 |
kylemsguy/FPGA-Litecoin-Miner | experimental/LX150-SLOWSIXTEEN-A/ltcminer_icarus.v | 12,192 | module MODULE1 (VAR51, VAR101, VAR106, VAR112, VAR69, VAR62, VAR59, VAR25, VAR52, VAR17);
function integer VAR72; input integer VAR43;
begin
VAR43 = VAR43-1;
for (VAR72=0; VAR43>0; VAR72=VAR72+1)
VAR43 = VAR43>>1;
end
endfunction
parameter VAR28 = VAR28;
parameter VAR28 = 40; VAR5
parameter VAR54 = VAR54; else
paramete... | gpl-3.0 |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/soc_system_mm_interconnect_0_avalon_st_adapter.v | 6,164 | module MODULE1 #(
parameter VAR16 = 66,
parameter VAR24 = 0,
parameter VAR9 = 66,
parameter VAR22 = 0,
parameter VAR8 = 0,
parameter VAR15 = 0,
parameter VAR12 = 1,
parameter VAR1 = 1,
parameter VAR11 = 0,
parameter VAR6 = 66,
parameter VAR2 = 0,
parameter VAR7 = 1,
parameter VAR21 = 0,
parameter VAR19 = 1,
parameter V... | gpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/DAQ_RAM.v | 4,961 | module MODULE1(
reset,
VAR19,
VAR6,
VAR27,
VAR17,
VAR28,
VAR9,
VAR18,
VAR30,
VAR32
);
input reset;
input VAR19;
input VAR6;
input VAR28;
output VAR27;
output reg [6:0] VAR17 = 7'd0;
output VAR9;
input VAR18;
input VAR30;
input [13:0] VAR32;
reg [10:0] VAR2 = 11'd0;
reg VAR27 = 1'b0;
reg VAR15 = 1'b0;
reg VAR20 = 1'b0;
... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.behavioral.pp.v | 2,375 | module MODULE1( VAR4, VAR9, VAR1, VAR7, VAR8, VAR3, VAR2 );
input VAR8, VAR7, VAR9, VAR4;
inout VAR3, VAR2;
output VAR1;
VAR6 VAR5(.VAR4(VAR4),.VAR9(VAR9),.VAR1(VAR1),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2));
VAR6 VAR10(.VAR4(VAR4),.VAR9(VAR9),.VAR1(VAR1),.VAR7(VAR7),.VAR8(VAR8),.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/slaveController/slaveRxStatusMonitor.v | 3,896 | module MODULE1(VAR4, VAR3, VAR5, VAR7, VAR1, clk, rst);
input [1:0] VAR4;
input VAR5;
input clk;
input rst;
output VAR7;
output [1:0] VAR3;
output VAR1;
wire [1:0] VAR4;
wire VAR5;
reg VAR7;
reg [1:0] VAR3;
reg VAR1;
wire clk;
wire rst;
reg [1:0]VAR2;
reg VAR6;
always @(VAR4)
begin
VAR3 <= VAR4;
end
always @(posedge cl... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a211oi/sky130_fd_sc_ls__a211oi.behavioral.v | 1,553 | module MODULE1 (
VAR5 ,
VAR13,
VAR7,
VAR14,
VAR3
);
output VAR5 ;
input VAR13;
input VAR7;
input VAR14;
input VAR3;
supply1 VAR9;
supply0 VAR10;
supply1 VAR8 ;
supply0 VAR11 ;
wire VAR1 ;
wire VAR2;
and VAR6 (VAR1 , VAR13, VAR7 );
nor VAR12 (VAR2, VAR1, VAR14, VAR3);
buf VAR4 (VAR5 , VAR2 );
endmodule | apache-2.0 |
kevintownsend/inara-hdl-libraries | arbiter/arbiter.v | 2,294 | module MODULE1(rst, clk, VAR14, VAR17, VAR25, VAR2, VAR11, valid, VAR1);
parameter VAR18 = 8;
parameter VAR8 = 8;
parameter VAR33 = 32;
parameter VAR3 = 1;
parameter VAR30 = VAR27(VAR8-1);
parameter VAR7 = VAR27(VAR33-1);
input rst;
input clk;
input [0:VAR8-1]VAR14;
input [VAR18*VAR8-1:0] VAR17;
output [0:VAR8-1]VAR25;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf.symbol.v | 1,262 | module MODULE1 (
input VAR6,
output VAR1
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/custom/usb/serialInterfaceEngine/siereceiver.v | 9,710 | module MODULE1 (VAR13, VAR21, clk, VAR29, rst);
input [1:0] VAR13;
input VAR21;
input clk;
input rst;
output [1:0] VAR29;
wire [1:0] VAR13;
wire VAR21;
wire clk;
reg [1:0] VAR29, VAR37;
wire rst;
reg [3:0]VAR39, VAR1;
reg [7:0]VAR22, VAR16;
reg [1:0]VAR31, VAR12;
reg [3:0] VAR38;
reg [3:0] VAR9;
always @ (VAR13 or VAR3... | gpl-3.0 |
qeedquan/fpga | de2-115/uart_echo/2_uart.v | 1,787 | module MODULE1
(
input wire clk,
input wire reset,
input wire VAR12,
input wire VAR24,
input wire VAR16,
input wire [7:0] VAR23,
output wire VAR35,
output wire VAR31,
output wire [7:0] VAR19,
output wire VAR20
);
parameter VAR37 = 8; parameter VAR4 = 16; parameter VAR34 = 163; parameter VAR14 = 9; parameter VAR11 = 5;
... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/fpu/hardlogic/bgm.v | 9,006 | module MODULE2(VAR85,
reset,
VAR24,
VAR69,
VAR10,
VAR8,
VAR73,
VAR72,
VAR43,
VAR71,
VAR38
);
input VAR85;
input reset;
input [VAR101-1:0] VAR24;
input [VAR101-1:0] VAR69;
input [VAR101-1:0] VAR10;
input [VAR101-1:0] VAR8;
input [VAR101-1:0] VAR73;
input [VAR101-1:0] VAR72;
input [VAR101-1:0] VAR43;
input [VAR101-1:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2/sky130_fd_sc_ms__and2.blackbox.v | 1,233 | module MODULE1 (
VAR7,
VAR4,
VAR2
);
output VAR7;
input VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4/sky130_fd_sc_ms__or4.pp.blackbox.v | 1,308 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR3 ,
VAR4,
VAR1,
VAR8 ,
VAR7
);
output VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR8 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.v | 2,623 | module MODULE1 (
VAR12 ,
VAR9 ,
VAR10 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR2,
VAR3 ,
VAR13 ,
VAR5 ,
VAR11
);
output VAR12 ;
output VAR9 ;
input VAR10 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR2;
input VAR3 ;
input VAR13 ;
input VAR5 ;
input VAR11 ;
VAR7 VAR4 (
.VAR12(VAR12),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR1(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o.blackbox.v | 1,360 | module MODULE1 (
VAR5 ,
VAR1,
VAR2,
VAR3,
VAR9
);
output VAR5 ;
input VAR1;
input VAR2;
input VAR3;
input VAR9;
supply1 VAR6;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ayaovi/yoda | nexys4_DDR_projects/Keyboard/src/hdl/PS2Receiver.v | 1,774 | module MODULE1(
input clk,
input VAR6,
input VAR2,
output [31:0] VAR8
);
wire VAR4, VAR1;
reg [7:0]VAR9;
reg [7:0]VAR7;
reg [3:0]VAR3;
reg [31:0]VAR5;
reg flag; | gpl-3.0 |
aap/pdp6 | verilog/core32k_x.v | 10,301 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR3,
input wire VAR168,
input wire VAR29,
input wire VAR138,
input wire VAR94,
input wire VAR143,
input wire VAR82,
input wire [21:35] VAR30,
input wire [18:21] VAR174,
input wire VAR15,
input wire [0:35] VAR73,
output wire VAR63,
output wire VAR19,
output w... | mit |
csail-csg/recycle-bsv-lib | src/v/EHR_6.v | 3,170 | module MODULE1 (
VAR21,
VAR16,
VAR14,
VAR18,
VAR17,
VAR1,
VAR2,
VAR5,
VAR25,
VAR11,
VAR8,
VAR12,
VAR22,
VAR6,
VAR29,
VAR15,
VAR4,
VAR20,
VAR10,
VAR28
);
parameter VAR13 = 1;
parameter VAR30 = 0;
input VAR21;
input VAR16;
output [VAR13-1:0] VAR14;
input [VAR13-1:0] VAR18;
input VAR17;
output [VAR13-1:0] VAR1;
input [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr.pp.symbol.v | 1,410 | module MODULE1 (
input VAR6 ,
output VAR1 ,
input VAR5,
input VAR4 ,
input VAR3 ,
input VAR7 ,
input VAR2
);
endmodule | apache-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_auto_pc_3/synth/image_processing_2d_design_auto_pc_3.v | 14,702 | module MODULE1 (
VAR19,
VAR88,
VAR83,
VAR68,
VAR21,
VAR84,
VAR63,
VAR31,
VAR12,
VAR28,
VAR56,
VAR60,
VAR48,
VAR92,
VAR25,
VAR1,
VAR51,
VAR101,
VAR57,
VAR103,
VAR71,
VAR10,
VAR80,
VAR53,
VAR38,
VAR11,
VAR97,
VAR23,
VAR43,
VAR73,
VAR79,
VAR20,
VAR14,
VAR102,
VAR58,
VAR17,
VAR74,
VAR98,
VAR7,
VAR35,
VAR72,
VAR16,
VAR34,
V... | gpl-2.0 |
archlabo/Frix | fpga/nexys4/rtl/psramcon.v | 12,705 | module MODULE1 (
VAR17,
VAR30,
VAR7,
VAR31,
VAR41,
VAR54,
clk,
reset,
VAR2,
VAR35,
VAR36,
VAR19,
VAR12,
VAR53,
VAR13,
VAR21,
VAR25,
VAR64,
VAR58,
VAR48
);
output [ 31: 0] VAR2;
output VAR35;
output VAR36;
input [ 24: 0] VAR17;
input [ 3: 0] VAR30;
input VAR7;
input [ 31: 0] VAR31;
input VAR41;
input VAR54;
input clk;
i... | bsd-2-clause |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_axis_fifo.v | 5,872 | module MODULE1
parameter VAR24 = 33,
parameter VAR1 = 1 ,
parameter VAR32 = 1 ,
parameter VAR7 = 14,
parameter VAR40 = 16,
parameter VAR2 = 4
) (
input VAR15 ,
input VAR12 ,
input [VAR24-1:0] VAR18 ,
input [VAR24-1:0] VAR29,
input VAR16 ,
input VAR9 ,
input VAR14 ,
input VAR8 ,
output VAR20 ,
output VAR4 ,
output VAR26... | mit |
sh-chris110/chris | FPGA/chris.convolution.ok/Qsys/convoluation_core.v | 1,411 | module MODULE1 (
input clk,
input reset,
input [31:0] VAR22,
input [31:0] VAR5,
input [31:0] VAR34,
input [31:0] VAR13,
input [31:0] VAR8,
input [31:0] VAR15,
input [31:0] VAR20,
input [31:0] VAR10,
input [31:0] VAR4,
input VAR32,
output VAR14,
input VAR6,
output [31:0] VAR18
);
parameter VAR1 = 8'd1;
parameter VAR30 =... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_1.behavioral.v | 3,431 | module MODULE1( VAR1, VAR3, VAR5, VAR6, VAR2, VAR4 );
input VAR5, VAR3, VAR1, VAR2, VAR4;
output VAR6;
VAR7 VAR9(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR4(VAR4));
VAR7 VAR8(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3/sky130_fd_sc_ls__nor3_1.v | 2,198 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR9,
VAR10,
VAR7 ,
VAR5
);
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR9;
input VAR10;
input VAR7 ;
input VAR5 ;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
silent-observer/RCPU | CPU/source/UART_Controller/RS232TX.v | 1,667 | module MODULE1 (
input wire clk,
input wire rst,
output reg VAR5,
input wire[7:0] VAR11,
input wire VAR3,
output reg VAR7,
input wire VAR4,
output reg VAR1
);
reg VAR2, VAR9, VAR10;
always @(posedge clk) begin
if (rst) begin
VAR2 <= 1'b0;
VAR9 <= 1'b0;
VAR10 <= 1'b0;
end else begin
VAR2 <= VAR3;
VAR9 <= VAR2;
VAR10 <= ... | mit |
saiedhk/WhirlpoolHashEngine | whirlpool_wcipher_theta.v | 10,119 | module MODULE1 (
output [7:0] VAR19, VAR56, VAR3, VAR137, VAR139, VAR58, VAR85, VAR52,
VAR8, VAR111, VAR133, VAR17, VAR115, VAR15, VAR72, VAR47,
VAR35, VAR41, VAR1, VAR129, VAR49, VAR29, VAR127, VAR99,
VAR83, VAR128, VAR73, VAR55, VAR59, VAR36, VAR88, VAR34,
VAR71, VAR12, VAR26, VAR64, VAR135, VAR89, VAR78, VAR44,
VAR8... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o_2.v | 2,469 | module MODULE2 (
VAR2 ,
VAR4 ,
VAR6 ,
VAR12 ,
VAR8 ,
VAR10 ,
VAR9,
VAR7,
VAR5 ,
VAR11
);
output VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR12 ;
input VAR8 ;
input VAR10 ;
input VAR9;
input VAR7;
input VAR5 ;
input VAR11 ;
VAR3 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR9... | apache-2.0 |
lvd2/zxevo | fpga/current/video/video_render.v | 5,191 | module MODULE1(
input wire clk,
input wire [63:0] VAR6,
input wire VAR7,
input wire VAR14,
input wire VAR13, input wire VAR2,
input wire VAR17,
input wire VAR18,
input wire [ 2:0] VAR26,
output wire [ 3:0] VAR16,
output wire [ 1:0] VAR4,
output wire [ 2:0] VAR15,
output wire [ 2:0] VAR11,
output wire VAR8,
input wire [... | gpl-3.0 |
wgml/sysrek | skin_color_segm/circle.v | 2,670 | module MODULE1 #
(
parameter [9:0] VAR19 = 720,
parameter [9:0] VAR2 = 576
)
(
input clk,
input VAR33,
input rst,
input VAR17,
input VAR5,
input VAR26,
input VAR27,
output [9:0] VAR14,
output [9:0] VAR38,
output VAR46,
output [9:0] VAR21,
output [9:0] VAR42
);
reg [9:0] VAR23 = 0;
reg [9:0] VAR28 = 0;
wire VAR30;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.functional.v | 1,218 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR3 ;
input VAR2;
notif0 VAR4 (VAR1 , VAR3, VAR2 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-kc705/mig_interface_model.v | 5,203 | module MODULE1
(
input [27:0] VAR12,
input [2:0] VAR21,
input VAR27,
input [511:0] VAR10,
input VAR20,
input [63:0] VAR31,
input VAR11,
output wire [511:0] VAR32,
output wire VAR18,
output wire VAR2,
output wire VAR9,
output wire VAR25,
output reg VAR3,
output reg VAR7,
output reg VAR13,
input VAR8
);
parameter VAR6 = ... | gpl-2.0 |
chiragsakhuja/gpu | gpu.v | 17,711 | module MODULE1(
VAR23,
VAR75,
VAR36,
VAR35,
VAR40,
VAR20,
VAR13,
VAR34,
VAR79,
VAR72,
VAR58,
VAR67,
VAR52,
VAR78,
VAR48,
VAR24,
VAR71,
VAR25,
VAR17,
VAR27,
VAR51,
VAR37
);
input VAR23;
input VAR75;
input VAR36;
input VAR35;
input VAR40;
output [7:0] VAR20;
output [9:0] VAR13;
input VAR34;
input [3:0] VAR79;
input [9:0]... | gpl-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/ICESTICK/T21-baud-tx/baudtx2.v | 2,115 | module MODULE1(input wire clk, input wire VAR4, output wire VAR2 );
parameter VAR10 = VAR9;
reg [9:0] VAR5;
wire VAR1;
always @(posedge VAR1)
if (VAR4 == 0)
VAR5 <= {"VAR3",2'b01};
else
VAR5 <= {VAR5[0], VAR5[9:1]};
assign VAR2 = (VAR4) ? VAR5[0] : 1;
VAR8 #(VAR10)
VAR6 (
.VAR7(clk),
.VAR11(VAR1)
);
endmodule | gpl-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_HLS_accel_0_0/hdl/verilog/HLS_accel_fptrunc_64ns_32_1.v | 1,159 | module MODULE1
VAR5 = 2,
VAR13 = 1,
VAR16 = 64,
VAR11 = 32
)(
input wire [VAR16-1:0] VAR14,
output wire [VAR11-1:0] dout
);
wire VAR15;
wire [63:0] VAR4;
wire VAR9;
wire [31:0] VAR6;
VAR7 VAR10 (
.VAR1 ( VAR15 ),
.VAR12 ( VAR4 ),
.VAR2 ( VAR9 ),
.VAR3 ( VAR6 )
);
assign VAR15 = 1'b1;
assign VAR4 = VAR14==='VAR8 ? 'b0 :... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/common/rtl/bw_clk_cl_ctu_2xcmp_b.v | 1,961 | module MODULE1(VAR2 ,VAR1 );
output VAR2 ;
input VAR1 ;
assign VAR2 = VAR1;
endmodule | gpl-2.0 |
qmn/riscv-invicta | hardware/src/alu.v | 2,232 | module MODULE1 (
output reg [31:0] VAR4,
input [31:0] VAR2,
input [31:0] VAR1,
input [31:0] VAR5,
input [4:0] VAR3
);
always @ (*) begin
case (VAR3)
endcase
end
endmodule | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR10 ,
VAR9 ,
VAR13 ,
VAR8 ,
VAR1 ,
VAR3,
VAR16,
VAR2 ,
VAR4
);
output VAR10 ;
input VAR9 ;
input VAR13 ;
input VAR8 ;
input VAR1 ;
input VAR3;
input VAR16;
input VAR2 ;
input VAR4 ;
wire VAR15 ;
wire VAR7 ;
wire VAR11;
nor VAR14 (VAR15 , VAR9, VAR13 );
and VAR6 (VAR7 , VAR15, VAR8, VAR1 );
VAR17 VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv.behavioral.pp.v | 1,774 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR12,
VAR8,
VAR1 ,
VAR7
);
output VAR11 ;
input VAR3 ;
input VAR12;
input VAR8;
input VAR1 ;
input VAR7 ;
wire VAR4 ;
wire VAR9;
not VAR5 (VAR4 , VAR3 );
VAR10 VAR6 (VAR9, VAR4, VAR12, VAR8);
buf VAR2 (VAR11 , VAR9 );
endmodule | apache-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_mil/top.v | 8,863 | module MODULE2 (
VAR11,
VAR45,
VAR100,
VAR26,
VAR42,
VAR21,
VAR111,
VAR87,
VAR39,
VAR67,
VAR15,
VAR73,
VAR60,
VAR82,
VAR24,
VAR29,
VAR86,
VAR75,
VAR59,
VAR57,
VAR103,
VAR102,
VAR22,
VAR4,
VAR101,
VAR8,
VAR50,
VAR88,
VAR91,
VAR35,
VAR34,
VAR113,
VAR12,
VAR65,
VAR81,
VAR2,
VAR94,
VAR17,
VAR44,
VAR105,
VAR76,
VAR80,
VAR52... | apache-2.0 |
blu006/de0-nano-clock | FPGA/clock_display.v | 1,950 | module MODULE1(
VAR11,
VAR5,
VAR4,
VAR1,
VAR3,
VAR10,
VAR6,
VAR2,
VAR9
);
input VAR11;
input [3:0] VAR5, VAR4, VAR1, VAR3, VAR10, VAR6;
output [5:0] VAR2;
output [6:0] VAR9;
reg [5:0] VAR2;
reg [3:0] VAR8;
wire [3:0] VAR7; | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.pp.symbol.v | 1,575 | module MODULE1 (
input VAR7 ,
output VAR2 ,
output VAR1 ,
input VAR8,
input VAR9 ,
input VAR11 ,
input VAR12 ,
input VAR10 ,
input VAR3 ,
input VAR5 ,
input VAR4 ,
input VAR6
);
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_queue.v | 6,094 | module MODULE1(
input VAR32,
input reset,
output VAR70,
input VAR19,
input VAR46,
input [9:0] VAR66,
input [31:0] VAR8,
input [3:0] VAR65,
input [9:0] VAR45,
input VAR2,
output VAR64,
output VAR47,
output [9:0] VAR51,
output [31:0] VAR33,
output [3:0] VAR14,
output [9:0] VAR38,
output VAR27
);
reg VAR67 [0:0];
reg [31:... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111oi/sky130_fd_sc_hd__a2111oi.pp.blackbox.v | 1,435 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR3 ,
VAR10 ,
VAR5 ,
VAR6 ,
VAR8,
VAR2,
VAR7 ,
VAR4
);
output VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR10 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR2;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
joaocarlos/udlx-verilog | fpga/rtl/42s16320.v | 40,139 | module MODULE1 (VAR62, VAR84, VAR64, VAR26, VAR80, VAR44, VAR22, VAR46, VAR68, VAR63);
parameter VAR58 = 13;
parameter VAR49 = 16;
parameter VAR70 = 10;
parameter VAR3 = 8388608;
inout [VAR49 - 1 : 0] VAR62;
input [VAR58 - 1 : 0] VAR84;
input [1 : 0] VAR64;
input VAR26;
input VAR80;
input VAR44;
input VAR22;
input VAR4... | lgpl-3.0 |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/lab4part2overall.v | 2,499 | module MODULE1(VAR52,VAR27,VAR1,VAR30,VAR49,VAR47,VAR42,VAR55,VAR2,VAR51,VAR15,VAR48);
input VAR52, VAR27, VAR30, VAR49, VAR47;
input [6:0] VAR1;
output VAR42, VAR15, VAR48;
output [7:0] VAR55;
output [3:0] VAR2;
output [5:0] VAR51;
wire VAR8;
wire VAR17;
wire VAR13;
wire VAR46;
wire [6:0] VAR41;
wire VAR36;
wire [7:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd2/sky130_fd_sc_hd__dlygate4sd2.symbol.v | 1,322 | module MODULE1 (
input VAR6,
output VAR4
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi_1.v | 2,332 | module MODULE1 (
VAR2 ,
VAR8 ,
VAR5 ,
VAR6,
VAR4,
VAR7,
VAR9 ,
VAR10
);
output VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR6;
input VAR4;
input VAR7;
input VAR9 ;
input VAR10 ;
VAR3 VAR1 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR10(VAR10)
);
endmodule
module MODULE1 ... | apache-2.0 |
leekeith/DEVBOX | Dev_Box_HW/soc_system/synthesis/submodules/soc_system_vga_alpha.v | 8,430 | module MODULE1 (
clk,
reset,
VAR16,
VAR14,
VAR7,
VAR8,
VAR24,
VAR15,
VAR12,
VAR19,
VAR10,
VAR6,
VAR1,
VAR17,
VAR2,
VAR13,
VAR18,
VAR25,
VAR11,
VAR3
);
input clk;
input reset;
input [29: 0] VAR16;
input VAR14;
input VAR7;
input [ 1: 0] VAR8;
input VAR24;
input [39: 0] VAR15;
input VAR12;
input VAR19;
input [ 1: 0] VAR10... | gpl-2.0 |
balangs/eTeak | tech/amust-mapping.v | 2,897 | module MODULE2 (output VAR11, input VAR32, VAR22);
VAR15 VAR25 (VAR11, VAR32, VAR22);
endmodule
module MODULE16 (output VAR11, input VAR32, VAR22, VAR16);
VAR12 VAR25 (VAR11, VAR32, VAR22, VAR16);
endmodule
module MODULE8 (output VAR11, input VAR32, VAR22);
VAR31 VAR25 (VAR11, VAR32, VAR22);
endmodule
module MODULE13 (... | bsd-3-clause |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_clocks.v | 15,452 | module MODULE1 (
VAR57,
VAR73,
reset,
VAR65,
VAR41,
VAR77,
VAR70,
VAR31
);
input VAR57;
input VAR73;
input reset;
output VAR65;
output VAR41;
output VAR77;
output VAR70;
output VAR31;
localparam VAR102 = 1;
localparam VAR27 = 1;
localparam VAR25 = 14;
localparam VAR67 = 31;
wire [ 2: 0] VAR19;
wire [ 2: 0] VAR93;
wire ... | mit |
jas0n1ee/THU-DSD | FB/ip/Audio_DAC_FIFO/hdl/AUDIO_DAC_FIFO.v | 3,230 | module MODULE1 ( VAR14,VAR24,VAR34,
VAR22,
VAR16,
VAR1,
VAR12,
VAR6,
VAR2,
VAR3 );
parameter VAR9 = 18432000; parameter VAR29 = 48000; parameter VAR33 = 16; parameter VAR15 = 2;
input [VAR33-1:0] VAR14;
input VAR24;
input VAR34;
output [VAR33-1:0] VAR22;
wire [VAR33-1:0] VAR4;
reg VAR18;
output VAR1;
output VAR12;
outp... | mit |
AnttiLukats/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/crypto_sha256_top.v | 2,531 | module MODULE1 (
input VAR30,
input VAR29,
input VAR34,
input [31:0] VAR10,
input [31:0] VAR32,
input [3:0] VAR20,
input VAR24,
input [1:0] VAR25,
input [2:0] VAR16,
input VAR31,
input VAR33,
output VAR28,
output VAR17,
output VAR12,
output [31:0] VAR23
);
wire [255:0] VAR14, VAR9;
wire [511:0] VAR35;
wire VAR1, VAR36;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3.pp.blackbox.v | 1,287 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR8 ,
VAR2 ,
VAR5,
VAR4,
VAR6 ,
VAR3
);
output VAR1 ;
input VAR7 ;
input VAR8 ;
input VAR2 ;
input VAR5;
input VAR4;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_tx_sie.v | 4,079 | module MODULE1
(input VAR3,
input VAR57,
input rst,
input [7:0] VAR48,
input VAR18,
output VAR42,
output VAR26,
inout VAR50,
inout VAR46);
wire VAR5, VAR38, VAR23;
VAR60 VAR15
(.VAR3(VAR3), .VAR57(VAR57),
.VAR48(VAR48), .VAR18(VAR18), .VAR17(VAR5), .read(VAR38),
.VAR29(VAR23));
wire VAR19, VAR36; wire VAR7; VAR55 VAR8
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill_diode/sky130_fd_sc_hs__fill_diode.behavioral.v | 1,141 | module MODULE1 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/or1200/or1200_sb.v | 6,499 | module MODULE1(
clk, rst,
VAR15, VAR1, VAR6, VAR28, VAR12, VAR11, VAR20,
VAR31, VAR29, VAR39,
VAR22, VAR38, VAR5, VAR16, VAR3, VAR37, VAR27,
VAR19, VAR34, VAR25
);
parameter VAR8 = VAR40;
parameter VAR4 = VAR40;
input clk; input rst;
input [VAR8-1:0] VAR15; input [VAR4-1:0] VAR1; input VAR6; input VAR28; input VAR12; i... | gpl-3.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_global_logic.v | 6,143 | module MODULE1
(
VAR31,
VAR3,
VAR23,
VAR19,
VAR2,
VAR28,
VAR29,
VAR7,
VAR32,
VAR20,
VAR14,
VAR17,
VAR11,
VAR5,
VAR13,
VAR24,
VAR21,
VAR15,
VAR30,
VAR1
);
input [0:3] VAR31;
output VAR3;
input [0:3] VAR19;
input [0:3] VAR23;
input [0:3] VAR2;
input [0:3] VAR28;
input [0:7] VAR29;
input [0:3] VAR7;
output [0:3] VAR32;
ou... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Pixel_RGB_Resampler.v | 7,566 | module MODULE1 (
clk,
reset,
VAR21,
VAR16,
VAR22,
VAR8,
VAR13,
VAR2,
VAR6,
VAR17,
VAR9,
VAR4,
VAR20,
VAR14
);
parameter VAR12 = 15;
parameter VAR18 = 29;
parameter VAR19 = 0;
parameter VAR10 = 1;
parameter VAR11 = 10'h3FF;
input clk;
input reset;
input [VAR12:0] VAR21;
input VAR16;
input VAR22;
input [VAR19:0] VAR8;
in... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_p_pp_pkg_s/sky130_fd_sc_hs__udp_dlatch_p_pp_pkg_s.blackbox.v | 1,448 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR6 ,
VAR3,
VAR1 ,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR2 ;
input VAR6 ;
input VAR3;
input VAR1 ;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a.blackbox.v | 1,353 | module MODULE1 (
VAR6 ,
VAR1,
VAR2,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR1;
input VAR2;
input VAR7 ;
input VAR4 ;
supply1 VAR3;
supply0 VAR5;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.behavioral.pp.v | 1,922 | module MODULE1 (
VAR9 ,
VAR15 ,
VAR5 ,
VAR4,
VAR1,
VAR8,
VAR7 ,
VAR3
);
output VAR9 ;
output VAR15 ;
input VAR5 ;
input VAR4;
input VAR1;
input VAR8;
input VAR7 ;
input VAR3 ;
wire VAR16 ;
wire VAR6;
wire VAR14 ;
reg VAR2 ;
VAR10 VAR12 (VAR16 , VAR14, VAR6, VAR2, VAR1, VAR8);
buf VAR11 (VAR9 , VAR16 );
not VAR13 (VAR15... | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/I2C_AV_Config.v | 4,840 | module MODULE1 ( VAR3,
VAR19,
VAR31,
VAR32 );
input VAR3;
input VAR19;
output VAR31;
inout VAR32;
reg [15:0] VAR1;
reg [23:0] VAR9;
reg VAR10;
reg VAR18;
wire VAR5;
wire VAR33;
reg [15:0] VAR2;
reg [5:0] VAR23;
reg [3:0] VAR20;
parameter VAR14 = 50000000; parameter VAR13 = 20000; parameter VAR7 = 51;
parameter VAR8 = 0... | gpl-3.0 |
LorhanSohaky/UFSCar | 2018/lab-arq1/aula_03-26/Lorhan740951/counter.v | 2,417 | module MODULE1 (VAR1, clk, reset);
output [7:0] VAR1;
input clk, reset;
reg [7:0] VAR1;
always @ (posedge clk or posedge reset)
if (reset)
VAR1 = 8'h00;
else
VAR1 <= VAR1 + 8'h01;
endmodule | mit |
combinatorylogic/soc | backends/c2/hw/ice/ice.v | 5,555 | module MODULE1(input clk,
input rst,
input VAR31,
output VAR25,
output reg [31:0] VAR19,
output reg VAR33,
input [31:0] VAR32,
input [31:0] VAR15,
input [31:0] VAR29);
wire [7:0] VAR2;
wire VAR34;
wire VAR26;
reg VAR23;
reg VAR38;
reg [7:0] VAR10;
reg [7:0] VAR11;
reg VAR24;
reg VAR40;
wire VAR35;
VAR36 VAR39(.clk(clk)... | mit |
manili/Pipelined_6502 | Decode.v | 274,170 | module MODULE1(
VAR31,
VAR48,
VAR29,
VAR25,
VAR14,
VAR11,
VAR22,
VAR4,
VAR32,
VAR35,
VAR20,
VAR49,
VAR36,
VAR42
,VAR5
);
input wire VAR31;
input wire VAR48;
input wire VAR29;
input wire VAR25;
input wire VAR14;
input wire [1:0] VAR11;
input wire [7:0] VAR22;
input wire [15:0] VAR4;
input wire [23:0] VAR32;
input wire V... | gpl-3.0 |
petrmikheev/miksys | verilog/MULT.v | 4,270 | module MODULE1 (
VAR16,
VAR14,
VAR2);
input [16:0] VAR16;
input [16:0] VAR14;
output [33:0] VAR2;
wire [33:0] VAR6;
wire [33:0] VAR2 = VAR6[33:0];
VAR18 VAR4 (
.VAR16 (VAR16),
.VAR14 (VAR14),
.VAR2 (VAR6),
.VAR5 (1'b0),
.VAR8 (1'b1),
.VAR11 (1'b0),
.sum (1'b0));
VAR4.VAR15 = "VAR7=5",
VAR4.VAR1 = "VAR3",
VAR4.VAR13 = ... | gpl-3.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_obuft2.v | 1,131 | module MODULE1(
input [1:0] VAR3,
input [1:0] VAR2,
output [1:0] VAR5
);
VAR4 VAR1(
.VAR3(VAR3[0]),
.VAR2(VAR2[0]),
.VAR5(VAR5[0])
);
VAR4 VAR6(
.VAR3(VAR3[1]),
.VAR2(VAR2[1]),
.VAR5(VAR5[1])
);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3b/sky130_fd_sc_hd__nand3b.symbol.v | 1,313 | module MODULE1 (
input VAR5,
input VAR7 ,
input VAR4 ,
output VAR6
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai22/gf180mcu_fd_sc_mcu9t5v0__oai22_2.functional.pp.v | 1,520 | module MODULE1( VAR3, VAR1, VAR9, VAR6, VAR2, VAR16, VAR20 );
input VAR2, VAR6, VAR1, VAR3;
inout VAR16, VAR20;
output VAR9;
wire VAR19;
not VAR7( VAR19, VAR2 );
wire VAR15;
not VAR11( VAR15, VAR6 );
wire VAR13;
and VAR18( VAR13, VAR19, VAR15 );
wire VAR5;
not VAR8( VAR5, VAR1 );
wire VAR4;
not VAR10( VAR4, VAR3 );
wir... | apache-2.0 |
CospanDesign/sdio-device | functions/my_function/my_function.v | 1,496 | module MODULE1 (
input clk,
input rst
);
localparam VAR1 = 32'h00000000;
endmodule | mit |
mfkiwl/parallella-platform | hdl/fifo_full_block.v | 2,883 | module MODULE1 (
VAR10, VAR9, VAR3,
reset, VAR6, VAR7, VAR2
);
parameter VAR1 = 2;
input reset;
input VAR6;
input [VAR1:0] VAR7; input VAR2;
output VAR10;
output [VAR1-1:0] VAR9;
output [VAR1:0] VAR3;
reg [VAR1:0] VAR3;
reg [VAR1:0] VAR5;
reg VAR10;
wire VAR11;
wire [VAR1:0] VAR4;
wire [VAR1:0] VAR8;
always @(posedge V... | gpl-3.0 |
Elphel/x393_sata | x393/util_modules/dly_16.v | 2,450 | module MODULE1 #(
parameter VAR2=1
)(
input clk,
input rst,
input [3:0] VAR3,
input [VAR2-1:0] din,
output [VAR2-1:0] dout
);
generate
genvar VAR4;
for (VAR4=0; VAR4 < VAR2; VAR4=VAR4+1) begin: VAR1
VAR5 VAR6 (
.clk(clk), .rst(rst), .VAR3(VAR3), .din(din[VAR4]), .dout(dout[VAR4]) );
end
endgenerate
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/edfxtp/sky130_fd_sc_hs__edfxtp.pp.blackbox.v | 1,310 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5 ,
VAR4 ,
VAR3,
VAR6
);
output VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
input VAR3;
input VAR6;
endmodule | apache-2.0 |
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