repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
vineeshvs/research | full_adder_sliced.v | 1,158 | module MODULE1 (VAR1, b0, VAR14, VAR10, b1, VAR5, VAR17, VAR13, VAR22);
input VAR1;
input b0;
input VAR14;
input VAR10;
input b1;
output VAR5;
output VAR17;
output VAR13;
output VAR12;
output VAR22;
wire VAR24;
wire VAR3;
wire VAR15;
wire VAR12;
wire VAR9;
assign VAR21 = VAR24 | VAR3;
assign VAR17 = VAR15;
VAR11 VAR4 (... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_4.behavioral.v | 2,309 | module MODULE1( VAR3, VAR5, VAR4, VAR8, VAR2 );
input VAR2, VAR8, VAR5, VAR3;
output VAR4;
VAR6 VAR1(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2));
VAR6 VAR7(.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_hip_s4gx_gen2_x4_128/pci_express_compiler-library/altpcie_pll_100_250.v | 10,094 | module MODULE1 (
VAR44,
VAR42,
VAR19);
input VAR44;
input VAR42;
output VAR19;
wire [5:0] VAR22;
wire [0:0] VAR26 = 1'h0;
wire [0:0] VAR38 = 1'h1;
wire [0:0] VAR40 = VAR22[0:0];
wire VAR19 = VAR40;
wire [5:0] VAR52 = {VAR26, VAR26, VAR26, VAR26, VAR26, VAR38};
wire VAR37 = VAR42;
wire [1:0] VAR48 = {VAR26, VAR37};
wire... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fa/sky130_fd_sc_hd__fa_2.v | 2,278 | module MODULE2 (
VAR4,
VAR2 ,
VAR9 ,
VAR7 ,
VAR11 ,
VAR5,
VAR6,
VAR3 ,
VAR10
);
output VAR4;
output VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR11 ;
input VAR5;
input VAR6;
input VAR3 ;
input VAR10 ;
VAR8 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR... | apache-2.0 |
iDoka/GOST-28147-89 | rtl/gost_28147_89.v | 2,068 | module MODULE1 (clk, rst, VAR12, VAR13, VAR3, VAR18, VAR6, VAR7);
input clk; input rst; input VAR12; input VAR13; output VAR3; input [255:0] VAR18; input [63:0] VAR6; output [63:0] VAR7;
reg [4:0] VAR14;
always @(posedge clk)
if(rst || VAR13)
VAR14 <= 5'h0;
else VAR14 <= VAR14 + 1;
wire [2:0] VAR17 = (&VAR14[4:3]) ? ~V... | mit |
jefg89/proyecto_final_prototipado | ProyectoFinal/HDLNeuralNetwork/ALUfuncionActivacion.v | 1,693 | module MODULE1 #(parameter VAR9 = 24, VAR22 = 4, VAR11 = 19, VAR14 = 1)
(VAR8,VAR16,VAR20,VAR15,VAR13,VAR3,VAR6);
input [4:0] VAR8;
input VAR16;
input signed [VAR9-1:0] VAR20,VAR15,VAR13;
output VAR6;
output reg signed [VAR9-1:0] VAR3 = 0;
wire signed [VAR9-1:0] VAR10,VAR23;
wire VAR17,VAR19;
VAR4 #(.VAR9(VAR9), .VAR22... | gpl-2.0 |
qeedquan/fpga | de2-115/uart_hello/uart_transmitter.v | 1,482 | module MODULE1
(
input wire clk,
input wire rst,
input wire [7:0] VAR10,
output reg VAR2,
output reg VAR9
);
parameter VAR7 = 50000000;
parameter VAR6 = 9600;
localparam VAR12 = VAR7/VAR6;
localparam VAR11 = 0;
localparam VAR14 = 1;
reg state, VAR3;
reg [31:0] VAR8;
reg [4:0] VAR1;
reg [9:0] VAR13;
reg VAR17, VAR4, VAR... | mit |
lokisz/openzcore | pippo-0.9/rtl/verilog/pippo_barrel.v | 5,295 | module MODULE1 (
VAR9,
VAR2,
VAR12,
VAR6,
VAR7,
VAR4,
VAR16,
VAR11,
VAR18,
VAR14,
VAR1
);
input [31:0] VAR9; input [31:0] VAR12; input [4:0] VAR2; input VAR4; input VAR16; input VAR11; input [4:0] VAR6; input [4:0] VAR7; input VAR18;
output [31:0] VAR14;
output VAR1;
reg [95:0] VAR3;
wire [31:0] VAR12;
wire [31:0] VAR1... | gpl-2.0 |
mshr-h/verilog_building_block | rtl/button_debounce.v | 1,112 | module MODULE1
parameter VAR2 = 10000000,
parameter VAR8 = 2
) (
input wire clk,
input wire VAR10,
input wire VAR9,
output reg VAR3
);
localparam VAR11 = VAR2 / VAR8;
localparam VAR4 = 0;
localparam VAR7 = 1;
localparam VAR5 = 2;
reg [VAR12(VAR11):0] VAR6;
reg [1:0] state, VAR1;
always @(posedge clk or negedge VAR10)
s... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp.pp.blackbox.v | 1,335 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR5 ,
VAR2,
VAR1 ,
VAR3 ,
VAR8 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR2;
input VAR1 ;
input VAR3 ;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v | 10,443 | module MODULE1 (VAR18, VAR33, VAR8, VAR7, VAR13, VAR22,
VAR29, VAR25, VAR21, VAR1, VAR16,
VAR12, VAR14, VAR20, VAR28, VAR26, VAR5,
VAR31, VAR6, VAR10
);
parameter VAR4 = 1;
input VAR18;
input VAR33;
input VAR8;
input VAR7;
input VAR13;
input VAR22;
input VAR29;
input VAR25;
input VAR21;
input VAR1;
input VAR16;
input [... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.functional.v | 1,443 | module MODULE1( VAR1, VAR6, VAR2, VAR16, VAR8 );
input VAR2, VAR1, VAR16, VAR8;
output VAR6;
wire VAR13;
not VAR10( VAR13, VAR2 );
wire VAR3;
not VAR9( VAR3, VAR1 );
wire VAR11;
and VAR15( VAR11, VAR13, VAR3 );
wire VAR7;
not VAR5( VAR7, VAR16 );
wire VAR12;
not VAR14( VAR12, VAR8 );
or VAR4( VAR6, VAR11, VAR7, VAR12 )... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf.pp.blackbox.v | 1,170 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR1;
input VAR2;
endmodule | apache-2.0 |
ymei/TMSPlane | Firmware/src/sdm_adc_data_aurora_recv.v | 2,221 | module MODULE1
parameter VAR17 = 20,
parameter VAR4 = 20,
parameter VAR7 = 19,
parameter VAR12 = 4
)
(
input VAR5,
input VAR14,
input VAR8,
input [63:0] VAR10,
input VAR15,
output [511:0] VAR6,
output VAR11,
output reg VAR16
);
localparam VAR9 = VAR4 / VAR12;
localparam VAR3 = 9;
reg [VAR9*VAR7*2 + VAR17*16 - 1 : 0] VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.v | 2,215 | module MODULE1 (
VAR2,
VAR5 ,
VAR1 ,
VAR3 ,
VAR7
);
output VAR2;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR7 ;
VAR6 VAR4 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR2,
VAR5
);
output VAR2;
input VAR5 ;
supply1 VAR1;
supply1 VAR3 ;
supply0 VAR7 ;
VAR6 VAR4 (
.... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_2.behavioral.pp.v | 1,328 | module MODULE1( VAR8, VAR4, VAR2, VAR6, VAR5, VAR1 );
input VAR6, VAR2, VAR4;
inout VAR5, VAR1;
output VAR8;
VAR7 VAR3(.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1));
VAR7 VAR9(.VAR8(VAR8),.VAR4(VAR4),.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
krucios/Echo_module | src/control_unit.v | 7,501 | module MODULE1 (
input wire clk,
input wire VAR34,
input wire[7:0] VAR5,
input wire VAR22,
input wire VAR27,
output reg VAR26 = 1,
output reg VAR3 = 1,
output reg[7:0] VAR21 = 0,
input wire[7:0] VAR31, output reg[7:0] VAR4, output reg[7:0] VAR30,
input wire VAR12,
input wire VAR19,
input wire[7:0] VAR8,
output reg VAR1... | gpl-3.0 |
bobnewgard/fcs | ver/uut_1_bitp.v | 4,133 | module MODULE1
(
output wire [31:0] VAR4,
output wire [31:0] VAR24,
output wire [31:0] VAR1,
output wire VAR14,
input wire [31:0] VAR31,
input wire VAR23,
input wire VAR22,
input wire VAR5,
input wire VAR27
);
localparam VAR13 = 1'b0;
localparam VAR30 = 1'b1;
localparam [31:0] VAR2 = {32{VAR13}};
localparam [31:0] VAR9... | gpl-3.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_gmultp2_32x32.v | 4,075 | module MODULE1 ( VAR2, VAR11, VAR5, VAR6, VAR9 );
input [VAR3-1:0] VAR2;
input [VAR3-1:0] VAR11;
input VAR5;
input VAR6;
output [VAR1-1:0] VAR9;
reg [VAR1-1:0] VAR10;
reg [VAR1-1:0] VAR4;
integer VAR7;
integer VAR8;
always @(VAR2)
VAR7 <= VAR2;
always @(VAR11)
VAR8 <= VAR11;
always @(posedge VAR5 or posedge VAR6)
if (V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2b/sky130_fd_sc_ms__nand2b_2.v | 2,147 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR2 ,
VAR5,
VAR9,
VAR1 ,
VAR3
);
output VAR6 ;
input VAR4 ;
input VAR2 ;
input VAR5;
input VAR9;
input VAR1 ;
input VAR3 ;
VAR7 VAR8 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR6 ,
VAR4,
VAR2
);
output VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdlclkp/sky130_fd_sc_hs__sdlclkp.symbol.v | 1,302 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR6,
output VAR1
);
supply1 VAR3;
supply0 VAR2;
endmodule | apache-2.0 |
YurongYou/MIPS_CPU | RM_ctrl.v | 1,270 | module MODULE1 (
input rst,
input[VAR1-1:0] VAR13,
input[VAR7-1:0] VAR3,
input[VAR6-1:0] VAR15,
output reg[VAR6-1:0] VAR5
);
reg[VAR10] VAR12;
reg[VAR9] VAR11;
always @ begin : VAR4
case (VAR13)
4'b1100 : VAR11 <= VAR15[31:16];
4'b0011 : VAR11 <= VAR15[15:0];
default : VAR11 <= VAR14;
endcase
end
always @(*) begin : VA... | mpl-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_multiplexer_128.v | 18,799 | module MODULE1
parameter VAR39 = 128,
parameter VAR106 = 12,
parameter VAR38 = 5, parameter VAR54 = "VAR103"
)
(
input VAR1,
input VAR112,
input [VAR106-1:0] VAR116, input [(VAR106*VAR19)-1:0] VAR11, input [(VAR106*VAR117)-1:0] VAR27, input [(VAR106*VAR39)-1:0] VAR69, output [VAR106-1:0] VAR50, output [VAR106-1:0] VAR1... | bsd-3-clause |
hcabrera-/atto | rtl/arbiter.v | 8,143 | module MODULE1 (
input wire [2:0] VAR10,
input wire [2:0] VAR9,
input wire [2:0] VAR8,
output reg [1:0] VAR4,
output reg [2:0] VAR12,
output reg [2:0] VAR11,
output reg VAR5
);
localparam VAR2 = 3'b111;
localparam VAR6 = 3'b101;
localparam VAR13 = 3'b001;
localparam VAR1 = 3'b000;
localparam VAR7 = 2'b00;
wire [2:0] VA... | gpl-3.0 |
origintfj/riscv | rv32i/rtl/merlin_lsqueue.v | 12,955 | module MODULE1
parameter VAR7 = 0,
parameter VAR29 = 2
)
(
input wire VAR11,
input wire VAR32,
output wire VAR10,
output wire [4:0] VAR9,
output reg [VAR47-1:0] VAR63,
output wire VAR55,
output wire VAR26,
input wire VAR3,
input wire VAR14,
input wire [1:0] VAR43,
input wire [2:0] VAR38,
input wire [4:0] VAR13,
input w... | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_mm_interconnect_1.v | 103,175 | module MODULE1 (
input wire VAR393, input wire VAR139, input wire VAR126, input wire [31:0] VAR117, output wire VAR308, input wire [3:0] VAR372, input wire VAR350, output wire [31:0] VAR27, output wire VAR31, input wire VAR230, input wire [31:0] VAR128, output wire [0:0] VAR368, output wire VAR113, input wire [31:0] VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/diode/sky130_fd_sc_hvl__diode.pp.blackbox.v | 1,230 | module MODULE1 (
VAR1,
VAR4 ,
VAR3 ,
VAR5 ,
VAR2
);
input VAR1;
input VAR4 ;
input VAR3 ;
input VAR5 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.pp.symbol.v | 1,400 | module MODULE1 (
input VAR2 ,
input VAR6 ,
input VAR5 ,
input VAR7 ,
input VAR4 ,
output VAR1 ,
input VAR9 ,
input VAR3,
input VAR8,
input VAR10
);
endmodule | apache-2.0 |
bgamari/timetag-fpga | altpll0.v | 14,791 | module MODULE1 (
VAR96,
VAR32,
VAR39);
input VAR96;
output VAR32;
output VAR39;
wire [5:0] VAR19;
wire VAR23;
wire [0:0] VAR68 = 1'h0;
wire [0:0] VAR43 = VAR19[0:0];
wire VAR32 = VAR43;
wire VAR39 = VAR23;
wire VAR103 = VAR96;
wire [1:0] VAR104 = {VAR68, VAR103};
VAR4 VAR15 (
.VAR44 (VAR104),
.clk (VAR19),
.VAR39 (VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2a/sky130_fd_sc_hs__o2bb2a_4.v | 2,271 | module MODULE2 (
VAR2 ,
VAR4,
VAR5,
VAR9 ,
VAR7 ,
VAR8,
VAR1
);
output VAR2 ;
input VAR4;
input VAR5;
input VAR9 ;
input VAR7 ;
input VAR8;
input VAR1;
VAR3 VAR6 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2 ,
VAR4,
VAR5,
VAR9 ,
VAR7
);
ou... | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/phy/mig_7series_v2_0_ddr_phy_rdlvl.v | 145,073 | module MODULE1 #
(
parameter VAR321 = 100, parameter VAR185 = 2, parameter VAR63 = 3333, parameter VAR323 = 64, parameter VAR77 = 3, parameter VAR237 = 8, parameter VAR181 = 8, parameter VAR66 = 1, parameter VAR113 = "VAR421", parameter VAR118 = "VAR15", parameter VAR9 = "VAR290", parameter VAR96 = "VAR188", parameter ... | bsd-2-clause |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/bench/verilog/msp_debug.v | 14,465 | module MODULE1 (
VAR91, VAR95, VAR70, VAR85, VAR9, VAR89, VAR65,
VAR5, VAR58 );
output [8*32-1:0] VAR91; output [8*32-1:0] VAR95; output [31:0] VAR70; output [8*32-1:0] VAR85; output [31:0] VAR9; output [15:0] VAR89; output [8*32-1:0] VAR65;
input VAR5; input VAR58;
function [64*8-1:0] VAR92;
input [32*8-1:0] VAR3;
inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd3/sky130_fd_sc_hd__dlygate4sd3.behavioral.pp.v | 1,832 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR12,
VAR9,
VAR11 ,
VAR6
);
output VAR10 ;
input VAR2 ;
input VAR12;
input VAR9;
input VAR11 ;
input VAR6 ;
wire VAR5 ;
wire VAR3;
buf VAR8 (VAR5 , VAR2 );
VAR4 VAR1 (VAR3, VAR5, VAR12, VAR9);
buf VAR7 (VAR10 , VAR3 );
endmodule | apache-2.0 |
DeanoC/ice40k-zpu | zpu_core.v | 25,719 | module MODULE2 (
interrupt, VAR12
clk, reset, VAR54, VAR69, VAR85, VAR1, VAR100, VAR82, VAR68 );
input clk;
input reset;
output VAR54;
output VAR69;
input VAR85;
input [31:0] VAR100;
output [31:0] VAR82;
output [31:0] VAR1;
output [3:0] VAR68;
input interrupt;
wire clk;
wire reset;
wire VAR54;
wire VAR69;
wire VAR85;
w... | mit |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/submodules/system_acl_iface_hps.v | 16,175 | module MODULE1 #(
parameter VAR89 = 0,
parameter VAR75 = 0
) (
output wire VAR54, input wire VAR55, output wire [11:0] VAR31, output wire [20:0] VAR86, output wire [3:0] VAR80, output wire [2:0] VAR2, output wire [1:0] VAR46, output wire [1:0] VAR38, output wire [3:0] VAR64, output wire [2:0] VAR32, output wire VAR26, ... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.functional.v | 1,746 | module MODULE1( VAR11, VAR5, VAR4, VAR8, VAR18 );
input VAR5, VAR8, VAR4;
output VAR18, VAR11;
wire VAR24;
and VAR3( VAR24, VAR5, VAR8 );
wire VAR9;
and VAR19( VAR9, VAR5, VAR4 );
wire VAR23;
and VAR25( VAR23, VAR8, VAR4 );
or VAR22( VAR18, VAR24, VAR9, VAR23 );
wire VAR20;
and VAR21( VAR20, VAR5, VAR8, VAR4 );
wire VA... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/typea.v | 3,066 | module MODULE1(
input VAR3,
input VAR4,
input VAR2,
input VAR8,
output VAR10,
output reg VAR6,
input VAR7,
input VAR5,
input VAR1
);
reg VAR9;
always @ (negedge VAR3 or negedge VAR4)
begin
if (VAR4 == 1'b0)
VAR9 <= 1'b0;
end
else if (VAR3 == 1'b0)
if (VAR2 == 1'b1)
if (VAR5 == 1'b0)
VAR9 <= VAR8;
else
VAR9 <= VAR7;
end... | lgpl-3.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/v6_ddr_top.v | 26,928 | module MODULE1 #
(
parameter VAR32 = 200,
parameter VAR101 = "VAR20",
parameter VAR63 = "VAR51",
parameter VAR65 = 6,
parameter VAR99 = 1, parameter VAR57 = 3, parameter VAR92 = 2,
parameter VAR81 = 2500,
parameter VAR100 = "VAR24",
parameter VAR74 = "VAR24",
parameter VAR45 = 1,
parameter VAR59 = 3,
parameter VAR37 = ... | mit |
patrick-samy/ace | control/unit.v | 1,677 | module MODULE1(input VAR14);
wire[31:0] VAR16;
wire[2:0] VAR8;
wire[4:0] VAR3;
wire VAR27;
wire[3:0] VAR28;
wire VAR15;
wire[1:0] VAR19;
wire[7:0] VAR5;
wire VAR23;
wire[1:0] VAR9;
wire[7:0] VAR2;
wire[1:0] VAR7;
wire[1:0] VAR18;
wire[1:0] VAR25;
wire VAR10;
VAR4 VAR17(VAR16, VAR28,
VAR15, VAR19,
VAR5,
VAR23, VAR9,
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv_1.v | 2,036 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR8,
VAR2,
VAR7 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR8;
input VAR2;
input VAR7 ;
input VAR1 ;
VAR6 VAR4 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR8;
supply0 VAR2;... | apache-2.0 |
HarmonInstruments/hififo | hdl/block_ram.v | 1,221 | module MODULE1
(
input VAR10,
input [VAR1-1:0] VAR8,
input VAR3,
input [VAR9-1:0] VAR2,
output reg [VAR1-1:0] VAR4,
input [VAR9-1:0] VAR7
);
parameter VAR9 = 9;
parameter VAR1 = 64;
reg [VAR1-1:0] VAR5[0:2**VAR9-1];
reg [VAR1-1:0] VAR6;
always @ (posedge VAR10)
begin
if(VAR3)
VAR5[VAR2] <= VAR8;
VAR6 <= VAR5[VAR7];
VAR... | gpl-3.0 |
sh-chris110/chris | FPGA/chris.system_ok/db/ip/soc_design/submodules/soc_design_niosII_core_cpu_debug_slave_tck.v | 8,323 | module MODULE1 (
VAR8,
VAR36,
VAR2,
VAR15,
VAR40,
VAR6,
VAR18,
VAR26,
VAR39,
VAR27,
VAR16,
VAR9,
VAR14,
VAR31,
VAR29,
VAR23,
VAR1,
VAR38,
VAR28,
VAR21,
VAR12,
VAR20,
VAR5,
VAR17,
VAR19,
VAR4,
VAR32,
VAR30,
VAR35,
VAR33,
VAR34
)
;
output [ 1: 0] VAR32;
output VAR30;
output [ 37: 0] VAR35;
output VAR33;
output VAR34;
inp... | gpl-2.0 |
jz0229/open-ephys-pcie | kc705-host-firmware/Sources/Verilog/clock_generator.v | 10,008 | module MODULE1(
input VAR46,
input VAR17,
input rst,
input [7:0] VAR23,
input [3:0] VAR27,
input [6:0] VAR113,
input VAR103,
output ready,
output VAR112,
output VAR101
);
wire VAR98;
wire VAR56;
wire VAR74;
wire VAR93;
wire VAR90;
reg VAR77;
reg VAR78;
reg [6:0] VAR107;
reg [15:0] VAR61;
wire [15:0] VAR76;
wire VAR43;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv.pp.blackbox.v | 1,259 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR5,
VAR3,
VAR1 ,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR5;
input VAR3;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_registers.v | 37,690 | module MODULE1( VAR263, VAR120, VAR242, VAR248, VAR165, VAR27, VAR282,
VAR26, VAR148, VAR290, VAR269, VAR297,
VAR293, VAR210, VAR122, VAR246, VAR213,
VAR174, VAR123, VAR221, VAR220, VAR119, VAR153,
VAR209, VAR200, VAR138, VAR171, VAR236,
VAR214, VAR273, VAR40, VAR18, VAR6, VAR45,
VAR178, VAR136, VAR224, VAR141,
VAR66, ... | gpl-2.0 |
xcthulhu/periphondemand | src/library/components/uart16550/hdl/uart_regs.v | 29,205 | module MODULE1 (clk,
VAR53, VAR110, VAR134, VAR147, VAR106, VAR64,
VAR50,
VAR11, VAR80,
VAR31, VAR121, VAR93, VAR62, VAR82, VAR54, VAR164, VAR158, VAR40, VAR48, VAR113,
VAR29, VAR57, VAR61
, VAR133
);
input clk;
input VAR53;
input [VAR92-1:0] VAR110;
input [7:0] VAR134;
output [7:0] VAR147;
input VAR106;
input VAR64;
o... | lgpl-2.1 |
chiragsakhuja/gpu | pll.v | 17,222 | module MODULE1 (
input wire VAR4, input wire rst, output wire VAR1, output wire VAR2 );
VAR5 VAR3 (
.VAR4 (VAR4), .rst (rst), .VAR1 (VAR1), .VAR2 (VAR2) );
endmodule | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/offset_flag_to_one_hot.v | 2,687 | module MODULE1
parameter VAR2 = 4
)
(
input [VAR1(VAR2)-1:0] VAR3,
input VAR4,
output [VAR2-1:0] VAR5
);
assign VAR5 = {{(VAR2-1){1'b0}},VAR4} << VAR3;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4_2.v | 2,231 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR8 ,
VAR3 ,
VAR10 ,
VAR5,
VAR7,
VAR1 ,
VAR9
);
output VAR11 ;
input VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR10 ;
input VAR5;
input VAR7;
input VAR1 ;
input VAR9 ;
VAR4 VAR2 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.... | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/glbl.v | 1,310 | module MODULE1 ();
parameter VAR29 = 1000;
parameter VAR19 = 0;
wire VAR6;
wire VAR24;
wire VAR27;
wire VAR17;
tri1 VAR9;
tri (weak1, strong0) VAR3 = VAR9;
reg VAR5;
reg VAR13;
reg VAR14;
wire VAR2;
wire VAR18;
wire VAR7;
wire VAR16;
wire VAR15;
reg VAR11;
reg VAR21;
reg VAR1;
reg VAR10;
reg VAR28;
reg VAR12 = 0;
reg V... | lgpl-3.0 |
jairov4/puj-ca-de1-audio-pump | ip/i2c_opencores/i2c_opencores.v | 1,974 | module MODULE1
(
VAR10, VAR12, VAR19, VAR5, VAR9,
VAR20, VAR16, VAR8, VAR21,
VAR11, VAR22
);
input VAR10; input VAR12;
input [2:0] VAR19; input [7:0] VAR5; output [7:0] VAR9; input VAR20; input VAR16; output VAR8; output VAR21;
inout VAR11; inout VAR22;
wire VAR3; wire VAR18;
wire VAR2;
wire VAR11;
wire VAR4;
assign VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b.blackbox.v | 1,326 | module MODULE1 (
VAR7 ,
VAR1,
VAR6 ,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR1;
input VAR6 ;
input VAR4 ;
input VAR8 ;
supply1 VAR5;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
HarmonInstruments/verilog | sincos/dual_cos.v | 1,466 | module MODULE1 (input VAR4,
input [25:0] VAR1, VAR13,
output signed [VAR7-1:0] o0, o1);
parameter VAR7 = 23;
reg [23:0] VAR19 = 0;
reg [23:0] VAR11 = 0;
reg VAR12 = 0;
reg VAR6 = 0;
always @ (posedge VAR4) begin
VAR19 <= VAR1[24] ? ~ VAR1[23:0] : VAR1[23:0];
VAR11 <= VAR13[24] ? ~ VAR13[23:0] : VAR13[23:0];
VAR12 <= VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.behavioral.pp.v | 1,969 | module MODULE1 (
VAR2 ,
VAR15 ,
VAR11 ,
VAR3,
VAR1,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR15 ;
input VAR11 ;
input VAR3;
input VAR1;
input VAR5 ;
input VAR8 ;
wire VAR9 ;
wire VAR14 ;
wire VAR13;
not VAR6 (VAR9 , VAR15 );
and VAR7 (VAR14 , VAR9, VAR11 );
VAR12 VAR4 (VAR13, VAR14, VAR3, VAR1);
buf VAR10 (VAR2 , VAR13 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3_2.v | 2,169 | module MODULE2 (
VAR9 ,
VAR3 ,
VAR6 ,
VAR4 ,
VAR2,
VAR1,
VAR7 ,
VAR10
);
output VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR4 ;
input VAR2;
input VAR1;
input VAR7 ;
input VAR10 ;
VAR8 VAR5 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODULE... | apache-2.0 |
jairov4/accel-oil | solution_spartan3/impl/verilog/nfa_accept_samples_generic_hw_mul_16ns_8ns_24_9.v | 1,752 | module MODULE1(clk, VAR13, VAR1, VAR22, VAR3);
input clk;
input VAR13;
input[16 - 1 : 0] VAR1; input[8 - 1 : 0] VAR22; output[24 - 1 : 0] VAR3;
reg[16 - 1 : 0] VAR15;
reg[8 - 1 : 0] VAR12;
wire [24 - 1 : 0] VAR10;
reg[24 - 1 : 0] VAR18;
reg[24 - 1 : 0] VAR9;
reg[24 - 1 : 0] VAR6;
reg[24 - 1 : 0] VAR2;
reg[24 - 1 : 0] V... | lgpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/clk_166M_83M/example_design/clk_166M_83M_exdes.v | 5,559 | module MODULE1
parameter VAR13 = 100
)
( input VAR10,
input VAR15,
output [3:1] VAR20,
input VAR6,
output VAR18
);
localparam VAR9 = 16;
localparam VAR8 = 3;
genvar VAR16;
wire VAR19 = !VAR18 || VAR6 || VAR15;
reg [VAR8:1] VAR7;
reg [VAR8:1] VAR3;
reg [VAR8:1] VAR17;
reg [VAR8:1] VAR21;
wire [VAR8:1] VAR11;
wire [VAR8:... | gpl-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/Timing.v | 2,198 | module MODULE1(
output reg VAR15,
input VAR17,
input clk,
input [7:0] VAR13,
input [7:0] VAR18,
input [1:0] VAR11,
input [3:0] VAR14,
input [7:0] VAR8,
output reg VAR20
);
reg [4:0] VAR16=0;
VAR5 VAR15=0;
reg [7:0] VAR10;
reg [7:0] VAR4=0;
reg [7:0] VAR1=0;
reg VAR7 = 1'b0, VAR3 = 1'b0, VAR9 = 1'b0;
always @ (posedge c... | gpl-3.0 |
hanw/sonic-lite | hw/verilog/traffic_controller/avalon_st_traffic_controller.v | 5,973 | module MODULE1 (
input wire VAR71 ,
input wire VAR39 ,
output wire VAR66,
input wire[23:0] VAR63 ,
output wire[31:0] VAR16 ,
input wire[31:0] VAR33 ,
input wire VAR72 ,
input wire VAR19 ,
input wire[39:0] VAR3 ,
input wire VAR34 ,
input wire VAR36 ,
input wire VAR6 ,
output wire VAR26 ,
output wire VAR20 ,
output wire ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbp/sky130_fd_sc_lp__dfbbp.pp.blackbox.v | 1,465 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1 ,
VAR5 ,
VAR8 ,
VAR2,
VAR9 ,
VAR7 ,
VAR10 ,
VAR4
);
output VAR6 ;
output VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR8 ;
input VAR2;
input VAR9 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or4bb/sky130_fd_sc_ms__or4bb.behavioral.v | 1,510 | module MODULE1 (
VAR10 ,
VAR1 ,
VAR7 ,
VAR14,
VAR3
);
output VAR10 ;
input VAR1 ;
input VAR7 ;
input VAR14;
input VAR3;
supply1 VAR6;
supply0 VAR9;
supply1 VAR11 ;
supply0 VAR12 ;
wire VAR13;
wire VAR2;
nand VAR5 (VAR13, VAR3, VAR14 );
or VAR8 (VAR2, VAR7, VAR1, VAR13);
buf VAR4 (VAR10 , VAR2 );
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_0/synth/system_auto_us_0.v | 9,997 | module MODULE1 (
VAR39,
VAR102,
VAR24,
VAR29,
VAR44,
VAR69,
VAR6,
VAR76,
VAR11,
VAR47,
VAR10,
VAR98,
VAR93,
VAR88,
VAR35,
VAR68,
VAR79,
VAR63,
VAR83,
VAR25,
VAR95,
VAR77,
VAR55,
VAR87,
VAR16,
VAR97,
VAR100,
VAR3,
VAR53,
VAR90,
VAR21,
VAR70,
VAR58,
VAR80
);
input wire VAR39;
input wire VAR102;
input wire [31 : 0] VAR24;... | mit |
SymbiFlow/fpga-tool-perf | third_party/rsdecoder/rsdecoder.v | 30,571 | module MODULE15(VAR34, VAR17, VAR160, enable, valid, VAR6, clk, VAR39);
input enable, clk, VAR39;
input [4:0] VAR6, VAR34;
output [4:0] VAR17;
wire [4:0] VAR17;
output VAR160, valid;
reg valid;
wire VAR160;
wire [4:0] VAR113, VAR51, VAR211, VAR238, VAR23, VAR116, VAR159, VAR208, VAR18, VAR218, VAR138, VAR63;
wire [4:0]... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.functional.pp.v | 1,934 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR13 ,
VAR1,
VAR8,
VAR15 ,
VAR14
);
output VAR3 ;
input VAR10 ;
input VAR13 ;
input VAR1;
input VAR8;
input VAR15 ;
input VAR14 ;
wire VAR2 ;
wire VAR7 ;
wire VAR6;
not VAR4 (VAR2 , VAR10 );
and VAR9 (VAR7 , VAR2, VAR13 );
VAR11 VAR12 (VAR6, VAR7, VAR1, VAR8);
buf VAR5 (VAR3 , VAR6 );
e... | apache-2.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/openMSP430_fpga.v | 23,433 | module MODULE1 (
VAR213, VAR149, VAR112, VAR63, VAR180, VAR156, VAR106, VAR226,
VAR27, VAR191, VAR175, VAR39, VAR4 );
output VAR213; output VAR149; output [9:0] VAR112; output VAR63; output VAR180; output VAR156; output VAR106; output VAR226;
input VAR27; input VAR191; input VAR175; input VAR39; input [9:0] VAR4;
wire ... | bsd-3-clause |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_fptrunc.v | 20,404 | module MODULE1
(
VAR81,
VAR75,
VAR10,
VAR33) ;
input VAR81;
input VAR75;
input [63:0] VAR10;
output [31:0] VAR33;
tri1 VAR81;
reg [11:0] VAR86;
reg VAR24;
reg VAR19;
reg VAR36;
reg VAR49;
reg VAR21;
reg VAR52;
reg VAR37;
reg VAR50;
reg [22:0] VAR2;
reg VAR34;
reg VAR16;
reg [22:0] VAR84;
reg [10:0] VAR61;
reg [22:0] VA... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_cmd_gen.v | 125,864 | module MODULE1
VAR206 = 33,
VAR126 = 3,
VAR337 = 8,
VAR270 = 4,
VAR355 = 4,
VAR313 = 5,
VAR196 = 2,
VAR48 = 2,
VAR358 = 5,
VAR147 = 2,
VAR321 = 2, VAR264 = 8,
VAR184 = 1, VAR99 = 1, VAR176 = 3,
VAR170 = 13,
VAR236 = 10,
VAR277 = 10,
VAR39 = 1,
VAR258 = 1,
VAR210 = 0,
VAR197 = 4,
VAR127 = 4,
VAR240 = 8,
VAR16 = 12,
VAR1... | lgpl-3.0 |
LordRafa/Sobel-FPGA | Project_With_Cache/ip/SIS/Sobel_cache.v | 4,994 | module MODULE1 (
input clk,
input rst,
input VAR51,
input [VAR33-1:0] VAR44,
input [13:0] VAR72,
output wire [12:0] VAR50,
input VAR11,
output wire [ 7:0] VAR65,
output wire [VAR33-1:0] VAR30,
input VAR59,
input VAR43,
output wire [VAR46-1:0] VAR41,
output wire VAR6,
input [VAR55-1:0] VAR16,
output wire [VAR29-1:0] VAR... | gpl-2.0 |
ncos/Xilinx-Verilog | INTERFACES/src/CAN/can_controller.v | 3,579 | module MODULE1
(
input wire VAR5,
input wire VAR1,
inout wire VAR3,
input wire [107:0] VAR2,
output reg [107:0] VAR4,
input wire VAR13,
output reg VAR15 = 1'b0,
output reg VAR22 = 1'b0
);
wire VAR7;
wire VAR6;
wire VAR10;
wire VAR21;
wire VAR17;
reg [107:0] VAR19 = 108'd0;
reg VAR18 = 1'b0; reg VAR23 = 1'b0; reg VAR14 ... | mit |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_jtag_uart_0.v | 23,624 | module MODULE2 (
clk,
VAR33,
VAR81,
valid
)
;
input clk;
input [ 7: 0] VAR33;
input VAR81;
input valid;
reg [31:0] VAR68; VAR67 VAR68 =
always @(posedge clk) begin
if (valid && VAR81) begin
VAR49 (VAR68);
end
end
endmodule
module MODULE7 (
clk,
VAR44,
VAR74,
VAR82,
VAR56,
VAR55,
VAR23
)
;
output VAR82;
output [ 7: 0] V... | apache-2.0 |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/serialcontrol.v | 3,471 | module MODULE1(
input wire VAR10,
input wire rst,
input wire[2:0] VAR30,
input wire VAR33,
input wire[7:0] VAR4,
output wire[31:0] VAR6,
output wire VAR26,
input wire VAR36,
output wire VAR2
);
reg[7:0] buffer[0:15];
reg[3:0] VAR32;
reg[3:0] VAR16;
wire VAR21;
wire[7:0] VAR31;
wire VAR28;
reg[7:0] VAR9;
wire[3:0] VAR19... | unlicense |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_pad_logic.v | 4,612 | module MODULE1(
VAR21,
VAR1, VAR17,
VAR13,
VAR2, VAR16, clk, VAR33, VAR39, VAR5,
VAR29, VAR7, VAR8
);
input VAR2;
input VAR16;
input clk;
input VAR5;
input VAR33;
input VAR39;
input VAR29;
input VAR7;
input VAR8;
output VAR21;
output VAR1;
output [1:0] VAR17;
output [1:0] VAR13;
wire VAR22;
wire VAR6;
wire VAR41;
wire ... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_mout/rtl/jbi_j_par_chk.v | 10,652 | module MODULE1 (
VAR7, VAR36, VAR22,
VAR16, VAR65,
VAR31, VAR101, VAR34,
VAR98,
VAR128, VAR107, VAR4, VAR58, VAR94,
VAR5, VAR38, VAR131, clk, VAR112
);
input VAR128;
input VAR107;
input VAR4;
input VAR58;
input [2:0] VAR94; input [2:0] VAR5; input [2:0] VAR38;
input [2:0] VAR131;
output VAR7; output VAR36; output [2:0]... | gpl-2.0 |
ptracton/vscale_soc | rtl/wb_riscvscale/wb_vscale.v | 12,119 | module MODULE1 (
input clk,
input rst,
input [VAR41-1:0] VAR47,
output [31:0] VAR22,
output VAR62,
output VAR24,
output [3:0] VAR27,
output VAR44,
output [2:0] VAR53,
output [1:0] VAR58,
output [31:0] VAR35,
input VAR7,
input VAR55,
input [31:0] VAR61,
input VAR38,
output [31:0] VAR8,
output VAR11,
output VAR13,
output... | mit |
migajv/mips_pipeline | verilog/control.v | 1,223 | module MODULE1(
input wire [5:0] VAR4,
output wire VAR5, VAR10, VAR2,
output wire [1:0] VAR6,
output wire [1:0] VAR12,
output wire VAR14, VAR8, VAR13);
reg VAR16, VAR17, VAR9, VAR7, VAR1, VAR3;
always @(*) begin
VAR16 <= 1'b0;
VAR17 <= 1'b0;
VAR9 <= 1'b0;
VAR7 <= 1'b0;
VAR1 <= 1'b0;
VAR3 <= 1'b0;
case (VAR4)
6'b100011:... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_037.v | 1,451 | module MODULE2 (
VAR5,
VAR9
);
input [31:0] VAR5;
output [31:0]
VAR9;
wire [31:0]
VAR11,
VAR10,
VAR8,
VAR1,
VAR6,
VAR7,
VAR2;
assign VAR11 = VAR5;
assign VAR2 = VAR7 << 1;
assign VAR8 = VAR10 - VAR11;
assign VAR10 = VAR11 << 9;
assign VAR7 = VAR6 - VAR10;
assign VAR6 = VAR1 - VAR11;
assign VAR1 = VAR8 << 4;
assign VAR9... | mit |
rkrajnc/minimig-mist | rtl/minimig/rga_decode.v | 26,894 | module MODULE1 (
input wire [ 9-1:1] VAR323,
output reg [236-1:0] VAR372
);
always @ (*) begin
VAR372[VAR90 ] = 0;
VAR372[VAR149 ] = 0;
VAR372[VAR319 ] = 0;
VAR372[VAR244 ] = 0;
VAR372[VAR150 ] = 0;
VAR372[VAR422 ] = 0;
VAR372[VAR155 ] = 0;
VAR372[VAR128 ] = 0;
VAR372[VAR106 ] = 0;
VAR372[VAR44 ] = 0;
VAR372[VAR164 ] =... | gpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/buffer/buf/buf_add_manage.v | 2,566 | module MODULE1(
input clk,
input reset,
input [3:0] VAR27,
input VAR12,
input [3:0] VAR2,
input VAR3,
output reg VAR11,
output reg [3:0] VAR14
);
reg [3:0] VAR13;
wire VAR25,VAR26;
wire [3:0] VAR18,VAR16;
reg VAR7,VAR22;
reg [2:0] VAR6;
parameter VAR1 = 3'd0,
VAR15 = 3'd1,
VAR8 = 3'd2,
VAR17 = 3'd3,
VAR9 = 3'd4;
always... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/ip/hdl/verilog/image_filter_Block_proc.v | 13,681 | module MODULE1 (
VAR33,
VAR53,
VAR46,
VAR55,
VAR63,
VAR4,
VAR15,
VAR32,
VAR7,
VAR31,
VAR38,
VAR35,
VAR60,
VAR24,
VAR44,
VAR25,
VAR17,
VAR3,
VAR57,
VAR26,
VAR29
);
parameter VAR2 = 1'b1;
parameter VAR8 = 1'b0;
parameter VAR12 = 1'b1;
parameter VAR58 = 32'b00000000000000000000000000000000;
parameter VAR61 = 1'b1;
paramet... | gpl-3.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/data_in.v | 7,203 | module MODULE3(clk,VAR21,VAR24,VAR25,VAR20,VAR2,VAR14,VAR4);
input clk,VAR21;
input VAR24;
input [4:0] VAR25;
input [3:0] VAR20;
output reg [3:0] VAR4;
output wire VAR2;
output wire VAR14;
wire VAR3,VAR22,VAR8;
wire [3:0] VAR19;
assign VAR15 = ~VAR3;
assign VAR1 = ~VAR22;
assign VAR14 = ~VAR8;
always @ ( VAR19 )
begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfxtp/sky130_fd_sc_hd__sdfxtp_2.v | 2,345 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR7,
VAR6,
VAR2 ,
VAR11
);
output VAR8 ;
input VAR10 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR7;
input VAR6;
input VAR2 ;
input VAR11 ;
VAR4 VAR1 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VA... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_asynch_rst_ff.v | 2,989 | module MODULE1 (
VAR1 ,
clk ,
reset ,
VAR2
);
input VAR1, clk, reset ;
output VAR2;
reg VAR2;
always @ ( posedge clk or posedge reset) begin
if (reset) begin
VAR2 <= 1'b1;
end else begin
VAR2 <= VAR1;
end
end
endmodule | gpl-3.0 |
MeshSr/onetswitch20 | ons20-app52-ref_ofshw/vivado/onets_7020_4x_ref_ofshw/ip/packet_pipeline_v1_0/src/user_data_path/dma_queue.v | 6,257 | module MODULE1
parameter VAR37 = 64,
parameter VAR39=VAR37/8,
parameter VAR17 = 0,
parameter VAR19 = 'hff,
parameter VAR38 = 0
)(
output [VAR37-1:0] VAR34,
output [VAR39-1:0] VAR15,
output VAR24,
input VAR3,
input [VAR37-1:0] VAR5,
input [VAR39-1:0] VAR33,
input VAR25,
output VAR1,
input [31:0] VAR31,
input VAR4,
input... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22ai/sky130_fd_sc_hvl__o22ai.blackbox.v | 1,368 | module MODULE1 (
VAR8 ,
VAR9,
VAR1,
VAR5,
VAR6
);
output VAR8 ;
input VAR9;
input VAR1;
input VAR5;
input VAR6;
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
martinmiranda14/Digitales | Lab_6/clkdiv/clkdiv.cache/ip/1ba1617468e3eb91/clk_wiz_0_stub.v | 1,305 | module MODULE1(VAR1, reset, VAR2, VAR3)
;
output VAR1;
input reset;
output VAR2;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.functional.pp.v | 1,895 | module MODULE1 (
VAR7,
VAR12,
VAR9 ,
VAR13 ,
VAR3 ,
VAR2 ,
VAR4
);
input VAR7;
input VAR12;
output VAR9 ;
input VAR13 ;
input VAR3 ;
input VAR2 ;
input VAR4 ;
wire VAR4 VAR14 ;
wire VAR5 ;
wire VAR11;
not VAR15 (VAR14 , VAR13 );
nand VAR6 (VAR5 , VAR4, VAR2, VAR3, VAR14 );
VAR10 VAR1 (VAR11, VAR5, VAR7, VAR12);
buf VAR... | apache-2.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | Dilation/ip/Dilation/acl_fp_convert_with_rounding_64.v | 11,654 | module MODULE1(VAR44, VAR5, VAR25, VAR33, VAR15, VAR34, VAR7, VAR9, enable);
parameter VAR35 = 1;
parameter VAR36 = 0;
parameter VAR27 = 1;
input VAR44;
input enable, VAR5;
input [31:0] VAR25;
output [63:0] VAR33;
input VAR15, VAR7;
output VAR9, VAR34;
wire VAR30;
wire [7:0] VAR29;
wire [22:0] VAR16;
wire [23:0] VAR8;
... | mit |
gtaylormb/fpga_nes | hw/zybo_vivado/zybo_vivado.runs/synth_1/nes_zybo_wrapper_X99.v | 3,841 | module MODULE1(VAR2,VAR1);
input[5:0] VAR2;
output reg[7:0] VAR1;
always @(VAR2)
begin
case(VAR2)
6'b000000: VAR1 = 8'b01101101;
6'b000001: VAR1 = 8'b00100010;
6'b000010: VAR1 = 8'b00000010;
6'b000011: VAR1 = 8'b01000010;
6'b000100: VAR1 = 8'b10000001;
6'b000101: VAR1 = 8'b10100000;
6'b000110: VAR1 = 8'b10100000;
6'b00... | bsd-2-clause |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_onchip_memory2_0.v | 2,974 | module MODULE1 (
address,
VAR25,
VAR27,
clk,
VAR29,
reset,
VAR12,
write,
VAR5,
VAR13
)
;
parameter VAR21 = "VAR20.VAR14";
output [ 31: 0] VAR13;
input [ 10: 0] address;
input [ 3: 0] VAR25;
input VAR27;
input clk;
input VAR29;
input reset;
input VAR12;
input write;
input [ 31: 0] VAR5;
wire VAR8;
wire [ 31: 0] VAR13;
w... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a221oi/sky130_fd_sc_hd__a221oi.functional.pp.v | 2,207 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR7 ,
VAR3 ,
VAR17 ,
VAR13 ,
VAR15,
VAR18,
VAR8 ,
VAR10
);
output VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR17 ;
input VAR13 ;
input VAR15;
input VAR18;
input VAR8 ;
input VAR10 ;
wire VAR20 ;
wire VAR16 ;
wire VAR12 ;
wire VAR4;
and VAR9 (VAR20 , VAR3, VAR17 );
and VAR14 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/xor2/sky130_fd_sc_ms__xor2.behavioral.v | 1,381 | module MODULE1 (
VAR6,
VAR4,
VAR10
);
output VAR6;
input VAR4;
input VAR10;
supply1 VAR2;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
wire VAR7;
xor VAR9 (VAR7, VAR10, VAR4 );
buf VAR3 (VAR6 , VAR7 );
endmodule | apache-2.0 |
jairov4/accel-oil | solution_kintex7/syn/verilog/sample_iterator_get_offset.v | 30,628 | module MODULE1 (
VAR65,
VAR7,
VAR105,
VAR49,
VAR62,
VAR26,
VAR89,
VAR35,
VAR88,
VAR55,
VAR87,
VAR43,
VAR9,
VAR11,
VAR51,
VAR106,
VAR45,
VAR81,
VAR50,
VAR85,
VAR97,
VAR21,
VAR99,
VAR2,
VAR42,
VAR24,
VAR79,
VAR27,
VAR69,
VAR34,
VAR63,
VAR15,
VAR73,
VAR86,
VAR58,
VAR90,
VAR93,
VAR72,
VAR101
);
input VAR65;
input VAR7;
inp... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbp/sky130_fd_sc_hs__dlrbp.pp.symbol.v | 1,423 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR6 ,
input VAR7,
input VAR5 ,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_2.behavioral.pp.v | 6,220 | module MODULE1( VAR26, VAR49, VAR18, VAR3, VAR9, VAR17, VAR58 );
input VAR18, VAR26, VAR49, VAR3;
inout VAR17, VAR58;
output VAR9;
reg VAR12;
VAR25 VAR44(.VAR26(VAR26),.VAR49(VAR49),.VAR18(VAR18),.VAR3(VAR3),.VAR9(VAR9),.VAR17(VAR17),.VAR58(VAR58),.VAR12(VAR12));
VAR25 VAR34(.VAR26(VAR26),.VAR49(VAR49),.VAR18(VAR18),.V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_4.functional.v | 1,585 | module MODULE1( VAR13, VAR15, VAR4, VAR7 );
input VAR15, VAR13, VAR4;
output VAR7;
wire VAR10;
not VAR19( VAR10, VAR4 );
wire VAR12;
and VAR16( VAR12, VAR10, VAR15, VAR13 );
wire VAR5;
not VAR2( VAR5, VAR13 );
wire VAR9;
and VAR11( VAR9, VAR5, VAR15, VAR4 );
wire VAR18;
not VAR6( VAR18, VAR15 );
wire VAR14;
and VAR8( V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311o/sky130_fd_sc_ms__a311o_1.v | 2,437 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR7 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR8,
VAR3,
VAR10 ,
VAR6
);
output VAR1 ;
input VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR3;
input VAR10 ;
input VAR6 ;
VAR11 VAR12 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8)... | apache-2.0 |
takeshineshiro/fpga_linear_128 | R_SEQ.v | 6,503 | module MODULE1 (
address,
VAR49,
VAR44);
input [7:0] address;
input VAR49;
output [127:0] VAR44;
wire [127:0] VAR29;
wire [127:0] VAR44 = VAR29[127:0];
VAR5 VAR33 (
.VAR24 (VAR49),
.VAR32 (address),
.VAR46 (VAR29),
.VAR48 (1'b0),
.VAR16 (1'b0),
.VAR19 (1'b1),
.VAR31 (1'b0),
.VAR27 (1'b0),
.VAR1 (1'b1),
.VAR53 (1'b1),
.... | mit |
mistryalok/Zedboard | learning/training/MSD/s07v2/vivado/project_2/project_2.srcs/sources_1/ipshared/Alok/sample_generator_v1_0/3db932ea/hdl/sample_generator_v1_0_M_AXIS.v | 3,056 | module MODULE1 #
(
parameter integer VAR2 = 32,
parameter integer VAR13 = 32
)
(
input wire [7:0] VAR14,
input wire VAR11,
input wire VAR1,
input wire VAR8,
output wire VAR9,
output wire [VAR2-1 : 0] VAR3,
output wire [(VAR2/8)-1 : 0] VAR12,
output wire VAR5,
input wire VAR7
);
reg [VAR2-1 : 0] VAR6;
assign VAR3 = VAR6... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_fifo_reorder.v | 3,401 | module MODULE1
, parameter VAR42(VAR28)
, parameter VAR27=VAR26(VAR28)
)
(
input VAR9
, input VAR17
, output VAR65
, output [VAR27-1:0] VAR51
, input VAR21
, input VAR47
, input [VAR27-1:0] VAR18
, input [VAR52-1:0] VAR6
, output VAR50
, output [VAR52-1:0] VAR45
, output [VAR27-1:0] VAR37
, input VAR67
, output logic V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai_2.v | 2,335 | module MODULE2 (
VAR11 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR9,
VAR1,
VAR10 ,
VAR4
);
output VAR11 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR9;
input VAR1;
input VAR10 ;
input VAR4 ;
VAR3 VAR5 (
.VAR11(VAR11),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.... | apache-2.0 |
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