repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
jotego/jt51 | syn/xilinx/ym09/hdl/ym09.v | 6,509 | module MODULE1(
input wire VAR98,
input wire VAR29,
input wire VAR50,
output wire VAR71,
inout wire [7:0] VAR61,
output wire VAR95,
output wire VAR19,
output wire VAR46,
output wire VAR16,
output wire VAR52,
input wire VAR9,
input wire VAR43,
input wire VAR34,
input wire VAR31,
input wire VAR87,
input wire VAR82,
outpu... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.behavioral.pp.v | 3,847 | module MODULE1( VAR7, VAR19, VAR5, VAR15, VAR13, VAR18 );
input VAR7, VAR19, VAR5;
inout VAR13, VAR18;
output VAR15;
reg VAR22;
VAR25 VAR6(.VAR7(VAR7),.VAR19(VAR19),.VAR5(VAR5),.VAR15(VAR15),.VAR13(VAR13),.VAR18(VAR18),.VAR22(VAR22));
VAR25 VAR8(.VAR7(VAR7),.VAR19(VAR19),.VAR5(VAR5),.VAR15(VAR15),.VAR13(VAR13),.VAR18(V... | apache-2.0 |
mbus/mbus | releases/mbus_example-v1.0/verilog/ablk.v | 2,375 | module MODULE1
(
VAR2, VAR5, VAR4, VAR1, VAR3 );
input VAR2;
input VAR5;
input VAR4;
input [3:0] VAR1;
input [3:0] VAR3;
always @(VAR2) begin
("%VAR6[1;34m",27);
("%VAR6[0m",27);
end
always @(VAR5) begin
("%VAR6[1;34m",27);
("%VAR6[0m",27);
end
always @(VAR4) begin
("%VAR6[1;34m",27);
("%VAR6[0m",27);
end
always @(VAR1... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.behavioral.pp.v | 1,182 | module MODULE1( VAR6, VAR3, VAR5, VAR4 );
input VAR6;
inout VAR5, VAR4;
output VAR3;
VAR1 VAR7(.VAR6(VAR6),.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR2(.VAR6(VAR6),.VAR3(VAR3),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkbuf/sky130_fd_sc_ms__clkbuf_16.v | 2,040 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR2,
VAR5,
VAR4 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR2;
input VAR5;
input VAR4 ;
input VAR1 ;
VAR3 VAR8 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR2;
supply0 VAR5;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.v | 2,175 | module MODULE2 (
VAR7 ,
VAR3 ,
VAR6,
VAR9,
VAR4,
VAR8 ,
VAR5
);
output VAR7 ;
input VAR3 ;
input VAR6;
input VAR9;
input VAR4;
input VAR8 ;
input VAR5 ;
VAR2 VAR1 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR7 ,
VAR3 ,
VAR6
);
output VAR7 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/diode/sky130_fd_sc_ls__diode.symbol.v | 1,245 | module MODULE1 (
input VAR5
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_mux_2to1_n/sky130_fd_sc_hd__udp_mux_2to1_n.blackbox.v | 1,236 | module MODULE1 (
VAR1 ,
VAR2,
VAR3,
VAR4
);
output VAR1 ;
input VAR2;
input VAR3;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfbbn/sky130_fd_sc_hd__dfbbn.pp.blackbox.v | 1,481 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR4 ,
VAR3 ,
VAR2 ,
VAR8,
VAR7 ,
VAR6 ,
VAR5 ,
VAR10
);
output VAR1 ;
output VAR9 ;
input VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR8;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR10 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_axi_st_converter.v | 57,284 | module MODULE1 #
( parameter
VAR79 = 4,
VAR216 = 32,
VAR119 = 4,
VAR94 = 3,
VAR116 = 2,
VAR166 = 2,
VAR77 = 4,
VAR157 = 3,
VAR156 = 32,
VAR184 = 4,
VAR71 = 32,
VAR193 = 5,
VAR47 = 4,
VAR114 = 32,
VAR11 = "VAR128",
VAR59 = 1
)
(
VAR141,
VAR111,
VAR183,
VAR2,
VAR138,
VAR96,
VAR22,
VAR142,
VAR27,
VAR218,
VAR167,
VAR14,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxtp/sky130_fd_sc_hd__dlxtp.functional.pp.v | 1,656 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR6,
VAR2,
VAR5,
VAR7 ,
VAR4
);
output VAR11 ;
input VAR10 ;
input VAR6;
input VAR2;
input VAR5;
input VAR7 ;
input VAR4 ;
wire VAR9;
VAR1 VAR3 (VAR9 , VAR10, VAR6, , VAR2, VAR5);
buf VAR8 (VAR11 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2.behavioral.v | 1,340 | module MODULE1 (
VAR3,
VAR10,
VAR5
);
output VAR3;
input VAR10;
input VAR5;
supply1 VAR8;
supply0 VAR9;
supply1 VAR4 ;
supply0 VAR2 ;
wire VAR6;
or VAR7 (VAR6, VAR5, VAR10 );
buf VAR1 (VAR3 , VAR6 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.behavioral.v | 1,163 | module MODULE1 ();
supply1 VAR2;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
rbarzic/async_logic | async_lib/single_rail_2ph/mousetrap/mousetrap_elt.v | 1,392 | module MODULE1 (
VAR15, VAR7, VAR8,
VAR22, VAR9, VAR24, VAR21
);
parameter VAR5=8;
parameter VAR17={VAR5{1'b0}};
output VAR15;
input VAR22;
input VAR9;
output VAR7;
input [VAR5-1:0] VAR24;
output [VAR5-1:0] VAR8;
input VAR21;
wire VAR1;
wire [VAR5:0] VAR23;
wire [VAR5:0] VAR11;
VAR4 VAR3(.VAR13(VAR9), .VAR6(VAR7), .VAR... | gpl-2.0 |
dekuNukem/FAP_Z80 | FAP_modules/video_card/FPGA_code/src/cpu_vreg.v | 1,236 | module MODULE1(
input wire clk,
input wire VAR10,
input wire VAR3,
input wire VAR9,
input wire VAR12,
output reg [7:0] VAR2,
input wire [15:0] VAR15,
inout wire [7:0] VAR13,
output reg VAR5,
output reg VAR6,
output reg [12:0] VAR1,
output reg [7:0] VAR8
);
reg VAR4;
assign VAR13 = VAR4 ? VAR8 : 8'VAR11;
always @(posedg... | mit |
scalable-networks/ext | uhd/fpga/usrp2/fifo/valve36.v | 1,401 | module MODULE1
(input clk, input reset, input VAR11,
input VAR1,
input [35:0] VAR10, input VAR7, output VAR5,
output [35:0] VAR9, output VAR3, input VAR4);
reg VAR2, VAR6;
wire VAR8 = (VAR7 & VAR5)? ~VAR10[33] : VAR6;
assign VAR9 = VAR10;
assign VAR5 = VAR2 ? 1'b1 : VAR4;
assign VAR3 = VAR2 ? 1'b0 : VAR7;
always @(pose... | gpl-2.0 |
benreynwar/fpga-sdrlib | verilog/fpgamath/multiply.v | 1,109 | module MODULE2
(output reg signed [35:0] VAR12,
input signed [17:0] VAR1,
input signed [17:0] VAR3,
input VAR7, input VAR4, input VAR13 );
always @(posedge VAR7)
if(VAR13)
VAR12 <= 36'VAR6;
else if(VAR4)
begin
VAR12 <= VAR1 * VAR3;
end
endmodule
module MODULE1
parameter VAR11 = 0
)
(
input wire clk,
input wire VAR9,
in... | mit |
ELBe7ery/i2c_draft_gsoc | Top module/rtl/i2cslave.v | 4,934 | module MODULE1 ( input VAR13, output VAR2, output reg [7:0] VAR1 );
parameter [7:0] VAR9=8'b10101011; parameter [4:0] VAR7=0, VAR8=1, VAR3=8, VAR16=9,
VAR14=17, VAR15=18, VAR4=19;
reg [4:0] VAR10 =0; reg VAR18 =0; assign VAR2 = (VAR18)? 0:1'VAR11; wire VAR6;
reg [7:0] VAR19; reg VAR12 =0, VAR5 =0; assign VAR6= VAR12 ^ ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.behavioral.v | 3,407 | module MODULE1 (
VAR11 ,
VAR12 ,
VAR16 ,
VAR34 ,
VAR22 ,
VAR1 ,
VAR29 ,
VAR37
);
output VAR11 ;
output VAR12 ;
input VAR16 ;
input VAR34 ;
input VAR22 ;
input VAR1 ;
input VAR29 ;
input VAR37;
supply1 VAR5;
supply0 VAR26;
supply1 VAR24 ;
supply0 VAR2 ;
wire VAR19 ;
wire VAR15 ;
wire VAR33 ;
wire VAR14 ;
reg VAR6 ;
wire... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/buf/gf180mcu_fd_sc_mcu7t5v0__buf_1.behavioral.v | 1,093 | module MODULE1( VAR1, VAR4 );
input VAR1;
output VAR4;
VAR2 VAR3(.VAR1(VAR1),.VAR4(VAR4));
VAR2 VAR5(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai_2.v | 2,411 | module MODULE2 (
VAR1 ,
VAR3,
VAR11,
VAR6 ,
VAR10 ,
VAR7,
VAR2,
VAR9 ,
VAR8
);
output VAR1 ;
input VAR3;
input VAR11;
input VAR6 ;
input VAR10 ;
input VAR7;
input VAR2;
input VAR9 ;
input VAR8 ;
VAR5 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR8... | apache-2.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/addsub/FSM_Add_Subtract.v | 8,934 | module MODULE1
(
input wire clk, input wire rst, input wire VAR12,
input wire VAR10,
input wire VAR19,
input wire VAR40,
input wire VAR28,
input wire VAR20,
output wire VAR31, output wire VAR2,
output reg VAR21, output reg VAR3,
output reg VAR30,
output reg VAR8, output reg VAR18, output reg VAR13,
output reg VAR16,
ou... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai33/gf180mcu_fd_sc_mcu9t5v0__oai33_1.behavioral.pp.v | 5,425 | module MODULE1( VAR3, VAR9, VAR8, VAR5, VAR12, VAR4, VAR1, VAR7, VAR6 );
input VAR12, VAR4, VAR1, VAR8, VAR9, VAR3;
inout VAR7, VAR6;
output VAR5;
VAR10 VAR11(.VAR3(VAR3),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR12(VAR12),.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR6(VAR6));
VAR10 VAR2(.VAR3(VAR3),.VAR9(VAR9),.VAR8(VAR8),.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfstp/sky130_fd_sc_hd__sdfstp.functional.pp.v | 2,163 | module MODULE1 (
VAR11 ,
VAR15 ,
VAR9 ,
VAR2 ,
VAR19 ,
VAR18,
VAR4 ,
VAR5 ,
VAR10 ,
VAR1
);
output VAR11 ;
input VAR15 ;
input VAR9 ;
input VAR2 ;
input VAR19 ;
input VAR18;
input VAR4 ;
input VAR5 ;
input VAR10 ;
input VAR1 ;
wire VAR12 ;
wire VAR8 ;
wire VAR13;
not VAR3 (VAR8 , VAR18 );
VAR17 VAR7 (VAR13, VAR9, VAR2,... | apache-2.0 |
horia141/bachelor-thesis | prj/components/VGA2/VGA2Interface.v | 3,834 | module MODULE1(VAR27,reset,VAR24,VAR29,VAR9,VAR19,VAR21,VAR23,VAR13,VAR17,VAR30,VAR3);
parameter VAR5 = 11;
parameter VAR2 = 800;
parameter VAR18 = 56;
parameter VAR1 = 120;
parameter VAR11 = 64;
parameter VAR8 = 11;
parameter VAR15 = 600;
parameter VAR25 = 37;
parameter VAR6 = 6;
parameter VAR16 = 23;
input wire VAR27... | mit |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/reader/rfid_reader_rx.v | 3,937 | module MODULE1 (
reset, clk, VAR2,
VAR9, VAR5,
VAR21, VAR31, VAR25,
VAR8, VAR10, VAR14,
VAR13, VAR23
);
input reset, clk, VAR2;
output VAR9, VAR5;
input [2:0] VAR21;
input VAR31;
input VAR25;
input [15:0] VAR14;
input [15:0] VAR8;
input [15:0] VAR10;
output [1023:0] VAR13;
output [9:0] VAR23;
reg [1023:0] VAR13;
reg [9... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2/sky130_fd_sc_lp__nand2_1.v | 2,097 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR5 ,
VAR6,
VAR8,
VAR9 ,
VAR2
);
output VAR4 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR8;
input VAR9 ;
input VAR2 ;
VAR1 VAR3 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR4,
VAR7,
VAR5
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai_4.v | 2,473 | module MODULE2 (
VAR9 ,
VAR11 ,
VAR4 ,
VAR6 ,
VAR1 ,
VAR8 ,
VAR10,
VAR5,
VAR2 ,
VAR7
);
output VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR6 ;
input VAR1 ;
input VAR8 ;
input VAR10;
input VAR5;
input VAR2 ;
input VAR7 ;
VAR3 VAR12 (
.VAR9(VAR9),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR10(V... | apache-2.0 |
AquarHEAD/stopwatch | src/display_16.v | 1,195 | module MODULE1(
input wire clk,
input wire[15:0] VAR1,
output reg[3:0] VAR3,
output reg[7:0] VAR4);
reg[3:0] VAR5 = 4'b0;
reg[15:0] VAR2 = 16'b0;
always @(posedge clk) begin
case (VAR2[15:14])
2'b00: begin
VAR3 <= 4'b1110;
VAR5 <= VAR1[3:0];
end
2'b01: begin
VAR3 <= 4'b1101;
VAR5 <= VAR1[7:4];
end
2'b10: begin
VAR3 <= ... | mit |
CeesWolfs/ceespu | src/gpu/primitives/serdes_n_to_1.v | 4,984 | module MODULE1 (
input VAR81,
input VAR53,
input rst,
input VAR42,
input [4:0] VAR1,
output reg VAR37
);
localparam VAR61 = 3'h5;
reg [7:0] VAR35;
integer VAR51;
wire [1-1:0] VAR23;
wire [1-1:0] VAR58;
wire [1-1:0] VAR32;
wire [1-1:0] VAR77;
wire [1-1:0] VAR44;
wire [1-1:0] VAR31;
reg [1-1:0] VAR71;
reg [1-1:0] VAR19;
... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/Oper_Start_In_syn.v | 41,476 | module MODULE6 ( clk, rst, VAR90, VAR246, VAR291 );
input [31:0] VAR246;
output [31:0] VAR291;
input clk, rst, VAR90;
wire VAR127, VAR352, VAR75, VAR81, VAR147, VAR182, VAR18, VAR277, VAR200, VAR353, VAR244, VAR196, VAR54, VAR364, VAR307, VAR241,
VAR249, VAR183, VAR231, VAR262, VAR33, VAR276, VAR109, VAR324, VAR105, VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and2/sky130_fd_sc_ls__and2.functional.pp.v | 1,783 | module MODULE1 (
VAR13 ,
VAR8 ,
VAR11 ,
VAR3,
VAR9,
VAR5 ,
VAR12
);
output VAR13 ;
input VAR8 ;
input VAR11 ;
input VAR3;
input VAR9;
input VAR5 ;
input VAR12 ;
wire VAR4 ;
wire VAR6;
and VAR2 (VAR4 , VAR8, VAR11 );
VAR10 VAR7 (VAR6, VAR4, VAR3, VAR9);
buf VAR1 (VAR13 , VAR6 );
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/system/synthesis/submodules/lsu_atomic.v | 14,521 | module MODULE1
(
clk, reset, VAR85, VAR55, VAR92, VAR65, VAR62, VAR29, VAR94,
VAR74, VAR25, VAR45, VAR81, VAR54, VAR26,
VAR75,
VAR56,
VAR67,
VAR58, VAR17, VAR57, VAR68, VAR20
);
parameter VAR73=32; parameter VAR63=4; parameter VAR51=32; parameter VAR96=32; parameter VAR46=2; parameter VAR48=32; parameter VAR69=0;
param... | mit |
ptracton/wb_soc_template | rtl/ALTERA/altera_syscon_pll_bb.v | 11,305 | module MODULE1 (
VAR3,
VAR2,
VAR4,
VAR1);
input VAR3;
input VAR2;
output VAR4;
output VAR1;
tri0 VAR3;
endmodule | mit |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/ISP1362.v | 4,179 | module MODULE1 (
input wire VAR21, input wire VAR9, input wire [15:0] VAR8, output wire [15:0] VAR3, input wire VAR11, input wire VAR28, input wire VAR15, input wire VAR13, output wire VAR6, input wire VAR23, input wire VAR25, input wire [15:0] VAR16, output wire [15:0] VAR20, input wire VAR26, input wire VAR2, input w... | gpl-3.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_bridge_v1_07_a/hdl/verilog/radio_bridge.v | 9,929 | module MODULE1
(
VAR75,
VAR78,
VAR46,
VAR63,
VAR27,
VAR15,
VAR34,
VAR59,
VAR21,
VAR55,
VAR44,
VAR6,
VAR1,
VAR42,
VAR19,
VAR79,
VAR52,
VAR41,
VAR24,
VAR23,
VAR22,
VAR10,
VAR11,
VAR40,
VAR48,
VAR9,
VAR3,
VAR74,
VAR56,
VAR7,
VAR4,
VAR67,
VAR25,
VAR86,
VAR30,
VAR73,
VAR47,
VAR71,
VAR32,
VAR16,
VAR58,
VAR39,
VAR66,
VAR62,
V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.pp.symbol.v | 1,368 | module MODULE1 (
input VAR4 ,
input VAR2 ,
input VAR1 ,
input VAR6 ,
output VAR7 ,
input VAR9 ,
input VAR8,
input VAR5,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22ai/sky130_fd_sc_hs__o22ai_2.v | 2,225 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR4 ,
VAR6 ,
VAR5 ,
VAR1,
VAR7
);
output VAR8 ;
input VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR1;
input VAR7;
VAR3 VAR9 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8 ,
VAR2,
VAR4,
VAR6,
VAR5
);... | apache-2.0 |
mosukiton/mipsprocessor | Mips_single_cycle.srcs/sources_1/new/regfile.v | 2,077 | module MODULE1(
output [31:0] VAR7, VAR2,
input [4:0] VAR5, VAR9, VAR3,
input [31:0] VAR8,
input VAR1, clk
);
reg [31:0] VAR6 [0:31];
VAR4 VAR6[0] = 32'h00000000;
always @ * if (VAR1 & (VAR3 != 5'b00000)) begin
VAR6[VAR3] <= VAR8;
end
assign VAR7 = (VAR5 != 0) ? VAR6[VAR5] : 0;
assign VAR2 = (VAR9 != 0) ? VAR6[VAR9] : ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.behavioral.pp.v | 2,196 | module MODULE1 (
VAR5 ,
VAR14 ,
VAR15 ,
VAR16,
VAR9,
VAR12,
VAR7 ,
VAR13
);
output VAR5 ;
input VAR14 ;
input VAR15 ;
input VAR16;
input VAR9;
input VAR12;
input VAR7 ;
input VAR13 ;
wire VAR18 ;
wire VAR4 ;
wire VAR8 ;
wire VAR2;
not VAR17 (VAR18 , VAR16 );
or VAR6 (VAR4 , VAR15, VAR14 );
nand VAR10 (VAR8 , VAR18, VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/phy/phy_pd_top.v | 16,207 | module MODULE1 #
(
parameter VAR18 = 100, parameter VAR54 = 3, parameter VAR64 = 8, parameter VAR48 = 16, parameter VAR27 = "VAR5", parameter VAR36 = 8, parameter VAR59 = "VAR50", parameter VAR30 = "VAR51", parameter VAR32 = "VAR17" )
(
input clk,
input rst,
input VAR35, output VAR58, input VAR45, input VAR63, output r... | lgpl-3.0 |
manili/Pipelined_6502 | Write_Back.v | 2,122 | module MODULE1(
VAR6,
VAR28,
VAR18,
VAR26,
VAR20,
VAR4,
VAR23,
VAR10,
VAR16,
VAR17,
VAR13,
VAR25,
VAR9,
VAR12,
VAR8,
VAR15
,VAR22
);
input wire VAR6;
input wire VAR28;
input wire VAR18;
input wire VAR26;
input wire [VAR5 - 1:0] VAR20;
input wire [7:0] VAR4;
input wire [15:0] VAR23;
input wire [15:0] VAR10;
input wire V... | gpl-3.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_SRAM_SS_210930.v | 11,817 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
not (VAR2, VAR1); | bsd-3-clause |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/debug_unit.v | 4,020 | module MODULE1 #(parameter VAR14=1)(
input wire clk,
input wire reset,
input wire [32*VAR14-1:0] VAR23,
input wire VAR36,
input wire [112:0] VAR25,
output wire [64:0] VAR24
);
wire [VAR14-1:0] VAR11;
wire [31:0] VAR13 [VAR14-1:0];
wire [12:0] VAR26 [VAR14-1:0];
wire [12:0] VAR40 [VAR14-1:0];
wire [VAR14-1:0] VAR38;
wir... | gpl-2.0 |
Digilent/vivado-library | ip/Pmods/PmodBLE_v1_0/src/PmodBLE.v | 19,246 | module MODULE1
(VAR171,
VAR177,
VAR66,
VAR144,
VAR125,
VAR180,
VAR109,
VAR95,
VAR76,
VAR36,
VAR35,
VAR15,
VAR136,
VAR87,
VAR47,
VAR39,
VAR148,
VAR92,
VAR104,
VAR159,
VAR133,
VAR38,
VAR32,
VAR90,
VAR68,
VAR45,
VAR13,
VAR40,
VAR127,
VAR71,
VAR21,
VAR84,
VAR99,
VAR132,
VAR121,
VAR190,
VAR51,
VAR18,
VAR6,
VAR151,
VAR131,
V... | mit |
manu3193/ControladorElevadorTDD | DecoGreytoBCD.v | 1,115 | module MODULE1(
VAR3, VAR4 );
input [2:0] VAR3;
output [2:0] VAR4;
assign VAR4[2] = VAR3[2];
xor VAR2(VAR4[1], VAR3[2], VAR3[1]);
xor VAR1(VAR4[0], VAR4[1], VAR3[0]);
endmodule | mit |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_mm_interconnect_0_avalon_st_adapter.v | 6,167 | module MODULE1 #(
parameter VAR18 = 34,
parameter VAR23 = 0,
parameter VAR5 = 34,
parameter VAR11 = 0,
parameter VAR3 = 0,
parameter VAR13 = 0,
parameter VAR9 = 1,
parameter VAR6 = 1,
parameter VAR22 = 0,
parameter VAR16 = 34,
parameter VAR17 = 0,
parameter VAR2 = 1,
parameter VAR10 = 0,
parameter VAR21 = 1,
parameter ... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/nios_system_uart_0.v | 28,386 | module MODULE1 (
VAR99,
VAR4,
clk,
VAR27,
VAR31,
VAR35,
VAR36,
VAR90,
VAR7,
VAR97,
VAR72,
VAR3,
VAR49
)
;
output VAR97;
output VAR72;
output VAR3;
output VAR49;
input [ 8: 0] VAR99;
input VAR4;
input clk;
input VAR27;
input VAR31;
input VAR35;
input VAR36;
input [ 7: 0] VAR90;
input VAR7;
reg VAR91;
reg [ 8: 0] VAR14;
... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_1c_v1_00_a/hdl/verilog/cf_adc_wr.v | 5,529 | module MODULE1 (
VAR3,
VAR25,
VAR10,
VAR17,
VAR30,
VAR21,
VAR24,
VAR26,
VAR2,
VAR22,
VAR11,
VAR23,
VAR8,
VAR20,
VAR12,
VAR19,
VAR5,
VAR9,
VAR27,
VAR29,
VAR28,
VAR15,
VAR16,
VAR13);
parameter VAR6 = 0;
input VAR3;
input VAR25;
input [ 7:0] VAR10;
input [ 7:0] VAR17;
input VAR30;
input VAR21;
output VAR24;
output VAR26;
... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v | 48,109 | module MODULE1 #
( parameter
VAR73 = 80,
VAR94 = 32,
VAR64 = 2,
VAR21 = 40,
VAR12 = 5,
VAR65 = 8,
VAR55 = 1,
VAR127 = 0,
VAR8 = 0,
VAR54 = 0,
VAR100 = 8,
VAR139 = 1,
VAR3 = 1,
VAR47 = 1,
VAR32 = 1,
VAR29 = 1,
VAR17 = 1,
VAR79 = 1,
VAR102 = 1,
VAR48 = 1,
VAR42 = 1,
VAR5 = 8,
VAR118 = 8,
VAR61 = 1,
VAR81 = 8
)
(
VAR112,
... | gpl-3.0 |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/MAC_rx/Broadcast_filter.v | 5,144 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR4
);
input VAR7 ;
input VAR8 ;
input VAR3 ;
output VAR6 ;
input VAR2 ;
input [15:0] VAR9 ;
input [15:0] VAR4 ;
reg [15:0] VAR1 ;
reg [15:0] VAR5 ;
reg VAR6 ;
always @ (posedge VAR8 or posedge VAR7)
if (VAR7)
VAR1 <=0;
else if (VAR1==VAR4)
VAR1 <=0;
else
VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.blackbox.v | 1,444 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR2
);
output VAR9 ;
input VAR10 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR2;
supply1 VAR1;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
c4puter/bridge-hdl | modules/wb_ram/wb_ram.v | 3,172 | module MODULE1 #
(
parameter VAR20 = 32, parameter VAR6 = 32, parameter VAR7 = (VAR20/8) )
(
input wire clk,
input wire [VAR6-1:0] VAR3, input wire [VAR20-1:0] VAR9, output wire [VAR20-1:0] VAR13, input wire VAR11, input wire [VAR7-1:0] VAR1, input wire VAR2, output wire VAR5, input wire VAR18 );
parameter VAR15 = VAR6... | gpl-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/NIOS_SYSTEMV3/synthesis/submodules/NIOS_SYSTEMV3_LCD.v | 2,246 | module MODULE1 (
address,
VAR3,
clk,
read,
VAR1,
write,
VAR6,
VAR5,
VAR4,
VAR8,
VAR2,
VAR7
)
;
output VAR5;
output VAR4;
output VAR8;
inout [ 7: 0] VAR2;
output [ 7: 0] VAR7;
input [ 1: 0] address;
input VAR3;
input clk;
input read;
input VAR1;
input write;
input [ 7: 0] VAR6;
wire VAR5;
wire VAR4;
wire VAR8;
wire [ 7:... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addf/gf180mcu_fd_sc_mcu7t5v0__addf_4.functional.pp.v | 1,772 | module MODULE1( VAR23, VAR24, VAR22, VAR1, VAR27, VAR13, VAR21 );
input VAR24, VAR1, VAR22;
inout VAR13, VAR21;
output VAR27, VAR23;
wire VAR11;
and VAR19( VAR11, VAR24, VAR1 );
wire VAR14;
and VAR5( VAR14, VAR24, VAR22 );
wire VAR16;
and VAR6( VAR16, VAR1, VAR22 );
or VAR17( VAR27, VAR11, VAR14, VAR16 );
wire VAR29;
a... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2ai/sky130_fd_sc_hdll__o2bb2ai_2.v | 2,427 | module MODULE1 (
VAR5 ,
VAR11,
VAR2,
VAR1 ,
VAR7 ,
VAR9,
VAR6,
VAR10 ,
VAR8
);
output VAR5 ;
input VAR11;
input VAR2;
input VAR1 ;
input VAR7 ;
input VAR9;
input VAR6;
input VAR10 ;
input VAR8 ;
VAR3 VAR4 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8... | apache-2.0 |
asicguy/gplgpu | hdl/lucy_tc/de3d_tc_load_gen.v | 7,615 | module MODULE1
(
input VAR2,
input [20:0] VAR16, input [11:0] VAR19, input [3:0] VAR1, input [8:0] VAR23, input [8:0] VAR9, input [8:0] VAR11, input [8:0] VAR8, input [8:0] VAR10, input [8:0] VAR7, input [8:0] VAR5, input [8:0] VAR22, input [2:0] VAR26, input [1:0] VAR12,
output reg [31:0] VAR13 );
reg [6:0] VAR15; reg... | gpl-3.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/ClockDiv.v | 4,592 | module MODULE1(VAR1, VAR9, VAR13, VAR3);
parameter VAR16 = 2 ; parameter VAR2 = 1 ; parameter VAR5 = 3 ;
parameter VAR6 = 0;
input VAR1; input VAR9;
output VAR13; output VAR3;
reg [ VAR16 -1 : 0 ] VAR12 ;
reg VAR13 ;
wire [VAR16-1:0] VAR10 ;
wire [VAR16-1:0] VAR8 ;
assign VAR3 = VAR12[VAR16-1] ;
assign VAR10 = VAR5 ;
a... | lgpl-3.0 |
fallen/milkymist-mmu | cores/minimac2/rtl/minimac2_psync.v | 1,079 | module MODULE1(
input VAR5,
input VAR3,
input VAR7,
output VAR1
);
reg VAR8;
always @(posedge VAR5)
if(VAR3)
VAR8 <= ~VAR8;
reg VAR4;
reg VAR2;
reg VAR6;
always @(posedge VAR7) begin
VAR4 <= VAR8;
VAR2 <= VAR4;
VAR6 <= VAR2;
end
assign VAR1 = VAR2 ^ VAR6; | lgpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_02/02 verilog/PorPruebas/ModulosBasicos/PruebasFPGA/divisorprueba/divisorprueba.v | 1,327 | module MODULE1 (
input reset,
input [7:0] VAR10,
input VAR7,
input clk,
output [3:0] VAR28,
output [6:0] VAR2
);
wire [7:0] VAR27;
wire [3:0] VAR1;
wire [3:0] VAR12;
wire [3:0] VAR13;
VAR15 VAR11 (
.reset ( reset ),
.VAR10 ( VAR10 ),
.VAR7 ( VAR7 ),
.VAR6 ( VAR6 ),
.VAR19 ( VAR19 ),
.VAR27 ( VAR27 )
);
VAR4 VAR26 (
.cl... | gpl-3.0 |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Multi Cycle CPU/Multi Cycle CPU.srcs/sources_1/new/ControlUnit.v | 2,885 | module MODULE1(
input [5:0] VAR36,
input clk,
input rst,
input VAR38,
input VAR1,
output wire [2:0] state,
output VAR24,
output [1:0] VAR22,
output VAR26,
output VAR37,
output VAR12,
output reg [2:0] VAR23,
output VAR29,
output VAR10,
output VAR48,
output VAR40,
output VAR28,
output VAR7,
output VAR45,
output [1:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn.functional.v | 2,250 | module MODULE1 (
VAR5 ,
VAR14 ,
VAR9 ,
VAR8 ,
VAR15 ,
VAR12,
VAR13
);
output VAR5 ;
input VAR14 ;
input VAR9 ;
input VAR8 ;
input VAR15 ;
input VAR12;
input VAR13;
wire VAR16 ;
wire VAR3 ;
wire VAR4;
wire VAR18 ;
wire VAR20 ;
wire VAR17 ;
not VAR19 (VAR3 , VAR12 );
VAR2 VAR7 (VAR4, VAR9, VAR8, VAR15 );
VAR10 VAR6 VAR1 ... | apache-2.0 |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/top.v | 9,571 | module MODULE2 (
VAR31,
VAR124,
VAR59,
VAR125,
VAR63,
VAR71,
VAR54,
VAR60,
VAR61,
VAR25,
VAR72,
VAR64,
VAR22,
VAR28,
VAR74,
VAR109,
VAR121,
VAR16,
VAR93,
VAR68,
VAR69,
VAR36,
VAR118,
VAR62,
VAR46,
VAR52,
VAR126,
VAR39,
VAR90,
VAR56,
VAR77,
VAR98,
VAR17,
VAR13,
VAR101,
VAR111,
VAR100,
VAR23,
VAR102,
VAR79,
VAR41,
VAR86,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.functional.pp.v | 1,998 | module MODULE1 (
VAR9 ,
VAR13 ,
VAR8 ,
VAR17 ,
VAR1 ,
VAR12,
VAR5,
VAR10 ,
VAR16
);
output VAR9 ;
input VAR13 ;
input VAR8 ;
input VAR17 ;
input VAR1 ;
input VAR12;
input VAR5;
input VAR10 ;
input VAR16 ;
wire VAR11 ;
wire VAR2 ;
wire VAR6;
nor VAR3 (VAR11 , VAR13, VAR8 );
and VAR15 (VAR2 , VAR11, VAR17, VAR1 );
VAR4 V... | apache-2.0 |
kkiningh/cs231n-project | src/rtl/SystolicDataSetupCol.v | 1,167 | module MODULE1 #(
parameter VAR4 = 8,
parameter VAR3 = 256,
parameter VAR1 = 2*VAR3-1
) (
input VAR7,
input reset,
input [VAR4-1:0] VAR5 [0:VAR3-1][0:VAR3-1],
output [VAR4-1:0] VAR6[0:VAR1-1][0:VAR3-1]
);
integer VAR2;
integer VAR8;
always @ (posedge VAR7 or posedge reset) begin
if (reset) begin
for( VAR2 = 0; VAR2 < V... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_fp_fptosi.v | 4,297 | module MODULE1( VAR9, enable, VAR1, VAR11, VAR14);
input VAR9;
input enable, VAR1;
input [31:0] VAR11;
output [31:0] VAR14;
wire VAR6;
wire [7:0] VAR8;
wire [22:0] VAR13;
wire [23:0] VAR2;
assign {VAR6, VAR8, VAR13} = VAR11;
assign VAR2 = {1'b1, VAR13};
reg VAR7;
reg [30:0] VAR10;
reg [7:0] VAR4;
always @( posedge VAR9... | mit |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.cache/ip/2018.2/ad4f3760cb81ab99/gcd_block_design_rst_ps7_0_100M_0_stub.v | 1,891 | module MODULE1(VAR8, VAR10, VAR6,
VAR4, VAR9, VAR3, VAR2, VAR1,
VAR7, VAR5)
;
input VAR8;
input VAR10;
input VAR6;
input VAR4;
input VAR9;
output VAR3;
output [0:0]VAR2;
output [0:0]VAR1;
output [0:0]VAR7;
output [0:0]VAR5;
endmodule | mit |
JeremySavonet/Eurobot-2017-Moon-Village | software/custom_leds/fpga/soc_system/synthesis/submodules/hps_sdram_p0_reset.v | 4,395 | module MODULE1(
VAR4,
VAR1,
VAR19,
VAR3,
VAR28,
VAR18,
VAR32,
VAR31,
VAR23,
VAR9,
VAR27,
VAR40,
VAR22,
VAR8,
VAR5,
VAR26,
VAR10,
VAR39,
VAR25,
VAR33
);
parameter VAR35 = "";
parameter VAR21 = 1;
input VAR4;
input VAR1;
input VAR19;
input VAR3;
input VAR28;
input VAR18;
input VAR32;
output VAR31;
output VAR23;
input [VA... | gpl-3.0 |
The7thPres/CFTP | CFTP_Sat/CFTP_Sat.srcs/sources_1/imports/Sources-On_Sat/MIPS32/RegisterFile.v | 1,726 | module MODULE1(
input VAR4,
input reset,
input [4:0] VAR11, VAR2, VAR10,
input [31:0] VAR8,
input VAR5,
output [31:0] VAR14, VAR6,
input [991:0] VAR12,
output [991:0] VAR3
);
wire [31:0] VAR15 [1:31];
reg [31:0] VAR7 [1:31];
integer VAR1;
always @(posedge VAR4) begin
for (VAR1=1; VAR1<32; VAR1=VAR1+1) begin
VAR7[VAR1] ... | lgpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | fifo.v | 2,382 | module MODULE1
parameter VAR13=8, VAR10=2 )
(
input wire clk, reset,
input wire rd, wr,
input wire [VAR13-1:0] VAR7,
output wire VAR8, VAR9,
output wire [VAR13-1:0] VAR3
);
reg [VAR13-1:0] VAR14 [2**VAR10-1:0]; reg [VAR10-1:0] VAR5, VAR12, VAR2;
reg [VAR10-1:0] VAR15, VAR4, VAR11;
reg VAR1, VAR6, VAR17, VAR16;
wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a31o/sky130_fd_sc_ms__a31o.pp.symbol.v | 1,366 | module MODULE1 (
input VAR1 ,
input VAR6 ,
input VAR9 ,
input VAR8 ,
output VAR7 ,
input VAR5 ,
input VAR4,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/IPRepo-1.0.3/V2NFC100DDR/src/NPM_Toggle_Top_DDR100.v | 42,027 | module MODULE1
(
parameter VAR235 = 4
)
(
VAR221 ,
VAR122 ,
VAR100 ,
VAR275 ,
VAR131 ,
VAR12 ,
VAR206 ,
VAR30 ,
VAR146 ,
VAR137 ,
VAR43 ,
VAR240 ,
VAR86 ,
VAR128 ,
VAR70 ,
VAR26 ,
VAR92 ,
VAR215 ,
VAR91 ,
VAR245 ,
VAR270 ,
VAR136 ,
VAR53 ,
VAR95 ,
VAR52 ,
VAR211 ,
VAR158 ,
VAR72 ,
VAR257 ,
VAR142 ,
VAR68 ,
VAR258 ,
VAR... | gpl-3.0 |
aap/pdp6 | verilog/core64k.v | 9,869 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR3,
input wire VAR35,
input wire VAR148,
input wire VAR34,
input wire VAR75,
input wire VAR104,
input wire VAR31,
input wire [21:35] VAR78,
input wire [18:21] VAR68,
input wire VAR57,
input wire [0:35] VAR38,
output wire VAR108,
output wire VAR26,
output wi... | mit |
borti4938/sd2snes | verilog/sd2snes_obc1/sd_dma.v | 3,980 | module MODULE1(
input [3:0] VAR3,
inout VAR15,
input VAR4,
input VAR2,
output VAR16,
output VAR6,
output VAR12,
output [7:0] VAR1,
input VAR20,
input [10:0] VAR13,
input [10:0] VAR18,
input VAR5,
input VAR11,
output [10:0] VAR9,
output [2:0] VAR7
);
reg [10:0] VAR14;
reg [10:0] VAR19;
reg VAR10;
always @(posedge VAR4) ... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/vfabric_multiport_lsu_streaming.v | 6,536 | module MODULE1(VAR27, VAR26, VAR80, VAR37,
VAR70, VAR68,
VAR64, VAR69, VAR36,
VAR52, VAR56, VAR11,
VAR50, VAR77, VAR79,
VAR33,
VAR75, VAR31, VAR45,
VAR41, VAR86, VAR8,
VAR13, VAR61, VAR89,
VAR47, VAR6, VAR22);
parameter VAR67 = 32;
parameter VAR85 = 16;
parameter VAR20 = 32;
input VAR27, VAR26;
input [VAR67-1:0] VAR80;... | mit |
cr88192/bgbtech_bjx1core | bjx1core32/MemTile2_0.v | 17,090 | module MODULE1(
clk,
reset,
VAR19,
VAR8,
VAR30,
VAR25,
VAR35,
VAR13,
VAR26,
VAR94,
VAR23,
VAR9,
VAR78,
VAR55,
VAR89,
VAR67,
VAR24
);
input clk; input reset;
input VAR19; input VAR8; input[2:0] VAR30;
input[63:0] VAR25;
input[63:0] VAR13;
output[63:0] VAR35;
input VAR26; input[47:0] VAR94;
output[63:0] VAR23;
output[47:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdfxtp/sky130_fd_sc_hvl__sdfxtp.functional.pp.v | 2,190 | module MODULE1 (
VAR16 ,
VAR5 ,
VAR3 ,
VAR15 ,
VAR10 ,
VAR7,
VAR2,
VAR14 ,
VAR17
);
output VAR16 ;
input VAR5 ;
input VAR3 ;
input VAR15 ;
input VAR10 ;
input VAR7;
input VAR2;
input VAR14 ;
input VAR17 ;
wire VAR18 ;
wire VAR12 ;
wire VAR11;
VAR8 VAR19 (VAR12 , VAR3, VAR15, VAR10 );
VAR4 VAR6 VAR1 (VAR18 , VAR12, VAR5... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and3/gf180mcu_fd_sc_mcu9t5v0__and3_4.behavioral.v | 1,250 | module MODULE1( VAR3, VAR4, VAR1, VAR6 );
input VAR4, VAR1, VAR3;
output VAR6;
VAR5 VAR7(.VAR3(VAR3),.VAR4(VAR4),.VAR1(VAR1),.VAR6(VAR6));
VAR5 VAR2(.VAR3(VAR3),.VAR4(VAR4),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
ptracton/vscale_soc | rtl/wb_ram/rtl/verilog/wb_ram.v | 1,645 | module MODULE1
parameter VAR28 = 256,
parameter VAR19 = VAR17(VAR28),
parameter VAR16 = "")
(input VAR26,
input VAR32,
input [VAR19-1:0] VAR24,
input [VAR6-1:0] VAR30,
input [3:0] VAR9,
input VAR13,
input [1:0] VAR18,
input [2:0] VAR14,
input VAR12,
input VAR23,
output reg VAR25,
output VAR2,
output [VAR6-1:0] VAR20);
... | mit |
DreamSourceLab/DSLogic-hdl | src/uart/uart_rx.v | 3,217 | module MODULE1
(
VAR7, reset,
VAR11, VAR6,
VAR1, VAR9
);
input VAR7; input reset; input VAR11; input VAR6; output [7:0] VAR1; output VAR9;
wire VAR5; wire VAR2;
reg [7:0] VAR1;
reg VAR9;
reg [1:0] VAR8;
reg VAR3;
reg [3:0] VAR12;
reg [3:0] VAR4;
reg [7:0] VAR10;
always @ (posedge VAR7 or posedge reset)
begin
if (reset)... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/and2/gf180mcu_fd_sc_mcu9t5v0__and2_1.behavioral.pp.v | 1,244 | module MODULE1( VAR5, VAR1, VAR3, VAR2, VAR4 );
input VAR5, VAR1;
inout VAR2, VAR4;
output VAR3;
VAR7 VAR6(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4));
VAR7 VAR8(.VAR5(VAR5),.VAR1(VAR1),.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
GSejas/Karatsuba_FPU | my_sourcefiles/addsub/Priority_Codec_32.v | 2,322 | module MODULE1(
input wire [25:0] VAR1,
output reg [4:0] VAR2
);
always @(VAR1)
begin
if(~VAR1[25]) begin VAR2 = 5'b00000; end else if(~VAR1[24]) begin VAR2 = 5'b00001; end else if(~VAR1[23]) begin VAR2 = 5'b00010; end else if(~VAR1[22]) begin VAR2 = 5'b00011; end else if(~VAR1[21]) begin VAR2 = 5'b00100; end else if(~... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/riffa/rxr_engine_classic.v | 25,353 | module MODULE1
parameter VAR46 = 128,
parameter VAR101=10)
( input VAR21,
input VAR38, input VAR142, output VAR58,
input [VAR46-1:0] VAR29,
input VAR106,
input VAR60,
input [VAR88-1:0] VAR67,
input VAR4,
input [VAR88-1:0] VAR158,
input [VAR47-1:0] VAR150,
output [VAR46-1:0] VAR152,
output VAR129,
output [(VAR46/32)-1:0... | gpl-3.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/Position_TopModule.v | 16,791 | module MODULE1(
input clk,
input rst,
input en,
output reg VAR1,
output reg [31:0] VAR101,
output reg [31:0] VAR78,
output reg [31:0] VAR81,
output reg [31:0] VAR22,
output reg [31:0] VAR85,
input VAR14,
output reg[31:0] VAR51,
output reg VAR86,
input [15:0] VAR64,
output reg VAR38,
output reg VAR43,
input VAR17,
outpu... | mit |
ShepardSiegel/ocpi | coregen/temac_v6/example_design/client/address_swap_module_8.v | 14,933 | module MODULE1 (
VAR8, VAR14, VAR29, VAR15, VAR28, VAR21, VAR23, VAR13, VAR12, VAR27, VAR18 );
input VAR8;
input VAR14;
input [7:0] VAR29;
input VAR15;
input VAR28;
input VAR21;
output [7:0] VAR23;
reg [7:0] VAR23;
output VAR13;
output VAR12;
output VAR27;
input VAR18;
reg VAR11; reg VAR20; wire [7:0] VAR26; reg [7:0] ... | lgpl-3.0 |
Valakor/EE201-Text-Editor | Altera_UP_PS2_Data_In.v | 5,687 | module MODULE1 (
clk,
reset,
VAR10,
VAR1,
VAR11,
VAR7,
VAR5,
VAR6,
VAR9 );
input clk;
input reset;
input VAR10;
input VAR1;
input VAR11;
input VAR7;
input VAR5;
output reg [7:0] VAR6;
output reg VAR9;
localparam VAR15 = 3'h0,
VAR14 = 3'h1,
VAR8 = 3'h2,
VAR3 = 3'h3,
VAR2 = 3'h4;
reg [3:0] VAR12;
reg [7:0] VAR16;
reg [2:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.symbol.v | 1,331 | module MODULE1 (
input VAR9 ,
input VAR3 ,
input VAR6 ,
input VAR5,
output VAR7
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a222oi/sky130_fd_sc_hdll__a222oi.symbol.v | 1,426 | module MODULE1 (
input VAR10,
input VAR6,
input VAR3,
input VAR9,
input VAR1,
input VAR5,
output VAR7
);
supply1 VAR2;
supply0 VAR11;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
JorisBolsens/PYNQ | Pynq-Z1/vivado/ip/arduino_io_switch_1.0/src/arduino_switch_digital_1_0_top.v | 2,228 | module MODULE1(
input VAR8, input [1:0] VAR1, output [1:0] VAR9, output [1:0] VAR16, output [1:0] VAR10, input [1:0] VAR14, input [1:0] VAR18, output [1:0] VAR4, output VAR17, input VAR5, input VAR2 );
assign VAR4 = VAR10;
VAR19 VAR20(
.VAR21(VAR8), .VAR3(VAR9[0]), .VAR13(VAR16[0]), .VAR12(VAR1[0]), .VAR11(VAR14[0]), .... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21bo/sky130_fd_sc_ms__a21bo_4.v | 2,318 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR4,
VAR7,
VAR8,
VAR10 ,
VAR5
);
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR4;
input VAR7;
input VAR8;
input VAR10 ;
input VAR5 ;
VAR9 VAR1 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODULE1 ... | apache-2.0 |
gtaylormb/fpga_nes | hw/src/cpu/apu/apu.v | 6,836 | module MODULE1
(
input wire VAR64, input wire VAR30, input wire [ 3:0] VAR11, input wire [15:0] VAR25, input wire [ 7:0] din, input wire VAR39, output wire VAR17, output wire [ 5:0] VAR48,
output wire [ 7:0] dout );
localparam [15:0] VAR43 = 16'h4000;
localparam [15:0] VAR34 = 16'h4004;
localparam [15:0] VAR62 = 16'h40... | bsd-2-clause |
kdgwill/VHDL_Verilog_Encryptions_And_Ciphers | Verilog_AES/AES/Encryption.v | 6,028 | module MODULE1
parameter VAR11 = 4,
parameter VAR19 = 8,
parameter VAR9 = 64
)(
input clk,
input rst,
input VAR16,
input[VAR19-1:0] VAR15,
input[VAR19-1:0] VAR6,
output reg VAR3,
output reg VAR12,
output reg[VAR11-1:0] VAR8,
output reg[VAR11-1:0] VAR25,
output reg[VAR19-1:0] VAR10
);
parameter VAR20 = VAR19/2; paramete... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso0n/sky130_fd_sc_hd__lpflow_inputiso0n.blackbox.v | 1,401 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR6;
supply1 VAR4;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/ewrapper_link_receiver.v | 6,931 | module MODULE1 (
VAR5, VAR4, VAR24, VAR13,
VAR9, VAR32, VAR1,
VAR22, VAR17, VAR20,
reset, VAR21, VAR6, VAR39, VAR25,
VAR19
);
input reset;
input [63:0] VAR21; input VAR6; input [7:0] VAR39; input VAR25;
input VAR19;
output VAR5; output VAR4;
output VAR24;
output VAR13;
output VAR9;
output [1:0] VAR32;
output [3:0] VAR1... | gpl-3.0 |
quartushaters/project | M1/Part 1/altfp_add_sub0_bb.v | 3,604 | module MODULE1 (
VAR3,
VAR1,
VAR2,
VAR4,
VAR5);
input VAR3;
input VAR1;
input [31:0] VAR2;
input [31:0] VAR4;
output [31:0] VAR5;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrbp/sky130_fd_sc_lp__dfrbp.pp.symbol.v | 1,430 | module MODULE1 (
input VAR1 ,
output VAR5 ,
output VAR9 ,
input VAR8,
input VAR4 ,
input VAR2 ,
input VAR3 ,
input VAR6 ,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22ai/sky130_fd_sc_ls__o22ai.functional.v | 1,519 | module MODULE1 (
VAR5 ,
VAR3,
VAR9,
VAR12,
VAR6
);
output VAR5 ;
input VAR3;
input VAR9;
input VAR12;
input VAR6;
wire VAR7 ;
wire VAR8 ;
wire VAR10;
nor VAR1 (VAR7 , VAR12, VAR6 );
nor VAR4 (VAR8 , VAR3, VAR9 );
or VAR2 (VAR10, VAR8, VAR7);
buf VAR11 (VAR5 , VAR10 );
endmodule | apache-2.0 |
amrmorsey/Digital-Design-Project | finalcounter.v | 2,011 | module MODULE1(
input clk,
input rst,
input [64:1] VAR11,
input [1:0] VAR2,
output reg [6:0] VAR8,
output reg [3:0] VAR24,
input select
);
wire VAR15;
wire VAR13;
wire [3:0] VAR23, VAR19;
wire [3:0] VAR14, VAR21;
wire [6:0] VAR6, VAR12, VAR1, VAR3;
wire [1:0] VAR7;
assign VAR23 = (VAR2 == 2'b00)? VAR11[4:1] : ((VAR2 ==... | gpl-2.0 |
DatanoiseTV/Parallax-Propeller-P8X32A-FPGA | P8X32A_Emulation/P8X32A_DE0_Nano/hub_mem.v | 2,866 | module MODULE1
(
input VAR12,
input VAR4,
input VAR1,
input [3:0] VAR18,
input [13:0] VAR2,
input [31:0] VAR5,
output [31:0] VAR8
);
reg [7:0] VAR3 [8191:0];
reg [7:0] VAR16 [8191:0];
reg [7:0] VAR17 [8191:0];
reg [7:0] VAR14 [8191:0];
reg [7:0] VAR11;
reg [7:0] VAR13;
reg [7:0] VAR6;
reg [7:0] VAR10;
always @(posedge ... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_r_axi3_conv.v | 8,787 | module MODULE1 #
(
parameter VAR38 = "none",
parameter integer VAR20 = 1,
parameter integer VAR14 = 32,
parameter integer VAR9 = 32,
parameter integer VAR11 = 0,
parameter integer VAR6 = 1,
parameter integer VAR41 = 1,
parameter integer VAR15 = 1
)
(
input wire VAR27,
input wire VAR12,
input wire VAR4,
input wire VAR28... | gpl-3.0 |
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