repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrbp/sky130_fd_sc_ms__dfrbp.functional.v | 1,759 | module MODULE1 (
VAR13 ,
VAR10 ,
VAR8 ,
VAR4 ,
VAR9
);
output VAR13 ;
output VAR10 ;
input VAR8 ;
input VAR4 ;
input VAR9;
wire VAR1;
wire VAR3;
not VAR5 (VAR3 , VAR9 );
VAR7 VAR12 VAR2 (VAR1 , VAR4, VAR8, VAR3 );
buf VAR11 (VAR13 , VAR1 );
not VAR6 (VAR10 , VAR1 );
endmodule | apache-2.0 |
finnball/igloo | infra/hdl/fifo.v | 5,494 | module MODULE2(
input VAR15,
input VAR48,
input VAR30,
input [VAR36 - 1 : 0] VAR35,
input VAR29,
input [15 :0] VAR4,
output [VAR36 - 1 : 0] VAR24,
output VAR27,
output VAR16
);
parameter VAR36 = 1;
parameter VAR14 = 0;
wire [15:0] VAR35, VAR24;
genvar VAR40;
generate
if (VAR36 <= 16 & VAR36 > 8)
begin
assign VAR35 = { ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3.symbol.v | 1,308 | module MODULE1 (
input VAR2,
input VAR5,
input VAR7,
output VAR1
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/fetch/fetch_cur_chroma.v | 10,546 | module MODULE1 (
clk ,
VAR18 ,
VAR37 ,
VAR46 ,
VAR30 ,
VAR54 ,
VAR8 ,
VAR47 ,
VAR31 ,
VAR28 ,
VAR1 ,
VAR20 ,
VAR10 ,
VAR7 ,
VAR43 ,
VAR56 ,
VAR41 ,
VAR59 ,
VAR52 ,
VAR62 ,
VAR34
);
input [1-1:0] clk ; input [1-1:0] VAR18 ; input VAR37 ;
input [4-1:0] VAR46 ; input [4-1:0] VAR30 ; input [5-1:0] VAR54 ; input [1-1:0] VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22o/sky130_fd_sc_hdll__a22o.pp.symbol.v | 1,376 | module MODULE1 (
input VAR2 ,
input VAR1 ,
input VAR5 ,
input VAR8 ,
output VAR3 ,
input VAR6 ,
input VAR4,
input VAR7,
input VAR9
);
endmodule | apache-2.0 |
gigglesninja/digital-system-design | Lab5/lab5dpath.v | 2,553 | module MODULE1(reset, clk, VAR15, VAR13, din, dout );
input reset, clk, VAR15;
input [9:0] din;
output [9:0] dout;
output VAR13;
wire [11:0] VAR27, VAR26, VAR8, VAR24, VAR23, VAR25;
wire [23:0] VAR19;
reg VAR5, VAR22, VAR1, VAR3, VAR13;
reg [1:0] VAR12, VAR2, VAR17, VAR7;
reg [11:0] VAR9, VAR4, VAR21, VAR18;
assign VAR... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_2.behavioral.pp.v | 1,784 | module MODULE1( VAR5, VAR11, VAR8, VAR12, VAR1 );
input VAR11, VAR5;
inout VAR12, VAR1;
output VAR8;
reg VAR7;
VAR2 VAR13(.VAR5(VAR5),.VAR11(VAR11),.VAR8(VAR8),.VAR12(VAR12),.VAR1(VAR1),.VAR7(VAR7));
VAR2 VAR6(.VAR5(VAR5),.VAR11(VAR11),.VAR8(VAR8),.VAR12(VAR12),.VAR1(VAR1),.VAR7(VAR7));
not VAR4(VAR9,VAR11);
buf VAR10(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.behavioral.pp.v | 2,270 | module MODULE1 (
VAR2 ,
VAR19 ,
VAR21 ,
VAR18 ,
VAR13,
VAR7,
VAR15 ,
VAR9
);
output VAR2 ;
output VAR19 ;
input VAR21 ;
input VAR18 ;
input VAR13;
input VAR7;
input VAR15 ;
input VAR9 ;
wire VAR4 ;
reg VAR8 ;
wire VAR12 ;
wire VAR1;
wire VAR14 ;
wire VAR20;
VAR17 VAR5 (VAR4 , VAR12, VAR1, VAR8, VAR13, VAR7);
buf VAR16 ... | apache-2.0 |
aj-michael/Digital-Systems | Pong/Phase4/debouncer.v | 1,204 | module MODULE1(VAR14, VAR1, VAR11, VAR8) ;
input VAR14, VAR11, VAR8;
output reg VAR1;
parameter VAR7=0, VAR2=1, VAR9=2, VAR3=3;
reg [1:0] VAR4, VAR13;
wire VAR12;
reg VAR10;
always @ (posedge VAR8)
if(VAR11==1) VAR4 <= 0;
else VAR4<=VAR13;
always@(VAR4)
case (VAR4)
0: begin VAR1<=0; VAR10<=1; end 1: begin VAR1<=0; VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd2/sky130_fd_sc_hs__tapvgnd2.symbol.v | 1,240 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | fpga/src/elink/hdl/ememory.v | 4,591 | module MODULE1(
VAR14, VAR17, VAR25, VAR23, VAR7,
VAR5, VAR22, VAR8,
clk, reset, VAR13, VAR1, VAR21, VAR9,
VAR15, VAR4, VAR20, VAR16
);
parameter VAR6 = 32;
parameter VAR2 = 32;
parameter VAR3 = 10;
input clk;
input reset;
input VAR13;
input VAR1;
input [1:0] VAR21;
input [3:0] VAR9;
input [VAR2-1:0] VAR15;
input [VAR6... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_nonsynth_mem_1r1w_sync_mask_write_byte_dma.v | 3,087 | module MODULE1
, parameter VAR24(VAR6)
, parameter VAR24(VAR12)
, parameter VAR21=(VAR30>>3)
, parameter VAR16=VAR21
, parameter VAR27=VAR25(VAR6)
, parameter VAR18=VAR31(VAR21)
, parameter VAR11=0
)
(
input VAR28
, input VAR26
, input VAR14
, input [VAR27-1:0] VAR32
, input VAR1
, input [VAR27-1:0] VAR29
, input [VAR3... | bsd-3-clause |
alexforencich/verilog-ethernet | example/DE5-Net/fpga/rtl/fpga.v | 11,886 | module MODULE1 (
input wire VAR118,
input wire [3:0] VAR120,
input wire [3:0] VAR123,
output wire [6:0] VAR171,
output wire VAR183,
output wire [6:0] VAR159,
output wire VAR189,
output wire [3:0] VAR82,
output wire [3:0] VAR201,
output wire VAR1,
output wire VAR64,
output wire VAR48,
input wire VAR96,
input wire VAR78,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probe_p/sky130_fd_sc_hd__probe_p.functional.v | 1,264 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
wire VAR1;
buf VAR2 (VAR1, VAR4 );
buf VAR3 (VAR5 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.blackbox.v | 1,344 | module MODULE1 (
VAR7 ,
VAR4,
VAR2,
VAR8 ,
VAR3
);
output VAR7 ;
input VAR4;
input VAR2;
input VAR8 ;
input VAR3 ;
supply1 VAR6;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361.v | 15,462 | module MODULE1 (
VAR162,
VAR21,
VAR12,
VAR55,
VAR80,
VAR27,
VAR124,
VAR1,
VAR56,
VAR152,
VAR126,
VAR171,
VAR160,
VAR208,
VAR6,
VAR49,
clk,
rst,
VAR132,
VAR3,
VAR36,
VAR169,
VAR83,
VAR125,
VAR187,
VAR202,
VAR154,
VAR174,
VAR40,
VAR19,
VAR197,
VAR145,
VAR15,
VAR59,
VAR158,
VAR66,
VAR118,
VAR52,
VAR8,
VAR85,
VAR189,
VAR17... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s6s/sky130_fd_sc_hs__dlymetal6s6s.behavioral.v | 1,760 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR5,
VAR9
);
output VAR6 ;
input VAR1 ;
input VAR5;
input VAR9;
wire VAR10 ;
wire VAR4;
buf VAR3 (VAR10 , VAR1 );
VAR8 VAR7 (VAR4, VAR10, VAR5, VAR9);
buf VAR2 (VAR6 , VAR4 );
endmodule | apache-2.0 |
ashwith/hdlroot | lib/modules/uart/design/uart_tx.v | 1,881 | module MODULE1(
input VAR12,
input VAR6,
input VAR1,
input [VAR13 - 1 : 0] VAR3,
input VAR14,
output VAR7,
output VAR11
);
parameter VAR13 = 8;
parameter VAR10 = 4'h0;
parameter VAR15 = 4'h1;
parameter VAR17 = 4'h2;
parameter VAR9 = 4'h3;
reg VAR4;
reg VAR5;
reg [1:0] VAR2;
reg [1:0] VAR16;
reg [2:0] VAR8;
always @ (po... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/probe_p/sky130_fd_sc_hvl__probe_p.pp.blackbox.v | 1,268 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR5,
VAR2,
VAR3 ,
VAR4
);
output VAR1 ;
input VAR6 ;
input VAR5;
input VAR2;
input VAR3 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o_lp.v | 2,445 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR6 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR4,
VAR1,
VAR12 ,
VAR2
);
output VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR12 ;
input VAR2 ;
VAR11 VAR9 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VA... | apache-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/gcd/gcd.srcs/sources_1/bd/gcd_block_design/ip/gcd_block_design_gcd_0_1/synth/gcd_block_design_gcd_0_1.v | 9,015 | module MODULE1 (
VAR19,
VAR17,
VAR2,
VAR9,
VAR12,
VAR5,
VAR8,
VAR13,
VAR18,
VAR3,
VAR7,
VAR11,
VAR23,
VAR10,
VAR14,
VAR21,
VAR20,
VAR15,
VAR16,
interrupt
);
input wire [5 : 0] VAR19;
input wire VAR17;
output wire VAR2;
input wire [31 : 0] VAR9;
input wire [3 : 0] VAR12;
input wire VAR5;
output wire VAR8;
output wire [1... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/pipistrello-s6-v1/rtl/verilog/xilinx_lpddr/mcb_controller/mcb_soft_calibration.v | 68,316 | module MODULE1 # (
parameter VAR187 = 10'd512, parameter VAR280 = "VAR264", parameter VAR206 = "VAR201", parameter VAR135 = 1'b0, parameter VAR194 = 1'b0, parameter VAR160 = 1'b1, parameter VAR115 = "VAR241"
)
(
input wire VAR131, input wire VAR107, output reg VAR102,
input wire VAR218, input wire VAR17,
input wire VAR... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/invz/gf180mcu_fd_sc_mcu7t5v0__invz_12.behavioral.pp.v | 1,251 | module MODULE1( VAR1, VAR5, VAR2, VAR7, VAR3 );
input VAR1, VAR5;
inout VAR7, VAR3;
output VAR2;
VAR8 VAR4(.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3));
VAR8 VAR6(.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
myhdl/myhdl | example/cookbook/bitonic/ori.v | 19,991 | module MODULE1 (
VAR6,
VAR98,
VAR69,
VAR46,
VAR57,
VAR3,
VAR75,
VAR22,
VAR17,
VAR29,
VAR13,
VAR83,
VAR79,
VAR65,
VAR47,
VAR55
);
input [3:0] VAR6;
input [3:0] VAR98;
input [3:0] VAR69;
input [3:0] VAR46;
input [3:0] VAR57;
input [3:0] VAR3;
input [3:0] VAR75;
input [3:0] VAR22;
output [3:0] VAR17;
wire [3:0] VAR17;
out... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32o/sky130_fd_sc_hs__a32o_1.v | 2,342 | module MODULE2 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR10 ,
VAR4 ,
VAR1 ,
VAR7,
VAR3
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR4 ;
input VAR1 ;
input VAR7;
input VAR3;
VAR6 VAR9 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311a/sky130_fd_sc_lp__o311a.behavioral.v | 1,555 | module MODULE1 (
VAR1 ,
VAR10,
VAR11,
VAR6,
VAR2,
VAR7
);
output VAR1 ;
input VAR10;
input VAR11;
input VAR6;
input VAR2;
input VAR7;
supply1 VAR8;
supply0 VAR15;
supply1 VAR5 ;
supply0 VAR12 ;
wire VAR3 ;
wire VAR9;
or VAR4 (VAR3 , VAR11, VAR10, VAR6 );
and VAR13 (VAR9, VAR3, VAR2, VAR7);
buf VAR14 (VAR1 , VAR9 );
end... | apache-2.0 |
drichmond/riffa | fpga/xilinx/vc707/VC707_Gen1x8If64/hdl/VC707_Gen1x8If64.v | 20,969 | module MODULE1
parameter VAR171 = 8,
parameter VAR45 = 64,
parameter VAR112 = 256,
parameter VAR175 = 5
)
(output [(VAR171 - 1) : 0] VAR11,
output [(VAR171 - 1) : 0] VAR124,
input [(VAR171 - 1) : 0] VAR150,
input [(VAR171 - 1) : 0] VAR152,
output [3:0] VAR80,
input VAR58,
input VAR88,
input VAR15
);
wire VAR148;
wire V... | bsd-3-clause |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_INVBUF_SRAM_SS_210930.v | 14,992 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
asicguy/gplgpu | hdl/hbi/hbi_addr_decoder.v | 27,591 | module MODULE1
(
input [31:0] VAR2, input [31:3] VAR18,
input VAR30, input [3:0] VAR67, input [31:8] VAR50, input [31:8] VAR64, input [31:9] VAR15, input [31:8] VAR31, input [31:12] VAR14, input [3:0] VAR41, input [31:12] VAR85, input [3:0] VAR7, input [31:12] VAR13,
input VAR70, input VAR82, input VAR87, input VAR68, ... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_mask_write_var.v | 1,469 | module MODULE1 #
(parameter VAR11(VAR5)
,parameter VAR11(VAR25)
,parameter VAR11(VAR6)
,parameter VAR12 = VAR5 / VAR25
,parameter VAR26=VAR8(VAR6)
,parameter VAR17=0
,parameter VAR2=0)
(input VAR9
,input VAR27
,input VAR7
,input [VAR5-1:0] VAR18
,input [VAR26-1:0] VAR22
,input [VAR5-1:0] VAR3
,input VAR14
,input [VAR26... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkinvkapwr/sky130_fd_sc_hd__lpflow_clkinvkapwr_1.v | 2,261 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR1,
VAR3 ,
VAR6 ,
VAR9 ,
VAR7
);
output VAR4 ;
input VAR8 ;
input VAR1;
input VAR3 ;
input VAR6 ;
input VAR9 ;
input VAR7 ;
VAR2 VAR5 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR4,
VAR8
);
output VAR4;
inpu... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai.blackbox.v | 1,381 | module MODULE1 (
VAR5 ,
VAR2,
VAR9,
VAR10,
VAR7,
VAR8
);
output VAR5 ;
input VAR2;
input VAR9;
input VAR10;
input VAR7;
input VAR8;
supply1 VAR3;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.pp.blackbox.v | 1,359 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1 ,
VAR2 ,
VAR7,
VAR5,
VAR4 ,
VAR8
);
output VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR7;
input VAR5;
input VAR4 ;
input VAR8 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/ram_128x8_dp_be/ram_128x8_dp_be.v | 10,521 | module MODULE1 (
VAR45,
VAR18,
VAR35,
VAR13,
VAR11,
VAR59,
VAR46,
VAR2,
VAR37,
VAR7,
VAR33);
input [2:0] VAR45;
input [2:0] VAR18;
input [15:0] VAR35;
input VAR13;
input VAR11;
input [127:0] VAR59;
input [127:0] VAR46;
input VAR2;
input VAR37;
output [127:0] VAR7;
output [127:0] VAR33;
wire [127:0] VAR19;
wire [127:0] ... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Control_Current.v | 5,376 | module MODULE1
(
VAR31,
reset,
VAR41,
VAR2,
VAR49,
VAR27,
VAR15,
VAR40
);
input VAR31;
input reset;
input VAR41;
input VAR2;
input signed [17:0] VAR49; input signed [17:0] VAR27; input signed [17:0] VAR15; output signed [17:0] VAR40;
wire signed [35:0] VAR25; wire signed [35:0] VAR22; wire signed [17:0] VAR35; wire sig... | gpl-3.0 |
EliasLuiz/TCC | Leon3/lib/opencores/ge_1000baseX/encoder_8b10b.v | 10,127 | module MODULE1 (
input reset,
input VAR39,
input VAR27,
input [7:0] VAR26,
output [9:0] VAR69,
output reg VAR43
);
wire VAR38, VAR35, VAR52, VAR57, VAR7, VAR34, VAR29;
wire VAR31, VAR28, VAR60, VAR33;
wire VAR40, VAR49, VAR44, VAR16;
wire VAR47, VAR53;
reg VAR62, VAR48;
wire VAR54, VAR6, VAR13, VAR17, VAR46, VAR67;
wir... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfbbn/sky130_fd_sc_lp__dfbbn.functional.v | 2,161 | module MODULE1 (
VAR15 ,
VAR6 ,
VAR7 ,
VAR17 ,
VAR1 ,
VAR13
);
output VAR15 ;
output VAR6 ;
input VAR7 ;
input VAR17 ;
input VAR1 ;
input VAR13;
wire VAR18 ;
wire VAR10 ;
wire VAR19 ;
wire VAR5 ;
wire VAR20 ;
wire VAR14;
wire VAR16 ;
not VAR21 (VAR18 , VAR13 );
not VAR3 (VAR10 , VAR1 );
not VAR2 (VAR19 , VAR17 );
VAR9 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/tiel/gf180mcu_fd_sc_mcu9t5v0__tiel.behavioral.pp.v | 1,090 | module MODULE1( VAR3, VAR6, VAR5 );
inout VAR6, VAR5;
output VAR3;
VAR1 VAR2(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5));
VAR1 VAR4(.VAR3(VAR3),.VAR6(VAR6),.VAR5(VAR5)); | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/riffa.v | 31,419 | module MODULE1
parameter VAR124 = 128,
parameter VAR319 = 12,
parameter VAR200 = 512, parameter VAR18 = 5, parameter VAR93 = "VAR265",
parameter VAR45 = "VAR172",
parameter VAR178 = 10
)
(
input VAR301,
input VAR120,
output VAR94,
input [VAR124-1:0] VAR75,
input VAR1,
input [(VAR124/32)-1:0] VAR159,
input VAR40,
input ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fah/sky130_fd_sc_lp__fah.pp.blackbox.v | 1,308 | module MODULE1 (
VAR2,
VAR7 ,
VAR8 ,
VAR1 ,
VAR9 ,
VAR3,
VAR6,
VAR4 ,
VAR5
);
output VAR2;
output VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR9 ;
input VAR3;
input VAR6;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
freecores/orsoc_graphics_accelerator | bench/verilog/gfx/blender_bench.v | 2,395 | module MODULE1();
reg VAR11;
reg VAR14;
reg VAR19;
reg [31:2] VAR4;
reg [15:0] VAR26;
reg [15:0] VAR21;
reg [1:0] VAR5;
reg [15:0] VAR23;
reg [15:0] VAR20;
reg signed [15:0] VAR16;
reg [7:0] VAR1;
reg [7:0] VAR12;
reg [31:0] VAR25;
reg VAR10;
reg VAR18;
reg VAR22;
wire [31:2] VAR6;
reg [31:0] VAR7;
wire [3:0] VAR17;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo.functional.pp.v | 2,043 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR15 ,
VAR7,
VAR11,
VAR3,
VAR6 ,
VAR16
);
output VAR1 ;
input VAR10 ;
input VAR15 ;
input VAR7;
input VAR11;
input VAR3;
input VAR6 ;
input VAR16 ;
wire VAR4 ;
wire VAR8 ;
wire VAR5;
nand VAR14 (VAR4 , VAR15, VAR10 );
nand VAR13 (VAR8 , VAR7, VAR4 );
VAR12 VAR2 (VAR5, VAR8, VAR11, VAR3)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill.behavioral.pp.v | 1,147 | module MODULE1 (
VAR1,
VAR2,
VAR4 ,
VAR3
);
input VAR1;
input VAR2;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
prernaa/CPUVerilog | HazardDetectionUnit.v | 1,482 | module MODULE1(
VAR2, VAR9, VAR6, VAR8, VAR4, VAR3, VAR12,
VAR7, VAR10
);
input [3:0] VAR2;
input [3:0] VAR9;
input VAR6;
input VAR8;
input VAR4;
input VAR3;
input VAR12;
output VAR7;
output VAR10;
reg VAR11;
reg VAR1;
reg [1:0] VAR5;
always @ (*)
begin
VAR5 = (VAR3===1'b1 && VAR4!==1'b1 && (
(VAR6===1'b1 && VAR8!==1'b... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn.symbol.v | 1,600 | module MODULE1 (
input VAR10 ,
output VAR3 ,
input VAR11,
input VAR1 ,
input VAR7 ,
input VAR4 ,
input VAR5
);
supply1 VAR2;
supply1 VAR8 ;
supply0 VAR9 ;
supply1 VAR12 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai_2.v | 2,297 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR2 ,
VAR9 ,
VAR10,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR9 ;
input VAR10;
input VAR5;
VAR4 VAR7 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODUL... | apache-2.0 |
rfotino/consolite-hardware | proj/ipcore_dir/s6_lpddr_ram/user_design/rtl/mcb_controller/iodrp_controller.v | 11,430 | module MODULE1(
input wire [7:0] VAR38,
input wire [7:0] VAR11,
output reg [7:0] VAR23,
input wire VAR43,
input wire VAR25,
output wire VAR30,
input wire VAR51,
input wire VAR8,
input wire VAR9,
output reg VAR17,
output wire VAR49, output reg VAR24,
output reg VAR28,
input wire VAR16 );
reg [7:0] VAR15; reg [7:0] VAR6;... | mit |
UviDTE-FPSoC/CycloneVSoC-time-measurements | fpga-hardware/DE1-SoC/FPGA_DMA/ip/altsource_probe/hps_reset.v | 4,072 | module MODULE1 (
VAR11,
VAR2,
VAR4);
input VAR11;
input VAR2;
output [2:0] VAR4;
wire [2:0] VAR26;
wire [2:0] VAR4 = VAR26[2:0];
VAR31 VAR20 (
.VAR11 (VAR11),
.VAR2 (VAR2),
.VAR4 (VAR26)
,
.VAR6 (),
.VAR16 (),
.VAR1 (),
.VAR9 (),
.VAR22 (),
.VAR8 (),
.VAR13 (),
.VAR19 (),
.VAR30 (),
.VAR5 (),
.VAR18 (),
.VAR25 (),
.VAR... | gpl-3.0 |
ptracton/wb_soc_template | rtl/lm32_top/rtl/verilog/lm32_addsub.v | 3,672 | module MODULE1 (
VAR8,
VAR18,
VAR19,
VAR13,
VAR14,
VAR10
);
input [31:0] VAR8;
input [31:0] VAR18;
input VAR19;
input VAR13;
output [31:0] VAR14;
wire [31:0] VAR14;
output VAR10;
wire VAR10;
generate
if (VAR5 == "VAR15" || VAR5 == "VAR4") begin
wire [32:0] VAR17 = VAR8 + VAR18 + VAR19;
wire [32:0] VAR7 = VAR8 - VAR18 -... | mit |
felixmo/Pong | pong.v | 16,500 | module MODULE2(
VAR2,
VAR54,
VAR74,
VAR50,
VAR45,
VAR44,
VAR85,
VAR14,
VAR64,
VAR12,
VAR92,
VAR30,
VAR16,
VAR48,
VAR84,
VAR72,
VAR4, VAR90, VAR63, VAR66, VAR20, VAR96, VAR28, VAR7
);
input VAR2, VAR54;
input VAR45, VAR44;
input [3:0] VAR74;
input [17:0] VAR50;
output [9:0] VAR85, VAR14, VAR64;
output VAR12, VAR92, VAR3... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_immu_tlb.v | 9,105 | module MODULE1(
clk, rst,
VAR37, VAR11, VAR36, VAR42, VAR28, VAR51, VAR16,
VAR25, VAR29, VAR49,
VAR22, VAR6, VAR12, VAR55, VAR39
);
parameter VAR45 = VAR19;
parameter VAR13 = VAR19;
input clk;
input rst;
input VAR37;
input [VAR13-1:0] VAR11;
output VAR36;
output [31:VAR34] VAR42;
output VAR28;
output VAR51;
output VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxbp/sky130_fd_sc_hs__sedfxbp.symbol.v | 1,481 | module MODULE1 (
input VAR2 ,
output VAR7 ,
output VAR8,
input VAR6 ,
input VAR4,
input VAR3,
input VAR9
);
supply1 VAR5;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3_2.v | 2,175 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR9 ,
VAR3 ,
VAR2,
VAR5,
VAR6 ,
VAR8
);
output VAR4 ;
input VAR7 ;
input VAR9 ;
input VAR3 ;
input VAR2;
input VAR5;
input VAR6 ;
input VAR8 ;
VAR10 VAR1 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE1 (... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/channel_64.v | 9,863 | module MODULE1 #(
parameter VAR90 = 9'd64,
parameter VAR11 = 2, parameter VAR5 = 1024,
parameter VAR16 = 512,
parameter VAR47 = 1024,
parameter VAR6 = VAR24((VAR90/32)+1)
)
(
input VAR86,
input VAR67,
input [2:0] VAR102, input [2:0] VAR28,
input [31:0] VAR66, input [VAR90-1:0] VAR32,
output VAR48, input VAR8, input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufkapwr/sky130_fd_sc_lp__bufkapwr.pp.blackbox.v | 1,313 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7 ,
VAR6 ,
VAR3,
VAR5 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR3;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
fredmorcos/attic | snippets/verilog/fibfast_old.v | 1,960 | module MODULE2 (clk, VAR16, VAR10, VAR4);
input [31:0] VAR10;
input clk;
input VAR16;
output [31:0] VAR4;
wire clk;
wire VAR16;
wire [31:0] VAR10;
reg [31:0] VAR4;
always @ (posedge clk)
if (VAR16) VAR4 <= VAR10;
endmodule
module MODULE1 (clk, VAR2, VAR5, VAR15, VAR6);
input [31:0] VAR2;
input clk;
input VAR5;
output [... | isc |
lneuhaus/pyrpl | pyrpl/fpga/rtl/axi_slave.v | 9,261 | module MODULE1 #(
parameter VAR25 = 64 , parameter VAR49 = 32 , parameter VAR32 = 8 , parameter VAR17 = VAR25 >> 3 )(
input VAR15 , input VAR44 , input [ VAR32-1: 0] VAR31 , input [ VAR49-1: 0] VAR45 , input [ 4-1: 0] VAR52 , input [ 3-1: 0] VAR14 , input [ 2-1: 0] VAR20 , input [ 2-1: 0] VAR26 , input [ 4-1: 0] VAR42 ... | mit |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_spram_2048x32_bw.v | 15,318 | module MODULE1(
VAR65, VAR28, VAR86,
clk, rst, VAR4, VAR68, VAR25, addr, VAR42, VAR47
);
input VAR65;
input [VAR81 - 1:0] VAR86; output VAR28;
input clk; input rst; input VAR4; input [3:0] VAR68; input VAR25; input [10:0] addr; input [31:0] VAR42; output [31:0] VAR47;
assign VAR28 = VAR65;
VAR79 VAR18(
VAR13 VAR18(
VAR... | mit |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_bram_7vx_req.v | 5,377 | module MODULE1 #(
parameter VAR27 = "VAR21", parameter VAR18 = "VAR17", parameter VAR3 = "500 VAR4", parameter VAR23 = "16 VAR24"
) (
input VAR12, input VAR30,
input [8:0] VAR25, input [8:0] VAR14, input [127:0] VAR7, input [15:0] VAR5, input VAR13, input VAR8, input VAR6, input VAR11,
input [8:0] VAR29, input [8:0] VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill.symbol.v | 1,186 | module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp.functional.pp.v | 2,040 | module MODULE1 (
VAR4,
VAR13 ,
VAR5,
VAR2 ,
VAR16,
VAR18,
VAR15 ,
VAR14
);
output VAR4;
input VAR13 ;
input VAR5;
input VAR2 ;
input VAR16;
input VAR18;
input VAR15 ;
input VAR14 ;
wire VAR6 ;
wire VAR10 ;
wire VAR11 ;
wire VAR17;
not VAR7 (VAR10 , VAR6 );
not VAR9 (VAR11 , VAR2 );
nor VAR8 (VAR17, VAR5, VAR13 );
VAR3 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn.behavioral.pp.v | 1,918 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR3,
VAR7 ,
VAR2 ,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR12 ;
input VAR3;
input VAR7 ;
input VAR2 ;
input VAR6 ;
input VAR4 ;
wire VAR1 ;
wire VAR14 ;
wire VAR10;
wire VAR11 ;
reg VAR16 ;
VAR15 VAR13 (VAR14 , VAR11, VAR1, VAR16, VAR7, VAR2);
not VAR5 (VAR1 , VAR10 );
buf VAR9 (VAR8 , VA... | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/bench/xilinx/DSP48A1.v | 7,518 | module MODULE1
parameter VAR17 = 1'b1,
parameter VAR23 = 1'b1,
parameter VAR35 = 1'b1,
parameter VAR68 = 1'b1,
parameter VAR46 = 1'b1,
parameter VAR70 = 1'b1,
parameter VAR11 = 1'b1,
parameter VAR4 = 1'b1,
parameter VAR76 = 1'b1,
parameter VAR50 = 1'b0, parameter VAR51 = 1'b1,
parameter VAR9 = "VAR47", parameter VAR80 ... | lgpl-3.0 |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/dewater_mode.v | 4,796 | module MODULE1
(
input VAR12, input VAR6, input VAR16, input [31:0]clk,
input [2:0]VAR14,
output reg VAR15,
output reg VAR3,output reg VAR17,
output [2:0]VAR1, output reg [31:0]VAR9
);
reg [1:0]state, VAR18;
reg VAR10, VAR11; wire [31:0]VAR20; wire [2:0]VAR8; wire VAR4, VAR7, VAR5; parameter VAR2 = 0, VAR13 = 1, VAR19 ... | mit |
seyedmaysamlavasani/GorillaPP | chisel/Gorilla++/verilogOrig/tt.v | 8,299 | module MODULE1(input clk, input reset,
output VAR123,
input VAR71,
input [31:0] VAR5,
input [4:0] VAR118,
input VAR28,
output VAR43,
output[31:0] VAR60,
output[4:0] VAR110,
input VAR86,
input VAR73,
input [15:0] VAR56,
input [7:0] VAR38,
input [15:0] VAR67,
input [3:0] VAR15,
output VAR41,
output VAR34,
output[15:0] VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32a/sky130_fd_sc_hs__o32a_4.v | 2,301 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR10 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR9,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR10 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR9;
input VAR8;
VAR2 VAR5 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8)
);
endmodule
module MODUL... | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10-old/mmio_if/synthesis/submodules/altera_mem_if_hhp_qseq_synth_top.v | 1,158 | module MODULE1
VAR9 = 32,
VAR8 = 32,
VAR5 = 32,
VAR1 = 16, VAR6 = 32,
VAR2 = 8,
VAR7 = 1,
VAR3 = 8,
VAR4 = 1,
VAR10 = 1
) (
);
endmodule | gpl-3.0 |
iBenza/async_benchmark_circuit | aclass/aclass.v | 5,611 | module MODULE17 (VAR37);
output VAR37;
supply1 VAR48;
assign VAR37= VAR48;
endmodule
module MODULE9 (VAR37);
output VAR37;
supply0 VAR19;
assign VAR37 = VAR19;
endmodule
module MODULE33(VAR37,VAR14,VAR13);
input VAR14,VAR13;
output VAR37;
and #(VAR35, VAR35) (VAR37,VAR14,VAR13);
endmodule
module MODULE22(VAR37,VAR14,VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.behavioral.v | 7,158 | module MODULE1( VAR5, VAR7, VAR1, VAR8, VAR2, VAR10, VAR6 );
input VAR6, VAR10, VAR1, VAR2, VAR7, VAR5;
output VAR8;
VAR9 VAR3(.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR2(VAR2),.VAR10(VAR10),.VAR6(VAR6));
VAR9 VAR4(.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8),.VAR2(VAR2),.VAR10(VAR10),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.pp.symbol.v | 1,294 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR5 ,
input VAR2,
input VAR6,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/maj3/sky130_fd_sc_hs__maj3.behavioral.pp.v | 2,136 | module MODULE1 (
VAR8,
VAR4,
VAR6 ,
VAR19 ,
VAR16 ,
VAR17
);
input VAR8;
input VAR4;
output VAR6 ;
input VAR19 ;
input VAR16 ;
input VAR17 ;
wire VAR15, VAR1 ;
wire VAR15, VAR5 ;
wire VAR13 ;
wire VAR2 ;
wire VAR14;
or VAR9 (VAR13 , VAR16, VAR19 );
and VAR7 (VAR1 , VAR13, VAR17 );
and VAR18 (VAR5 , VAR19, VAR16 );
or V... | apache-2.0 |
golfit/QcmPhaseDelayBoard | counter_n.v | 7,741 | module MODULE1 (clk,VAR10,VAR2);
parameter VAR7=14; VAR11 VAR5 7
input clk,VAR10;
output reg [VAR7-1:0] VAR2;
reg [13:0] VAR1; reg [13:0] VAR8; reg [6:0] VAR4; reg VAR12; reg reset;
parameter VAR9=40000;
parameter VAR6=50;
parameter VAR3=2'b10; | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/offset_to_mask.v | 3,740 | module MODULE1
parameter VAR5 = 4)
(
input VAR7,
input [VAR4(VAR5)-1:0] VAR6,
output [VAR5-1:0] VAR3
);
reg [7:0] VAR8,VAR1;
wire [3:0] VAR2;
assign VAR2 = {VAR7,{{(3-VAR4(VAR5)){1'b0}},VAR6}};
assign VAR3 = (VAR9)? VAR1[7 -: VAR5]: VAR8[VAR5-1:0];
always @(*) begin
VAR8 = 0;
VAR1 = 0;
casex(VAR2)
default: begin
VAR8 =... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab0-3/double_register/register.v | 1,892 | module MODULE1(
VAR14,
VAR6,
VAR15,
VAR7,
VAR5,
VAR2,
VAR1,
VAR4,
clk,
reset,
VAR11,
VAR3
);
input wire [4:0] VAR14; input wire [4:0] VAR6; input wire [31:0] VAR15;input wire VAR7; input wire [4:0] VAR5; input wire [4:0] VAR2; input wire [31:0] VAR1;input wire VAR4; input wire clk; input wire reset;
output wire [31:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv.functional.v | 1,259 | module MODULE1 (
VAR2,
VAR4
);
output VAR2;
input VAR4;
wire VAR5;
not VAR3 (VAR5, VAR4 );
buf VAR1 (VAR2 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o_4.v | 2,444 | module MODULE2 (
VAR8 ,
VAR9 ,
VAR2 ,
VAR4 ,
VAR6 ,
VAR12 ,
VAR11,
VAR10,
VAR7 ,
VAR3
);
output VAR8 ;
input VAR9 ;
input VAR2 ;
input VAR4 ;
input VAR6 ;
input VAR12 ;
input VAR11;
input VAR10;
input VAR7 ;
input VAR3 ;
VAR1 VAR5 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR11(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai_4.v | 2,461 | module MODULE2 (
VAR8 ,
VAR3 ,
VAR11 ,
VAR12 ,
VAR1 ,
VAR7 ,
VAR6,
VAR5,
VAR4 ,
VAR9
);
output VAR8 ;
input VAR3 ;
input VAR11 ;
input VAR12 ;
input VAR1 ;
input VAR7 ;
input VAR6;
input VAR5;
input VAR4 ;
input VAR9 ;
VAR10 VAR2 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(... | apache-2.0 |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/Sora_FRL_STATUS_decoder.v | 5,499 | module MODULE1(
input clk,
input VAR2,
output reg VAR10,
output reg VAR9,
output reg VAR4,
output reg VAR15,
output reg VAR7
);
reg VAR6; reg [3:0] VAR14;
reg [7:0] VAR12;
parameter VAR3 = 4'b0001;
parameter VAR11 = 4'b0010;
parameter VAR8 = 4'b0100;
parameter VAR13 = 4'b1000;
reg [3:0] VAR5;
VAR1 VAR12 <= 8'h00;
alway... | bsd-2-clause |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_i2s/rtl/i2s_mem_controller.v | 5,181 | module MODULE1 (
input rst,
input clk,
input enable,
input VAR33,
input VAR45,
output [23:0] VAR28,
output [1:0] VAR38,
input [1:0] VAR1,
input VAR25,
input [31:0] VAR24,
input VAR22,
output reg VAR32,
output reg [23:0] VAR46,
output reg VAR37
);
wire VAR30;
reg VAR31 = 0;
wire VAR18;
reg VAR7 = 0;
wire [23:0] VAR5;
wi... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_mul_dbl_pumped.v | 3,349 | module MODULE1
parameter VAR14=32
)
(
input VAR2,
input VAR10,
input enable,
input [VAR14-1:0] VAR11,
input [VAR14-1:0] b1,
input [VAR14-1:0] VAR4,
input [VAR14-1:0] VAR13,
output reg [VAR14-1:0] VAR16,
output reg [VAR14-1:0] VAR1
);
reg [VAR14-1:0] VAR15;
reg [VAR14-1:0] VAR9;
reg [VAR14-1:0] VAR7;
reg [VAR14-1:0] VAR... | mit |
airabinovich/finalArquitectura | UART/tx.v | 2,505 | module MODULE1 (
input VAR15, input reset,
input VAR4, input VAR9, input [7:0] VAR11, output reg VAR7, output reg VAR3 );
localparam [1:0] VAR12 = 0,
VAR8 = 1,
VAR13 = 2,
VAR14 = 3;
localparam VAR6=1'b0,
VAR2= 1'b1;
reg [1:0] VAR1, VAR10;
reg [2:0] VAR5;
reg [7:0] din;
always @(posedge VAR15, posedge reset)
begin
if(re... | lgpl-2.1 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9434/axi_ad9434_pnmon.v | 8,369 | module MODULE1 (
VAR7,
VAR15,
VAR4,
VAR11,
VAR9);
input VAR7;
input [47:0] VAR15;
input [ 3:0] VAR4;
output VAR11;
output VAR9;
reg [47:0] VAR1 = 'd0;
wire [47:0] VAR14;
wire [47:0] VAR13;
function [47:0] VAR6;
input [47:0] din;
reg [47:0] dout;
begin
dout[47] = din[8] ^ din[4];
dout[46] = din[7] ^ din[3];
dout[45] = d... | gpl-3.0 |
alpenwasser/pitaya | doc/report/sandbox/code-listings/code/axi_axis_reader.v | 2,721 | module MODULE1 #
(
parameter integer VAR27 = 32,
parameter integer VAR3 = 16
)
(
input wire VAR20,
input wire VAR4,
input wire [VAR3-1:0] VAR23, input wire VAR15, output wire VAR6, input wire [VAR27-1:0] VAR25, input wire VAR16, output wire VAR17, output wire [1:0] VAR7, output wire VAR18, input wire VAR11, input wire ... | mit |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s.v | 25,791 | module MODULE1 #(
parameter VAR123 = 0,
parameter integer VAR192 = 4,
parameter integer VAR60 = 30,
parameter integer VAR176 = 32,
parameter integer VAR106 = 1,
parameter integer VAR62 = 1
)
(
input wire VAR68 ,
input wire VAR142 ,
input wire [VAR192-1:0] VAR153 ,
input wire [VAR60-1:0] VAR122 ,
input wire [((VAR123 ==... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha_1.v | 2,184 | module MODULE2 (
VAR7,
VAR8 ,
VAR9 ,
VAR1 ,
VAR5,
VAR6,
VAR10 ,
VAR3
);
output VAR7;
output VAR8 ;
input VAR9 ;
input VAR1 ;
input VAR5;
input VAR6;
input VAR10 ;
input VAR3 ;
VAR2 VAR4 (
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
module MODULE2... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_ic_top.v | 10,246 | module MODULE1(
clk, rst,
VAR42, VAR56, VAR27, VAR23, VAR57, VAR18, VAR2,
VAR51, VAR31, VAR8,
VAR52,
VAR9, VAR55, VAR26,
VAR1, VAR49,
VAR11, VAR13, VAR39, VAR73, VAR7,
VAR46, VAR21, VAR53,
VAR32, VAR50, VAR41
);
parameter VAR34 = VAR66;
input clk;
input rst;
output [VAR34-1:0] VAR42;
output [31:0] VAR56;
output VAR27;
... | gpl-3.0 |
davidkoltak/tawas-core | ip/debug_ip/rtl/spdr.v | 17,725 | module MODULE1
(
input clk,
input VAR51,
input rst,
input VAR12,
input [31:0] VAR61,
input VAR1,
input [1:0] VAR38,
input VAR27,
output VAR3,
output [31:0] VAR5,
output [31:0] VAR36,
output VAR33,
output VAR64,
output [3:0] VAR88,
input [31:0] VAR77,
output reg VAR73,
output reg [31:0] VAR16,
output reg VAR13,
output V... | mit |
zhijian-liu/mips-cpu | src/cpu/stage/stage_ex.v | 16,677 | module MODULE1(
input reset ,
input [31:0] VAR18 ,
output [31:0] VAR28 ,
input [ 7:0] VAR13 ,
output [ 7:0] VAR35 ,
input [ 2:0] VAR42 ,
input [31:0] VAR2 ,
output [31:0] VAR10 ,
input [31:0] VAR43 ,
output [31:0] VAR32 ,
input VAR17 ,
output reg VAR39 ,
input [ 4:0] VAR12 ,
output reg [ 4:0] VAR25 ,
input [31:0] VAR15... | mit |
vipinkmenon/scas | hw/fpga/source/pcie_if/v6_pcie_top.v | 19,540 | module MODULE1 # (
parameter VAR201 = "VAR42",
parameter VAR104 = 64, parameter VAR14 = VAR104 / 8, parameter VAR217 = 4,
parameter VAR188 = 1,
parameter VAR74 = 1
)
(
output [3:0] VAR83,
output [3:0] VAR213,
input [3:0] VAR16,
input [3:0] VAR184,
input VAR181,
input VAR107,
input VAR11,
input VAR94,
output VAR209,
out... | mit |
toyoshim/mc6502 | rtl/MC6502InterruptLogic.v | 4,034 | module MODULE1(
clk,
VAR23,
VAR27,
VAR10,
VAR12,
VAR3,
VAR32,
VAR13,
VAR4,
VAR9,
VAR2,
VAR30,
VAR15,
VAR8,
VAR5,
VAR22,
VAR1,
VAR26,
VAR33);
input clk;
input VAR23;
input VAR27;
input VAR10;
input [ 7:0] VAR12;
input VAR3;
output [15:0] VAR32;
output VAR13;
output VAR4;
output [ 7:0] VAR9;
input [ 7:0] VAR2;
input [ 7:... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.symbol.v | 1,457 | module MODULE1 (
input VAR2 ,
output VAR3 ,
input VAR4 ,
input VAR1,
input VAR8,
input VAR5
);
supply1 VAR6;
supply0 VAR7;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a_2.v | 2,212 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR9,
VAR3
);
output VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR9;
input VAR3;
VAR4 VAR7 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR8 ,
VAR5,
VAR1,
VAR6,
VAR2
);... | apache-2.0 |
omicronns/studies-sys-rek | lab2/delay_line/src/delay_line.v | 1,204 | module MODULE1 #(
parameter VAR6 = 0,
parameter VAR4 = 8
)(
input VAR5,
input rst,
input clk,
input [VAR4 - 1:0] in,
output [VAR4 - 1:0] out
);
wire [VAR4 - 1:0] VAR2 [VAR6:0];
assign VAR2[0] = in;
assign out = VAR2[VAR6];
generate
genvar VAR1;
for(VAR1 = 0; VAR1 < VAR6; VAR1 = VAR1 + 1)
VAR3 #(
.VAR4(VAR4)
)
VAR7 (
.V... | mit |
alexforencich/xfcp | lib/eth/example/NetFPGA_SUME/fpga/rtl/si5324_i2c_init.v | 17,495 | module MODULE1 (
input wire clk,
input wire rst,
output wire [6:0] VAR11,
output wire VAR15,
output wire VAR8,
output wire VAR1,
output wire VAR12,
output wire VAR16,
output wire VAR4,
input wire VAR13,
output wire [7:0] VAR6,
output wire VAR3,
input wire VAR14,
output wire VAR9,
output wire VAR7,
input wire VAR2
);
lo... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.functional.v | 1,294 | module MODULE1 (
VAR1,
VAR7,
VAR8,
VAR3,
VAR4
);
output VAR1;
input VAR7;
input VAR8;
input VAR3;
input VAR4;
wire VAR5;
or VAR2 (VAR5, VAR4, VAR3, VAR8, VAR7 );
buf VAR6 (VAR1 , VAR5 );
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Chroma_Resampler.v | 9,131 | module MODULE1 (
clk,
reset,
VAR4,
VAR14,
VAR15,
VAR12,
VAR23,
VAR21,
VAR2,
VAR25,
VAR24,
VAR22,
VAR6,
VAR16
);
parameter VAR28 = 15; parameter VAR8 = 23;
parameter VAR17 = 0; parameter VAR18 = 1;
input clk;
input reset;
input [VAR28:0] VAR4;
input VAR14;
input VAR15;
input [VAR17:0] VAR12;
input VAR23;
input VAR21;
ou... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.blackbox.v | 1,532 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR11 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR6
);
output VAR7 ;
output VAR12 ;
input VAR11 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR6;
supply1 VAR10;
supply0 VAR3;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_timer_0.v | 6,782 | module MODULE1 (
address,
VAR21,
clk,
VAR13,
VAR14,
VAR23,
irq,
VAR32
)
;
output irq;
output [ 15: 0] VAR32;
input [ 2: 0] address;
input VAR21;
input clk;
input VAR13;
input VAR14;
input [ 15: 0] VAR23;
wire VAR9;
wire VAR11;
wire VAR26;
reg [ 3: 0] VAR7;
wire VAR29;
reg VAR16;
wire VAR12;
wire [ 31: 0] VAR33;
reg [ 3... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/MódulosBásicos/Fifo-muestras/Muestra 1/fifo.v | 2,590 | module MODULE1
parameter VAR4 = 4,
parameter VAR16 = 8
)
(
input clk, reset,
input rd, wr,
input [VAR16-1:0] VAR17,
output [VAR16-1:0] VAR15,
output VAR7,
output VAR10
);
parameter VAR3 = (1 << VAR4);
reg [VAR16-1:0] VAR9 [VAR3-1:0];
reg [VAR4-1:0] VAR14, VAR11;
reg [VAR4-1:0] VAR12, VAR13;
reg VAR2, VAR18, VAR6, VAR8;... | gpl-3.0 |
mlarouche/sd2snes | verilog/sd2snes_cx4/mcu_cmd.v | 13,054 | module MODULE1(
input clk,
input VAR51,
input VAR49,
input [7:0] VAR45,
input [7:0] VAR10,
output [2:0] VAR46,
output VAR34,
output VAR37,
output VAR53,
input VAR52,
output [7:0] VAR20,
input [7:0] VAR50,
output [7:0] VAR13,
input [31:0] VAR18,
input [2:0] VAR31,
output [23:0] VAR7,
output [23:0] VAR44,
output [23:0] V... | gpl-2.0 |
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