repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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|---|---|---|---|---|
asicguy/gplgpu | hdl/de/de_top_misc.v | 7,588 | module MODULE1
( input VAR46,
input VAR58,
input VAR21,
input VAR60,
input [1:0] VAR25,
input VAR4,
input VAR32,
input VAR17,
input [4:0] VAR38,
input VAR7,
input VAR59,
input VAR30,
input VAR15,
input VAR34,
input VAR9,
input VAR54,
input VAR13,
input VAR12,
input [23:0] VAR26,
input VAR1,
input VAR61,
input VAR42,
in... | gpl-3.0 |
olgirard/openmsp430 | fpga/xilinx_diligent_s3board/rtl/verilog/driver_7segment.v | 9,521 | module MODULE1 (
VAR50, VAR40, VAR22, VAR41, VAR36, VAR28, VAR21, VAR45, VAR53, VAR25, VAR1, VAR3, VAR42,
VAR7, VAR38, VAR56, VAR59, VAR4, VAR20 );
output [15:0] VAR50; output VAR40; output VAR22; output VAR41; output VAR36; output VAR28; output VAR21; output VAR45; output VAR53; output VAR25; output VAR1; output VAR3;... | bsd-3-clause |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/niosII_microc_lab1/db/ip/niosII_system/submodules/niosII_system_green_leds.v | 2,262 | module MODULE1 (
address,
VAR1,
clk,
VAR8,
VAR3,
VAR7,
VAR6,
VAR5
)
;
output [ 7: 0] VAR6;
output [ 31: 0] VAR5;
input [ 1: 0] address;
input VAR1;
input clk;
input VAR8;
input VAR3;
input [ 31: 0] VAR7;
wire VAR2;
reg [ 7: 0] VAR9;
wire [ 7: 0] VAR6;
wire [ 7: 0] VAR4;
wire [ 31: 0] VAR5;
assign VAR2 = 1;
assign VAR4 ... | gpl-2.0 |
ThotIP/async_fifo | src/vlog/rptr_empty.v | 2,487 | module MODULE1
parameter VAR10 = 4
)(
input wire VAR12,
input wire VAR8,
input wire VAR13,
input wire [VAR10 :0] VAR11,
output reg VAR15,
output reg VAR1,
output wire [VAR10-1:0] VAR9,
output reg [VAR10 :0] VAR2
);
reg [VAR10:0] VAR4;
wire [VAR10:0] VAR7, VAR14, VAR5;
wire VAR3, VAR6;
always @(posedge VAR12 or negedge ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor3/sky130_fd_sc_hs__xnor3.blackbox.v | 1,233 | module MODULE1 (
VAR4,
VAR6,
VAR5,
VAR1
);
output VAR4;
input VAR6;
input VAR5;
input VAR1;
supply1 VAR3;
supply0 VAR2;
endmodule | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/gpio/gpio_core.v | 2,580 | module MODULE1 #(
parameter VAR2 = 16,
parameter VAR11 = 8,
parameter VAR3 = 0,
parameter VAR6 = 0
) (
VAR5,
VAR1,
VAR19,
VAR23,
VAR17,
VAR7,
VAR18,
VAR13
);
localparam VAR15 = 0;
input wire VAR5;
input wire VAR1;
input wire [VAR2-1:0] VAR19;
input wire [7:0] VAR23;
output reg [7:0] VAR17;
input wire VAR7;
input wire V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.behavioral.v | 1,390 | module MODULE1 (
VAR5,
VAR3,
VAR7,
VAR4,
VAR12
);
output VAR5;
input VAR3;
input VAR7;
input VAR4;
input VAR12;
supply1 VAR8;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR9 ;
wire VAR6;
or VAR1 (VAR6, VAR12, VAR4, VAR7, VAR3 );
buf VAR10 (VAR5 , VAR6 );
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/DecOp4_XE.v | 14,388 | module MODULE1(
VAR5,
VAR9,
VAR64,
VAR91,
VAR105,
VAR99
);
input[31:0] VAR5;
output[6:0] VAR9;
output[6:0] VAR64;
output[6:0] VAR91;
output[31:0] VAR105;
output[7:0] VAR99;
reg[6:0] VAR94;
reg[6:0] VAR89;
reg[6:0] VAR62; reg[31:0] VAR34; reg[7:0] VAR83;
assign VAR9 = VAR94;
assign VAR64 = VAR89;
assign VAR91 = VAR62;
a... | mit |
aj-michael/Digital-Systems | Lab2-ManualKeypadScannerAndEncoder/KeyEncoderAJM.v | 1,489 | module MODULE1(VAR14, VAR3, VAR8);
input [3:0] VAR14;
input [3:0] VAR3;
output reg [4:0] VAR8;
parameter VAR4 = 0;
parameter VAR7 = 1;
parameter VAR2 = 2;
parameter VAR10 = 3;
parameter VAR16 = 4;
parameter VAR12 = 5;
parameter VAR6 = 6;
parameter VAR20 = 7;
parameter VAR5 = 8;
parameter VAR18 = 9;
parameter VAR19 = 10... | mit |
peteasa/oh | src/accelerator/dv/dut_accelerator.v | 17,435 | module MODULE1(
VAR9, VAR64, VAR117, VAR25, VAR95,
VAR23, VAR56, VAR82, VAR68, VAR86, VAR65, VAR51, VAR24
);
parameter VAR108 = 32;
parameter VAR66 = 12'h810;
parameter VAR120 = 12;
parameter VAR94 = 6;
parameter VAR119 = 2*VAR108 + 40;
parameter VAR6 = 1;
input VAR23;
input VAR56;
input VAR82;
input [VAR6*VAR6-1:0] VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_2.functional.pp.v | 1,081 | module MODULE1( VAR14, VAR6, VAR5, VAR13, VAR9, VAR4, VAR11 );
input VAR5, VAR6, VAR14, VAR9, VAR4, VAR11;
output VAR13;
or VAR3( VAR8, VAR6, VAR14 );
VAR2( VAR1, 1'b0, 1'b0, VAR5, VAR8, VAR11 );
wire VAR7;
not VAR10( VAR7, VAR1 );
or VAR12( VAR13, VAR5, VAR7 );
endmodule | apache-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/ad_dcfilter.v | 5,907 | module MODULE1 (
clk,
valid,
VAR96,
VAR78,
VAR30,
VAR5,
VAR24,
VAR69);
input clk;
input valid;
input [15:0] VAR96;
output VAR78;
output [15:0] VAR30;
input VAR5;
input [15:0] VAR24;
input [15:0] VAR69;
reg [47:0] VAR14 = 'd0;
reg [47:0] VAR55 = 'd0;
reg VAR27 = 'd0;
reg [15:0] VAR31 = 'd0;
reg VAR2 = 'd0;
reg [15:0] VA... | lgpl-3.0 |
monotone-RK/FACE | IEICE-Trans/bandwidth/PCIe/src/riffa_wrapper_vc707.v | 38,581 | module MODULE1
parameter VAR48 = 128,
parameter VAR206 = 256,
parameter VAR175 = 5,
parameter VAR112 = "VAR105")
( input [VAR48-1:0] VAR37,
input [(VAR48/8)-1:0] VAR289,
input VAR84,
input VAR145,
output VAR15,
input [VAR117-1:0] VAR328,
output VAR81,
output VAR302,
output [VAR48-1:0] VAR59,
output [(VAR48/8)-1:0] VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi.behavioral.v | 1,831 | module MODULE1 (
VAR1 ,
VAR5,
VAR19,
VAR18,
VAR11,
VAR12,
VAR9
);
output VAR1 ;
input VAR5;
input VAR19;
input VAR18;
input VAR11;
input VAR12;
input VAR9;
supply1 VAR20;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR13 ;
wire VAR8 ;
wire VAR7 ;
wire VAR14 ;
wire VAR17;
nand VAR2 (VAR8 , VAR19, VAR5 );
nand VAR10 (VAR7 , VAR... | apache-2.0 |
jakubfi/mera400f | src/ifctl.v | 2,440 | module MODULE1(
input VAR16,
input VAR22,
input VAR20,
input VAR17,
input VAR2,
input VAR15,
input VAR6,
input VAR21,
input VAR8,
input VAR9,
output reg VAR13,
output VAR3,
output VAR24,
output VAR18
);
parameter VAR19;
parameter VAR1;
wire VAR10 = VAR8 | VAR9;
assign VAR24 = VAR7 & VAR21;
assign VAR3 = VAR7 | VAR5 | (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.pp.symbol.v | 1,384 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR9 ,
input VAR7 ,
output VAR8 ,
input VAR2 ,
input VAR3,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
dvanmali/Superscalar_Pipeline_Processor | multiplier.v | 1,746 | module MODULE1(clk, VAR4, enable, VAR6, VAR9, VAR3, VAR1);
input clk, VAR4, enable;
input [31:0] VAR6, VAR9;
output [63:0] VAR3;
output VAR1;
reg [63:0] VAR3, VAR7;
reg [31:0] VAR5;
reg [63:0] VAR2;
reg VAR8;
reg [6:0] VAR10; | apache-2.0 |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/fifo_w16_d5_A.v | 2,977 | module MODULE1 (
clk,
VAR2,
VAR11,
VAR3,
VAR15);
parameter VAR16 = 32'd16;
parameter VAR6 = 32'd3;
parameter VAR17 = 32'd6;
input clk;
input [VAR16-1:0] VAR2;
input VAR11;
input [VAR6-1:0] VAR3;
output [VAR16-1:0] VAR15;
reg[VAR16-1:0] VAR14 [0:VAR17-1];
integer VAR10;
always @ (posedge clk)
begin
if (VAR11)
begin
for ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.functional.pp.v | 2,202 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR7 ,
VAR13 ,
VAR12 ,
VAR3,
VAR20 ,
VAR4 ,
VAR2 ,
VAR15
);
output VAR11 ;
output VAR6 ;
input VAR7 ;
input VAR13 ;
input VAR12 ;
input VAR3;
input VAR20 ;
input VAR4 ;
input VAR2 ;
input VAR15 ;
wire VAR14;
wire VAR10 ;
wire VAR1;
not VAR19 (VAR14 , VAR3 );
not VAR18 (VAR10 , VAR12 );
V... | apache-2.0 |
aj-michael/Digital-Systems | Lab4-Part1-40x7bit-RAM/ipcore_dir/Clock35MHz.v | 5,607 | module MODULE1
( input VAR19,
output VAR30,
output VAR49
);
VAR14 VAR25
(.VAR15 (VAR5),
.VAR26 (VAR19));
wire VAR42;
wire VAR29;
wire [7:0] VAR35;
wire VAR12;
wire VAR4;
wire VAR40;
VAR36
.VAR2 (20),
.VAR47 (7),
.VAR45 ("VAR9"),
.VAR13 (10.0),
.VAR1 ("VAR31"),
.VAR27 ("1X"),
.VAR43 ("VAR7"),
.VAR17 (0),
.VAR8 ("VAR9"))... | mit |
jasonabele/gnuradio | gr-gpio/src/fpga/lib/integ_shifter.v | 2,158 | module MODULE1(VAR6,VAR2,VAR1);
parameter VAR5 = 16;
parameter VAR3 = 8;
input [7:0] VAR6;
input wire [VAR5+VAR3-1:0] VAR2;
output reg [VAR5-1:0] VAR1;
reg [3:0] VAR4;
always @*
if (VAR6 >= 8'd128)
VAR4 = 8;
else if (VAR6 >= 8'd64)
VAR4 = 7;
else if (VAR6 >= 8'd32)
VAR4 = 6;
else if (VAR6 >= 8'd16)
VAR4 = 5;
else if (V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai221/gf180mcu_fd_sc_mcu7t5v0__oai221_2.behavioral.v | 3,306 | module MODULE1( VAR7, VAR1, VAR5, VAR2, VAR8, VAR6 );
input VAR8, VAR6, VAR1, VAR7, VAR2;
output VAR5;
VAR3 VAR4(.VAR7(VAR7),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6));
VAR3 VAR9(.VAR7(VAR7),.VAR1(VAR1),.VAR5(VAR5),.VAR2(VAR2),.VAR8(VAR8),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/inv/sky130_fd_sc_ms__inv_2.v | 1,995 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR4,
VAR7,
VAR6 ,
VAR3
);
output VAR5 ;
input VAR2 ;
input VAR4;
input VAR7;
input VAR6 ;
input VAR3 ;
VAR1 VAR8 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR5,
VAR2
);
output VAR5;
input VAR2;
supply1 VAR4;
supply0 VAR7;... | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/EEPROM_v1_01_a/hdl/verilog/OWM.v | 6,578 | module MODULE1 (
VAR59, VAR66, VAR76, VAR42, VAR44, VAR33, VAR18, VAR15,
VAR7, VAR74, VAR86,
VAR62, VAR50, VAR14, VAR87, VAR41, VAR8, VAR90, VAR11,
VAR82, VAR56, VAR54, VAR51, VAR52, VAR63, VAR46, VAR75,
VAR24, VAR91, VAR48, VAR72, VAR81, VAR35, VAR88, VAR39);
input [2:0] VAR59; input VAR66; input VAR76; input VAR42; i... | bsd-2-clause |
tmolteno/TART | hardware/FPGA/wishbone/example/wb_sram_dual_port.v | 5,621 | module MODULE1
parameter VAR23 = 1 << VAR14,
parameter VAR39 = VAR14-1,
parameter VAR21 = VAR14+1,
parameter VAR43 = 3)
(
input VAR41,
input VAR42, input VAR28,
input VAR25,
input VAR44,
input VAR37, output reg VAR29 = 0,
output reg VAR24 = 0,
input [VAR39:0] VAR35,
input [31:0] VAR15,
output reg [31:0] VAR34,
input VA... | lgpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/pmodgyro.v | 5,839 | module MODULE1 (
input wire clk,
input wire VAR15,
inout wire [3:0] VAR23,
output wire [15:0] VAR26,
output wire [15:0] VAR28,
output wire [15:0] VAR19,
output wire [15:0] VAR38,
output wire [7:0] VAR34,
output wire [15:0] VAR39,
output wire [15:0] VAR7,
output wire [15:0] VAR5,
output wire [15:0] VAR6,
output reg [ 7 ... | mit |
theapi/de1-soc | vga/DE1_SOC/DE1_SOC.v | 1,953 | module MODULE1(
input VAR13,
input VAR14,
input VAR1,
input VAR21,
input [3:0] VAR16,
output [7:0] VAR10,
output VAR3,
output VAR24,
output [7:0] VAR25,
output VAR34,
output [7:0] VAR33,
output VAR22,
output VAR12
);
wire VAR4;
wire VAR29, VAR5, VAR31, VAR9;
assign VAR22 = 1'b0;
assign VAR24 = VAR29;
VAR15 VAR32(
.VAR2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_pwrgood_pp_pg/sky130_fd_sc_hs__udp_pwrgood_pp_pg.blackbox.v | 1,311 | module MODULE1 (
VAR4,
VAR2 ,
VAR1 ,
VAR3
);
output VAR4;
input VAR2 ;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
chaohu/Daily-Learning | Verilog/lab2/lab2_3/lab3_2_1/lab3_2_1.srcs/sources_1/new/lab3_2_1.v | 2,229 | module MODULE1(
input [7:0] VAR4,
input VAR5,
output reg [2:0] VAR3,
output reg VAR1,VAR2
);
always
@(VAR4 or VAR5)
if(VAR5 == 1)
begin
VAR3=7;
VAR1 = 1;
VAR2 = 1;
end
else if(VAR5 == 0&&VAR4 == 255)
begin
VAR3 = 7;
VAR1 = 0;
VAR2 = 1;
end
else if(VAR5 == 0&&VAR4[7] == 0)
begin
VAR3 = 0;
VAR1 = 1;
VAR2 = 0;
end
else if... | mit |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/INPUT_CTL.v | 9,376 | module MODULE1(
clk,
reset,
VAR43,
VAR44,
VAR32,
VAR7,
VAR16,
VAR36,
VAR6,
VAR34,
VAR15,
VAR11,
VAR47,
VAR21,
VAR27,
VAR48,
VAR25,
VAR40,
VAR39);
input clk;
input reset;
input VAR44;
input [133:0] VAR32;
output VAR7;
input VAR16;
input [11:0] VAR36;
input VAR6;
input [133:0] VAR34;
output VAR15;
input VAR11;
input [11:... | apache-2.0 |
jairov4/accel-oil | solution_spartan3/impl/pcores/nfa_accept_samples_generic_hw_top_v1_00_a/synhdl/verilog/nfa_accept_sample.v | 49,215 | module MODULE1 (
VAR265,
VAR93,
VAR2,
VAR155,
VAR175,
VAR301,
VAR119,
VAR306,
VAR158,
VAR11,
VAR32,
VAR286,
VAR230,
VAR163,
VAR53,
VAR76,
VAR8,
VAR219,
VAR110,
VAR312,
VAR232,
VAR30,
VAR91,
VAR192,
VAR207,
VAR185,
VAR126,
VAR67,
VAR225,
VAR294,
VAR224,
VAR250,
VAR153,
VAR145,
VAR107,
VAR105,
VAR18,
VAR290,
VAR261,
VAR2... | lgpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA/integracion_fisica/front_end/source/RKOA_OPCHANGE.v | 4,055 | module MODULE1
(
input wire [VAR11-1:0] VAR25,
input wire [VAR11-1:0] VAR28,
output reg [2*VAR11-1:0] VAR21
);
wire [1:0] VAR27;
wire [3:0] VAR7;
assign VAR27 = 2'b00;
assign VAR7 = 4'b0000;
wire [VAR11/2-1:0] VAR2;
wire [VAR11/2:0] VAR26;
wire [VAR11/2-3:0] VAR4;
wire [VAR11/2-4:0] VAR16;
reg [4*(VAR11/2)-1:0] VAR1;
a... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tap/sky130_fd_sc_hd__tap.symbol.v | 1,228 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_onchip_memory2_0.v | 3,019 | module MODULE1 (
address,
VAR4,
VAR18,
clk,
VAR26,
reset,
VAR25,
write,
VAR27,
VAR21
)
;
parameter VAR28 = "MODULE1.VAR19";
output [ 63: 0] VAR21;
input [ 12: 0] address;
input [ 7: 0] VAR4;
input VAR18;
input clk;
input VAR26;
input reset;
input VAR25;
input write;
input [ 63: 0] VAR27;
wire VAR8;
wire [ 63: 0] VAR21;... | gpl-3.0 |
Canaan-Creative/MM | verilog/xilinx/bram.v | 3,468 | module MODULE1 #(
parameter VAR4 = 16384, parameter VAR35 = "VAR52" ) (
input wire VAR17, VAR64,
input wire VAR53, VAR47,
input wire [31:0] VAR59, VAR22,
input wire [31:0] VAR58, VAR46,
output wire [31:0] VAR44, VAR31,
input wire VAR13, VAR21,
input wire VAR61, VAR63
);
localparam VAR16 = VAR4 * 8 / 16384 ;
localparam ... | unlicense |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_gt_rx_valid_filter_7x.v | 9,131 | module MODULE1 #(
parameter VAR8 = 28,
parameter VAR11 = 1
)
(
output [1:0] VAR15,
output [15:0] VAR6,
output VAR30,
output VAR21,
output [ 2:0] VAR46,
output VAR41,
input [1:0] VAR4,
input [15:0] VAR25,
input VAR17,
input VAR40,
input [ 2:0] VAR19,
input VAR22,
input VAR24,
input VAR35,
input VAR9,
input VAR20
);
loca... | lgpl-3.0 |
P3Stor/P3Stor | DDR3/ip_top/mem_intfc.v | 40,225 | module MODULE1 #
(
parameter VAR139 = 100,
parameter VAR204 = 64,
parameter VAR64 = "1T",
parameter VAR124 = "0", parameter VAR6 = 3, parameter VAR86 = 2, parameter VAR171 = "8", parameter VAR209 = "VAR15", parameter VAR170 = 1, parameter VAR26 = 5,
parameter VAR244 = 12, parameter VAR65 = "VAR234", parameter VAR115 = ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvn/sky130_fd_sc_hdll__einvn.behavioral.v | 1,322 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR1
);
output VAR6 ;
input VAR3 ;
input VAR1;
supply1 VAR5;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR7 ;
notif0 VAR4 (VAR6 , VAR3, VAR1 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.ip_user_files/ipstatic/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_incr_cmd.v | 4,487 | module MODULE1 #
(
parameter integer VAR1 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR1-1:0] VAR2 ,
input wire [7:0] VAR11 ,
input wire [2:0] VAR15 ,
input wire VAR12 ,
output wire [VAR1-1:0] VAR13 ,
input wire VAR4 ,
output reg VAR7
);
reg VAR9;
reg [11:0] VAR16;
reg [8:0] VAR5;
reg VAR8;
wire [3:0] VA... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | coding_theory/decoder.v | 1,924 | module MODULE1 (VAR3,VAR6);
output reg [10:0] VAR6;
input [14:0] VAR3;
reg [3:0] VAR2;
reg [3:0] VAR1;
reg [3:0] VAR5;
reg [14:0] VAR4;
always @(*)
begin
VAR2[0]=VAR3[2]^VAR3[4]^VAR3[6]^VAR3[8]^VAR3[10]^VAR3[12]^VAR3[14];
VAR2[1]=VAR3[2]^VAR3[5]^VAR3[6]^VAR3[9]^VAR3[10]^VAR3[13]^VAR3[14];
VAR2[2]=VAR3[4]^VAR3[5]^VAR3[6... | mit |
atalbb/sha1 | SHA1_core.srcs/sources_1/new/SHA1_core.v | 32,125 | module MODULE1(
input clk,
input rst,
input VAR31,
input [159:0]VAR27,
input VAR19,
input [9:0]VAR23,
input [511:0]VAR16,
output reg VAR28,
output reg [159:0]VAR12
);
reg [31:0]VAR20[80:0],VAR24[80:0],VAR6[80:0],VAR5[80:0],VAR8[80:0];
reg [31:0]VAR29[4:0];
reg [31:0]VAR2[4:0];
reg [31:0]VAR13[3:0];
reg [31:0]VAR14[79:0... | apache-2.0 |
xuwenyihust/MapReduce_NoC | RTL/node.v | 1,544 | module MODULE1(clk, rst, VAR13, VAR9, VAR11, VAR1);
parameter VAR7 = 32;
input clk;
input rst;
input [VAR7-1:0] VAR13; input [VAR7-1:0] VAR9; input VAR11; input VAR1;
wire [VAR7-1:0] VAR6; wire VAR10; wire VAR17;
reg VAR3;
wire VAR14;
always@(posedge clk or rst)
if(!rst)
VAR3 <= 1'b0;
else
VAR3 <= VAR10;
assign VAR14 =... | mit |
peteasa/oh | src/xilibs/dv/OSERDESE2.v | 3,239 | module MODULE1 (
VAR10, VAR33, VAR40, VAR21, VAR24, VAR16, VAR2,
VAR3, VAR28, VAR31, VAR1, VAR25, VAR17, VAR32, VAR42, VAR39, VAR19, VAR20, VAR6, VAR12,
VAR15, VAR37, VAR14, VAR41, VAR4, VAR13, VAR9
);
parameter VAR38=0;
parameter VAR30=0;
parameter VAR18=0;
parameter VAR36=0;
parameter VAR8=0;
parameter VAR29=0;
param... | mit |
mbus/mbus | layer_controller_v2/verilog/mem_ctrl.v | 2,084 | module MODULE1(
VAR13,
VAR1,
VAR7,
VAR18,
VAR3,
VAR17,
VAR4,
VAR8
);
parameter VAR6 = 65536;
parameter VAR15 = 32;
parameter VAR19 = 32;
input VAR13;
input VAR1;
input [VAR19-3:0] VAR7;
input [VAR15-1:0] VAR18;
input VAR3;
input VAR17;
output reg [VAR15-1:0] VAR4;
output reg VAR8;
wire [VAR10(VAR6-1)-1:0] VAR9 = VAR7[V... | apache-2.0 |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_rxcounters.v | 8,304 | module MODULE1
(
VAR23, VAR36, VAR2, VAR5, VAR29, VAR30, VAR6, VAR32,
VAR20, VAR3, VAR21, VAR35, VAR25, VAR27, VAR14, VAR7,
VAR28, VAR15, VAR24,VAR4,VAR33,VAR22, VAR17,
VAR1, VAR8, VAR31, VAR34, VAR19
);
input VAR23;
input VAR36;
input VAR2;
input VAR29;
input [1:0] VAR30;
input VAR20;
input VAR5;
input VAR6;
input VAR... | gpl-2.0 |
rkrajnc/minimig-mist | rtl/minimig/denise_colortable_ram_mf.v | 9,738 | module MODULE1 (
VAR2,
VAR4,
VAR28,
enable,
VAR34,
VAR19,
VAR44,
VAR8);
input [3:0] VAR2;
input VAR4;
input [31:0] VAR28;
input enable;
input [7:0] VAR34;
input [7:0] VAR19;
input VAR44;
output [31:0] VAR8;
tri1 [3:0] VAR2;
tri1 VAR4;
tri1 enable;
tri0 VAR44;
wire [31:0] VAR24;
wire [31:0] VAR8 = VAR24[31:0];
VAR56 VAR... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_ic_fsm.v | 8,685 | module MODULE1(
clk, rst,
VAR17, VAR8, VAR4,
VAR3,
VAR6, VAR15,
VAR26, VAR19,
VAR7, VAR12,
VAR20,
VAR2, VAR24, VAR5,
VAR11
);
input clk;
input rst;
input VAR17;
input VAR8;
input VAR4;
input VAR3;
input VAR6;
input VAR15;
input [31:0] VAR26;
output [31:0] VAR19;
output [3:0] VAR7;
output VAR20;
output VAR2;
output VAR2... | mit |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/wasca.v | 63,700 | module MODULE1 (
input wire VAR156, output wire VAR401, output wire VAR54, input wire VAR367, output wire VAR129, input wire VAR39, input wire VAR226, output wire VAR19, output wire [12:0] VAR259, output wire [1:0] VAR181, output wire VAR42, output wire VAR122, output wire VAR361, inout wire [15:0] VAR328, output wire ... | gpl-2.0 |
manu3193/TextEditor | PS2_Controller.v | 7,287 | module MODULE1 #(parameter VAR30 = 0) (
VAR29,
reset,
VAR17,
VAR31,
VAR33, VAR22,
VAR28,
VAR35,
VAR19,
VAR25 );
input VAR29;
input reset;
input [7:0] VAR17;
input VAR31;
inout VAR33;
inout VAR22;
output VAR28;
output VAR35;
output [7:0] VAR19;
output VAR25;
wire [7:0] VAR21;
wire VAR12, VAR6, VAR14;
generate
if(VAR30) ... | mit |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_stub.v | 1,322 | module MODULE1(VAR1, VAR2)
;
input [9:0]VAR1;
output [31:0]VAR2;
endmodule | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_pipe_rate.v | 33,908 | module MODULE1 #
(
parameter VAR10 = "1.1", parameter VAR91 = "VAR70", parameter VAR65 = "VAR87", parameter VAR46 = "VAR115", parameter VAR63 = "VAR115", parameter VAR69 = "VAR87", parameter VAR48 = 4'd15
)
(
input VAR113,
input VAR83,
input VAR75,
input [ 1:0] VAR30,
input VAR2,
input VAR94,
input VAR97,
input VAR50,
... | lgpl-3.0 |
skalldri/mips-verilog | register-file/alu.v | 5,278 | module MODULE1 (VAR5, VAR2, VAR7, VAR4, VAR3);
input [31:0] VAR5;
input [31:0] VAR2;
input [4:0] VAR7;
output [31:0] VAR4;
output VAR3;
reg [31:0] VAR4 = 0;
reg VAR3 = 0;
reg [31:0] VAR6 = 0;
reg [31:0] VAR1 = 0;
always @(VAR5 or VAR2 or VAR7)
begin
if (VAR7 == 'b00000)
begin
VAR4 = VAR5 << VAR2;
VAR3 = 0;
, (VAR5), (V... | gpl-2.0 |
yupferris/kaze-hello | hello.v | 1,661 | module MODULE1(
input VAR15,
input VAR4,
output VAR11);
reg [7:0] VAR2;
reg VAR5;
wire VAR1;
reg [0:VAR6 - 1] VAR7;
reg [1:0] state;
always @(posedge VAR15 or negedge VAR4)
if (VAR4 == 1'b0) begin
VAR2 <= 0;
VAR5 <= 0;
VAR7 <= VAR8;
state <= VAR14;
end else begin
case (state)
if (VAR7[0:7] != 0) begin
VAR2 <= VAR7[0:7]... | bsd-2-clause |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_dma_reader/rtl/wb_dma_reader.v | 12,987 | module MODULE1 #(
parameter VAR87 = 8
)(
input clk,
input rst,
output [31:0] VAR79,
input VAR101,
input VAR51,
input [3:0] VAR115,
input [31:0] VAR72,
input VAR6,
output reg VAR37,
output reg [31:0] VAR9,
input [31:0] VAR22,
output reg VAR92,
output VAR3,
output VAR89,
output VAR90,
output [3:0] VAR55,
output [31:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311oi/sky130_fd_sc_ls__a311oi.symbol.v | 1,395 | module MODULE1 (
input VAR6,
input VAR4,
input VAR3,
input VAR7,
input VAR8,
output VAR2
);
supply1 VAR9;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
m-labs/milkymist | cores/pfpu/rtl/pfpu_prog.v | 1,713 | module MODULE1(
input VAR1,
input VAR13,
output [6:0] VAR2,
output [6:0] VAR12,
output [3:0] VAR14,
output [6:0] VAR17,
input VAR15,
input [1:0] VAR6,
input [8:0] VAR11,
output [31:0] VAR10,
input [31:0] VAR18,
input VAR3,
output [10:0] VAR16
);
wire [10:0] VAR7;
wire [24:0] VAR4;
reg [24:0] VAR5;
wire VAR9;
reg [24:0]... | lgpl-3.0 |
CeesWolfs/ceespu | src/ceespu_decode.v | 5,754 | module MODULE1(
input VAR48,
input VAR8,
input VAR69,
input VAR1,
input [31:0] VAR32,
input [31:0] VAR59,
input [31:0] VAR46,
input [13:0] VAR68,
input VAR23,
output reg [31:0] VAR3 = 0,
output reg [31:0] VAR67 = 0,
output reg [31:0] VAR17 = 0,
output reg [3:0] VAR37 = 0,
output reg VAR30 = 0,
output reg VAR56 = 0,
out... | mit |
quartushaters/project | M1/Part 1/rominout2_bb.v | 7,738 | module MODULE1 (
VAR2,
VAR3,
VAR4,
VAR1,
VAR5);
input [8:0] VAR2;
input [8:0] VAR3;
input VAR4;
output [31:0] VAR1;
output [31:0] VAR5;
tri1 VAR4;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand2/sky130_fd_sc_hs__nand2_1.v | 1,970 | module MODULE1 (
VAR5 ,
VAR6 ,
VAR3 ,
VAR1,
VAR4
);
output VAR5 ;
input VAR6 ;
input VAR3 ;
input VAR1;
input VAR4;
VAR7 VAR2 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR6,
VAR3
);
output VAR5;
input VAR6;
input VAR3;
supply1 VAR1;
supply0 VAR4;
VAR7 VAR2 (
.... | apache-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/rw_ctrl.v | 1,125 | module MODULE1(VAR3, clk, VAR5, VAR6, VAR2, VAR4);
input VAR3;
input clk;
input VAR5;
input VAR6;
output VAR2; output VAR4;
reg VAR2;
reg VAR1;
always @(posedge clk or negedge VAR3) begin
if (~VAR3) begin
VAR2 <= 1'b0;
end else begin
VAR2 <= VAR5;
end
end
always @(posedge clk or negedge VAR3) begin
if (~VAR3) begin
VAR... | mit |
alexforencich/xfcp | lib/eth/example/fb2CG/fpga_10g/rtl/led_sreg_driver.v | 3,657 | module MODULE1 #(
parameter VAR9 = 8,
parameter VAR4 = 0,
parameter VAR15 = 31
)
(
input wire clk,
input wire rst,
input wire [VAR9-1:0] VAR1,
output wire VAR21,
output wire VAR8,
output wire VAR3
);
localparam VAR16 = VAR20(VAR9+1);
localparam VAR7 = VAR20(VAR15+1);
reg [VAR16-1:0] VAR11 = 0;
reg [VAR7-1:0] VAR13 = 0;... | mit |
freecores/btcminer | fpga/miner253.v | 2,141 | module MODULE1 (clk, reset, VAR1, VAR18, VAR10, VAR15, VAR7);
parameter VAR5 = 32'd0;
parameter VAR16 = 32'd1;
parameter VAR14 = 32'd0;
input clk, reset;
input [255:0] VAR1;
input [95:0] VAR18;
output reg [31:0] VAR10, VAR7, VAR15;
reg [31:0] VAR22;
wire [255:0] VAR13;
wire [31:0] VAR17;
reg VAR6, VAR21, VAR9, VAR19;
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.behavioral.v | 1,399 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR5
);
output VAR7 ;
input VAR4 ;
input VAR5;
supply1 VAR2;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR1 ;
bufif0 VAR8 (VAR7 , VAR4, VAR5 );
endmodule | apache-2.0 |
DougFirErickson/parallella-hw | boards/archive/gen1.1/fpga/hdl/fifo_full_block.v | 2,811 | module MODULE1 (
VAR8, VAR6, VAR10,
reset, VAR7, VAR11, VAR5
);
parameter VAR2 = 2;
input reset;
input VAR7;
input [VAR2:0] VAR11; input VAR5;
output VAR8;
output [VAR2-1:0] VAR6;
output [VAR2:0] VAR10;
reg [VAR2:0] VAR10;
reg [VAR2:0] VAR9;
reg VAR8;
wire VAR4;
wire [VAR2:0] VAR3;
wire [VAR2:0] VAR1;
always @(posedge ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21a/sky130_fd_sc_hvl__o21a.functional.v | 1,416 | module MODULE1 (
VAR5 ,
VAR2,
VAR3,
VAR4
);
output VAR5 ;
input VAR2;
input VAR3;
input VAR4;
wire VAR7 ;
wire VAR1;
or VAR9 (VAR7 , VAR3, VAR2 );
and VAR8 (VAR1, VAR7, VAR4 );
buf VAR6 (VAR5 , VAR1 );
endmodule | apache-2.0 |
amerc/phimii | precompiled/server.v | 346,824 | module MODULE1(VAR39,VAR40,VAR19,VAR22,VAR7,VAR51,clk,rst,VAR50,VAR6,VAR4,VAR24,VAR43,VAR48);
integer VAR26;
real VAR9;
input [15:0] VAR39;
input [15:0] VAR40;
input VAR19;
input VAR22;
input VAR7;
input VAR51;
input clk;
input rst;
output [15:0] VAR50;
output [15:0] VAR6;
output VAR4;
output VAR24;
output VAR43;
outpu... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_printf_buffer_address_generator.v | 3,341 | module MODULE1
(
input VAR18,
input VAR20,
input enable,
output VAR17,
input VAR12,
input VAR24,
input [31:0] VAR1,
input [31:0] VAR3,
input VAR19,
output reg VAR10,
output reg [31:0] VAR11,
output VAR4,
output VAR13,
output [5:0] VAR23,
output [31:0] VAR16,
output [255:0] VAR7,
output [31:0] VAR5,
input VAR15,
input [... | mit |
terpstra/opa | syn/pll.v | 1,947 | module MODULE1(
input wire VAR15,
input wire rst,
output wire VAR6,
output wire VAR18
);
VAR7 #(
.VAR19("false"),
.VAR14("50.0 VAR5"),
.VAR8("VAR10"),
.VAR11(1),
.VAR4("100.000000 VAR5"),
.VAR12("0 VAR3"),
.VAR21(50),
.VAR20("VAR9"),
.VAR16("VAR9")
) VAR17 (
.rst (rst),
.VAR13 ({VAR6}),
.VAR18 (VAR18),
.VAR2 ( ),
.VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn_8.v | 2,018 | module MODULE1 (
VAR6 ,
VAR5,
VAR7 ,
VAR4,
VAR3
);
input VAR6 ;
input VAR5;
output VAR7 ;
input VAR4;
input VAR3;
VAR1 VAR2 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR6 ,
VAR5,
VAR7
);
input VAR6 ;
input VAR5;
output VAR7 ;
supply1 VAR4;
supply0 VAR3;
VAR1 VAR2 (
... | apache-2.0 |
sarchar/uart_de0_nano | uart_fifo.v | 6,161 | module MODULE1
VAR1 = 10)
(input reset,
input VAR26,
input VAR22, input [7:0] VAR18,
input VAR27,
input [7:0] VAR14,
input VAR29,
input VAR36,
output reg VAR32,
output VAR23,
output reg VAR3,
output reg [7:0] VAR15,
output reg [VAR24-1:0] VAR2,
output reg [VAR24-1:0] VAR16,
output reg [7:0] VAR33,
output reg [VAR1-1:0]... | mit |
fallen/milkymist-mmu | cores/pfpu/rtl/pfpu.v | 5,896 | module MODULE1 #(
parameter VAR3 = 4'h0
) (
input VAR7,
input VAR19,
input [13:0] VAR70,
input VAR75,
input [31:0] VAR42,
output [31:0] VAR24,
output irq,
output [31:0] VAR56,
output [31:0] VAR60,
output VAR27,
output VAR76,
input VAR58
);
wire VAR32;
wire [31:0] VAR33;
wire [31:0] VAR69;
wire VAR77;
wire [3:0] VAR39;
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp.behavioral.pp.v | 2,884 | module MODULE1 (
VAR8 ,
VAR15 ,
VAR28 ,
VAR6 ,
VAR27 ,
VAR3,
VAR20 ,
VAR26 ,
VAR1 ,
VAR17
);
output VAR8 ;
input VAR15 ;
input VAR28 ;
input VAR6 ;
input VAR27 ;
input VAR3;
input VAR20 ;
input VAR26 ;
input VAR1 ;
input VAR17 ;
wire VAR9 ;
wire VAR24 ;
wire VAR12 ;
reg VAR4 ;
wire VAR30 ;
wire VAR14 ;
wire VAR5 ;
wire... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/upd77c25_pgmrom.v | 9,258 | module MODULE1 (
VAR58,
VAR47,
VAR48,
VAR28,
VAR6,
VAR1);
input VAR58;
input [23:0] VAR47;
input [10:0] VAR48;
input [10:0] VAR28;
input VAR6;
output [23:0] VAR1;
tri1 VAR58;
tri0 VAR6;
wire [23:0] VAR37;
wire [23:0] VAR1 = VAR37[23:0];
VAR33 VAR40 (
.VAR9 (VAR28),
.VAR2 (VAR48),
.VAR21 (VAR58),
.VAR30 (VAR47),
.VAR38 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.v | 2,189 | module MODULE2 (
VAR2 ,
VAR8 ,
VAR7,
VAR4,
VAR9,
VAR3 ,
VAR1
);
output VAR2 ;
input VAR8 ;
input VAR7;
input VAR4;
input VAR9;
input VAR3 ;
input VAR1 ;
VAR5 VAR6 (
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2 ,
VAR8 ,
VAR7
);
output VAR2 ;... | apache-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_iverilog/Verilog_RTL/mkFPR_RegFile.v | 7,048 | module MODULE1(VAR50,
VAR22,
VAR32,
VAR43,
VAR76,
VAR44,
VAR1,
VAR72,
VAR74,
VAR52,
VAR13,
VAR63,
VAR5,
VAR6,
VAR60,
VAR33,
VAR69);
input VAR50;
input VAR22;
input VAR32;
output VAR43;
input VAR76;
output VAR44;
input [4 : 0] VAR1;
output [63 : 0] VAR72;
input [4 : 0] VAR74;
output [63 : 0] VAR52;
input [4 : 0] VAR13;
... | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/oq_regs_eval_full.v | 7,754 | module MODULE1
parameter VAR12 = 13,
parameter VAR39 = 8,
parameter VAR20 = 2,
parameter VAR9 = 8,
parameter VAR5 = VAR43(VAR9),
parameter VAR28 = 11,
parameter VAR29 = VAR28-VAR43(VAR39),
parameter VAR16 = 2048/VAR39, parameter VAR21 = 60/VAR39 + 1,
parameter VAR40 = VAR43((2**VAR12)/VAR21)
)
(
input VAR42,
input [VAR... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/ucore/pps_id.v | 14,237 | module MODULE1
(
VAR74,VAR48,
VAR49,
VAR63,VAR40,VAR39,
VAR27,VAR11,VAR22,VAR8,
VAR52,VAR31,
VAR33,VAR61,
VAR23,VAR10,VAR78,VAR20,VAR29,VAR81,
VAR16,VAR4,VAR67,
VAR41,VAR9,VAR68,VAR6,VAR62,VAR17,VAR32,VAR34,VAR43,VAR38,VAR83,
VAR58,VAR64,VAR57,VAR2
);
parameter VAR69 = VAR53;
parameter VAR79 = VAR79;
input VAR74;
input... | mit |
cambridgehackers/atomicc | doc/lpm/generated/Lpm.v | 7,527 | \begin{VAR19}
module MODULE1 (input wire VAR55, input wire VAR41,
input wire VAR24,
input wire [31:0]VAR6,
output wire VAR3,
output wire VAR25,
output wire [31:0]VAR28,
input wire VAR14);
wire [2:0]VAR53;
wire [15:0]VAR9;
wire VAR27;
wire VAR7;
wire [3:0]VAR29;
wire VAR35;
wire [22:0]VAR52;
wire VAR40;
wire VAR33;
wire... | gpl-2.0 |
miamiasheep/nctu-dlab-99 | lab8/state_control.v | 4,379 | module MODULE1(
input VAR13, VAR11, VAR8, VAR4, VAR23,
input [3:0] VAR2,
output [7:0] VAR9,
output reg [8:0] VAR1,
output reg [8:0] VAR3
);
localparam VAR20 = 2'd0;
localparam VAR17 = 2'd1;
localparam VAR7 = 2'd2;
localparam VAR15 = 2'd3;
localparam VAR16 = 2'd0;
localparam VAR10 = 2'd1;
localparam VAR18 = 2'd2;
localp... | gpl-3.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/eth_clockgen.v | 5,359 | module MODULE1(VAR5, VAR6, VAR7, VAR1, VAR9, VAR8);
input VAR5; input VAR6; input [7:0] VAR7;
output VAR8; output VAR1; output VAR9;
reg VAR8;
reg [7:0] VAR4;
wire VAR10;
wire [7:0] VAR2;
wire [7:0] VAR3;
assign VAR3[7:0] = (VAR7[7:0]<2)? 8'h02 : VAR7[7:0]; assign VAR2[7:0] = (VAR3[7:0]>>1) - 8'b1;
always @ (posedge VA... | gpl-3.0 |
Elphel/x353 | control/ioports353.v | 50,857 | module MODULE2#(
parameter VAR29 = "VAR66",
parameter VAR220 = "VAR186",
parameter VAR86 = 4,
parameter VAR162 = "0",
parameter VAR261 = "0"
) (VAR53,VAR218,VAR128,VAR117,VAR36,VAR279,VAR64,VAR71);
output VAR53,VAR36;
input VAR218,VAR279;
input VAR128,VAR64;
output VAR117,VAR71;
VAR25 #(
.VAR142(VAR29),
.VAR164(VAR86),... | gpl-3.0 |
maltanar/spmv-vector-cache | proj/ip/AXIOutputRegisters_1.0/hdl/AXIOutputRegisters_v1_0_S00_AXI.v | 22,057 | module MODULE1 #
(
parameter integer VAR43 = 32,
parameter integer VAR33 = 6
)
(
output wire [VAR43-1 : 0] VAR53,
output wire [VAR43-1 : 0] VAR50,
output wire [VAR43-1 : 0] VAR6,
output wire [VAR43-1 : 0] VAR49,
output wire [VAR43-1 : 0] VAR24,
output wire [VAR43-1 : 0] VAR21,
output wire [VAR43-1 : 0] VAR66,
output wi... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.pp.blackbox.v | 1,289 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR4 ,
VAR6,
VAR5,
VAR3 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR4 ;
input VAR6;
input VAR5;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn.pp.blackbox.v | 1,287 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR3,
VAR7,
VAR2,
VAR1 ,
VAR5
);
output VAR6 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR2;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
DatanoiseTV/Parallax-Propeller-P8X32A-FPGA | P8X32A_Emulation/P8X32A_DE0_Nano/cog_vid.v | 4,143 | module MODULE1
(
input VAR28,
input VAR15,
input VAR3,
input VAR26,
input VAR18,
input [31:0] VAR24,
input [31:0] VAR16,
input [31:0] VAR12,
input [7:0] VAR21,
input VAR20,
output ack,
output [31:0] VAR31
);
reg [31:0] VAR23;
reg [31:0] VAR4;
always @(posedge VAR28 or negedge VAR3)
if (!VAR3)
VAR23 <= 32'b0;
else if (V... | gpl-3.0 |
m-labs/milkymist | cores/pfpu/rtl/pfpu_faddsub.v | 3,799 | module MODULE1(
input VAR7,
input VAR3,
input [31:0] VAR40,
input [31:0] VAR32,
input VAR19,
input VAR26,
output [31:0] VAR31,
output reg VAR24
);
reg VAR28;
reg VAR13;
reg [7:0] VAR35;
reg [22:0] VAR36;
reg VAR15;
reg [7:0] VAR38;
reg [22:0] VAR4;
always @(posedge VAR7) begin
if(VAR3)
VAR28 <= 1'b0;
end
else begin
VAR... | lgpl-3.0 |
plindstroem/oh | elink/hdl/erx_cfg.v | 5,288 | module MODULE1 (
VAR3, VAR9, VAR5, VAR6, VAR22,
VAR25, VAR11, VAR17,
reset, clk, VAR27, VAR19, VAR18, VAR2, VAR1, VAR10
);
parameter VAR21 = 6; parameter VAR7 = 4'h0;
input reset; input clk;
input VAR27;
input VAR19; input [14:0] VAR18; input [31:0] VAR2;
output [31:0] VAR3;
output VAR9; output VAR5; input [8:0] VAR1; ... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_regfile_we.v | 2,231 | module MODULE1 (
address,
VAR8,
clk,
VAR1,
VAR5,
VAR3,
VAR9,
VAR2
)
;
output VAR9;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR8;
input clk;
input VAR1;
input VAR5;
input [ 31: 0] VAR3;
wire VAR6;
reg VAR4;
wire VAR9;
wire VAR7;
wire [ 31: 0] VAR2;
assign VAR6 = 1;
assign VAR7 = {1 {(address == 0)}} & VAR4;
a... | gpl-3.0 |
anderson1008/NOCulator | hring/hw/buffered/src/router_wrap.v | 7,928 | module MODULE1
(clk, reset, VAR1, VAR6, VAR36,
VAR50, VAR3, VAR49, VAR62,
VAR56);
localparam VAR66 = VAR41 * VAR52;
localparam VAR2 = VAR66 * VAR61;
localparam VAR28 = VAR24(VAR2);
localparam VAR35
= (VAR64 + VAR51 - 1) / VAR51;
localparam VAR37 = VAR60(VAR35, VAR63);
localparam VAR4 = VAR24(VAR37);
localparam VAR27 = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2.symbol.v | 1,262 | module MODULE1 (
input VAR5,
input VAR2,
output VAR3
);
supply1 VAR1;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
olgirard/opengfx430 | core/rtl/verilog/openGFX430.v | 23,218 | module MODULE1 (
VAR80, VAR93,
VAR2, VAR77, VAR150, VAR56, VAR117,
VAR42, VAR155,
VAR142, VAR61, VAR23, VAR88, VAR3, VAR91
VAR73, VAR101, VAR152, VAR100, VAR21,
VAR34, VAR22, VAR4, VAR116, VAR11, VAR109, VAR38 );
parameter [14:0] VAR118 = 15'h0200;
input VAR80; input VAR93;
input [13:0] VAR2; input VAR77; input [1:0] V... | bsd-3-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/altera/ad_rst.v | 2,998 | module MODULE1 (
VAR7,
clk,
rst);
input VAR7;
input clk;
output rst;
VAR2 #(.VAR8(1), .VAR1(1'b1)) VAR5 (
.enable (1'b1),
.VAR6 (1'b0),
.VAR3 (VAR7),
.VAR4 (clk),
.VAR9 (rst));
endmodule | gpl-3.0 |
lbl-cal/StanfordNoC | router/src/clib/c_binary_op.v | 2,741 | module MODULE1
(VAR6, VAR5);
parameter VAR7 = 2;
parameter VAR8 = 1;
parameter VAR4 = VAR3;
input [0:VAR8*VAR7-1] VAR6;
output [0:VAR8-1] VAR5;
wire [0:VAR8-1] VAR5;
generate
genvar VAR11;
for(VAR11 = 0; VAR11 < VAR8; VAR11 = VAR11 + 1)
begin:VAR10
wire [0:VAR7-1] VAR9;
genvar VAR2;
for(VAR2 = 0; VAR2 < VAR7; VAR2 = VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.functional.pp.v | 2,164 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR2 ,
VAR5 ,
VAR8 ,
VAR1,
VAR14,
VAR13 ,
VAR7
);
output VAR3 ;
input VAR9 ;
input VAR2 ;
input VAR5 ;
input VAR8 ;
input VAR1;
input VAR14;
input VAR13 ;
input VAR7 ;
wire VAR17 ;
wire VAR15 ;
wire VAR11 ;
wire VAR19;
nand VAR6 (VAR17 , VAR2, VAR9 );
nand VAR18 (VAR15 , VAR8, VAR5 );
and... | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/top.v | 19,434 | module MODULE1(
VAR187,
reset,
VAR89, VAR253, VAR229, VAR11,
VAR33, VAR92, VAR78, VAR254,
VAR98,
VAR151, VAR108, VAR119, VAR69,
VAR123,
VAR37, VAR30, VAR54,
VAR147, VAR127, VAR74,
VAR245, VAR76, VAR18,
VAR158, VAR73,
VAR94, VAR109,
VAR183, VAR63, VAR23,
VAR46,
VAR155, VAR197, VAR191,
VAR10, VAR2, VAR24,
VAR194, VAR110,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3/sky130_fd_sc_hd__or3.pp.blackbox.v | 1,281 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR3,
VAR5,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR3;
input VAR5;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/cpu.v | 8,758 | module MODULE1 (
input wire clk,
input wire clk,
input wire reset,
input wire [VAR83] VAR42,
input wire VAR57,
input wire VAR10,
output wire VAR46,
output wire [VAR27] VAR61,
output wire VAR14,
output wire VAR112,
output wire [VAR83] VAR18,
input wire [VAR83] VAR26,
input wire VAR104,
input wire VAR2,
output wire VAR68... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfbbn/sky130_fd_sc_hd__sdfbbn.blackbox.v | 1,528 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR10 ,
VAR7 ,
VAR6 ,
VAR9 ,
VAR12 ,
VAR4
);
output VAR5 ;
output VAR1 ;
input VAR10 ;
input VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR12 ;
input VAR4;
supply1 VAR8;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR11 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_sfr.v | 7,621 | module MODULE1 (
VAR26, VAR7, VAR29, VAR28, VAR3,
VAR1, VAR12, VAR30, VAR36, VAR11, VAR4, VAR24, VAR37, VAR18, VAR31, VAR17, VAR6 );
output VAR26; output [15:0] VAR7; output VAR29; output VAR28; output VAR3;
input VAR1; input VAR12; input [7:0] VAR30; input [15:0] VAR36; input VAR11; input [1:0] VAR4; input VAR24; inpu... | bsd-3-clause |
GustavoOS/ARMAria | src/ControlUnit/Ramifier.v | 1,706 | module MODULE1
parameter VAR7 = 4
)(
input [(VAR7 - 1):0] VAR1,
input VAR3, VAR6, VAR2, VAR5,
output reg VAR4
);
always @ ( * ) begin
case (VAR1)
0:begin VAR4 = VAR6;
end
1:begin VAR4 = !VAR6;
end
2:begin VAR4 = VAR2;
end
3:begin VAR4 = !VAR2;
end
4:begin VAR4 = VAR3;
end
5:begin VAR4 = !(VAR3);
end
6:begin VAR4 = VAR5... | mit |
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