repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
liqimai/Assignment1-Calculator | Integer-Arithmetic/IntegerMultiplication/IntegerMultiplication.v | 2,196 | module MODULE1(
input [31:0] VAR10,
input [31:0] VAR11,
output [63:0] VAR5,
input VAR3,
input clk
);
reg [65:0] VAR4;
reg [6:0] VAR1;
reg VAR7;
wire [32:0] VAR12,VAR13,VAR2,VAR9,VAR6;
wire [63:0] VAR8;
assign VAR13[31:0] = -VAR11,
VAR12[31:0] = (-VAR11)<<1,
VAR2[31:0] = VAR11,
VAR9[31:0] = VAR11<<1,
VAR13[32] = ~VAR11[... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N8_M8_P2_syn.v | 2,048 | module MODULE1 ( VAR20, VAR30, VAR60 );
input [7:0] VAR20;
input [7:0] VAR30;
output [8:0] VAR60;
wire VAR15, VAR66, VAR42, VAR54, VAR50, VAR53, VAR5, VAR44, VAR37, VAR17, VAR9, VAR38, VAR61, VAR59,
VAR35, VAR33, VAR40, VAR43;
VAR1 VAR41 ( .VAR25(VAR30[0]), .VAR21(VAR20[0]), .VAR4(VAR42) );
VAR70 VAR12 ( .VAR22(VAR20[3... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi.pp.blackbox.v | 1,474 | module MODULE1 (
VAR7 ,
VAR5,
VAR2,
VAR6 ,
VAR3 ,
VAR1,
VAR4,
VAR9 ,
VAR8
);
output VAR7 ;
input VAR5;
input VAR2;
input VAR6 ;
input VAR3 ;
input VAR1;
input VAR4;
input VAR9 ;
input VAR8 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcjesdadc1/a5gt/system_top.v | 11,502 | module MODULE1 (
VAR89,
VAR45,
VAR130,
VAR74,
VAR103,
VAR16,
VAR24,
VAR98,
VAR73,
VAR119,
VAR169,
VAR123,
VAR94,
VAR79,
VAR44,
VAR15,
VAR151,
VAR173,
VAR134,
VAR132,
VAR63,
VAR117,
VAR128,
VAR23,
VAR137,
VAR95,
VAR84,
VAR34,
VAR26,
VAR131,
VAR125,
VAR48,
VAR67,
VAR39,
VAR21,
VAR180,
VAR120,
VAR25,
VAR28,
VAR193);
input... | gpl-3.0 |
manasks/ece_510_pre_si_val | Lab1/building_blocks.v | 4,150 | module MODULE1
(
input VAR5,
input VAR2,
input VAR8,
output VAR9,
output VAR10
);
assign VAR9 = VAR5 ^ VAR2 ^ VAR8;
assign VAR10 = (VAR5 & VAR2) | (VAR2 & VAR8) | (VAR8 & VAR5);
endmodule
module MODULE6
(
input VAR21,
input VAR18,
input VAR20,
output VAR22,
output VAR6
);
assign VAR22 = VAR21 ^ VAR18 ^ VAR20;
assign VA... | gpl-3.0 |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/main_fsm.v | 2,598 | module MODULE1(VAR5, VAR21, VAR19, VAR10, VAR18, VAR2,
VAR13, VAR16, VAR17, VAR25, VAR26, VAR3,
VAR11, VAR9);
parameter VAR20 = 3'b000,
VAR23 = 3'b001,
VAR7 = 3'b010,
VAR12 = 3'b011,
VAR1 = 3'b100,
VAR22 = 3'b101,
VAR15 = 3'b110,
VAR14 = 2'b00,
VAR6 = 2'b01;
input VAR5;
input VAR21;
input VAR19;
input VAR18;
input VAR2... | mit |
AbhishekShah212/School_Projects | ELEN232/labs/Week8Lab.v | 3,203 | module MODULE1(
input VAR1,
output reg [6:0] VAR6,
output reg [3:0] VAR4
);
reg[1:0 ] VAR3 = 2'b00;
reg [27:0] VAR5;
reg VAR2;
begin
begin
end
begin
begin | mit |
perillamint/humbleverilogcalc | sixbitmul.v | 4,468 | module MODULE1 (VAR30, VAR20, sum, VAR65);
input[14:0] VAR30;
input[14:0] VAR20;
output[14:0] sum;
output VAR65;
wire[14:0] VAR37;
VAR15 VAR35 (VAR30[0], VAR20[0], 0, VAR37[0], sum[0]);
VAR15 VAR64 (VAR30[1], VAR20[1], VAR37[0], VAR37[1], sum[1]);
VAR15 VAR57 (VAR30[2], VAR20[2], VAR37[1], VAR37[2], sum[2]);
VAR15 VAR1... | gpl-3.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_gtp_pipe_drp.v | 11,724 | module MODULE1 #
(
parameter VAR35 = 2'd1, parameter VAR16 = 1'd0
)
(
input VAR11,
input VAR10,
input VAR32,
input VAR19,
input [15:0] VAR2,
input VAR27,
output [ 8:0] VAR23,
output VAR21,
output [15:0] VAR15,
output VAR37,
output VAR14,
output [ 2:0] VAR22
);
reg VAR18;
reg VAR33;
reg [15:0] VAR1;
reg VAR31;
reg VAR29... | mit |
Digilent/vivado-library | ip/Pmods/PmodSD_v1_0/src/PmodSD.v | 13,422 | module MODULE1
(VAR105,
VAR39,
VAR25,
VAR163,
VAR197,
VAR205,
VAR8,
VAR67,
VAR94,
VAR118,
VAR119,
VAR151,
VAR93,
VAR190,
VAR27,
VAR166,
VAR71,
VAR55,
VAR186,
VAR28,
VAR32,
VAR1,
VAR87,
VAR171,
VAR60,
VAR63,
VAR83,
VAR183,
VAR160,
VAR202,
VAR33,
VAR182,
VAR189,
VAR154,
VAR180,
VAR82,
VAR48,
VAR134,
VAR73,
VAR65,
VAR199,... | mit |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_onchip_memory2_0.v | 3,201 | module MODULE1 (
address,
VAR24,
VAR29,
clk,
VAR5,
VAR35,
reset,
VAR34,
write,
VAR36,
VAR17
)
;
parameter VAR13 = "MODULE1.VAR22";
output [ 31: 0] VAR17;
input [ 15: 0] address;
input [ 3: 0] VAR24;
input VAR29;
input clk;
input VAR5;
input VAR35;
input reset;
input VAR34;
input write;
input [ 31: 0] VAR36;
wire VAR25;... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor3/gf180mcu_fd_sc_mcu7t5v0__xor3_4.behavioral.v | 2,510 | module MODULE1( VAR1, VAR6, VAR4, VAR2 );
input VAR6, VAR1, VAR4;
output VAR2;
VAR3 VAR5(.VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4),.VAR2(VAR2));
VAR3 VAR7(.VAR1(VAR1),.VAR6(VAR6),.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3/sky130_fd_sc_ms__and3.pp.symbol.v | 1,280 | module MODULE1 (
input VAR7 ,
input VAR4 ,
input VAR1 ,
output VAR5 ,
input VAR6 ,
input VAR3,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
qeedquan/fpga | de2-115/vgaxor/vsg.v | 2,490 | module MODULE1
(
input wire rst,
input wire clk,
output reg VAR16,
output reg VAR1,
output reg VAR10
);
parameter VAR4 = 800;
parameter VAR3 = 144;
parameter VAR11 = 16;
parameter VAR2 = 525;
parameter VAR14 = 34;
parameter VAR13 = 11;
parameter VAR18 = 96;
parameter VAR5 = 2;
reg [10:0] VAR17;
reg [9:0] VAR6;
wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2/sky130_fd_sc_lp__mux2_m.v | 2,184 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR8 ,
VAR5 ,
VAR6,
VAR10,
VAR7 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR8 ;
input VAR5 ;
input VAR6;
input VAR10;
input VAR7 ;
input VAR3 ;
VAR4 VAR9 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE... | apache-2.0 |
andykarpov/radio-86rk-wxeda | src/rom/bios.v | 6,351 | module MODULE1 (
address,
VAR18,
VAR46);
input [10:0] address;
input VAR18;
output [7:0] VAR46;
tri1 VAR18;
wire [7:0] VAR8;
wire [7:0] VAR46 = VAR8[7:0];
VAR36 VAR19 (
.VAR30 (VAR18),
.VAR5 (address),
.VAR4 (VAR8),
.VAR6 (1'b0),
.VAR28 (1'b0),
.VAR33 (1'b1),
.VAR25 (1'b0),
.VAR1 (1'b0),
.VAR44 (1'b1),
.VAR24 (1'b1),
.... | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_rf_16x81.v | 12,587 | module MODULE1(
VAR27, VAR80, VAR20, VAR26, VAR79, VAR49, VAR73, VAR44, VAR22, VAR6, VAR68, VAR3, VAR52, VAR19, do
);
input VAR27;
input VAR80;
input VAR20;
input VAR26;
input VAR79;
input VAR49;
input VAR73;
input [4:0] VAR44;
input [3:0] VAR22;
input [3:0] VAR6;
input [80:0] VAR68;
input VAR3;
output VAR52;
output [8... | gpl-2.0 |
bkboggy/MIPS | FORWARDING_UNIT.v | 1,727 | module MODULE1(
input [4:0] VAR8,
input [4:0] VAR2,
input [4:0] VAR1,
input [1:0] VAR3,
input [4:0] VAR4,
input [1:0] VAR6,
output reg [1:0] VAR7,
output reg [1:0] VAR5);
always @ * begin
VAR7 <= 2'b00;
VAR5 <= 2'b00;
if (VAR3[1] &&
(VAR1 != 0) && (VAR1 == VAR8))
begin
VAR7 <= 2'b10;
end
if (VAR3[1] &&
(VAR1 != 0) && (... | mit |
Digilent/vivado-library | ip/hls_contrast_stretch_1_0/hdl/verilog/hls_contrast_strefYi.v | 5,326 | module MODULE3
VAR18 = 32,
VAR34 = 32,
VAR7 = 32
)
(
input clk,
input reset,
input VAR12,
input [VAR18-1:0] VAR27,
input [VAR34-1:0] VAR5,
input [1:0] VAR15,
output wire [1:0] VAR13,
output wire [VAR7-1:0] VAR31,
output wire [VAR7-1:0] VAR6
);
localparam VAR22 = (VAR18 > VAR34)? VAR18 : VAR34;
reg [VAR18-1:0] VAR2[0:VA... | mit |
mindrobots/P8X32A_Emulation | P8X32A_Nexys4/src/dig.v | 4,933 | module MODULE1
(
input VAR37,
output [7:0] VAR34,
input VAR23, input VAR7,
input [31:0] VAR33, output [31:0] VAR1, output [31:0] VAR16,
output [7:0] VAR35 );
reg [31:0] VAR31;
always @(posedge VAR23)
if (VAR37)
VAR31 <= VAR31 + 1'b1;
reg VAR38;
always @(posedge VAR23 or negedge VAR37)
if (!VAR37)
VAR38 <= 1'b0;
else
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a2111o/sky130_fd_sc_hd__a2111o_2.v | 2,448 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR12 ,
VAR2 ,
VAR6 ,
VAR11 ,
VAR10,
VAR9,
VAR3 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR12 ;
input VAR2 ;
input VAR6 ;
input VAR11 ;
input VAR10;
input VAR9;
input VAR3 ;
input VAR4 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50.functional.v | 1,309 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
wire VAR2;
buf VAR1 (VAR2, VAR3 );
buf VAR5 (VAR4 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4b/sky130_fd_sc_hdll__nor4b.behavioral.v | 1,518 | module MODULE1 (
VAR7 ,
VAR2 ,
VAR3 ,
VAR11 ,
VAR4
);
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR11 ;
input VAR4;
supply1 VAR10;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR14 ;
wire VAR1 ;
wire VAR13;
not VAR8 (VAR1 , VAR4 );
nor VAR6 (VAR13, VAR2, VAR3, VAR11, VAR1);
buf VAR12 (VAR7 , VAR13 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32o/sky130_fd_sc_hdll__a32o.behavioral.pp.v | 2,246 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR6 ,
VAR2 ,
VAR13 ,
VAR15 ,
VAR17,
VAR16,
VAR1 ,
VAR18
);
output VAR14 ;
input VAR10 ;
input VAR6 ;
input VAR2 ;
input VAR13 ;
input VAR15 ;
input VAR17;
input VAR16;
input VAR1 ;
input VAR18 ;
wire VAR19 ;
wire VAR5 ;
wire VAR11 ;
wire VAR4;
and VAR3 (VAR19 , VAR2, VAR10, VAR6 );
and... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nfc-substrate/bch_shared_kes-1.0.0/d_KES_PE_ELU_sMINodr.v | 5,766 | module MODULE1 (
input wire VAR20,
input wire VAR3,
input wire VAR4,
input wire VAR11,
input wire [VAR14-1:0] VAR7,
input wire [VAR14-1:0] VAR29,
input wire [VAR14-1:0] VAR17,
input wire [VAR14-1:0] VAR28,
input wire VAR8,
output reg [VAR14-1:0] VAR13,
output reg VAR5,
output reg [VAR14-1:0] VAR18
);
parameter [11:0] V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtp/gf180mcu_fd_sc_mcu9t5v0__icgtp_2.behavioral.v | 2,716 | module MODULE1( VAR19, VAR17, VAR23, VAR6 );
input VAR23, VAR17, VAR19;
output VAR6;
reg VAR11;
VAR8 VAR13(.VAR19(VAR19),.VAR17(VAR17),.VAR23(VAR23),.VAR6(VAR6),.VAR11(VAR11));
VAR8 VAR9(.VAR19(VAR19),.VAR17(VAR17),.VAR23(VAR23),.VAR6(VAR6),.VAR11(VAR11));
not VAR24(VAR4,VAR17);
not VAR20(VAR7,VAR19);
and VAR18(VAR21,V... | apache-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/clock_generator_pll_s8_diff.v | 9,646 | module MODULE1 (VAR23, VAR71, VAR31, VAR72, reset, VAR96, VAR26) ;
parameter integer VAR44 = 8 ; parameter integer VAR6 = 2 ; parameter integer VAR77 = 1 ; parameter real VAR95 = 6.000 ; parameter VAR25 = "VAR7" ;
input reset ; input VAR23, VAR71 ; output VAR31 ; output VAR72 ; output VAR96 ; output VAR26 ;
wire VAR76 ... | apache-2.0 |
parallella/oh | gpio/hdl/gpio.v | 8,307 | module MODULE1 #( parameter integer VAR66 = 24, parameter integer VAR62 = 32, parameter integer VAR44 = 104 )
(
input VAR35, input clk, input VAR54, input [VAR44-1:0] VAR39, output VAR18, output VAR60, output [VAR44-1:0] VAR42, input VAR3, output reg [VAR66-1:0] VAR2, output reg [VAR66-1:0] VAR59, input [VAR66-1:0] VAR... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_rank_timer.v | 120,334 | module MODULE1 #
( parameter
VAR146 = 2,
VAR126 = 4,
VAR52 = "VAR143",
VAR173 = 1,
VAR240 = 1,
VAR150 = 4,
VAR224 = 2,
VAR54 = 0,
VAR85 = 0,
VAR106 = 5,
VAR174 = 0,
VAR69 = 0,
VAR226 = 0,
VAR86 = 0,
VAR35 = 0,
VAR63 = 0,
VAR124 = 0,
VAR189 = 0,
VAR181 = 0,
VAR237 = 0,
VAR10 = 0,
VAR111 = 0
)
(
VAR172,
VAR32,
VAR70,
VAR... | gpl-3.0 |
eda-globetrotter/PicenoDecoders | viterbi/syn/src/bmu.v | 2,417 | module MODULE1 (VAR3, VAR5, VAR10, VAR8, VAR6, VAR4, VAR9, VAR7, VAR1, VAR2);
output [1:0] VAR10, VAR8, VAR6, VAR4, VAR9, VAR7, VAR1, VAR2;
input VAR3, VAR5;
reg [1:0] VAR10, VAR8, VAR6, VAR4, VAR9, VAR7, VAR1, VAR2;
always@ (VAR3 or VAR5)
begin
if (VAR3==0 && VAR5==0)
begin
VAR10 <= 2'd0; VAR8 <= 2'd2; VAR6 <= 2'd2; V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/fah/sky130_fd_sc_hd__fah_1.v | 2,283 | module MODULE2 (
VAR10,
VAR6 ,
VAR8 ,
VAR5 ,
VAR1 ,
VAR7,
VAR4,
VAR9 ,
VAR2
);
output VAR10;
output VAR6 ;
input VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR7;
input VAR4;
input VAR9 ;
input VAR2 ;
VAR11 VAR3 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.behavioral.pp.v | 2,231 | module MODULE1 (
VAR10 ,
VAR17,
VAR2,
VAR7 ,
VAR11 ,
VAR19,
VAR18,
VAR3 ,
VAR5
);
output VAR10 ;
input VAR17;
input VAR2;
input VAR7 ;
input VAR11 ;
input VAR19;
input VAR18;
input VAR3 ;
input VAR5 ;
wire VAR15 ;
wire VAR12 ;
wire VAR16 ;
wire VAR9;
and VAR1 (VAR15 , VAR7, VAR11 );
nor VAR6 (VAR12 , VAR17, VAR2 );
or ... | apache-2.0 |
MeshSr/onetswitch20 | ons20-app21-ref_switch/vivado/onets_7020_ref_switch/ip/ref_switch_core/src/ip/rxlengthfifo_128x13.v | 13,725 | module MODULE1(
rst,
VAR355,
VAR369,
din,
VAR218,
VAR349,
dout,
VAR281,
VAR14
);
input rst;
input VAR355;
input VAR369;
input [12 : 0] din;
input VAR218;
input VAR349;
output [12 : 0] dout;
output VAR281;
output VAR14;
VAR45 #(
.VAR197(0),
.VAR29(0),
.VAR11(0),
.VAR273(0),
.VAR194(0),
.VAR195(0),
.VAR98(0),
.VAR193(32)... | lgpl-2.1 |
thelonious/sound_out | DeltaSigma.v | 1,041 | module MODULE1(VAR8, VAR3, VAR4, VAR9);
output VAR8; reg VAR8; input [VAR1:0] VAR3; input VAR4;
input VAR9;
reg [VAR1+2:0] VAR2; reg [VAR1+2:0] VAR7; reg [VAR1+2:0] VAR5; reg [VAR1+2:0] VAR6;
always @(VAR5) VAR6 = {VAR5[VAR1+2], VAR5[VAR1+2]} << (VAR1+1);
always @(VAR3 or VAR6) VAR2 = VAR3 + VAR6;
always @(VAR2 or VAR5... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3_1.v | 2,037 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR3,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR3;
input VAR6;
VAR2 VAR4 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR5,
VAR1
);
output VAR5;
input VAR1;
supply1 VAR3;
supply0 VAR6;
VAR2 VAR4 (
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule | apache-2.0 |
rurume/openrisc_vision_hardware | ISE/or1200_spram_128x32.v | 7,371 | module MODULE1(
VAR1, VAR6, VAR5,
clk, rst, VAR17, VAR16, VAR8, addr, VAR18, VAR12
);
parameter VAR20 = 7;
parameter VAR9 = 32;
input VAR1;
input [VAR25 - 1:0] VAR5;
output VAR6;
input clk; input rst; input VAR17; input VAR16; input VAR8; input [VAR20-1:0] addr; input [VAR9-1:0] VAR18; output [VAR9-1:0] VAR12;
VAR7 VAR... | gpl-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/BRAM1.v | 2,806 | module MODULE1(VAR14,
VAR9,
VAR11,
VAR7,
VAR1,
VAR3
);
parameter VAR2 = 0;
parameter VAR13 = 1;
parameter VAR8 = 1;
parameter VAR5 = 1;
input VAR14;
input VAR9;
input VAR11;
input [VAR13-1:0] VAR7;
input [VAR8-1:0] VAR1;
output [VAR8-1:0] VAR3;
reg [VAR8-1:0] VAR4[0:VAR5-1];
reg [VAR8-1:0] VAR10;
reg [VAR8-1:0] VAR6;
i... | lgpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/lsu_basic_coalescer.v | 17,870 | module MODULE2
(
clk, reset, VAR81, VAR113, VAR19, VAR20, VAR88, VAR8,
VAR29, VAR26, VAR71, VAR109, VAR17, VAR14,
VAR98
);
parameter VAR42=32; parameter VAR28=4; parameter VAR38=32; parameter VAR75=2; parameter VAR82=32;
localparam VAR13=8*VAR28;
localparam VAR2=8*VAR38;
localparam VAR94=VAR70(VAR38);
localparam VAR34=... | mit |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_phy.v | 31,242 | module MODULE1 (
VAR3,
VAR98,
VAR38,
VAR9,
VAR94,
VAR6,
VAR57,
VAR63,
VAR72,
VAR47,
VAR67,
VAR12,
VAR48,
VAR76,
VAR23,
VAR18,
VAR19,
VAR70,
VAR92,
VAR74,
VAR34,
VAR22,
VAR50,
VAR52,
VAR55,
VAR82,
VAR1,
VAR44,
VAR88,
VAR105,
VAR71,
VAR68,
VAR87,
VAR13,
VAR41,
VAR58,
VAR11,
VAR35,
VAR75,
VAR26,
VAR79,
VAR61,
VAR66,
VAR91... | gpl-3.0 |
alonso193/proyecto1 | Pruebas/REGS_SD/REG.v | 10,261 | module MODULE1(clk, VAR69, addr, VAR50, VAR33, ack, req, reset);
parameter VAR5 = 32;
parameter VAR39 = 5;
parameter VAR32 = 28;
input clk;
wire clk;
input VAR69;
wire VAR69;
input req;
wire req;
output ack;
reg ack;
input [VAR39-1: 0] addr;
wire addr;
input [VAR5-1: 0] VAR50;
wire VAR50;
output [VAR5-1: 0] VAR33;
reg ... | gpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/i2s_audio.v | 2,911 | module MODULE1 (
input VAR4,
input [15:0] VAR7,
input [15:0] VAR1,
output reg [3:0] VAR6,
output reg VAR2,
output VAR5
);
reg [5:0] VAR10 = 0;
reg [3:0] VAR8 = 0;
reg [63:0] VAR12 = 64'd0;
reg VAR3 = 0;
reg [15:0] VAR9[0:2];
reg [15:0] VAR11[0:2];
assign VAR5 = VAR4;
always @(negedge VAR4)
begin
VAR2 <= VAR10[5];
VAR6[... | gpl-3.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_register.v | 4,685 | module MODULE1 #
(
parameter VAR11 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR11-1:0] VAR7,
input wire VAR13,
output wire VAR1,
input wire VAR5,
input wire VAR3,
output wire [VAR11-1:0] VAR18,
output wire VAR2,
input wire VAR16,
output wire VAR9,
output wire VAR8
);
reg VAR17 = 0;
reg [VAR11-1:0] VAR15 = 0;... | mit |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/master_interface.v | 8,233 | module MODULE1(
VAR30,
VAR21,
VAR5,
clk,
rst,
VAR24,
VAR22,
VAR18,
VAR25,
VAR3,
VAR17,
VAR27
);
output VAR30;
input [7:0] VAR21;
input VAR5;
input clk;
input rst;
input VAR24;
output VAR22;
output [7:0] VAR18;
output [7:0] VAR25;
output [15:0] VAR3;
output [15:0] VAR17;
output [15:0] VAR27;
reg VAR30;
reg VAR22;
reg [7... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_pipeline_base.v | 4,568 | module MODULE1 (
clk,
reset,
VAR16,
VAR11,
VAR13,
VAR5,
VAR1,
VAR15
);
parameter VAR9 = 1;
parameter VAR3 = 8;
parameter VAR6 = 1;
localparam VAR7 = VAR9 * VAR3;
input clk;
input reset;
output VAR16;
input VAR11;
input [VAR7-1:0] VAR13;
input VAR5;
output VAR1;
output [VAR7-1:0] VAR15;
reg VAR14;
reg VAR12;
reg [VAR7-1... | mit |
shahid313/MSCourseWork | Adv ASIC Design and FPGA/8bitRISCProcessor/8bitRISCProcessor/RISC/rom.v | 1,486 | module MODULE1 ( input [7:0] addr,output reg [15:0] dout );
always @ (addr)
case (addr)
8'b00000000: dout = 16'b0111000000010111; 8'b00000001: dout = 16'b1000000100100010; 8'b00000010: dout = 16'b1010000000100000; 8'b00000011: dout = 16'b1001000000110000; 8'b00000100: dout = 16'b0001000100100100; 8'b00000101: dout = 16... | gpl-2.0 |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ip/image_processing_2d_design_frequency_analyzer_manager_0_1/synth/image_processing_2d_design_frequency_analyzer_manager_0_1.v | 6,862 | module MODULE1 (
VAR11,
VAR3,
VAR25,
VAR19,
VAR30,
irq,
VAR14,
VAR17,
VAR15,
VAR5,
VAR6,
VAR10,
VAR29,
VAR4,
VAR16,
VAR1,
VAR23,
VAR27,
VAR21,
VAR20,
VAR7,
VAR26,
VAR22,
VAR2,
VAR12,
VAR24,
VAR18
);
input wire [7 : 0] VAR11;
input wire VAR3;
input wire VAR25;
input wire VAR19;
input wire VAR30;
output wire irq;
input w... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.behavioral.v | 7,158 | module MODULE1( VAR1, VAR3, VAR5, VAR8, VAR9, VAR7, VAR10 );
input VAR7, VAR10, VAR9, VAR8, VAR1, VAR5;
output VAR3;
VAR6 VAR2(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR9(VAR9),.VAR7(VAR7),.VAR10(VAR10));
VAR6 VAR4(.VAR1(VAR1),.VAR3(VAR3),.VAR5(VAR5),.VAR8(VAR8),.VAR9(VAR9),.VAR7(VAR7),.VAR10(VAR10)); | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/bacb4a7006262daa/zqynq_lab_1_design_xbar_0_stub.v | 5,974 | module MODULE1(VAR57, VAR65, VAR29, VAR28,
VAR60, VAR4, VAR31, VAR51, VAR25, VAR78,
VAR37, VAR52, VAR77, VAR13, VAR33, VAR69,
VAR43, VAR68, VAR23, VAR70, VAR3, VAR58, VAR34,
VAR46, VAR6, VAR27, VAR71, VAR35, VAR11,
VAR15, VAR42, VAR41, VAR1, VAR62, VAR66, VAR30,
VAR45, VAR72, VAR20, VAR73, VAR39, VAR55, VAR24,
VAR63, V... | mit |
titorgalaxy/lzw | hw/src/Thermometer.v | 3,181 | module MODULE1(
VAR14,
VAR6,
enable,
VAR13
);
parameter VAR11=0;
localparam VAR15=(1<<VAR11);
localparam VAR10=(1<<(VAR11-1));
output reg [VAR15-1:0] VAR14;
input [VAR11+1-1:0] VAR6;
input enable;
input VAR13;
reg VAR9;
reg VAR2;
reg VAR4;
reg VAR16;
wire [VAR10+1-1:0] VAR7;
wire [VAR10+1-1:0] VAR3;
generate
if(VAR11<=... | gpl-3.0 |
mbuesch/pyprofibus | phy_fpga/block_ram_mod.v | 1,605 | module MODULE1 #(
parameter VAR5 = 16,
parameter VAR10 = 8,
parameter VAR6 = 1024,
) (
input clk,
input [VAR5 - 1 : 0] VAR2,
output reg [VAR10 - 1 : 0] VAR8,
input [VAR10 - 1 : 0] VAR4,
input VAR9,
input [VAR5 - 1 : 0] VAR1,
output reg [VAR10 - 1 : 0] VAR7,
);
reg [VAR10 - 1 : 0] VAR11 [VAR6 - 1 : 0];
integer VAR3; | gpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/ssio_ddr_out.v | 2,236 | module MODULE1 #
(
parameter VAR17 = "VAR9",
parameter VAR7 = "VAR13",
parameter VAR14 = "VAR10",
parameter VAR19 = 1
)
(
input wire clk,
input wire VAR11,
input wire [VAR19-1:0] VAR8,
input wire [VAR19-1:0] VAR4,
output wire VAR12,
output wire [VAR19-1:0] VAR6
);
wire VAR16 = VAR14 == "VAR10" ? VAR11 : clk;
VAR2 #(
.V... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_speed/debouncer.v | 4,159 | module MODULE1
parameter VAR1 = 4
)
(
input VAR4,
input VAR5,
input VAR6,
output reg VAR3
);
reg [VAR1-1:0] VAR2;
always @(posedge VAR4)
begin
if(VAR5 == 1)
begin
VAR2 <= 0;
VAR3 <= 0;
end
else
begin
VAR2 <= {VAR2[VAR1-2:0], VAR6};
if(VAR2 == {VAR1{1'b1}})
begin
VAR3 <= 1'b1;
end
else if(VAR2 == {VAR1{1'b0}})
begin
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.behavioral.v | 1,325 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR3 ;
wire VAR8;
not VAR4 (VAR8, VAR1 );
buf VAR7 (VAR2 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.symbol.v | 1,655 | module MODULE1 (
input VAR7 ,
output VAR5 ,
input VAR2 ,
input VAR3 ,
input VAR1 ,
input VAR4,
input VAR8 ,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio/sky130_fd_io__top_sio.pp.blackbox.v | 2,760 | module MODULE1 (
VAR18 ,
VAR12,
VAR10 ,
VAR27 ,
VAR7 ,
VAR1 ,
VAR24 ,
VAR13 ,
VAR3 ,
VAR11 ,
VAR25 ,
VAR26 ,
VAR5 ,
VAR23 ,
VAR4 ,
VAR17 ,
VAR6,
VAR22 ,
VAR16 ,
VAR2 ,
VAR8,
VAR14 ,
VAR21 ,
VAR28 ,
VAR15 ,
VAR9 ,
VAR19 ,
VAR20
);
output VAR18 ;
inout VAR12;
inout VAR10 ;
input [2:0] VAR27 ;
input VAR7 ;
input VAR1 ;
ou... | apache-2.0 |
gajjanag/6111_Project | src/bram.v | 1,817 | module MODULE1(input wire VAR7,
input wire VAR1,
input wire[16:0] VAR6,
input wire[11:0] VAR8,
input wire VAR4,
input wire[16:0] VAR3,
output reg[11:0] VAR5);
reg[11:0] VAR2[76799:0];
always @(posedge VAR7) begin
if (VAR1) begin
VAR2[VAR6] <= VAR8;
end
end
always @(posedge VAR4) begin
VAR5 <= VAR2[VAR3];
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.symbol.v | 1,363 | module MODULE1 (
input VAR2,
input VAR4,
input VAR1,
input VAR5,
output VAR7
);
supply1 VAR9;
supply0 VAR8;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fpu/bsg_fpu_preprocess.v | 1,171 | module MODULE1
, parameter VAR10(VAR5 )
)
(
input [VAR12+VAR5:0] VAR3
, output logic VAR14
, output logic VAR1
, output logic VAR11
, output logic VAR2
, output logic VAR7
, output logic VAR17
, output logic VAR9
, output logic VAR16
, output logic [VAR12-1:0] VAR8
, output logic [VAR5-1:0] VAR13
);
assign VAR13 = VAR3... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.blackbox.v | 1,323 | module MODULE1 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/rw_manager_inst_ROM_reg.v | 1,454 | module MODULE1(
VAR2,
VAR4,
VAR6,
VAR9,
VAR5,
VAR7);
parameter VAR3 = "";
parameter VAR8 = "";
input [(VAR8-1):0] VAR2;
input VAR4;
input [(VAR8-1):0] VAR9;
input [(VAR3-1):0] VAR6;
input VAR5;
output reg [(VAR3-1):0] VAR7;
reg [(VAR3-1):0] VAR1[(2**VAR8-1):0];
always @(posedge VAR4)
begin
if (VAR5)
VAR1[VAR9]<= VAR6;
... | lgpl-3.0 |
jaechoon2/FPGA-Imaging-Library | Point/Threshold/HDL/Threshold.srcs/sources_1/new/Threshold.v | 3,283 | module MODULE1(
clk,
VAR9,
VAR2,
VAR1,
VAR3,
VAR6,
VAR12,
VAR8,
VAR11
);
parameter VAR5 = 0;
parameter VAR7 = 8;
input clk;
input VAR9;
input VAR2;
input [VAR7 - 1 : 0] VAR1;
input [VAR7 - 1 : 0] VAR3;
input VAR6;
input [VAR7 - 1 : 0] VAR12;
output VAR8;
output VAR11;
reg VAR4;
reg VAR10;
generate
always @(posedge clk ... | lgpl-2.1 |
Madh93/scpu | modules/uc.v | 9,361 | module MODULE1(input wire VAR21,reset,VAR24, input wire [1:0] VAR10, input wire [5:0] VAR18,
output reg VAR12, VAR14, VAR9, VAR5, VAR8, VAR6, VAR13, VAR20, VAR15, VAR19, VAR7, VAR1, VAR22, output wire [2:0] VAR23);
assign VAR23 = VAR18[2:0];
always @(*)
begin
VAR5 <= 1'b0; VAR8 <= 1'b0; VAR6 <= 1'b0; VAR13 <= 1'b0; VAR... | mit |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/hps_sdram_p0_generic_ddio.v | 2,314 | module MODULE1(
VAR23,
VAR3,
VAR11,
VAR9,
VAR20
);
parameter VAR17 = 1;
localparam VAR15 = 4 * VAR17;
localparam VAR5 = VAR17;
input [VAR15-1:0] VAR23;
input VAR3;
input [VAR17-1:0] VAR9;
input [VAR17-1:0] VAR20;
output [VAR5-1:0] VAR11;
generate
genvar VAR13;
for (VAR13 = 0; VAR13 < VAR17; VAR13 = VAR13 + 1)
begin:VAR... | gpl-2.0 |
chaohu/Daily-Learning | Digital-Logic/lab/design/Chip_Decoder/Chip_Decoder.srcs/sources_1/new/Chip_Decoder.v | 1,196 | module MODULE1(
input VAR6,VAR8,VAR16,VAR11,VAR15,VAR2,VAR5,VAR9,
output reg [3:0] VAR3,
output reg VAR10,VAR13
);
reg [1:0] VAR14;
parameter VAR7 = 0,VAR12 = 1,VAR4 = 2,VAR1 = 3;
always @(VAR6 or VAR8 or VAR2 or VAR16 or VAR5 or VAR9)
begin
if((VAR6 == 1) & (VAR8 == 1) & (VAR2 == 0) & VAR16 & (VAR5 != VAR9))
VAR10 = 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_2.v | 2,463 | module MODULE2 (
VAR11 ,
VAR6,
VAR3,
VAR10 ,
VAR2 ,
VAR7,
VAR4,
VAR8 ,
VAR9
);
output VAR11 ;
input VAR6;
input VAR3;
input VAR10 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR8 ;
input VAR9 ;
VAR1 VAR5 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9... | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/ControlUnit/controlunit.v | 2,357 | module MODULE1 (output reg VAR6, VAR13, VAR18, VAR16, VAR10, VAR1, VAR7, VAR11,VAR3,VAR22,VAR5,VAR9,VAR14,output reg[4:0] VAR20, output reg[3:0] VAR17, input VAR12, VAR4,VAR2, input [31:0] VAR15,input [3:0] VAR19);
reg [4:0] VAR24, VAR8;
task VAR23;
input [17:0] VAR21;
fork
{VAR17,VAR6, VAR13, VAR18, VAR16,VAR20, VAR10... | apache-2.0 |
mammenx/synesthesia_moksha | wxp/dgn/syn/limbus/synthesis/submodules/limbus_nios2_qsys_0_jtag_debug_module_tck.v | 8,288 | module MODULE1 (
VAR8,
VAR40,
VAR22,
VAR38,
VAR7,
VAR1,
VAR39,
VAR35,
VAR20,
VAR31,
VAR15,
VAR32,
VAR17,
VAR12,
VAR24,
VAR36,
VAR16,
VAR11,
VAR19,
VAR25,
VAR4,
VAR23,
VAR10,
VAR5,
VAR29,
VAR30,
VAR13,
VAR28,
VAR18,
VAR14,
VAR21
)
;
output [ 1: 0] VAR13;
output VAR28;
output [ 37: 0] VAR18;
output VAR14;
output VAR21;
i... | gpl-3.0 |
toomij/DE2Labs | Lab2/lab2_part2.v | 3,611 | module MODULE1 (VAR11, VAR5, VAR2, VAR7, VAR3);
input [17:0] VAR11;
output [0:6] VAR5, VAR2, VAR7, VAR3;
wire VAR16;
wire [3:0] VAR14, VAR12;
assign VAR12[3] = 0;
MODULE2 VAR17 (VAR11[3:0], VAR16);
MODULE3 VAR8 (VAR11[3:0], VAR12[2:0]);
MODULE4 VAR15 (VAR16, VAR11[3:0], VAR12, VAR14);
MODULE6 VAR4 (VAR16, VAR2);
MODULE... | gpl-2.0 |
dhesant/elec4320 | Lab2/key_encoder.v | 1,274 | module MODULE1( VAR2, VAR4, clk );
input [8:0] VAR2; input clk;
output [4:0] VAR4;
reg [2:0] VAR3;
reg [1:0] VAR1;
always @ (posedge clk) begin
case (VAR2[8:7]) 2'b11: VAR1 <= 0;
2'b01: VAR1 <= 1;
2'b00: VAR1 <= 2;
2'b10: VAR1 <= 3;
endcase
case (VAR2[6:0])
7'b0000001: VAR3 <= 1;
7'b0000010: VAR3 <= 2;
7'b0000100: VAR3... | mit |
rkrajnc/minimig-mist | rtl/or1200/or1200_top.v | 24,381 | module MODULE1(
VAR202, VAR95, VAR167, VAR356,
VAR162, VAR227, VAR75, VAR343, VAR248, VAR217,
VAR369, VAR316, VAR123, VAR31, VAR173, VAR361,
VAR57,
VAR319, VAR24,
VAR250, VAR14, VAR84, VAR189, VAR93, VAR71,
VAR141, VAR5, VAR374, VAR310, VAR298, VAR121,
VAR171,
VAR65, VAR351,
VAR87, VAR82, VAR131, VAR267, VAR355, VAR53,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.v | 2,119 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR5,
VAR1,
VAR2 ,
VAR8
);
output VAR7 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR2 ;
input VAR8 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR7,
VAR3
);
output VAR7;
input VAR3;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
PeterMagnusson/modexp | src/rtl/modexp_core.v | 28,644 | module MODULE1(
input wire clk,
input wire VAR130,
input wire VAR174,
output wire ready,
input wire [07 : 0] VAR33,
input wire [07 : 0] VAR68,
output wire [63 : 0] VAR69,
input wire VAR15,
input wire VAR18,
input wire VAR5,
input wire [31 : 0] VAR167,
output wire [31 : 0] VAR81,
input wire VAR151,
input wire VAR57,
inp... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.functional.pp.v | 1,786 | module MODULE1 (
VAR1 ,
VAR10 ,
VAR2,
VAR6,
VAR4 ,
VAR11
);
output VAR1 ;
input VAR10 ;
input VAR2;
input VAR6;
input VAR4 ;
input VAR11 ;
wire VAR12 ;
wire VAR3;
buf VAR7 (VAR12 , VAR10 );
VAR5 VAR8 (VAR3, VAR12, VAR2, VAR6);
buf VAR9 (VAR1 , VAR3 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_1.functional.pp.v | 1,416 | module MODULE1( VAR15, VAR1, VAR8, VAR12, VAR14, VAR5, VAR13 );
input VAR14, VAR12, VAR8, VAR15;
inout VAR5, VAR13;
output VAR1;
wire VAR4;
not VAR10( VAR4, VAR14 );
wire VAR3;
not VAR9( VAR3, VAR12 );
wire VAR2;
not VAR16( VAR2, VAR8 );
wire VAR6;
not VAR11( VAR6, VAR15 );
or VAR7( VAR1, VAR4, VAR3, VAR2, VAR6 );
endm... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/channel.v | 21,216 | module MODULE1
parameter VAR42 = 128,
parameter VAR62 = 2, parameter VAR23 = VAR25((VAR42/32)+1)
)
(
input VAR7,
input VAR67,
input [2:0] VAR33, input [2:0] VAR54,
input [31:0] VAR41, input [VAR42-1:0] VAR14,
output VAR55, input VAR64, input VAR58, input VAR27,
output VAR53, input VAR6, input VAR60, input VAR28,
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.functional.pp.v | 2,056 | module MODULE1 (
VAR5 ,
VAR13,
VAR3 ,
VAR1 ,
VAR17 ,
VAR16 ,
VAR11 ,
VAR9
);
output VAR5 ;
input VAR13;
input VAR3 ;
input VAR1 ;
input VAR17 ;
input VAR16 ;
input VAR11 ;
input VAR9 ;
wire VAR15 ;
wire VAR6;
wire VAR8 ;
not VAR10 (VAR15 , VAR13 );
not VAR2 (VAR6, VAR1 );
VAR7 VAR14 VAR4 (VAR8 , VAR3, VAR6, VAR15, , VA... | apache-2.0 |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/Top_Level.v | 10,479 | module MODULE1
(
input wire VAR88, input wire VAR57, input wire [7:0] VAR51, input wire VAR37, input wire VAR39, input wire VAR76, output wire [7:0] VAR50, output wire [7:0] VAR19, output wire [7:0] VAR29, output wire VAR71, output wire VAR35, output wire VAR64, output wire VAR27, output wire VAR89, output wire VAR43, ... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/bit_capture_data.v | 2,385 | module MODULE1(
input VAR6,
input VAR9,
input VAR13,
input VAR5,
output reg VAR14, output reg VAR7, output reg VAR3, output reg VAR10, output reg VAR4, output reg VAR2, output reg VAR8, output reg VAR12, output reg VAR1, output reg VAR11 );
always@(posedge VAR9 or negedge VAR13)
begin
if(!VAR13)
begin
VAR7 <= 1'b0;
VAR... | gpl-3.0 |
SiLab-Bonn/fe65_p2 | firmware/src/no_tdc/fe65p2_mio.v | 12,268 | module MODULE1 (
input wire VAR3,
inout wire [7:0] VAR95,
input wire [15:0] VAR43,
input wire VAR75,
input wire VAR113,
inout wire [7:0] VAR36,
input wire VAR5,
input wire VAR71,
input wire VAR61,
output wire [19:0] VAR77,
inout wire [15:0] VAR162,
output wire VAR1,
output wire VAR50,
output wire VAR18,
output wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dlatch_p/sky130_fd_sc_ls__udp_dlatch_p.symbol.v | 1,294 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR3
);
endmodule | apache-2.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/channelizer/checkpoint/sysgen/channelizer_entity_declarations.v | 44,868 | module MODULE2 (
output [(8 - 1):0] VAR5,
input clk,
input VAR4,
input VAR2);
assign VAR5 = 8'b00000001;
endmodule
module MODULE1 (
input [(1 - 1):0] VAR6,
output [(1 - 1):0] VAR5,
input clk,
input VAR4,
input VAR2);
wire VAR3;
reg VAR1[0:(1 - 1)];
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin... | gpl-3.0 |
natsutan/NPU | fpga_implement/npu8/npu8.cache/ip/b68c3a7a323700c9/mul17_16_stub.v | 1,311 | module MODULE1(VAR3, VAR4, VAR1, VAR2)
;
input VAR3;
input [16:0]VAR4;
input [15:0]VAR1;
output [16:0]VAR2;
endmodule | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1.behavioral.pp.v | 1,153 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
jotego/jt12 | hdl/jt12_logsin.v | 8,284 | module MODULE1
(
input [7:0] addr,
input clk,
input VAR2,
output reg [11:0] VAR3
);
reg [11:0] VAR1[255:0]; | gpl-3.0 |
monotone-RK/FACE | IEICE-Trans/data_compression/8-way_2-tree/src/riffa/sg_list_reader_32.v | 5,594 | module MODULE1 #(
parameter VAR7 = 9'd32
)
(
input VAR20,
input VAR9,
input [VAR7-1:0] VAR21, input VAR6, output VAR10,
output VAR23, output VAR2, input VAR8, output [63:0] VAR14, output [31:0] VAR11 );
reg [2:0] VAR1=VAR12, VAR1=VAR12;
reg [2:0] VAR18=VAR5, VAR18=VAR5;
reg [VAR7-1:0] VAR25={VAR7{1'd0}}, VAR25={VAR7{1'... | mit |
hoglet67/CoPro6502 | src/m32632/M32632.v | 10,897 | module MODULE1( VAR34, VAR99, VAR86, VAR61, VAR138, VAR104, VAR148, VAR45, VAR8,
VAR110, VAR42, VAR14, VAR47, VAR63, VAR101, VAR139,
VAR69, VAR51, VAR87, VAR97, VAR22, VAR90, VAR125, VAR140, VAR36,
VAR124, VAR53, VAR143, VAR122, VAR55, VAR38,
VAR144, VAR30, VAR142, VAR134,
VAR111, VAR123, VAR48, VAR92, VAR32 );
input V... | gpl-3.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_register.v | 10,315 | module MODULE1 #
(
parameter VAR28 = 8,
parameter VAR36 = (VAR28>8),
parameter VAR26 = (VAR28/8),
parameter VAR20 = 1,
parameter VAR48 = 0,
parameter VAR22 = 8,
parameter VAR3 = 0,
parameter VAR2 = 8,
parameter VAR47 = 1,
parameter VAR4 = 1,
parameter VAR8 = 2
)
(
input wire clk,
input wire rst,
input wire [VAR28-1:0] ... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/1af391c58f596ed5/zqynq_lab_1_design_axi_bram_ctrl_0_0_stub.v | 4,101 | module MODULE1(VAR36, VAR5, VAR13,
VAR26, VAR46, VAR18, VAR40, VAR21, VAR25,
VAR7, VAR29, VAR20, VAR4, VAR22, VAR43,
VAR37, VAR48, VAR34, VAR39, VAR10, VAR19, VAR32,
VAR41, VAR45, VAR24, VAR38, VAR47, VAR11,
VAR2, VAR3, VAR51, VAR49, VAR28, VAR8, VAR35,
VAR1, VAR17, VAR27, VAR30, VAR6, VAR42, VAR12,
VAR14, VAR31, VAR44... | mit |
AnttiLukats/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/nandc_brams.v | 1,354 | module MODULE1 #(
parameter VAR5 = 32,
parameter VAR4 = 10,
parameter VAR11 = 517
) (
input wire VAR3,
input wire VAR14,
input wire [VAR4-1:0] VAR7,
input wire [VAR5-1:0] VAR1,
output reg [VAR5-1:0] VAR10,
input wire VAR8,
input wire VAR13,
input wire [VAR4-1:0] VAR9,
input wire [VAR5-1:0] VAR2,
output reg [VAR5-1:0] V... | apache-2.0 |
boylansr/Prop_Muse | P1V/P8X32A_Emulation/P8X32A_DE0_Nano/hub_mem.v | 2,749 | module MODULE1
(
input VAR13,
input VAR9,
input VAR7,
input [3:0] VAR19,
input [13:0] VAR16,
input [31:0] VAR12,
output [31:0] VAR17
);
reg [7:0] VAR6 [8191:0];
reg [7:0] VAR14 [8191:0];
reg [7:0] VAR1 [8191:0];
reg [7:0] VAR8 [8191:0];
reg [7:0] VAR3;
reg [7:0] VAR11;
reg [7:0] VAR5;
reg [7:0] VAR2;
always @(posedge V... | gpl-3.0 |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/water_let_mode.v | 2,812 | module MODULE1
(
input VAR4,
input VAR6,
input [31:0]clk,
input VAR3,
input VAR11,
input [2:0]VAR12,
output reg VAR5,
output reg VAR8,
output reg [2:0]VAR9
);
reg VAR10;
wire [(VAR2-1):0]VAR7;
wire VAR1; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.behavioral.pp.v | 2,031 | module MODULE1 (
VAR2 ,
VAR11 ,
VAR14,
VAR17,
VAR10,
VAR15 ,
VAR3
);
output VAR2 ;
input VAR11 ;
input VAR14;
input VAR17;
input VAR10;
input VAR15 ;
input VAR3 ;
reg VAR6 ;
wire VAR12 ;
wire VAR1;
wire VAR5 ;
wire VAR16 ;
VAR13 VAR4 (VAR12 , VAR5, VAR1, VAR6, VAR17, VAR10);
buf VAR8 (VAR16, VAR12 );
VAR7 VAR9 (VAR2 , ... | apache-2.0 |
kevintownsend/R3 | coregen/fifo_fwft_64x512.v | 26,099 | module MODULE2 (
clk, VAR50, rst, VAR91, VAR129, VAR46, VAR29, dout, din
);
input clk;
input VAR50;
input rst;
output VAR91;
input VAR129;
output VAR46;
output VAR29;
output [63 : 0] dout;
input [63 : 0] din;
wire VAR21;
wire VAR56;
wire \VAR130/VAR119/VAR49.VAR110/VAR118.VAR160/VAR149/VAR47 ;
wire \VAR130/VAR119/VAR49... | mit |
jotego/jt12 | hdl/jt12_rst.v | 1,028 | module MODULE1(
input rst,
input clk,
output reg VAR2
);
reg VAR1;
always @(negedge clk)
if( rst ) begin
VAR1 <= 1'b0;
VAR2 <= 1'b0;
end else begin
{ VAR2, VAR1 } <= { VAR1, 1'b1 };
end
endmodule MODULE1 | gpl-3.0 |
asicguy/gplgpu | hdl/de_temp/ded_funcol.v | 4,469 | module MODULE1
(
input VAR23, input [1:0] VAR14, input [1:0] VAR22, input VAR15,
VAR6,
VAR24,
input VAR27,
input [31:0] VAR19, input [31:0] VAR7, input VAR13,
input [(VAR10<<3)-1:0] VAR20, VAR12 VAR25 input [6:0] VAR1,
input [(VAR10<<3)-1:0] VAR16,VAR21,
output [(VAR10<<3)-1:0] VAR18, output [VAR10-1:0] VAR5, output [V... | gpl-3.0 |
AdriaanSwan/Verilog-Quadrature-Decoder-I2C-Slave | Verilog/I2CSlave.v | 3,127 | module MODULE1(VAR28, VAR18, VAR4, VAR8, VAR17, VAR6, VAR15, VAR14, VAR7);
input VAR28;
input VAR18;
inout VAR4;
input[15:0] VAR8;
input[15:0] VAR17;
input[15:0] VAR6;
input[15:0] VAR15;
output[7:0] VAR14;
output[1:0] VAR7;
parameter VAR9 = 7'b1110010;
reg[3:0] VAR3 = 4'b1000;
reg[15:0] VAR21 [0:3];
reg [2:0] VAR19 = 3... | gpl-2.0 |
zYeoman/32BIT-MIPS-CPU | pipeline/UART.v | 4,534 | module MODULE1(clk,VAR10,VAR6,VAR2,VAR11,VAR7,rst);
input clk; input rst;
input [7:0]VAR6; input VAR2; output reg VAR10; output reg VAR11; output reg VAR7;
wire VAR9;
VAR3 VAR5(.clk(clk),
.VAR9(VAR9),
.VAR4(~VAR11),
.rst(rst));
reg [3:0]VAR1;
reg [7:0]VAR8;
begin
begin | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.symbol.v | 1,282 | module MODULE1 (
input VAR7,
input VAR6,
input VAR4,
input VAR9,
output VAR3
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_switches.v | 1,841 | module MODULE1 (
address,
clk,
VAR5,
VAR1,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR5;
input VAR1;
wire VAR6;
wire [ 7: 0] VAR2;
wire [ 7: 0] VAR4;
reg [ 31: 0] VAR3;
assign VAR6 = 1;
assign VAR4 = {8 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR1)
begin
if (VAR1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_2.functional.v | 1,734 | module MODULE1( VAR10, VAR7, VAR19, VAR21, VAR20, VAR9, VAR11 );
input VAR21, VAR19, VAR10, VAR20, VAR7, VAR11;
output VAR9;
not VAR4( VAR16, VAR20 );
wire VAR6;
not VAR18( VAR6, VAR19 );
wire VAR26;
not VAR2( VAR26, VAR10 );
wire VAR15;
and VAR13( VAR15, VAR6, VAR26 );
wire VAR5;
not VAR24( VAR5, VAR7 );
wire VAR12;
a... | apache-2.0 |
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