repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
omicronns/studies-sys-rek | lab3/or_gate/src/or_gate.v | 4,002 | module MODULE1
(
input [9:0] VAR3,
output VAR1
);
wire [4095:0]VAR2=4096'hf5ffe6ecf6c7fd7c7577ec5e5f46e55ef474ee66444ff77d756475fde5d76f6fd7ced54c7f67476cdf5fed477ff4644fdf4eee4e476f776665e4fefd7ee5f4f5def75ce5fe4d75ffcc7f47ffcfcffde657cd5475dfc566f66d7cdc675cd655cdf46fd476f7cdddd7fe4dd7e4f545d4c467ee457c5f654664cc6f45... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor4bb/sky130_fd_sc_hs__nor4bb_4.v | 2,198 | module MODULE2 (
VAR5 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR7,
VAR3
);
output VAR5 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR7;
input VAR3;
VAR9 VAR2 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR5 ,
VAR1 ,
VAR8 ,
VAR6,
VAR4
... | apache-2.0 |
yanhongwang/ColorImage | CTC/CTC.v | 47,755 | module MODULE1
(
input VAR40,
input VAR44,
input[ VAR26 - 1 : 0 ]VAR32,
input[ VAR26 - 1 : 0 ]VAR51,
input[ VAR26 - 1 : 0 ]VAR1,
output[ VAR26 - 1 : 0 ]VAR37,
output[ VAR26 - 1 : 0 ]VAR25,
output[ VAR26 - 1 : 0 ]VAR20
);
reg[ VAR23 - 1 : 0 ]VAR18;
reg[ VAR23 - 1 : 0 ]VAR53;
reg[ VAR23 - 1 : 0 ]VAR34;
reg[ VAR23 - 1 : 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3b/sky130_fd_sc_hs__or3b.behavioral.v | 1,872 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR6 ,
VAR7 ,
VAR8,
VAR12
);
output VAR5 ;
input VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR8;
input VAR12;
wire VAR1 ;
wire VAR3 ;
wire VAR10;
not VAR13 (VAR1 , VAR7 );
or VAR4 (VAR3 , VAR6, VAR9, VAR1 );
VAR2 VAR14 (VAR10, VAR3, VAR8, VAR12);
buf VAR11 (VAR5 , VAR10 );
endmodule | apache-2.0 |
codustry/cuckoo | FPGA - Verilog HDL/alarm.v | 1,327 | module MODULE1(
output [3:0] VAR5, VAR10, VAR15, VAR6,
input VAR1, VAR3, VAR14
);
wire VAR2, VAR2, VAR16, VAR16, VAR17, VAR11, VAR7, VAR8;
parameter VAR12 = 4'b0000;
parameter VAR13 = 1'b1;
assign VAR7 = !(VAR15[0] & VAR15[2] & VAR2);
assign VAR8 = !(!VAR3 & VAR10[0] & VAR10[1] & VAR5[1]);
VAR4 VAR9(VAR6, VAR2, VAR12, ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn.pp.symbol.v | 1,419 | module MODULE1 (
input VAR3 ,
output VAR2 ,
output VAR1 ,
input VAR5,
input VAR6 ,
input VAR4 ,
input VAR7
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/inv/gf180mcu_fd_sc_mcu7t5v0__inv_20.behavioral.v | 1,106 | module MODULE1( VAR5, VAR3 );
input VAR5;
output VAR3;
VAR2 VAR4(.VAR5(VAR5),.VAR3(VAR3));
VAR2 VAR1(.VAR5(VAR5),.VAR3(VAR3)); | apache-2.0 |
dnet/proxmark3 | fpga/lo_edge_detect.v | 2,235 | module MODULE1(
input VAR12, input VAR5,
output VAR4, output VAR33,
output VAR15, output VAR3, output VAR22, output VAR14,
input [7:0] VAR16, output VAR32,
output VAR9, input VAR2, output VAR21,
input VAR26,
output VAR24,
input VAR25,
input VAR10, input [7:0] VAR27
);
wire VAR7 = VAR2 & !VAR25;
wire VAR20 = !VAR2 & VAR... | gpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/ptp_clock.v | 8,554 | module MODULE1 #
(
parameter VAR28 = 4,
parameter VAR30 = 4,
parameter VAR44 = 4,
parameter VAR46 = 16,
parameter VAR5 = 4'h6,
parameter VAR37 = 16'h6666,
parameter VAR24 = 1,
parameter VAR26 = 4'h0,
parameter VAR7 = 16'h0002,
parameter VAR49 = 16'h0005
)
(
input wire clk,
input wire rst,
input wire [95:0] VAR11,
input... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/s3esk_mini_top.v | 15,442 | module MODULE1 (
input clk,
input rst,
output VAR33,
input VAR26,
input VAR24,
input VAR325,
input VAR201,
input VAR334,
output VAR117
);
wire [31:0] VAR49;
wire [31:0] VAR340;
wire [31:0] VAR17;
wire [3:0] VAR349;
wire VAR61;
wire VAR178;
wire VAR10;
wire VAR371;
wire VAR302;
wire VAR165;
wire [3:0] VAR58;
wire [1:0] ... | apache-2.0 |
ptracton/wb_soc_template | rtl/ZIP/rtl/zipcpu.v | 58,905 | module MODULE1(VAR41, VAR177, VAR145,
VAR236, VAR173, VAR132, VAR206, VAR234,
VAR178, VAR279, VAR50,
VAR171,
VAR238, VAR37,
VAR232, VAR97,
VAR33, VAR82, VAR104, VAR272,
VAR205, VAR146, VAR229,
VAR271,
VAR101, VAR114, VAR144
, VAR257
);
parameter [31:0] VAR29=32'h0100000;
parameter VAR103=30,
VAR287=8;
parameter VAR259 ... | mit |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/cnorm.v | 5,181 | module MODULE1 ( VAR14 ,VAR3 ,VAR13 ,VAR9 ,VAR8 ,VAR6 ,VAR5 ,VAR1 ,VAR10 ,VAR12 );
output VAR5 ;
reg VAR5 ;
output VAR1 ;
reg VAR1 ;
output [VAR11+1:0] VAR10 ;
wire [VAR11+1:0] VAR10 ;
output [VAR11+1:0] VAR12 ;
wire [VAR11+1:0] VAR12 ;
input VAR14 ;
wire VAR14 ;
input VAR3 ;
wire VAR3 ;
input VAR13 ;
wire VAR13 ;
inpu... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_src1_data_stream_2_V.v | 3,990 | module MODULE1
VAR10 = "VAR25",
VAR27 = 8,
VAR28 = 15,
VAR9 = 20000
)
(
input wire clk,
input wire reset,
output wire VAR26,
input wire VAR21,
input wire VAR15,
input wire [VAR27-1:0] VAR24,
output wire VAR1,
input wire VAR3,
input wire VAR5,
output wire [VAR27-1:0] VAR7
);
reg [VAR27-1:0] VAR16[0:VAR9-1];
reg [VAR27-1... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/nfc-substrate/tiger4_nfc_substrate-1.0.0/DCFIFO_36x16_DR.v | 2,758 | module MODULE1
(
input VAR5 ,
input VAR10 ,
input [35:0] VAR16 ,
input VAR1 ,
output VAR15 ,
input VAR6 ,
input VAR11 ,
output [35:0] VAR12 ,
input VAR20 ,
output VAR8
);
VAR2
VAR17
(
.VAR13 (VAR5 ),
.VAR4 (VAR10 ),
.din (VAR16 ),
.VAR19 (VAR1 ),
.VAR9 (VAR15 ),
.VAR3 (VAR6 ),
.VAR18 (VAR11 ),
.dout (VAR12 ),
.VAR14 (V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor3/sky130_fd_sc_lp__xor3.blackbox.v | 1,289 | module MODULE1 (
VAR3,
VAR4,
VAR1,
VAR8
);
output VAR3;
input VAR4;
input VAR1;
input VAR8;
supply1 VAR5;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
SymbiFlow/prjxray | fuzzers/005-tilegrid/top.v | 2,339 | module MODULE2(input clk, VAR4, [VAR3-1:0] VAR14, output do);
parameter integer VAR3 = VAR19;
parameter integer VAR43 = VAR34 + VAR41;
wire [VAR3-1:0] VAR22;
genvar VAR6;
generate
for (VAR6 = 0; VAR6 < VAR19; VAR6 = VAR6+1) begin:VAR37
VAR16 VAR1(.VAR38(VAR14[VAR6]), .VAR20(VAR22[VAR6]));
end
endgenerate
reg [VAR3-1:0]... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s.symbol.v | 1,358 | module MODULE1 (
input VAR1,
output VAR6
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25.symbol.v | 1,356 | module MODULE1 (
input VAR1,
output VAR5
);
supply1 VAR4;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuflp/sky130_fd_sc_lp__clkbuflp.functional.v | 1,270 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
wire VAR5;
buf VAR4 (VAR5, VAR2 );
buf VAR3 (VAR1 , VAR5 );
endmodule | apache-2.0 |
mzakharo/usb-de2-fpga | support/DE2_NIOS_DEVICE_LED/HW/epcs_controller.v | 18,002 | module MODULE1 (
VAR4,
clk,
VAR74,
VAR17,
VAR78,
VAR54,
VAR58,
VAR93,
VAR86,
VAR5,
VAR51,
VAR66,
VAR7,
VAR40,
irq,
VAR64
)
;
output VAR86;
output VAR5;
output VAR51;
output [ 15: 0] VAR66;
output VAR7;
output VAR40;
output irq;
output VAR64;
input VAR4;
input clk;
input [ 15: 0] VAR74;
input VAR17;
input [ 2: 0] VAR78;... | gpl-3.0 |
aap/pdp6 | verilog/memory.v | 1,755 | module MODULE2(
VAR17, VAR4,
VAR10, VAR6, VAR5, VAR1,
VAR11, VAR2
);
input wire VAR17;
input wire VAR4;
input wire [17:0] VAR10;
input wire VAR6;
input wire VAR5;
input wire [35:0] VAR1;
output wire [35:0] VAR11;
output wire VAR2;
reg [35:0] VAR9[0:'o40000-1];
wire VAR3 = VAR10[17:14] == 0;
wire [13:0] addr = VAR10[13:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o211ai/sky130_fd_sc_hd__o211ai.functional.v | 1,468 | module MODULE1 (
VAR4 ,
VAR9,
VAR6,
VAR3,
VAR5
);
output VAR4 ;
input VAR9;
input VAR6;
input VAR3;
input VAR5;
wire VAR2 ;
wire VAR7;
or VAR1 (VAR2 , VAR6, VAR9 );
nand VAR8 (VAR7, VAR5, VAR2, VAR3);
buf VAR10 (VAR4 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux4/sky130_fd_sc_hvl__mux4.functional.v | 1,600 | module MODULE1 (
VAR5 ,
VAR4,
VAR3,
VAR10,
VAR11,
VAR7,
VAR8
);
output VAR5 ;
input VAR4;
input VAR3;
input VAR10;
input VAR11;
input VAR7;
input VAR8;
wire VAR1;
VAR6 VAR2 (VAR1, VAR4, VAR3, VAR10, VAR11, VAR7, VAR8);
buf VAR9 (VAR5 , VAR1 );
endmodule | apache-2.0 |
vancemiller/verilog-stopwatch | fsm_template.v | 2,080 | module MODULE1(
input clk,
input VAR2, input [VAR12-1:0] VAR7, output [VAR5-1:0] VAR6 );
reg [VAR9-1:0] state = ??; reg [VAR9-1:0] VAR10; reg [VAR5-1:0] VAR6;
parameter VAR13 = ??, VAR1 = ??, VAR4 = ??, ... VAR3.;
always @(posedge clk) if (VAR2 == 1) state <= VAR8??;
else state <= VAR10;
always @ case (state)
VAR1: VAR... | mit |
zeruniverse/Multiple-cycle_CPU | ISE project/mccu.v | 5,929 | module MODULE1 (VAR11, VAR26, VAR48, VAR46, VAR29, VAR4, VAR30, VAR36, VAR44, VAR9, VAR39, VAR5, VAR10, VAR25,VAR38, VAR8, VAR43, VAR6, VAR27, state);
input [5:0] VAR11, VAR26;
input VAR48, VAR46, VAR29;
output reg VAR4, VAR30, VAR36, VAR44, VAR9, VAR39, VAR5;
output reg [3:0] VAR10;
output reg [1:0] VAR8, VAR43;
outpu... | gpl-3.0 |
benreynwar/fpga-sdrlib | verilog/fft/stage_to_out.v | 1,866 | module MODULE1
parameter VAR8 = 8,
parameter VAR2 = 3,
parameter VAR13 = 32,
parameter VAR16 = 1
)
(
input wire clk,
input wire VAR15,
input wire VAR9,
output reg [VAR2-1:0] addr,
input wire [VAR13-1:0] VAR14,
output reg VAR3,
input wire VAR4,
input wire [VAR16-1:0] VAR5,
output reg VAR7,
output reg [VAR13-1:0] VAR1,
o... | mit |
PiJoules/Zybo-Vision-Processing | hdmi_passthrough_720p.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v | 4,029 | module MODULE1
(
input VAR3,
output VAR1,
input reset,
output VAR5
);
VAR4 VAR2
(
.VAR3(VAR3),
.VAR1(VAR1),
.reset(reset),
.VAR5(VAR5)
);
endmodule | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50.blackbox.v | 1,288 | module MODULE1 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_mclk_txrx.v | 2,054 | module MODULE1(
out,
VAR8,
VAR9, VAR5, VAR7, VAR3, VAR6, VAR4, VAR2
);
input [7:0] VAR9; input VAR2; input VAR5; input [8:1] VAR7; input [8:1] VAR3; input VAR6; input VAR4; inout VAR8;
output out;
assign VAR8 = VAR4 ? VAR6 : 1'VAR1;
assign out = VAR8;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_pg/sky130_fd_sc_hs__udp_dff_pr_pp_pg.blackbox.v | 1,357 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR5,
VAR6 ,
VAR4
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR5;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6d8f288943408fbb/zqynq_lab_1_design_rst_ps7_0_100M_0_stub.v | 1,895 | module MODULE1(VAR8, VAR2, VAR1,
VAR6, VAR5, VAR7, VAR3, VAR10,
VAR9, VAR4)
;
input VAR8;
input VAR2;
input VAR1;
input VAR6;
input VAR5;
output VAR7;
output [0:0]VAR3;
output [0:0]VAR10;
output [0:0]VAR9;
output [0:0]VAR4;
endmodule | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/fanout_splitter_stall_free.v | 2,143 | module MODULE1(VAR12, VAR13, VAR10, VAR9, VAR7, VAR3, VAR5, VAR4);
parameter VAR8 = 32;
parameter VAR6 = 2;
parameter VAR2 = 0;
parameter VAR11 = 0;
input VAR12, VAR13;
input [VAR8-1:0] VAR10;
input VAR9;
output reg VAR7;
output reg [VAR8-1:0] VAR3;
input [VAR6-1:0] VAR5;
output reg [VAR6-1:0] VAR4;
generate
if (VAR11)... | mit |
ultraembedded/riscv | core/riscv/riscv_csr_regfile.v | 22,743 | module MODULE1
parameter VAR78 = 1,
parameter VAR10 = 0
)
(
input VAR43
,input VAR79
,input VAR129
,input VAR104
,input [31:0] VAR72
,input [31:0] VAR12
,input [5:0] VAR23
,input [31:0] VAR68
,input [31:0] VAR100
,input VAR31
,input [11:0] VAR76
,output [31:0] VAR61
,input [11:0] VAR32
,input [31:0] VAR73
,output VAR30... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand2/gf180mcu_fd_sc_mcu7t5v0__nand2_4.behavioral.pp.v | 1,259 | module MODULE1( VAR2, VAR6, VAR5, VAR8, VAR1 );
input VAR2, VAR6;
inout VAR8, VAR1;
output VAR5;
VAR3 VAR4(.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1));
VAR3 VAR7(.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfxbp/sky130_fd_sc_lp__dfxbp.pp.symbol.v | 1,336 | module MODULE1 (
input VAR8 ,
output VAR6 ,
output VAR3 ,
input VAR4 ,
input VAR1 ,
input VAR2,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
P3Stor/P3Stor | pcie/IP core/pcie_command_rec_fifo.v | 13,657 | module MODULE1(
rst,
VAR170,
VAR202,
din,
VAR394,
VAR191,
dout,
VAR73,
VAR111,
VAR231,
VAR368,
VAR255,
VAR33
);
input rst;
input VAR170;
input VAR202;
input [127 : 0] din;
input VAR394;
input VAR191;
output [127 : 0] dout;
output VAR73;
output VAR111;
output VAR231;
output VAR368;
output [8 : 0] VAR255;
output [8 : 0] ... | gpl-2.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/image_to_block_fifo.v | 2,194 | module MODULE1 #(
parameter VAR25 = 9
)(
input clk,
input rst,
input VAR13,
input VAR1,
input VAR18,
input VAR4,
input VAR9,
input [2:0] VAR3,
input [2:0] VAR34,
input [1:0] VAR19,
output VAR2,
input VAR16,
input VAR8,
output [24:0] VAR12,
output [23:0] VAR17
);
wire VAR30;
reg VAR11;
wire [23:0] VAR35;
reg VAR36;
reg ... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pll/niosii/synthesis/submodules/altera_std_synchronizer_nocut.v | 4,856 | module MODULE1 (
clk,
VAR1,
din,
dout
);
parameter VAR2 = 3;
input clk;
input VAR1;
input din;
output dout;
reg VAR4;
reg [VAR2-2:0] VAR3; | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4b/sky130_fd_sc_hd__nand4b.behavioral.v | 1,528 | module MODULE1 (
VAR7 ,
VAR8,
VAR11 ,
VAR10 ,
VAR4
);
output VAR7 ;
input VAR8;
input VAR11 ;
input VAR10 ;
input VAR4 ;
supply1 VAR14;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR12 ;
wire VAR13 ;
wire VAR6;
not VAR5 (VAR13 , VAR8 );
nand VAR3 (VAR6, VAR4, VAR10, VAR11, VAR13);
buf VAR2 (VAR7 , VAR6 );
endmodule | apache-2.0 |
DSDL2016/project2 | source/synthesizer/I2C_AV_Config.v | 4,735 | module MODULE1 ( VAR12,
VAR7,
VAR27,
VAR17,
VAR16 );
input VAR12;
input VAR7;
output VAR27;
output VAR17;
inout VAR16;
reg [15:0] VAR6;
reg [23:0] VAR22;
reg VAR26;
reg VAR10;
wire VAR23;
wire VAR15;
reg [15:0] VAR37;
reg [5:0] VAR31;
reg [3:0] VAR35;
reg VAR27;
parameter VAR4 = 50000000; parameter VAR3 = 20000; parame... | mit |
unihd-cag/openhmc | rtl/hmc_controller/rx/rx_descrambler.v | 6,700 | module MODULE1 #(
parameter VAR11=16,
parameter VAR6=1
)
(
input wire clk,
input wire VAR9,
input wire VAR8,
input wire VAR4,
output reg VAR2,
input wire [VAR11-1:0] VAR13,
output reg [VAR11-1:0] VAR3
);
reg [14:0] VAR1; wire [14:0] VAR12; wire [14:0] VAR7 [VAR11-1:0]; wire [14:0] VAR5;
wire [VAR11-1:0] VAR10;
generate... | lgpl-3.0 |
SymbiFlow/fpga-tool-perf | third_party/ibex/ibex_prefetch_buffer.v | 5,499 | module MODULE1 (
VAR50,
VAR27,
VAR61,
VAR58,
VAR10,
VAR13,
VAR2,
VAR30,
VAR55,
VAR53,
VAR41,
VAR9,
VAR14,
VAR62,
VAR57,
VAR60,
VAR32,
VAR5
);
input wire VAR50;
input wire VAR27;
input wire VAR61;
input wire VAR58;
input wire [31:0] VAR10;
input wire VAR13;
output wire VAR2;
output wire [31:0] VAR30;
output wire [31:0] ... | isc |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_efc/rtl/pad_efc.v | 1,567 | module MODULE1 (
VAR2, VAR1
);
inout VAR2;
inout VAR1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hs__udp_dff_nsr_pp_pg_n.blackbox.v | 1,628 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR8,
VAR5 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR8;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
merckhung/zet | cores/vga/rtl/fml/vga_dac_regs_fml.v | 2,363 | module MODULE1 (
input clk,
input [7:0] VAR1,
output reg [3:0] VAR13,
output reg [3:0] VAR10,
output reg [3:0] VAR5,
input write,
input [1:0] VAR11,
input [7:0] VAR8,
output reg [3:0] VAR9,
input [1:0] VAR4,
input [7:0] VAR3,
input [3:0] VAR2
);
reg [3:0] VAR6 [0:255];
reg [3:0] VAR7 [0:255];
reg [3:0] VAR12 [0:255];
a... | gpl-3.0 |
ShepardSiegel/ocpi | rtl/mkFrameGate8B.v | 56,326 | module MODULE1(VAR144,
VAR239,
VAR180,
VAR28,
VAR215,
VAR197,
VAR94,
VAR203,
VAR156,
VAR45,
VAR357,
VAR131,
VAR63,
VAR93,
VAR41,
VAR250,
VAR82,
VAR3,
VAR339,
VAR306,
VAR8,
VAR242,
VAR13,
VAR290,
VAR50,
VAR157,
VAR51,
VAR346,
VAR212,
VAR85,
VAR37,
VAR230);
parameter [31 : 0] VAR323 = 32'b0;
parameter [0 : 0] VAR252 = 1'... | lgpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/Tiger4SharedKES_v1_0_0/8069a058/src/d_KES_PE_DC_2MAXodr.v | 4,509 | module MODULE1 (
input wire VAR6,
input wire VAR18,
input wire VAR19,
input wire VAR17,
input wire [VAR20-1:0] VAR21,
input wire [VAR20-1:0] VAR13,
output wire [VAR20-1:0] VAR22
);
parameter [11:0] VAR5 = 12'b000000000000;
parameter [11:0] VAR8 = 12'b000000000001;
parameter VAR16 = 2'b01; parameter VAR2 = 2'b10;
reg [1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.functional.pp.v | 1,712 | module MODULE1 (
VAR11,
VAR2,
VAR1 ,
VAR7 ,
VAR6
);
input VAR11;
input VAR2;
output VAR1 ;
input VAR7 ;
input VAR6 ;
wire VAR10 ;
wire VAR5;
xor VAR3 (VAR10 , VAR6, VAR7 );
VAR9 VAR4 (VAR5, VAR10, VAR11, VAR2);
buf VAR8 (VAR1 , VAR5 );
endmodule | apache-2.0 |
petrmikheev/miksys | verilog/RAM8192x32_2RW_bb.v | 9,080 | module MODULE1 (
VAR10,
VAR11,
VAR5,
VAR8,
VAR6,
VAR4,
VAR1,
VAR2,
VAR9,
VAR3,
VAR7);
input [12:0] VAR10;
input [12:0] VAR11;
input [3:0] VAR5;
input [3:0] VAR8;
input VAR6;
input [31:0] VAR4;
input [31:0] VAR1;
input VAR2;
input VAR9;
output [31:0] VAR3;
output [31:0] VAR7;
tri1 [3:0] VAR5;
tri1 [3:0] VAR8;
tri1 VAR6;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3_1.v | 2,164 | module MODULE2 (
VAR10 ,
VAR9 ,
VAR1 ,
VAR3 ,
VAR6,
VAR7,
VAR5 ,
VAR2
);
output VAR10 ;
input VAR9 ;
input VAR1 ;
input VAR3 ;
input VAR6;
input VAR7;
input VAR5 ;
input VAR2 ;
VAR4 VAR8 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.symbol.v | 1,266 | module MODULE1 (
input VAR1,
output VAR3
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Jbag/Uart_zhixin | design/Bps_select.v | 2,489 | module MODULE1(
input clk, input VAR3, input en, output reg VAR1, output reg [3:0] VAR6 );
parameter VAR5 = 13'd5207, VAR2 = 13'd2603;
reg flag;
always @(posedge clk or negedge VAR3)
if(!VAR3)
flag <= 0;
else
if(en)
flag <= 1;
else
if(VAR6 == 4'd10) flag <= 0;
reg [12:0] VAR4;
always @(posedge clk or negedge VAR3)
if(!... | gpl-3.0 |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_LevelGateway.v | 2,127 | module MODULE1(
input VAR7,
input reset,
input VAR5,
output VAR11,
input VAR10,
input VAR4
);
reg VAR1;
reg [31:0] VAR8;
wire VAR12;
wire VAR6;
wire VAR2;
wire VAR3;
wire VAR9;
assign VAR11 = VAR9;
assign VAR12 = VAR5 & VAR10;
assign VAR6 = VAR12 ? 1'h1 : VAR1;
assign VAR2 = VAR4 ? 1'h0 : VAR6;
assign VAR3 = VAR1 == 1'... | apache-2.0 |
m-labs/milkymist | cores/tmu2/rtl/tmu2_blend.v | 5,518 | module MODULE1 #(
parameter VAR31 = 26
) (
input VAR92,
input VAR60,
output VAR23,
input VAR100,
output VAR54,
input [VAR31-1-1:0] VAR19,
input [15:0] VAR48,
input [15:0] VAR98,
input [15:0] VAR79,
input [15:0] VAR68,
input [5:0] VAR10,
input [5:0] VAR40,
output VAR83,
input VAR5,
output [VAR31-1-1:0] VAR36,
output [15... | lgpl-3.0 |
davidjabon/AXI-Peripheral-Library | pwm_1.0/hdl/pwm_v1_0_S00_AXI.v | 13,922 | module MODULE1 #
(
parameter integer VAR20 = 32,
parameter integer VAR18 = 4
)
(
output wire VAR26,
input wire VAR25,
input wire VAR14,
input wire [VAR18-1 : 0] VAR34,
input wire [2 : 0] VAR27,
input wire VAR28,
output wire VAR5,
input wire [VAR20-1 : 0] VAR9,
input wire [(VAR20/8)-1 : 0] VAR39,
input wire VAR19,
outpu... | gpl-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_clkgate.v | 1,919 | module MODULE1
(clk, enable, VAR2);
input clk;
input enable;
output VAR2;
wire VAR2;
reg VAR1;
always @(clk, enable)
begin
if(clk == 0)
VAR1 <= enable;
end
assign VAR2 = clk & VAR1;
endmodule | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_AsyncResetRegVec_129.v | 9,922 | module MODULE1(
input VAR155,
input reset,
input [19:0] VAR149,
output [19:0] VAR39,
input VAR137
);
wire VAR59;
wire VAR120;
wire VAR7;
wire VAR153;
wire VAR28;
wire VAR34;
wire VAR144;
wire VAR29;
wire VAR156;
wire VAR71;
wire VAR16;
wire VAR117;
wire VAR143;
wire VAR129;
wire VAR121;
wire VAR157;
wire VAR82;
wire VA... | apache-2.0 |
housq/lc3 | LC3_keyboard_regs.v | 1,058 | module MODULE1(
input clk,
input reset,
input VAR2,
input VAR5,
input [15:0] VAR8,
input [7:0] VAR3,
input VAR4,
output reg[15:0] VAR1,
output reg[15:0] VAR6,
output VAR7
);
always@(posedge clk) if (reset) begin
VAR6<=16'b0;
VAR1<=16'b0;
end
else begin
if(VAR4) begin
VAR1<={8'b0,VAR3};
VAR6[15]<=1'b1;
end else if(VAR5)... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.blackbox.v | 1,204 | module MODULE1 (
VAR3 ,
VAR2,
VAR4,
VAR1
);
output VAR3 ;
input VAR2;
input VAR4;
input VAR1 ;
endmodule | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/SGDMA_dispatcher/csr_block.v | 14,935 | module MODULE1 (
clk,
reset,
VAR6,
VAR16,
VAR7,
VAR8,
VAR37,
VAR36,
VAR18,
VAR19,
VAR15,
VAR41,
VAR5,
VAR43,
VAR47,
VAR21,
VAR9,
VAR32,
VAR44,
VAR22,
VAR1,
VAR25,
VAR26,
VAR45,
VAR28,
VAR34,
VAR49,
VAR14,
VAR23,
VAR46,
VAR40,
VAR48
);
parameter VAR27 = 3;
localparam VAR12 = 3'b001;
input clk;
input reset;
input [31:0] ... | mit |
gtaylormb/opl3_fpga | fpga/modules/clks/ip/clk_gen/clk_gen_clk_wiz.v | 6,616 | module MODULE1
( input VAR68,
output clk,
output VAR15
);
wire VAR64;
wire VAR14;
VAR41 VAR9
(.VAR50 (VAR64),
.VAR22 (VAR68));
wire VAR1;
wire VAR72;
wire VAR60;
wire VAR63;
wire VAR84;
wire VAR23;
wire VAR49;
wire [15:0] VAR58;
wire VAR10;
wire VAR76;
wire VAR19;
wire VAR59;
wire VAR26;
wire VAR77;
wire VAR32;
wire VA... | lgpl-3.0 |
Jawanga/ece385final | finalproject/synthesis/submodules/finalproject_keycode.v | 2,280 | module MODULE1 (
address,
VAR4,
clk,
VAR8,
VAR6,
VAR2,
VAR7,
VAR9
)
;
output [ 7: 0] VAR7;
output [ 31: 0] VAR9;
input [ 1: 0] address;
input VAR4;
input clk;
input VAR8;
input VAR6;
input [ 31: 0] VAR2;
wire VAR3;
reg [ 7: 0] VAR5;
wire [ 7: 0] VAR7;
wire [ 7: 0] VAR1;
wire [ 31: 0] VAR9;
assign VAR3 = 1;
assign VAR1 ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_4.functional.pp.v | 1,184 | module MODULE1( VAR8, VAR14, VAR2, VAR7, VAR3 );
input VAR14, VAR8;
inout VAR7, VAR3;
output VAR2;
wire VAR1;
and VAR11( VAR1, VAR14, VAR8 );
wire VAR5;
not VAR13( VAR5, VAR14 );
wire VAR10;
not VAR6( VAR10, VAR8 );
wire VAR12;
and VAR9( VAR12, VAR5, VAR10 );
or VAR4( VAR2, VAR1, VAR12 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_zed_audio_ctrl_0_0/ip_design_zed_audio_ctrl_0_0_stub.v | 2,399 | module MODULE1(VAR19, VAR20, VAR11, VAR5, VAR21,
VAR7, VAR9, VAR17, VAR16, VAR12, VAR13,
VAR15, VAR3, VAR1, VAR10, VAR23, VAR18,
VAR6, VAR22, VAR8, VAR14, VAR2, VAR4)
;
output VAR19;
output VAR20;
input VAR11;
output VAR5;
input VAR21;
input VAR7;
input [31:0]VAR9;
input VAR17;
input [31:0]VAR16;
input [3:0]VAR12;
inpu... | mit |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/new/clock/clock_100kHz.v | 1,044 | module MODULE1(clk,VAR2,VAR1);
input clk,VAR2;
output reg VAR1;
reg [15:0] counter;
always @ (posedge clk or negedge VAR2)
if (!VAR2)
begin
VAR1 <= 0;
counter <= 0;
end
else
if (counter == 16'd499) begin
VAR1 <= !VAR1;
counter <= 0;
end
else
begin
VAR1 <= VAR1;
counter <= counter + 1;
end
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_pwrgood_pp_p/sky130_fd_sc_hdll__udp_pwrgood_pp_p.blackbox.v | 1,259 | module MODULE1 (
VAR3,
VAR2 ,
VAR1
);
output VAR3;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
rkrajnc/minimig-de1 | rtl/mist/user_io.v | 2,828 | module MODULE1(
input VAR13,
input VAR15,
output reg VAR3,
input VAR6,
input [7:0] VAR22,
output [5:0] VAR12,
output [5:0] VAR9,
output [2:0] VAR14,
output VAR17,
output [1:0] VAR7,
output [7:0] VAR16,
output [1:0] VAR19,
output [1:0] VAR20
);
reg [6:0] VAR10;
reg [7:0] VAR5;
reg [5:0] VAR2;
reg [5:0] VAR8;
reg [5:0] V... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_gmultp2_32x32.v | 6,770 | module MODULE1 ( VAR8, VAR2, VAR3, VAR4, VAR10 );
input [VAR1-1:0] VAR8;
input [VAR1-1:0] VAR2;
input VAR3;
input VAR4;
output [VAR5-1:0] VAR10;
reg [VAR5-1:0] VAR9;
reg [VAR5-1:0] VAR6;
integer VAR11;
integer VAR7;
always @(VAR8)
VAR11 <= VAR8;
always @(VAR2)
VAR7 <= VAR2;
always @(posedge VAR3 or posedge VAR4)
if (VA... | gpl-2.0 |
DreamSourceLab/DSLogic-hdl | src/i2c/i2cSlave.v | 6,002 | module MODULE1 (
clk,
rst,
VAR1,
VAR13,
VAR12,
VAR8,
VAR21,
VAR9
);
input clk;
input rst;
inout VAR1;
input VAR13;
output [7:0] VAR12;
output [7:0] VAR8;
output VAR21;
input [7:0] VAR9;
reg VAR20;
reg VAR17;
reg [VAR15-1:0] VAR16;
reg [VAR15-1:0] VAR28;
reg [VAR4-1:0] VAR26;
reg [VAR18-1:0] VAR22;
reg [1:0] VAR14;
wire... | gpl-2.0 |
GSejas/Karatsuba_FPU | Resultados/CORDIC/CORDIC_Arch3_Vivado/CORDIC_Arch3_Vivado.srcs/sources_1/imports/my_sourcefiles/addsub/FPU_ADD_Substract_PIPELINED.v | 24,860 | module MODULE1
/*#(parameter VAR96 = 32, parameter VAR45 = 8, parameter VAR13 = 23,
parameter VAR171=26, parameter VAR86 = 5)
parameter VAR171 = 55, parameter VAR86 = 6) (
input wire clk,
input wire rst,
input wire VAR114,
input wire [VAR96-1:0] VAR163,
input wire [VAR96-1:0] VAR25,
input wire VAR193,
output wire VAR17... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/10KEYBOARD/Version_01/02 verilog/Touch/MódulosBásicos/teclado2/psdos.v | 1,375 | module MODULE1 ( input VAR6,
input VAR4,
output [7:0] VAR7,
output reg VAR9
);
reg [8:0] VAR2;
reg [7:0] VAR3;
reg [3:0] VAR8;
reg [3:0] VAR1;
reg VAR5;
begin
begin
begin
begin
begin
begin | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/usdrx1/cpld/usdrx1_cpld.v | 4,783 | module MODULE1 (
VAR3,
VAR17,
VAR5,
VAR11,
VAR6,
VAR8,
VAR18,
VAR15,
VAR2,
VAR9,
VAR10,
VAR13,
VAR4,
VAR14
);
input [13:0] VAR3;
input VAR17;
input VAR5;
input VAR11;
inout VAR6;
input VAR8;
input VAR18;
output [13:0] VAR15;
output VAR2;
output VAR9;
output VAR10;
inout VAR13;
output VAR4;
output VAR14;
reg [15:0] VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtp/sky130_fd_sc_hs__dfrtp.symbol.v | 1,359 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR5,
input VAR1
);
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
polysome/hydra | implementation/Top_controller_v2.v | 21,551 | module MODULE1(
clk,
VAR68,
VAR17, VAR147, VAR113,
VAR98, VAR95, VAR40, VAR43, VAR85,
VAR39 ,
VAR139 ,
VAR60 ,
VAR130
);
parameter VAR49 = 31;
parameter VAR157 = 3'd0;
parameter VAR154 = 3'd1;
parameter VAR32 = 3'd2;
parameter VAR56 = 3'd3;
parameter VAR116 = 3'd4;
parameter VAR81 = 3'd5;
parameter VAR121 = 3'd6;
param... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/eio_rx/hdl/eio_rx.v | 13,147 | module MODULE1 (
VAR16, VAR13, VAR99, VAR71, VAR38,
VAR78, VAR60, VAR73,
VAR39, VAR29, reset, VAR52, VAR55, VAR17,
VAR23, VAR37, VAR40, VAR98, VAR79,
VAR33, VAR43, VAR112, VAR120,
VAR48, VAR117, VAR44, VAR81
);
parameter VAR115 = "VAR63";
input VAR39, VAR29; input reset;
input VAR52;
input VAR55, VAR17; input [7:0] VAR... | gpl-3.0 |
bkboggy/MIPS | INSTR_MEM.v | 3,606 | module MODULE1(input clk, input [31:0] addr, output reg [31:0] VAR2);
reg [31:0] VAR1 [128:0];
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai.functional.v | 1,592 | module MODULE1 (
VAR5 ,
VAR6,
VAR10,
VAR13,
VAR1,
VAR11
);
output VAR5 ;
input VAR6;
input VAR10;
input VAR13;
input VAR1;
input VAR11;
wire VAR7 ;
wire VAR8 ;
wire VAR4;
or VAR9 (VAR7 , VAR1, VAR13 );
or VAR2 (VAR8 , VAR10, VAR6 );
nand VAR3 (VAR4, VAR8, VAR7, VAR11);
buf VAR12 (VAR5 , VAR4 );
endmodule | apache-2.0 |
jaechoon2/FPGA-Imaging-Library | InOut/IIC_Ctrl/src/IICctrl.v | 2,445 | module MODULE1
(
input VAR21,
input VAR26,
output VAR29,
inout VAR20
);
parameter VAR6 = 170;
reg [7:0] VAR8;
wire [7:0] VAR12;
reg VAR4;
parameter VAR10 = 25000000;
parameter VAR14 = 10000;
reg [15:0] VAR28;
reg VAR25;
always@(posedge VAR21 or negedge VAR26)
begin
if(!VAR26)
begin
VAR28 <= 0;
VAR25 <= 0;
end
else
begi... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4_2.v | 2,253 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR1 ,
VAR10 ,
VAR5 ,
VAR7,
VAR4,
VAR8 ,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR1 ;
input VAR10 ;
input VAR5 ;
input VAR7;
input VAR4;
input VAR8 ;
input VAR2 ;
VAR3 VAR11 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4/sky130_fd_sc_lp__nor4.blackbox.v | 1,308 | module MODULE1 (
VAR3,
VAR7,
VAR9,
VAR5,
VAR2
);
output VAR3;
input VAR7;
input VAR9;
input VAR5;
input VAR2;
supply1 VAR8;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc.behavioral.pp.v | 2,061 | module MODULE1 (
VAR4 ,
VAR7,
VAR10 ,
VAR13 ,
VAR1 ,
VAR2 ,
VAR5
);
output VAR4 ;
input VAR7;
input VAR10 ;
input VAR13 ;
input VAR1 ;
input VAR2 ;
input VAR5 ;
wire VAR6 ;
wire VAR14 ;
wire VAR12;
not VAR15 (VAR6 , VAR7 );
and VAR11 (VAR14 , VAR6, VAR10 );
VAR9 VAR8 (VAR12, VAR14, VAR13, VAR1, VAR7);
buf VAR3 (VAR4 , ... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/cmp/rtl/rep_jbi_sc0_2.v | 2,844 | module MODULE1(
VAR14, VAR18, VAR3,
VAR15, VAR2,
VAR9, VAR16,
VAR5, VAR11,
VAR12, VAR13, VAR8, VAR17,
VAR1, VAR10, VAR7,
VAR4, VAR6
);
output [31:0] VAR14;
output [31:0] VAR18;
output [6:0] VAR3;
output VAR15;
output VAR2;
output VAR9;
output VAR16;
output VAR5;
output VAR11;
input [31:0] VAR12;
input [31:0] VAR13;
inp... | gpl-2.0 |
kwantam/multiexp-a5gx | ocram/g_ram.v | 11,256 | module MODULE1 (
VAR61,
VAR60,
VAR3,
VAR55,
VAR26,
VAR19,
VAR20,
VAR28,
VAR53,
VAR11,
VAR45,
VAR38);
input VAR61;
input [8:0] VAR60;
input [8:0] VAR3;
input VAR55;
input [31:0] VAR26;
input [31:0] VAR19;
input VAR20;
input VAR28;
input VAR53;
input VAR11;
output [31:0] VAR45;
output [31:0] VAR38;
tri0 VAR61;
tri1 VAR55... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/mem.v | 3,310 | module MODULE1 (
VAR8,
VAR3,
VAR6,
VAR10,
VAR2,
VAR4,
VAR11);
parameter VAR5 = 16;
parameter VAR7 = 5;
localparam VAR12 = VAR5 - 1;
localparam VAR9 = VAR7 - 1;
input VAR8;
input VAR3;
input [VAR9:0] VAR6;
input [VAR12:0] VAR10;
input VAR2;
input [VAR9:0] VAR4;
output [VAR12:0] VAR11;
reg [VAR12:0] VAR1[0:((2**VAR7)-1)]... | mit |
sabertazimi/hust-lab | verilog/labs/lab5/src/shift_out_register.v | 1,336 | module MODULE1
(
input [VAR3:0] VAR1,
input clk,
input VAR4,
input VAR7,
input [(VAR3-1):0] VAR6,
input VAR8,
output [(VAR3-1):0] VAR5,
output VAR2
);
reg [(VAR3-1):0] VAR9;
always @(posedge VAR1[0] or posedge clk) begin
if (VAR1[0]) begin
VAR9 <= VAR1[VAR3:1];
end
else begin
if (VAR4) begin
VAR9 <= VAR6;
end
else if (... | mit |
kyzhai/NUNY | src/hardware/rain.v | 6,344 | module MODULE1 (
address,
VAR45,
VAR13);
input [11:0] address;
input VAR45;
output [11:0] VAR13;
tri1 VAR45;
wire [11:0] VAR42;
wire [11:0] VAR13 = VAR42[11:0];
VAR26 VAR43 (
.VAR28 (address),
.VAR4 (VAR45),
.VAR39 (VAR42),
.VAR17 (1'b0),
.VAR52 (1'b0),
.VAR48 (1'b1),
.VAR6 (1'b0),
.VAR8 (1'b0),
.VAR23 (1'b1),
.VAR10 (... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o22a/sky130_fd_sc_ms__o22a.symbol.v | 1,363 | module MODULE1 (
input VAR3,
input VAR7,
input VAR2,
input VAR6,
output VAR8
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c7ba741286d72229/ip_design_auto_pc_0_stub.v | 4,475 | module MODULE1(VAR29, VAR25, VAR10, VAR27,
VAR46, VAR18, VAR20, VAR6, VAR15, VAR48,
VAR40, VAR1, VAR26, VAR54, VAR42, VAR28, VAR3,
VAR39, VAR43, VAR22, VAR45, VAR51, VAR53, VAR36,
VAR19, VAR21, VAR16, VAR35, VAR12, VAR11,
VAR5, VAR30, VAR44, VAR2, VAR7, VAR4, VAR49,
VAR59, VAR17, VAR38, VAR56, VAR13, VAR57,
VAR37, VAR5... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18.blackbox.v | 1,322 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
supply1 VAR6;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1n/sky130_fd_sc_hd__lpflow_inputiso1n.pp.blackbox.v | 1,427 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR3,
VAR4 ,
VAR6 ,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR1 ;
input VAR3;
input VAR4 ;
input VAR6 ;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrbp/sky130_fd_sc_hvl__dfrbp.functional.pp.v | 2,424 | module MODULE1 (
VAR15 ,
VAR10 ,
VAR19 ,
VAR1 ,
VAR13,
VAR4 ,
VAR9 ,
VAR5 ,
VAR8
);
output VAR15 ;
output VAR10 ;
input VAR19 ;
input VAR1 ;
input VAR13;
input VAR4 ;
input VAR9 ;
input VAR5 ;
input VAR8 ;
wire VAR2 ;
wire VAR6 ;
wire VAR16 ;
wire VAR18;
not VAR17 (VAR6 , VAR13 );
VAR21 VAR12 VAR22 (VAR2 , VAR1, VAR19,... | apache-2.0 |
Murailab-arch/magukara | cores/sfifo/rtl/ram_dp_ar_aw.v | 2,410 | module MODULE1 (
VAR15 , VAR13 , VAR20 , VAR14 , VAR1 , VAR19 , VAR4 , VAR2 , VAR6 , VAR11 );
parameter VAR16 = 8 ;
parameter VAR17 = 8 ;
parameter VAR10 = 1 << VAR17;
input [VAR17-1:0] VAR15 ;
input VAR20 ;
input VAR14 ;
input VAR1 ;
input [VAR17-1:0] VAR19 ;
input VAR2 ;
input VAR6 ;
input VAR11 ;
inout [VAR16-1:0] V... | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_dst_data_stream_2_V.v | 3,017 | module MODULE2 (
clk,
VAR1,
VAR18,
VAR23,
VAR4);
parameter VAR3 = 32'd8;
parameter VAR25 = 32'd1;
parameter VAR19 = 32'd2;
input clk;
input [VAR3-1:0] VAR1;
input VAR18;
input [VAR25-1:0] VAR23;
output [VAR3-1:0] VAR4;
reg[VAR3-1:0] VAR7 [0:VAR19-1];
integer VAR24;
always @ (posedge clk)
begin
if (VAR18)
begin
for (VAR... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_obc1/cheat.v | 11,968 | module MODULE1(
input clk,
input [7:0] VAR4,
input [23:0] VAR27,
input [7:0] VAR65,
input VAR62,
input VAR42,
input VAR49,
input VAR12,
input VAR15,
input VAR34,
input VAR7,
input VAR33,
input VAR26,
input VAR59,
input VAR5,
input VAR54,
input [2:0] VAR22,
input VAR63,
input [31:0] VAR23,
output [7:0] VAR24,
output VAR... | gpl-2.0 |
8l/kestrel | 2/nexys2/kia/kia.v | 4,148 | module MODULE1(
input VAR5,
input VAR27,
input [0:0] VAR12,
input VAR19,
input VAR31,
input VAR20,
output VAR6,
output [7:0] VAR26,
input VAR33,
input VAR3
);
reg [7:0] VAR13[0:15];
reg [3:0] VAR22;
reg [3:0] VAR4;
wire [3:0] VAR32 = VAR4+1;
wire VAR2 = (VAR32 == VAR22);
wire VAR11 = (VAR22 == VAR4);
reg ack;
assign VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.v | 2,463 | module MODULE2 (
VAR8 ,
VAR9,
VAR4,
VAR5 ,
VAR1 ,
VAR7,
VAR2,
VAR11 ,
VAR10
);
output VAR8 ;
input VAR9;
input VAR4;
input VAR5 ;
input VAR1 ;
input VAR7;
input VAR2;
input VAR11 ;
input VAR10 ;
VAR3 VAR6 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR10(... | apache-2.0 |
martinmiranda14/Digitales | Lab_6/new/show_two_lines.v | 7,695 | module MODULE1(
input clk,
input rst,
input [10:0]VAR8,
input [10:0]VAR6,
input [8 * VAR11 - 1 : 0] VAR34,
output VAR15,
output reg VAR14
);
localparam VAR13 = 3'd3; parameter VAR40 = 11'd280;
parameter VAR21 = 11'd50;
localparam VAR19 = 8'd5;
localparam VAR41 = 8'd8;
localparam VAR11 = 3; localparam VAR2 = 1; localpar... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/maj3/sky130_fd_sc_hd__maj3_2.v | 2,174 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR8 ,
VAR2 ,
VAR1,
VAR3,
VAR10 ,
VAR4
);
output VAR6 ;
input VAR9 ;
input VAR8 ;
input VAR2 ;
input VAR1;
input VAR3;
input VAR10 ;
input VAR4 ;
VAR7 VAR5 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4.blackbox.v | 1,275 | module MODULE1 (
VAR4,
VAR5,
VAR1,
VAR7,
VAR2
);
output VAR4;
input VAR5;
input VAR1;
input VAR7;
input VAR2;
supply1 VAR6;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/snescmd_buf.v | 10,706 | module MODULE1 (
VAR30,
VAR24,
VAR42,
VAR45,
VAR3,
VAR57,
VAR58,
VAR2,
VAR18);
input [8:0] VAR30;
input [8:0] VAR24;
input VAR42;
input [7:0] VAR45;
input [7:0] VAR3;
input VAR57;
input VAR58;
output [7:0] VAR2;
output [7:0] VAR18;
tri1 VAR42;
tri0 VAR57;
tri0 VAR58;
wire [7:0] VAR28;
wire [7:0] VAR27;
wire [7:0] VAR2 ... | gpl-2.0 |
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