repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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alonso193/proyecto1 | Pruebas/DATA_SD/probador.v | 3,017 | module MODULE1(
output reg VAR7,
output reg VAR10,
output reg VAR9,
output reg [3:0] VAR12,
output reg VAR11,
output reg VAR5,
output reg [15:0] VAR6,
output reg VAR2,
output reg VAR3,
output reg VAR1,
output reg VAR13,
output reg VAR4,
output reg VAR8
);
always
begin
VAR7= ! VAR7;
end | gpl-3.0 |
alexforencich/verilog-ethernet | rtl/axis_gmii_tx.v | 13,349 | module MODULE1 #
(
parameter VAR23 = 8,
parameter VAR9 = 1,
parameter VAR10 = 64,
parameter VAR25 = 0,
parameter VAR17 = 96,
parameter VAR7 = VAR25,
parameter VAR27 = 16,
parameter VAR12 = (VAR7 ? VAR27 : 0) + 1
)
(
input wire clk,
input wire rst,
input wire [VAR23-1:0] VAR16,
input wire VAR26,
output wire VAR8,
input ... | mit |
VishalRohra/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/sdhc/rtl/verilog/sd_top.v | 11,898 | module MODULE1 (
input wire VAR90,
input wire VAR4,
input wire VAR36,
input wire VAR92,
input wire VAR67,
input wire VAR22,
output wire VAR124,
output wire VAR50,
input wire [3:0] VAR9,
output wire [3:0] VAR96,
output wire [3:0] VAR10,
output wire VAR111,
output wire [31:0] VAR5,
input wire [31:0] VAR56,
output wire [3... | apache-2.0 |
cpulabs/mist1032isa | src/core/execute/execute_adder.v | 4,712 | module MODULE1 #(
parameter VAR11 = 32
)(
input wire [VAR11-1:0] VAR10,
input wire [VAR11-1:0] VAR1,
input wire [4:0] VAR9,
output wire [VAR11-1:0] VAR3,
output wire VAR17,
output wire VAR13,
output wire VAR7,
output wire VAR2,
output wire VAR16
);
assign {VAR16, VAR2, VAR13, VAR17, VAR7, VAR3} = VAR14(VAR9, VAR10, VAR... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_riscv/bsg_htif/bsg_fsb_to_htif_connector.v | 1,476 | module MODULE1
import VAR7::VAR17;
,parameter VAR30=(VAR17)
,parameter VAR4(VAR32)
)
(input VAR26
,input VAR1
,input VAR11
,input [VAR30-1:0] VAR27
,output VAR6
,output VAR5
,output [VAR30-1:0] VAR23
,input VAR22
,input VAR15
,input [VAR35-1:0] VAR20
,output VAR33
,output VAR34
,output [VAR35-1:0] VAR36
,input VAR24
);... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.behavioral.v | 1,577 | module MODULE1 (
VAR1 ,
VAR8,
VAR13,
VAR10,
VAR3,
VAR15
);
output VAR1 ;
input VAR8;
input VAR13;
input VAR10;
input VAR3;
input VAR15;
supply1 VAR5;
supply0 VAR14;
supply1 VAR4 ;
supply0 VAR11 ;
wire VAR9 ;
wire VAR2;
or VAR6 (VAR9 , VAR13, VAR8, VAR10 );
nand VAR12 (VAR2, VAR15, VAR9, VAR3);
buf VAR7 (VAR1 , VAR2 );
... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_nopipe_20.v | 15,253 | module MODULE1 (
clk,
reset,
VAR52,
VAR33,
VAR12,
VAR109,
VAR48
);
parameter VAR117 = 18;
parameter VAR66 = 20;
parameter VAR37 = 10;
localparam VAR54 = 21;
input clk;
input reset;
input VAR52;
input VAR33;
input [VAR117-1:0] VAR12; output VAR109;
output [VAR117-1:0] VAR48;
localparam VAR70 = 18; localparam VAR24 = 36;... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkbuf/sky130_fd_sc_hd__clkbuf_2.v | 2,034 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR5,
VAR1,
VAR2 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR5;
input VAR1;
input VAR2 ;
input VAR3 ;
VAR8 VAR4 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR5;
supply0 VAR1;... | apache-2.0 |
bkboggy/MIPS | I_FETCH.v | 1,107 | module MODULE1(input clk, VAR27, input wire [31:0] VAR26,
output wire [31:0] VAR25, VAR8);
wire [31:0] VAR4;
wire [31:0] VAR21;
wire [31:0] VAR3;
wire [31:0] VAR23;
VAR15 mux(.VAR17(VAR26), .VAR6(VAR3), .sel(VAR27), .VAR20(VAR23));
VAR12 VAR16(.clk(clk), .VAR1(VAR23), .VAR12(VAR4));
VAR5 VAR10(.clk(clk), .addr(VAR4), .... | mit |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_spram_256x32.v | 3,630 | module MODULE1(
input clk, input rst, input VAR7, input [3:0] VAR6, input VAR10, input [7:0] addr, input [31:0] VAR2, output [31:0] do
);
wire VAR9;
assign VAR9 = VAR7 & (|VAR6);
VAR4
VAR12
VAR3
.VAR17 ( 32 ) ,
.VAR1 ( 8 )
) VAR13 (
.VAR14 ( clk ),
.VAR16 ( VAR2 ),
.VAR8 ( VAR9 ),
.VAR5 ( addr ),
.VAR11 ( VAR6 ),
.VAR1... | lgpl-3.0 |
Tao-J/nexys3MIPSSoC | mux4to1_32.v | 1,088 | module MODULE1(
input wire [1:0] sel,
input wire [31:0] VAR1,
input wire [31:0] VAR3,
input wire [31:0] VAR5,
input wire [31:0] VAR2,
output reg [31:0] VAR4
);
always @(*)
case(sel)
2'b00: VAR4<=VAR1;
2'b01: VAR4<=VAR3;
2'b10: VAR4<=VAR5;
2'b11: VAR4<=VAR2;
endcase
endmodule | gpl-3.0 |
jotego/jt12 | hdl/adpcm/jt10_adpcma_lut.v | 11,418 | module MODULE1(
input clk, input VAR3,
input VAR1,
input [8:0] addr, output reg [11:0] VAR2
);
reg [11:0] lut[0:391]; | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | kcpsm6.v | 79,783 | module MODULE1 (address, VAR363, VAR344, VAR63, VAR176, VAR31, VAR133, VAR149, VAR386, interrupt, VAR159, VAR66, reset, clk) ;
parameter [7:0] VAR358 = 8'h00 ;
parameter [11:0] VAR270 = 12'h3FF ;
parameter integer VAR356 = 64 ;
output [11:0] address ;
input [17:0] VAR363 ;
output VAR344 ;
input [7:0] VAR63 ;
output [7:... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_arbiter.v | 53,317 | module MODULE1 #
( parameter
VAR87 = 4,
VAR79 = 4,
VAR164 = "VAR40",
VAR142 = 0,
VAR170 = 0,
VAR157 = 1,
VAR100 = 1,
VAR18 = 3,
VAR35 = 13,
VAR43 = 10,
VAR113 = 10,
VAR70 = 10,
VAR25 = 4,
VAR84 = 2,
VAR161 = 1
)
(
VAR105,
VAR172,
VAR94,
VAR167,
VAR75,
VAR133,
VAR85,
VAR117,
VAR158,
VAR173,
VAR8,
VAR175,
VAR72,
VAR34,
V... | gpl-3.0 |
orbancedric/DeepGate | other/Mojo Projects/Mojo-SDRAM/ipcore_dir/sdram_clk_gen/example_design/sdram_clk_gen_exdes.v | 4,769 | module MODULE1
parameter VAR22 = 100
)
( input VAR12,
input VAR25,
output [1:1] VAR4,
output VAR16
);
localparam VAR1 = 16;
wire VAR3 = VAR25;
reg VAR7;
reg VAR17;
reg VAR6;
reg VAR23;
wire VAR27;
wire VAR13;
wire clk;
reg [VAR1-1:0] counter;
VAR5 VAR21
( .VAR20 (VAR12),
.VAR9 (VAR27));
assign VAR13 = ~clk;
VAR18 VAR26... | gpl-3.0 |
fpgasystems/Centaur | rtl/fthread/fifo_reader.v | 14,494 | module MODULE1 #(parameter VAR6 = 32,
parameter VAR28 = VAR71)
(
input wire clk,
input wire VAR39,
input wire [57:0] VAR42,
input wire [3:0] VAR52,
input wire VAR66,
input wire VAR41,
output reg [57:0] VAR80,
output reg [2+VAR28-1:0] VAR83,
output reg VAR44,
input wire VAR74,
output reg [57:0] VAR69,
output reg [VAR20-... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.symbol.v | 1,351 | module MODULE1 (
input VAR6,
input VAR7,
input VAR3,
input VAR8,
input VAR4,
output VAR5
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkBranch_Predictor.v | 24,936 | module MODULE1(VAR58,
VAR105,
VAR96,
VAR99,
VAR6,
VAR122,
VAR102,
VAR50,
VAR125,
VAR12,
VAR118,
VAR119,
VAR24,
VAR138,
VAR71,
VAR26);
input VAR58;
input VAR105;
input VAR96;
output VAR99;
input [63 : 0] VAR6;
input VAR122;
output VAR102;
input VAR50;
input [31 : 0] VAR125;
output [63 : 0] VAR12;
input [63 : 0] VAR118;
... | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/bus/bus_master_mux.v | 7,481 | module MODULE1(
input wire [VAR3] VAR31 , input wire VAR25 , input wire VAR11 , input wire [VAR32] VAR10 , input wire VAR7 , input wire [VAR3] VAR20 , input wire VAR13 , input wire VAR17 , input wire [VAR32] VAR14 , input wire VAR15 , input wire [VAR3] VAR9 , input wire VAR30 , input wire VAR29 , input wire [VAR32] VAR... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_filter.v | 1,317 | module MODULE1(
input VAR5,
input VAR2,
input VAR8,
input VAR13,
output reg VAR3,
output reg VAR4,
output reg VAR12
);
reg VAR10;
reg VAR9;
reg VAR11;
reg VAR7;
reg VAR6;
reg VAR1;
always @(posedge VAR5) begin
VAR10 <= VAR2;
VAR9 <= VAR8;
VAR11 <= VAR13;
VAR3 <= VAR10;
VAR4 <= VAR9;
VAR12 <= VAR11;
end
endmodule | lgpl-3.0 |
walkthetalk/fsref | ip/fscpu/src/include/AM_sw_img.v | 2,723 | module MODULE1 # (
parameter integer VAR16 = 32
) (
input wire clk,
input wire VAR15,
input wire VAR4,
input wire VAR10,
input wire signed [VAR16-1:0] VAR2,
input wire VAR1,
input wire VAR17,
input wire VAR18,
output reg VAR22,
output reg signed [VAR16-1:0] VAR14,
output reg VAR3,
output reg VAR19
);
reg [1:0] VAR11;
r... | gpl-3.0 |
jas0n1ee/THU-DSD | FB/ip/opencores_i2c/i2c_master_top.v | 9,912 | module MODULE1(
VAR18, VAR29, VAR1, VAR3, VAR17, VAR25,
VAR51, VAR6, VAR7, VAR16, VAR4,
VAR30, VAR9, VAR33, VAR21, VAR15, VAR38 );
parameter VAR10 = 1'b0;
input VAR18; input VAR29; input VAR1; input [2:0] VAR3; input [7:0] VAR17; output [7:0] VAR25; input VAR51; input VAR6; input VAR7; output VAR16; output VAR4;
reg [7... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_tx.v | 11,482 | module MODULE1 (
VAR73,
VAR55,
VAR52,
VAR32,
VAR62,
VAR37,
VAR92,
VAR28,
VAR22,
VAR17,
VAR88,
VAR85,
VAR69,
VAR81,
VAR89,
VAR87,
VAR11,
VAR84,
VAR53,
VAR3,
VAR24,
VAR93,
VAR29,
VAR50,
VAR58,
VAR49,
VAR65);
parameter VAR72 = 0;
parameter VAR1 = 0;
parameter VAR78 = 32'h00060061;
input VAR73;
output VAR55;
output VAR52;
... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/ccx_arb.v | 10,167 | module MODULE1(
VAR28, VAR1, VAR34,
VAR12, VAR3, VAR4,
VAR16, VAR66, VAR57,
VAR38, VAR53, VAR31, VAR20,
VAR60, VAR35, VAR65,
VAR61, VAR63, VAR56, VAR55,
VAR49, VAR29, VAR26, VAR21,
VAR36, VAR48, VAR2, VAR45,
VAR5, VAR42, VAR59, VAR22,
VAR18, VAR52, VAR43, VAR13, VAR54,
VAR46, VAR41
);
output [7:0] VAR35; output [7:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp.functional.v | 2,125 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR16 ,
VAR9 ,
VAR8 ,
VAR17 ,
VAR6
);
output VAR5 ;
output VAR3 ;
input VAR16 ;
input VAR9 ;
input VAR8 ;
input VAR17 ;
input VAR6;
wire VAR7 ;
wire VAR1 ;
wire VAR10;
not VAR18 (VAR1 , VAR6 );
VAR14 VAR4 (VAR10, VAR9, VAR8, VAR17 );
VAR11 VAR2 VAR12 (VAR7 , VAR10, VAR16, VAR1);
buf VAR15... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/decap/sky130_fd_sc_hvl__decap.behavioral.v | 1,139 | module MODULE1 ();
supply1 VAR3;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2ai/sky130_fd_sc_ls__o2bb2ai.functional.pp.v | 2,184 | module MODULE1 (
VAR12 ,
VAR19,
VAR10,
VAR18 ,
VAR11 ,
VAR14,
VAR13,
VAR9 ,
VAR15
);
output VAR12 ;
input VAR19;
input VAR10;
input VAR18 ;
input VAR11 ;
input VAR14;
input VAR13;
input VAR9 ;
input VAR15 ;
wire VAR6 ;
wire VAR2 ;
wire VAR16 ;
wire VAR8;
nand VAR4 (VAR6 , VAR10, VAR19 );
or VAR3 (VAR2 , VAR11, VAR18 );... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_INVBUF_LVT_TT_210930.v | 14,913 | module MODULE1 (VAR2, VAR1);
output VAR2;
input VAR1;
buf (VAR2, VAR1); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand2/sky130_fd_sc_hdll__nand2.behavioral.pp.v | 1,810 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR11 ,
VAR6,
VAR9,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR6;
input VAR9;
input VAR1 ;
input VAR2 ;
wire VAR12 ;
wire VAR5;
nand VAR4 (VAR12 , VAR11, VAR8 );
VAR10 VAR7 (VAR5, VAR12, VAR6, VAR9);
buf VAR13 (VAR3 , VAR5 );
endmodule | apache-2.0 |
sam-falvo/verilog-foundations | wishbone/pipelined/master.v | 5,454 | module MODULE1(
input VAR4,
input VAR5,
input VAR11,
output VAR16,
output [VAR8:0] VAR2,
output VAR3,
output VAR14,
output VAR6,
input VAR13
);
parameter VAR17 = 16;
parameter VAR10 = VAR10;
parameter VAR15 = VAR15;
parameter VAR8 = VAR17 - 1;
reg [VAR8:0] VAR2;
reg VAR14;
reg VAR6;
reg [VAR8:0] VAR7, VAR12;
reg VAR1, ... | mpl-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_mux.v | 12,976 | module MODULE1 #
(
parameter VAR34 = 4,
parameter VAR47 = 8,
parameter VAR13 = (VAR47>8),
parameter VAR77 = (VAR47/8),
parameter VAR24 = 0,
parameter VAR41 = 8,
parameter VAR89 = 0,
parameter VAR87 = 8,
parameter VAR56 = 1,
parameter VAR51 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR34-1:0] VAR88,
output wir... | mit |
parallella/oh | common/hdl/oh_datagate.v | 1,109 | module MODULE1 #(parameter VAR1 = 32, parameter VAR3 = 3 )
(
input clk, input en, input [VAR1-1:0] din, output [VAR1-1:0] dout );
reg [VAR3-1:0] VAR2;
wire enable;
always @ (posedge clk)
VAR2[VAR3-1:0] <= {VAR2[VAR3-2:0],en};
assign enable = en | (|VAR2[VAR3-1:0]);
assign dout[VAR1-1:0] = {(VAR1){enable}} & din[VAR1-1:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn.behavioral.pp.v | 3,448 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR4 ,
VAR29 ,
VAR12 ,
VAR14 ,
VAR16 ,
VAR37,
VAR19 ,
VAR28 ,
VAR13 ,
VAR21
);
output VAR2 ;
output VAR7 ;
input VAR4 ;
input VAR29 ;
input VAR12 ;
input VAR14 ;
input VAR16 ;
input VAR37;
input VAR19 ;
input VAR28 ;
input VAR13 ;
input VAR21 ;
wire VAR25 ;
wire VAR30 ;
wire VAR9 ;
wire V... | apache-2.0 |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_static_mrdwr.v | 30,158 | module MODULE1 #
(
parameter VAR129 = 1 ,
parameter VAR16 = 8 ,
parameter VAR43 = 8 ,
parameter VAR113 = 32 ,
parameter VAR103 = 32'h12A00000 ,
parameter VAR69 = 32'h13A00000 ,
parameter VAR91 = 32'h12A00FFF ,
parameter VAR97 = 32'h13A00FFF ,
parameter VAR34 = 0 ,
parameter VAR2 = 1 ,
parameter VAR89 = 1 ,
parameter VA... | gpl-3.0 |
sh-chris110/chris | FPGA/Math/db/altera_mult_add_37p2.v | 17,735 | module MODULE1
(
VAR89,
VAR193,
VAR132,
VAR286,
VAR186,
VAR226) ;
input VAR89;
input VAR193;
input [15:0] VAR132;
input [15:0] VAR286;
input VAR186;
output [31:0] VAR226;
tri0 VAR89;
tri1 VAR193;
tri0 [15:0] VAR132;
tri0 [15:0] VAR286;
tri1 VAR186;
wire [31:0] VAR96;
VAR57 VAR328
(
.VAR89(VAR89),
.VAR66(),
.VAR193(VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3.behavioral.pp.v | 1,810 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR9 ,
VAR6 ,
VAR13,
VAR8,
VAR4 ,
VAR12
);
output VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR6 ;
input VAR13;
input VAR8;
input VAR4 ;
input VAR12 ;
wire VAR14 ;
wire VAR5;
and VAR1 (VAR14 , VAR6, VAR10, VAR9 );
VAR11 VAR3 (VAR5, VAR14, VAR13, VAR8);
buf VAR2 (VAR7 , VAR5 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.blackbox.v | 1,297 | module MODULE1 (
VAR6,
VAR1 ,
VAR5,
VAR3
);
output VAR6;
input VAR1 ;
input VAR5;
input VAR3 ;
supply1 VAR2;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_4.behavioral.v | 1,098 | module MODULE1( VAR4, VAR5 );
input VAR4;
output VAR5;
VAR2 VAR1(.VAR4(VAR4),.VAR5(VAR5));
VAR2 VAR3(.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
fredmorcos/attic | projects/vo-tools/machines/sbn/sbn.v | 3,359 | module MODULE1 (clk, state, VAR13, VAR19, VAR20);
parameter VAR11 = 8; parameter VAR30 = 32;
input clk;
output [2:0] state;
output [VAR11-1:0] VAR13;
output [VAR30-1:0] VAR19, VAR20;
parameter VAR25 = 4 * VAR11;
reg [VAR25-1:0] VAR14[0:((1<<VAR11)-1)];
reg [VAR30-1:0] VAR10[0:((1<<VAR11)-1)];
reg [VAR30-1:0] VAR21, VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.v | 2,334 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR9 ,
VAR6 ,
VAR3 ,
VAR7,
VAR8,
VAR1 ,
VAR11
);
output VAR4 ;
input VAR2 ;
input VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR7;
input VAR8;
input VAR1 ;
input VAR11 ;
VAR5 VAR10 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR11... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_PI_Sat_block.v | 2,207 | module MODULE1
(
VAR15,
VAR7,
VAR10
);
input signed [35:0] VAR15; output signed [35:0] VAR7; output VAR10;
wire signed [17:0] VAR3; wire signed [18:0] VAR8; wire signed [18:0] VAR13; wire signed [17:0] VAR17; wire signed [35:0] VAR12; wire VAR16;
assign VAR3 = 18'VAR14;
assign VAR8 = VAR3;
assign VAR13 = - (VAR8);
assi... | gpl-3.0 |
fabianz66/cursos-tec | taller-digital/Proyecto Final/proyecto-final/top_module.v | 1,119 | module MODULE1(
input VAR3,
input reset,
output VAR6,
output VAR8,
output VAR1,
output VAR5
);
wire[15:0] VAR2, VAR7;
reg[2:0] VAR4;
begin | mit |
SiLab-Bonn/basil | basil/firmware/modules/tlu/tlu_controller_core.v | 29,267 | module MODULE1 #(
parameter VAR129 = 16,
parameter VAR186 = 8, parameter VAR31 = 17, parameter VAR96 = 8,
parameter VAR78 = 32
) (
input wire VAR39,
input wire VAR52,
input wire [VAR129-1:0] VAR112,
input wire [7:0] VAR29,
input wire VAR93,
input wire VAR198,
output reg [7:0] VAR211,
input wire VAR218,
input wire VAR14... | bsd-3-clause |
alan4186/ParCNN | Hardware/v/top.v | 9,239 | module MODULE1(
input VAR123,
input VAR40,
input VAR5,
output [8:0] VAR6,
output [17:0] VAR14,
input [3:0] VAR23,
input [17:0] VAR71,
output reg [6:0] VAR110,
output [7:0] VAR127,
output VAR125,
output VAR108,
output [7:0] VAR16,
output VAR82,
output [7:0] VAR133,
output VAR92,
output VAR152,
output [12:0] VAR156,
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn.pp.symbol.v | 1,575 | module MODULE1 (
input VAR8 ,
output VAR10 ,
output VAR7 ,
input VAR2,
input VAR6 ,
input VAR1 ,
input VAR3 ,
input VAR5 ,
input VAR12 ,
input VAR9 ,
input VAR11 ,
input VAR4
);
endmodule | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/syn/src/spare/build1/regfileww.v | 5,171 | module MODULE1 (VAR2,VAR5,VAR11,VAR9,VAR8,VAR13,
VAR6,VAR14,VAR4,VAR1,clk);
output [127:0] VAR2,VAR5;
input [0:127] VAR11;
input clk;
input VAR4;
input VAR6, VAR14;
input [4:0] VAR13, VAR9, VAR8;
input [15:0] VAR1;
reg [127:0] VAR2,VAR5;
reg [127:0] VAR7 [31:0];
reg [127:0] VAR10; reg [127:0] VAR3; reg [7:0] VAR12;
alw... | mit |
ptracton/Picoblaze | projects/basic/rtl/kcpsm6.v | 82,826 | module MODULE1 (address, VAR152, VAR382, VAR165, VAR206, VAR321, VAR385, VAR14, VAR291, interrupt, VAR93, VAR251, reset, clk) ;
parameter [7:0] VAR306 = 8'h00 ;
parameter [11:0] VAR39 = 12'h3FF ;
parameter integer VAR327 = 64 ;
output [11:0] address ;
input [17:0] VAR152 ;
output VAR382 ;
input [7:0] VAR165 ;
output [7... | mit |
crypt5/Mechatronics | Serial to SPI/SERIAL_OUT.v | 1,042 | module MODULE1(VAR6,VAR5,VAR2,VAR8,VAR3,VAR10,VAR9,VAR7);
input VAR6,VAR3,VAR7;
input [7:0]VAR5;
output reg VAR9,VAR8,VAR10=1;
output reg [4:0]VAR2=0;
reg [9:0] VAR4=0;
reg [6:0] VAR1=0;
always@(posedge VAR6 or negedge VAR7)
begin
if(VAR7==0)
begin
VAR1=0;
VAR2=0;
VAR10=1;
VAR8=0;
VAR9=1;
end
else
begin
if(VAR3==1)
beg... | mit |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_64x36_2clk.v | 5,302 | module MODULE1(
din,
VAR3,
VAR30,
rst,
VAR5,
VAR70,
dout,
VAR1,
VAR37,
VAR79,
VAR38);
input [35 : 0] din;
input VAR3;
input VAR30;
input rst;
input VAR5;
input VAR70;
output [35 : 0] dout;
output VAR1;
output VAR37;
output [6 : 0] VAR79;
output [6 : 0] VAR38;
VAR103 #(
.VAR88(0),
.VAR57(0),
.VAR48(7),
.VAR75("VAR47"),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfsbp/sky130_fd_sc_hvl__dfsbp.pp.blackbox.v | 1,376 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR8 ,
VAR9 ,
VAR6,
VAR7 ,
VAR3 ,
VAR5 ,
VAR1
);
output VAR4 ;
output VAR2 ;
input VAR8 ;
input VAR9 ;
input VAR6;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_sd_host/rtl/wb_sd_host.v | 35,548 | module MODULE1 #(
parameter VAR47 = 1,
parameter VAR205 = 1,
parameter VAR50 = 1,
parameter VAR69 = 11, parameter VAR105 = 0,
parameter VAR88 = 0
)(
input clk,
input rst,
input VAR182,
input VAR168,
input [3:0] VAR2,
input [31:0] VAR136,
input VAR7,
output reg VAR48,
output reg [31:0] VAR45,
input [31:0] VAR281,
output... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_register.v | 4,462 | module MODULE1(VAR6, VAR8, VAR5, VAR7, VAR4, VAR2);
parameter VAR1 = 8; parameter VAR3 = 0;
input [VAR1-1:0] VAR6;
input VAR5;
input VAR7;
input VAR4;
input VAR2;
output [VAR1-1:0] VAR8;
reg [VAR1-1:0] VAR8;
always @ (posedge VAR7 or posedge VAR4)
begin
if(VAR4)
VAR8<= VAR3;
end
else
if(VAR2)
VAR8<= VAR3;
else
if(VAR5)... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.pp.blackbox.v | 1,234 | module MODULE1 (
VAR2,
VAR3 ,
VAR1 ,
VAR5 ,
VAR4
);
input VAR2;
input VAR3 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi.functional.v | 2,130 | module MODULE1 (
VAR11,
VAR15,
VAR17 ,
VAR1 ,
VAR5 ,
VAR14 ,
VAR4 ,
VAR6
);
input VAR11;
input VAR15;
output VAR17 ;
input VAR1 ;
input VAR5 ;
input VAR14 ;
input VAR4 ;
input VAR6 ;
wire VAR4 VAR10 ;
wire VAR4 VAR9 ;
wire VAR13 ;
wire VAR18;
nand VAR2 (VAR10 , VAR5, VAR1, VAR14 );
nand VAR16 (VAR9 , VAR6, VAR4 );
and ... | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_switches.v | 1,894 | module MODULE1 (
address,
clk,
VAR3,
VAR2,
VAR1
)
;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input clk;
input [ 9: 0] VAR3;
input VAR2;
wire VAR5;
wire [ 9: 0] VAR6;
wire [ 9: 0] VAR4;
reg [ 31: 0] VAR1;
assign VAR5 = 1;
assign VAR4 = {10 {(address == 0)}} & VAR6;
always @(posedge clk or negedge VAR2)
begin
if (VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.behavioral.v | 1,713 | module MODULE1 (
VAR7 ,
VAR10,
VAR12,
VAR6 ,
VAR16
);
output VAR7 ;
input VAR10;
input VAR12;
input VAR6 ;
input VAR16 ;
supply1 VAR3;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR4 ;
wire VAR1 ;
wire VAR13 ;
wire VAR14;
and VAR5 (VAR1 , VAR6, VAR16 );
nor VAR9 (VAR13 , VAR10, VAR12 );
or VAR8 (VAR14, VAR13, VAR1);
buf VAR... | apache-2.0 |
DatanoiseTV/Parallax-Propeller-P8X32A-FPGA | P8X32A_Emulation/P8X32A_DE0_Nano/hub.v | 6,563 | module MODULE1
(
input VAR10,
input VAR37,
input VAR2,
input [7:0] VAR9,
input VAR29,
input VAR38,
input VAR11,
input [1:0] VAR47,
input [15:0] VAR23,
input [31:0] VAR6,
output reg [31:0] VAR39,
output VAR28,
output [7:0] VAR48,
output reg [7:0] VAR33,
output [7:0] VAR30,
output [27:0] VAR45,
output reg [7:0] VAR27
);
... | gpl-3.0 |
olgirard/opengfx430 | core/rtl/verilog/ogfx_reg.v | 58,930 | module MODULE1 (
VAR64,
VAR87, VAR30, VAR51,
VAR86, VAR311, VAR26, VAR293, VAR184, VAR217, VAR333,
VAR81,
VAR282,
VAR163, VAR278, VAR65, VAR19, VAR313,
VAR77, VAR323, VAR20, VAR54, VAR300
VAR326, VAR113, VAR224, VAR175,
VAR316, VAR328, VAR200, VAR96, VAR94, VAR119, VAR84, VAR58, VAR299, VAR229, VAR125, VAR251 VAR106
VA... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s50/sky130_fd_sc_hd__clkdlybuf4s50.pp.blackbox.v | 1,343 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4,
VAR6,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR1 ;
input VAR4;
input VAR6;
input VAR3 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222oi/sky130_fd_sc_hs__a222oi.symbol.v | 1,382 | module MODULE1 (
input VAR9,
input VAR1,
input VAR3,
input VAR4,
input VAR7,
input VAR6,
output VAR2
);
supply1 VAR5;
supply0 VAR8;
endmodule | apache-2.0 |
Kipsora/MIPS-CPU | source/machine/cpu/stages/mem-wb-buffer.v | 2,309 | module MODULE1(
input wire VAR1,
input wire reset,
input wire[VAR16] VAR11,
input wire VAR3,
input wire[VAR15] VAR6,
input wire[VAR12] VAR7,
input wire VAR13,
input wire[VAR12] VAR10,
input wire[VAR12] VAR5,
output reg VAR18,
output reg[VAR15] VAR2,
output reg[VAR12] VAR19,
output reg VAR9,
output reg[VAR12] VAR17,
out... | mit |
YosysHQ/yosys | techlibs/efinix/arith_map.v | 2,437 | module MODULE1(
module 80efinixalu (VAR20, VAR13, VAR25, VAR27, VAR11, VAR23, VAR32);
parameter VAR4 = 0;
parameter VAR15 = 0;
parameter VAR1 = 1;
parameter VAR31 = 1;
parameter VAR24 = 1;
input [VAR1-1:0] VAR20;
input [VAR31-1:0] VAR13;
output [VAR24-1:0] VAR11, VAR23;
input VAR25, VAR27;
output [VAR24-1:0] VAR32;
wir... | isc |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/vio_init_pattern_bram.v | 11,740 | module MODULE1 #
(
parameter VAR11 = 100,
parameter VAR27 = 32'h00000000,
parameter VAR2 = 8,
parameter VAR21 = 4,
parameter VAR42 = 16,
parameter VAR18 = 8,
parameter VAR4 = VAR18
)
(
input VAR25,
input VAR10,
input VAR13,
input [31:0] VAR15, input VAR19, input [3:0] VAR29, input [31:0] VAR54, input [31:0] VAR6, input... | lgpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_s6_x1_125/source/pcie_bram_s6.v | 6,069 | module MODULE1 #(
parameter VAR1 = 0, parameter VAR9 = 0 ) (
input VAR8, input VAR13,
input VAR4, input [11:0] VAR12, input [VAR9 - 1:0] VAR7,
input VAR5, input VAR15, input [11:0] VAR11,
output [VAR9 - 1:0] VAR10 );
localparam VAR3 = ((VAR9 == 4) ? 11 :
(VAR9 == 9) ? 10 :
(VAR9 == 18) ? 9 :
8
);
localparam VAR2 = ((VA... | lgpl-3.0 |
richard42/CoCo3FPGA | ps2_keyboard.v | 5,922 | module MODULE1 (
VAR1,
VAR20,
VAR15,
VAR5,
VAR19,
VAR12,
VAR17
);
input VAR1;
input VAR20;
input VAR15;
input VAR5;
output VAR19;
reg VAR19;
output VAR12;
reg VAR12;
output [7:0] VAR17;
reg [7:0] VAR17;
reg VAR13;
reg VAR7;
reg VAR9;
reg VAR6;
reg VAR10;
reg VAR16;
reg [2:0] VAR11;
reg [3:0] VAR4;
reg [7:0] VAR3;
wire ... | bsd-3-clause |
prernaa/CPUVerilog | alu.v | 2,550 | module MODULE1(
VAR7, VAR12, VAR4, VAR2, VAR3,
VAR1, out );
parameter VAR11 = 16;
input [VAR11-1:0] VAR7, VAR12;
input [2:0] VAR4;
input [3:0] VAR2;
input VAR3;
output reg[VAR11-1:0] out;
output [2:0] VAR1;
wire [VAR11-1:0] VAR8;
assign VAR8 = ~VAR12 + 1'b1;
reg [2:0] VAR10;
reg [2:0] VAR6;
reg [2:0] VAR9;
always @(VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or4/gf180mcu_fd_sc_mcu9t5v0__or4_1.behavioral.v | 1,317 | module MODULE1( VAR6, VAR8, VAR2, VAR3, VAR4 );
input VAR6, VAR8, VAR2, VAR3;
output VAR4;
VAR5 VAR1(.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4));
VAR5 VAR7(.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2),.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/alu_current.v | 330,546 | module MODULE1 (VAR5,VAR3,VAR4,VAR2,VAR1);
output [0:127] VAR1;
input [0:127] VAR5;
input [0:127] VAR3;
input [0:1] VAR4;
input [0:4] VAR2;
reg [0:127] VAR1;
always @(VAR5 or VAR3 or VAR4 or VAR2)
begin
case(VAR2)
begin
case(VAR4)
case(VAR3[5:7])
0:
begin
VAR1[0:7]<=VAR5[0:7]>>0;
VAR1[8:15]<=VAR5[8:15]>>0;
VAR1[16:23]<... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv_8.v | 2,036 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR5,
VAR4,
VAR8 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR5;
input VAR4;
input VAR8 ;
input VAR3 ;
VAR7 VAR6 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR5;
supply0 VAR4;... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/controller/arb_row_col.v | 16,373 | module MODULE1 #
(
parameter VAR21 = 100,
parameter VAR64 = "1T",
parameter VAR75 = 5,
parameter VAR44 = "VAR52",
parameter VAR12 = 4,
parameter VAR46 = 2,
parameter VAR25 = 2,
parameter VAR51 = 37500, parameter VAR29 = 12500, parameter VAR80 = 6 )
(
VAR78, VAR14, VAR100, VAR70, VAR86, VAR93,
VAR54, VAR81, VAR37,
VAR59... | lgpl-3.0 |
praveendath92/securePUF | source/SystemMonitor.v | 1,112 | module MODULE1(
input wire clk,
input wire [6:0] VAR10,
output wire VAR5,
output wire [15:0] VAR2
);
wire VAR3, VAR11, VAR7, VAR4;
wire [15:0] VAR8;
assign VAR3 = 1'b1;
assign VAR11 = 1'b0;
assign VAR7 = 1'b0;
assign VAR4 = 1'b0;
assign VAR8 = 16'h0000;
VAR9 VAR1(
.VAR10(VAR10[6:0]),
.VAR6(clk),
.VAR3(VAR3),
.VAR8(VAR8... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/norflash32/rtl/norflash32.v | 1,611 | module MODULE1 #(
parameter VAR8 = 21
) (
input VAR3,
input VAR6,
input [31:0] VAR5,
output reg [31:0] VAR10,
input VAR4,
input VAR1,
output reg VAR7,
output reg [VAR8-1:0] VAR2,
input [31:0] VAR9
);
always @(posedge VAR3) begin
if(VAR1 & VAR4)
VAR2 <= VAR5[VAR8+1:2];
VAR10 <= VAR9;
end
reg [3:0] counter;
always @(pose... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o.blackbox.v | 1,388 | module MODULE1 (
VAR3 ,
VAR8,
VAR7,
VAR5,
VAR2,
VAR6
);
output VAR3 ;
input VAR8;
input VAR7;
input VAR5;
input VAR2;
input VAR6;
supply1 VAR4;
supply0 VAR9;
supply1 VAR10 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
vkchettimada/aayudha | helloworld/src/helloworld.v | 1,212 | module MODULE1 (
input clk,
input rst,
output [7:0] VAR16,
output reg VAR5,
input VAR3,
input [7:0] VAR6,
input VAR15
);
localparam VAR9 = 1;
localparam VAR11 = 0,
VAR1 = 1;
localparam VAR10 = 23;
reg [VAR9-1:0] VAR4, VAR2;
reg [4:0] VAR13, VAR14;
VAR8 VAR8 (
.clk(clk),
.addr(VAR14),
.VAR7(VAR16)
);
always @(*) begin
V... | mit |
rurume/openrisc_vision_hardware | ISE/or1200_spram_32x24.v | 8,042 | module MODULE1(
VAR11, VAR17, VAR20,
clk, rst, VAR19, VAR13, VAR23, addr, VAR18, VAR22
);
parameter VAR4 = 5;
parameter VAR25 = 24;
input VAR11;
input [VAR9 - 1:0] VAR20;
output VAR17;
input clk; input rst; input VAR19; input VAR13; input VAR23; input [VAR4-1:0] addr; input [VAR25-1:0] VAR18; output [VAR25-1:0] VAR22;
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o311ai/sky130_fd_sc_ls__o311ai.behavioral.v | 1,577 | module MODULE1 (
VAR1 ,
VAR2,
VAR7,
VAR14,
VAR5,
VAR15
);
output VAR1 ;
input VAR2;
input VAR7;
input VAR14;
input VAR5;
input VAR15;
supply1 VAR10;
supply0 VAR3;
supply1 VAR12 ;
supply0 VAR11 ;
wire VAR8 ;
wire VAR6;
or VAR4 (VAR8 , VAR7, VAR2, VAR14 );
nand VAR13 (VAR6, VAR15, VAR8, VAR5);
buf VAR9 (VAR1 , VAR6 );
en... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4/sky130_fd_sc_hs__nand4_4.v | 2,126 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR1 ,
VAR6 ,
VAR2 ,
VAR5,
VAR4
);
output VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR2 ;
input VAR5;
input VAR4;
VAR8 VAR9 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7,
VAR3,
VAR1,
VAR6,
VAR2
);
... | apache-2.0 |
davidlee80/miaow | src/verilog/rtl/instr_buffer/instr_buffer.v | 1,511 | module MODULE1(
VAR6,
VAR4,
VAR5,
VAR2,
VAR3,
VAR8,
clk,
rst
);
parameter VAR7 = 1;
input clk;
input rst;
input [(VAR7 - 1):0] VAR6;
input [(VAR7*32 - 1):0] VAR4;
input [(VAR7*39 - 1):0] VAR5;
output [(VAR7 - 1):0] VAR2;
output [(VAR7*32 - 1):0] VAR3;
output [(VAR7*39 - 1):0] VAR8;
reg [(VAR7 - 1):0] VAR2;
reg [(VAR7*3... | bsd-3-clause |
monotone-RK/FACE | CQ/src/ip_dram/ecc/mig_7series_v2_3_ecc_buf.v | 6,293 | module MODULE1
parameter VAR34 = 100,
parameter VAR3 = 64,
parameter VAR38 = 4,
parameter VAR5 = 1,
parameter VAR22 = 64,
parameter VAR44 = 4
)
(
VAR21,
clk, rst, VAR8, VAR24, VAR31,
VAR33, VAR35, VAR11
);
input clk;
input rst;
input [VAR38-1:0] VAR8;
input [VAR5-1:0] VAR24;
wire [4:0] VAR42;
input [VAR38-1:0] VAR31;
i... | mit |
nickdesaulniers/Omicron | write_back.v | 1,250 | module MODULE1(
input [15:0] VAR4,
input [15:0] VAR6,
input [2:0] VAR8,
input VAR5,
input VAR1,
output [15:0] VAR3,
output VAR7,
output [2:0] VAR2
);
assign VAR3 = VAR5 ? VAR6 : VAR4;
assign VAR7 = VAR1;
assign VAR2 = VAR8;
endmodule | gpl-3.0 |
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC | bin_Dilation_Operation/system/synthesis/submodules/hps_sdram_p0_reset_sync.v | 1,933 | module MODULE1(
VAR7,
clk,
VAR3
);
parameter VAR6 = 4;
parameter VAR5 = 1;
input VAR7;
input clk;
output [VAR5-1:0] VAR3;
reg [VAR6+VAR5-2:0] VAR4 ;
generate
genvar VAR1;
for (VAR1=0; VAR1<VAR6+VAR5-1; VAR1=VAR1+1)
begin: VAR2
always @(posedge clk or negedge VAR7)
begin
if (~VAR7)
VAR4[VAR1] <= 1'b0;
end
else
begin
if ... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/stream_encoder_ip_prj/stream_encoder_ip_prj.ip_user_files/ipstatic/axi_traffic_gen_v2_0_7/hdl/src/verilog/axi_traffic_gen_v2_0_registers.v | 19,081 | module MODULE1
parameter VAR45 = 0 ,
parameter VAR19 = 0 ,
parameter VAR89 = 32,
parameter VAR126 = 1 ,
parameter VAR4 = 32,
parameter VAR93 = 1 ,
parameter VAR26 = 1 ,
parameter VAR143 = 0 ,
parameter VAR30 = 0 , parameter VAR39 = 0 , parameter VAR103 = 0 ,
parameter VAR65 = 0 ,
parameter VAR43 = 0 ,
parameter VAR109 ... | gpl-3.0 |
m-labs/fjmem-m1 | boards/milkymist-one/rtl/system.v | 1,521 | module MODULE1(
input VAR9,
output [23:0] VAR15,
inout [15:0] VAR3,
output VAR11,
output VAR1,
output VAR12,
output VAR8,
input VAR7,
output VAR6,
output VAR4
);
wire VAR2;
wire VAR13;
assign VAR13 = VAR9;
assign VAR2 = 1'b0;
assign VAR12 = 1'b0;
assign VAR8 = 1'b1;
wire VAR14;
reg [25:0] counter;
always @(posedge VAR1... | gpl-3.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_ram_switch.v | 45,893 | module MODULE1 #
(
parameter VAR10 = 4096,
parameter VAR50 = 32,
parameter VAR55 = 0,
parameter VAR3 = 4,
parameter VAR47 = 4,
parameter VAR34 = 8,
parameter VAR27 = (VAR34>8),
parameter VAR29 = (VAR34/8),
parameter VAR54 = 8,
parameter VAR44 = (VAR54>8),
parameter VAR9 = (VAR54/8),
parameter VAR23 = 0,
parameter VAR19... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b.behavioral.pp.v | 1,978 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR8 ,
VAR2 ,
VAR11 ,
VAR15,
VAR6,
VAR13 ,
VAR5
);
output VAR12 ;
input VAR7 ;
input VAR8 ;
input VAR2 ;
input VAR11 ;
input VAR15;
input VAR6;
input VAR13 ;
input VAR5 ;
wire VAR10 ;
wire VAR3 ;
wire VAR16;
not VAR9 (VAR10 , VAR11 );
or VAR4 (VAR3 , VAR10, VAR2, VAR8, VAR7 );
VAR17 VAR1... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPCG_Toggle_MNC_getFT.v | 22,489 | module MODULE1
(
parameter VAR74 = 4
)
(
VAR69 ,
VAR20 ,
VAR14 ,
VAR58 ,
VAR4 ,
VAR47 ,
VAR73 ,
VAR77 ,
VAR62 ,
VAR68 ,
VAR36 ,
VAR32 ,
VAR9 ,
VAR21 ,
VAR41 ,
VAR44 ,
VAR12 ,
VAR51 ,
VAR15 ,
VAR6 ,
VAR60 ,
VAR55 ,
VAR49 ,
VAR28 ,
VAR19 ,
VAR5 ,
VAR66
);
input VAR69 ;
input VAR20 ;
input [5:0] VAR14 ;
input [4:0] VAR58 ... | gpl-3.0 |
jeffkub/n64-cart-reader | old/fpga/soc_system/soc_system/soc_system_bb.v | 4,560 | module MODULE1 (
VAR34,
VAR62,
VAR30,
VAR6,
VAR51,
VAR67,
VAR41,
VAR17,
VAR50,
VAR49,
VAR75,
VAR56,
VAR66,
VAR71,
VAR68,
VAR24,
VAR7,
VAR65,
VAR61,
VAR60,
VAR28,
VAR2,
VAR69,
VAR29,
VAR48,
VAR12,
VAR53,
VAR33,
VAR46,
VAR15,
VAR54,
VAR27,
VAR58,
VAR8,
VAR38,
VAR47,
VAR32,
VAR13,
VAR1,
VAR43,
VAR19,
VAR42,
VAR10,
VAR70,
... | mit |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_010.v | 1,438 | module MODULE1 (
VAR1,
VAR8
);
input [31:0] VAR1;
output [31:0]
VAR8;
wire [31:0]
VAR3,
VAR10,
VAR9,
VAR12,
VAR7,
VAR4,
VAR2;
assign VAR3 = VAR1;
assign VAR4 = VAR7 << 2;
assign VAR2 = VAR7 + VAR4;
assign VAR9 = VAR10 - VAR3;
assign VAR10 = VAR3 << 9;
assign VAR7 = VAR9 + VAR12;
assign VAR12 = VAR3 << 6;
assign VAR8 = ... | mit |
davidjabon/AXI-Peripheral-Library | pwm_1.0/hdl/pwm_v1_0.v | 2,253 | module MODULE1 #
(
parameter integer VAR1 = 32,
parameter integer VAR32 = 4
)
(
output wire VAR16,
input wire VAR47,
input wire VAR26,
input wire [VAR32-1 : 0] VAR45,
input wire [2 : 0] VAR33,
input wire VAR10,
output wire VAR4,
input wire [VAR1-1 : 0] VAR3,
input wire [(VAR1/8)-1 : 0] VAR6,
input wire VAR40,
output wi... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_misc_chunk1.v | 8,154 | module MODULE1(VAR42 ,VAR64 ,VAR33 ,
VAR9 ,VAR53 ,VAR62 ,VAR57 ,VAR52 ,
VAR30 ,VAR58 ,VAR67 ,VAR13 ,VAR38 ,VAR28 ,VAR35
,VAR66 ,VAR65 ,VAR37 ,VAR10 ,VAR24 ,VAR19
,VAR61 ,VAR50 ,VAR22 ,VAR6 ,VAR26 ,VAR1 ,VAR60 ,VAR51 ,VAR46 ,
clk ,VAR4 ,VAR18 ,VAR21 ,VAR40 ,VAR69 ,VAR45 ,
VAR70 ,VAR7 ,VAR59 ,VAR43
);
input [5:4] VAR40 ;... | gpl-2.0 |
thekroko/ili9341_fpga | pll_bb.v | 11,770 | module MODULE1 (
VAR2,
VAR1,
VAR3);
input VAR2;
output VAR1;
output VAR3;
endmodule | lgpl-3.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/clk_dcm.v | 4,064 | module MODULE1 (VAR9,
rst,
clk,
VAR11,
VAR31);
input VAR9;
input rst;
output clk;
output VAR11;
output VAR31;
wire VAR12;
wire VAR25;
wire VAR26;
wire VAR7;
wire VAR41;
wire [7:0] VAR38;
parameter VAR1 = 1'b0;
assign clk = VAR26;
assign VAR11 = VAR7;
VAR19 VAR23
( .VAR35 (VAR9),
.VAR10 (VAR26),
.VAR36 (VAR1),
.VAR3 (... | lgpl-3.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/UE1_PORT.v | 4,563 | module MODULE1(
clk,
VAR54,
reset,
VAR60,
VAR24,
VAR17,
VAR26,
VAR69,
VAR21,
VAR73,
VAR58,
VAR42,
VAR68,
VAR49,
VAR55,
VAR56,
VAR65,
VAR10,
VAR35,
VAR39,
VAR51,
VAR46,
VAR6,
VAR22,
VAR27,
address,
write,
read,
VAR59,
VAR63,
VAR36);
input clk;
input VAR54;
input VAR60;
input reset;
input VAR73;input [133:0] VAR58;
outpu... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/FBModule.v | 7,971 | module MODULE1(
input clk,
input VAR69,
input [1:0] sel,
input signed [12:0] VAR101,
input signed [12:0] VAR14,
input signed [12:0] VAR43,
input signed [12:0] VAR21,
input signed [12:0] VAR98,
input signed [12:0] VAR85,
input [7:0] VAR77,
input [7:0] VAR87,
input signed [12:0] VAR44,
input VAR7,
input VAR46,
input [6:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.behavioral.v | 1,919 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR2 ,
VAR11 ,
VAR3,
VAR13
);
output VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR11 ;
input VAR3;
input VAR13;
wire VAR6 ;
wire VAR5 ;
wire VAR14;
or VAR10 (VAR6 , VAR2, VAR9 );
and VAR8 (VAR5 , VAR6, VAR11 );
VAR12 VAR4 (VAR14, VAR5, VAR3, VAR13);
buf VAR1 (VAR7 , VAR14 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b_4.v | 2,136 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR3,
VAR1,
VAR7 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR3;
input VAR1;
input VAR7 ;
input VAR4 ;
VAR9 VAR8 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6 ,
VAR2,
VAR5
);
output VAR6 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand3/sky130_fd_sc_hd__nand3.blackbox.v | 1,260 | module MODULE1 (
VAR3,
VAR5,
VAR2,
VAR6
);
output VAR3;
input VAR5;
input VAR2;
input VAR6;
supply1 VAR4;
supply0 VAR7;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc.blackbox.v | 1,335 | module MODULE1 (
VAR5 ,
VAR7,
VAR4
);
output VAR5 ;
input VAR7;
input VAR4 ;
supply1 VAR1;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core.v | 16,593 | module MODULE1 (
input wire clk, input wire reset, input wire [7:0] VAR14, output wire [31:0] VAR11, input wire VAR54, input wire [31:0] VAR38, input wire VAR6, output wire VAR29, input wire VAR3, input wire VAR9, input wire VAR8, input wire VAR43, output wire VAR1, output wire VAR42, input wire [7:0] VAR7, input wire ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.functional.pp.v | 1,469 | module MODULE1( VAR13, VAR16, VAR5, VAR9, VAR10, VAR7, VAR3 );
input VAR5, VAR16, VAR9, VAR10;
inout VAR7, VAR3;
output VAR13;
wire VAR17;
not VAR18( VAR17, VAR5 );
wire VAR11;
not VAR8( VAR11, VAR16 );
wire VAR14;
and VAR15( VAR14, VAR17, VAR11 );
wire VAR12;
not VAR1( VAR12, VAR9 );
wire VAR2;
not VAR4( VAR2, VAR10 )... | apache-2.0 |
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