repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v | 4,529 | module MODULE1
,parameter VAR63(VAR49)
,parameter VAR63(VAR41)
,parameter VAR63(VAR62)
,parameter VAR56 = 1
,parameter VAR29 = 0
)
(input VAR52
,input VAR44
,input [VAR56-1:0][VAR16(VAR47)-1:0] VAR28
,output [VAR56-1:0][VAR16(VAR47)-1:0] VAR69
,input [VAR16(VAR47)-1:0] VAR61
,output [VAR16(VAR47)-1:0] VAR7
);
VAR5 [VAR... | bsd-3-clause |
hoglet67/CoPro6502 | src/m32632/DP_FPU.v | 53,771 | module MODULE5 ( VAR38, VAR102, VAR133, VAR199, VAR139, VAR179,
VAR45, VAR191, VAR119, VAR131, VAR170, VAR77, VAR80 );
input [1:0] VAR38;
input VAR102,VAR133;
input [1:0] VAR199;
input [31:0] VAR139,VAR179;
output [52:32] VAR45,VAR191;
output [31:0] VAR119,VAR131;
output VAR170,VAR77,VAR80;
reg [31:0] VAR119,VAR131;
as... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_fp_add_double.v | 120,439 | module MODULE1
(
VAR11,
VAR3,
VAR7,
VAR2,
VAR14,
VAR5) ;
input VAR11;
input VAR3;
input VAR7;
input [54:0] VAR2;
input [5:0] VAR14;
output [54:0] VAR5;
tri0 VAR11;
tri1 VAR3;
tri0 VAR7;
reg [0:0] VAR13;
reg [54:0] VAR10;
wire [6:0] VAR12;
wire VAR8;
wire [31:0] VAR6;
wire [384:0] VAR9;
wire [5:0] VAR1;
wire [329:0] VAR... | mit |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_character_lcd_communication.v | 9,935 | module MODULE1 (
clk,
reset,
VAR11,
enable,
VAR26,
VAR17,
VAR20,
VAR5,
VAR32,
VAR16,
VAR6,
VAR14,
VAR34,
VAR18,
VAR30,
VAR4
);
parameter VAR13 = 7'h7F; parameter VAR12 = 7; parameter VAR33 = 7'h01;
parameter VAR22 = 3; parameter VAR29 = 15; parameter VAR15 = 1; parameter VAR23 = 4; parameter VAR3 = 4'h1;
input clk;
inp... | mit |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pll/niosii/synthesis/submodules/niosii_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,487 | module MODULE1 (
VAR29,
VAR47,
clk,
VAR15,
VAR33,
VAR49,
VAR39,
VAR14,
VAR7,
VAR50,
VAR34,
VAR26,
VAR20,
VAR11,
VAR40,
VAR19,
VAR48,
VAR32,
VAR27,
VAR5,
VAR36,
VAR3,
VAR24,
VAR41,
VAR37,
VAR9,
VAR10,
VAR43,
VAR22,
VAR6,
VAR53,
VAR57,
VAR1
)
;
output [ 37: 0] VAR36;
output VAR3;
output VAR24;
output VAR41;
output VAR37;... | mit |
dawsonjon/fpu | long_to_double/long_to_double.v | 2,849 | module MODULE1(
VAR16,
VAR4,
VAR27,
clk,
rst,
VAR21,
VAR24,
VAR5);
input clk;
input rst;
input [63:0] VAR16;
input VAR4;
output VAR5;
output [63:0] VAR21;
output VAR24;
input VAR27;
reg VAR1;
reg [63:0] VAR26;
reg VAR22;
reg VAR6;
reg [2:0] state;
parameter VAR25 = 3'd0,
VAR12 = 3'd1,
VAR23 = 3'd2,
VAR19 = 3'd3,
VAR2 =... | mit |
myriadrf/A2300 | hdl/wca/hal/WcaInterruptIF.v | 3,627 | module MODULE1
(
input wire VAR2, input wire reset, input wire [7:0] VAR3,
output wire VAR8,
input wire [11:0] VAR10, inout wire [7:0] VAR15 );
parameter VAR14=0;
wire [7:0] VAR9;
wire [7:0] VAR13;
wire [7:0] VAR1;
wire VAR7;
assign VAR7 = (VAR3[7] & VAR9[7]) | (VAR3[6] & VAR9[6])
| (VAR3[5] & VAR9[5]) | (VAR3[4] & VAR... | gpl-2.0 |
HarmonInstruments/verilog | math/dual_mult_add.v | 1,628 | module MODULE1
(
input VAR10,
input VAR7,
input VAR9, input signed [24:0] VAR16,
input signed [17:0] VAR5,
input signed [24:0] VAR13,
input signed [17:0] VAR3,
output signed [47:0] VAR20
);
wire [47:0] VAR21;
VAR15 #(.VAR8(1), .VAR18(1)) VAR4
(
.VAR10(VAR10),
.VAR17(VAR7),
.VAR14(1'b1),
.VAR11(1'b1),
.VAR12(1'b1),
.VAR... | gpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_w_axi3_conv.v | 10,418 | module MODULE1 #
(
parameter VAR30 = "none",
parameter integer VAR26 = 1,
parameter integer VAR29 = 32,
parameter integer VAR34 = 32,
parameter integer VAR17 = 0,
parameter integer VAR40 = 1,
parameter integer VAR23 = 1,
parameter integer VAR18 = 1
)
(
input wire VAR14,
input wire VAR12,
input wire VAR9,
input wire [VA... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/example_design/rtl/traffic_gen/mcb_flow_control.v | 17,386 | module MODULE1 #
(
parameter VAR9 = 100,
parameter VAR14 = "VAR45"
)
(
input VAR19,
input [9:0] VAR64,
output reg VAR48,
input VAR24,
input [2:0] VAR18,
input [31:0] VAR27,
input [5:0] VAR34,
input VAR15,
output reg [2:0] VAR20,
output reg [31:0] VAR36,
output reg [5:0] VAR31,
output VAR49, input VAR53,
input VAR6,
out... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latq/gf180mcu_fd_sc_mcu9t5v0__latq_1.behavioral.v | 1,718 | module MODULE1( VAR3, VAR8, VAR10 );
input VAR8, VAR3;
output VAR10;
reg VAR9;
VAR4 VAR5(.VAR3(VAR3),.VAR8(VAR8),.VAR10(VAR10),.VAR9(VAR9));
VAR4 VAR6(.VAR3(VAR3),.VAR8(VAR8),.VAR10(VAR10),.VAR9(VAR9));
not VAR2(VAR7,VAR8);
buf VAR1(VAR11,VAR8); | apache-2.0 |
XCopter-HSU/XCopter | documentations/Bumblebee_Documentation/SoPC/NIOS_MCAPI_Base_v07/soc_system/synthesis/submodules/soc_system_cpu_s0_jtag_debug_module_tck.v | 8,218 | module MODULE1 (
VAR39,
VAR10,
VAR4,
VAR18,
VAR2,
VAR35,
VAR29,
VAR37,
VAR7,
VAR16,
VAR26,
VAR9,
VAR19,
VAR33,
VAR28,
VAR22,
VAR20,
VAR30,
VAR34,
VAR6,
VAR13,
VAR12,
VAR25,
VAR36,
VAR11,
VAR15,
VAR32,
VAR1,
VAR3,
VAR24,
VAR27
)
;
output [ 1: 0] VAR32;
output VAR1;
output [ 37: 0] VAR3;
output VAR24;
output VAR27;
input... | gpl-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_fpga_m/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.v | 7,805 | module MODULE1 #(
parameter VAR23 = 0, parameter VAR49 = 0,
parameter VAR59 = 0,
parameter VAR62 = 0,
parameter VAR31 = 0,
parameter VAR35 = 0, parameter VAR52 = 50000 ) (
input wire VAR47,
input wire VAR4,
input wire VAR28,
output wire VAR13,
input wire VAR9,
input wire VAR53,
input wire VAR5,
input wire VAR29,
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_sn.blackbox.v | 1,546 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR2 ,
VAR1 ,
VAR4 ,
VAR5,
VAR3 ,
VAR9 ,
VAR8
);
output VAR6 ;
input VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR4 ;
input VAR5;
input VAR3 ;
input VAR9 ;
input VAR8 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/math/flt_mult_comb.v | 2,908 | module MODULE1
(
input [31:0] VAR3,
input [31:0] VAR8,
output reg [31:0] VAR4
);
reg [47:0] VAR10; reg VAR1; reg [7:0] VAR2; reg VAR11;
reg VAR12; reg [7:0] VAR7; reg VAR5;
reg VAR6; reg [24:0] VAR9; reg VAR13;
always @* VAR13 = (~VAR6 & ~VAR9[24]);
always @* begin
VAR10 = {1'b1,VAR3[22:0]} * {1'b1,VAR8[22:0]};
VAR1 = ... | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_two_fifo.v | 4,432 | module MODULE1 #(parameter VAR10(VAR41)
, parameter VAR8=0
, parameter VAR26=0
, parameter VAR21=VAR26
)
(input VAR18
, input VAR43
, output VAR7 , input [VAR41-1:0] VAR38 , input VAR32
, output VAR23 , output[VAR41-1:0] VAR16 , input VAR24 );
wire VAR14 = VAR24;
wire VAR22;
logic VAR37, VAR3;
logic VAR9, VAR17;
VAR39 ... | bsd-3-clause |
gbraad/minimig-de1 | rtl/ctrl/ctrl_flash.v | 4,603 | module MODULE1 #(
parameter VAR24 = 22, parameter VAR6 = 8, parameter VAR10 = 22, parameter VAR29 = 32, parameter VAR3 = VAR29/8, parameter VAR22 = 3, parameter VAR4 = 1 )(
input wire clk,
input wire rst,
input wire VAR21,
input wire [VAR10-1:0] VAR28,
input wire VAR12,
input wire VAR20,
input wire [VAR3-1:0] sel,
inpu... | gpl-3.0 |
audiocircuit/NCSU-Low-Power-RFID | FIFO/FIFO.v | 5,844 | module MODULE1(
input wire VAR5,
input wire en,
input wire VAR1,
input wire VAR8,
input wire read,
input wire write,
input wire [7:0] VAR11,
output reg [7:0] VAR4,
output wire VAR7,
output wire VAR10
);
reg [3:0] VAR9;
reg [3:0] VAR3;
reg [7:0] memory [0:7];
reg [7:0] VAR6;
assign VAR10 = ((VAR3[3] != VAR9[3]) &&
(VAR3... | gpl-3.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/unencoded_cam_lut_sm_lpm.v | 9,268 | module MODULE1
parameter VAR48 = 3,
parameter VAR52 = 16,
parameter VAR36 = VAR29(VAR52),
parameter VAR53 = 0, parameter VAR25 = {VAR48{1'b0}}, parameter VAR43 = {VAR46{1'b0}}, parameter VAR35 = {VAR46{1'b0}} )
( input VAR11,
input [VAR46-1:0] VAR42,
input [VAR46-1:0] VAR8,
output reg VAR17,
output reg VAR40,
output [V... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | DOS_Mario.ip_user_files/ip/dist_mem_gen_0/dist_mem_gen_0_stub.v | 1,263 | module MODULE1(VAR2, VAR1)
;
input [10:0]VAR2;
output [23:0]VAR1;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_hd__udp_dlatch_pr_pp_pg_n.blackbox.v | 1,464 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR6 ,
VAR5 ,
VAR3,
VAR4 ,
VAR2
);
output VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/snes_controller.v | 9,086 | module MODULE1(
VAR36, VAR7, VAR37, VAR38, VAR40 );
input VAR7;
input VAR38;
output VAR36;
output VAR37;
output [12:0] VAR40;
reg [12:0] VAR13; reg VAR44; reg pulse; reg VAR22; reg [17:0] VAR42;
reg [5:0] VAR12;
parameter VAR45 = 1;
parameter VAR9 = 2;
parameter VAR41 = 3;
parameter VAR11 = 4;
parameter VAR30 = 5;
para... | mit |
DreamIP/GPStudio | support/io/d5m/hdl/Line_Buffer.v | 4,524 | module MODULE1 (
VAR8,
VAR16,
VAR3,
VAR17,
VAR7,
VAR9);
input VAR8;
input VAR16;
input [11:0] VAR3;
output [11:0] VAR17;
output [11:0] VAR7;
output [11:0] VAR9;
wire [23:0] VAR4;
wire [11:0] VAR15;
wire [23:12] VAR1 = VAR4[23:12];
wire [11:0] VAR6 = VAR4[11:0];
wire [11:0] VAR9 = VAR1[23:12];
wire [11:0] VAR7 = VAR6[11... | gpl-3.0 |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-A/ltcminer_icarus.v | 8,086 | module MODULE1 (VAR74, VAR41, VAR47, VAR39, VAR62, VAR71, VAR14, VAR12, VAR35, VAR65);
function integer VAR79; input integer VAR29;
begin
VAR29 = VAR29-1;
for (VAR79=0; VAR29>0; VAR79=VAR79+1)
VAR29 = VAR29>>1;
end
endfunction
parameter VAR86 = VAR86;
parameter VAR86 = 50;
parameter VAR70 = VAR24;
parameter VAR70 = 125... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111oi/sky130_fd_sc_ms__a2111oi.behavioral.v | 1,599 | module MODULE1 (
VAR7 ,
VAR6,
VAR14,
VAR1,
VAR5,
VAR11
);
output VAR7 ;
input VAR6;
input VAR14;
input VAR1;
input VAR5;
input VAR11;
supply1 VAR13;
supply0 VAR15;
supply1 VAR8 ;
supply0 VAR3 ;
wire VAR2 ;
wire VAR10;
and VAR9 (VAR2 , VAR6, VAR14 );
nor VAR12 (VAR10, VAR1, VAR5, VAR11, VAR2);
buf VAR4 (VAR7 , VAR10 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai.pp.symbol.v | 1,359 | module MODULE1 (
input VAR9 ,
input VAR1 ,
input VAR5 ,
input VAR7 ,
output VAR8 ,
input VAR2 ,
input VAR3,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o.pp.symbol.v | 1,368 | module MODULE1 (
input VAR9 ,
input VAR5 ,
input VAR7 ,
input VAR4 ,
output VAR1 ,
input VAR3 ,
input VAR6,
input VAR8,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufinv/sky130_fd_sc_hs__bufinv.functional.pp.v | 1,680 | module MODULE1 (
VAR3,
VAR6,
VAR4 ,
VAR7
);
input VAR3;
input VAR6;
output VAR4 ;
input VAR7 ;
wire VAR2 ;
wire VAR1;
not VAR5 (VAR2 , VAR7 );
VAR10 VAR8 (VAR1, VAR2, VAR3, VAR6);
buf VAR9 (VAR4 , VAR1 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/0a0e961c932ad738/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v | 1,745 | module MODULE1(VAR10, VAR9, VAR3, VAR11, VAR6, VAR5, VAR13, VAR14, VAR8, VAR1,
VAR4, VAR12, VAR7, VAR2)
;
input VAR10;
input VAR9;
input VAR3;
input [3:0]VAR11;
input [31:0]VAR6;
input [31:0]VAR5;
output [31:0]VAR13;
input VAR14;
input VAR8;
input VAR1;
input [3:0]VAR4;
input [31:0]VAR12;
input [31:0]VAR7;
output [31:0... | mit |
DougFirErickson/parallella-hw | boards/archive/gen0/fpga/hdl/parallella_7020_top.v | 41,746 | module MODULE1 (
VAR320, VAR75, VAR332, VAR149,
VAR6, VAR267, VAR66, VAR244, VAR356, VAR276,
VAR91, VAR47, VAR228, VAR239, VAR208, VAR127,
VAR177, VAR13, VAR175, VAR291, VAR253, VAR187,
VAR382, VAR281, VAR49, VAR241, VAR8,
VAR113, VAR297, VAR43, VAR20, VAR50,
VAR225, VAR201, VAR342, VAR145, VAR305,
VAR322, VAR326, VAR9... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/ddr3_int_alt_ddrx_controller_wrapper.v | 17,925 | module MODULE1 (
VAR82,
VAR31,
VAR112,
VAR45,
VAR106,
VAR38,
VAR50,
VAR87,
VAR76,
VAR67,
VAR101,
VAR54,
VAR83,
VAR26,
VAR46,
VAR5,
VAR4,
VAR23,
VAR113,
VAR36,
VAR66,
VAR49,
VAR14,
VAR25,
VAR40,
VAR105,
VAR13,
VAR24,
VAR18,
VAR84,
VAR69,
VAR47,
VAR80,
VAR39,
VAR30,
VAR110,
VAR117,
VAR77,
VAR107,
VAR88,
VAR35,
VAR90,
VAR... | gpl-3.0 |
tmatsuya/milkymist-ml401 | cores/lm32/rtl/lm32_mc_arithmetic.v | 9,873 | module MODULE1 (
VAR12,
VAR26,
VAR17,
VAR1,
VAR28,
VAR15,
VAR5,
VAR14,
VAR22,
VAR8,
VAR11,
VAR34,
VAR35,
VAR31,
VAR7
);
input VAR12; input VAR26; input VAR17; input VAR1; VAR19 VAR33
input VAR28; input VAR15; VAR27
input VAR5; VAR27
input VAR14; input VAR22; input VAR8; VAR27
input [VAR32] VAR11;
input [VAR32] VAR34;
o... | lgpl-3.0 |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_wrap_cmd.v | 6,463 | module MODULE1 #
(
parameter integer VAR13 = 32
)
(
input wire clk ,
input wire reset ,
input wire [VAR13-1:0] VAR9 ,
input wire [7:0] VAR16 ,
input wire [2:0] VAR25 ,
input wire VAR19 ,
output wire [VAR13-1:0] VAR7 ,
input wire VAR4 ,
output reg VAR14
);
reg VAR5;
wire [11:0] VAR17;
wire [3:0] VAR10;
reg [11:0] VAR23;... | mit |
kramble/FPGA-Litecoin-Miner | experimental/DE2-115-SLOWSIXTEEN/salsaengine.v | 20,435 | module MODULE1 (VAR10, reset, din, dout, VAR17, VAR34, VAR18, VAR36 );
input VAR10;
input reset; input VAR17;
input VAR34; output VAR18;
output reg VAR36 = 1'b0;
parameter VAR45 = 8; input [VAR45-1:0] din;
output [VAR45-1:0] dout;
parameter VAR14 = 12;
parameter VAR49 = 16;
function integer VAR9; input integer VAR102;
... | gpl-3.0 |
ptracton/wb_soc_template | rtl/ZIP/rtl/wbdblpriarb.v | 9,050 | module MODULE1(VAR3, VAR30,
VAR13,VAR35,VAR33,VAR34,VAR16,VAR15, VAR19, VAR14, VAR17, VAR22, VAR28,
VAR8,VAR11,VAR9,VAR21,VAR26,VAR10, VAR18, VAR40, VAR4, VAR41, VAR23,
VAR2, VAR5, VAR36, VAR29, VAR38, VAR6, VAR37, VAR27,
VAR24, VAR25, VAR20);
parameter VAR1=32, VAR31=32;
input wire VAR3, VAR30;
input wire VAR13, VAR35... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_front_side_bus_hop_in_no_fc.v | 1,260 | module MODULE1 #(parameter VAR12(VAR10))
( input VAR1
, input VAR3
, input [VAR10-1:0] VAR4
, input VAR8
, output [1:0][VAR10-1:0] VAR9
, output [1:0] VAR5
, input VAR7
);
logic [VAR10-1:0] VAR11;
logic VAR14;
assign VAR9[0] = VAR11;
assign VAR5[0] = VAR14;
assign VAR9[1] = VAR11;
assign VAR5[1] = VAR14 & VAR7;
VAR2 #(... | bsd-3-clause |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/02 verilog/FSM.v | 1,694 | module MODULE1(reset,clk,enable,VAR7,VAR4,VAR1,VAR5, VAR2);
input wire reset;
input wire clk;
input wire enable;
input wire VAR7;
input wire VAR4;
output reg VAR1;
output reg VAR5;
output reg VAR2;
localparam VAR6 = 2'b00;
localparam VAR8 = 2'b01;
localparam VAR3 = 2'b11;
reg [1:0] VAR9 = VAR6;
reg [1:0] state = VAR6;
... | gpl-3.0 |
freecores/tiny_tate_bilinear_pairing | group_size_is_911_bits/rtl/pe.v | 4,760 | module MODULE4(clk, reset, VAR10, d0, d1, d2, out);
input clk;
input reset;
input [10:0] VAR10;
input [VAR53:0] d0;
input [VAR8:0] d1, d2;
output [VAR8:0] out;
reg [VAR53:0] VAR14;
reg [VAR8:0] VAR1, VAR39, VAR59;
wire [1:0] VAR18, VAR38, VAR66;
wire [VAR8:0] MODULE6, VAR65, VAR6,
VAR45, VAR63, VAR49, VAR32, VAR22, VAR... | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/vfabric_counter_fifo.v | 2,394 | module MODULE1 (
VAR5, VAR9, VAR3, VAR8, VAR1,
VAR13, VAR12
);
parameter VAR11=2048;
localparam VAR6 = VAR10(VAR11)+1;
input VAR5, VAR9, VAR3;
input VAR8, VAR12;
output VAR13, VAR1;
reg [VAR6-1:0] VAR4;
reg [VAR6:0] VAR14;
wire VAR7, VAR2;
assign VAR7 = VAR8;
assign VAR2 = VAR13 & ~VAR12;
always @(posedge VAR5 or neged... | mit |
neale/MachX02 | Voltmeter/SlowClock.v | 1,267 | module MODULE1(
input VAR1, input VAR2,
output reg VAR4
);
reg [14:0] VAR3;
always @ (posedge VAR1, negedge VAR2)
begin
VAR3 <= VAR3 + 1; if(!VAR2)
begin
VAR4 <= 0;
VAR3 <= 0; end
else
if(VAR3 >= 1800) begin VAR4 <= ~VAR4;
VAR3 <= 0; end
end
endmodule | mit |
hsnuonly/PikachuVolleyFPGA | VGA.ip_user_files/ip/shadow_pixel/shadow_pixel_stub.v | 1,307 | module MODULE1(VAR1, VAR2, VAR5, VAR3, VAR4)
;
input VAR1;
input [0:0]VAR2;
input [10:0]VAR5;
input [11:0]VAR3;
output [11:0]VAR4;
endmodule | gpl-3.0 |
ultraembedded/riscv | top_cache_axi/src_v/dcache_if_pmem.v | 8,977 | module MODULE2
(
input VAR13
,input VAR37
,input [ 31:0] VAR56
,input [ 31:0] VAR53
,input VAR46
,input [ 3:0] VAR32
,input VAR29
,input [ 10:0] VAR40
,input VAR12
,input VAR1
,input VAR19
,input VAR8
,input VAR3
,input VAR44
,input [ 31:0] VAR45
,output [ 31:0] VAR17
,output VAR34
,output VAR18
,output VAR4
,output [ ... | bsd-3-clause |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/V2NFC100DDR/src/NPM_Toggle_DO_tADL_DDR100.v | 20,619 | module MODULE1
(
parameter VAR30 = 4
)
(
VAR1 ,
VAR41 ,
VAR15 ,
VAR27 ,
VAR38 ,
VAR4 ,
VAR5 ,
VAR22 ,
VAR26 ,
VAR43 ,
VAR39 ,
VAR51 ,
VAR17 ,
VAR46 ,
VAR48 ,
VAR13 ,
VAR34 ,
VAR32 ,
VAR10
);
input VAR1 ;
input VAR41 ;
output VAR15 ;
output VAR27 ;
input VAR38 ;
input VAR4 ;
input [VAR30 - 1:0] VAR5 ;
input [31:0] VAR22... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai_1.v | 2,314 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR3 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR4,
VAR2
);
output VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR4;
input VAR2;
VAR10 VAR9 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 ... | apache-2.0 |
bunnie/novena-gpbb-fpga | novena-gpbb.srcs/sources_1/imports/imports/adc10cs022.v | 3,776 | module MODULE1(
output wire VAR35,
output wire VAR4,
input wire VAR36,
output wire VAR18,
output reg [9:0] VAR10,
input wire [2:0] VAR22,
output reg VAR33,
input wire VAR9,
input wire VAR7,
input wire reset
);
parameter VAR15 = 5'b1 << 0;
parameter VAR2 = 5'b1 << 1;
parameter VAR34 = 5'b1 << 2;
parameter VAR13 = 5'b1 <... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp_2.v | 2,262 | module MODULE1 (
VAR5,
VAR4 ,
VAR7,
VAR6 ,
VAR10,
VAR2,
VAR3 ,
VAR8
);
output VAR5;
input VAR4 ;
input VAR7;
input VAR6 ;
input VAR10;
input VAR2;
input VAR3 ;
input VAR8 ;
VAR9 VAR1 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
... | apache-2.0 |
cpulabs/gci-std-display | rtl/vram_controller/gci_std_display_vram_controller_sram.v | 10,815 | module MODULE1 #(
parameter VAR24 = 20,
parameter VAR75 = 640,
parameter VAR72 = 480
)(
input wire VAR41,
input wire VAR67,
input wire VAR19,
input wire VAR81,
input wire [VAR24-1:0] VAR58,
input wire [15:0] VAR53,
output wire VAR61,
input wire VAR27,
input wire VAR51,
output wire [9:0] VAR7,
output wire [9:0] VAR34,
o... | bsd-2-clause |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/syncreg.v | 5,881 | module MODULE1 (
VAR16,
VAR14,
VAR3,
VAR10,
VAR8
);
input VAR16;
input VAR14;
input VAR3;
input [3:0] VAR10;
output [3:0] VAR8;
reg [3:0] VAR11;
reg [3:0] VAR4;
reg VAR7;
reg VAR6;
wire VAR2;
wire VAR21;
wire VAR18;
wire VAR1;
wire [3:0] VAR8;
assign VAR21 = VAR2 & VAR1;
assign VAR2 = !(VAR10 == VAR11);
assign VAR8 = V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvpwrvgnd/sky130_fd_sc_hs__tapvpwrvgnd.functional.pp.v | 1,149 | module MODULE1 (
VAR1,
VAR2
);
input VAR1;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4bb/sky130_fd_sc_ms__nand4bb.functional.v | 1,436 | module MODULE1 (
VAR10 ,
VAR7,
VAR6,
VAR4 ,
VAR1
);
output VAR10 ;
input VAR7;
input VAR6;
input VAR4 ;
input VAR1 ;
wire VAR3;
wire VAR9;
nand VAR2 (VAR3, VAR1, VAR4 );
or VAR5 (VAR9, VAR6, VAR7, VAR3);
buf VAR8 (VAR10 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp_1.v | 2,615 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR10 ,
VAR11 ,
VAR3 ,
VAR5 ,
VAR4,
VAR8 ,
VAR6 ,
VAR13 ,
VAR9
);
output VAR1 ;
output VAR7 ;
input VAR10 ;
input VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR4;
input VAR8 ;
input VAR6 ;
input VAR13 ;
input VAR9 ;
VAR2 VAR12 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.VAR3(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.v | 2,345 | module MODULE1 (
VAR8 ,
VAR10 ,
VAR2 ,
VAR7 ,
VAR5 ,
VAR11,
VAR6,
VAR4 ,
VAR9
);
output VAR8 ;
input VAR10 ;
input VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR11;
input VAR6;
input VAR4 ;
input VAR9 ;
VAR3 VAR1 (
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR6(VAR6),
.VAR4(VAR4),
.... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ffu/rtl/sparc_ffu_part_add32.v | 1,772 | module MODULE1 (
VAR3,
VAR2, VAR5, VAR7, VAR1
) ;
input [31:0] VAR2;
input [31:0] VAR5;
input VAR7;
input VAR1;
output [31:0] VAR3;
wire VAR6; wire VAR4;
assign VAR4 = (VAR1)? VAR6: VAR7;
assign {VAR6, VAR3[15:0]} = VAR2[15:0]+VAR5[15:0]+{15'b0,VAR7};
assign VAR3[31:16] = VAR2[31:16]+VAR5[31:16]+{15'b0,VAR4};
endmodule | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_NVMeHostController_0_0/src/pcie_7x_0_core_top/source/pcie_7x_0_core_top_axi_basic_top.v | 11,075 | module MODULE1 #(
parameter VAR54 = 128, parameter VAR48 = "VAR35", parameter VAR34 = "VAR43", parameter VAR17 = "VAR43", parameter VAR25 = 1,
parameter VAR19 = (VAR54 == 128) ? 2 : 1, parameter VAR44 = VAR54 / 8 ) (
input [VAR54-1:0] VAR3, input VAR46, output VAR58, input [VAR44-1:0] VAR57, input VAR39, input [3:0] VA... | gpl-3.0 |
KestrelComputer/polaris | processor/docs/example/output_csr.v | 2,565 | module MODULE1(
input [11:0] VAR8,
output VAR7,
output [63:0] VAR12,
input [63:0] VAR9,
input VAR14,
input VAR5,
input VAR1
);
wire VAR4 = (VAR8 == 12'h0FF);
assign VAR7 = VAR4;
wire [63:0] VAR11 = {64'h0000000000000004};
assign VAR12 = (VAR4 ? VAR11 : 0);
wire write = VAR4 & VAR5;
wire VAR10 = write ? VAR9[11] : 1'b0;... | mpl-2.0 |
alexforencich/verilog-cam | rtl/cam.v | 3,296 | module MODULE1 #(
parameter VAR9 = 64,
parameter VAR7 = 5,
parameter VAR1 = "VAR8",
parameter VAR10 = 4
)
(
input wire clk,
input wire rst,
input wire [VAR7-1:0] VAR19,
input wire [VAR9-1:0] VAR13,
input wire VAR4,
input wire VAR12,
output wire VAR6,
input wire [VAR9-1:0] VAR14,
output wire [2**VAR7-1:0] VAR15,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2.pp.blackbox.v | 1,254 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR2 ,
VAR4,
VAR1,
VAR5 ,
VAR3
);
output VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR3 ;
endmodule | apache-2.0 |
dailypips/miaow | src/verilog/rtl/issue/branch_wait.v | 1,671 | module MODULE1
(
VAR4,
clk, rst, VAR20, VAR2, VAR9, VAR8,
VAR17
);
input clk, rst;
input VAR20, VAR2;
input [VAR6-1:0] VAR9;
input VAR8;
input [VAR6-1:0] VAR17;
output [VAR13-1:0] VAR4;
wire VAR10;
wire [VAR13-1:0] VAR14,
VAR21;
wire [VAR13-1:0] VAR18, VAR16;
assign VAR4 = VAR18;
VAR5 VAR11
(
.VAR12(VAR9),
.out(VAR14),... | bsd-3-clause |
BigEd/beeb816 | rtl/level1b_mk2_m.v | 23,891 | module MODULE1 (
input [15:0] VAR77,
input VAR49,
input VAR93,
input VAR90,
input VAR51,
input VAR27,
input VAR131,
input VAR38,
input VAR25,
input [1:0] VAR58,
output [1:0] VAR121,
input VAR117,
input VAR74,
input VAR61,
output VAR30,
output VAR8,
output VAR56,
output VAR2,
output [15:0] VAR9,
input VAR26,
input VAR48... | lgpl-2.1 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_of_pre_fifo.v | 7,040 | module MODULE1 #
(
parameter VAR8 = 100, parameter VAR10 = 4, parameter VAR15 = 32 )
(
input clk, input rst, input VAR21, input VAR6, input [VAR15-1:0] din, output VAR3, output [VAR15-1:0] dout, output VAR12 );
localparam VAR7
= (VAR10 == 2) ? 1 :
((VAR10 == 3) || (VAR10 == 4)) ? 2 :
(((VAR10 == 5) || (VAR10 == 6) ||
(... | mit |
bigeagle/riffa | fpga/xilinx/vc709/VC709_Gen2x8If128/hdl/VC709Gen2x8If128.v | 26,210 | module MODULE1
parameter VAR188 = 8,
parameter VAR123 = 128,
parameter VAR103 = 256,
parameter VAR10 = 6
)
(output [(VAR188 - 1) : 0] VAR132,
output [(VAR188 - 1) : 0] VAR176,
input [(VAR188 - 1) : 0] VAR76,
input [(VAR188 - 1) : 0] VAR196,
output [7:0] VAR20,
input VAR94,
input VAR221,
input VAR40
);
wire VAR133;
wire... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3_0.v | 2,164 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR7,
VAR1,
VAR2 ,
VAR6
);
output VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR7;
input VAR1;
input VAR2 ;
input VAR6 ;
VAR10 VAR5 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (... | apache-2.0 |
bbrown1867/ObjectTracking | hw/common/old_terasic_modules/td_detect.v | 1,046 | module MODULE1
(
output VAR6,
input VAR1,
input VAR8,
input VAR2
);
reg VAR7;
reg VAR3;
reg VAR5;
reg [7:0] VAR4;
assign VAR6 = VAR7 || VAR3;
always@(posedge VAR8 or negedge VAR2) begin
if(!VAR2)
begin
VAR5 <= 1'b0;
VAR4 <= 4'h0;
VAR7 <= 1'b0;
VAR3 <= 1'b0;
end
else
begin
VAR5 <= VAR1;
if(!VAR1) VAR4 <= VAR4+1'b1;
end
... | mit |
jncronin/jca | spi_program/spi2.v | 3,854 | module MODULE1(clk, VAR1, VAR8, VAR11, VAR2, VAR12, VAR5, VAR13, VAR6, VAR7);
input clk;
input [31:0] VAR1;
output [7:0] VAR8;
input [7:0] VAR11;
input VAR2;
output VAR12;
output VAR5;
output VAR13;
input VAR6;
input [1:0] VAR7;
reg [7:0] VAR3 = 8'hff; reg [7:0] VAR9 = 8'h00;
reg VAR5 = 0;
reg [31:0] VAR10 = 32'd0;
reg... | mit |
INTI-CMNB/Lattuino_IP_Core | devices/tmcounter.v | 8,488 | module MODULE1
parameter VAR34=24,
parameter VAR8=1
)
(
input VAR32, input VAR33, input [2:0] VAR25, output [7:0] VAR22, input [7:0] VAR31, input VAR1, input VAR11, output VAR36, output [5:0] VAR16, output [5:0] VAR3 );
localparam integer VAR12=VAR26(VAR34);
reg [31:0] VAR4=0;
reg [9:0] VAR18=0;
wire VAR30;
reg [31:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb_1.v | 2,325 | module MODULE1 (
VAR6 ,
VAR9 ,
VAR3 ,
VAR11 ,
VAR10 ,
VAR4,
VAR1,
VAR5 ,
VAR2
);
output VAR6 ;
input VAR9 ;
input VAR3 ;
input VAR11 ;
input VAR10 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR2 ;
VAR8 VAR7 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/ha/sky130_fd_sc_ls__ha.pp.blackbox.v | 1,276 | module MODULE1 (
VAR5,
VAR1 ,
VAR8 ,
VAR6 ,
VAR2,
VAR4,
VAR3 ,
VAR7
);
output VAR5;
output VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR2;
input VAR4;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
aabdelfattah/alhaitham-hardware | Sdram_Control/sdr_data_path.v | 2,652 | module MODULE1(
VAR2,
VAR1,
VAR7,
VAR3,
VAR5,
VAR6
);
input VAR2; input VAR1; input [VAR4-1:0] VAR7; input [VAR4/8-1:0] VAR3; output [VAR4-1:0] VAR5;
output [VAR4/8-1:0] VAR6; reg [VAR4/8-1:0] VAR6;
always @(posedge VAR2 or negedge VAR1)
begin
if (VAR1 == 0)
VAR6 <= VAR4/8-1'hF;
end
else
VAR6 <= VAR3;
end
assign VAR5 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/tap/sky130_fd_sc_ms__tap.functional.v | 1,056 | module MODULE1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxtp/sky130_fd_sc_hd__edfxtp.behavioral.pp.v | 2,182 | module MODULE1 (
VAR11 ,
VAR20 ,
VAR3 ,
VAR21 ,
VAR16,
VAR2,
VAR8 ,
VAR17
);
output VAR11 ;
input VAR20 ;
input VAR3 ;
input VAR21 ;
input VAR16;
input VAR2;
input VAR8 ;
input VAR17 ;
wire VAR14 ;
reg VAR9 ;
wire VAR18 ;
wire VAR4 ;
wire VAR6;
wire VAR5 ;
wire VAR19 ;
wire VAR15 ;
VAR7 VAR10 (VAR5, VAR14, VAR18, VAR4 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.behavioral.pp.v | 2,260 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR12 ,
VAR11 ,
VAR10 ,
VAR17 ,
VAR4,
VAR9,
VAR16 ,
VAR6
);
output VAR8 ;
input VAR3 ;
input VAR12 ;
input VAR11 ;
input VAR10 ;
input VAR17 ;
input VAR4;
input VAR9;
input VAR16 ;
input VAR6 ;
wire VAR18 ;
wire VAR15 ;
wire VAR5 ;
wire VAR19;
nand VAR7 (VAR18 , VAR12, VAR3, VAR11 );
nand... | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_dfilt1.v | 4,019 | module MODULE1 (
input VAR11 , input VAR15 , input [ 14-1: 0] VAR10 , output [ 14-1: 0] VAR8 ,
input [ 18-1: 0] VAR12 , input [ 25-1: 0] VAR25 , input [ 25-1: 0] VAR29 , input [ 25-1: 0] VAR9 );
reg [ 18-1: 0] VAR13 ;
reg [ 25-1: 0] VAR24 ;
reg [ 25-1: 0] VAR27 ;
reg [ 25-1: 0] VAR28 ;
always @(posedge VAR11) begin
VAR... | mit |
zeldin/iceGDROM | fpga/source/cdda/cdda_interface.v | 4,706 | module MODULE1 (
output VAR34,
output VAR3,
output VAR55,
input clk,
input rst,
input[10:0] VAR31,
input[31:0] VAR43,
output[7:0] VAR19,
input VAR18,
input VAR57,
input[3:0] VAR15,
output VAR53,
input[7:0] VAR11,
input[8:0] VAR54,
input VAR27,
);
parameter VAR32 = 33868800;
assign VAR53 = 1'b0;
reg [7:0] VAR49;
assign ... | gpl-3.0 |
hcabrera-/atto | rtl/inport.v | 1,380 | module MODULE1 #(parameter VAR9 = 2, parameter VAR6 = 2)
(
input wire VAR16,
input wire VAR3,
input wire [1:0] VAR10,
input wire [47:0] VAR8,
output wire VAR1,
output wire VAR4,
output wire VAR11,
output wire [47:0] VAR15
);
wire VAR12;
reg [47:0] VAR18 = 48'b0;
reg VAR14;
VAR7 VAR17
(
.VAR16 (VAR16),
.VAR3 (VAR3),
.VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or4/gf180mcu_fd_sc_mcu7t5v0__or4_1.behavioral.v | 1,317 | module MODULE1( VAR3, VAR7, VAR4, VAR6, VAR8 );
input VAR3, VAR7, VAR4, VAR6;
output VAR8;
VAR5 VAR1(.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8));
VAR5 VAR2(.VAR3(VAR3),.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8)); | apache-2.0 |
chriz2600/DreamcastHDMI | Core/source/maple_bus/maple_in.v | 5,235 | module MODULE1(
input rst,
input clk,
input VAR40,
input VAR41,
input VAR30,
output VAR24,
output VAR5,
output VAR8,
input VAR17,
input VAR38,
output [7:0] VAR23,
output VAR26
);
assign VAR24 = VAR3;
assign VAR5 = VAR19;
assign VAR8 = VAR33;
assign VAR23 = { VAR34, VAR18 };
assign VAR26 = VAR35;
reg VAR9, VAR31;
reg VA... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/memc_flow_vcontrol.v | 20,867 | module MODULE1 #
(
parameter VAR58 = 100,
parameter VAR37 = 4,
parameter VAR83 = 32,
parameter VAR19 = 6,
parameter VAR29 = 4,
parameter VAR3 = "VAR73",
parameter VAR74 = "VAR51"
)
(
input VAR80,
input [9:0] VAR47,
input [3:0] VAR82,
input [5:0] VAR14,
output reg VAR44,
input VAR53,
input [2:0] VAR46,
input [31:0] VAR1... | lgpl-3.0 |
sam-falvo/kestrel | cores/KCP53K/cpu2/rtl/verilog/alu.v | 2,624 | module MODULE1(
input [63:0] VAR36,
input [63:0] VAR16,
input VAR27,
input VAR13,
input VAR28,
input VAR29,
input VAR7,
input VAR8,
input VAR31,
input VAR6, input VAR33, output [63:0] VAR43,
output VAR40,
output VAR41,
output VAR45
);
wire [63:0] VAR23 = VAR16 ^ ({64{VAR7}});
wire [63:0] VAR11 = VAR36[62:0] + VAR23[62:... | mpl-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_phy_alt_mem_phy_dq_dqs.v | 30,291 | module MODULE1
(
VAR63,
VAR46,
VAR21,
VAR27,
VAR11,
VAR18,
VAR34,
VAR66,
VAR45,
VAR49,
VAR67,
VAR15,
VAR22,
VAR36,
VAR68,
VAR10,
VAR13,
VAR52,
VAR5,
VAR4,
VAR56,
VAR57,
VAR38,
VAR24,
VAR26,
VAR60,
VAR30,
VAR25) ;
input [7:0] VAR63;
input [7:0] VAR46;
output [7:0] VAR21;
output [7:0] VAR27;
input [7:0] VAR11;
output [7:... | gpl-3.0 |
Anirudh94/Connect4-FPGA | Connect4/player1_bb.v | 4,903 | module MODULE1 (
address,
VAR1,
VAR2);
input [10:0] address;
input VAR1;
output [2:0] VAR2;
tri1 VAR1;
endmodule | mit |
P3Stor/P3Stor | pcie/core/pcie_bram_v6.v | 11,438 | module MODULE1
parameter VAR4 = 0, parameter VAR13 = 0 )
(
input VAR14, input VAR1,
input VAR12, input [12:0] VAR7, input [VAR13 - 1:0] VAR18,
input VAR2, input VAR3, input [12:0] VAR6,
output [VAR13 - 1:0] VAR8 );
localparam VAR5 = ((VAR13 == 4) ? 12 :
(VAR13 == 9) ? 11 :
(VAR13 == 18) ? 10 :
(VAR13 == 36) ? 9 :
8
);
... | gpl-2.0 |
racerxdl/SuperINT | Slave Codes/FPGA/PWMCore.v | 1,599 | module MODULE1(
input clk,
input [15:0] period,
input [7:0] VAR1,
input enable,
input reset,
output VAR4
);
reg [15:0] VAR3 = 0;
wire rst = ~reset;
reg VAR2 = 0;
always @(posedge clk)
begin
if(enable & ~rst )
begin
if(VAR3 <= VAR1)
VAR2 <= 1;
end
else
VAR2 <= 0;
if(VAR3 == period)
VAR3 <= 0;
end
else
VAR3 <= VAR3 +1;
e... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fa/sky130_fd_sc_lp__fa.blackbox.v | 1,293 | module MODULE1 (
VAR8,
VAR6 ,
VAR9 ,
VAR5 ,
VAR4
);
output VAR8;
output VAR6 ;
input VAR9 ;
input VAR5 ;
input VAR4 ;
supply1 VAR1;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/spi/spi_slave.v | 9,284 | module MODULE1
parameter VAR5 = VAR21-2,
parameter VAR15 = 8'hA7, parameter VAR44 = 3)
( input VAR55,
input VAR49,
output reg VAR40 = 1'b0,
output reg VAR26 = 1'b0,
output VAR19,
input VAR24,
input VAR9, input VAR51, input VAR48, output reg [VAR5:0] VAR13,
input [VAR42:0] VAR38,
output reg [VAR42:0] VAR3,
output VAR34,... | lgpl-3.0 |
zhangly/azpr_cpu | rtl/cpu/rtl/ex_reg.v | 4,731 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR10] VAR27, input wire VAR12,
input wire VAR33, input wire VAR18, input wire VAR17,
input wire [VAR39] VAR41, input wire VAR21, input wire VAR35, input wire [VAR14] VAR9, input wire [VAR10] VAR31, input wire [VAR32] VAR7, input wire [VAR29] VAR24, input w... | mit |
asicguy/gplgpu | hdl/ramdac_sp/pal_ctl.v | 6,474 | module MODULE1
(
VAR33,
VAR37,
VAR13,
VAR25,
VAR32,
VAR10,
VAR28,
VAR14,
VAR21,
VAR6, VAR1,
VAR26,
VAR31, VAR2,
VAR20,
VAR18 , VAR27,
VAR22,
VAR34,
VAR30,
VAR24
);
input VAR33,
VAR37,
VAR13,
VAR25,
VAR32,
VAR10,
VAR28;
input [7:0] VAR14, VAR21,
VAR6,
VAR24;
input [7:0] VAR2, VAR20,
VAR18;
input [2:0] VAR27;
output [7:0... | gpl-3.0 |
mballance/wb_dma | rtl/wb_dma_ch_sel.v | 54,392 | module MODULE1(clk, rst,
VAR132, VAR2, VAR6,
VAR320, VAR346, VAR29, VAR59, VAR169, VAR107, VAR250, VAR64,
VAR305, VAR219, VAR355, VAR239, VAR389, VAR114, VAR217, VAR345,
VAR33, VAR174, VAR147, VAR354, VAR366, VAR316, VAR20, VAR47,
VAR343, VAR142, VAR201, VAR378, VAR161, VAR238, VAR146, VAR295,
VAR57, VAR325, VAR73, VAR... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/interrupt_controller.v | 5,437 | module MODULE1 (
input VAR13, input VAR1, input VAR11, input VAR7, output VAR19, input VAR17, output VAR10, input VAR16, output VAR4 );
reg [2:0] VAR14=VAR9;
reg [2:0] VAR2=VAR9;
reg VAR15=0;
reg VAR5=0;
assign VAR19 = (VAR14 == VAR12);
assign VAR4 = VAR15;
assign VAR10 = VAR5;
always @(*) begin
case (VAR14)
if (VAR11)... | bsd-3-clause |
timofonic/fpga_nes | hw/src/cmn/uart/uart.v | 4,995 | module MODULE1
parameter VAR40 = 50000000,
parameter VAR34 = 19200,
parameter VAR17 = 8,
parameter VAR32 = 1,
parameter VAR7 = 0 )
(
input wire clk, input wire reset, input wire VAR5, input wire [VAR17-1:0] VAR33, input wire VAR12, input wire VAR24, output wire VAR16, output wire [VAR17-1:0] VAR2, output wire VAR36, ou... | bsd-2-clause |
sharebrained/medusa | hdl/medusa_cape/map_door.v | 2,636 | module MODULE1 (
input VAR7,
input [11:0] VAR18,
input [11:0] VAR3,
input VAR26,
output reg [9:0] VAR20,
output VAR29
);
parameter VAR5 = 16;
parameter VAR13;
parameter VAR10;
parameter VAR1;
parameter VAR25;
parameter VAR24;
parameter VAR19 = 127;
parameter VAR11 = 65;
parameter VAR16 = VAR13;
parameter VAR22 = VAR1 +... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi22/gf180mcu_fd_sc_mcu7t5v0__aoi22_1.behavioral.v | 2,309 | module MODULE1( VAR7, VAR2, VAR4, VAR3, VAR1 );
input VAR3, VAR1, VAR2, VAR7;
output VAR4;
VAR6 VAR5(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR3(VAR3),.VAR1(VAR1));
VAR6 VAR8(.VAR7(VAR7),.VAR2(VAR2),.VAR4(VAR4),.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_r_channel.v | 6,152 | module MODULE1 #
(
parameter integer VAR28 = 4,
parameter integer VAR47 = 32
)
(
input wire clk ,
input wire reset ,
output wire [VAR28-1:0] VAR36 ,
output wire [VAR47-1:0] VAR40 ,
output wire [1:0] VAR12 ,
output wire VAR1 ,
output wire VAR15 ,
input wire VAR34 ,
input wire [VAR47-1:0] VAR2 ,
input wire [1:0] VAR26 ,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a21o/sky130_fd_sc_hdll__a21o_6.v | 2,264 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR1 ,
VAR4 ,
VAR8,
VAR10,
VAR3 ,
VAR5
);
output VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR8;
input VAR10;
input VAR3 ;
input VAR5 ;
VAR2 VAR9 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_p0_addr_cmd_datapath.v | 5,762 | module MODULE1(
clk,
VAR59,
VAR35,
VAR31,
VAR41,
VAR24,
VAR9,
VAR22,
VAR49,
VAR52,
VAR44,
VAR21,
VAR25,
VAR38,
VAR55,
VAR34,
VAR6,
VAR36
);
parameter VAR15 = "";
parameter VAR27 = "";
parameter VAR16 = "";
parameter VAR33 = "";
parameter VAR3 = "";
parameter VAR40 = "";
parameter VAR48 = "";
parameter VAR2 = "";
parame... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41oi/sky130_fd_sc_ms__a41oi.behavioral.v | 1,572 | module MODULE1 (
VAR4 ,
VAR8,
VAR5,
VAR7,
VAR2,
VAR6
);
output VAR4 ;
input VAR8;
input VAR5;
input VAR7;
input VAR2;
input VAR6;
supply1 VAR12;
supply0 VAR15;
supply1 VAR3 ;
supply0 VAR14 ;
wire VAR11 ;
wire VAR13;
and VAR10 (VAR11 , VAR8, VAR5, VAR7, VAR2 );
nor VAR9 (VAR13, VAR6, VAR11 );
buf VAR1 (VAR4 , VAR13 );
e... | apache-2.0 |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_immu.v | 14,326 | module MODULE1
parameter VAR10 = "VAR54",
parameter VAR85 = 32,
parameter VAR7 = 6,
parameter VAR91 = 1
)
(
input clk,
input rst,
input VAR84,
output VAR51,
input [VAR85-1:0] VAR57,
input [VAR85-1:0] VAR40,
output reg [VAR85-1:0] VAR50,
output reg VAR89,
input VAR52,
output reg VAR44,
output VAR24,
output reg VAR46,
in... | mit |
chriswynnyk/american-put-verilog | american_put_stratix/src/value_membank.v | 9,749 | module MODULE1(
clk,
VAR33,
VAR80,
VAR20,
VAR66,
VAR14,
VAR69,
VAR104,
VAR54,
VAR15,
VAR105,
VAR51,
VAR62,
VAR32,
VAR91,
VAR59,
VAR13,
VAR24,
VAR72,
VAR46,
VAR52,
VAR100,
VAR1,
VAR63,
VAR34,
VAR57,
VAR16,
VAR5,
VAR87,
VAR3,
VAR65,
VAR42,
VAR12,
VAR81,
VAR25,
VAR18,
VAR97,
VAR67,
VAR64,
VAR31,
VAR2,
VAR23,
VAR89,
VAR75,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.blackbox.v | 1,206 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR3;
endmodule | apache-2.0 |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rising_edge_detect.v | 2,431 | module MODULE1(
input clk,
input rst,
input in,
output VAR1);
reg VAR2;
always@(posedge clk)begin
if(rst)begin
VAR2 <= 1'b0;
end else begin
VAR2 <= in;
end
end
assign VAR1 = ~VAR2 & in;
endmodule | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnrnq/gf180mcu_fd_sc_mcu7t5v0__dffnrnq_2.behavioral.v | 3,689 | module MODULE1( VAR23, VAR10, VAR21, VAR11 );
input VAR23, VAR10, VAR21;
output VAR11;
reg VAR1;
VAR2 VAR24(.VAR23(VAR23),.VAR10(VAR10),.VAR21(VAR21),.VAR11(VAR11),.VAR1(VAR1));
VAR2 VAR3(.VAR23(VAR23),.VAR10(VAR10),.VAR21(VAR21),.VAR11(VAR11),.VAR1(VAR1));
not VAR19(VAR30,VAR10);
and VAR29(VAR22,VAR21,VAR30);
and VAR1... | apache-2.0 |
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