repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfbbp/sky130_fd_sc_ms__dfbbp_1.v | 2,577 | module MODULE2 (
VAR12 ,
VAR8 ,
VAR11 ,
VAR7 ,
VAR5 ,
VAR6,
VAR10 ,
VAR2 ,
VAR1 ,
VAR3
);
output VAR12 ;
output VAR8 ;
input VAR11 ;
input VAR7 ;
input VAR5 ;
input VAR6;
input VAR10 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
VAR9 VAR4 (
.VAR12(VAR12),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR6(VAR6),
.V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a311o/sky130_fd_sc_hs__a311o.behavioral.pp.v | 1,965 | module MODULE1 (
VAR8,
VAR3,
VAR9 ,
VAR5 ,
VAR15 ,
VAR2 ,
VAR1 ,
VAR14
);
input VAR8;
input VAR3;
output VAR9 ;
input VAR5 ;
input VAR15 ;
input VAR2 ;
input VAR1 ;
input VAR14 ;
wire VAR1 VAR12 ;
wire VAR11 ;
wire VAR4;
and VAR13 (VAR12 , VAR2, VAR5, VAR15 );
or VAR7 (VAR11 , VAR12, VAR14, VAR1 );
VAR6 VAR10 (VAR4, VA... | apache-2.0 |
jh247247/ECE3091-chickybot | chickybot.cydsn/FIFO/FIFO.v | 5,956 | module MODULE1 (
output VAR19,
input clk,
input [7:0] VAR50,
input VAR39
);
VAR41 #(.VAR18(
{
8'hFF, 8'h00,
8'hFF, 8'hFF,
1'h0, VAR34, VAR36,
10'h00, VAR1,VAR23,
}
)) VAR44(
.reset(1'b0),
.clk(clk),
.VAR48(3'b0),
.VAR12(1'b0),
.VAR38(1'b0),
.VAR14(VAR39),
.VAR54(1'b0),
.VAR9(1'b0),
.VAR15(1'b0),
.VAR42(),
.VAR47(),
.VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.pp.blackbox.v | 1,323 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR6 ,
VAR4,
VAR7
);
output VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR6 ;
input VAR4;
input VAR7;
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_custom_fptoint.v | 6,133 | module MODULE1(VAR18, VAR16, VAR7, VAR1, VAR28, VAR27, VAR2, VAR10, enable);
input VAR18, VAR16;
input [31:0] VAR7;
output [31:0] VAR1;
input VAR28, VAR2, enable;
output VAR27, VAR10;
parameter VAR20 = 1;
parameter VAR25 = 0;
parameter VAR19 = 1;
reg [4:0] VAR8;
reg [31:0] VAR32;
reg VAR3;
reg VAR23;
reg [8:0] VAR31;
w... | mit |
secworks/sha3 | src/rtl/sha3_core.v | 16,280 | module MODULE1(
input wire clk,
input wire VAR42,
input wire VAR79,
input wire VAR78,
input wire [1 : 0] VAR54,
input wire VAR15,
input wire [31 : 0] VAR69,
input wire [1023 : 0] VAR82,
output wire ready,
output wire [511 : 0] VAR25,
output wire VAR66
);
parameter VAR95 = 79;
parameter VAR33 = 0;
parameter VAR31 = 1;
p... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a.behavioral.v | 1,662 | module MODULE1 (
VAR16 ,
VAR2,
VAR5,
VAR10,
VAR9,
VAR13
);
output VAR16 ;
input VAR2;
input VAR5;
input VAR10;
input VAR9;
input VAR13;
supply1 VAR4;
supply0 VAR17;
supply1 VAR11 ;
supply0 VAR8 ;
wire VAR7 ;
wire VAR14 ;
wire VAR6;
or VAR12 (VAR7 , VAR9, VAR10 );
or VAR1 (VAR14 , VAR5, VAR2 );
and VAR15 (VAR6, VAR7, VA... | apache-2.0 |
asicguy/gplgpu | hdl/math/flt_recip_fast.v | 11,225 | module MODULE1
(
input clk,
input [31:0] VAR27,
output [31:0] VAR18
);
wire [7:0] VAR23;
MODULE2 MODULE1
(
.clk (clk),
.VAR5 (VAR27[22:16]),
.VAR3 (VAR23)
);
MODULE3 MODULE2
(
.clk (clk),
.VAR24 (VAR23),
.VAR27 (VAR27),
.VAR18 (VAR18)
);
endmodule
module MODULE2
(
input clk,
input [6:0] VAR5,
output reg [7:0] VAR3
);
a... | gpl-3.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii/db/ip/niosii/submodules/niosii_nios2_gen2_0_cpu_mult_cell.v | 8,030 | module MODULE1 (
VAR29,
VAR27,
VAR51,
clk,
VAR23,
VAR38,
VAR22,
VAR49
)
;
output [ 31: 0] VAR38;
output [ 31: 0] VAR22;
output [ 31: 0] VAR49;
input [ 31: 0] VAR29;
input [ 31: 0] VAR27;
input VAR51;
input clk;
input VAR23;
wire [ 31: 0] VAR38;
wire [ 31: 0] VAR22;
wire [ 31: 0] VAR49;
wire VAR47;
wire [ 31: 0] VAR6;
w... | mit |
flycrow/pyxdl | logicanalyzer/serial_wb_parport.v | 1,912 | module MODULE1(
VAR4, VAR5, VAR3,VAR9,
VAR13, VAR12, VAR8, VAR6, VAR1,VAR11, VAR7
);
output [31:0] VAR4;
output [7:0] VAR5;
input VAR13;
input VAR12;
input [31:0] VAR8;
input VAR6;
input [7:0] VAR11;
input [1:0] VAR7;
input VAR1;
output VAR9;
output VAR3;
reg [31:0] VAR4;
reg [7:0] VAR5;
wire VAR13;
wire VAR12;
wire VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.blackbox.v | 1,260 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
supply1 VAR2;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/buf_ram_2p_64x512.v | 3,733 | module MODULE1 (
clk ,
VAR9 ,
VAR29 ,
VAR28 ,
VAR23 ,
VAR7 ,
VAR1
);
input clk ;
input [1:0] VAR9 ;
input [8:0] VAR29 ;
input [VAR30*8-1:0] VAR28 ;
input VAR23 ;
input [8:0] VAR7 ;
output [VAR30*8-1:0] VAR1 ;
reg [VAR30*8-1:0] VAR14 ;
reg [7:0] VAR17 ;
always @(*) begin
case (VAR9)
2'b00: begin VAR17=8'hff ; VAR14=VAR2... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.blackbox.v | 1,321 | module MODULE1 (
VAR3,
VAR1
);
output VAR3;
input VAR1;
supply1 VAR4;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/double_buffer.v | 4,322 | module MODULE1
(input clk, input reset, input VAR7,
input VAR40,
input VAR42,
output VAR1,
input VAR20,
input VAR10,
input [VAR24-1:0] VAR44,
output [VAR24-1:0] VAR37,
input [35:0] VAR47,
output [35:0] VAR15,
input [35:0] VAR27,
input VAR52,
output VAR35,
output [35:0] VAR18,
output VAR13,
input VAR39
);
wire [35:0] VA... | gpl-2.0 |
Arlet/vga16 | handshake.v | 1,043 | module MODULE1(
input VAR2, output VAR7,
input VAR1, output VAR10 );
reg VAR5 = 0;
reg VAR3 = 0;
wire VAR11;
wire VAR6;
assign VAR7 = ~(VAR5 ^ VAR6);
assign VAR10 = (VAR3 ^ VAR11);
MODULE2 MODULE2(
.VAR9(VAR2),
.VAR8(VAR1),
.in(VAR5),
.out(VAR11) );
MODULE2 MODULE1(
.VAR9(VAR1),
.VAR8(VAR2),
.in(VAR3),
.out(VAR6) );
al... | lgpl-2.1 |
toyoshim/tvcl | SevenSegmentLED.v | 1,431 | module MODULE1(
VAR1,
VAR3,
VAR5,
VAR8,
VAR11,
VAR6,
VAR10,
VAR7);
input [3:0] VAR1;
output VAR3;
output VAR5;
output VAR8;
output VAR11;
output VAR6;
output VAR10;
output VAR7;
wire [6:0] VAR9;
function [6:0] VAR4;
input [3:0] VAR2;
begin
case (VAR1)
4'h0: VAR4 = 7'b0000001;
4'h1: VAR4 = 7'b1001111;
4'h2: VAR4 = 7'b00... | bsd-3-clause |
P3Stor/P3Stor | pcie/app/FLOW_CONTROLLER.v | 2,449 | module MODULE1(
clk,
VAR16,
VAR6,
VAR17,
VAR20,
VAR5,
VAR13,
VAR3,
VAR21,
VAR1,
VAR8,
VAR14,
VAR2
);
parameter VAR7 = 128;
parameter VAR18 = 256;
parameter VAR19 = 36;
parameter VAR11 = 154;
parameter VAR9 = 29;
parameter VAR4 = 18;
input clk;
input VAR16 , VAR6;
input VAR17;
input [10:0] VAR20; input [31:0] VAR5;
inpu... | gpl-2.0 |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/impl/ip/hdl/verilog/contact_discoverycud.v | 1,461 | module MODULE1 (VAR6, VAR7, VAR1, VAR4, VAR8, clk);
parameter VAR2 = 8;
parameter VAR5 = 6;
parameter VAR9 = 64;
input[VAR5-1:0] VAR6;
input VAR7;
input[VAR2-1:0] VAR1;
input VAR4;
output reg[VAR2-1:0] VAR8;
input clk;
reg [VAR2-1:0] VAR3[0:VAR9-1];
begin
begin
begin
end | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/dram_async_pad.v | 3,894 | module MODULE1(
VAR17,
VAR15,
VAR7, VAR2, VAR1, VAR14,
VAR9, VAR5, VAR22, VAR19, VAR3, VAR16, VAR18
);
input VAR18; input [8:1] VAR16; input [8:1] VAR3; input VAR19; input VAR22; input VAR5; input VAR9; input VAR14; input VAR1; input VAR2; input [7:0] VAR7;
inout VAR15;
output VAR17;
wire VAR10;
VAR11 VAR6(
.VAR10(VAR1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o_4.v | 2,339 | module MODULE2 (
VAR11 ,
VAR6 ,
VAR7 ,
VAR1 ,
VAR4 ,
VAR2,
VAR9,
VAR3 ,
VAR8
);
output VAR11 ;
input VAR6 ;
input VAR7 ;
input VAR1 ;
input VAR4 ;
input VAR2;
input VAR9;
input VAR3 ;
input VAR8 ;
VAR10 VAR5 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR... | apache-2.0 |
thinkoco/de1_soc_opencl | de10_standard_sharedonly_vga/ip/TERASIC_AUDIO/AUDIO_DAC.v | 3,972 | module MODULE1(
clk,
reset,
write,
VAR26,
VAR28,
VAR17,
VAR23,
VAR15,
VAR2
);
parameter VAR4 = 32;
input clk;
input reset;
input write;
input [(VAR4-1):0] VAR26;
output VAR28;
input VAR17;
input VAR23;
input VAR15;
output VAR2;
reg VAR8;
reg VAR12;
reg [4:0] VAR27; reg VAR21;
reg [(VAR4-1):0] VAR19;
reg [(VAR4-1):0] VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn.pp.symbol.v | 1,368 | module MODULE1 (
input VAR3 ,
output VAR4 ,
output VAR7 ,
input VAR5,
input VAR2 ,
input VAR6 ,
input VAR8 ,
input VAR1
);
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_rate.v | 46,086 | module MODULE1 #
(
parameter VAR86 = "VAR39", parameter VAR29 = "VAR40", parameter VAR36 = "3.0", parameter VAR50 = "VAR15", parameter VAR3 = "VAR6", parameter VAR119 = "VAR39", parameter VAR13 = "VAR39", parameter VAR103 = "VAR6", parameter VAR67 = 4'd15
)
(
input VAR46,
input VAR81,
input VAR108,
input VAR61,
input [... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_misc/rtl/bw_io_misc_chunk6.v | 1,684 | module MODULE1(VAR10 ,VAR14 ,VAR9 ,VAR5 ,VAR12 ,VAR13 ,
VAR11 );
output VAR10 ;
input VAR14 ;
input VAR9 ;
input VAR12 ;
input VAR13 ;
inout VAR5 ;
inout VAR11 ;
supply0 VAR15 ;
wire VAR4 ;
VAR16 VAR3 (
.VAR2 (VAR15 ),
.VAR9 (VAR9 ),
.VAR1 (VAR15 ),
.VAR6 (VAR10 ),
.VAR7 (VAR11 ),
.VAR13 (VAR13 ) );
VAR16 VAR8 (
.VAR2 ... | gpl-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_splitter.v | 4,368 | module MODULE1 #
(
parameter integer VAR1 = 2 )
(
input wire VAR5,
input wire VAR6,
input wire VAR4,
output wire VAR7,
output wire [VAR1-1:0] VAR9,
input wire [VAR1-1:0] VAR2
);
reg [VAR1-1:0] VAR10;
wire VAR8;
wire [VAR1-1:0] VAR3;
always @(posedge VAR5) begin
if (VAR6 | VAR8) VAR10 <= {VAR1{1'b0}};
end
else VAR10 <= ... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/altera_reset_controller.v | 12,329 | module MODULE1
parameter VAR41 = 6,
parameter VAR15 = 0,
parameter VAR26 = 0,
parameter VAR32 = 0,
parameter VAR21 = 0,
parameter VAR77 = 0,
parameter VAR53 = 0,
parameter VAR31 = 0,
parameter VAR39 = 0,
parameter VAR76 = 0,
parameter VAR14 = 0,
parameter VAR34 = 0,
parameter VAR70 = 0,
parameter VAR68 = 0,
parameter V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi_lp.v | 2,369 | module MODULE1 (
VAR10 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR2 ,
VAR7,
VAR4,
VAR5 ,
VAR8
);
output VAR10 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR5 ;
input VAR8 ;
VAR9 VAR11 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/decap/sky130_fd_sc_hdll__decap.pp.blackbox.v | 1,206 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR2
);
input VAR1;
input VAR3;
input VAR4 ;
input VAR2 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nand3/gf180mcu_fd_sc_mcu7t5v0__nand3_1.functional.v | 1,218 | module MODULE1( VAR2, VAR9, VAR6, VAR4 );
input VAR4, VAR6, VAR2;
output VAR9;
wire VAR7;
not VAR10( VAR7, VAR4 );
wire VAR5;
not VAR8( VAR5, VAR6 );
wire VAR3;
not VAR11( VAR3, VAR2 );
or VAR1( VAR9, VAR7, VAR5, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp.pp.blackbox.v | 1,367 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR2 ,
VAR4,
VAR3 ,
VAR6 ,
VAR5 ,
VAR8
);
output VAR7 ;
input VAR1 ;
input VAR2 ;
input VAR4;
input VAR3 ;
input VAR6 ;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
donnaware/AGC | rtl/de0/modules/ng_SUB.v | 3,797 | module MODULE1(
input [ 7:0] VAR3, output [22:0] VAR2 );
wire VAR7 = VAR3[ 7]; wire VAR8 = VAR3[ 6]; wire [ 3:0] VAR6 = VAR3[5:2]; wire VAR5 = VAR3[ 1]; wire VAR10 = VAR3[ 0];
assign VAR2[22 ] = VAR9;
assign VAR2[21 ] = VAR11;
assign VAR2[20:0] = VAR4;
wire VAR9 = !( VAR8 & !VAR7); wire VAR11 = !(!VAR8 & VAR7);
reg [19... | gpl-3.0 |
dtysky/FPGA-Imaging-Library | Connector/DataDelay/srcs/DataDelay.v | 1,031 | module MODULE1(clk, VAR5, VAR3);
parameter VAR1 = 8;
parameter delay = 1;
input clk;
input[VAR1 - 1 : 0] VAR5;
output[VAR1 - 1 : 0] VAR3;
genvar VAR4;
generate
for (VAR4 = 0; VAR4 < delay; VAR4 = VAR4 + 1) begin : VAR2
reg[VAR1 - 1 : 0] VAR6;
if(VAR4 == 0) begin
always @(posedge clk)
VAR6 <= VAR5;
end else begin
always... | lgpl-2.1 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.behavioral.v | 1,188 | module MODULE1( VAR3, VAR5, VAR6 );
input VAR6, VAR3;
output VAR5;
VAR4 VAR2(.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6));
VAR4 VAR1(.VAR3(VAR3),.VAR5(VAR5),.VAR6(VAR6)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o221a/sky130_fd_sc_hs__o221a.blackbox.v | 1,359 | module MODULE1 (
VAR1 ,
VAR8,
VAR3,
VAR2,
VAR6,
VAR7
);
output VAR1 ;
input VAR8;
input VAR3;
input VAR2;
input VAR6;
input VAR7;
supply1 VAR5;
supply0 VAR4;
endmodule | apache-2.0 |
pseudoincorrect/FPGA_MCU_wifi | FPGA/src/pll/pll_bb.v | 11,104 | module MODULE1 (
VAR4,
VAR3,
VAR1,
VAR2);
input VAR4;
input VAR3;
output VAR1;
output VAR2;
tri0 VAR4;
endmodule | mit |
jotego/jt12 | hdl/alt/eg_comb.v | 5,816 | module MODULE1(
input VAR20,
input [ 4:0] VAR18,
input [ 4:0] VAR15,
input [14:0] VAR11,
input VAR22,
input [ 1:0] VAR10,
input [ 9:0] VAR14,
input [ 6:0] VAR2,
input VAR4,
input [ 1:0] VAR30,
input [ 6:0] VAR21,
output VAR28,
output reg [9:0] VAR12,
output reg [9:0] VAR3
);
reg [6:0] VAR7;
reg [5:0] VAR29;
always @
VA... | gpl-3.0 |
CatherineH/QubitekkCC | CC1/src/DE0Nano/verilog/coincidence_counter.v | 4,517 | module MODULE1 (
VAR7,
VAR1,
VAR25,
VAR18);
input VAR7;
input VAR1;
input VAR25;
output [21:0] VAR18;
wire [21:0] VAR3;
wire [21:0] VAR18 = VAR3[21:0];
VAR12 VAR14 (
.VAR7 (VAR7),
.VAR1 (VAR1),
.VAR25 (VAR25),
.VAR18 (VAR3),
.VAR19 (1'b0),
.VAR13 (1'b0),
.VAR8 (1'b1),
.VAR2 (1'b1),
.VAR15 (),
.VAR23 ({22{1'b0}}),
.VAR5... | mit |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_sys_clk_timer.v | 6,853 | module MODULE1 (
address,
VAR17,
clk,
VAR32,
VAR20,
VAR19,
irq,
VAR22
)
;
output irq;
output [ 15: 0] VAR22;
input [ 2: 0] address;
input VAR17;
input clk;
input VAR32;
input VAR20;
input [ 15: 0] VAR19;
wire VAR5;
wire VAR18;
wire VAR31;
reg [ 3: 0] VAR3;
wire VAR9;
reg VAR14;
wire VAR2;
wire [ 31: 0] VAR7;
reg [ 31: ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfsbp/sky130_fd_sc_lp__sdfsbp.symbol.v | 1,524 | module MODULE1 (
input VAR2 ,
output VAR1 ,
output VAR4 ,
input VAR7,
input VAR11 ,
input VAR6 ,
input VAR9
);
supply1 VAR8;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.behavioral.v | 1,521 | module MODULE1 (
VAR12 ,
VAR5,
VAR6,
VAR11,
VAR13
);
output VAR12 ;
input VAR5;
input VAR6;
input VAR11;
input VAR13;
supply1 VAR1;
supply0 VAR10;
supply1 VAR7 ;
supply0 VAR3 ;
wire VAR8 ;
wire VAR14;
or VAR4 (VAR8 , VAR6, VAR5, VAR11 );
and VAR2 (VAR14, VAR8, VAR13 );
buf VAR9 (VAR12 , VAR14 );
endmodule | apache-2.0 |
travisg/cpu | rtl/lib/seven_segment.v | 1,825 | module MODULE1
(
input [3:0] in,
output reg [6:0] VAR1
);
always @ (in)
begin
case (in)
0: VAR1 = 7'b1000000;
1: VAR1 = 7'b1111001;
2: VAR1 = 7'b0100100;
3: VAR1 = 7'b0110000;
4: VAR1 = 7'b0011001;
5: VAR1 = 7'b0010010;
6: VAR1 = 7'b0000010;
7: VAR1 = 7'b1111000;
8: VAR1 = 7'b0000000;
9: VAR1 = 7'b0011000;
10: VAR1 = 7... | mit |
jotego/jt12 | ver/common/hybrid_pwm_sd.v | 1,169 | module MODULE1
(
input clk,
input VAR3,
input [15:0] din,
output dout
);
reg [4:0] VAR2;
reg [4:0] VAR1;
reg [33:0] VAR4;
reg [15:0] VAR5;
reg out;
assign dout=out;
always @(posedge clk, negedge VAR3) begin
if(!VAR3)
begin
VAR5<=16'b0000010000000000;
VAR1<=5'b10000;
VAR2<=5'd0;
VAR4<=34'd0;
end
else
begin
VAR2<=VAR2+1;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b.blackbox.v | 1,291 | module MODULE1 (
VAR6 ,
VAR7 ,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR4;
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/ipcore_dir/write_data_fifo.v | 13,589 | module MODULE1(
rst,
VAR155,
VAR123,
din,
VAR288,
VAR365,
dout,
VAR32,
VAR206,
VAR63,
VAR208,
VAR10
);
input rst;
input VAR155;
input VAR123;
input [255 : 0] din;
input VAR288;
input VAR365;
output [31 : 0] dout;
output VAR32;
output VAR206;
output [12 : 0] VAR63;
output [9 : 0] VAR208;
output VAR10;
VAR215 #(
.VAR304(... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2/sky130_fd_sc_hdll__mux2_16.v | 2,209 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR8 ,
VAR9 ,
VAR5,
VAR7,
VAR4 ,
VAR3
);
output VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR9 ;
input VAR5;
input VAR7;
input VAR4 ;
input VAR3 ;
VAR10 VAR6 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE1 (... | apache-2.0 |
rkrajnc/minimig-mist | rtl/lcd/lcd.v | 16,925 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR1,
input wire [ 4-1:0] VAR8,
input wire [ 4-1:0] VAR14,
input wire [ 4-1:0] VAR13,
output reg [ 16-1:0] VAR2,
output reg VAR9,
output reg VAR7,
output reg VAR6,
output reg VAR5,
output reg VAR11
);
reg [ 4-1:0] VAR15;
always @ (posedge clk, posedge rst) begi... | gpl-3.0 |
ShirmanXia/EE469SPRING16 | lab4/nios_system/synthesis/submodules/nios_system_sub_outputs.v | 1,920 | module MODULE1 (
address,
clk,
VAR5,
VAR6,
VAR4
)
;
output [ 31: 0] VAR4;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR5;
input VAR6;
wire VAR2;
wire [ 7: 0] VAR3;
wire [ 7: 0] VAR1;
reg [ 31: 0] VAR4;
assign VAR2 = 1;
assign VAR1 = {8 {(address == 0)}} & VAR3;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/fifo_8x32.v | 1,881 | module MODULE1(
input [31:0] din, input VAR9,
input VAR8,
output [31:0] dout, output VAR2,
output VAR10,
input reset,
input clk
);
parameter VAR5 = 3;
parameter VAR4 = 2 ** VAR5;
reg [31:0] VAR7 [VAR4 - 1 : 0];
reg [VAR5 - 1 : 0] VAR3;
reg [VAR5 - 1 : 0] VAR1;
reg [VAR5 - 1 + 1 : 0] VAR6;
always @(posedge clk)
begin
if... | mit |
CospanDesign/nysa-artemis-pcie-platform | artemis_pcie/slave/wb_artemis_pcie_platform/rtl/adapter_ppfifo_2_ppfifo.v | 3,584 | module MODULE1 #(
parameter VAR2 = 32
)(
input clk,
input rst,
input VAR5,
output reg VAR3,
input [23:0] VAR11,
input [VAR2 - 1:0] VAR7,
output reg VAR12,
input [1:0] VAR8,
output reg [1:0] VAR4,
input [23:0] VAR9,
output reg VAR10,
output [VAR2 - 1:0] VAR13
);
reg [23:0] VAR6;
reg [23:0] VAR1;
assign VAR13 = VAR7;
alw... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v | 1,115 | module MODULE1 #(parameter VAR5(VAR7 )
,parameter VAR5(VAR8 )
, parameter VAR3 = 0
, parameter VAR2 = 0
, parameter VAR9 = 0
, parameter VAR1 = 0
)
(input [VAR7*VAR8-1:0] VAR4
, output [VAR7-1:0] VAR6
); | bsd-3-clause |
benjaminfjones/fpga-tunes | src/pwm.v | 1,209 | module MODULE1 #(parameter VAR3 = 24) (
input clk,
input rst,
input [VAR3-1:0] period,
input [VAR3-1:0] VAR6,
output MODULE1
);
reg VAR1, VAR4;
reg [VAR3-1:0] VAR2, VAR5;
assign MODULE1 = VAR4;
always@(VAR5) begin
if (VAR5 > period) begin
VAR2 = 1'b0;
end else begin
VAR2 = VAR5 + 1'b1;
end
if (VAR6 > VAR2) begin
VAR1 =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41ai/sky130_fd_sc_lp__o41ai.functional.v | 1,475 | module MODULE1 (
VAR1 ,
VAR11,
VAR7,
VAR6,
VAR2,
VAR5
);
output VAR1 ;
input VAR11;
input VAR7;
input VAR6;
input VAR2;
input VAR5;
wire VAR8 ;
wire VAR10;
or VAR3 (VAR8 , VAR2, VAR6, VAR7, VAR11 );
nand VAR4 (VAR10, VAR5, VAR8 );
buf VAR9 (VAR1 , VAR10 );
endmodule | apache-2.0 |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkHost_Control_Status.v | 27,709 | module MODULE1(VAR123,
VAR18,
VAR30,
VAR107,
VAR132,
VAR34,
VAR3,
VAR80,
VAR143,
VAR49,
VAR122,
VAR95,
VAR68,
VAR156,
VAR145,
VAR51,
VAR98,
VAR6,
VAR74,
VAR69,
VAR39,
VAR81,
VAR41,
VAR119,
VAR121,
VAR13,
VAR141,
VAR146,
VAR75,
VAR164,
VAR57,
VAR61,
VAR92,
VAR133,
VAR151,
VAR109,
VAR66,
VAR33,
VAR157,
VAR56,
VAR86,
VAR4... | apache-2.0 |
neale/CS-program | 474-VLSI/Lab3/tes_pll_syn.v | 20,114 | module MODULE1
(
VAR64,
clk,
VAR48) ;
input VAR64;
output [4:0] clk;
input [1:0] VAR48;
tri0 VAR64;
tri0 [1:0] VAR48;
wire [4:0] VAR51;
wire VAR63;
VAR30 VAR17
(
.VAR13(),
.VAR64(VAR64),
.clk(VAR51),
.VAR55(),
.VAR8(VAR63),
.VAR23(VAR63),
.VAR48(VAR48),
.VAR67(),
.VAR39(),
.VAR31(),
.VAR29(),
.VAR36(),
.VAR34()
,
.VAR3... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp.pp.symbol.v | 1,442 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR1,
input VAR7 ,
input VAR4 ,
input VAR8 ,
input VAR5 ,
input VAR3
);
endmodule | apache-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_hdmi/ip/i2c/I2C_HDMI_Config.v | 4,612 | module MODULE1 ( VAR6,
VAR18,
VAR14,
VAR17,
VAR22,
VAR8
);
input VAR6;
input VAR18;
output VAR14;
inout VAR17;
input VAR22;
output VAR8 ;
reg [15:0] VAR7;
reg [23:0] VAR23;
reg VAR5;
reg VAR13;
wire VAR24;
wire VAR3;
reg [15:0] VAR9;
reg [5:0] VAR25;
reg [3:0] VAR2;
reg VAR8 ;
parameter VAR4 = 50000000; parameter VAR20... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/bank/BankManager.v | 3,493 | module MODULE1(
dout,
din,
address,
VAR7,
VAR12,
enable,
VAR14,
VAR4,
reset,
clk
);
localparam VAR18 = 0;
localparam VAR2 = 1;
localparam VAR8 = 2;
output reg [VAR19-1:0] dout;
input wire [VAR19-1:0] din;
input wire [VAR19-1:0] address;
input wire [VAR17-1:0] VAR7;
input wire VAR12;
input wire enable;
output reg [VAR19... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlclkp/sky130_fd_sc_hvl__dlclkp.behavioral.v | 2,138 | module MODULE1 (
VAR20,
VAR18,
VAR8
);
output VAR20;
input VAR18;
input VAR8 ;
supply1 VAR10;
supply0 VAR16;
supply1 VAR2 ;
supply0 VAR6 ;
wire VAR14 ;
wire VAR9 ;
wire VAR12 ;
wire VAR19;
reg VAR15 ;
wire VAR11 ;
wire VAR7 ;
not VAR1 (VAR9 , VAR12 );
VAR17 VAR5 (VAR14 , VAR19, VAR9, VAR15, VAR10, VAR16);
and VAR4 (VAR... | apache-2.0 |
myriadrf/A2300 | hdl/wca/WcaRssi.v | 1,044 | module MODULE1 (
input VAR2,
input reset,
input VAR6,
input [11:0] VAR4,
output [7:0] VAR5
);
wire [11:0] VAR1 = VAR4[11] ? ~VAR4 : VAR4;
reg [23:0] VAR3;
always @(posedge VAR2)
if(reset )
VAR3 <= 24'd0;
else if (VAR6)
VAR3 <= VAR3 + VAR1 - {1'b0,VAR3[23:13]};
assign VAR5 = VAR3[23:16];
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp_4.v | 2,130 | module MODULE2 (
VAR9 ,
VAR1 ,
VAR5 ,
VAR4,
VAR8,
VAR6 ,
VAR3
);
output VAR9 ;
input VAR1 ;
input VAR5 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR3 ;
VAR7 VAR2 (
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR9 ,
VAR1 ,
VAR5
);
output VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfrbp/sky130_fd_sc_hd__sdfrbp.functional.v | 2,101 | module MODULE1 (
VAR4 ,
VAR12 ,
VAR15 ,
VAR9 ,
VAR14 ,
VAR5 ,
VAR6
);
output VAR4 ;
output VAR12 ;
input VAR15 ;
input VAR9 ;
input VAR14 ;
input VAR5 ;
input VAR6;
wire VAR16 ;
wire VAR17 ;
wire VAR7;
not VAR10 (VAR17 , VAR6 );
VAR2 VAR11 (VAR7, VAR9, VAR14, VAR5 );
VAR1 VAR3 VAR18 (VAR16 , VAR7, VAR15, VAR17);
buf VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand2b/sky130_fd_sc_lp__nand2b.functional.pp.v | 1,936 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR7 ,
VAR11,
VAR6,
VAR5 ,
VAR3
);
output VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR11;
input VAR6;
input VAR5 ;
input VAR3 ;
wire VAR12 ;
wire VAR13 ;
wire VAR2;
not VAR9 (VAR12 , VAR7 );
or VAR1 (VAR13 , VAR12, VAR4 );
VAR14 VAR10 (VAR2, VAR13, VAR11, VAR6);
buf VAR15 (VAR8 , VAR2 );
en... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.pp.symbol.v | 1,358 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR1,
output VAR5 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_1.behavioral.v | 3,431 | module MODULE1( VAR6, VAR5, VAR9, VAR3, VAR4, VAR8 );
input VAR9, VAR5, VAR6, VAR4, VAR8;
output VAR3;
VAR7 VAR1(.VAR6(VAR6),.VAR5(VAR5),.VAR9(VAR9),.VAR3(VAR3),.VAR4(VAR4),.VAR8(VAR8));
VAR7 VAR2(.VAR6(VAR6),.VAR5(VAR5),.VAR9(VAR9),.VAR3(VAR3),.VAR4(VAR4),.VAR8(VAR8)); | apache-2.0 |
ShirmanXia/EE469SPRING16 | lab3/db/ip/nios_system/submodules/altera_reset_synchronizer.v | 3,553 | module MODULE1
parameter VAR5 = 1,
parameter VAR4 = 2
)
(
input VAR3 ,
input clk,
output VAR6
);
reg [VAR4-1:0] VAR2;
reg VAR1;
generate if (VAR5) begin
always @(posedge clk or posedge VAR3) begin
if (VAR3) begin
VAR2 <= {VAR4{1'b1}};
VAR1 <= 1'b1;
end
else begin
VAR2[VAR4-2:0] <= VAR2[VAR4-1:1];
VAR2[VAR4-1] <= 0;
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21bai/sky130_fd_sc_ls__o21bai_2.v | 2,329 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR2 ,
VAR10,
VAR8,
VAR5,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR9 ;
input VAR2 ;
input VAR10;
input VAR8;
input VAR5;
input VAR6 ;
input VAR7 ;
VAR1 VAR4 (
.VAR3(VAR3),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE1 ... | apache-2.0 |
ByronPhung/hardware-accelerated-dna-matching-and-variation-detection | Hardware/Verilog/Search_8Comparators.v | 2,837 | module MODULE1(
input VAR19,
input reset,
input [1023:0] VAR4,
input [63:0] VAR24,
output reg VAR25
);
reg [7:0] counter;
reg [63:0] VAR21, VAR20, VAR22, VAR18, VAR9, VAR17, VAR14, VAR16;
wire VAR10, VAR12, VAR15, VAR6, VAR3, VAR23, VAR27, VAR29;
VAR26 VAR5
(
.VAR4(VAR21),
.VAR24(VAR24),
.VAR25(VAR10)
);
VAR26 VAR7
(
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrckapwr/sky130_fd_sc_hd__lpflow_isobufsrckapwr.pp.symbol.v | 1,492 | module MODULE1 (
input VAR1 ,
output VAR4 ,
input VAR5,
input VAR8,
input VAR7 ,
input VAR2 ,
input VAR3 ,
input VAR6
);
endmodule | apache-2.0 |
linuxbest/lzs | decode/rtl/verilog/generic_tpram.v | 9,125 | module MODULE1(
VAR81, VAR21, VAR58, VAR30, VAR63, VAR82, VAR66, VAR10,
VAR24, VAR9, VAR35, VAR65, VAR38, VAR28, VAR34, VAR74
);
parameter VAR70 = 5;
parameter VAR60 = 32;
parameter VAR45 = (1<<VAR70);
input VAR81; input VAR21; input VAR58; input VAR30; input VAR63; input [VAR70-1:0] VAR82; input [VAR60-1:0] VAR66; out... | gpl-2.0 |
miamiasheep/nctu-dlab-99 | lab8/Tic_Tac_Toe.v | 1,198 | module MODULE1(
input VAR36,
input [3:0] VAR39,
input VAR27,
input VAR9,
input VAR25,
input VAR3,
output wire VAR26,
output wire VAR7,
output wire VAR31,
output VAR17,
output VAR8,
output [7:0] VAR32
);
reg VAR28;
wire reset;
wire VAR34;
wire VAR2;
wire VAR21;
wire [10:0] VAR33;
wire [11:0] VAR13;
wire [8:0] VAR10;
wir... | gpl-3.0 |
AmeerAbdelhadi/Multiported-RAM | mpram_lvt_reg.v | 7,232 | module MODULE1
localparam VAR25 = VAR9(VAR5 ); localparam VAR23 = VAR9(VAR11);
reg [VAR25 -1:0] VAR20 [VAR11-1:0] ; reg [VAR7 -1:0] VAR13 [VAR11-1:0] ; wire [VAR7*VAR26-1:0] VAR21 [VAR11-1:0] ; reg [VAR7 -1:0] VAR3 [VAR11-1:0][VAR26-1:0]; reg [VAR7 -1:0] VAR15 [VAR26-1:0] ; wire [VAR23 *VAR26-1:0] VAR17 ; reg [VAR23 -1... | bsd-3-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Project Creator Script/Approximate_Adders/integracion_fisica/front_end/source/ETAII_N16_Q4.v | 1,139 | module MODULE1(
input [15:0] VAR5,
input [15:0] VAR1,
output [16:0] VAR4
);
wire [2:0] VAR6;
wire [4:0] VAR10,VAR7,VAR2,VAR11,VAR8,VAR3,VAR9;
assign VAR6[2:0] = VAR5[ 1: 0] + VAR1[ 1: 0];
assign VAR10[4:0] = VAR5[ 3: 0] + VAR1[ 3: 0];
assign VAR7[4:0] = VAR5[ 5: 2] + VAR1[ 5: 2];
assign VAR2[4:0] = VAR5[ 7: 4] + VAR1[ ... | gpl-3.0 |
camacazio/de0_nano_DAC | DE0_12bitDAC_controller/db/altpll_myfirstfpga_altpll.v | 4,012 | module MODULE1
(
clk,
VAR4) ;
output [4:0] clk;
input [1:0] VAR4;
tri0 [1:0] VAR4;
wire [4:0] VAR18;
wire VAR29;
VAR30 VAR12
(
.VAR33(),
.clk(VAR18),
.VAR20(),
.VAR9(VAR29),
.VAR38(VAR29),
.VAR4(VAR4),
.VAR8(),
.VAR31(),
.VAR19(),
.VAR24(),
.VAR14(),
.VAR10()
,
.VAR15(1'b0),
.VAR25(1'b0),
.VAR27(1'b0),
.VAR21(1'b1),
.V... | gpl-3.0 |
ncos/Xilinx-Verilog | GYRACC/src/d2str.v | 3,413 | module MODULE2#
(
parameter integer VAR1 = 16 )
(
output wire [127:0] VAR11,
input wire [VAR1-1:0] VAR10
);
genvar VAR6;
generate
for (VAR6 = 0; VAR6 < VAR1; VAR6 = VAR6 + 1) begin
assign VAR11[8*VAR6+7:8*VAR6] = VAR10[VAR6]? "1" : "0";
end
for (VAR6 = VAR1; VAR6 < 16; VAR6 = VAR6 + 1) begin
assign VAR11[8*VAR6+7:8*VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4b/sky130_fd_sc_ms__and4b.behavioral.v | 1,508 | module MODULE1 (
VAR14 ,
VAR9,
VAR2 ,
VAR11 ,
VAR5
);
output VAR14 ;
input VAR9;
input VAR2 ;
input VAR11 ;
input VAR5 ;
supply1 VAR12;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR6 ;
wire VAR13 ;
wire VAR8;
not VAR10 (VAR13 , VAR9 );
and VAR3 (VAR8, VAR13, VAR2, VAR11, VAR5);
buf VAR1 (VAR14 , VAR8 );
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_phy_10g_rx.v | 5,015 | module MODULE1 #
(
parameter VAR33 = 64,
parameter VAR22 = (VAR33/8),
parameter VAR26 = (VAR33/32),
parameter VAR21 = 4'h6,
parameter VAR19 = 16'h6666,
parameter VAR18 = 0,
parameter VAR30 = 96,
parameter VAR14 = (VAR18 ? VAR30 : 0) + 1,
parameter VAR10 = 0,
parameter VAR16 = 0,
parameter VAR24 = 0,
parameter VAR23 = 0... | mit |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_TIME_OUT.v | 1,877 | module MODULE1 (
address,
clk,
VAR4,
VAR6,
VAR2
)
;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 7: 0] VAR4;
input VAR6;
wire VAR3;
wire [ 7: 0] VAR1;
wire [ 7: 0] VAR5;
reg [ 31: 0] VAR2;
assign VAR3 = 1;
assign VAR5 = {8 {(address == 0)}} & VAR1;
always @(posedge clk or negedge VAR6)
begin
if (VAR6... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_hps_0.v | 7,259 | module MODULE1 #(
parameter VAR45 = 0,
parameter VAR44 = 1
) (
output wire VAR35, input wire VAR52, output wire [11:0] VAR41, output wire [29:0] VAR19, output wire [3:0] VAR54, output wire [2:0] VAR56, output wire [1:0] VAR21, output wire [1:0] VAR51, output wire [3:0] VAR23, output wire [2:0] VAR10, output wire VAR46,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a.blackbox.v | 1,290 | module MODULE1 (
VAR4 ,
VAR1,
VAR6,
VAR2
);
output VAR4 ;
input VAR1;
input VAR6;
input VAR2;
supply1 VAR3;
supply0 VAR5;
endmodule | apache-2.0 |
roberth188/EMU-Hearing-Assistance-Device | EMU_Basic_Project/FFT_and_IFFT_Module.v | 40,788 | module MODULE1(
VAR128,
VAR51,
VAR103,
VAR55,
VAR48,
VAR81,
VAR114,
VAR75,
VAR46,
rst,
VAR141
);
input VAR128, VAR46, rst;
input [9:0] VAR48;
input [8:0] VAR51;
output [9:0] VAR103;
input [13:0] VAR141;
output VAR81;
output [1:0] VAR55;
output [8:0] VAR75;
output [11:0] VAR114;
wire VAR136, VAR113, VAR14, VAR83, VAR151... | mit |
thurday/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_TX.v | 4,907 | module MODULE1 (
input VAR18,
input VAR17,
input VAR3,
input [31:0] VAR4,
input VAR12,
input VAR8,
output [3:0] VAR11,
output VAR20
);
reg [31:0] VAR2;
reg [8:0] VAR1;
parameter VAR22 = 10'h008;
reg VAR14;
assign VAR20 = VAR14;
wire [7:0] VAR16;
wire [31:0] VAR23;
assign VAR23 = VAR8 ? VAR2 : {8'h5c,8'h5c,8'h5c,8'h5c};... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputiso1p/sky130_fd_sc_hd__lpflow_inputiso1p_1.v | 2,334 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR7,
VAR3 ,
VAR2 ,
VAR1 ,
VAR5
);
output VAR9 ;
input VAR6 ;
input VAR7;
input VAR3 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
VAR8 VAR4 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR9 ,
VAR6 ,
VAR7
);
output VA... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_reduce.v | 1,712 | if (VAR6 && (VAR4<=VAR1)) \
begin: VAR8 \
wire [VAR1-1:0] VAR10 = VAR1 ' (VAR2); \
VAR12 VAR5(.VAR2(VAR10),.VAR7); \
end
module MODULE1 #(parameter VAR3(VAR4 )
, parameter VAR11 = 0
, parameter VAR13 = 0
, parameter VAR9 = 0
, parameter VAR6 = 0
)
(input [VAR4-1:0] VAR2
, output VAR7
); | bsd-3-clause |
tommythorn/yari | shared/rtl/target/LPRP-3c25/main.v | 7,769 | module MODULE1(input wire VAR66,
input wire VAR8,
input wire VAR69,
output wire VAR62,
input wire VAR20,
input wire VAR37,
input wire VAR25,
input wire VAR33,
input wire VAR63,
input wire VAR30,
input wire VAR45,
input wire VAR29,
input wire VAR52,
inout wire [ 7:0] VAR31,
input wire [ 5:0] VAR43, input wire VAR78,
out... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrtp/sky130_fd_sc_ms__dlrtp_2.v | 2,362 | module MODULE1 (
VAR5 ,
VAR4,
VAR7 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR9 ,
VAR10
);
output VAR5 ;
input VAR4;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR10 ;
VAR8 VAR2 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_1.functional.pp.v | 3,028 | module MODULE1( VAR33, VAR17, VAR9, VAR26, VAR22, VAR5, VAR36, VAR23, VAR13 );
input VAR36, VAR5, VAR9, VAR22, VAR17, VAR33;
inout VAR23, VAR13;
output VAR26;
wire VAR35;
not VAR38( VAR35, VAR36 );
wire VAR7;
not VAR28( VAR7, VAR9 );
wire VAR8;
not VAR37( VAR8, VAR17 );
wire VAR3;
and VAR21( VAR3, VAR35, VAR7, VAR8 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.functional.pp.v | 1,973 | module MODULE1 (
VAR12,
VAR13,
VAR4 ,
VAR8 ,
VAR5 ,
VAR14
);
input VAR12;
input VAR13;
output VAR4 ;
input VAR8 ;
input VAR5 ;
input VAR14;
wire VAR6 ;
wire VAR11 ;
wire VAR9;
nand VAR1 (VAR6 , VAR5, VAR8 );
nand VAR10 (VAR11 , VAR14, VAR6 );
VAR3 VAR7 (VAR9, VAR11, VAR12, VAR13);
buf VAR2 (VAR4 , VAR9 );
endmodule | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_SLAVE/source_code/freedm_bus_slave/fb_crc.v | 2,096 | module MODULE1 (VAR7, VAR9, VAR4, VAR5, VAR6, VAR11, VAR3);
input VAR7;
input VAR9;
input [3:0] VAR4;
input VAR5;
input VAR6;
output [7:0] VAR11;
output VAR3;
reg [7:0] VAR11;
wire [7:0] VAR1;
wire [7:0] VAR10;
wire [7:0] VAR2;
wire [7:0] VAR8;
assign VAR1[7] = VAR11[6] ^ ((VAR4[3] ^ VAR11[7]) & VAR5);
assign VAR1[6] =... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfsbp/sky130_fd_sc_hd__dfsbp.functional.pp.v | 1,956 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR12 ,
VAR7 ,
VAR16,
VAR9 ,
VAR17 ,
VAR15 ,
VAR8
);
output VAR11 ;
output VAR2 ;
input VAR12 ;
input VAR7 ;
input VAR16;
input VAR9 ;
input VAR17 ;
input VAR15 ;
input VAR8 ;
wire VAR13;
wire VAR10 ;
not VAR3 (VAR10 , VAR16 );
VAR14 VAR1 VAR6 (VAR13 , VAR7, VAR12, VAR10, , VAR9, VAR17);... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/executer.v | 10,091 | module MODULE1(
input clk,
input VAR29,
input [5:0] VAR35,
input VAR17,
input [133:0] VAR37,
output VAR7,
input VAR4,
input [31:0] VAR18,
output VAR16,
output VAR25, output reg VAR9,
output reg [133:0] VAR10,
output reg VAR6,
output VAR26,
input VAR11
);
reg VAR36;
wire [133:0] VAR1;
wire [7:0] VAR3;
reg VAR5;
reg VAR1... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_dp4.v | 15,069 | module MODULE1(
VAR15, VAR37,
VAR19, VAR14, VAR23, VAR6,
VAR39, VAR13,
VAR33, VAR43,
VAR28, VAR22, VAR8,
VAR16, VAR20, VAR5
);
output [7:0] VAR15;
output [VAR34-1:0] VAR37;
input [5:0] VAR43; input [5:0] VAR33; input [5:0] VAR13; input [5:0] VAR39; input [5:0] VAR6; input VAR23; input [7:0] VAR14; input VAR19;
input [V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu9t5v0__latrsnq_4.behavioral.v | 6,154 | module MODULE1( VAR3, VAR21, VAR18, VAR7, VAR63 );
input VAR18, VAR3, VAR21, VAR7;
output VAR63;
reg VAR23;
VAR16 VAR58(.VAR3(VAR3),.VAR21(VAR21),.VAR18(VAR18),.VAR7(VAR7),.VAR63(VAR63),.VAR23(VAR23));
VAR16 VAR52(.VAR3(VAR3),.VAR21(VAR21),.VAR18(VAR18),.VAR7(VAR7),.VAR63(VAR63),.VAR23(VAR23));
and VAR46(VAR42,VAR7,VAR... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_demux.v | 12,982 | module MODULE1 #
(
parameter VAR33 = 4,
parameter VAR88 = 8,
parameter VAR28 = (VAR88>8),
parameter VAR18 = (VAR88/8),
parameter VAR10 = 0,
parameter VAR76 = 8,
parameter VAR41 = 0,
parameter VAR8 = 8,
parameter VAR63 = 1,
parameter VAR2 = 1
)
(
input wire clk,
input wire rst,
input wire VAR87,
output wire VAR34,
input... | mit |
google/xls | xls/uncore_rtl/ice40/uart_transmitter_two_bytes_main.v | 3,311 | module MODULE1(
input wire clk,
output wire VAR17,
output wire VAR20,
output wire VAR3
);
parameter VAR19 = VAR1;
localparam
VAR22 = 'd0,
VAR9 = 'd1,
VAR11 = 'd2,
VAR2 = 'd3;
localparam VAR7 = 2;
reg [VAR7-1:0] state = VAR22;
reg [7:0] VAR16 = 'hff;
reg VAR15 = 0;
reg VAR6 = 1;
reg [VAR7-1:0] VAR5;
reg [7:0] VAR14;
reg... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_axis_dma_tx.v | 6,688 | module MODULE1 (
VAR42,
VAR27,
VAR23,
VAR38,
VAR4,
VAR34,
VAR26,
VAR43,
VAR37,
VAR28,
VAR11,
VAR1,
VAR32,
VAR7,
VAR2,
VAR6,
VAR31);
localparam VAR12 = 32'h00050062;
parameter VAR10 = 0;
input VAR42;
output VAR27;
input VAR23;
output VAR38;
output [31:0] VAR4;
input VAR34;
input VAR26;
input VAR43;
input VAR37;
input VA... | gpl-3.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/ocpi/arSRLFIFO.v | 2,838 | module MODULE1 (VAR8,VAR15,VAR6,VAR2,VAR4,VAR11,VAR16,VAR5,VAR7);
parameter VAR12 = 128;
parameter VAR10 = 5;
parameter VAR1 = 2**VAR10;
input VAR8;
input VAR15;
input VAR7;
input VAR6;
input VAR2;
output VAR4;
output VAR11;
input[VAR12-1:0] VAR16;
output[VAR12-1:0] VAR5;
reg[VAR10-1:0] pos; reg[VAR12-1:0] VAR3[VAR1-1:... | gpl-2.0 |
amrmorsey/Digital-Design-Project | FSMup.v | 1,849 | module MODULE1(
clk, rst, in, out );
input clk, rst;
input in;
output reg [1:0] out;
wire VAR3, VAR8;
assign VAR8 = in;
reg [1:0] state, VAR6;
parameter [1:0] VAR2 = 2'b00, VAR1 = 2'b01, VAR4 = 2'b10, VAR5 = 2'b11;
always @ (VAR8 or state )
if(VAR8 == 2'b0) VAR6 = state;
else
case (state)
VAR2:
begin
if(VAR8) begin VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp.functional.v | 1,214 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR1;
notif1 VAR3 (VAR2 , VAR4, VAR1 );
endmodule | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/IPRepo-1.0.0/Tiger4NSC/src/CRC_generator.v | 8,101 | module MODULE1
parameter VAR12 = 32,
parameter VAR27 = 64,
parameter VAR1 = 13,
parameter VAR11 = 4158,
parameter VAR9 = 2
)
(
VAR40 ,
VAR19 ,
VAR30 ,
VAR33 ,
VAR36 ,
VAR20 ,
VAR6 ,
VAR18 ,
VAR25 ,
VAR32 ,
VAR3 ,
VAR16 ,
VAR10 ,
VAR35 ,
VAR13
);
input VAR40 ;
input VAR19 ;
input VAR30 ;
input VAR33 ;
input [VAR12-1:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand3/sky130_fd_sc_ls__nand3.pp.symbol.v | 1,286 | module MODULE1 (
input VAR3 ,
input VAR2 ,
input VAR7 ,
output VAR6 ,
input VAR8 ,
input VAR1,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
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