code stringlengths 144 85.5k | apis sequence | extract_api stringlengths 121 59.8k |
|---|---|---|
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk12", 0, Pins("4"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("23"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("26"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("27"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("28"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("29"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("30"), IOStandard("LVCMOS33")),
# RGB led, active-low
("rgb_led", 0,
Subsignal("r", Pins("112")),
Subsignal("g", Pins("114")),
Subsignal("b", Pins("113")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("106")),
Subsignal("g", Pins("111")),
Subsignal("b", Pins("110")),
IOStandard("LVCMOS33"),
),
("rgb_led", 2,
Subsignal("r", Pins("101")),
Subsignal("g", Pins("104")),
Subsignal("b", Pins("102")),
IOStandard("LVCMOS33"),
),
("rgb_led", 3,
Subsignal("r", Pins("98")),
Subsignal("g", Pins("100")),
Subsignal("b", Pins("99")),
IOStandard("LVCMOS33"),
),
# Switches
("user_sw", 0, Pins("75"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("76"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("78"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("79"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("80"), IOStandard("LVCMOS33")),
("user_sw", 5, Pins("81"), IOStandard("LVCMOS33")),
("user_sw", 6, Pins("82"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("83"), IOStandard("LVCMOS33")),
# Buttons.
("user_btn", 0, Pins("58"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("59"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("60"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("61"), IOStandard("LVCMOS33")),
("user_btn", 4, Pins("62"), IOStandard("LVCMOS33")),
("user_btn", 5, Pins("63"), IOStandard("LVCMOS33")),
("user_btn", 6, Pins("64"), IOStandard("LVCMOS33")),
("user_btn", 7, Pins("65"), IOStandard("LVCMOS33")),
# Serial.
# FT232H has only one interface -> use (arbitrary) two pins from J2 to
# connect an external USB<->serial adapter
("serial", 0,
Subsignal("tx", Pins("116")), # J2.17
Subsignal("rx", Pins("115")), # J2.18
IOStandard("LVCMOS33")
),
# Seven Segment
("seven_seg_dig", 0, Pins("137"), IOStandard("LVCMOS33")),
("seven_seg_dig", 1, Pins("140"), IOStandard("LVCMOS33")),
("seven_seg_dig", 2, Pins("141"), IOStandard("LVCMOS33")),
("seven_seg_dig", 3, Pins("7"), IOStandard("LVCMOS33")),
("seven_seg", 0, Pins("138 142 9 11 12 139 8 10"), IOStandard("LVCMOS33")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
["J1", "- 38 39 40 41 42 43 44 66 67 68 69 70 71 72 96 95 94 93 -"],
["J2", "- 136 135 134 133 132 131 130 129 128 123 122 121 120 119 118 117 116 115 -"],
]
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1N-4")
self.toolchain.options["use_mspi_as_gpio"] = 1
def create_programmer(self):
return OpenFPGALoader("runber")
def do_finalize(self, fragment):
GowinPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
| [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((3780, 3894), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-UV4LQ144C6/I5"""', '_io', '_connectors'], {'toolchain': 'toolchain', 'devicename': '"""GW1N-4"""'}), "(self, 'GW1N-UV4LQ144C6/I5', _io, _connectors,\n toolchain=toolchain, devicename='GW1N-4')\n", (3802, 3894), False, 'from litex.build.gowin.platform import GowinPlatform\n'), ((3995, 4019), 'litex.build.openfpgaloader.OpenFPGALoader', 'OpenFPGALoader', (['"""runber"""'], {}), "('runber')\n", (4009, 4019), False, 'from litex.build.openfpgaloader import OpenFPGALoader\n'), ((4066, 4107), 'litex.build.gowin.platform.GowinPlatform.do_finalize', 'GowinPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4091, 4107), False, 'from litex.build.gowin.platform import GowinPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2017-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0,
Subsignal("p", Pins("G10"), IOStandard("LVDS")),
Subsignal("n", Pins("F10"), IOStandard("LVDS"))
),
("clk300", 0,
Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")),
Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12"))
),
("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
# Leds
("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
# Buttons
("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")),
("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")),
("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")),
("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")),
("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")),
# Switches
("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")),
("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")),
("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")),
("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")),
# SMA
("user_sma_clock", 0,
Subsignal("p", Pins("D23"), IOStandard("LVDS")),
Subsignal("n", Pins("C23"), IOStandard("LVDS"))
),
("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")),
("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")),
("user_sma_gpio", 0,
Subsignal("p", Pins("H27"), IOStandard("LVDS")),
Subsignal("n", Pins("G27"), IOStandard("LVDS"))
),
("user_sma_gpio_p", 0, Pins("H27"), IOStandard("LVCMOS18")),
("user_sma_gpio_n", 0, Pins("G27"), IOStandard("LVCMOS18")),
# I2C
("i2c", 0,
Subsignal("scl", Pins("J24")),
Subsignal("sda", Pins("J25")),
IOStandard("LVCMOS18")
),
# Serial
("serial", 0,
Subsignal("cts", Pins("L23")),
Subsignal("rts", Pins("K27")),
Subsignal("tx", Pins("K26")),
Subsignal("rx", Pins("G25")),
IOStandard("LVCMOS18")
),
# SPIFlash
("spiflash", 0, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("U7")),
Subsignal("dq", Pins("AC7 AB7 AA7 Y7")),
IOStandard("LVCMOS18")
),
("spiflash", 1, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("G26")),
Subsignal("dq", Pins("M20 L20 R21 R22")),
IOStandard("LVCMOS18")
),
# SDCard
("spisdcard", 0,
Subsignal("clk", Pins("AL10")),
Subsignal("cs_n", Pins("AH8")),
Subsignal("mosi", Pins("AD9"), Misc("PULLUP")),
Subsignal("miso", Pins("AP9"), Misc("PULLUP")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS18")
),
("sdcard", 0,
Subsignal("clk", Pins("AL10")),
Subsignal("cmd", Pins("AD9"), Misc("PULLUP True")),
Subsignal("data", Pins("AP9 AN9 AH9 AH8"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS18")
),
# Rotary Encoder
("rotary", 0,
Subsignal("a", Pins("Y21")),
Subsignal("b", Pins("AD26")),
Subsignal("push", Pins("AF28")),
IOStandard("LVCMOS18")
),
# HDMI
("hdmi", 0,
Subsignal("d", Pins(
"AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12",
"AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11",
"AG10 AK8")),
Subsignal("de", Pins("AE11")),
Subsignal("clk", Pins("AF13")),
Subsignal("vsync", Pins("AH13")),
Subsignal("hsync", Pins("AE13")),
Subsignal("spdif", Pins("AE12")),
Subsignal("spdif_out", Pins("AF12")),
IOStandard("LVCMOS18")
),
# DDR4 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17",
"AF18 AH19 AF15 AD19 AJ14 AG19"),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
#Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
#Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
#Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
IOStandard("POD12_DCI")),
Subsignal("dq", Pins(
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
"AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
"AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23",
"AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
"AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
"AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
"AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32"),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2")),
Subsignal("rx_n", Pins("AB1")),
Subsignal("tx_p", Pins("AC4")),
Subsignal("tx_n", Pins("AC3"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2")),
Subsignal("rx_n", Pins("AB1 AD1")),
Subsignal("tx_p", Pins("AC4 AE4")),
Subsignal("tx_n", Pins("AC3 AE3"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")),
Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5"))
),
("pcie_x8", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
),
# SGMII Clk
("sgmii_clock", 0,
Subsignal("p", Pins("P26"), IOStandard("LVDS_25")),
Subsignal("n", Pins("N26"), IOStandard("LVDS_25"))
),
# SI570
("si570_refclk", 0,
Subsignal("p", Pins("P6")),
Subsignal("n", Pins("P5"))
),
# SMA
("user_sma_mgt_refclk", 0,
Subsignal("p", Pins("V6")),
Subsignal("n", Pins("V5"))
),
("user_sma_mgt_tx", 0,
Subsignal("p", Pins("R4")),
Subsignal("n", Pins("R3"))
),
("user_sma_mgt_rx", 0,
Subsignal("p", Pins("P2")),
Subsignal("n", Pins("P1"))
),
# SFP
("sfp", 0,
Subsignal("txp", Pins("U4")),
Subsignal("txn", Pins("U3")),
Subsignal("rxp", Pins("T2")),
Subsignal("rxn", Pins("T1"))
),
("sfp_tx", 0,
Subsignal("p", Pins("U4")),
Subsignal("n", Pins("U3")),
),
("sfp_rx", 0,
Subsignal("p", Pins("T2")),
Subsignal("n", Pins("T1")),
),
("sfp_tx_disable_n", 0, Pins("AL8"), IOStandard("LVCMOS18")),
("sfp", 1,
Subsignal("txp", Pins("W4")),
Subsignal("txn", Pins("W3")),
Subsignal("rxp", Pins("V2")),
Subsignal("rxn", Pins("V1"))
),
("sfp_tx", 1,
Subsignal("p", Pins("W4")),
Subsignal("n", Pins("W3")),
),
("sfp_rx", 1,
Subsignal("p", Pins("V2")),
Subsignal("n", Pins("V1")),
),
("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"DP0_C2M_P" : "F6",
"DP0_C2M_N" : "F5",
"DP0_M2C_P" : "E4",
"DP0_M2C_N" : "E3",
"DP1_C2M_P" : "D6",
"DP1_C2M_N" : "D5",
"DP1_M2C_P" : "D2",
"DP1_M2C_N" : "D1",
"DP2_C2M_P" : "C4",
"DP2_C2M_N" : "C3",
"DP2_M2C_P" : "B2",
"DP2_M2C_N" : "B1",
"DP3_C2M_P" : "B6",
"DP3_C2M_N" : "B5",
"DP3_M2C_P" : "A4",
"DP3_M2C_N" : "A3",
"DP4_C2M_P" : "N4",
"DP4_C2M_N" : "N3",
"DP4_M2C_P" : "M2",
"DP4_M2C_N" : "M1",
"DP5_C2M_P" : "J4",
"DP5_C2M_N" : "J3",
"DP5_M2C_P" : "H2",
"DP5_M2C_N" : "H1",
"DP6_C2M_P" : "L4",
"DP6_C2M_N" : "L3",
"DP6_M2C_P" : "K2",
"DP6_M2C_N" : "K1",
"DP7_C2M_P" : "G4",
"DP7_C2M_N" : "G3",
"DP7_M2C_P" : "F2",
"DP7_M2C_N" : "F1",
"LA06_P" : "D13",
"LA06_N" : "C13",
"LA10_P" : "L8",
"LA10_N" : "K8",
"LA14_P" : "B10",
"LA14_N" : "A10",
"LA18_CC_P" : "E22",
"LA18_CC_N" : "E23",
"LA27_P" : "H21",
"LA27_N" : "G21",
"HA01_CC_P" : "E16",
"HA01_CC_N" : "D16",
"HA05_P" : "J15",
"HA05_N" : "J14",
"HA09_P" : "F18",
"HA09_N" : "F17",
"HA13_P" : "B14",
"HA13_N" : "A14",
"HA16_P" : "A19",
"HA16_N" : "A18",
"HA20_P" : "C19",
"HA20_N" : "B19",
"CLK1_M2C_P" : "E25",
"CLK1_M2C_N" : "D25",
"LA00_CC_P" : "H11",
"LA00_CC_N" : "G11",
"LA03_P" : "A13",
"LA03_N" : "A12",
"LA08_P" : "J8",
"LA08_N" : "H8",
"LA12_P" : "E10",
"LA12_N" : "D10",
"LA16_P" : "B9",
"LA16_N" : "A9",
"LA20_P" : "B24",
"LA20_N" : "A24",
"LA22_P" : "G24",
"LA22_N" : "F25",
"LA25_P" : "D20",
"LA25_N" : "D21",
"LA29_P" : "B20",
"LA29_N" : "A20",
"LA31_P" : "B25",
"LA31_N" : "A25",
"LA33_P" : "A27",
"LA33_N" : "A28",
"HA03_P" : "G15",
"HA03_N" : "G14",
"HA07_P" : "L19",
"HA07_N" : "L18",
"HA11_P" : "J19",
"HA11_N" : "J18",
"HA14_P" : "F15",
"HA14_N" : "F14",
"HA18_P" : "B17",
"HA18_N" : "B16",
"HA22_P" : "C18",
"HA22_N" : "C17",
"GBTCLK1_M2C_P" : "H6",
"GBTCLK1_M2C_N" : "H5",
"GBTCLK0_M2C_P" : "K6",
"GBTCLK0_M2C_N" : "K5",
"LA01_CC_P" : "G9",
"LA01_CC_N" : "F9",
"LA05_P" : "L13",
"LA05_N" : "K13",
"LA09_P" : "J9",
"LA09_N" : "H9",
"LA13_P" : "D9",
"LA13_N" : "C9",
"LA17_CC_P" : "D24",
"LA17_CC_N" : "C24",
"LA23_P" : "G22",
"LA23_N" : "F22",
"LA26_P" : "G20",
"LA26_N" : "F20",
"PG_M2C" : "L27",
"HA00_CC_P" : "G17",
"HA00_CC_N" : "G16",
"HA04_P" : "G19",
"HA04_N" : "F19",
"HA08_P" : "K18",
"HA08_N" : "K17",
"HA12_P" : "K16",
"HA12_N" : "J16",
"HA15_P" : "D14",
"HA15_N" : "C14",
"HA19_P" : "D19",
"HA19_N" : "D18",
"PRSNT_M2C_B" : "H24",
"CLK0_M2C_P" : "H12",
"CLK0_M2C_N" : "G12",
"LA02_P" : "K10",
"LA02_N" : "J10",
"LA04_P" : "L12",
"LA04_N" : "K12",
"LA07_P" : "F8",
"LA07_N" : "E8",
"LA11_P" : "K11",
"LA11_N" : "J11",
"LA15_P" : "D8",
"LA15_N" : "C8",
"LA19_P" : "C21",
"LA19_N" : "C22",
"LA21_P" : "F23",
"LA21_N" : "F24",
"LA24_P" : "E20",
"LA24_N" : "E21",
"LA28_P" : "B21",
"LA28_N" : "B22",
"LA30_P" : "C26",
"LA30_N" : "B26",
"LA32_P" : "E26",
"LA32_N" : "D26",
"HA02_P" : "H19",
"HA02_N" : "H18",
"HA06_P" : "L15",
"HA06_N" : "K15",
"HA10_P" : "H17",
"HA10_N" : "H16",
"HA17_CC_P" : "E18",
"HA17_CC_N" : "E17",
"HA21_P" : "E15",
"HA21_N" : "D15",
"HA23_P" : "B15",
"HA23_N" : "A15",
}
),
("LPC", {
"GBTCLK0_M2C_P" : "AA24",
"GBTCLK0_M2C_N" : "AA25",
"LA01_CC_P" : "W25",
"LA01_CC_N" : "Y25",
"LA05_P" : "V27",
"LA05_N" : "V28",
"LA09_P" : "V26",
"LA09_N" : "W26",
"LA13_P" : "AA20",
"LA13_N" : "AB20",
"LA17_CC_P" : "AA32",
"LA17_CC_N" : "AB32",
"LA23_P" : "AD30",
"LA23_N" : "AD31",
"LA26_P" : "AF33",
"LA26_N" : "AG34",
"CLK0_M2C_P" : "AA24",
"CLK0_M2C_N" : "AA25",
"LA02_P" : "AA22",
"LA02_N" : "AB22",
"LA04_P" : "U26",
"LA04_N" : "U27",
"LA07_P" : "V22",
"LA07_N" : "V23",
"LA11_P" : "V21",
"LA11_N" : "W21",
"LA15_P" : "AB25",
"LA15_N" : "AB26",
"LA19_P" : "AA29",
"LA19_N" : "AB29",
"LA21_P" : "AC33",
"LA21_N" : "AD33",
"LA24_P" : "AE32",
"LA24_N" : "AF32",
"LA28_P" : "V31",
"LA28_N" : "W31",
"LA30_P" : "Y31",
"LA30_N" : "Y32",
"LA32_P" : "W30",
"LA32_N" : "Y30",
"LA06_P" : "V29",
"LA06_N" : "W29",
"LA10_P" : "T22",
"LA10_N" : "T23",
"LA14_P" : "U21",
"LA14_N" : "U22",
"LA18_CC_P" : "AB30",
"LA18_CC_N" : "AB31",
"LA27_P" : "AG31",
"LA27_N" : "AG32",
"CLK1_M2C_P" : "AC31",
"CLK1_M2C_N" : "AC32",
"LA00_CC_P" : "W23",
"LA00_CC_N" : "W24",
"LA03_P" : "W28",
"LA03_N" : "Y28",
"LA08_P" : "U24",
"LA08_N" : "U25",
"LA12_P" : "AC22",
"LA12_N" : "AC23",
"LA16_P" : "AB21",
"LA16_N" : "AC21",
"LA20_P" : "AA34",
"LA20_N" : "AB34",
"LA22_P" : "AC34",
"LA22_N" : "AD34",
"LA25_P" : "AE33",
"LA25_N" : "AF34",
"LA29_P" : "U34",
"LA29_N" : "V34",
"LA31_P" : "V33",
"LA31_N" : "W34",
"LA33_P" : "W33",
"LA33_N" : "Y33",
}
),
("pmod0", "AK25 AN21 AH18 AM19 AE26 AF25 AE21 AM17"),
("pmod1", "AL14 AM14 AP16 AP15 AM16 AM15 AN18 AN17"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((18029, 18124), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xcku040-ffva1156-2-e"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xcku040-ffva1156-2-e', _io, _connectors,\n toolchain='vivado')\n", (18052, 18124), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((18170, 18188), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (18186, 18188), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((18235, 18277), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (18261, 18277), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Board diagram/pinout:
# https://user-images.githubusercontent.com/1450143/133655492-532d5e9a-0635-4889-85c9-68683d06cae0.png
# http://dl.sipeed.com/TANG/Nano/HDK/Tang-NANO-2704(Schematic).pdf
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk24", 0, Pins("35"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("16"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("17"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("18"), IOStandard("LVCMOS33")),
# Buttons.
("user_btn", 0, Pins("15"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("14"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("8")),
Subsignal("rx", Pins("9")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):
default_clk_name = "clk24"
default_clk_period = 1e9/24e6
def __init__(self):
GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-1")
self.toolchain.options["use_done_as_gpio"] = 1
def create_programmer(self):
return OpenFPGALoader("tangnano")
def do_finalize(self, fragment):
GowinPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
| [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((1481, 1592), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-LV1QN48C6/I5"""', '_io', '_connectors'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1N-1"""'}), "(self, 'GW1N-LV1QN48C6/I5', _io, _connectors,\n toolchain='gowin', devicename='GW1N-1')\n", (1503, 1592), False, 'from litex.build.gowin.platform import GowinPlatform\n'), ((1693, 1719), 'litex.build.openfpgaloader.OpenFPGALoader', 'OpenFPGALoader', (['"""tangnano"""'], {}), "('tangnano')\n", (1707, 1719), False, 'from litex.build.openfpgaloader import OpenFPGALoader\n'), ((1766, 1807), 'litex.build.gowin.platform.GowinPlatform.do_finalize', 'GowinPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1791, 1807), False, 'from litex.build.gowin.platform import GowinPlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 msloniewski <<EMAIL>>
# Copyright (c) 2019 vytautasb <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import subprocess
import sys
import math
from shutil import which
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools
# IO/Placement Constraints (.qsf) ------------------------------------------------------------------
def _format_constraint(c, signame, fmt_r):
# IO location constraints
if isinstance(c, Pins):
tpl = "set_location_assignment -comment \"{name}\" -to {signame} Pin_{pin}"
return tpl.format(signame=signame, name=fmt_r, pin=c.identifiers[0])
# IO standard constraints
elif isinstance(c, IOStandard):
tpl = "set_instance_assignment -name io_standard -comment \"{name}\" \"{std}\" -to {signame}"
return tpl.format(signame=signame, name=fmt_r, std=c.name)
# Others constraints
elif isinstance(c, Misc):
if not isinstance(c.misc, str) and len(c.misc) == 2:
tpl = "set_instance_assignment -comment \"{name}\" -name {misc[0]} \"{misc[1]}\" -to {signame}"
return tpl.format(signame=signame, name=fmt_r, misc=c.misc)
else:
tpl = "set_instance_assignment -comment \"{name}\" -name {misc} -to {signame}"
return tpl.format(signame=signame, name=fmt_r, misc=c.misc)
def _format_qsf_constraint(signame, pin, others, resname):
fmt_r = "{}:{}".format(*resname[:2])
if resname[2] is not None:
fmt_r += "." + resname[2]
fmt_c = [_format_constraint(c, signame, fmt_r) for c in ([Pins(pin)] + others)]
return '\n'.join(fmt_c)
def _build_qsf_constraints(named_sc, named_pc):
qsf = []
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
qsf.append(_format_qsf_constraint("{}[{}]".format(sig, i), p, others, resname))
else:
qsf.append(_format_qsf_constraint(sig, pins[0], others, resname))
if named_pc:
qsf.append("\n\n".join(named_pc))
return "\n".join(qsf)
# Timing Constraints (.sdc) ------------------------------------------------------------------------
def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_commands):
sdc = []
# Clock constraints
for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
is_port = False
for sig, pins, others, resname in named_sc:
if sig == vns.get_name(clk):
is_port = True
if is_port:
tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
else:
tpl = "create_clock -name {clk} -period {period} [get_nets {{{clk}}}]"
sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
# False path constraints
for from_, to in sorted(false_paths, key=lambda x: (x[0].duid, x[1].duid)):
tpl = "set_false_path -from [get_clocks {{{from_}}}] -to [get_clocks {{{to}}}]"
sdc.append(tpl.format(from_=vns.get_name(from_), to=vns.get_name(to)))
# Add additional commands
sdc += additional_sdc_commands
# Generate .sdc
tools.write_to_file("{}.sdc".format(build_name), "\n".join(sdc))
# Project (.qsf) -----------------------------------------------------------------------------------
def _build_qsf(device, ips, sources, vincpaths, named_sc, named_pc, build_name, additional_qsf_commands):
qsf = []
# Set device
qsf.append("set_global_assignment -name DEVICE {}".format(device))
# Add sources
for filename, language, library in sources:
if language == "verilog": language = "systemverilog" # Enforce use of SystemVerilog
tpl = "set_global_assignment -name {lang}_FILE {path} -library {lib}"
# Do not add None type files
if language is not None:
qsf.append(tpl.format(lang=language.upper(), path=filename.replace("\\", "/"), lib=library))
# Check if the file is a header. Those should not be explicitly added to qsf,
# but rather included in include search_path
else:
if filename.endswith(".svh") or filename.endswith(".vh"):
fpath = os.path.dirname(filename)
if fpath not in vincpaths:
vincpaths.append(fpath)
# Add ips
for filename in ips:
tpl = "set_global_assignment -name QSYS_FILE {filename}"
qsf.append(tpl.replace(filename=filename.replace("\\", "/")))
# Add include paths
for path in vincpaths:
qsf.append("set_global_assignment -name SEARCH_PATH {}".format(path.replace("\\", "/")))
# Set top level
qsf.append("set_global_assignment -name top_level_entity " + build_name)
# Add io, placement constraints
qsf.append(_build_qsf_constraints(named_sc, named_pc))
# Set timing constraints
qsf.append("set_global_assignment -name SDC_FILE {}.sdc".format(build_name))
# Add additional commands
qsf += additional_qsf_commands
# Generate .qsf
tools.write_to_file("{}.qsf".format(build_name), "\n".join(qsf))
# Script -------------------------------------------------------------------------------------------
def _build_script(build_name, create_rbf):
if sys.platform in ["win32", "cygwin"]:
script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
script_file = "build_" + build_name + ".bat"
else:
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
script_file = "build_" + build_name + ".sh"
script_contents += """
quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_sta {build_name} -c {build_name}"""
if create_rbf:
script_contents += """
if [ -f "{build_name}.sof" ]
then
quartus_cpf -c {build_name}.sof {build_name}.rbf
fi
"""
script_contents = script_contents.format(build_name=build_name)
tools.write_to_file(script_file, script_contents, force_unix=True)
return script_file
def _run_script(script):
if sys.platform in ["win32", "cygwin"]:
shell = ["cmd", "/c"]
else:
shell = ["bash"]
if which("quartus_map") is None:
msg = "Unable to find Quartus toolchain, please:\n"
msg += "- Add Quartus toolchain to your $PATH."
raise OSError(msg)
if subprocess.call(shell + [script]) != 0:
raise OSError("Error occured during Quartus's script execution.")
# AlteraQuartusToolchain ---------------------------------------------------------------------------
class AlteraQuartusToolchain:
attr_translate = {}
def __init__(self):
self.clocks = dict()
self.false_paths = set()
self.additional_sdc_commands = []
self.additional_qsf_commands = []
def build(self, platform, fragment,
build_dir = "build",
build_name = "top",
run = True,
**kwargs):
# Create build directory
cwd = os.getcwd()
os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir)
# Finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# Generate verilog
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
platform.add_source(v_file)
# Generate design timing constraints file (.sdc)
_build_sdc(
clocks = self.clocks,
false_paths = self.false_paths,
vns = v_output.ns,
named_sc = named_sc,
build_name = build_name,
additional_sdc_commands = self.additional_sdc_commands)
# Generate design project and location constraints file (.qsf)
_build_qsf(
device = platform.device,
ips = platform.ips,
sources = platform.sources,
vincpaths = platform.verilog_include_paths,
named_sc = named_sc,
named_pc = named_pc,
build_name = build_name,
additional_qsf_commands = self.additional_qsf_commands)
# Generate build script
script = _build_script(build_name, platform.create_rbf)
# Run
if run:
_run_script(script)
os.chdir(cwd)
return v_output.ns
def add_period_constraint(self, platform, clk, period):
clk.attr.add("keep")
period = math.floor(period*1e3)/1e3 # round to lowest picosecond
if clk in self.clocks:
if period != self.clocks[clk]:
raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
.format(self.clocks[clk], period))
self.clocks[clk] = period
def add_false_path_constraint(self, platform, from_, to):
from_.attr.add("keep")
to.attr.add("keep")
if (to, from_) not in self.false_paths:
self.false_paths.add((from_, to))
| [
"litex.build.tools.get_litex_git_revision",
"litex.build.generic_platform.Pins",
"litex.build.tools.write_to_file"
] | [((6393, 6459), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(True)'}), '(script_file, script_contents, force_unix=True)\n', (6412, 6459), False, 'from litex.build import tools\n'), ((6627, 6647), 'shutil.which', 'which', (['"""quartus_map"""'], {}), "('quartus_map')\n", (6632, 6647), False, 'from shutil import which\n'), ((6808, 6841), 'subprocess.call', 'subprocess.call', (['(shell + [script])'], {}), '(shell + [script])\n', (6823, 6841), False, 'import subprocess\n'), ((7460, 7471), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (7469, 7471), False, 'import os\n'), ((7480, 7517), 'os.makedirs', 'os.makedirs', (['build_dir'], {'exist_ok': '(True)'}), '(build_dir, exist_ok=True)\n', (7491, 7517), False, 'import os\n'), ((7526, 7545), 'os.chdir', 'os.chdir', (['build_dir'], {}), '(build_dir)\n', (7534, 7545), False, 'import os\n'), ((9088, 9101), 'os.chdir', 'os.chdir', (['cwd'], {}), '(cwd)\n', (9096, 9101), False, 'import os\n'), ((5584, 5614), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (5612, 5614), False, 'from litex.build import tools\n'), ((5741, 5771), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (5769, 5771), False, 'from litex.build import tools\n'), ((9237, 9264), 'math.floor', 'math.floor', (['(period * 1000.0)'], {}), '(period * 1000.0)\n', (9247, 9264), False, 'import math\n'), ((4431, 4456), 'os.path.dirname', 'os.path.dirname', (['filename'], {}), '(filename)\n', (4446, 4456), False, 'import os\n'), ((1721, 1730), 'litex.build.generic_platform.Pins', 'Pins', (['pin'], {}), '(pin)\n', (1725, 1730), False, 'from litex.build.generic_platform import Pins, IOStandard, Misc\n')] |
#!/usr/bin/env python3
import time
from statistics import mean
from litex import RemoteClient
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
# # #
# Read frequency meter
fmeter_values = []
print("Reading frequency...")
for i in range(100):
fmeter_value = wb.regs.fmeter_value.read()
print(fmeter_value)
fmeter_values.append(fmeter_value)
time.sleep(1.0)
print(f'average: {mean(fmeter_values)}')
| [
"litex.RemoteClient"
] | [((102, 138), 'litex.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (114, 138), False, 'from litex import RemoteClient\n'), ((364, 379), 'time.sleep', 'time.sleep', (['(1.0)'], {}), '(1.0)\n', (374, 379), False, 'import time\n'), ((398, 417), 'statistics.mean', 'mean', (['fmeter_values'], {}), '(fmeter_values)\n', (402, 417), False, 'from statistics import mean\n')] |
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from bft import Bft
from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface
from litex.soc.interconnect.stream import (ClockDomainCrossing, Converter,
Endpoint)
from migen import *
from pld_axi import *
class Leaf(Module):
def __init__(self, clk, rst, start, platform):
self.platform = platform
self.clk = clk
self.reset = rst
self.start = start
self.resend = 0
self.din_leaf_bft2interface_1 = Signal(49, name="din_leaf_bft2interface_1")
self.dout_leaf_interface2bft_1 = Signal(49, name="dout_leaf_interface2bft_1")
self.din_leaf_bft2interface_2 = Signal(49, name="din_leaf_bft2interface_2")
self.dout_leaf_interface2bft_2 = Signal(49, name="dout_leaf_interface2bft_2")
def connect_input(self, din, dout):
self.comb += self.din_leaf_bft2interface_1.eq(din)
self.comb += dout.eq(self.dout_leaf_interface2bft_1)
def connect_output(self, din, dout):
self.comb += self.din_leaf_bft2interface_2.eq(din)
self.comb += dout.eq(self.dout_leaf_interface2bft_2)
class Leaf2(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_2",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class Leaf3(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_3",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class Leaf4(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_4",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class Leaf5(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_5",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class InterfaceWrapperLeafOnly(Module):
def __init__(self, clk, rst, platform, clock_domain="bft"):
self.source = PldAXIStreamInterface(data_width=32)
self.sink = PldAXIStreamInterface(data_width=32)
self.clk = clk
self.rst = rst
self.resend = Signal(1, name="resend")
self.din_leaf_bft2interface_1 = Signal(49, name="din_leaf_bft2interface_1")
self.dout_leaf_interface2bft_1 = Signal(49, name="dout_leaf_interface2bft_1")
self.din_leaf_bft2interface_2 = Signal(49, name="din_leaf_bft2interface_2")
self.dout_leaf_interface2bft_2 = Signal(49, name="dout_leaf_interface2bft_2")
self.platform = platform
source_sigs = self.source.get_signals()
sink_sigs = self.sink.get_signals()
self.specials += Instance(
"InterfaceWrapperLeafOnly",
i_clk=self.clk,
i_reset=self.rst,
i_resend=self.resend,
# bft interface
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
# stream interface
i_Input_1_V_V=sink_sigs["tpayload"].data,
i_Input_1_V_V_ap_vld=sink_sigs["tvalid"],
o_Input_1_V_V_ap_ack=sink_sigs["tready"],
o_Output_1_V_V=source_sigs["tpayload"].data,
o_Output_1_V_V_ap_vld=source_sigs["tvalid"],
i_Output_1_V_V_ap_ack=source_sigs["tready"],
)
def connect_input(self, stream):
assert isinstance(stream, Endpoint)
assert stream.payload.data.nbits == 32
self.comb += stream.connect(self.sink)
def connect_output(self, stream):
assert isinstance(stream, Endpoint)
assert stream.payload.data.nbits == 32
self.comb += self.source.connect(stream)
class RenderingLeafOnly(Module):
def __init__(self, clk, rst, platform, start=1, clock_domain="bft"):
self.axil = AXILiteInterface(
data_width=32, address_width=5, clock_domain=clock_domain
)
self.clk = clk
self.rst = rst
self.start = start
self.platform = platform
self.clock_domain = clock_domain
self.submodules.interface_wrapper = (
interface_wrapper
) = InterfaceWrapperLeafOnly(clk, rst, platform)
self.submodules.leaf_2 = leaf_2 = Leaf2(clk, rst, start, platform)
self.submodules.leaf_3 = leaf_3 = Leaf3(clk, rst, start, platform)
self.submodules.leaf_4 = leaf_4 = Leaf4(clk, rst, start, platform)
self.submodules.leaf_5 = leaf_5 = Leaf5(clk, rst, start, platform)
data_1 = Signal(49)
data_2 = Signal(49)
data_3 = Signal(49)
data_4 = Signal(49)
data_5 = Signal(49)
data_6 = Signal(49)
data_7 = Signal(49)
data_8 = Signal(49)
data_9 = Signal(49)
data_a = Signal(49)
# interface_wrapper
self.comb += data_1.eq(interface_wrapper.dout_leaf_interface2bft_1)
self.comb += interface_wrapper.din_leaf_bft2interface_1.eq(data_3)
self.comb += data_2.eq(interface_wrapper.dout_leaf_interface2bft_2)
self.comb += interface_wrapper.din_leaf_bft2interface_2.eq(data_4)
# self.comb += interface_wrapper.din_leaf_bft2interface_2.eq(interface_wrapper.dout_leaf_interface2bft_1)
# self.comb += interface_wrapper.din_leaf_bft2interface_1.eq(interface_wrapper.dout_leaf_interface2bft_2)
self.comb += interface_wrapper.resend.eq(0)
# leaves
leaf_2.connect_input(data_1, data_3)
leaf_2.connect_output(data_5, data_6)
leaf_3.connect_input(data_6, data_5)
leaf_3.connect_output(data_7, data_8)
leaf_4.connect_input(data_8, data_7)
leaf_4.connect_output(data_9, data_a)
leaf_5.connect_input(data_a, data_9)
leaf_5.connect_output(data_2, data_4)
self.platform.add_source_dir("rtl/leaf_interface/")
self.platform.add_source_dir("rtl/rendering_leaf_only/")
self.platform.add_source("rtl/SynFIFO.v")
def connect_input(self, stream, clock_domain="sys"):
assert isinstance(stream, Endpoint)
input_stream = stream
# if clock_domain != self.clock_domain:
# from IPython import embed; embed()
# self.submodules.input_cross_domain_converter = input_cross_domain_converter = \
# ClockDomainCrossing(input_stream.description, cd_from=clock_domain, cd_to=self.clock_domain, depth=8)
# mm2s_axis_bft = AXIStreamInterface(32)
# self.comb += input_stream.connect(input_cross_domain_converter.sink)
# self.comb += input_cross_domain_converter.source.connect(mm2s_axis_bft)
# input_stream = mm2s_axis_bft
self.interface_wrapper.connect_input(input_stream)
def connect_output(self, stream, clock_domain="sys"):
assert isinstance(stream, Endpoint)
output_stream = stream
# if clock_domain != self.clock_domain:
# from IPython import embed; embed()
# self.submodules.output_cross_domain_converter = output_cross_domain_converter = \
# ClockDomainCrossing(output_stream.description, cd_from=self.clock_domain, cd_to=clock_domain, depth=8)
# s2mm_axis_bft = AXIStreamInterface(32)
# self.comb += output_cross_domain_converter.source.connect(output_stream)
# self.comb += s2mm_axis_bft.connect(output_cross_domain_converter.sink)
# output_stream = s2mm_axis_bft
self.interface_wrapper.connect_output(output_stream)
| [
"litex.soc.interconnect.axi.AXILiteInterface"
] | [((5719, 5794), 'litex.soc.interconnect.axi.AXILiteInterface', 'AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(5)', 'clock_domain': 'clock_domain'}), '(data_width=32, address_width=5, clock_domain=clock_domain)\n', (5735, 5794), False, 'from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface\n')] |
from litex.tools.litex_client import RemoteClient
wb = RemoteClient("192.168.1.50", 1234, csr_data_width=8)
wb.open()
regs = wb.regs
# # #
print("temperature: %f°C" %(regs.xadc_temperature.read()*503.975/4096 - 273.15))
print("vccint: %fV" %(regs.xadc_vccint.read()/4096*3))
print("vccaux: %fV" %(regs.xadc_vccaux.read()/4096*3))
print("vccbram: %fV" %(regs.xadc_vccbram.read()/4096*3))
# # #
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((56, 108), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', (['"""192.168.1.50"""', '(1234)'], {'csr_data_width': '(8)'}), "('192.168.1.50', 1234, csr_data_width=8)\n", (68, 108), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import csv
import logging
import argparse
from operator import and_
from functools import reduce
from itertools import zip_longest
from migen import *
from migen.genlib.misc import WaitTimer
from litex.build.sim.config import SimConfig
from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.tools.litex_sim import SimSoC
from litedram.frontend.bist import _LiteDRAMBISTGenerator, _LiteDRAMBISTChecker, \
_LiteDRAMPatternGenerator, _LiteDRAMPatternChecker
# LiteDRAM Benchmark SoC ---------------------------------------------------------------------------
class LiteDRAMBenchmarkSoC(SimSoC):
def __init__(self,
sdram_module = "MT48LC16M16",
sdram_data_width = 32,
bist_base = 0x0000000,
bist_end = 0x0100000,
bist_length = 1024,
bist_random = False,
bist_alternating = False,
num_generators = 1,
num_checkers = 1,
pattern_init = None,
**kwargs):
# SimSoC -----------------------------------------------------------------------------------
SimSoC.__init__(self,
with_sdram = True,
sdram_module = sdram_module,
sdram_data_width = sdram_data_width,
**kwargs
)
# BIST Generator / Checker -----------------------------------------------------------------
# make sure that we perform at least one access
bist_length = max(bist_length, self.sdram.controller.interface.data_width // 8)
custom_pattern_mode = pattern_init is not None
if custom_pattern_mode:
make_generator = lambda: _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=pattern_init)
make_checker = lambda: _LiteDRAMPatternChecker(self.sdram.crossbar.get_port(), init=pattern_init)
else:
make_generator = lambda: _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
make_checker = lambda: _LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
generators = [make_generator() for _ in range(num_generators)]
checkers = [make_checker() for _ in range(num_checkers)]
self.submodules += generators + checkers
if custom_pattern_mode:
def bist_config(module):
return []
if not bist_alternating:
address_set = set()
for addr, _ in pattern_init:
assert addr not in address_set, \
'Duplicate address 0x%08x in pattern_init, write will overwrite previous value!' % addr
address_set.add(addr)
else:
def bist_config(module):
return [
module.base.eq(bist_base),
module.end.eq(bist_end),
module.length.eq(bist_length),
module.random_addr.eq(bist_random),
]
assert not (bist_random and not bist_alternating), \
'Write to random address may overwrite previously written data before reading!'
# check address correctness
assert bist_end > bist_base
assert bist_end <= 2**(len(generators[0].end)) - 1, 'End address outside of range'
bist_addr_range = bist_end - bist_base
assert bist_addr_range > 0 and bist_addr_range & (bist_addr_range - 1) == 0, \
'Length of the address range must be a power of 2'
def combined_read(modules, signal, operator):
sig = Signal()
self.comb += sig.eq(reduce(operator, (getattr(m, signal) for m in modules)))
return sig
def combined_write(modules, signal):
sig = Signal()
self.comb += [getattr(m, signal).eq(sig) for m in modules]
return sig
# Sequencer --------------------------------------------------------------------------------
class LiteDRAMCoreControl(Module, AutoCSR):
def __init__(self):
self.init_done = CSRStorage()
self.init_error = CSRStorage()
self.submodules.ddrctrl = ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
display = Signal()
finish = Signal()
self.submodules.fsm = fsm = FSM(reset_state="WAIT-INIT")
fsm.act("WAIT-INIT",
If(self.ddrctrl.init_done.storage, # Written by CPU when initialization is done
NextState("BIST-GENERATOR")
)
)
if bist_alternating:
# force generators to wait for checkers and vice versa
# connect them in pairs, with each unpaired connected to the first of the others
bist_connections = []
for generator, checker in zip_longest(generators, checkers):
g = generator or generators[0]
c = checker or checkers[0]
bist_connections += g.run.eq(c.ready), c.run.eq(g.ready)
fsm.act("BIST-GENERATOR",
combined_write(generators + checkers, 'start').eq(1),
*bist_connections,
*map(bist_config, generators + checkers),
If(combined_read(checkers, 'done', and_),
NextState("DISPLAY")
)
)
else:
fsm.act("BIST-GENERATOR",
combined_write(generators, 'start').eq(1),
combined_write(generators, 'run').eq(1),
*map(bist_config, generators),
If(combined_read(generators, 'done', and_),
NextState("BIST-CHECKER")
)
)
fsm.act("BIST-CHECKER",
combined_write(checkers, 'start').eq(1),
combined_write(checkers, 'run').eq(1),
*map(bist_config, checkers),
If(combined_read(checkers, 'done', and_),
NextState("DISPLAY")
)
)
fsm.act("DISPLAY",
display.eq(1),
NextState("FINISH")
)
fsm.act("FINISH",
finish.eq(1)
)
# Simulation Results -----------------------------------------------------------------------
def max_signal(signals):
signals = iter(signals)
s = next(signals)
out = Signal(len(s))
self.comb += out.eq(s)
for curr in signals:
prev = out
out = Signal(max(len(prev), len(curr)))
self.comb += If(prev > curr, out.eq(prev)).Else(out.eq(curr))
return out
generator_ticks = max_signal((g.ticks for g in generators))
checker_errors = max_signal((c.errors for c in checkers))
checker_ticks = max_signal((c.ticks for c in checkers))
self.sync += [
If(display,
Display("BIST-GENERATOR ticks: %08d", generator_ticks),
Display("BIST-CHECKER errors: %08d", checker_errors),
Display("BIST-CHECKER ticks: %08d", checker_ticks),
)
]
# Simulation End ---------------------------------------------------------------------------
end_timer = WaitTimer(2**16)
self.submodules += end_timer
self.comb += end_timer.wait.eq(finish)
self.sync += If(end_timer.done, Finish())
# Build --------------------------------------------------------------------------------------------
def load_access_pattern(filename):
with open(filename, newline='') as f:
reader = csv.reader(f)
pattern_init = [(int(addr, 0), int(data, 0)) for addr, data in reader]
return pattern_init
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Benchmark SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
parser.add_argument("--bist-alternating", action="store_true", help="Perform alternating writes/reads (WRWRWR... instead of WWW...RRR...)")
parser.add_argument("--num-generators", default=1, help="Number of BIST generators")
parser.add_argument("--num-checkers", default=1, help="Number of BIST checkers")
parser.add_argument("--access-pattern", help="Load access pattern (address, data) from CSV (ignores --bist-*)")
parser.add_argument("--log-level", default="info", help="Set logging verbosity",
choices=['critical', 'error', 'warning', 'info', 'debug'])
args = parser.parse_args()
root_logger = logging.getLogger()
root_logger.setLevel(getattr(logging, args.log_level.upper()))
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
# Configuration --------------------------------------------------------------------------------
soc_kwargs["with_uart"] = False
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
soc_kwargs["bist_base"] = int(args.bist_base, 0)
soc_kwargs["bist_length"] = int(args.bist_length, 0)
soc_kwargs["bist_random"] = args.bist_random
soc_kwargs["bist_alternating"] = args.bist_alternating
soc_kwargs["num_generators"] = int(args.num_generators)
soc_kwargs["num_checkers"] = int(args.num_checkers)
if args.access_pattern:
soc_kwargs["pattern_init"] = load_access_pattern(args.access_pattern)
# SoC ------------------------------------------------------------------------------------------
soc = LiteDRAMBenchmarkSoC(**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(
threads = args.threads,
sim_config = sim_config,
opt_level = args.opt_level,
trace = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end)
)
if __name__ == "__main__":
main()
| [
"litex.tools.litex_sim.SimSoC.__init__",
"litex.build.sim.config.SimConfig"
] | [((7932, 8004), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteDRAM Benchmark SoC Simulation"""'}), "(description='LiteDRAM Benchmark SoC Simulation')\n", (7955, 8004), False, 'import argparse\n'), ((9954, 9973), 'logging.getLogger', 'logging.getLogger', ([], {}), '()\n', (9971, 9973), False, 'import logging\n'), ((10148, 10180), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {'default_clk': '"""sys_clk"""'}), "(default_clk='sys_clk')\n", (10157, 10180), False, 'from litex.build.sim.config import SimConfig\n'), ((1276, 1390), 'litex.tools.litex_sim.SimSoC.__init__', 'SimSoC.__init__', (['self'], {'with_sdram': '(True)', 'sdram_module': 'sdram_module', 'sdram_data_width': 'sdram_data_width'}), '(self, with_sdram=True, sdram_module=sdram_module,\n sdram_data_width=sdram_data_width, **kwargs)\n', (1291, 1390), False, 'from litex.tools.litex_sim import SimSoC\n'), ((7440, 7458), 'migen.genlib.misc.WaitTimer', 'WaitTimer', (['(2 ** 16)'], {}), '(2 ** 16)\n', (7449, 7458), False, 'from migen.genlib.misc import WaitTimer\n'), ((7788, 7801), 'csv.reader', 'csv.reader', (['f'], {}), '(f)\n', (7798, 7801), False, 'import csv\n'), ((4976, 5009), 'itertools.zip_longest', 'zip_longest', (['generators', 'checkers'], {}), '(generators, checkers)\n', (4987, 5009), False, 'from itertools import zip_longest\n')] |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
rom_base = 0x00000000
dump_size = 0x8000
words_per_packet = 128
wb = RemoteClient()
wb.open()
# # #
print("dumping cpu rom to dump.bin...")
dump = []
for n in range(dump_size//(words_per_packet*4)):
dump += wb.read(rom_base + n*words_per_packet*4, words_per_packet)
f = open("dump.bin", "wb")
for v in dump:
f.write(v.to_bytes(4, byteorder="big"))
f.close()
# # #
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((144, 158), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (156, 158), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020-21 gatecat <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import crosslink_nx_vip
from litex_boards.platforms import crosslink_nx_vip
from litehyperbus.core.hyperbus import HyperRAM
from litex.soc.cores.ram import NXLRAM
from litex.soc.cores.spi_flash import SpiFlash
from litex.build.io import CRG
from litex.build.generic_platform import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.freqmeter import FreqMeter
from litex.soc.cores.gpio import GPIOIn
from litex.build.lattice.oxide import oxide_args, oxide_argdict
from dphy_wrapper import DPHY_CSIRX_CIL
from mipi_csi import *
kB = 1024
mB = 1024*kB
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain()
# TODO: replace with PLL
# Clocking
self.submodules.sys_clk = sys_osc = NXOSCA()
sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
# use cam_reset here because it's also hardwired to the reset of the cameras
rst_n = platform.request("cam_reset")
# Power On Reset
por_cycles = 4096
por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0) | self.rst)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x40000000,
"main_ram": 0x50000000,
"csr": 0xf0000000,
}
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs):
platform = crosslink_nx_vip.Platform(toolchain=toolchain)
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
kwargs["integrated_sram_size"] = 0
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Crosslink-NX VIP Input Board",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB LRAM (used as SRAM) ------------------------------------------------------------
size = 128*kB
self.submodules.spram = NXLRAM(32, size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
# Use HyperRAM generic PHY as main ram -----------------------------------------------------
size = 8*1024*kB
hr_pads = platform.request("hyperram", 0)
self.submodules.hyperram = HyperRAM(hr_pads)
self.register_mem("main_ram", self.mem_map["main_ram"], self.hyperram.bus, size)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
refclk = platform.request("clk27_0")
cam_mclk = platform.request("camera_mclk", 0)
self.comb += cam_mclk.eq(refclk)
self.submodules.i2c = I2CMaster(platform.request("i2c", 0))
self.add_csr("i2c")
self.submodules.dphy = DPHY_CSIRX_CIL(
pads = platform.request("camera", 0),
num_lanes = 4,
clk_mode = "ENABLED",
deskew = "DISABLED",
gearing = 8,
loc = "TDPHY_CORE2",
)
self.comb += [
self.dphy.sync_clk.eq(ClockSignal()),
self.dphy.sync_rst.eq(ResetSignal()),
self.dphy.pd_dphy.eq(0),
self.dphy.hs_rx_en.eq(1),
]
self.submodules.clk_byte_freq = FreqMeter(period=sys_clk_freq, clk=self.dphy.clk_byte)
self.add_csr("clk_byte_freq")
self.submodules.hs_rx_data = GPIOIn(pads=self.dphy.hs_rx_data)
self.add_csr("hs_rx_data")
self.submodules.hs_rx_sync = GPIOIn(pads=self.dphy.hs_rx_sync)
self.add_csr("hs_rx_sync")
self.clock_domains.cd_mipi = ClockDomain()
self.comb += self.cd_mipi.clk.eq(self.dphy.clk_byte)
dphy_header = Signal(32)
for i in range(0, 4):
prev_sync = Signal()
self.sync.mipi += prev_sync.eq(self.dphy.hs_rx_sync[i])
self.sync.mipi += If(prev_sync, dphy_header[(8*i):(8*(i+1))].eq(self.dphy.hs_rx_data[(8*i):(8*(i+1))]))
self.submodules.dphy_header = GPIOIn(pads=dphy_header)
self.add_csr("dphy_header")
wa = WordAligner(lane_width=8, num_lanes=4, depth=3)
swapped_data = Cat(self.dphy.hs_rx_data[24:32], self.dphy.hs_rx_data[8:16], self.dphy.hs_rx_data[16:24], self.dphy.hs_rx_data[0:8])
self.sync.mipi += [
wa.data_in.eq(swapped_data),
wa.sync_in.eq(self.dphy.hs_rx_sync)
]
self.submodules.wa = wa
packet_cap = PacketCapture(data=wa.data_out, data_sync=wa.sync_out, depth=128)
self.submodules.packet_cap = packet_cap
packet_io = wishbone.SRAM(self.packet_cap.mem, read_only=True)
self.submodules.packet_io = packet_io
self.register_mem("packet_io", 0xb0000000, packet_io.bus, size=0x4000)
image_cap = ImageCapture(data=wa.data_out, data_sync=wa.sync_out, subsample_x=10, subsample_y=32, out_width=60, out_height=33)
self.submodules.image_cap = image_cap
image_io = wishbone.SRAM(self.image_cap.mem, read_only=True)
self.submodules.image_io = image_io
self.register_mem("image_io", 0xb0010000, image_io.bus, size=0x4000)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain: radiant (default) or prjoxide")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1")
parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash")
builder_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
hyperram = args.with_hyperram,
toolchain = args.toolchain,
cpu_type = "picorv32",
cpu_variant = "minimal",
integrated_rom_size = 32768,
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.wishbone.SRAM",
"litex.build.lattice.oxide.oxide_args",
"litex.soc.cores.ram.NXLRAM",
"litex.soc.cores.freqmeter.FreqMeter",
"litex.soc.cores.gpio.GPIOIn",
"litex.build.lattice.oxide.oxide_argdict"
] | [((7015, 7089), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Crosslink-NX VIP Board"""'}), "(description='LiteX SoC on Crosslink-NX VIP Board')\n", (7038, 7089), False, 'import argparse\n'), ((7766, 7784), 'litex.build.lattice.oxide.oxide_args', 'oxide_args', (['parser'], {}), '(parser)\n', (7776, 7784), False, 'from litex.build.lattice.oxide import oxide_args, oxide_argdict\n'), ((2100, 2143), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_por', '(~rst_n)'], {}), '(self.cd_por, ~rst_n)\n', (2122, 2143), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2169, 2235), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '((por_counter != 0) | self.rst)'], {}), '(self.cd_sys, (por_counter != 0) | self.rst)\n', (2191, 2235), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2669, 2715), 'litex_boards.platforms.crosslink_nx_vip.Platform', 'crosslink_nx_vip.Platform', ([], {'toolchain': 'toolchain'}), '(toolchain=toolchain)\n', (2694, 2715), False, 'from litex_boards.platforms import crosslink_nx_vip\n'), ((3535, 3551), 'litex.soc.cores.ram.NXLRAM', 'NXLRAM', (['(32)', 'size'], {}), '(32, size)\n', (3541, 3551), False, 'from litex.soc.cores.ram import NXLRAM\n'), ((3841, 3858), 'litehyperbus.core.hyperbus.HyperRAM', 'HyperRAM', (['hr_pads'], {}), '(hr_pads)\n', (3849, 3858), False, 'from litehyperbus.core.hyperbus import HyperRAM\n'), ((5025, 5079), 'litex.soc.cores.freqmeter.FreqMeter', 'FreqMeter', ([], {'period': 'sys_clk_freq', 'clk': 'self.dphy.clk_byte'}), '(period=sys_clk_freq, clk=self.dphy.clk_byte)\n', (5034, 5079), False, 'from litex.soc.cores.freqmeter import FreqMeter\n'), ((5155, 5188), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', ([], {'pads': 'self.dphy.hs_rx_data'}), '(pads=self.dphy.hs_rx_data)\n', (5161, 5188), False, 'from litex.soc.cores.gpio import GPIOIn\n'), ((5261, 5294), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', ([], {'pads': 'self.dphy.hs_rx_sync'}), '(pads=self.dphy.hs_rx_sync)\n', (5267, 5294), False, 'from litex.soc.cores.gpio import GPIOIn\n'), ((5761, 5785), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', ([], {'pads': 'dphy_header'}), '(pads=dphy_header)\n', (5767, 5785), False, 'from litex.soc.cores.gpio import GPIOIn\n'), ((6339, 6389), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['self.packet_cap.mem'], {'read_only': '(True)'}), '(self.packet_cap.mem, read_only=True)\n', (6352, 6389), False, 'from litex.soc.interconnect import wishbone\n'), ((6716, 6765), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['self.image_cap.mem'], {'read_only': '(True)'}), '(self.image_cap.mem, read_only=True)\n', (6729, 6765), False, 'from litex.soc.interconnect import wishbone\n'), ((8156, 8175), 'litex.build.lattice.oxide.oxide_argdict', 'oxide_argdict', (['args'], {}), '(args)\n', (8169, 8175), False, 'from litex.build.lattice.oxide import oxide_args, oxide_argdict\n'), ((8375, 8434), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (8387, 8434), False, 'import os\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2016-2017 <NAME> <<EMAIL>>
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
IBM's 8b/10b Encoding
This scheme is used by a large number of protocols including Display Port, PCI
Express, Gigabit Ethernet, SATA and USB 3.
The encoding is built by combining an 5b/6b and 3b/4b encoding schemes and
guarantees both DC balance and enough bit transitions to recover the clock
signal.
Note: This encoding is *not* used by DVI/HDMI (that uses a *different* 8b/10b
scheme called TMDS).
"""
from functools import reduce
from operator import add
from migen import *
from litex.soc.interconnect import stream
# Helpers ------------------------------------------------------------------------------------------
def K(x, y):
return (y << 5) | x
def disparity(word, nbits):
n0 = 0
n1 = 0
for i in range(nbits):
if word & (1 << i):
n1 += 1
else:
n0 += 1
return n1 - n0
def reverse_table_flip(inputs, flips, nbits):
outputs = [None]*2**nbits
for i, (word, flip) in enumerate(zip(inputs, flips)):
if outputs[word] is not None:
raise ValueError
outputs[word] = i
if flip:
word_n = ~word & (2**nbits-1)
if outputs[word_n] is not None:
raise ValueError
outputs[word_n] = i
for i in range(len(outputs)):
if outputs[i] is None:
outputs[i] = 0
return outputs
def reverse_table(inputs, nbits):
outputs = [None]*2**nbits
for i, word in enumerate(inputs):
if outputs[word] is not None:
raise ValueError
outputs[word] = i
for i in range(len(outputs)):
if outputs[i] is None:
outputs[i] = 0
return outputs
# 5b6b ---------------------------------------------------------------------------------------------
table_5b6b = [
0b011000,
0b100010,
0b010010,
0b110001,
0b001010,
0b101001,
0b011001,
0b000111,
0b000110,
0b100101,
0b010101,
0b110100,
0b001101,
0b101100,
0b011100,
0b101000,
0b100100,
0b100011,
0b010011,
0b110010,
0b001011,
0b101010,
0b011010,
0b000101,
0b001100,
0b100110,
0b010110,
0b001001,
0b001110,
0b010001,
0b100001,
0b010100,
]
table_5b6b_unbalanced = [bool(disparity(c, 6)) for c in table_5b6b]
table_5b6b_flip = list(table_5b6b_unbalanced)
table_5b6b_flip[7] = True
table_6b5b = reverse_table_flip(table_5b6b, table_5b6b_flip, 6)
table_6b5b[0b001111] = 0b11100 # K.28
table_6b5b[0b110000] = 0b11100 # K.28
# 3b4b ---------------------------------------------------------------------------------------------
table_3b4b = [
0b0100,
0b1001,
0b0101,
0b0011,
0b0010,
0b1010,
0b0110,
0b0001, # Primary D.x.7
]
table_3b4b_unbalanced = [bool(disparity(c, 4)) for c in table_3b4b]
table_3b4b_flip = list(table_3b4b_unbalanced)
table_3b4b_flip[3] = True
table_4b3b = reverse_table_flip(table_3b4b, table_3b4b_flip, 4)
# Alternative D.x.7
table_4b3b[0b0111] = 0b0111
table_4b3b[0b1000] = 0b0111
table_4b3b_kn = reverse_table(table_3b4b, 4)
table_4b3b_kp = reverse_table([~x & 0b1111 for x in table_3b4b], 4)
# Primary D.x.7 is not used
table_4b3b_kn[0b0001] = 0b000
table_4b3b_kn[0b1000] = 0b111
table_4b3b_kp[0b1110] = 0b000
table_4b3b_kp[0b0111] = 0b111
# Single Encoder -----------------------------------------------------------------------------------
@CEInserter()
class SingleEncoder(Module):
def __init__(self, lsb_first=False):
self.d = Signal(8)
self.k = Signal()
self.disp_in = Signal()
self.output = Signal(10)
self.disp_out = Signal()
# # #
# Stage 1: 5b/6b and 3b/4b encoding.
code5b = self.d[:5]
code6b = Signal(6, reset_less=True)
code6b_unbalanced = Signal(reset_less=True)
code6b_flip = Signal()
self.sync += [
If(self.k & (code5b == 28),
code6b.eq(0b110000),
code6b_unbalanced.eq(1),
code6b_flip.eq(1)
).Else(
code6b.eq(Array(table_5b6b)[code5b]),
code6b_unbalanced.eq(Array(table_5b6b_unbalanced)[code5b]),
code6b_flip.eq(Array(table_5b6b_flip)[code5b])
)
]
code3b = self.d[5:]
code4b = Signal(4, reset_less=True)
code4b_unbalanced = Signal(reset_less=True)
code4b_flip = Signal()
self.sync += [
code4b.eq(Array(table_3b4b)[code3b]),
code4b_unbalanced.eq(Array(table_3b4b_unbalanced)[code3b]),
If(self.k,
code4b_flip.eq(1)
).Else(
code4b_flip.eq(Array(table_3b4b_flip)[code3b])
)
]
alt7_rd0 = Signal(reset_less=True) # If disparity is -1, use alternative D.x.7.
alt7_rd1 = Signal(reset_less=True) # If disparity is +1, use alternative D.x.7.
self.sync += [
alt7_rd0.eq(0),
alt7_rd1.eq(0),
If(code3b == 7,
If((code5b == 17) | (code5b == 18) | (code5b == 20),
alt7_rd0.eq(1)),
If((code5b == 11) | (code5b == 13) | (code5b == 14),
alt7_rd1.eq(1)),
If(self.k,
alt7_rd0.eq(1),
alt7_rd1.eq(1)
)
)
]
# Stage 2 (combinatorial): disparity control.
output_6b = Signal(6)
disp_inter = Signal()
self.comb += [
disp_inter.eq(self.disp_in ^ code6b_unbalanced),
If(~self.disp_in & code6b_flip,
output_6b.eq(~code6b)
).Else(
output_6b.eq(code6b)
)
]
output_4b = Signal(4)
self.comb += [
If(~disp_inter & alt7_rd0,
self.disp_out.eq(~disp_inter),
output_4b.eq(0b0111)
).Elif(disp_inter & alt7_rd1,
self.disp_out.eq(~disp_inter),
output_4b.eq(0b1000)
).Else(
self.disp_out.eq(disp_inter ^ code4b_unbalanced),
If(~disp_inter & code4b_flip,
output_4b.eq(~code4b)
).Else(
output_4b.eq(code4b)
)
)
]
output_msb_first = Signal(10)
self.comb += output_msb_first.eq(Cat(output_4b, output_6b))
if lsb_first:
for i in range(10):
self.comb += self.output[i].eq(output_msb_first[9-i])
else:
self.comb += self.output.eq(output_msb_first)
# Encoder ------------------------------------------------------------------------------------------
class Encoder(Module):
def __init__(self, nwords=1, lsb_first=False):
self.ce = Signal(reset=1)
self.d = [Signal(8) for _ in range(nwords)]
self.k = [Signal() for _ in range(nwords)]
self.output = [Signal(10, reset_less=True) for _ in range(nwords)]
self.disparity = [Signal() for _ in range(nwords)]
# # #
encoders = [SingleEncoder(lsb_first) for _ in range(nwords)]
self.comb += [encoder.ce.eq(self.ce) for encoder in encoders]
self.submodules += encoders
self.sync += If(self.ce, encoders[0].disp_in.eq(encoders[-1].disp_out))
for e1, e2 in zip(encoders, encoders[1:]):
self.comb += e2.disp_in.eq(e1.disp_out)
for d, k, output, disparity, encoder in zip(self.d, self.k, self.output, self.disparity, encoders):
self.comb += [
encoder.d.eq(d),
encoder.k.eq(k)
]
output.reset_less = True
self.sync += If(self.ce,
output.eq(encoder.output),
disparity.eq(encoder.disp_out)
)
# Decoder ------------------------------------------------------------------------------------------
class Decoder(Module):
def __init__(self, lsb_first=False):
self.ce = Signal(reset=1)
self.input = Signal(10)
self.d = Signal(8)
self.k = Signal()
self.invalid = Signal()
# # #
input_msb_first = Signal(10)
if lsb_first:
for i in range(10):
self.comb += input_msb_first[i].eq(self.input[9-i])
else:
self.comb += input_msb_first.eq(self.input)
code6b = input_msb_first[4:]
code5b = Signal(5)
code4b = input_msb_first[:4]
code3b = Signal(3, reset_less=True)
mem_6b5b = Memory(5, len(table_6b5b), init=table_6b5b)
port_6b5b = mem_6b5b.get_port(has_re=True)
self.specials += mem_6b5b, port_6b5b
self.comb += port_6b5b.adr.eq(code6b)
self.comb += port_6b5b.re.eq(self.ce)
self.sync += If(self.ce,
self.k.eq(0),
If(code6b == 0b001111,
self.k.eq(1),
code3b.eq(Array(table_4b3b_kn)[code4b])
).Elif(code6b == 0b110000,
self.k.eq(1),
code3b.eq(Array(table_4b3b_kp)[code4b])
).Else(
If((code4b == 0b0111) | (code4b == 0b1000), # D.x.A7/K.x.7
If((code6b != 0b100011) &
(code6b != 0b010011) &
(code6b != 0b001011) &
(code6b != 0b110100) &
(code6b != 0b101100) &
(code6b != 0b011100), self.k.eq(1))
),
code3b.eq(Array(table_4b3b)[code4b])
),
)
self.comb += code5b.eq(port_6b5b.dat_r)
self.comb += self.d.eq(Cat(code5b, code3b))
# Basic invalid symbols detection: check that we have 4,5 or 6 ones in the symbol. This does
# not report all invalid symbols but still allow detecting issues with the link.
ones = Signal(4, reset_less=True)
self.sync += If(self.ce, ones.eq(reduce(add, [self.input[i] for i in range(10)])))
self.comb += self.invalid.eq((ones != 4) & (ones != 5) & (ones != 6))
# Stream Encoder -----------------------------------------------------------------------------------
class StreamEncoder(stream.PipelinedActor):
def __init__(self, nwords=1):
self.sink = sink = stream.Endpoint([("d", nwords*8), ("k", nwords)])
self.source = source = stream.Endpoint([("data", nwords*10)])
stream.PipelinedActor.__init__(self, latency=2)
# # #
# Encoders
encoder = Encoder(nwords, True)
self.submodules += encoder
# Control
self.comb += encoder.ce.eq(self.pipe_ce)
# Datapath
for i in range(nwords):
self.comb += [
encoder.k[i].eq(sink.k[i]),
encoder.d[i].eq(sink.d[8*i:8*(i+1)]),
source.data[10*i:10*(i+1)].eq(encoder.output[i])
]
# Stream Encoder -----------------------------------------------------------------------------------
class StreamDecoder(stream.PipelinedActor):
def __init__(self, nwords=1):
self.sink = sink = stream.Endpoint([("data", nwords*10)])
self.source = source = stream.Endpoint([("d", nwords*8), ("k", nwords)])
stream.PipelinedActor.__init__(self, latency=1)
# # #
# Decoders
decoders = [Decoder(True) for _ in range(nwords)]
self.submodules += decoders
# Control
self.comb += [decoders[i].ce.eq(self.pipe_ce) for i in range(nwords)]
# Datapath
for i in range(nwords):
self.comb += [
decoders[i].input.eq(sink.data[10*i:10*(i+1)]),
source.k[i].eq(decoders[i].k),
source.d[8*i:8*(i+1)].eq(decoders[i].d)
] | [
"litex.soc.interconnect.stream.PipelinedActor.__init__",
"litex.soc.interconnect.stream.Endpoint"
] | [((10573, 10624), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('d', nwords * 8), ('k', nwords)]"], {}), "([('d', nwords * 8), ('k', nwords)])\n", (10588, 10624), False, 'from litex.soc.interconnect import stream\n'), ((10654, 10694), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', nwords * 10)]"], {}), "([('data', nwords * 10)])\n", (10669, 10694), False, 'from litex.soc.interconnect import stream\n'), ((10701, 10748), 'litex.soc.interconnect.stream.PipelinedActor.__init__', 'stream.PipelinedActor.__init__', (['self'], {'latency': '(2)'}), '(self, latency=2)\n', (10731, 10748), False, 'from litex.soc.interconnect import stream\n'), ((11395, 11435), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', nwords * 10)]"], {}), "([('data', nwords * 10)])\n", (11410, 11435), False, 'from litex.soc.interconnect import stream\n'), ((11465, 11516), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('d', nwords * 8), ('k', nwords)]"], {}), "([('d', nwords * 8), ('k', nwords)])\n", (11480, 11516), False, 'from litex.soc.interconnect import stream\n'), ((11523, 11570), 'litex.soc.interconnect.stream.PipelinedActor.__init__', 'stream.PipelinedActor.__init__', (['self'], {'latency': '(1)'}), '(self, latency=1)\n', (11553, 11570), False, 'from litex.soc.interconnect import stream\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.csr import CSRStorage, AutoCSR
from litedram.common import Settings, tXXDController
from litedram.phy.utils import Serializer, Deserializer, edge
# PHY ----------------------------------------------------------------------------------------------
class SimSerDesMixin:
"""Helper class for easier (de-)serialization to simulation pads."""
def ser(self, *, i, o, clkdiv, clk, name="", **kwargs):
assert len(o) == 1
kwargs = dict(i=i, i_dw=len(i), o=o, o_dw=1, clk=clk, clkdiv=clkdiv,
name=f"ser_{name}".strip("_"), **kwargs)
self.submodules += Serializer(**kwargs)
def des(self, *, i, o, clkdiv, clk, name="", **kwargs):
assert len(i) == 1
kwargs = dict(i=i, i_dw=1, o=o, o_dw=len(o), clk=clk, clkdiv=clkdiv,
name=f"des_{name}".strip("_"), **kwargs)
self.submodules += Deserializer(**kwargs)
# Platform -----------------------------------------------------------------------------------------
class SimPad(Settings):
def __init__(self, name, width, io=False):
self.set_attributes(locals())
class SimulationPads(Module):
"""Pads for simulation purpose
Tristate pads are simulated as separate input/output pins (name_i, name_o) and
an output-enable pin (name_oe). Output pins are to be driven byt the PHY and
input pins are to be driven by the DRAM simulator. An additional pin without
a suffix is created and this module will include logic to set this pin to the
actual value depending on the output-enable signal.
"""
def layout(self, **kwargs):
raise NotImplementedError("Simulation pads layout as a list of SimPad objects")
def __init__(self, **kwargs):
for pad in self.layout(**kwargs):
if pad.io:
o, i, oe = (f"{pad.name}_{suffix}" for suffix in ["o", "i", "oe"])
setattr(self, pad.name, Signal(pad.width))
setattr(self, o, Signal(pad.width, name=o))
setattr(self, i, Signal(pad.width, name=i))
setattr(self, oe, Signal(name=oe))
self.comb += If(getattr(self, oe),
getattr(self, pad.name).eq(getattr(self, o))
).Else(
getattr(self, pad.name).eq(getattr(self, i))
)
else:
setattr(self, pad.name, Signal(pad.width, name=pad.name))
class Clocks(dict):
"""Helper for definiting simulation clocks
Dictionary format is `{name: {"freq_hz": _, "phase_deg": _}, ...}`.
"""
def names(self):
return list(self.keys())
def add_io(self, io):
for name in self.names():
io.append((name + "_clk", 0, Pins(1)))
def add_clockers(self, sim_config):
for name, desc in self.items():
sim_config.add_clocker(name + "_clk", **desc)
class CRG(Module):
"""Clock & Reset Generator for Verilator-based simulation"""
def __init__(self, platform, clock_domains=None):
if clock_domains is None:
clock_domains = ["sys"]
elif isinstance(clock_domains, Clocks):
clock_domains = list(clock_domains.names())
# request() before creating clock_domains to avoid signal renaming problem
clock_domains = {name: platform.request(name + "_clk") for name in clock_domains}
self.clock_domains.cd_por = ClockDomain(reset_less=True)
for name in clock_domains.keys():
setattr(self.clock_domains, "cd_" + name, ClockDomain(name=name))
int_rst = Signal(reset=1)
self.sync.por += int_rst.eq(0)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
for name, clk in clock_domains.items():
cd = getattr(self, "cd_" + name)
self.comb += cd.clk.eq(clk)
self.comb += cd.rst.eq(int_rst)
class Platform(SimPlatform):
def __init__(self, io, clocks: Clocks):
common_io = [
("sys_rst", 0, Pins(1)),
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
]
clocks.add_io(common_io)
SimPlatform.__init__(self, "SIM", common_io + io)
# Logging ------------------------------------------------------------------------------------------
class SimLogger(Module, AutoCSR):
"""Logger for use in simulation
This module allows for easier message logging when running simulation designs.
The logger can be used from `comb` context so it the methods can be directly
used inside `FSM` code. It also provides logging levels that can be used to
filter messages, either by specifying the default `log_level` or in runtime
by driving to the `level` signal or using a corresponding CSR.
"""
# Allows to use Display inside FSM and to filter log messages by level (statically or dynamically)
DEBUG = 0
INFO = 1
WARN = 2
ERROR = 3
NONE = 4
def __init__(self, log_level=INFO, clk_freq=None):
self.ops = []
self.level = Signal(reset=log_level, max=self.NONE)
self.time_ps = None
if clk_freq is not None:
self.time_ps = Signal(64)
cnt = Signal(64)
self.sync += cnt.eq(cnt + 1)
self.comb += self.time_ps.eq(cnt * int(1e12/clk_freq))
def debug(self, fmt, *args, **kwargs):
return self.log("[DEBUG] " + fmt, *args, level=self.DEBUG, **kwargs)
def info(self, fmt, *args, **kwargs):
return self.log("[INFO] " + fmt, *args, level=self.INFO, **kwargs)
def warn(self, fmt, *args, **kwargs):
return self.log("[WARN] " + fmt, *args, level=self.WARN, **kwargs)
def error(self, fmt, *args, **kwargs):
return self.log("[ERROR] " + fmt, *args, level=self.ERROR, **kwargs)
def log(self, fmt, *args, level=DEBUG, once=True):
cond = Signal()
if once: # make the condition be triggered only on rising edge
condition = edge(self, cond)
else:
condition = cond
self.ops.append((level, condition, fmt, args))
return cond.eq(1)
def add_csrs(self):
self._level = CSRStorage(len(self.level), reset=self.level.reset.value)
self.comb += self.level.eq(self._level.storage)
def do_finalize(self):
for level, cond, fmt, args in self.ops:
if self.time_ps is not None:
fmt = f"[%16d ps] {fmt}"
args = (self.time_ps, *args)
self.sync += If((level >= self.level) & cond, Display(fmt, *args))
def log_level_getter(log_level):
"""Parse logging level description
Log level can be presented in a simple form (e.g. `--log-level=DEBUG`) to specify
the same level for all modules, or can set different levels for different modules
e.g. `--log-level=all=INFO,data=DEBUG`.
"""
def get_level(name):
return getattr(SimLogger, name.upper())
if "=" not in log_level: # simple log_level, e.g. "INFO"
return lambda _: get_level(log_level)
# parse log_level in the per-module form, e.g. "--log-level=all=INFO,data=DEBUG"
per_module = dict(part.split("=") for part in log_level.strip().split(","))
return lambda module: get_level(per_module.get(module, per_module.get("all", None)))
# Simulator ----------------------------------------------------------------------------------------
class PulseTiming(Module):
"""Timing monitor with pulse input/output
This module works like `tXXDController` with the following differences:
* countdown triggered by a low to high pulse on `trigger`
* `ready` is initially low, only after a trigger it can become high
* provides `ready_p` which is high only for 1 cycle when `ready` becomes high
"""
def __init__(self, t):
self.trigger = Signal()
self.ready = Signal()
self.ready_p = Signal()
ready_d = Signal()
triggered = Signal()
tctrl = tXXDController(t)
self.submodules += tctrl
self.sync += If(self.trigger, triggered.eq(1)),
self.comb += [
self.ready.eq(triggered & tctrl.ready),
self.ready_p.eq(edge(self, self.ready)),
tctrl.valid.eq(edge(self, self.trigger)),
]
| [
"litex.build.sim.SimPlatform.__init__",
"litex.build.generic_platform.Pins"
] | [((908, 928), 'litedram.phy.utils.Serializer', 'Serializer', ([], {}), '(**kwargs)\n', (918, 928), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((1174, 1196), 'litedram.phy.utils.Deserializer', 'Deserializer', ([], {}), '(**kwargs)\n', (1186, 1196), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((4694, 4743), 'litex.build.sim.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""SIM"""', '(common_io + io)'], {}), "(self, 'SIM', common_io + io)\n", (4714, 4743), False, 'from litex.build.sim import SimPlatform\n'), ((8512, 8529), 'litedram.common.tXXDController', 'tXXDController', (['t'], {}), '(t)\n', (8526, 8529), False, 'from litedram.common import Settings, tXXDController\n'), ((6518, 6534), 'litedram.phy.utils.edge', 'edge', (['self', 'cond'], {}), '(self, cond)\n', (6522, 6534), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((4279, 4286), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (4283, 4286), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((8723, 8745), 'litedram.phy.utils.edge', 'edge', (['self', 'self.ready'], {}), '(self, self.ready)\n', (8727, 8745), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((8775, 8799), 'litedram.phy.utils.edge', 'edge', (['self', 'self.trigger'], {}), '(self, self.trigger)\n', (8779, 8799), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((3023, 3030), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (3027, 3030), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((4358, 4365), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (4362, 4365), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((4410, 4417), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (4414, 4417), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((4462, 4469), 'litex.build.generic_platform.Pins', 'Pins', (['(8)'], {}), '(8)\n', (4466, 4469), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((4514, 4521), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (4518, 4521), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((4566, 4573), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (4570, 4573), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((4618, 4625), 'litex.build.generic_platform.Pins', 'Pins', (['(8)'], {}), '(8)\n', (4622, 4625), False, 'from litex.build.generic_platform import Pins, Subsignal\n')] |
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")),
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
# GND on JP1 Pin 12.
Subsignal("tx", Pins("B5"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("B4"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"P2 N5 N6 M8 P8 T7 N8 T6",
"R1 P1 N2 N1 L4")),
Subsignal("ba", Pins("M7 M6")),
Subsignal("cs_n", Pins("P6")),
Subsignal("cke", Pins("L7")),
Subsignal("ras_n", Pins("L2")),
Subsignal("cas_n", Pins("L1")),
Subsignal("we_n", Pins("C2")),
Subsignal("dq", Pins(
"G2 G1 L8 K5 K2 J2 J1 R7",
"T4 T2 T3 R3 R5 P3 N3 K1")),
Subsignal("dm", Pins("R6 T5")),
IOStandard("3.3-V LVTTL")
),
("epcs", 0,
Subsignal("data0", Pins("H2")),
Subsignal("dclk", Pins("H1")),
Subsignal("ncs0", Pins("D2")),
Subsignal("asd0", Pins("C1")),
IOStandard("3.3-V LVTTL")
),
("i2c", 0,
Subsignal("sclk", Pins("F2")),
Subsignal("sdat", Pins("F1")),
IOStandard("3.3-V LVTTL")
),
("g_sensor", 0,
Subsignal("cs_n", Pins("G5")),
Subsignal("int", Pins("M2")),
IOStandard("3.3-V LVTTL")
),
("adc", 0,
Subsignal("cs_n", Pins("A10")),
Subsignal("saddr", Pins("B10")),
Subsignal("sclk", Pins("B14")),
Subsignal("sdat", Pins("A9")),
IOStandard("3.3-V LVTTL")
),
("gpio_0", 0, Pins(
"D3 C3 A2 A3 B3 B4 A4 B5",
"A5 D5 B6 A6 B7 D6 A7 C6",
"C8 E6 E7 D8 E8 F8 F9 E9",
"C9 D9 E11 E10 C11 B11 A12 D11",
"D12 B12"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0, Pins(
"F13 T15 T14 T13 R13 T12 R12 T11",
"T10 R11 P11 R10 N12 P9 N9 N11",
"L16 K16 R16 L15 P15 P16 R14 N16",
"N15 P14 L14 N14 M10 L13 J16 K15",
"J13 J14"),
IOStandard("3.3-V LVTTL")
),
("gpio_2", 0, Pins(
"A14 B16 C14 C16 C15 D16 D15 D14",
"F15 F16 F14 G16 G15"),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
| [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((3739, 3789), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE22F17C6"""', '_io'], {}), "(self, 'EP4CE22F17C6', _io)\n", (3762, 3789), False, 'from litex.build.altera import AlteraPlatform\n'), ((3839, 3851), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (3849, 3851), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((3898, 3940), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3924, 3940), False, 'from litex.build.altera import AlteraPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
# Button
("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
Subsignal("tx", Pins("AA13"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("AA14"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
# SDR SDRAM
("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"V2 V1 U2 U1 V3 V4 Y2 AA1",
"Y3 V5 W1 Y4 V6")),
Subsignal("ba", Pins("Y1 W2")),
Subsignal("cs_n", Pins("AA3")),
Subsignal("cke", Pins("W6")),
Subsignal("ras_n", Pins("AB3")),
Subsignal("cas_n", Pins("AA4")),
Subsignal("we_n", Pins("AB4")),
Subsignal("dq", Pins(
"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
Subsignal("dm", Pins("AA5 W7")),
IOStandard("3.3-V LVTTL")
),
# GPIOs
#ignore for now
#("gpio_0", 0, Pins(
# "D3 C3 A2 A3 B3 B4 A4 B5",
# "A5 D5 B6 A6 B7 D6 A7 C6",
# "C8 E6 E7 D8 E8 F8 F9 E9",
# "C9 D9 E11 E10 C11 B11 A12 D11",
# "D12 B12"),
# IOStandard("3.3-V LVTTL")
#),
#("gpio_1", 0, Pins(
# "F13 T15 T14 T13 R13 T12 R12 T11",
# "T10 R11 P11 R10 N12 P9 N9 N11",
# "L16 K16 R16 L15 P15 P16 R14 N16",
# "N15 P14 L14 N14 M10 L13 J16 K15",
# "J13 J14"),
# IOStandard("3.3-V LVTTL")
#),
#("gpio_2", 0, Pins(
# "A14 B16 C14 C16 C15 D16 D15 D14",
# "F15 F16 F14 G16 G15"),
# IOStandard("3.3-V LVTTL")
#),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE15F23C8", _io)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
| [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((2536, 2586), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE15F23C8"""', '_io'], {}), "(self, 'EP4CE15F23C8', _io)\n", (2559, 2586), False, 'from litex.build.altera import AlteraPlatform\n'), ((2636, 2648), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (2646, 2648), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((2695, 2737), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2721, 2737), False, 'from litex.build.altera import AlteraPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
# Button
("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
# SPIFlash (W25Q64)
("spiflash", 0,
# clk
Subsignal("cs_n", Pins("E2")),
Subsignal("clk", Pins("K2")),
Subsignal("mosi", Pins("D1")),
Subsignal("miso", Pins("E2")),
IOStandard("3.3-V LVTTL"),
),
# SDR SDRAM
("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"V2 V1 U2 U1 V3 V4 Y2 AA1",
"Y3 V5 W1 Y4 V6")),
Subsignal("ba", Pins("Y1 W2")),
Subsignal("cs_n", Pins("AA3")),
Subsignal("cke", Pins("W6")),
Subsignal("ras_n", Pins("AB3")),
Subsignal("cas_n", Pins("AA4")),
Subsignal("we_n", Pins("AB4")),
Subsignal("dq", Pins(
"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
Subsignal("dm", Pins("AA5 W7")),
IOStandard("3.3-V LVTTL")
),
]
# The connectors are named after the daughterboard, not the core board
# because on the different core boards the names vary, but on the
# daughterboard they stay the same, which we need to connect the
# daughterboard peripherals to the core board.
# On this board J2 is U7 and J3 is U8
_connectors = [
("J2", {
# odd row even row
7: "R1", 8: "R2",
9: "P1", 10: "P2",
11: "N1", 12: "N2",
13: "M1", 14: "M2",
15: "J1", 16: "J2",
17: "H1", 18: "H2",
19: "F1", 20: "F2",
21: "E1", 22: "D2",
23: "C1", 24: "C2",
25: "B1", 26: "B2",
27: "B3", 28: "A3",
29: "B4", 30: "A4",
31: "C4", 32: "C3",
33: "B5", 34: "A5",
35: "B6", 36: "A6",
37: "B7", 38: "A7",
39: "B8", 40: "A8",
41: "B9", 42: "A9",
43: "B10", 44: "A10",
45: "B13", 46: "A13",
47: "B14", 48: "A14",
49: "B15", 50: "A15",
51: "B16", 52: "A16",
53: "B17", 54: "A17",
55: "B18", 56: "A18",
57: "B19", 58: "A19",
59: "B20", 60: "A20",
}),
("J3", {
# odd row even row
7: "AA13", 8: "AB13",
9: "AA14", 10: "AB14",
11: "AA15", 12: "AB15",
13: "AA16", 14: "AB16",
15: "AA17", 16: "AB17",
17: "AA18", 18: "AB18",
19: "AA19", 20: "AB19",
21: "AA20", 22: "AB20",
23: "Y22", 24: "Y21",
25: "W22", 26: "W21",
27: "V22", 28: "V21",
29: "U22", 30: "U21",
31: "R22", 32: "R21",
33: "P22", 34: "P21",
35: "N22", 36: "N21",
37: "M22", 38: "M21",
39: "L22", 40: "L21",
41: "K22", 42: "K21",
43: "J22", 44: "J21",
45: "H22", 46: "H21",
47: "F22", 48: "F21",
49: "E22", 50: "E21",
51: "D22", 52: "D21",
53: "C22", 54: "C21",
55: "B22", 56: "B21",
57: "N20", 58: "N19",
59: "M20", 60: "M19",
})
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
core_resources = [
("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
),
]
def __init__(self, variant="ep4ce15", toolchain="quartus", with_daughterboard=False):
device = {
"ep4ce15": "EP4CE15F23C8",
"ep4ce55": "EP4CE55F23C8"
}[variant]
io = _io
connectors = _connectors
if with_daughterboard:
from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
io += daughterboard.io
connectors += daughterboard.connectors
else:
io += self.core_resources
AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
if with_daughterboard:
# an ethernet pin takes K22, so make it available
self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
| [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((4685, 4759), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', 'device', 'io', 'connectors'], {'toolchain': 'toolchain'}), '(self, device, io, connectors, toolchain=toolchain)\n', (4708, 4759), False, 'from litex.build.altera import AlteraPlatform\n'), ((5037, 5049), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (5047, 5049), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((5096, 5138), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (5122, 5138), False, 'from litex.build.altera import AlteraPlatform\n')] |
from migen import Module, Signal, Instance, ClockDomain, If
from litex.build.lattice.platform import LatticePlatform
from litex.soc.cores import up5kspram, spi_flash
from litex_boards.targets.fomu import _CRG
import litex.soc.doc as lxsocdoc
import spibone
from ..romgen import RandomFirmwareROM, FirmwareROM
from ..fomutouch import TouchPads
from ..sbwarmboot import SBWarmBoot
from rtl.sbled import SBLED
import argparse
import os
def add_platform_args(parser):
parser.add_argument(
"--revision", choices=["evt", "dvt", "pvt", "hacker"], required=True,
help="build foboot for a particular hardware revision"
)
class Platform(LatticePlatform):
def __init__(self, revision=None, toolchain="icestorm"):
self.revision = revision
self.hw_platform = "fomu"
if revision == "evt":
from litex_boards.platforms.fomu_evt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm")
self.spi_size = 16 * 1024 * 1024
self.spi_dummy = 6
elif revision == "dvt":
from litex_boards.platforms.fomu_pvt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 6
elif revision == "pvt":
from litex_boards.platforms.fomu_pvt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 6
elif revision == "hacker":
from litex_boards.platforms.fomu_hacker import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 4
else:
raise ValueError("Unrecognized revision: {}. Known values: evt, dvt, pvt, hacker".format(revision))
self.warmboot_offsets = [
160,
160,
157696,
262144,
262144 + 32768,
]
def get_config(self, git_version):
return [
("USB_VENDOR_ID", 0x1209), # pid.codes
("USB_PRODUCT_ID", 0x5bf0), # Assigned to Fomu project
("USB_DEVICE_VER", 0x0101), # Bootloader version
("USB_MANUFACTURER_NAME", "Foosn"),
] + {
"evt": [("USB_PRODUCT_NAME", "Fomu EVT running DFU Bootloader {}".format(git_version))],
"dvt": [("USB_PRODUCT_NAME", "Fomu DVT running DFU Bootloader {}".format(git_version))],
"pvt": [("USB_PRODUCT_NAME", "Fomu PVT running DFU Bootloader {}".format(git_version))],
"hacker":[("USB_PRODUCT_NAME", "Fomu Hacker running DFU Bootloader {}".format(git_version))],
}[self.revision]
def add_crg(self, soc):
soc.submodules.crg = _CRG(self)
def add_cpu_variant(self, soc, debug=False):
if debug:
soc.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
else:
soc.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
def add_sram(self, soc):
spram_size = 128*1024
soc.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
return spram_size
def add_reboot(self, soc):
soc.submodules.reboot = SBWarmBoot(soc, self.warmboot_offsets)
def add_touch(self, soc):
self.add_extension(TouchPads.touch_device)
soc.submodules.touch = TouchPads(self.request("touch_pads"))
def add_rgb(self, soc):
soc.submodules.rgb = SBLED(self.revision, self.request("rgb_led"))
def create_programmer(self):
raise ValueError("programming is not supported")
def build_templates(self, use_dsp, pnr_seed, placer):
# Override default LiteX's yosys/build templates
assert hasattr(self.toolchain, "yosys_template")
assert hasattr(self.toolchain, "build_template")
self.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
self.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
self.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
self.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
self.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
self.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
self.toolchain.build_template[1] += " --placer {}".format(placer)
def finialise(self, output_dir):
make_multiboot_header(os.path.join(output_dir, "gateware", "multiboot-header.bin"),
self.warmboot_offsets)
with open(os.path.join(output_dir, 'gateware', 'multiboot-header.bin'), 'rb') as multiboot_header_file:
multiboot_header = multiboot_header_file.read()
with open(os.path.join(output_dir, 'gateware', 'top.bin'), 'rb') as top_file:
top = top_file.read()
with open(os.path.join(output_dir, 'gateware', 'top-multiboot.bin'), 'wb') as top_multiboot_file:
top_multiboot_file.write(multiboot_header)
top_multiboot_file.write(top)
print(
"""Foboot build complete. Output files:
{}/gateware/top.bin Bitstream file. Load this onto the FPGA for testing.
{}/gateware/top-multiboot.bin Multiboot-enabled bitstream file. Flash this onto FPGA ROM.
{}/gateware/top.v Source Verilog file. Useful for debugging issues.
{}/software/include/generated/ Directory with header files for API access.
{}/software/bios/bios.elf ELF file for debugging bios.
""".format(output_dir, output_dir, output_dir, output_dir, output_dir))
def make_multiboot_header(filename, boot_offsets=[160]):
"""
ICE40 allows you to program the SB_WARMBOOT state machine by adding the following
values to the bitstream, before any given image:
[7e aa 99 7e] Sync Header
[92 00 k0] Boot mode (k = 1 for cold boot, 0 for warmboot)
[44 03 o1 o2 o3] Boot address
[82 00 00] Bank offset
[01 08] Reboot
[...] Padding (up to 32 bytes)
Note that in ICE40, the second nybble indicates the number of remaining bytes
(with the exception of the sync header).
The above construct is repeated five times:
INITIAL_BOOT The image loaded at first boot
BOOT_S00 The first image for SB_WARMBOOT
BOOT_S01 The second image for SB_WARMBOOT
BOOT_S10 The third image for SB_WARMBOOT
BOOT_S11 The fourth image for SB_WARMBOOT
"""
while len(boot_offsets) < 5:
boot_offsets.append(boot_offsets[0])
with open(filename, 'wb') as output:
for offset in boot_offsets:
# Sync Header
output.write(bytes([0x7e, 0xaa, 0x99, 0x7e]))
# Boot mode
output.write(bytes([0x92, 0x00, 0x00]))
# Boot address
output.write(bytes([0x44, 0x03,
(offset >> 16) & 0xff,
(offset >> 8) & 0xff,
(offset >> 0) & 0xff]))
# Bank offset
output.write(bytes([0x82, 0x00, 0x00]))
# Reboot command
output.write(bytes([0x01, 0x08]))
for x in range(17, 32):
output.write(bytes([0]))
| [
"litex.soc.cores.up5kspram.Up5kSPRAM",
"litex.build.lattice.platform.LatticePlatform.__init__"
] | [((3049, 3059), 'litex_boards.targets.fomu._CRG', '_CRG', (['self'], {}), '(self)\n', (3053, 3059), False, 'from litex_boards.targets.fomu import _CRG\n'), ((3371, 3407), 'litex.soc.cores.up5kspram.Up5kSPRAM', 'up5kspram.Up5kSPRAM', ([], {'size': 'spram_size'}), '(size=spram_size)\n', (3390, 3407), False, 'from litex.soc.cores import up5kspram, spi_flash\n'), ((923, 1016), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-sg48', _io, _connectors,\n toolchain='icestorm')\n", (947, 1016), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((5756, 5816), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""multiboot-header.bin"""'], {}), "(output_dir, 'gateware', 'multiboot-header.bin')\n", (5768, 5816), False, 'import os\n'), ((1206, 1300), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-uwg30"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-uwg30', _io, _connectors,\n toolchain='icestorm')\n", (1230, 1300), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((5892, 5952), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""multiboot-header.bin"""'], {}), "(output_dir, 'gateware', 'multiboot-header.bin')\n", (5904, 5952), False, 'import os\n'), ((1489, 1583), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-uwg30"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-uwg30', _io, _connectors,\n toolchain='icestorm')\n", (1513, 1583), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((6068, 6115), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""top.bin"""'], {}), "(output_dir, 'gateware', 'top.bin')\n", (6080, 6115), False, 'import os\n'), ((1778, 1872), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-uwg30"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-uwg30', _io, _connectors,\n toolchain='icestorm')\n", (1802, 1872), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((6200, 6257), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""top-multiboot.bin"""'], {}), "(output_dir, 'gateware', 'top-multiboot.bin')\n", (6212, 6257), False, 'import os\n')] |
# Support for the Digilent Atlys (http://digilentinc.com/atlys/) - The board used for HDMI2USB prototyping.
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, iMPACT
# There appear to be 4 x LTC2481C on the U1-SCL / U1-SDA lines connected to the Cypress
class DynamicLVCMOS(object):
"""Object to allow configuration of IOBs connected to dynamic voltage level.
This is used because VCCB2 supply for Bank 2 can be connected to either the
VCC2V5 or VCC3V3 rail depending on JP12, however there is no way to
autodetect this.
"""
def __init__(self, name):
self.name = name
self.level = None
def set(self, value):
self.level = {
"VCC2V5": "LVCMOS25",
"VCC3V3": "LVCMOS33",
}[value]
def __str__(self):
assert self.level, "%s object accessed before voltage level set!" % self.name
return self.level
def __add__(self, o):
return str(self) + o
def __radd__(self, o):
return o + str(self)
# VCC Bank 0 == 3V3
LVCMOS_BANK0 = "LVCMOS33"
# VCC Bank 1 == 3V3
LVCMOS_BANK1 = "LVCMOS33"
# VCC Bank 2 == 3V3 or 2V5
LVCMOS_BANK2 = DynamicLVCMOS("LVCMOS_BANK2")
# VCC Bank 3 == 1V8
LVCMOS_BANK3 = "LVCMOS18"
# VCC Aux == 3V3
_io = [
# NET "clk" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
# SG8002JF - 100MHz - CMOS Crystal Oscillator
("clk100", 0, Pins("L15"), IOStandard(LVCMOS_BANK1)),
# M0/RESET button
# VCCB2 --[10K]--+--[1k]-- M0/Reset
# |
# GND -[ BTN ]-+--[390]- BTNRST
# NET "btn<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
("cpu_reset", 0, Pins("T15"), IOStandard(LVCMOS_BANK2)),
## onBoard USB controller - FIXME
# CY7C68013A-56
# EEPROM config 24AA128 -- A0,A1,A2 = 1,0,0 -- JP9 connects / disconnects SDA
# NET "EppAstb" LOC = "B9"; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA
# NET "EppDstb" LOC = "A9"; # Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = U1-FLAGB
# NET "UsbFlag" LOC = "C15"; # Bank = 0, Pin name = IO_L64P_SCP5, Sch name = U1-FLAGC
# NET "EppWait" LOC = "F13"; # Bank = 0, Pin name = IO_L63P_SCP7, Sch name = U1-SLRD
# NET "EppDB<0>" LOC = "A2"; # Bank = 0, Pin name = IO_L2N, Sch name = U1-FD0
# NET "EppDB<1>" LOC = "D6"; # Bank = 0, Pin name = IO_L3P, Sch name = U1-FD1
# NET "EppDB<2>" LOC = "C6"; # Bank = 0, Pin name = IO_L3N, Sch name = U1-FD2
# NET "EppDB<3>" LOC = "B3"; # Bank = 0, Pin name = IO_L4P, Sch name = U1-FD3
# NET "EppDB<4>" LOC = "A3"; # Bank = 0, Pin name = IO_L4N, Sch name = U1-FD4
# NET "EppDB<5>" LOC = "B4"; # Bank = 0, Pin name = IO_L5P, Sch name = U1-FD5
# NET "EppDB<6>" LOC = "A4"; # Bank = 0, Pin name = IO_L5N, Sch name = U1-FD6
# NET "EppDB<7>" LOC = "C5"; # Bank = 0, Pin name = IO_L6P, Sch name = U1-FD7
# HDMI2USB configuration....
("fx2", 0,
Subsignal("ifclk", Pins("C10")),
Subsignal("data", Pins("A2 D6 C6 B3 A3 B4 A4 C5")),
Subsignal("addr", Pins("A14 B14"), Misc("DRIVE=12")),
Subsignal("flaga", Pins("B9"), Misc("DRIVE=12")),
Subsignal("flagb", Pins("A9"), Misc("DRIVE=12")),
Subsignal("flagc", Pins("C15"), Misc("DRIVE=12")),
Subsignal("rd_n", Pins("F13"), Misc("DRIVE=12")),
Subsignal("wr_n", Pins("E13")),
Subsignal("oe_n", Pins("A15"), Misc("DRIVE=12")),
Subsignal("cs_n", Pins("B2")),
Subsignal("pktend_n", Pins("C4"), Misc("DRIVE=12")),
IOStandard(LVCMOS_BANK0)
),
## onBoard Quad-SPI Flash
# 16Mbyte x4 SPI Flash for configuration & data storage. An FPGA
# configuration file requires less than 12Mbits, leaving 116Mbits
# available for user data.
# Numonyx -- N25Q12-F8 or N25Q12-SF
# DQ0 - SDI, DQ1 - SDO, DQ2 -> ^WP/DQ2 (pulled high), DQ3 -> ^HOLD/DQ3 (pulled high)
("spiflash4x", 0,
# NET "FlashCS" LOC = "V3"; # Bank = 2, Pin name = IO_L65N_CSO_B_2, Sch name = CS
Subsignal("cs_n", Pins("V3")),
# NET "FlashCLK" LOC = "R15"; # Bank = 2, Pin name = IO_L1P_CCLK_2, Sch name = SCK
Subsignal("clk", Pins("R15")),
# NET "FlashMemDq<0>" LOC = "T13"; # Bank = 2, Pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI
# NET "FlashMemDq<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = DQ1
# NET "FlashMemDq<2>" LOC = "T14"; # Bank = 2, Pin name = IO_L12P_D1_MISO2_2, Sch name = DQ2
# NET "FlashMemDq<3>" LOC = "V14"; # Bank = 2, Pin name = IO_L12N_D2_MISO3_2, Sch name = DQ3
Subsignal("dq", Pins("T13", "R13", "T14", "V14")),
IOStandard(LVCMOS_BANK2), Misc("SLEW=FAST")
),
## onBoard Leds
# NET "Led<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0
# NET "Led<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1
# NET "Led<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2
# NET "Led<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3
# NET "Led<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4
# NET "Led<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
# NET "Led<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
# NET "Led<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
("user_led", 0, Pins("U18"), IOStandard(LVCMOS_BANK1)),
("user_led", 1, Pins("M14"), IOStandard(LVCMOS_BANK1)),
("user_led", 2, Pins("N14"), IOStandard(LVCMOS_BANK1)),
("user_led", 3, Pins("L14"), IOStandard(LVCMOS_BANK1)),
("user_led", 4, Pins("M13"), IOStandard(LVCMOS_BANK1)),
("user_led", 5, Pins("D4"), IOStandard(LVCMOS_BANK0)),
("user_led", 6, Pins("P16"), IOStandard(LVCMOS_BANK1)),
("user_led", 7, Pins("N12"), IOStandard(LVCMOS_BANK2)),
## onBoard PUSH BUTTONS - FIXME
# Mapping "up" to north
# VCC1V8 - pulled down to GND via 10k
# NET "btn<1>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU
("user_btn", 0, Pins("N4"), IOStandard(LVCMOS_BANK3)), # North button
# NET "btn<2>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL
("user_btn", 1, Pins("P4"), IOStandard(LVCMOS_BANK3)), # East button
# NET "btn<3>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND
("user_btn", 2, Pins("P3"), IOStandard(LVCMOS_BANK3)), # South button
# NET "btn<4>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR
("user_btn", 3, Pins("F6"), IOStandard(LVCMOS_BANK3)), # West button
# NET "btn<5>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC
("user_btn", 4, Pins("F5"), IOStandard(LVCMOS_BANK3)), # Center button
## onBoard SWITCHES - FIXME
# SW(0,1,2,3) - VCC3V3 / GND
# SW(4,5,6) - VCCB2 / GND
# SW(7) - VCC1V8 / GND
# NET "sw<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0
# NET "sw<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1
# NET "sw<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2
# NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3
# NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4
# NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
# NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
# NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
("user_sw", 0, Pins("A10"), IOStandard(LVCMOS_BANK0)),
("user_sw", 1, Pins("D14"), IOStandard(LVCMOS_BANK0)),
("user_sw", 2, Pins("C14"), IOStandard(LVCMOS_BANK0)),
("user_sw", 3, Pins("P15"), IOStandard(LVCMOS_BANK1)),
("user_sw", 4, Pins("P12"), IOStandard(LVCMOS_BANK2)),
("user_sw", 5, Pins("R5"), IOStandard(LVCMOS_BANK2)),
("user_sw", 6, Pins("T5"), IOStandard(LVCMOS_BANK2)),
("user_sw", 7, Pins("E4"), IOStandard(LVCMOS_BANK3)),
## TEMAC Ethernet MAC - FIXME
# 10/100/1000 Ethernet PHY
# 88E111-B2-RCJ1-C000 - Marvell Alaska Tri-mode PHY (the 88E1111)
# paired with a Halo HFJ11-1G01E RJ-45 connector
# Runs from 1.2V power supply
("eth_clocks", 0,
# NET "phytxclk" LOC = "K16"; # Bank = 1, Pin name = IO_L41N_GCLK8_M1CASN, Sch name = E-TXCLK
Subsignal("tx", Pins("K16")),
# NET "phygtxclk" LOC = "L12"; # Bank = 1, Pin name = IO_L40P_GCLK11_M1A5, Sch name = E-GTXCLK
Subsignal("gtx", Pins("L12")),
# NET "phyrxclk" LOC = "K15"; # Bank = 1, Pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = E-RXCLK
Subsignal("rx", Pins("K15")),
IOStandard(LVCMOS_BANK1)
),
("eth", 0,
# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET
Subsignal("rst_n", Pins("G13")),
# NET "phyint" LOC = "L16"; # Bank = 1, Pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = E-INT
Subsignal("int_n", Pins("L16")),
# NET "phymdi" LOC = "N17"; # Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = E-MDIO
Subsignal("mdio", Pins("N17")),
# NET "phymdc" LOC = "F16"; # Bank = 1, Pin name = IO_L1N_A24_VREF, Sch name = E-MDC
Subsignal("mdc", Pins("F16")),
# NET "phyrxdv" LOC = "F17"; # Bank = 1, Pin name = IO_L35P_A11_M1A7, Sch name = E-RXDV
Subsignal("rx_dv", Pins("F17")),
# NET "phyrxer" LOC = "F18"; # Bank = 1, Pin name = IO_L35N_A10_M1A2, Sch name = E-RXER
Subsignal("rx_er", Pins("F18")),
# NET "phyRXD<0>" LOC = "G16"; # Bank = 1, Pin name = IO_L38P_A5_M1CLK, Sch name = E-RXD0
# NET "phyRXD<1>" LOC = "H14"; # Bank = 1, Pin name = IO_L36N_A8_M1BA1, Sch name = E-RXD1
# NET "phyRXD<2>" LOC = "E16"; # Bank = 1, Pin name = IO_L33P_A15_M1A10, Sch name = E-RXD2
# NET "phyRXD<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L1P_A25, Sch name = E-RXD3
# NET "phyRXD<4>" LOC = "F14"; # Bank = 1, Pin name = IO_L30P_A21_M1RESET, Sch name = E-RXD4
# NET "phyRXD<5>" LOC = "E18"; # Bank = 1, Pin name = IO_L33N_A14_M1A4, Sch name = E-RXD5
# NET "phyRXD<6>" LOC = "D18"; # Bank = 1, Pin name = IO_L31N_A18_M1A12, Sch name = E-RXD6
# NET "phyRXD<7>" LOC = "D17"; # Bank = 1, Pin name = IO_L31P_A19_M1CKE, Sch name = E-RXD7
Subsignal("rx_data", Pins("G16 H14 E16 F15 F14 E18 D18 D17")),
# NET "phytxen" LOC = "H15"; # Bank = 1, Pin name = IO_L37P_A7_M1A0, Sch name = E-TXEN
Subsignal("tx_en", Pins("H15")),
# NET "phytxer" LOC = "G18"; # Bank = 1, Pin name = IO_L38N_A4_M1CLKN, Sch name = E-TXER
Subsignal("tx_er", Pins("G18")),
# NET "phyTXD<0>" LOC = "H16"; # Bank = 1, Pin name = IO_L37N_A6_M1A1, Sch name = E-TXD0
# NET "phyTXD<1>" LOC = "H13"; # Bank = 1, Pin name = IO_L36P_A9_M1BA0, Sch name = E-TXD1
# NET "phyTXD<2>" LOC = "K14"; # Bank = 1, Pin name = IO_L39N_M1ODT, Sch name = E-TXD2
# NET "phyTXD<3>" LOC = "K13"; # Bank = 1, Pin name = IO_L34N_A12_M1BA2, Sch name = E-TXD3
# NET "phyTXD<4>" LOC = "J13"; # Bank = 1, Pin name = IO_L39P_M1A3, Sch name = E-TXD4
# NET "phyTXD<5>" LOC = "G14"; # Bank = 1, Pin name = IO_L30N_A20_M1A11, Sch name = E-TXD5
# NET "phyTXD<6>" LOC = "H12"; # Bank = 1, Pin name = IO_L32P_A17_M1A8, Sch name = E-TXD6
# NET "phyTXD<7>" LOC = "K12"; # Bank = 1, Pin name = IO_L34P_A13_M1WE, Sch name = E-TXD7
Subsignal("tx_data", Pins("H16 H13 K14 K13 J13 G14 H12 K12")),
# C17 - from Atlys reference manual, not listed in UCF file?
Subsignal("col", Pins("C17")),
# C18 - from Atlys reference manual, not listed in UCF file?
Subsignal("crs", Pins("C18")),
IOStandard(LVCMOS_BANK1)
),
## DDR2
# 128Mbyte DDR2 16-bit wide data @ 800MHz
# Older boards - MT47H64M16HR-25E - DDR2 - 2.5ns @ CL = 5 (DDR2-800)
# Newer boards - MIRA P3R1GE3EGF G8E DDR2 -
#
# The interface supports SSTL18 signaling. Address and control signals
# are terminated through 47-ohm resistors to a 0.9V VTT, and data
# signals use the On-Die-Termination (ODT) feature of the DDR2 chip.
#
# When generating a MIG core for the MIRA part, selecting the
# “EDE1116AXXX-8E” device will result in the correct timing parameters
# being set. When generating a component for the Micron part, it can be
# selected by name within the wizard. The part loaded on your Atlys can
# be determined by examining the print on the DDR2 component (IC13).
#
# NET "DDR2CLK0" LOC = "G3"; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P
# NET "DDR2CLK1" LOC = "G1"; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N
("ddram_clock", 0,
Subsignal("p", Pins("G3")),
Subsignal("n", Pins("G1")),
IOStandard("DIFF_SSTL18_II"), Misc("IN_TERM=NONE")
),
("ddram", 0,
# NET "DDR2CKE" LOC = "H7"; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE
Subsignal("cke", Pins("H7"), IOStandard("SSTL18_II")),
# NET "DDR2RASN" LOC = "L5"; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS
Subsignal("ras_n", Pins("L5"), IOStandard("SSTL18_II")),
# NET "DDR2CASN" LOC = "K5"; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS
Subsignal("cas_n", Pins("K5"), IOStandard("SSTL18_II")),
# NET "DDR2WEN" LOC = "E3"; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE
Subsignal("we_n", Pins("E3"), IOStandard("SSTL18_II")),
# NET "DDR2BA0" LOC = "F2"; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0
# NET "DDR2BA1" LOC = "F1"; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1
# NET "DDR2BA2" LOC = "E1"; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2
Subsignal("ba", Pins("F2 F1 E1"), IOStandard("SSTL18_II")),
# NET "DDR2A0" LOC = "J7"; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0
# NET "DDR2A1" LOC = "J6"; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1
# NET "DDR2A2" LOC = "H5"; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2
# NET "DDR2A3" LOC = "L7"; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3
# NET "DDR2A4" LOC = "F3"; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4
# NET "DDR2A5" LOC = "H4"; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5
# NET "DDR2A6" LOC = "H3"; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6
# NET "DDR2A7" LOC = "H6"; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7
# NET "DDR2A8" LOC = "D2"; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8
# NET "DDR2A9" LOC = "D1"; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9
# NET "DDR2A10" LOC = "F4"; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10
# NET "DDR2A11" LOC = "D3"; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11
# NET "DDR2A12" LOC = "G6"; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12
Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6"), IOStandard("SSTL18_II")),
# NET "DDR2DQ0" LOC = "L2"; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0
# NET "DDR2DQ1" LOC = "L1"; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1
# NET "DDR2DQ2" LOC = "K2"; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2
# NET "DDR2DQ3" LOC = "K1"; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3
# NET "DDR2DQ4" LOC = "H2"; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4
# NET "DDR2DQ5" LOC = "H1"; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5
# NET "DDR2DQ6" LOC = "J3"; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6
# NET "DDR2DQ7" LOC = "J1"; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7
# NET "DDR2DQ8" LOC = "M3"; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8
# NET "DDR2DQ9" LOC = "M1"; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9
# NET "DDR2DQ10" LOC = "N2"; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10
# NET "DDR2DQ11" LOC = "N1"; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11
# NET "DDR2DQ12" LOC = "T2"; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12
# NET "DDR2DQ13" LOC = "T1"; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13
# NET "DDR2DQ14" LOC = "U2"; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14
# NET "DDR2DQ15" LOC = "U1"; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15
Subsignal("dq", Pins(
"L2 L1 K2 K1 H2 H1 J3 J1",
"M3 M1 N2 N1 T2 T1 U2 U1"), IOStandard("SSTL18_II")),
# U == Upper, L == Lower
# NET "DDR2UDQS" LOC="P2"; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P
# NET "DDR2UDQSN" LOC="P1"; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N
# NET "DDR2LDQS" LOC="L4"; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P
# NET "DDR2LDQSN" LOC="L3"; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N
Subsignal("dqs", Pins("P2 L4"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dqs_n", Pins("P1 L3"), IOStandard("DIFF_SSTL18_II")),
# NET "DDR2UDM" LOC="K4"; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = DDR-UDM
# NET "DDR2LDM" LOC="K3"; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM
Subsignal("dm", Pins("K4 K3"), IOStandard("SSTL18_II")),
# NET "DDR2ODT" LOC="K6"; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT
Subsignal("odt", Pins("K6"), IOStandard("SSTL18_II"))
),
## onboard HDMI OUT
# Type A connector, marked as J2 on the board, next to the power connector.
# Buffered / protected with TMDS141RHAR
# NET "HDMIOUTCLKP" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P
# NET "HDMIOUTCLKN" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N
# NET "HDMIOUTD0P" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P
# NET "HDMIOUTD0N" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N
# NET "HDMIOUTD1P" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P
# NET "HDMIOUTD1N" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N
# NET "HDMIOUTD2P" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P
# NET "HDMIOUTD2N" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N
# NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL
# NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA
("hdmi_out", 0,
Subsignal("clk_p", Pins("B6"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("A6"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("D8"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("C8"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("C7"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("A7"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("B8"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("A8"), IOStandard("TMDS_33")),
# Disconnect JP6 and JP7 for FPGA SCL/SDA control, otherwise
# this is connected to J3's SCL/SDA pins.
Subsignal("scl", Pins("D9"), IOStandard("I2C")),
Subsignal("sda", Pins("C9"), IOStandard("I2C")),
),
## onboard HDMI IN1 (PMODA)
# Type A connector, marked as J1, on side with USB connectors.
# Buffered / protected with TMDS141RHAR
# JP4 connects / disconnects 5V to HDMI pin 18, for input to work make
# sure it is connected.
# NET "HDMIIN1CLKP" LOC = "D11"; # Bank = 0, Pin name = IO_L36P_GCLK15, Sch name = TMDS-RXB-CLK_P
# NET "HDMIIN1CLKN" LOC = "C11"; # Bank = 0, Pin name = IO_L36N_GCLK14, Sch name = TMDS-RXB-CLK_N
# NET "HDMIIN1D0P" LOC = "G9"; # Bank = 0, Pin name = IO_L38P, Sch name = TMDS-RXB-0_P
# NET "HDMIIN1D0N" LOC = "F9"; # Bank = 0, Pin name = IO_L38N_VREF, Sch name = TMDS-RXB-0_N
# NET "HDMIIN1D1P" LOC = "B11"; # Bank = 0, Pin name = IO_L39P, Sch name = TMDS-RXB-1_P
# NET "HDMIIN1D1N" LOC = "A11"; # Bank = 0, Pin name = O_L39N, Sch name = TMDS-RXB-1_N
# NET "HDMIIN1D2P" LOC = "B12"; # Bank = 0, Pin name = IO_L41P, Sch name = TMDS-RXB-2_P
# NET "HDMIIN1D2N" LOC = "A12"; # Bank = 0, Pin name = IO_L41N, Sch name = TMDS-RXB-2_N
# NET "HDMIIN1SCL" LOC = "C13"; # Bank = 0, Pin name = IO_L50P, Sch name = PMOD-SCL
# NET "HDMIIN1SDA" LOC = "A13"; # Bank = 0, Pin name = IO_L50N, Sch name = PMOD-SDA
("hdmi_in", 0,
Subsignal("clk_p", Pins("D11")),
Subsignal("clk_n", Pins("C11")),
Subsignal("data0_p", Pins("G9")),
Subsignal("data0_n", Pins("F9")),
Subsignal("data1_p", Pins("B11")),
Subsignal("data1_n", Pins("A11")),
Subsignal("data2_p", Pins("B12")),
Subsignal("data2_n", Pins("A12")),
# Make sure JP2 is connected. Shared with J1.
Subsignal("scl", Pins("C13"), IOStandard(LVCMOS_BANK0)),
Subsignal("sda", Pins("A13"), IOStandard(LVCMOS_BANK0)),
#Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")),
#Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33"))
),
## onboard HDMI IN2
# Type A connector, marked as J3, between audio connectors and Ethernet
# RJ45 connector.
# Buffered / protected with a TMDS141RHAR
# JP8 connects / disconnects 5V to HDMI pin 18, for input to work make
# sure it is connected.
# NET "HDMIIN2CLKP" LOC = "H17"; # Bank = 1, Pin name = IO_L43P_GCLK5_M1DQ4, Sch name = TMDS-RX-CLK_P
# NET "HDMIIN2CLKN" LOC = "H18"; # Bank = 1, Pin name = IO_L43N_GCLK4_M1DQ5, Sch name = TMDS-RX-CLK_N
# NET "HDMIIN2D0P" LOC = "K17"; # Bank = 1, Pin name = IO_L45P_A1_M1LDQS, Sch name = TMDS-RX-0_P
# NET "HDMIIN2D0N" LOC = "K18"; # Bank = 1, Pin name = IO_L45N_A0_M1LDQSN, Sch name = TMDS-RX-0_N
# NET "HDMIIN2D1P" LOC = "L17"; # Bank = 1, Pin name = IO_L46P_FCS_B_M1DQ2, Sch name = TMDS-RX-1_P
# NET "HDMIIN2D1N" LOC = "L18"; # Bank = 1, Pin name = IO_L46N_FOE_B_M1DQ3, Sch name = TMDS-RX-1_N
# NET "HDMIIN2D2P" LOC = "J16"; # Bank = 1, Pin name = IO_L44P_A3_M1DQ6, Sch name = TMDS-RX-2_P
# NET "HDMIIN2D2N" LOC = "J18"; # Bank = 1, Pin name = IO_L44N_A2_M1DQ7, Sch name = TMDS-RX-2_N
# NET "HDMIIN2SCL" LOC = "M16"; # Bank = 1, Pin name = IO_L47P_FWE_B_M1DQ0, Sch name = TMDS-RX-SCL
# NET "HDMIIN2SDA" LOC = "M18"; # Bank = 1, Pin name = IO_L47N_LDC_M1DQ1, Sch name = TMDS-RX-SDA
("hdmi_in", 1,
Subsignal("clk_p", Pins("H17")),
Subsignal("clk_n", Pins("H18")),
Subsignal("data0_p", Pins("K17")),
Subsignal("data0_n", Pins("K18")),
Subsignal("data1_p", Pins("L17")),
Subsignal("data1_n", Pins("L18")),
Subsignal("data2_p", Pins("J16")),
Subsignal("data2_n", Pins("J18")),
# Disconnect JP6 and JP7 for FPGA SCL/SDA control, otherwise
# this is connected to J2's SCL/SDA pins.
Subsignal("scl", Pins("M16"), IOStandard(LVCMOS_BANK1)),
Subsignal("sda", Pins("M18"), IOStandard(LVCMOS_BANK1)),
#Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")),
#Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33"))
),
## onboard USB Host Controller - FIXME
# PIC32MX440F256H-40I/MR
# USB-HID port (for mouse/keyboard)
# PS/2 Keyboard - K_CLK - P17
# PS/2 Keyboard - K_DAT - N15
# PS/2 Mouse - M_CLK - N18
# PS/2 Mouse - M_DAT - P18
# FPGA Serial programming - DIN - R13
# FPGA Serial programming - CLK - R15
# NET "USBCLK" LOC = "P17"; # Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = PIC32-SCK1
# NET "USBSDI" LOC = "N15"; # Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = PIC32-SDI1
# NET "USBSS" LOC = "P18"; # Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = PIC32-SS1
# NET "USBSDO" LOC = "N18"; # Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = PIC32-SDO1
## Audio - FIXME
# National Semiconductor - LM4550VH
# AC-97 Codec with line-in, line-out, mic, & headphone
# Audio
# NET "BITCLK" LOC = "L13"; # Bank = 1, Pin name = IO_L40N_GCLK10_M1A6, Sch name = AUD-BIT-CLK
# NET "AUDSYNC" LOC = "U17"; # Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = AUD-SYNC
# NET "AUDRST" LOC = "T17"; # Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = AUD-RESET
# NET "AUDSDI" LOC = "T18"; # Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = AUD-SDI
# NET "AUDSDO" LOC = "N16"; # Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AUD-SDO
## USB UART Connector
# USB Micro B port marked as UART between HDMI connector and USB A connector.
# XR21V1410IL16 - Vizzini USB Serial - https://github.com/shenki/exar-uart-driver
# NET "UartRx" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
# NET "UartTx" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
("serial", 0,
Subsignal("rx", Pins("A16"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("B16"), IOStandard("LVCMOS33")),
),
# ("fpga_cfg",
# Subsignal("din", Pins("T14")),
# Subsignal("cclk", Pins("R14")),
# Subsignal("init_b", Pins("T12")),
# Subsignal("prog_b", Pins("A2")),
# Subsignal("done", Pins("T15")),
# ),
# ("jtag",
# Subsignal("tms", Pins("B2")),
# Subsignal("tdo", Pins("B16")),
# Subsignal("tdi", Pins("B1")),
# Subsignal("tck", Pins("A15")),
# ),
]
# This Micro-D HDMI connector only works when VCCB2 is set to 3V3.
_io_vccb2_3v3 = [
## PMOD Connector
# Micro-D connector, marked as JB, on the same side as switches + LEDs
# but on the underside of the board below MOD connector. Works as
# either output or input because it isn't buffered. Also often referred
# to as "JA".
# JP12 connects VCC to 3.3V or 2.5V, make sure 3.3V is selected.
# JP3 connects / disconnects 5V to HDMI pin 19.
# * To use as output, remove the jumper.
# * To use as input, make sure it is connected.
# NET "JB<5>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = JA-CLK_P
# NET "JB<4>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = JA-CLK_N
# NET "JB<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, Sch name = JA-D0_P
# NET "JB<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, Sch name = JA-D0_N
# NET "JB<7>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, Sch name = JA-D1_P
# NET "JB<6>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, Sch name = JA-D1_N
# NET "JB<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, Sch name = JA-D2_P
# NET "JB<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, Sch name = JA-D2_N
("hdmi_out", 1,
Subsignal("clk_p", Pins("T9"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("V9"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("R3"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("T3"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("T4"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("V4"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("N5"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("P6"), IOStandard("TMDS_33")),
# Make sure JP2 is connected. Shared with JA.
#Subsignal("scl", Pins("C13"), IOStandard("LVCMOS33")),
#Subsignal("sda", Pins("A13"), IOStandard("LVCMOS33")),
),
]
_io_vccb2_2v5 = []
_connectors = [
## onboard VHDCI - FIXME
# Can either run at 2.5V or 3.3V dependent on JP12 connector.
# Channel 1 connects to P signals, Channel 2 to N signals
# NET "VHDCIIO1<0>" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P
# NET "VHDCIIO1<1>" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P
# NET "VHDCIIO1<2>" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P
# NET "VHDCIIO1<3>" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P
# NET "VHDCIIO1<4>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P
# NET "VHDCIIO1<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P
# NET "VHDCIIO1<6>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P
# NET "VHDCIIO1<7>" LOC = "M10"; # Bank = 2, Pin name = *IO_L22P, Sch name = EXP-IO8_P
# NET "VHDCIIO1<8>" LOC = "U11"; # Bank = 2, Pin name = IO_L23P, Sch name = EXP-IO9_P
# NET "VHDCIIO1<9>" LOC = "R10"; # Bank = 2, Pin name = IO_L29P_GCLK3, Sch name = EXP-IO10_P
# NET "VHDCIIO1<10>" LOC = "U10"; # Bank = 2, Pin name = IO_L30P_GCLK1_D13, Sch name = EXP-IO11_P
# NET "VHDCIIO1<11>" LOC = "R8"; # Bank = 2, Pin name = IO_L31P_GCLK31_D14, Sch name = EXP-IO12_P
# NET "VHDCIIO1<12>" LOC = "M8"; # Bank = 2, Pin name = *IO_L40P, Sch name = EXP-IO13_P
# NET "VHDCIIO1<13>" LOC = "U8"; # Bank = 2, Pin name = IO_L41P, Sch name = EXP-IO14_P
# NET "VHDCIIO1<14>" LOC = "U7"; # Bank = 2, Pin name = IO_L43P, Sch name = EXP-IO15_P
# NET "VHDCIIO1<15>" LOC = "N7"; # Bank = 2, Pin name = *IO_L44P, Sch name = EXP-IO16_P
# NET "VHDCIIO1<16>" LOC = "T6"; # Bank = 2, Pin name = IO_L45P, Sch name = EXP-IO17_P
# NET "VHDCIIO1<17>" LOC = "R7"; # Bank = 2, Pin name = IO_L46P, Sch name = EXP-IO18_P
# NET "VHDCIIO1<18>" LOC = "N6"; # Bank = 2, Pin name = *IO_L47P, Sch name = EXP-IO19_P
# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P
# --
# NET "VHDCIIO2<0>" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N
# NET "VHDCIIO2<1>" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N
# NET "VHDCIIO2<2>" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N
# NET "VHDCIIO2<3>" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N
# NET "VHDCIIO2<4>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N
# NET "VHDCIIO2<5>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N
# NET "VHDCIIO2<6>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N
# NET "VHDCIIO2<7>" LOC = "N9"; # Bank = 2, Pin name = *IO_L22N, Sch name = EXP-IO8_N
# NET "VHDCIIO2<8>" LOC = "V11"; # Bank = 2, Pin name = IO_L23N, Sch name = EXP-IO9_N
# NET "VHDCIIO2<9>" LOC = "T10"; # Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = EXP-IO10_N
# NET "VHDCIIO2<10>" LOC = "V10"; # Bank = 2, Pin name = IO_L30N_GCLK0_USERCCLK, Sch name = EXP-IO11_N
# NET "VHDCIIO2<11>" LOC = "T8"; # Bank = 2, Pin name = IO_L31N_GCLK30_D15, Sch name = EXP-IO12_N
# NET "VHDCIIO2<12>" LOC = "N8"; # Bank = 2, Pin name = *IO_L40N, Sch name = EXP-IO13_N
# NET "VHDCIIO2<13>" LOC = "V8"; # Bank = 2, Pin name = IO_L41N_VREF, Sch name = EXP-IO14_N
# NET "VHDCIIO2<14>" LOC = "V7"; # Bank = 2, Pin name = IO_L43N, Sch name = EXP-IO15_N
# NET "VHDCIIO2<15>" LOC = "P8"; # Bank = 2, Pin name = *IO_L44N, Sch name = EXP-IO16_N
# NET "VHDCIIO2<16>" LOC = "V6"; # Bank = 2, Pin name = IO_L45N, Sch name = EXP-IO17_N
# NET "VHDCIIO2<17>" LOC = "T7"; # Bank = 2, Pin name = IO_L46N, Sch name = EXP-IO18_N
# NET "VHDCIIO2<18>" LOC = "P7"; # Bank = 2, Pin name = *IO_L47N, Sch name = EXP-IO19_N
# NET "VHDCIIO2<19>" LOC = "V5"; # Bank = 2, Pin name = IO_49N_D4, Sch name = EXP-IO20_N
("VHDCI",
{
"EXP-IO1_P": "U16",
"EXP-IO2_P": "U15",
"EXP-IO3_P": "U13",
"EXP-IO4_P": "M11",
"EXP-IO5_P": "R11",
"EXP-IO6_P": "T12",
"EXP-IO7_P": "N10",
"EXP-IO8_P": "M10",
"EXP-IO9_P": "U11",
"EXP-IO10_P": "R10",
"EXP-IO11_P": "U10",
"EXP-IO12_P": "R8",
"EXP-IO13_P": "M8",
"EXP-IO14_P": "U8",
"EXP-IO15_P": "U7",
"EXP-IO16_P": "N7",
"EXP-IO17_P": "T6",
"EXP-IO18_P": "R7",
"EXP-IO19_P": "N6",
"EXP-IO20_P": "U5",
"EXP-IO1_N": "V16",
"EXP-IO2_N": "V15",
"EXP-IO3_N": "V13",
"EXP-IO4_N": "N11",
"EXP-IO5_N": "T11",
"EXP-IO6_N": "V12",
"EXP-IO7_N": "P11",
"EXP-IO8_N": "N9",
"EXP-IO9_N": "V11",
"EXP-IO10_N": "T10",
"EXP-IO11_N": "V10",
"EXP-IO12_N": "T8",
"EXP-IO13_N": "N8",
"EXP-IO14_N": "V8",
"EXP-IO15_N": "V7",
"EXP-IO16_N": "P8",
"EXP-IO17_N": "V6",
"EXP-IO18_N": "T7",
"EXP-IO19_N": "P7",
"EXP-IO20_N": "V5",
}
),
]
_hdmi_infos = {
"HDMI_IN0_MNEMONIC": "J1",
"HDMI_IN0_DESCRIPTION" : (
" Type A connector, marked as J1, on side with USB connectors.\\r\\n"
" To use J1, make sure:\\r\\n"
" * JP4 has a jumper (it connects / disconnects 5V to HDMI pin 18).\\r\\n"
" * JP2 (marked only as SDA/SCL - not to be confused with JP6 and JP6)\\r\\n"
" has *two* jumpers (horizontally).\\r\\n"
" * JP5 has a jumper (it enables the HDMI input buffer).\\r\\n"
),
"HDMI_IN1_MNEMONIC": "J3",
"HDMI_IN1_DESCRIPTION" : (
" Type A connector, marked as J3, between audio connectors and\\r\\n"
" Ethernet RJ45 connector.\\r\\n"
" To use J3, make sure:\\r\\n"
" * JP8 has a jumper (it connects / disconnects 5V to HDMI pin 18)\\r\\n"
" * JP6 and JP7 do *not* have any jumpers (it connect J3's and J2's\\r\\n"
" EDID lines together).\\r\\n"
),
"HDMI_OUT0_MNEMONIC": "J2",
"HDMI_OUT0_DESCRIPTION" : (
" Type A connector, marked as J2, next to the power connector.\\r\\n"
" To use J2, make sure:\\r\\n"
" * JP8 has a jumper (it connects / disconnects 5V to HDMI pin 18)\\r\\n"
" * JP6 and JP7 do *not* have any jumpers (it connect J3's and J2's\\r\\n"
" EDID lines together).\\r\\n"
),
"HDMI_OUT1_MNEMONIC": "JB",
"HDMI_OUT1_DESCRIPTION" : (
" Micro-D connector, marked as JB, on the same side as switches\\r\\n"
" + LEDs but on the underside of the board below MOD connector.\\r\\n"
" Works as either output or input because it isn't buffered.\\r\\n"
" Also often referred to as 'JA'.\\r\\n"
)
}
class Platform(XilinxPlatform):
name = "atlys"
default_clk_name = "clk100"
default_clk_period = 10.0
hdmi_infos = _hdmi_infos
# https://reference.digilentinc.com/atlys:atlys:refmanual#flash_memory
# The Atlys has a XC6SLX45 which bitstream takes up ~12Mbit (1484472 bytes)
# 0x200000 offset (16Mbit) gives plenty of space
gateware_size = 0x200000
# Micron N25Q128 (ID 0x0018ba20)
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_model = "n25q128"
spiflash_read_dummy_bits = 10
spiflash_clock_div = 4
spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
def __init__(self, programmer="openocd", vccb2_voltage="VCC3V3"):
# Some IO configurations only work at certain vccb2 voltages.
if vccb2_voltage == "VCC3V3":
_io.extend(_io_vccb2_3v3)
elif vccb2_voltage == "VCC2V5":
_io.extend(_io_vccb2_2v5)
else:
raise SystemError("Unknown vccb2_voltage=%r" % vccb2_voltage)
# Resolve the LVCMOS_BANK2 voltage level before anything uses the _io
# definition.
LVCMOS_BANK2.set(vccb2_voltage)
# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer
# FPGA AUX is connected to the 3.3V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def create_programmer(self):
# Preferred programmer - Needs ixo-usb-jtag and latest openocd.
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
if self.programmer == "openocd":
return OpenOCD(config="board/digilent_atlys.cfg", flash_proxy_basename=proxy)
# Alternative programmers - not regularly tested.
elif self.programmer == "xc3sprog":
return XC3SProg("jtaghs1_fast", "bscan_spi_digilent_atlys.bit")
elif self.programmer == "impact":
return iMPACT()
elif self.programmer == "adept":
return Adept("Atlys", 0)
elif self.programmer == "fpgalink":
from mibuild.fpgalink_programmer import FPGALink
return FPGALink("1443:0007")
elif self.programmer == "urjtag":
return UrJTAG(cable="USBBlaster", pld="spartan-6")
else:
raise ValueError("{} programmer is not supported".format(self.programmer))
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# The oscillator clock sources.
try:
self.add_period_constraint(self.lookup_request("clk100"), 10.0)
except ConstraintError:
pass
# HDMI input clock pins.
for i in range(2):
try:
self.add_period_constraint(self.lookup_request("hdmi_in", i).clk_p, 12)
except ConstraintError:
pass
# Ethernet input clock pins.
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 40.0)
except ConstraintError:
pass
# USB input clock pins.
try:
self.add_period_constraint(self.lookup_request("fx2").ifclk, 10)
except ConstraintError:
pass
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.iMPACT",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((37550, 37618), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx45-csg324-3"""', '_io', '_connectors'], {}), "(self, 'xc6slx45-csg324-3', _io, _connectors)\n", (37573, 37618), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38798, 38840), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (38824, 38840), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38313, 38321), 'litex.build.xilinx.iMPACT', 'iMPACT', ([], {}), '()\n', (38319, 38321), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38524, 38545), 'mibuild.fpgalink_programmer.FPGALink', 'FPGALink', (['"""1443:0007"""'], {}), "('1443:0007')\n", (38532, 38545), False, 'from mibuild.fpgalink_programmer import FPGALink\n')] |
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.openocd import OpenOCD
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
("rgb_leds", 0,
Subsignal("r", Pins("G6 G3 J3 K1")),
Subsignal("g", Pins("F6 J4 J2 H6")),
Subsignal("b", Pins("E1 G4 H4 K2")),
IOStandard("LVCMOS33")
),
("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("D10")),
Subsignal("rx", Pins("A9")),
IOStandard("LVCMOS33")),
("spiflash_4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33")
),
("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
("ddram", 0,
Subsignal("a", Pins(
"R2 M6 N4 T1 N6 R7 V6 U7",
"R8 V7 R6 U6 T6 T8"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P3"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("M4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("U8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"K5 L3 K3 L6 M3 M1 L4 M2",
"V4 T5 U4 V5 V1 T3 U3 R3"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL15")),
Subsignal("odt", Pins("R5"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("K6"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("eth_clocks", 0,
Subsignal("tx", Pins("H16")),
Subsignal("rx", Pins("F15")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("C16")),
Subsignal("mdio", Pins("K13")),
Subsignal("mdc", Pins("F16")),
Subsignal("rx_dv", Pins("G16")),
Subsignal("rx_er", Pins("C17")),
Subsignal("rx_data", Pins("D18 E17 E18 G17")),
Subsignal("tx_en", Pins("H15")),
Subsignal("tx_data", Pins("H14 J14 J13 H17")),
Subsignal("col", Pins("D17")),
Subsignal("crs", Pins("G14")),
IOStandard("LVCMOS33")
),
]
class Platform(XilinxPlatform):
name = "arty"
default_clk_name = "clk100"
default_clk_period = 10.0
# From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
# 17536096 bits == 2192012 == 0x21728c -- Therefore 0x220000
gateware_size = 0x220000
# Micron N25Q128A13ESF40 (ID 0x0018ba20)
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_model = "n25q128a13"
spiflash_read_dummy_bits = 10
spiflash_clock_div = 2
spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
def __init__(self, toolchain="vivado", programmer="openocd"):
XilinxPlatform.__init__(self, "xc7a35t-csg324-1", _io,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/digilent_arty.cfg", flash_proxy_basename=proxy)
elif self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
| [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.VivadoProgrammer"
] | [((4558, 4633), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-csg324-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a35t-csg324-1', _io, toolchain=toolchain)\n", (4581, 4633), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((5276, 5345), 'litex.build.openocd.OpenOCD', 'OpenOCD', ([], {'config': '"""board/digilent_arty.cfg"""', 'flash_proxy_basename': 'proxy'}), "(config='board/digilent_arty.cfg', flash_proxy_basename=proxy)\n", (5283, 5345), False, 'from litex.build.openocd import OpenOCD\n'), ((5409, 5427), 'litex.build.xilinx.XC3SProg', 'XC3SProg', (['"""nexys4"""'], {}), "('nexys4')\n", (5417, 5427), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((5489, 5545), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""n25q128-3.3v-spi-x1_x2_x4"""'}), "(flash_part='n25q128-3.3v-spi-x1_x2_x4')\n", (5505, 5545), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n')] |
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