code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs -------------------------------------------------------------------------------------------... | [
"litex.build.generic_platform.IOStandard",
"litex.build.openocd.OpenOCD",
"litex.build.generic_platform.Pins",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((367, 377), 'litex.build.generic_platform.Pins', 'Pins', (['"""Y9"""'], {}), "('Y9')\n", (371, 377), False, 'from litex.build.generic_platform import Pins, IOStandard, Subsignal\n'), ((379, 401), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (389, 401), False, 'f... |
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("E18"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("F13"), IOStandard("LVCMOS33")),
("user_... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.VivadoProgrammer"
] | [((4437, 4511), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7s50csga324-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7s50csga324-1', _io, toolchain=toolchain)\n", (4460, 4511), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), (... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import TinyProgProgrammer
# IOs --... | [
"litex.build.lattice.programmer.TinyProgProgrammer",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((2067, 2160), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-lp8k-cm81"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-lp8k-cm81', _io, _connectors,\n toolchain='icestorm')\n", (2091, 2160), False, 'from litex.build.lattice import Lattic... |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]
# Import lxbuildenv to integrate the ... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((1727, 1736), 'migen.Signal', 'Signal', (['(8)'], {}), '(8)\n', (1733, 1736), False, 'from migen import Module, Signal, Instance, ClockDomain, If, run_simulation\n'), ((1763, 1797), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {'write_from_dev': '(True)'}), '(8, write_from_dev=True)\n', (1773, 179... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs --------------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2778, 2869), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020clg400-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7z020clg400-1', _io, _connectors,\n toolchain=toolchain)\n", (2801, 2869), False, 'from litex.build.xilinx import XilinxPlatform, ... |
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 Dolu1990 <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copy... | [
"litex.build.tools.generated_banner",
"litex.soc.doc.csr.DocumentedCSRRegion",
"litex.build.tools.get_litex_git_revision",
"litex.soc.doc.rst.reflow",
"litex.build.tools.get_migen_git_revision"
] | [((1470, 1492), 'os.getenv', 'os.getenv', (['"""CLANG"""', '""""""'], {}), "('CLANG', '')\n", (1479, 1492), False, 'import os\n'), ((3895, 3917), 'litex.build.tools.generated_banner', 'generated_banner', (['"""//"""'], {}), "('//')\n", (3911, 3917), False, 'from litex.build.tools import generated_banner\n'), ((4193, 42... |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by a... | [
"litex.soc.integration.soc_core.soc_core_argdict",
"litex.soc.integration.builder.builder_argdict"
] | [((4207, 4251), 'os.path.join', 'os.path.join', (['directory', 'f"""{build_name}.bit"""'], {}), "(directory, f'{build_name}.bit')\n", (4219, 4251), False, 'import os\n'), ((2759, 2795), 'litex.soc.integration.soc_core.soc_core_argdict', 'soc_core.soc_core_argdict', (['self.args'], {}), '(self.args)\n', (2784, 2795), Fa... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs -------------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((1213, 1298), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu49dr-ffvf1760-2-e"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xczu49dr-ffvf1760-2-e', _io, toolchain=toolchain\n )\n", (1236, 1298), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgramme... |
#!/usr/bin/env python3
#
# This file is part of Linux-on-LiteX-VexRiscv
#
# Copyright (c) 2019-2021, Linux-on-LiteX-VexRiscv Developers
# SPDX-License-Identifier: BSD-2-Clause
import json
import argparse
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from lite... | [
"litex.build.sim.config.SimConfig",
"litex.soc.cores.cpu.vexriscv_smp.VexRiscvSMP.args_read",
"litex.soc.cores.cpu.vexriscv_smp.VexRiscvSMP.args_fill",
"litex.build.sim.verilator.verilator_build_args",
"litex.build.sim.SimPlatform.__init__",
"litex.tools.litex_sim.get_sdram_phy_settings",
"litex.build.s... | [((5305, 5378), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Linux on LiteX-VexRiscv Simulation"""'}), "(description='Linux on LiteX-VexRiscv Simulation')\n", (5328, 5378), False, 'import argparse\n'), ((5796, 5825), 'litex.soc.cores.cpu.vexriscv_smp.VexRiscvSMP.args_fill', 'VexRiscvSM... |
#!/usr/bin/env python3
#
# This file is based on https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/radiona_ulx3s.py
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.... | [
"litex.build.lattice.trellis.trellis_args",
"litex.build.lattice.trellis.trellis_argdict"
] | [((6880, 6900), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (6892, 6900), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((2774, 2851), 'litex_boards.platforms.radiona_ulx3s.Platform', 'radiona_ulx3s.Platform', ([], {'device': 'device',... |
#!/usr/bin/env python3
import argparse
from migen import *
from platforms import icebreaker
from litex.soc.cores import *
from litex.soc.integration import soc_core
from litex.soc.cores import gpio
from litex.soc.integration.builder import *
from gateware import ice40
# Build --------------------------------------... | [
"litex.soc.integration.soc_core.SoCCore",
"litex.soc.cores.gpio.GPIOOut"
] | [((403, 424), 'platforms.icebreaker.Platform', 'icebreaker.Platform', ([], {}), '()\n', (422, 424), False, 'from platforms import icebreaker\n'), ((488, 602), 'litex.soc.integration.soc_core.SoCCore', 'soc_core.SoCCore', (['platform', 'sys_clk_freq'], {'cpu_variant': '"""lite"""', 'integrated_rom_size': '(8192)', 'inte... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
import importlib
from migen import *
from litex.build.io import CRG
from litex.soc.integration.soc_core im... | [
"litex.soc.integration.soc.SoCRegion"
] | [((4122, 4140), 'litex_boards.platforms.tec0117.Platform', 'tec0117.Platform', ([], {}), '()\n', (4138, 4140), False, 'from litex_boards.platforms import tec0117\n'), ((4643, 4700), 'spiflash.serialflash.SerialFlashManager.get_flash_device', 'SerialFlashManager.get_flash_device', (['"""ftdi://ftdi:2232/2"""'], {}), "('... |
# Support for the Digilent Arty Board
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.interconnect import wishbone
from gateware... | [
"litex.soc.interconnect.wishbone.SRAM"
] | [((2063, 2112), 'targets.utils.csr_map_update', 'csr_map_update', (['SoCSDRAM.csr_map', 'csr_peripherals'], {}), '(SoCSDRAM.csr_map, csr_peripherals)\n', (2077, 2112), False, 'from targets.utils import csr_map_update, period_ns\n'), ((1885, 1939), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer... |
#!/usr/bin/env python3
#
# Wrappers specifically meant for cores integrating in LiteX SoCs.
#
# Copyright (C) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: CERN-OHL-P-2.0
#
import importlib
import math
import os
import pkg_resources
import tempfile
from migen import *
from migen.genlib.cdc import MultiReg, Pulse... | [
"litex.soc.cores.uart.UART.__init__",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.stream.Endpoint"
] | [((1214, 1239), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', (['width'], {}), '(width)\n', (1232, 1239), False, 'from litex.soc.interconnect import stream, wishbone\n'), ((3858, 3922), 'pkg_resources.resource_filename', 'pkg_resources.resource_filename', (['"""no2migen"""', '"""cores/no2usb/rtl/""... |
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015-2021 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2019 Antmicro <www.antmicro.com>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016-2017 Tim 'mithro' Ansell <<... | [
"litex.soc.integration.export.get_csr_svd",
"litex.soc.integration.export.get_linker_regions",
"litex.soc.doc.generate_docs",
"litex.soc.integration.export.get_csr_header",
"litex.soc.integration.export.get_memory_x",
"litex.soc.integration.export.get_cpu_mak",
"litex.soc.integration.soc.colorer",
"li... | [((1024, 1043), 'os.path.realpath', 'os.path.realpath', (['d'], {}), '(d)\n', (1040, 1043), False, 'import os\n'), ((1134, 1170), 'os.makedirs', 'os.makedirs', (['dir_path'], {'exist_ok': '(True)'}), '(dir_path, exist_ok=True)\n', (1145, 1170), False, 'import os\n'), ((1072, 1096), 'os.path.exists', 'os.path.exists', (... |
import subprocess
from migen.fhdl.module import Module
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import CSRStorage, CSRStatus, CSRField, AutoCSR
class Version(Module, AutoCSR):
def __init__(self, model, models, seed):
"""Create a `Version` block.
Arg... | [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.integration.doc.ModuleDoc"
] | [((503, 702), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""SoC Version Information\n\n This block contains various information about the state of the source code\n repository when this SoC was built.\n """'], {}), '(\n """SoC Version Information\n\n This block... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex.build.generic_platform import Pins, Subsignal
from litex.build.sim.config import SimConfig
from litex.soc.interconnect.csr import CSR... | [
"litex.build.sim.gtkwave.wishbone_sorter",
"litex.soc.interconnect.csr.CSR",
"litex.soc.integration.builder.Builder",
"litex.build.sim.gtkwave.regex_filter",
"litex.build.sim.gtkwave.wishbone_colorer",
"litex.build.generic_platform.Pins",
"litex.build.sim.gtkwave.dfi_per_phase_colorer",
"litex.build.s... | [((7756, 7802), 'os.path.join', 'os.path.join', (['builder.gateware_dir', '"""sim.gtkw"""'], {}), "(builder.gateware_dir, 'sim.gtkw')\n", (7768, 7802), False, 'import os\n'), ((11640, 11707), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Generic LiteX SoC Simulation"""'}), "(description... |
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.openfpgaloader import OpenFPGALoader
from litex.soc.cores.bitbang import I2CMaster
from ..crg_ecp5 import CRG
from litespi.opcodes import SpiNorFlashOpCodes as Codes
from ..flash_modules import S25FL064L
from... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.lattice.LatticePlatform.__init__"
] | [((4331, 4441), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', 'f"""LFE5U-{device}-8BG256C"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, f'LFE5U-{device}-8BG256C', _io, _connectors,\n toolchain=toolchain, **kwargs)\n", (4355, 4441), False, 'from litex.build.l... |
# Support for the Numato Saturn (http://numato.com/product/saturn-spartan-6-fpga-development-board-with-ddr-sdram)
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
#FIXME:
#this is for the LX45 version
#check on "no connect pins" for LX9 and LX25
_io = [
("clk100", 0, Pins(... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((7516, 7583), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx45-2csg324"""', '_io', '_connectors'], {}), "(self, 'xc6slx45-2csg324', _io, _connectors)\n", (7539, 7583), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
"""Small SoC definition for zephyr to run on"""
import logging
import os
from litescope import LiteScopeAnalyzer
from litex.build.generic_platform import IOStandard, Pins, Subsignal
from litex.soc.cores.gpio import GPIOIn, GPIOOut
from litex_boards.targets.c10lprefkit import BaseSoC
pmod1_uart_ios = [
(
"... | [
"litex.build.generic_platform.Pins",
"litex.build.generic_platform.IOStandard"
] | [((426, 451), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""3.3-V LVTTL"""'], {}), "('3.3-V LVTTL')\n", (436, 451), False, 'from litex.build.generic_platform import IOStandard, Pins, Subsignal\n'), ((579, 609), 'logging.getLogger', 'logging.getLogger', (['"""ZephyrSoC"""'], {}), "('ZephyrSoC')\n", (596... |
from migen import *
from migen.genlib.misc import WaitTimer
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from litex.build.tools import write_to_file
from litex.soc.interconnect.csr import *
from litex.soc.cores.gpio import GPIOInOut
from litex.soc.interconnect import stream
class LiteScopeIO(Module, Aut... | [
"litex.soc.cores.gpio.GPIOInOut",
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.AsyncFIFO",
"litex.build.tools.write_to_file"
] | [((528, 562), 'litex.soc.cores.gpio.GPIOInOut', 'GPIOInOut', (['self.input', 'self.output'], {}), '(self.input, self.output)\n', (537, 562), False, 'from litex.soc.cores.gpio import GPIOInOut\n'), ((1285, 1331), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['self.enable.storage', 'enable', '"""scope"""'], {}), "(self.enab... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2017-2018 <NAME> <<EMAIL>>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import re
import sys
import math
import subprocess
import shutil
from shu... | [
"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file"
] | [((1812, 1853), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['ys_name', 'ys_contents'], {}), '(ys_name, ys_contents)\n', (1831, 1853), False, 'from litex.build import tools\n'), ((6826, 6899), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['build_script_file', 'script_contents'], {'force_uni... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Acorn CLE 215+ is a cryptocurrency mining accelerator card from SQRL that can be repurposed
# as a generic FPGA PCIe development board: http://www.squirrelsresearch.com/acorn-cle-215-plus
from ... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3881, 3956), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg484-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg484-2', _io, toolchain='vivado')\n", (3904, 3956), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((4654, 4712), 'litex.b... |
#!/usr/bin/env python3
# This script generates dut.v file for testing asics-ws usb1_device
# Disable pylint's E1101, which breaks completely on migen
# pylint:disable=E1101
import argparse
from migen import Module, Signal, Instance, ClockDomain, If
from migen.fhdl.structure import ResetSignal
from litex.build.gener... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.build.sim.platform.SimPlatform.__init__",
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.build.generic_platform.Pins",
"litex.soc.integration.builder.Builder",
"litex.soc.integration.soc_core.soc_core_args",
"litex.soc.integration.builder.bu... | [((7185, 7270), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build test file for dummy or eptri module"""'}), "(description='Build test file for dummy or eptri module'\n )\n", (7208, 7270), False, 'import argparse\n'), ((7279, 7299), 'litex.soc.integration.builder.builder_args', 'bu... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 bunnie <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen.genlib.cdc import MultiReg
from litex.soc.cores.clock import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr_eventma... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.doc.ModuleDoc"
] | [((1033, 6291), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""Intro\n\n I2S controller/peripheral creates a controller/peripheral audio interface instance depending on a configured controller variable.\n Tx and Rx interfaces are inferred based upon the presence or absence of the respective pin... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>$
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect import stream
# Altera Atlantic JTAG -----------------------------------------------------------------------------
class JTAGAtlantic(Module):
def... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((364, 394), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (379, 394), False, 'from litex.soc.interconnect import stream\n'), ((426, 456), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (441, 456), ... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk12", 0, Pins("A10"), IOStandard("LVCMOS33"... | [
"litex.build.lattice.LatticePlatform.request",
"litex.build.lattice.LatticePlatform.__init__"
] | [((3745, 3831), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5UM5G-85F-8BG381"""', '_io', '_connectors'], {}), "(self, 'LFE5UM5G-85F-8BG381', _io, _connectors, **\n kwargs)\n", (3769, 3831), False, 'from litex.build.lattice import LatticePlatform\n'), ((4191, 4237), 'l... |
from migen import *
from litex.soc.interconnect import stream
# This is the module generated by litex_read_verilog.
# We can't use it directly because it doesn't have
# stream endpoints.
# We could add endpoints directly here but lets do this in
# another module (StreamAddOne)
# !!!!!!!!!! Your module from verilog h... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((443, 473), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (458, 473), False, 'from litex.soc.interconnect import stream\n'), ((505, 535), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (520, 535), ... |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
# The iCEBreaker is the first open source iCE40 FPGA development board desig... | [
"litex.build.lattice.programmer.IceStormProgrammer",
"litex.soc.cores.clock.iCE40PLL",
"litex.soc.cores.up5kspram.Up5kSPRAM"
] | [((4870, 4890), 'litex.build.lattice.programmer.IceStormProgrammer', 'IceStormProgrammer', ([], {}), '()\n', (4888, 4890), False, 'from litex.build.lattice.programmer import IceStormProgrammer\n'), ((5190, 5252), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on iCEBreaker"""'}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.efinix.platform import EfinixPlatform
from litex.build.efinix import EfinixProgrammer
# IOs -----------------------------------------------... | [
"litex.build.efinix.EfinixProgrammer",
"litex.build.efinix.platform.EfinixPlatform.__init__",
"litex.build.efinix.platform.EfinixPlatform.do_finalize"
] | [((4003, 4113), 'litex.build.efinix.platform.EfinixPlatform.__init__', 'EfinixPlatform.__init__', (['self', '"""T20F256C4"""', '_io', '_connectors'], {'iobank_info': '_bank_info', 'toolchain': 'toolchain'}), "(self, 'T20F256C4', _io, _connectors, iobank_info=\n _bank_info, toolchain=toolchain)\n", (4026, 4113), Fals... |
#!/usr/bin/env python3
from migen import *
from migen.genlib.io import CRG
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores import dna, xadc
from litex.soc.cores.spi ... | [
"litex.soc.cores.dna.DNA",
"litex.soc.cores.xadc.XADC",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2139, 2213), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-2fgg676"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-2fgg676', _io, toolchain='vivado')\n", (2162, 2213), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((3030, 3039), 'litex.soc... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2021 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
import os
import sys
import socket
import time
import threading
from litex.tools.rem... | [
"litex.tools.remote.comm_uart.CommUART",
"litex.tools.remote.comm_usb.CommUSB",
"litex.tools.remote.etherbone.EtherboneRecord",
"litex.tools.remote.etherbone.EtherbonePacket",
"litex.tools.remote.comm_udp.CommUDP",
"litex.tools.remote.etherbone.EtherboneWrites",
"litex.tools.remote.comm_devmem.CommDevme... | [((6111, 6170), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX Server utility"""'}), "(description='LiteX Server utility')\n", (6134, 6170), False, 'import argparse\n'), ((2899, 2948), 'socket.socket', 'socket.socket', (['socket.AF_INET', 'socket.SOCK_STREAM'], {}), '(socket.AF_INE... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 msloniewski <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import deca
from litex.soc.cores.clock import Max10PLL
from litex.soc.integration.soc_core impo... | [
"litex.soc.cores.clock.Max10PLL"
] | [((2605, 2661), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on DECA"""'}), "(description='LiteX SoC on DECA')\n", (2628, 2661), False, 'import argparse\n'), ((878, 903), 'litex.soc.cores.clock.Max10PLL', 'Max10PLL', ([], {'speedgrade': '"""-6"""'}), "(speedgrade='-6')\n", (8... |
#!/usr/bin/env python3
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("Power On...")
wb.regs.gpio0_out.write(1)
time.sleep(0.5)
wb.regs.gpio0_out.write(0)
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((74, 88), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (86, 88), False, 'from litex import RemoteClient\n'), ((155, 170), 'time.sleep', 'time.sleep', (['(0.5)'], {}), '(0.5)\n', (165, 170), False, 'import time\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# iCESugar FPGA: https://www.aliexpress.com/item/4001201771358.html
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer impo... | [
"litex.build.lattice.programmer.IceSugarProgrammer",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((3452, 3544), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'ice40-up5k-sg48', _io, _connectors,\n toolchain=toolchain)\n", (3476, 3544), False, 'from litex.build.lattice import LatticePlatf... |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by a... | [
"litex.get_data_mod",
"litex.soc.cores.cpu.vexriscv.core.CPU_VARIANTS.update",
"litex.soc.cores.cpu.vexriscv.core.GCC_FLAGS.update"
] | [((899, 1401), 'litex.soc.cores.cpu.vexriscv.core.CPU_VARIANTS.update', 'core.CPU_VARIANTS.update', (["{'custom': 'VexRiscv_Custom', 'custom+cfu': 'VexRiscv_CustomCfu', 'hps+cfu':\n 'VexRiscv_HpsCfu', 'hpsdelta+cfu': 'VexRiscv_HpsdeltaCfu', 'dbpl8+cfu':\n 'VexRiscv_dbpl8Cfu', 'slim+cfu': 'VexRiscv_SlimCfu', 'slim... |
#!/usr/bin/env python3
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
# Modified for OrangeCrab ADC board <NAME> <<EMAIL>>
# Power Dissipation suggestions from Greg on OrangeCrab Discord:
# You can save a reasonable amount of power by not using the "virtual"
# power pins. The next step is disabling ODT... | [
"litex.soc.cores.gpio.GPIOOut",
"litex.build.generic_platform.Pins",
"litex.build.lattice.trellis.trellis_argdict",
"litex.soc.cores.spi_flash.SpiFlashDualQuad",
"litex.build.generic_platform.IOStandard",
"litex.build.lattice.trellis.trellis_args"
] | [((12852, 12914), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on OrangeCrab"""'}), "(description='LiteX SoC on OrangeCrab')\n", (12875, 12914), False, 'import argparse\n'), ((13128, 13148), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parse... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
import os
from migen import *
from litex.build.generic_platform import tools
from litex.soc.integration.soc_core import *
from litex.soc.integration.cpu_interface import get_csr_header
from litex.soc.interconnect import wishbone
from litex.soc.interco... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.axi.AXI2Wishbone",
"litex.soc.interconnect.axi.AXIInterface",
"litex.build.generic_platform.tools.write_to_file"
] | [((2930, 2992), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': '(32)', 'address_width': '(32)', 'id_width': '(12)'}), '(data_width=32, address_width=32, id_width=12)\n', (2946, 2992), False, 'from litex.soc.interconnect import axi\n'), ((5188, 5249), 'litex.soc.interconnect.axi.AXIIn... |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
import time
wb = RemoteClient()
wb.open()
wb.write(0x82002800, 0x77)
time.sleep(1)
wb.write(0x82002800, 0)
time.sleep(1)
wb.write(0x82002800, 0x77)
#for i in range(6):
# print(wb.read(0x08000000+4*i))
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((91, 105), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (103, 105), False, 'from litex.tools.litex_client import RemoteClient\n'), ((144, 157), 'time.sleep', 'time.sleep', (['(1)'], {}), '(1)\n', (154, 157), False, 'import time\n'), ((182, 195), 'time.sleep', 'time.sleep', (['(1)'], {}),... |
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock import ECP5PLL
from litex.soc.interconnect.csr import AutoCSR, CSRStorage
class CRG(Module, AutoCSR):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_por ... | [
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.cores.clock.ECP5PLL"
] | [((1184, 1193), 'litex.soc.cores.clock.ECP5PLL', 'ECP5PLL', ([], {}), '()\n', (1191, 1193), False, 'from litex.soc.cores.clock import ECP5PLL\n'), ((1477, 1489), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {}), '()\n', (1487, 1489), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage\n'),... |
#!/usr/bin/env python3
import os
import argparse
from migen import *
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
fr... | [
"litex.soc.cores.spi.SPIMaster"
] | [((3233, 3293), 'litex.soc.cores.spi.SPIMaster', 'SPIMaster', (['spi_pads', 'data_width', 'self.clk_freq', 'spi_clk_freq'], {}), '(spi_pads, data_width, self.clk_freq, spi_clk_freq)\n', (3242, 3293), False, 'from litex.soc.cores.spi import SPIMaster\n'), ((6890, 6975), 'liteeth.mac.LiteEthMAC', 'LiteEthMAC', ([], {'phy... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020-2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use:
# python3 -m litex_boards.targets.sqrl_fk33 --with-hbm --sys-clk-freq=250e6 --csr-csv=csr.csv --build --load
# litex_server --jtag --jtag-config=openocd_xc7_f... | [
"litex.soc.integration.soc.SoCRegion",
"litex.soc.cores.ram.xilinx_usp_hbm2.USPHBM2"
] | [((5951, 6007), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on FK33"""'}), "(description='LiteX SoC on FK33')\n", (5974, 6007), False, 'import argparse\n'), ((2191, 2206), 'litex_boards.platforms.fk33.Platform', 'fk33.Platform', ([], {}), '()\n', (2204, 2206), False, 'from l... |
"""Submodule for controlling the 7-Segment display"""
from litex.soc.interconnect.csr import AutoCSR, CSRStorage
from migen import Array, If, Module, Signal
class SegmentDisplay(Module, AutoCSR):
def __init__(self, an_pads, c_pads, sys_clk_freq, rate):
self._d = CSRStorage(3, description="Dot segments")
... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((278, 319), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(3)'], {'description': '"""Dot segments"""'}), "(3, description='Dot segments')\n", (288, 319), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage\n'), ((339, 391), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {'... |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["icestorm", "yosys", "nextpnr-ice40"]
#LX_CONFIG = "skip-git" # This... | [
"litex.soc.integration.builder.Builder",
"litex.soc.interconnect.csr.CSRStorage"
] | [((462, 487), 'os.path.dirname', 'os.path.dirname', (['__file__'], {}), '(__file__)\n', (477, 487), False, 'import os, os.path, shutil, sys, subprocess\n'), ((1640, 1703), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build Fomu Main Gateware"""'}), "(description='Build Fomu Main Gatewa... |
#
# apple2.py - Part of a2fomu - Copyright (c) 2020-2021 <NAME>
#
# This file is part of a2fomu which is released under the two clause BSD
# licence. See file LICENSE in the project root directory or visit the
# project at https://github.com/elecbrick/a2fomu for full license details.
from migen import Module, Signal,... | [
"litex.soc.interconnect.csr.CSRField",
"litex.soc.integration.doc.ModuleDoc",
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.csr.CSRStorage"
] | [((659, 975), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""FOMU Apple II+\n A virtual computer within a virtual computer inside a USB port.\n Instantiate 6502 processor with 1MHz core clock.\n Tie in to system memory as a wishbone master.\n Create virtual keyboar... |
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
'''
Fills the row memories from a DMA source.
'''
from migen import *
from litex.soc.interconnect import csr, stream
from csr_mixin import CSRMixin
from utils import FastLatch
class StreamCounter(Module):
def __init__(self, layout):
... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.Converter"
] | [((374, 397), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (389, 397), False, 'from litex.soc.interconnect import csr, stream\n'), ((452, 463), 'utils.FastLatch', 'FastLatch', ([], {}), '()\n', (461, 463), False, 'from utils import FastLatch\n'), ((1381, 1404), 'litex.soc... |
#
# This file is part of LiteSPI
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from collections import OrderedDict
from migen import *
from litespi.common import *
from litex.soc.interconnect import stream
from litex.soc.interconnect.... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.packet.Dispatcher",
"litex.soc.interconnect.packet.Arbiter",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((427, 462), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy_ctl_layout'], {}), '(spi_phy_ctl_layout)\n', (442, 462), False, 'from litex.soc.interconnect import stream\n'), ((483, 519), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy_data_layout'], {}), '(spi_phy_data_la... |
# Support for the Pipistrello - http://pipistrello.saanlima.com/
from fractions import Fraction
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT46H32M16
from ... | [
"litex.gen.genlib.resetsync.AsyncResetSynchronizer"
] | [((7367, 7416), 'targets.utils.csr_map_update', 'csr_map_update', (['SoCSDRAM.csr_map', 'csr_peripherals'], {}), '(SoCSDRAM.csr_map, csr_peripherals)\n', (7381, 7416), False, 'from targets.utils import csr_map_update\n'), ((1538, 1564), 'fractions.Fraction', 'Fraction', (['(clk_freq * p)', 'f0'], {}), '(clk_freq * p, f... |
from migen import Module, Signal, If, Instance, ClockSignal
from litex.soc.integration.doc import ModuleDoc
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField
class SBLED(Module, AutoCSR):
def __init__(self, revision, pads):
rgba_pwm = Signal(3)
self.intro = ModuleDoc(... | [
"litex.soc.interconnect.csr.CSRField",
"litex.soc.integration.doc.ModuleDoc",
"litex.soc.interconnect.csr.CSRStorage"
] | [((278, 287), 'migen.Signal', 'Signal', (['(3)'], {}), '(3)\n', (284, 287), False, 'from migen import Module, Signal, If, Instance, ClockSignal\n'), ((310, 1135), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""RGB LED Controller\n\n The ICE40 contains two different RGB LED control devices. Th... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2016-2017 Tim 'mithro' Ansell <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platf... | [
"litex.build.xilinx.programmer.XC3SProg",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((5395, 5463), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx45-csg324-3"""', '_io', '_connectors'], {}), "(self, 'xc6slx45-csg324-3', _io, _connectors)\n", (5418, 5463), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((5581, 5603), 'litex.build.xilinx.program... |
#!/usr/bin/env python3
import os
import csv
import sys
import glob
import json
import time
from operator import or_
from functools import reduce
from collections import namedtuple
from migen import log2_int
# ###########################################################################
def discover_generated_files_d... | [
"litex.tools.litex_server.RemoteServer"
] | [((1516, 1546), 'sys.path.append', 'sys.path.append', (['GENERATED_DIR'], {}), '(GENERATED_DIR)\n', (1531, 1546), False, 'import sys\n'), ((12306, 12361), 'collections.namedtuple', 'namedtuple', (['"""BISTError"""', "['offset', 'data', 'expected']"], {}), "('BISTError', ['offset', 'data', 'expected'])\n", (12316, 12361... |
from orbtrace.usb_serialnumber import USBSerialNumberHandler
from orbtrace.test_io import TestIO
from migen import *
from litex.soc.integration.soc_core import SoCCore
from litex.soc.integration.soc import SoCRegion
from .trace import TraceCore
from .trace.usb_handler import TraceUSBHandler
from .power.usb_handler i... | [
"litex.soc.interconnect.axi.AXILiteClockDomainCrossing",
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.ClockDomainCrossing",
"litex.soc.interconnect.stream.Demultiplexer",
"litex.soc.interconnect.axi.AXILiteInterface",
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.... | [((2050, 2163), 'litex.soc.integration.soc_core.SoCCore.__init__', 'SoCCore.__init__', (['self', 'platform', 'sys_clk_freq'], {'ident': '"""LiteX SoC for Orbtrace"""', 'ident_version': '(True)'}), "(self, platform, sys_clk_freq, ident=\n 'LiteX SoC for Orbtrace', ident_version=True, **kwargs)\n", (2066, 2163), False... |
#!/usr/bin/env python3
import os
import argparse
import sys
import subprocess
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import DDROutput
#from migen.genlib.io import CRG
#from litex.build.generic_platform import IOStandard, Subsignal, Pins
from litex_boards.pl... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((5918, 5987), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Colorlight 5A-75B"""'}), "(description='LiteX SoC on Colorlight 5A-75B')\n", (5941, 5987), False, 'import argparse\n'), ((6043, 6063), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}),... |
# This file is Copyright (c) 2016 <NAME> <<EMAIL>>
# License: BSD
from collections import OrderedDict
from migen.genlib.misc import WaitTimer
from litex.soc.interconnect import stream
from litex.soc.interconnect.stream import EndpointDescription
from litex.soc.interconnect.packet import *
from litex.soc.interconnect... | [
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream.EndpointDescription"
] | [((751, 786), 'litex.soc.interconnect.stream.EndpointDescription', 'EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (770, 786), False, 'from litex.soc.interconnect.stream import EndpointDescription\n'), ((950, 999), 'litex.soc.interconnect.stream.EndpointDescription', 'EndpointDescription', (['pay... |
from litex.tools.litex_client import RemoteClient
import numpy as np
import matplotlib.pyplot as plt
import pdb
wb = RemoteClient()
wb.open()
ADC_SRAM_BASE = 0x20000000
nsamples = 1024
MAX_SAMPLES = 128
Fs = 50e6
midrange = 2048
if __name__ == '__main__':
remaining_samples = nsamples - MAX_SAMPLES
s = np.... | [
"litex.tools.litex_client.RemoteClient"
] | [((118, 132), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (130, 132), False, 'from litex.tools.litex_client import RemoteClient\n'), ((618, 656), 'numpy.uint16', 'np.uint16', (['[(s_i & 4095) for s_i in s]'], {}), '([(s_i & 4095) for s_i in s])\n', (627, 656), True, 'import numpy as np\n'... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programm... | [
"litex.build.lattice.programmer.LatticeProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((7164, 7271), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', "(device + '-40-9BG400C')", '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, device + '-40-9BG400C', _io, _connectors,\n toolchain=toolchain, **kwargs)\n", (7188, 7271), False, 'from litex.build.lattice i... |
#
# This file is part of LiteSPI
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import WaitTimer
from litex.soc.interconnect import wishbone, stream
from litex.gen.common import reverse_bytes
from litex.soc.interconnect.csr import ... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.stream.Endpoint",
"litex.gen.common.reverse_bytes"
] | [((1618, 1654), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_core2phy_layout'], {}), '(spi_core2phy_layout)\n', (1633, 1654), False, 'from litex.soc.interconnect import wishbone, stream\n'), ((1686, 1722), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy2core_layout'], {}),... |
#
# This file is part of USB3-PIPE project.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.common import *
from usb3_pipe.lfps import LFPSUnit
from usb3_pipe.training import TSUnit
from usb3_pipe.ltssm ... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((1194, 1238), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (1209, 1238), False, 'from litex.soc.interconnect import stream\n'), ((1261, 1305), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl... |
#!/usr/bin/python3
from fusesoc.capi2.generator import Generator
from litex.build.tools import write_to_file
from litex.build.tools import replace_in_file
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.lattice import LatticePlatform
from litex.soc.integration.... | [
"litex.build.tools.replace_in_file",
"litex.build.lattice.LatticePlatform",
"litex.build.xilinx.XilinxPlatform"
] | [((766, 799), 'os.path.join', 'os.path.join', (['base_dir', '"""gen-src"""'], {}), "(base_dir, 'gen-src')\n", (778, 799), False, 'import os\n'), ((469, 494), 'os.path.join', 'os.path.join', (['base', 'added'], {}), '(base, added)\n', (481, 494), False, 'import os\n'), ((502, 519), 'os.path.exists', 'os.path.exists', ([... |
#
# This file is part of LiteX-Boards.
#
# Support for the ZTEX USB-FGPA Module 2.13:
# <https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html>
# With (no-so-optional) expansion, either the ZTEX Debug board:
# <https://www.ztex.de/usb-fpga-2/debug.e.html>
# Or the SBusFPGA adapter board:
# <https://github.com/rdolbeau/SB... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((6622, 6698), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', 'device', '_io', '_connectors'], {'toolchain': 'toolchain'}), '(self, device, _io, _connectors, toolchain=toolchain)\n', (6645, 6698), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((7340, 7384), 'litex.build... |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys"]
# Import lxbuildenv to integrate the ... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.wishbone.SRAM.__init__",
"litex.build.generic_platform.Misc",
"litex.soc.interconnect.wishbone.SRAM",
"litex.build.generic_platform.Pins",
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.integration.builder.Builder",
"litex.soc.in... | [((347, 366), 'sys.path.append', 'sys.path.append', (['""""""'], {}), "('')\n", (362, 366), False, 'import sys\n'), ((35055, 35118), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build Fomu Main Gateware"""'}), "(description='Build Fomu Main Gateware')\n", (35078, 35118), False, 'import... |
#!/usr/bin/env python3
import math
from migen import *
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.builder import Builder
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.clock import S7PLL, S7IDELAYCTRL
from litex_boards.platforms impor... | [
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.soc.cores.clock.S7IDELAYCTRL",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.builder.Builder",
"litex.soc.cores.clock.S7PLL"
] | [((3327, 3454), 'rowhammer_tester.targets.common.ArgumentParser', 'common.ArgumentParser', ([], {'description': '"""LiteX SoC on DDR4 Datacenter Test Board"""', 'sys_clk_freq': '"""100e6"""', 'module': '"""MTA18ASF2G72PZ"""'}), "(description='LiteX SoC on DDR4 Datacenter Test Board',\n sys_clk_freq='100e6', module='... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs -----------------------------------------------------... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((5137, 5200), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', 'device', '_io'], {'toolchain': 'toolchain'}), '(self, device, _io, toolchain=toolchain)\n', (5160, 5200), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((5826, 5885), 'litex.build.openocd.OpenOCD', 'OpenOCD'... |
#!/usr/bin/env python3
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.cores import dna, xadc
from l... | [
"litex.soc.cores.dna.DNA",
"litex.soc.cores.xadc.XADC",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((3781, 3856), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (3804, 3856), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((4771, 4780), 'litex.s... |
import time
import sdram_init as _sdram_init
from sdram_init import *
# ###########################################################################
def sdram_software_control(wb):
wb.regs.sdram_dfii_control.write(dfii_control_cke|dfii_control_odt|dfii_control_reset_n)
def sdram_hardware_control(wb):
wb.regs... | [
"litex.RemoteClient"
] | [((1449, 1466), 'time.sleep', 'time.sleep', (['(0.001)'], {}), '(0.001)\n', (1459, 1466), False, 'import time\n'), ((2220, 2231), 'time.time', 'time.time', ([], {}), '()\n', (2229, 2231), False, 'import time\n'), ((3621, 3635), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (3633, 3635), False, 'from litex imp... |
from litex import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient()
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_trigger(cond={"s7pciephy_sink_valid" : 1})
#analyzer.configure_trigger(cond={})
analyzer.con... | [
"litex.RemoteClient"
] | [((108, 122), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (120, 122), False, 'from litex import RemoteClient\n'), ((152, 208), 'litescope.software.driver.analyzer.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (['wb.regs', '"""analyzer"""'], {'debug': '(True)'}), "(wb.regs, 'analyzer', debug=True)\n",... |
# -*- coding: utf-8 -*-
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
class LED(Module, AutoCSR):
def __init__(self, pads):
self.dat = CSRStorage(8)
self.addr = CSRStorage(4)
self.ctrl = CSRStorage(len(... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((237, 250), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {}), '(8)\n', (247, 250), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((271, 284), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(4)'], {}), '(4)\n', (281, 284), False, 'from litex.soc.inter... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 Tim 'mithro' Ansell <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect import wishbone
kB = 1024
"""
... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((1749, 1774), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', (['width'], {}), '(width)\n', (1767, 1774), False, 'from litex.soc.interconnect import wishbone\n')] |
# This file is Copyright (c) 2017-2018 <NAME> <<EMAIL>>
# License: BSD
import os
import sys
import subprocess
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.lattice import common
def _build_pcf(named_sc, named_pc):
r = ""
... | [
"litex.build.tools.write_to_file",
"litex.build.tools.get_litex_git_revision"
] | [((1659, 1738), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['build_script_file', 'build_script_contents'], {'force_unix': '(False)'}), '(build_script_file, build_script_contents, force_unix=False)\n', (1678, 1738), False, 'from litex.build import tools\n'), ((1936, 1969), 'subprocess.call', 'subprocess.... |
# parts of this code are inspired from the litevideo output core
from migen import *
from litex.soc.interconnect import stream
from photonsdi.constants import *
from photonsdi.util.timing import *
class SdiTimingGenerator(Module):
def __init__(self, genlock_stream=None):
# TODO: probably some stream hand... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((381, 419), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['SDI_TIMING_PARAMETERS'], {}), '(SDI_TIMING_PARAMETERS)\n', (396, 419), False, 'from litex.soc.interconnect import stream\n'), ((467, 494), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['SDI_TIMING'], {}), '(SDI_TIMING)\n', (4... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
import unittest
from migen import *
from litex.soc.interconnect import csr
from litex.soc.interconnect import csr_bus
def csr32_write(dut, adr, dat):
for i in range(4):
yield from dut.csr.write(adr + 3 - i, (dat >> 8*i) & 0xff)
def csr... | [
"litex.soc.interconnect.csr_bus.Interface",
"litex.soc.interconnect.csr_bus.CSRBankArray",
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.csr.CSRStorage"
] | [((536, 545), 'litex.soc.interconnect.csr.CSR', 'csr.CSR', ([], {}), '()\n', (543, 545), False, 'from litex.soc.interconnect import csr\n'), ((570, 626), 'litex.soc.interconnect.csr.CSRStorage', 'csr.CSRStorage', (['(32)'], {'reset': '(305419896)', 'write_from_dev': '(True)'}), '(32, reset=305419896, write_from_dev=Tru... |
#!/usr/bin/env python3
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
class ADXL362SPI:
def __init__(self, regs):
self.regs = regs
def write(self, addr, byte):
val = (0b00001010 << 16) | ((addr & 0xff) << 8) | (byte & 0xff)
self.regs.adxl362_length.w... | [
"litex.RemoteClient"
] | [((74, 88), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (86, 88), False, 'from litex import RemoteClient\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.cdc import MultiReg
from litex.soc.interconnect import wishbone
class EMIF(Module):
"""External Memory Interface core
Provides a simple EMIF to Wishbone Mast... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((394, 414), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (412, 414), False, 'from litex.soc.interconnect import wishbone\n'), ((2445, 2465), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2463, 2465), False, 'from litex.soc.interconnect im... |
#!/usr/bin/env python3
import time
import random
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
# Test led
print("Testing Led...")
for i in range(64):
wb.regs.leds_out.write(i)
time.sleep(0.1)
# Test rgb led pwm
print("Testing RGB Led (PWM)...")
wb.regs.rgbled_r_period.write(64*1024)
w... | [
"litex.RemoteClient"
] | [((88, 102), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (100, 102), False, 'from litex import RemoteClient\n'), ((664, 681), 'random.Random', 'random.Random', (['(42)'], {}), '(42)\n', (677, 681), False, 'import random\n'), ((210, 225), 'time.sleep', 'time.sleep', (['(0.1)'], {}), '(0.1)\n', (220, 225), Fa... |
#
# This file is based on the file from LiteSDCard.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
from litex.soc.cores.dma import WishboneD... | [
"litex.soc.cores.dma.WishboneDMAReader",
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.Converter"
] | [((613, 643), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (628, 643), False, 'from litex.soc.interconnect import stream\n'), ((742, 802), 'litex.soc.cores.dma.WishboneDMAReader', 'WishboneDMAReader', (['bus'], {'with_csr': '(True)', 'endianness': 'endiannes... |
from .wrapper import Wrapper
import nmigen
import migen
import luna.usb2
from luna.gateware.architecture.car import PHYResetController
from litex.soc.interconnect.stream import Endpoint
class USBDevice(migen.Module):
def __init__(self, pads, wrapper, *args, **kwargs):
self.wrapper = wrapper
phy... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((340, 360), 'luna.gateware.architecture.car.PHYResetController', 'PHYResetController', ([], {}), '()\n', (358, 360), False, 'from luna.gateware.architecture.car import PHYResetController\n'), ((595, 612), 'migen.TSTriple', 'migen.TSTriple', (['(8)'], {}), '(8)\n', (609, 612), False, 'import migen\n'), ((632, 646), 'm... |
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
import os
from migen import *
from litex.soc.interconnect import wishbone
CPU_VARIANTS = ["standard"]
class Minerva(Module):
@property
def name(self):
return "minerva"
@pr... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((1075, 1095), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1093, 1095), False, 'from litex.soc.interconnect import wishbone\n'), ((1116, 1136), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1134, 1136), False, 'from litex.soc.interconnec... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# BeagleWire FPGA Cape:
# - Crowd Supply campaign: https://www.crowdsupply.com/qwerty-embedded-design/beaglewire
# - Docs: https://beaglewire.github.io/
# - Software Repo: https://github.com/BeagleWir... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.IceStormProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((5687, 5780), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-hx8k-tq144"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'ice40-hx8k-tq144', _io, _connectors,\n toolchain=toolchain)\n", (5711, 5780), False, 'from litex.build.lattice import LatticePla... |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from migen.genlib.misc import chooser, WaitTimer
from migen.genlib.record import Record
from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import wishbone
from litex.soc.interconnect import stream
class ... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((480, 500), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (498, 500), False, 'from litex.soc.interconnect import wishbone\n'), ((1935, 1960), 'migen.genlib.misc.WaitTimer', 'WaitTimer', (['(clk_freq // 10)'], {}), '(clk_freq // 10)\n', (1944, 1960), False, 'from migen.genlib.mis... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import socket
from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
from litex.tools.remote.etherbone import EtherboneReads, Ether... | [
"litex.tools.remote.etherbone.EtherbonePacket",
"litex.tools.remote.etherbone.EtherboneRecord",
"litex.tools.remote.csr_builder.CSRBuilder.__init__"
] | [((611, 664), 'litex.tools.remote.csr_builder.CSRBuilder.__init__', 'CSRBuilder.__init__', (['self'], {'comm': 'self', 'csr_csv': 'csr_csv'}), '(self, comm=self, csr_csv=csr_csv)\n', (630, 664), False, 'from litex.tools.remote.csr_builder import CSRBuilder\n'), ((859, 907), 'socket.socket', 'socket.socket', (['socket.A... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import usb.core
import time
from litex.tools.remote.csr_builder import CSRBuilder
# Wishbone USB Protocol Bridge
# ============================
#
# This module implements a bridge to connect LiteX to the t... | [
"litex.tools.remote.csr_builder.CSRBuilder.__init__"
] | [((2499, 2552), 'litex.tools.remote.csr_builder.CSRBuilder.__init__', 'CSRBuilder.__init__', (['self'], {'comm': 'self', 'csr_csv': 'csr_csv'}), '(self, comm=self, csr_csv=csr_csv)\n', (2518, 2552), False, 'from litex.tools.remote.csr_builder import CSRBuilder\n'), ((3275, 3294), 'time.sleep', 'time.sleep', (['(0.2 * t... |
#!/usr/bin/env python3
from litex import RemoteClient
from wb_lib import *
wb = RemoteClient(host="localhost", port=1234, csr_csv="csr.csv", debug=False)
wb.open()
dump(wb, wb.bases.hbpf_data_mem, 80)
wb.close()
| [
"litex.RemoteClient"
] | [((82, 155), 'litex.RemoteClient', 'RemoteClient', ([], {'host': '"""localhost"""', 'port': '(1234)', 'csr_csv': '"""csr.csv"""', 'debug': '(False)'}), "(host='localhost', port=1234, csr_csv='csr.csv', debug=False)\n", (94, 155), False, 'from litex import RemoteClient\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 msloniewski <<EMAIL>>
# License: BSD
import argparse
from migen import *
from litex_boards.partner.platforms import max1000
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram i... | [
"litex.soc.cores.spi_flash.SpiFlash",
"litex.soc.cores.gpio.GPIOOut.__init__"
] | [((6810, 6869), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on MAX1000"""'}), "(description='LiteX SoC on MAX1000')\n", (6833, 6869), False, 'import argparse\n'), ((726, 759), 'litex.soc.cores.gpio.GPIOOut.__init__', 'gpio.GPIOOut.__init__', (['self', 'pads'], {}), '(self, p... |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
# The Colorlight 5A-75E PCB and IOs have been documented by @derekmulcahy:
# https://github.com/q3k/chubby75/issues/59
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.OpenOCDJTAGProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((4699, 4790), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', 'device', 'io'], {'connectors': 'connectors', 'toolchain': '"""trellis"""'}), "(self, device, io, connectors=connectors, toolchain\n ='trellis')\n", (4723, 4790), False, 'from litex.build.lattice import LatticePlatf... |
#!/usr/bin/env python3
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
prog.load_bitstream("build/gateware/top.bit")
| [
"litex.build.xilinx.VivadoProgrammer"
] | [((79, 97), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (95, 97), False, 'from litex.build.xilinx import VivadoProgrammer\n')] |
from migen.fhdl.decorators import ClockDomainsRenamer
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.interconnect import stream
from gateware.encoder import EncoderDMAReader, EncoderBuffer, Encoder
from gateware.streamer import USBStreamer
from targets.atlys.video import SoC as BaseSoC
class ... | [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((485, 534), 'targets.atlys.video.SoC.__init__', 'BaseSoC.__init__', (['self', 'platform', '*args'], {}), '(self, platform, *args, **kwargs)\n', (501, 534), True, 'from targets.atlys.video import SoC as BaseSoC\n'), ((719, 749), 'gateware.encoder.EncoderDMAReader', 'EncoderDMAReader', (['encoder_port'], {}), '(encoder... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((4556, 4631), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-fgg676-3"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-fgg676-3', _io, toolchain='vivado')\n", (4579, 4631), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((5176, 5234), 'litex.b... |
import argparse
import os
from migen import *
from migen.genlib.misc import WaitTimer
from litex.soc.integration.builder import builder_args, builder_argdict, Builder
from litex.build.sim.config import SimConfig
from litex.soc.integration.soc_core import SoCMini
from litex.soc.interconnect import ahb
from litex.build.s... | [
"litex.soc.interconnect.ahb.Interface",
"litex.soc.cores.cpu.gowin_emcu.core.AHBFlash",
"litex.build.generic_platform.Pins",
"litex.soc.integration.builder.builder_argdict",
"litex.soc.integration.builder.Builder",
"litex.soc.integration.builder.builder_args",
"litex.build.sim.SimPlatform.__init__",
"... | [((1767, 1792), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (1790, 1792), False, 'import argparse\n'), ((1797, 1817), 'litex.soc.integration.builder.builder_args', 'builder_args', (['parser'], {}), '(parser)\n', (1809, 1817), False, 'from litex.soc.integration.builder import builder_args, bu... |
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
# DDR3 init and test for a7ddrphy design
# use arty_ddr3 design with this script to
# find working bitslip/delay configuration
dfii_control_sel = 0x01
dfii_control_cke = 0x02
dfii_control_odt = 0x04
dfii_control_reset_n = 0x08
... | [
"litex.RemoteClient"
] | [((489, 514), 'litex.RemoteClient', 'RemoteClient', ([], {'debug': '(False)'}), '(debug=False)\n', (501, 514), False, 'from litex import RemoteClient\n'), ((741, 756), 'time.sleep', 'time.sleep', (['(0.1)'], {}), '(0.1)\n', (751, 756), False, 'import time\n'), ((947, 962), 'time.sleep', 'time.sleep', (['(0.1)'], {}), '... |
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from bft import Bft
from interface_wrapper import InterfaceWrapper
from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface
from litex.soc.interconnect.stream import (ClockDomainCrossing, Converter,
... | [
"litex.soc.interconnect.axi.AXILiteInterface"
] | [((3826, 3901), 'litex.soc.interconnect.axi.AXILiteInterface', 'AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(5)', 'clock_domain': 'clock_domain'}), '(data_width=32, address_width=5, clock_domain=clock_domain)\n', (3842, 3901), False, 'from litex.soc.interconnect.axi import AXILiteInterface, AXIStre... |
from migen.genlib.io import CRG
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores import gpio, uart
class BaseSoC(SoCCore):
csr_map = {
"gpio_led": 14,
}
csr_map.update(SoCCore.csr_map)
def __init__(self, platform, cpu, sim: bool, **kwargs):
sys_clk_freq = int(1e... | [
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.soc.cores.uart.UART"
] | [((437, 502), 'litex.soc.integration.soc_core.SoCCore.__init__', 'SoCCore.__init__', (['self', 'platform'], {'clk_freq': 'sys_clk_freq'}), '(self, platform, clk_freq=sys_clk_freq, **kwargs)\n', (453, 502), False, 'from litex.soc.integration.soc_core import SoCCore\n'), ((920, 1030), 'litex.soc.cores.uart.UART', 'uart.U... |
from migen import *
import nmigen
from nmigen.hdl.rec import DIR_FANIN, DIR_FANOUT, DIR_NONE
from luna.gateware.stream import StreamInterface
from ..nmigen import cmsis_dap
from litex.soc.interconnect.stream import Endpoint
from litex.build.io import SDRInput, SDROutput, SDRTristate
class CMSIS_DAP(Module):
d... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((376, 399), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (384, 399), False, 'from litex.soc.interconnect.stream import Endpoint\n'), ((420, 443), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (428, 443), False... |
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2015 <NAME> <<EMAIL>>
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018-2017 Tim 'mithro' Ansell <<EMAIL>>
# Copyright (c) 2019 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex import get_... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.get_data_mod"
] | [((2532, 2552), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2550, 2552), False, 'from litex.soc.interconnect import wishbone\n'), ((2588, 2608), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2606, 2608), False, 'from litex.soc.interconnec... |
# Support for Digilent Nexys Video board
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.uart import *
from litedram.modul... | [
"litex.soc.integration.soc_core.mem_decoder"
] | [((3210, 3259), 'targets.utils.csr_map_update', 'csr_map_update', (['SoCSDRAM.csr_map', 'csr_peripherals'], {}), '(SoCSDRAM.csr_map, csr_peripherals)\n', (3224, 3259), False, 'from targets.utils import csr_map_update, period_ns\n'), ((4533, 4577), 'gateware.info.Info', 'info.Info', (['platform', 'self.__class__.__name_... |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import os
import argparse
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import colorlight_5a_75b
from litex.soc.cor... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((5286, 5364), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""pulsegen test using LiteX and colorlite"""'}), "(description='pulsegen test using LiteX and colorlite')\n", (5309, 5364), False, 'import argparse\n'), ((2273, 2315), 'litex_boards.platforms.colorlight_5a_75b.Platform', 'color... |
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("E3"), IOStandard... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((1042, 1127), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35ticsg324-1L"""', '_io', '[]'], {'toolchain': 'toolchain'}), "(self, 'xc7a35ticsg324-1L', _io, [], toolchain=toolchain\n )\n", (1065, 1127), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1580, 1... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""LiteDRAM BankMachine (Rows/Columns management)."""
import math
from migen import *
from litex.soc.interconnect import stream
from litedram.common import *... | [
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.Buffer"
] | [((3816, 3921), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (['cmd_buffer_layout', 'settings.cmd_buffer_depth'], {'buffered': 'settings.cmd_buffer_buffered'}), '(cmd_buffer_layout, settings.cmd_buffer_depth, buffered=\n settings.cmd_buffer_buffered)\n', (3831, 3921), False, 'from litex.soc.interconn... |
# This file is Copyright (c) 2018-2020 <NAME> <<EMAIL>>
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
# License: BSD
from migen import *
from litex.soc.interconnect import stream
from litedram.common import LiteDRAMNativePort
from litedram.frontend import dma
# Helpers ------------------------------... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((2062, 2101), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (2077, 2101), False, 'from litex.soc.interconnect import stream\n'), ((2160, 2210), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'dma.LiteDRAMDMAWriter', (['port'], {'fifo_depth': '... |
# This file is Copyright (c) 2014 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 Tim 'mithro' Ansell <<EMAIL>>
# License: BSD
from migen import *
from migen.genlib.record import Record
from migen.genlib.cdc i... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.cores.usb_fifo.FT245PHYSynchronous",
"litex.soc.interconnect.wishbonebridge.WishboneStreamingBridge.__init__",
"litex.soc.cores.usb_fifo.FT245PHYAsynchronous",
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((8287, 8317), 'migen.genlib.record.Record', 'Record', (["[('tx', 1), ('rx', 1)]"], {}), "([('tx', 1), ('rx', 1)])\n", (8293, 8317), False, 'from migen.genlib.record import Record\n'), ((719, 749), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (734, 749), Fa... |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
import argparse
from migen import *
from litex.build.generic_platform import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((4076, 4146), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX standalone core generator"""'}), "(description='LiteX standalone core generator')\n", (4099, 4146), False, 'import argparse\n'), ((2974, 3030), 'valentyusb.usbcore.io.IoBuf', 'usbio.IoBuf', (['usb_pads.d_p', 'usb_pads.d... |
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