code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
import os
from distutils.dir_util import copy_tree
from litex.build import tools
from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header
def copy_litepcie_software(dst):
src = os.path.abspath(os.path.dirname(__file__))
copy_tree(src, dst)
def generate_litepcie_software_heade... | [
"litex.soc.integration.export.get_mem_header",
"litex.soc.integration.export.get_csr_header",
"litex.soc.integration.export.get_soc_header"
] | [((263, 282), 'distutils.dir_util.copy_tree', 'copy_tree', (['src', 'dst'], {}), '(src, dst)\n', (272, 282), False, 'from distutils.dir_util import copy_tree\n'), ((351, 426), 'litex.soc.integration.export.get_csr_header', 'get_csr_header', (['soc.csr_regions', 'soc.constants'], {'with_access_functions': '(False)'}), '... |
from migen import *
from litex.soc.interconnect.stream import Endpoint, Pipeline, Converter, Cast, CombinatorialActor
class Output(Module):
def __init__(self):
self.sink = sink = Endpoint([('data', 1)])
self.out = out = Signal()
self.submodules.fsm = fsm = FSM()
data = Signal()
... | [
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.Cast",
"litex.soc.interconnect.stream.Converter"
] | [((193, 216), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 1)]"], {}), "([('data', 1)])\n", (201, 216), False, 'from litex.soc.interconnect.stream import Endpoint, Pipeline, Converter, Cast, CombinatorialActor\n'), ((1884, 1924), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('r', 1), ... |
#!/usr/bin/env python3
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import nfcard
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import colo... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.clock.USPMMCM",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc_core.colorer",
"litex.soc.interconnect.axi.AXILiteInterface",
"litex.soc.cores.clock.USIDELAYCTRL",
... | [((10346, 10454), 'rowhammer_tester.targets.common.ArgumentParser', 'common.ArgumentParser', ([], {'description': '"""LiteX SoC on NFCard"""', 'sys_clk_freq': '"""125e6"""', 'module': '"""MTA16ATF2G64HZ"""'}), "(description='LiteX SoC on NFCard', sys_clk_freq=\n '125e6', module='MTA16ATF2G64HZ')\n", (10367, 10454), ... |
#!/usr/bin/env python3
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import arty
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform):
s... | [
"litex.build.generic_platform.IOStandard",
"litex.build.generic_platform.Pins"
] | [((4683, 4733), 'litex_boards.platforms.arty.Platform', 'arty.Platform', ([], {'variant': '"""a7-35"""', 'toolchain': '"""vivado"""'}), "(variant='a7-35', toolchain='vivado')\n", (4696, 4733), False, 'from litex_boards.platforms import arty\n'), ((565, 608), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetS... |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
import sys
wb = RemoteClient(debug=True)
wb.open()
wb.regs.j2_pins_oe.write(int(sys.argv[1], 0))
print("0x{:08x}".format(wb.regs.j2_pins_oe.read()))
wb.regs.j2_pins_out.write(int(sys.argv[2], 0))
print("0x{:08x}".format(wb.regs.j2_pins_out.read... | [
"litex.tools.litex_client.RemoteClient"
] | [((90, 114), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'debug': '(True)'}), '(debug=True)\n', (102, 114), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
class DMARecorder:
def __init__(self, name):
self._start = getattr(wb.regs, name + "_start")
self._done = getattr(wb.regs, name + "_done")
self._base = getattr(wb.regs, name + "_bas... | [
"litex.RemoteClient"
] | [((73, 87), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (85, 87), False, 'from litex import RemoteClient\n')] |
import logging
from migen import *
from litex.soc.cores.dma import WishboneDMAReader
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
from gateware.jtframe.sound.pole import Pole
class CenJT6295(Module):
def __init__(self, tuning_word):
... | [
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.cores.dma.WishboneDMAReader",
"litex.soc.interconnect.csr.CSRStorage"
] | [((957, 979), 'litex.soc.cores.dma.WishboneDMAReader', 'WishboneDMAReader', (['bus'], {}), '(bus)\n', (974, 979), False, 'from litex.soc.cores.dma import WishboneDMAReader\n'), ((2193, 2243), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['self.bus.adr_width'], {'reset': 'default_base'}), '(self.bus.adr_width... |
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import GenericPlatform
from litex.build.microsemi import common, libero_soc
class MicrosemiPlatform(GenericPlatform):
bitstream_ext = ".bit"
def __init__(self, *args, toolchain="libero_soc_polarfire", **kwarg... | [
"litex.build.microsemi.libero_soc.MicrosemiLiberoSoCPolarfireToolchain",
"litex.build.generic_platform.GenericPlatform.__init__",
"litex.build.generic_platform.GenericPlatform.get_verilog"
] | [((332, 379), 'litex.build.generic_platform.GenericPlatform.__init__', 'GenericPlatform.__init__', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (356, 379), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((766, 888), 'litex.build.generic_platform.GenericPlatform.get_verilog', 'GenericPlat... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Cam Link 4K PCB and IOs have been documented by @GregDavill and @ApertusOSCinema:
# https://wiki.apertus.org/index.php/Elgato_CAM_LINK_4K
# The FX3 exploration tool (and FPGA loader) has been d... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((2420, 2512), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8BG381C"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'LFE5U-25F-8BG381C', _io, toolchain=\n toolchain, **kwargs)\n", (2444, 2512), False, 'from litex.build.lattice import LatticePlatform\n'), ((25... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("G13"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("D14"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("T14"), IOStandard("LVCMOS33")),
# K17 - QSPI_D... | [
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((2975, 3066), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7s50csga324-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7s50csga324-1', _io, _connectors,\n toolchain=toolchain)\n", (2998, 3066), False, 'from litex.build.xilinx import XilinxPlatform, ... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Avalon support for LiteX"""
from migen import *
from litex.soc.interconnect import stream
# Avalon-ST to/from native LiteX's stream ----------------------------------------------------------
# In... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((953, 976), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (968, 976), False, 'from litex.soc.interconnect import stream\n'), ((1008, 1031), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (1023, 1031), False, 'from litex.soc.i... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Work-In-Progress...
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs -----------------------------------------... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((1741, 1815), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k70t-fbg676-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7k70t-fbg676-1', _io, toolchain='vivado')\n", (1764, 1815), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1865, 1922), 'litex.bui... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs --------------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((821, 912), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z010clg225-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7z010clg225-1', _io, _connectors,\n toolchain=toolchain)\n", (844, 912), False, 'from litex.build.xilinx import XilinxPlatform, Viva... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs ------------------------------------... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.LatticeProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((1594, 1654), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LCMXO3L-6900C-5BG256C"""', '_io'], {}), "(self, 'LCMXO3L-6900C-5BG256C', _io)\n", (1618, 1654), False, 'from litex.build.lattice import LatticePlatform\n'), ((3576, 3608), 'litex.build.lattice.programmer.LatticePro... |
#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
import os
import sys
import json
from litex.build import tools
def main():
if len(sys.argv) < 2:
print("usage: litex_read_verilog verilog_file [module]")
exit(1)
verilog_file = sys.argv[1]
json... | [
"litex.build.tools.write_to_file"
] | [((592, 638), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['"""yosys_v2j.ys"""', 'yosys_v2j'], {}), "('yosys_v2j.ys', yosys_v2j)\n", (611, 638), False, 'from litex.build import tools\n'), ((643, 677), 'os.system', 'os.system', (['"""yosys -q yosys_v2j.ys"""'], {}), "('yosys -q yosys_v2j.ys')\n", (652, 67... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("K12"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("K13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("R10"), IOStandard("LVCMOS33")),
("user_led", 3, ... | [
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((3723, 3798), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-ftg256-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a35t-ftg256-1', _io, toolchain=toolchain)\n", (3746, 3798), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'),... |
# -*- coding: utf-8 -*-
# Copyright (C) 2022 Antmicro
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# S... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((856, 876), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (874, 876), False, 'from litex.soc.interconnect import wishbone\n'), ((1405, 1441), 'migen.genlib.fifo.SyncFIFO', 'SyncFIFO', (['bus.data_width', 'fifo_depth'], {}), '(bus.data_width, fifo_depth)\n', (1413, 1441), False, ... |
#
# This file is part of LiteSPI
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import stream
from litespi.common import *
class LiteSPIPHYModel(Module):
"""LiteSPI PHY simulat... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((887, 923), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy_data_layout'], {}), '(spi_phy_data_layout)\n', (902, 923), False, 'from litex.soc.interconnect import stream\n'), ((955, 990), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy_ctl_layout'], {}), '(spi_phy_ctl_la... |
#!/usr/bin/env python3
# This script generates dut.v file for testing TinyFPGA Bootloader
# Disable pylint's E1101, which breaks completely on migen
# pylint:disable=E1101
from migen import Module, Signal, Instance, ClockDomain, If
from migen.fhdl.specials import TSTriple
from migen.fhdl.structure import ResetSignal
... | [
"litex.build.generic_platform.Pins",
"litex.build.sim.platform.SimPlatform.__init__",
"litex.soc.integration.builder.Builder",
"litex.soc.integration.soc_core.SoCCore.__init__"
] | [((5337, 5422), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build test file for dummy or eptri module"""'}), "(description='Build test file for dummy or eptri module'\n )\n", (5360, 5422), False, 'import argparse\n'), ((5967, 6044), 'litex.soc.integration.builder.Builder', 'Builder... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ------------------------------------------------... | [
"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.programmer.USBBlaster"
] | [((3082, 3124), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', 'device', '_io'], {}), '(self, device, _io)\n', (3105, 3124), False, 'from litex.build.altera import AlteraPlatform\n'), ((3471, 3483), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (3481, 34... |
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
class BIST:
def __init__(self, tx_name, rx_name):
self._tx_enable = getattr(wb.regs, tx_name + "_enable")
self._rx_enable = getattr(wb.regs, rx_name + "_enable")
self._rx_err... | [
"litex.RemoteClient"
] | [((85, 99), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (97, 99), False, 'from litex import RemoteClient\n'), ((491, 506), 'time.sleep', 'time.sleep', (['(0.1)'], {}), '(0.1)\n', (501, 506), False, 'import time\n'), ((548, 561), 'time.sleep', 'time.sleep', (['(1)'], {}), '(1)\n', (558, 561), False, 'import ... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.gen.sim import run_simulation
from litex.soc.interconnect import wishbone
from litedram.frontend.wish... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.gen.sim.run_simulation"
] | [((1426, 1477), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 'generators'], {'vcd_name': '"""sim.vcd"""'}), "(dut, generators, vcd_name='sim.vcd')\n", (1440, 1477), False, 'from litex.gen.sim import run_simulation\n'), ((1675, 1721), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], ... |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by a... | [
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((1408, 1446), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado.vivado_build_argdict', (['self.args'], {}), '(self.args)\n', (1435, 1446), False, 'from litex.build.xilinx import vivado\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = [... | [
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((17793, 17851), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build DiVA Gateware"""'}), "(description='Build DiVA Gateware')\n", (17816, 17851), False, 'import argparse\n'), ((18269, 18339), 'os.path.join', 'os.path.join', (['builder.output_dir', '"""software"""', '"""DiVA-fw"""', '"... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import terasic_sockit
from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.soc_co... | [
"litex.soc.cores.clock.CycloneVPLL",
"litex.soc.cores.video.VideoVGAPHY"
] | [((6562, 6632), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on the Terasic SoCKit"""'}), "(description='LiteX SoC on the Terasic SoCKit')\n", (6585, 6632), False, 'import argparse\n'), ((2068, 2166), 'litedram.modules._TechnologyTimings', '_TechnologyTimings', ([], {'tREFI':... |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from migen.genlib.cdc import MultiReg
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.s... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream_sim.PacketLogger",
"litex.soc.interconnect.stream_sim.PacketStreamer",
"litex.soc.interconnect.stream_sim.Randomizer",
"litex.soc.interconnect.stream_sim.Packet",
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.cs... | [((4491, 4505), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(32)'], {}), '(32)\n', (4501, 4505), False, 'from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage\n'), ((6015, 6028), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {}), '(8)\n', (6025, 6028), False, 'from ... |
import random
from operator import or_
from functools import reduce
from collections import defaultdict
from sdram_init import *
# DRAM commands ----------------------------------
def sdram_software_control(wb):
wb.regs.sdram_dfii_control.write(dfii_control_cke|dfii_control_odt|dfii_control_reset_n)
def sdram_c... | [
"litex.RemoteClient"
] | [((1502, 1540), 'functools.reduce', 'reduce', (['or_', '(1 << m for m in modules)'], {}), '(or_, (1 << m for m in modules))\n', (1508, 1540), False, 'from functools import reduce\n'), ((3272, 3291), 'random.Random', 'random.Random', (['seed'], {}), '(seed)\n', (3285, 3291), False, 'import random\n'), ((6120, 6137), 'co... |
#!/usr/bin/env python3
import os
import subprocess
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.cores.spi_flash import SpiFlash
from litex.soc.cores.gpio import GPIOOut, GPIOIn
from litex.soc.cores.spi import SPIMaster
from lit... | [
"litex.soc.cores.spi.SPIMaster",
"litex.soc.integration.soc_core.mem_decoder",
"litex.soc.cores.icap.ICAPBitstream",
"litex.soc.interconnect.wishbone.SRAM",
"litex.soc.cores.spi_flash.SpiFlash",
"litex.soc.cores.xadc.XADC"
] | [((3060, 3080), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(16384)'], {}), '(16384)\n', (3073, 3080), False, 'from litex.soc.interconnect import wishbone\n'), ((3369, 3465), 'litex.soc.cores.spi_flash.SpiFlash', 'SpiFlash', (['spiflash_pads'], {'dummy': '(11)', 'div': '(2)', 'with_bitbang': '(True)', '... |
import nmigen
from litex.soc.interconnect.stream import Endpoint
from .. import dfu
class DFUHandler:
def __init__(self, if_num, areas):
self.source = Endpoint([('data', 8), ('addr', 24)])
self.handler = dfu.DFUHandler(if_num, areas)
def wrap(self, wrapper):
wrapper.connect(self... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((166, 203), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 8), ('addr', 24)]"], {}), "([('data', 8), ('addr', 24)])\n", (174, 203), False, 'from litex.soc.interconnect.stream import Endpoint\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((1921, 1941), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1939, 1941), False, 'from litex.soc.interconnect import wishbone\n'), ((4386, 4397), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (4395, 4397), False, 'import os\n'), ((4462, 4486), 'os.path.exists', 'os.path.exists', (... |
#!/usr/bin/env python3
import time
import random
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
# test buttons
print("Testing Buttons/Switches...")
while True:
buttons = wb.regs.buttons_in.read()
switches = wb.regs.switches_in.read()
print("buttons: {:02x} / switches: {:02x}".format... | [
"litex.RemoteClient"
] | [((88, 102), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (100, 102), False, 'from litex import RemoteClient\n'), ((345, 360), 'time.sleep', 'time.sleep', (['(0.5)'], {}), '(0.5)\n', (355, 360), False, 'import time\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2019 Antmicro <www.antmicro.com>
# Copyright (c) 2019 Tim 'mithro' Ansell <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen impo... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.get_data_mod"
] | [((2543, 2563), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2561, 2563), False, 'from litex.soc.interconnect import wishbone\n'), ((6504, 6535), 'litex.get_data_mod', 'get_data_mod', (['"""cpu"""', '"""picorv32"""'], {}), "('cpu', 'picorv32')\n", (6516, 6535), False, 'from lite... |
import sys
import struct
import os.path
import argparse
from migen import *
from litex.build.generic_platform import Pins, Subsignal, IOStandard
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from gateware import cas
from gateware import spi_flash
from targets.utils import ... | [
"litex.build.generic_platform.Pins",
"litex.build.generic_platform.IOStandard"
] | [((557, 579), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (567, 579), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard\n'), ((776, 827), 'targets.utils.dict_set_max', 'dict_set_max', (['kwargs', '"""integrated_sram_size"""', '(10240)']... |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# FIXME: Cleanup/Move.
import os
from migen import *
from migen.genlib.cdc import *
from migen import ClockDomain
from litex.build.generic_platform import *
from litex.soc.interconnect import axi
from li... | [
"litex.soc.interconnect.axi.AXIInterface"
] | [((785, 847), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': '(256)', 'address_width': '(32)', 'id_width': '(8)'}), '(data_width=256, address_width=32, id_width=8)\n', (801, 847), False, 'from litex.soc.interconnect import axi\n'), ((913, 975), 'litex.soc.interconnect.axi.AXIInterfac... |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk48", 0, Pins("M1"), IOStandard("LVCMOS18"... | [
"litex.build.lattice.LatticePlatform.__init__"
] | [((4033, 4137), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8MG285C"""', '_io', '_connectors'], {'toolchain': '"""trellis"""'}), "(self, 'LFE5U-25F-8MG285C', _io, _connectors,\n toolchain='trellis', **kwargs)\n", (4057, 4137), False, 'from litex.build.lattice i... |
# Copyright 2020 <NAME> <<EMAIL>>
# Adapted from code by <NAME> <<EMAIL>> https://github.com/smunaut/ice40-playground/blob/icepick/projects/icepick_test/rtl/sense.v
from migen import *
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
from litex.soc.doc.module import ModuleDoc
from lit... | [
"litex.build.io.DDRInput",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr.CSRStatus"
] | [((2185, 2232), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(24)'], {'description': '"""Conversion result."""'}), "(24, description='Conversion result.')\n", (2194, 2232), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((2995, 3045), 'litex.build.io.DDRInput', '... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import argparse
from migen import *
from litex.build.generic_platform import *... | [
"litex.build.sim.gtkwave.GTKWSave",
"litex.build.sim.gtkwave.wishbone_colorer",
"litex.build.sim.config.SimConfig",
"litex.build.sim.verilator.verilator_build_argdict",
"litex.build.sim.gtkwave.dfi_in_phase_colorer",
"litex.build.sim.SimPlatform.__init__",
"litex.build.sim.gtkwave.wishbone_sorter",
"l... | [((15030, 15058), 'litex.build.sim.verilator.verilator_build_args', 'verilator_build_args', (['parser'], {}), '(parser)\n', (15050, 15058), False, 'from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict\n'), ((17562, 17629), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'descr... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ---------------------------------------------------... | [
"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster"
] | [((1784, 1854), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE6E22C8"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'EP4CE6E22C8', _io, toolchain=toolchain)\n", (1807, 1854), False, 'from litex.build.altera import AlteraPlatform\n'), ((1904, 1916), 'litex.build.altera.pr... |
from migen import *
from targets.netv2.base import SoC as BaseSoC
from litex.soc.interconnect import wishbone
from litex.soc.cores.freqmeter import FreqMeter
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepci... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.freqmeter.FreqMeter"
] | [((2088, 2136), 'targets.utils.csr_map_update', 'csr_map_update', (['BaseSoC.csr_map', 'csr_peripherals'], {}), '(BaseSoC.csr_map, csr_peripherals)\n', (2102, 2136), False, 'from targets.utils import period_ns, csr_map_update\n'), ((587, 607), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}),... |
from migen import *
from litespi.common import spi_phy_ctl_layout, spi_phy_data_layout, USER
from litex.soc.interconnect.stream import Endpoint
PROGRAM_SIZE = 256
#ERASE_CMD = 0x20
#ERASE_SIZE = 4096
ERASE_CMD = 0xd8
ERASE_SIZE = 65536
class FlashWriter(Module):
def __init__(self):
# PHY interface
... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((356, 384), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (['spi_phy_ctl_layout'], {}), '(spi_phy_ctl_layout)\n', (364, 384), False, 'from litex.soc.interconnect.stream import Endpoint\n'), ((420, 449), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (['spi_phy_data_layout'], {}), '(spi_phy_data_layout)... |
#!/usr/bin/env python3
#
# This file is part of LiteSPI
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
from litex.build.lattice.trel... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((6036, 6106), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX LiteSPI SoC on Colorlight"""'}), "(description='LiteX LiteSPI SoC on Colorlight')\n", (6059, 6106), False, 'import argparse\n'), ((6322, 6342), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}... |
# This file is Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016 <NAME> <<EMAIL>>
# License: BSD
from functools import reduce
from operator import and_
from migen import *
from migen.genlib.cdc import MultiReg, ElasticBuffer
from migen.genlib.misc import WaitTimer
from migen.genlib.io import ... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((971, 1015), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (986, 1015), False, 'from litex.soc.interconnect import stream\n'), ((2586, 2630), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl',... |
#
# This file is part of USB3-PIPE project.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from functools import reduce
from operator import xor
from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.common import COM
# Scrambler Unit (Appendix B) -------... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((4422, 4466), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (4437, 4466), False, 'from litex.soc.interconnect import stream\n'), ((4498, 4542), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl... |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2017-2018 <NAME> <<EMAIL>>
# License: BSD
import os
import subprocess
from litex.build.generic_programmer import GenericProgrammer
from litex.build import tools
class LatticeProgrammer(GenericProgrammer):
needs_bitreverse = Fal... | [
"litex.build.generic_programmer.GenericProgrammer.__init__",
"litex.build.tools.write_to_file"
] | [((594, 636), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['xcf_file', 'xcf_content'], {}), '(xcf_file, xcf_content)\n', (613, 636), False, 'from litex.build import tools\n'), ((645, 693), 'subprocess.call', 'subprocess.call', (["['pgrcmd', '-infile', xcf_file]"], {}), "(['pgrcmd', '-infile', xcf_file])\... |
#!/usr/bin/env python3
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# Trigger a reset of the SoC
#wb.regs.ctrl_reset.write(1)
# Dump all CSR registers of the SoC
for name, reg in wb.regs.__dict__.items():
print("0x{:08x} : 0x{:08x} {}".format(reg.addr, reg.read(), name))
wb.close()
| [
"litex.RemoteClient"
] | [((61, 75), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (73, 75), False, 'from litex import RemoteClient\n')] |
#!/usr/bin/env python3
import argparse
import os
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from liteeth.phy.model import... | [
"litex.build.sim.config.SimConfig",
"litex.build.sim.SimPlatform.__init__"
] | [((3115, 3126), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {}), '()\n', (3124, 3126), False, 'from litex.build.sim.config import SimConfig\n'), ((1479, 1517), 'litex.build.sim.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""SIM"""', '_io'], {}), "(self, 'SIM', _io)\n", (1499, 1517), False, 'from... |
#!/usr/bin/env python3
import sys
import os
cmd, prog = sys.argv[:2]
if len(sys.argv) == 3:
fname = sys.argv[2]
else:
p = os.environ['PLATFORM']
t = os.environ['TARGET']
c = os.environ['CPU']
fname = "build/{p}_{t}_{c}/gateware/top.bit".format(
p=p, t=t, c=c)
if prog == 'ise':
from l... | [
"litex.build.xilinx.iMPACT",
"litex.build.xilinx.VivadoProgrammer"
] | [((363, 371), 'litex.build.xilinx.iMPACT', 'iMPACT', ([], {}), '()\n', (369, 371), False, 'from litex.build.xilinx import iMPACT\n'), ((551, 572), 'os.path.exists', 'os.path.exists', (['fname'], {}), '(fname)\n', (565, 572), False, 'import os\n'), ((458, 476), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ... |
import os
from migen import *
from litex.soc.interconnect import csr_bus, wishbone
class MCS51(Module):
"""
8051 CPU core. This is a wrapper around Verilog turbo8051 model.
"""
def __init__(self, platform, ea=Constant(0)):
self.platform = platform
self.interrupt = Signal(2)
... | [
"litex.soc.interconnect.csr_bus.Interface",
"litex.soc.interconnect.wishbone.Interface"
] | [((336, 399), 'litex.soc.interconnect.csr_bus.Interface', 'csr_bus.Interface', ([], {'data_width': '(32)', 'address_width': '(16)', 'alignment': '(8)'}), '(data_width=32, address_width=16, alignment=8)\n', (353, 399), False, 'from litex.soc.interconnect import csr_bus, wishbone\n'), ((424, 470), 'litex.soc.interconnect... |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2017 <NAME> <<EMAIL>>
# License: BSD
from migen.fhdl.structure import Signal
from migen.genlib.record import Record
from litex.build.generic_platform import GenericPlatform
from litex.build.sim import common, verilator
class SimPla... | [
"litex.build.generic_platform.GenericPlatform.__init__",
"litex.build.generic_platform.GenericPlatform.request",
"litex.build.sim.verilator.SimVerilatorToolchain",
"litex.build.generic_platform.GenericPlatform.get_verilog"
] | [((416, 463), 'litex.build.generic_platform.GenericPlatform.__init__', 'GenericPlatform.__init__', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (440, 463), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((799, 849), 'litex.build.generic_platform.GenericPlatform.request', 'GenericPlatform... |
#!/usr/bin/env python3
import sys
import os
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import arty
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
fr... | [
"litex.gen.genlib.resetsync.AsyncResetSynchronizer",
"litex.soc.cores.xadc.XADC",
"litex.soc.cores.dna.DNA",
"litex.boards.platforms.arty.Platform"
] | [((9017, 9032), 'litex.boards.platforms.arty.Platform', 'arty.Platform', ([], {}), '()\n', (9030, 9032), False, 'from litex.boards.platforms import arty\n'), ((3977, 3986), 'litex.soc.cores.dna.DNA', 'dna.DNA', ([], {}), '()\n', (3984, 3986), False, 'from litex.soc.cores import dna, xadc\n'), ((4018, 4029), 'litex.soc.... |
#!/usr/bin/env python3
from migen import *
from migen.genlib.cdc import MultiReg
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from tick import *
from display import *
from bcd import *
from core import *
# IOs --------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((1114, 1189), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (1137, 1189), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1548, 1577), 'migen.g... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2749, 2824), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k420tl-ffg901"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7k420tl-ffg901', _io, toolchain=toolchain)\n", (2772, 2824), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((2874, 2... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs --------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3901, 3992), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020-clg484-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7z020-clg484-1', _io, _connectors,\n toolchain='vivado')\n", (3924, 3992), False, 'from litex.build.xilinx import XilinxPlatfo... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# https://www.crowdsupply.com/fairwaves/xtrx
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((1151, 1224), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50tcpg236-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a50tcpg236-2', _io, toolchain='vivado')\n", (1174, 1224), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1757, 1814), 'litex.build... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ---------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3503, 3594), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020-clg400-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7z020-clg400-1', _io, _connectors,\n toolchain='vivado')\n", (3526, 3594), False, 'from litex.build.xilinx import XilinxPlatfo... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")),
("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("B8"), IOStandard("LVCMOS33"),
Misc("SLEW=FAS... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((6125, 6192), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx9-csg324-2"""', '_io', '_connectors'], {}), "(self, 'xc6slx9-csg324-2', _io, _connectors)\n", (6148, 6192), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import mini_4k
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from l... | [
"litex.build.generic_platform.Pins",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((6578, 6654), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC Blackmagic Decklink Mini 4K"""'}), "(description='LiteX SoC Blackmagic Decklink Mini 4K')\n", (6601, 6654), False, 'import argparse\n'), ((7663, 7688), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_ar... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ---------------------------------------------------... | [
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.AlteraPlatform.do_finalize"
] | [((1545, 1595), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""5CSEMA5F31C6"""', '_io'], {}), "(self, '5CSEMA5F31C6', _io)\n", (1568, 1595), False, 'from litex.build.altera import AlteraPlatform\n'), ((1645, 1657), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}... |
#
# This file is part of LiteX-Boards.
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import TinyProgProgrammer
# IOs ----... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.TinyProgProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((2376, 2472), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-hx8k-tq144:4k"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'ice40-hx8k-tq144:4k', _io, _connectors,\n toolchain=toolchain)\n", (2400, 2472), False, 'from litex.build.lattice import Latt... |
#!/usr/bin/env python3
import argparse
from migen import *
from migen.genlib.io import CRG
from litex.build.generic_platform import IOStandard, Subsignal, Pins
from litex_boards.platforms import colorlight_5a_75b
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.integration.soc_... | [
"litex.build.lattice.trellis.trellis_args",
"litex.build.lattice.trellis.trellis_argdict"
] | [((1111, 1180), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Colorlight 5A-75B"""'}), "(description='LiteX SoC on Colorlight 5A-75B')\n", (1134, 1180), False, 'import argparse\n'), ((1465, 1485), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}),... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
("clk50", 0, Pins("A10"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("T9"), IOStandard("LVCMOS33")), # D1
("user_led", 1, Pins("R9"), IOStandard("LVCMOS33")), # D3
("user_sw", 0, Pins("T8"), IOStandard... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2428, 2483), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx16-ftg256-2"""', '_io'], {}), "(self, 'xc6slx16-ftg256-2', _io)\n", (2451, 2483), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
import random
from utils import *
from read_level import read_level, default_arty_settings
def _compare(val, ref, fmt, nbytes=4):
assert fmt in ["bin", "hex"]
if fmt == "hex":
print("0x{:0{n}x} {cmp} 0x{:0{n}x}".format(
val, ref, n=nbytes*2, cmp="==" if val == ref e... | [
"litex.RemoteClient"
] | [((708, 727), 'random.Random', 'random.Random', (['seed'], {}), '(seed)\n', (721, 727), False, 'import random\n'), ((1419, 1438), 'random.Random', 'random.Random', (['seed'], {}), '(seed)\n', (1432, 1438), False, 'import random\n'), ((2995, 3009), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (3007, 3009), Fa... |
#!/usr/bin/env python3
import os
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
# Info
# #########################
# - Completer le questionnaire (en commentant les réponses avec #)
# - Completer le code manquant (indiqué par TODO). (Ne pas oublier la dé... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2181, 2256), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (2204, 2256), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import orang... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((8240, 8301), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on OrangeCrab"""'}), "(description='LiteX SoC on OrangeCrab')\n", (8262, 8301), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((9328, 9348), 'litex.build.lattice.t... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import timeline
from migen.genlib.cdc import PulseSynchronizer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
# Xilinx 7... | [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((1252, 1284), 'migen.genlib.cdc.PulseSynchronizer', 'PulseSynchronizer', (['"""sys"""', '"""icap"""'], {}), "('sys', 'icap')\n", (1269, 1284), False, 'from migen.genlib.cdc import PulseSynchronizer\n'), ((5541, 5585), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', 32)]", 'fifo_depth'], {}... |
from itertools import product, count
import itertools
from sys import stdout
import time
import json
import ctypes
from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('--samples'... | [
"litex.tools.litex_client.RemoteClient"
] | [((263, 288), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (286, 288), False, 'import argparse\n'), ((501, 537), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (513, 537), False, 'from litex.tools.litex_client im... |
#
# This file is part of LiteHyperBus
#
# Copyright (c) 2019-2022 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import timeline
from litex.build.io import DifferentialOutput
from litex.so... | [
"litex.build.io.DifferentialOutput",
"litex.soc.interconnect.wishbone.Interface"
] | [((844, 864), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (862, 864), False, 'from litex.soc.interconnect import wishbone\n'), ((1910, 1957), 'litex.build.io.DifferentialOutput', 'DifferentialOutput', (['clk', 'pads.clk_p', 'pads.clk_n'], {}), '(clk, pads.clk_p, pads.clk_n)\n', ... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2016 whitequark <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import signal
import os
import time
import serial
import threading
import multiprocessi... | [
"litex.build.openocd.OpenOCD",
"litex.RemoteClient"
] | [((18233, 18258), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (18256, 18258), False, 'import argparse\n'), ((2627, 2694), 'litex.RemoteClient', 'RemoteClient', ([], {'host': 'host', 'base_address': 'base_address', 'csr_csv': 'csr_csv'}), '(host=host, base_address=base_address, csr_csv=csr_cs... |
#!/usr/bin/env python3
import sys
import os
import argparse
import subprocess
import struct
import importlib
from migen.fhdl import verilog
from migen.fhdl.structure import _Fragment
from litex.build.tools import write_to_file
from litex.build.xilinx.common import *
from litex.soc.integration import cpu_interface
... | [
"litex.build.tools.write_to_file",
"litex.soc.integration.cpu_interface.get_csr_csv"
] | [((546, 591), 'importlib.import_module', 'importlib.import_module', (["(default + '.' + name)"], {}), "(default + '.' + name)\n", (569, 591), False, 'import importlib\n'), ((624, 1165), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'formatter_class': 'argparse.RawDescriptionHelpFormatter', 'description': ... |
#!/usr/bin/python3
from litex.build.tools import write_to_file
from litex.build.tools import replace_in_file
from litedram.gen import *
import subprocess
import os
import shutil
def make_new_dir(base, added):
r = os.path.join(base, added)
if os.path.exists(r):
shutil.rmtree(r)
os.mkdir(r)
retu... | [
"litex.build.tools.replace_in_file"
] | [((516, 549), 'os.path.join', 'os.path.join', (['base_dir', '"""gen-src"""'], {}), "(base_dir, 'gen-src')\n", (528, 549), False, 'import os\n'), ((219, 244), 'os.path.join', 'os.path.join', (['base', 'added'], {}), '(base, added)\n', (231, 244), False, 'import os\n'), ((252, 269), 'os.path.exists', 'os.path.exists', ([... |
#!/usr/bin/env python3
'''
---------------------
LiteX SoC on Marble
---------------------
with support for SO-DIMM DDR3, ethernet and UART.
To synthesize, add --build, to configure the FPGA over jtag, add --load.
-----------------
Example configs
-----------------
with ethernet and DDR3, default IP: 192.168.1.50/24... | [
"litex.soc.cores.bitbang.I2CMaster",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((5686, 5755), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on BerkeleyLab Marble"""'}), "(description='LiteX SoC on BerkeleyLab Marble')\n", (5708, 5755), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((2694, 2723), 'litex... |
#!/usr/bin/env python3
# This file is Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
import argparse
import sys
import socket
import time
import threading
from litex.tools.remote.etherbone import Etherbone... | [
"litex.tools.remote.comm_uart.CommUART",
"litex.tools.remote.comm_pcie.CommPCIe",
"litex.tools.remote.comm_usb.CommUSB",
"litex.tools.remote.comm_udp.CommUDP",
"litex.tools.remote.etherbone.EtherboneWrites",
"litex.tools.remote.etherbone.EtherbonePacket",
"litex.tools.remote.etherbone.EtherboneRecord"
] | [((3427, 3452), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (3450, 3452), False, 'import argparse\n'), ((958, 1007), 'socket.socket', 'socket.socket', (['socket.AF_INET', 'socket.SOCK_STREAM'], {}), '(socket.AF_INET, socket.SOCK_STREAM)\n', (971, 1007), False, 'import socket\n'), ((5487, 552... |
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import IceStormProgrammer
_io = [
("rgb_led", 0,
Subsignal("r", Pins("41")),
Subsignal("g", Pins("40")),
Subsignal("b", Pins("39")),
IOStandard("LVCMOS33")... | [
"litex.build.lattice.programmer.IceStormProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((4137, 4230), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-sg48', _io, _connectors,\n toolchain='icestorm')\n", (4161, 4230), False, 'from litex.build.lattice import Lattic... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import quicklogic_quickfeather
from litex.soc.integration.soc... | [
"litex.soc.integration.soc.SoCRegion"
] | [((3511, 3586), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on QuickLogic QuickFeather"""'}), "(description='LiteX SoC on QuickLogic QuickFeather')\n", (3534, 3586), False, 'import argparse\n'), ((1623, 1657), 'litex_boards.platforms.quicklogic_quickfeather.Platform', 'quick... |
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2014-2021 <NAME> <<EMAIL>>
# This file is Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import time
import logging
import datetime
from math import log2, ceil
... | [
"litex.soc.cores.identifier.Identifier",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.jtag.JTAGPHY",
"litex.soc.cores.cpu.CPUS.keys",
"litex.soc.interconnect.axi.AXI2Wishbone",
"litex.soc.cores.spi.SPIMaster",
"litex.soc.cores.video.ColorBarsPattern",
"litex.soc.interconnect.stream.Cl... | [((639, 678), 'logging.basicConfig', 'logging.basicConfig', ([], {'level': 'logging.INFO'}), '(level=logging.INFO)\n', (658, 678), False, 'import logging\n'), ((1889, 1919), 'logging.getLogger', 'logging.getLogger', (['"""SoCRegion"""'], {}), "('SoCRegion')\n", (1906, 1919), False, 'import logging\n'), ((4271, 4294), '... |
import argparse
import os
import sys
import threading
from litex.tools.litex_server import RemoteServer
from litex.tools.litex_client import RemoteClient
TOP_DIR=os.path.join(os.path.dirname(__file__), "..")
sys.path.append(TOP_DIR)
from make import get_args, get_testdir
class ServerProxy(threading.Thread):
d... | [
"litex.tools.remote.comm_uart.CommUART",
"litex.tools.remote.comm_pcie.CommPCIe",
"litex.tools.remote.comm_usb.CommUSB",
"litex.tools.remote.comm_udp.CommUDP"
] | [((212, 236), 'sys.path.append', 'sys.path.append', (['TOP_DIR'], {}), '(TOP_DIR)\n', (227, 236), False, 'import sys\n'), ((178, 203), 'os.path.dirname', 'os.path.dirname', (['__file__'], {}), '(__file__)\n', (193, 203), False, 'import os\n'), ((2486, 2527), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'... |
# This file is Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2017 <NAME> <<EMAIL>>
# License: BSD
import os
import sys
import subprocess
from migen.fhdl.structure import _Fragment
from litex.build import tools
from litex.build.generic_platform import *
sim_directory = os.path.abspath(os.pat... | [
"litex.build.tools.write_to_file"
] | [((358, 393), 'os.path.join', 'os.path.join', (['sim_directory', '"""core"""'], {}), "(sim_directory, 'core')\n", (370, 393), False, 'import os\n'), ((314, 339), 'os.path.dirname', 'os.path.dirname', (['__file__'], {}), '(__file__)\n', (329, 339), False, 'import os\n'), ((1063, 1107), 'litex.build.tools.write_to_file',... |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores import up5kspram
from litex.soc.integration import SoCCore
fr... | [
"litex.soc.integration.soc_core.soc_core_argdict",
"litex.soc.integration.builder.builder_argdict",
"litex.soc.integration.SoCCore.__init__",
"litex.soc.cores.up5kspram.Up5kSPRAM",
"litex.soc.integration.soc_core.soc_core_args",
"litex.soc.integration.builder.builder_args"
] | [((8489, 8509), 'os.path.splitext', 'os.path.splitext', (['fn'], {}), '(fn)\n', (8505, 8509), False, 'import os, shutil, subprocess\n'), ((8544, 8571), 'shutil.copyfile', 'shutil.copyfile', (['fn', 'fn_dfu'], {}), '(fn, fn_dfu)\n', (8559, 8571), False, 'import os, shutil, subprocess\n'), ((8576, 8668), 'subprocess.chec... |
#
# This file is part of LiteX-Boards.
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2022 Lone Dynamics Corporation <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Krote FPGA board: https://github.com/machdyne/krote
#
from litex.build.generic_platform import *
from... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((1700, 1793), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-hx8k-bg121"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'ice40-hx8k-bg121', _io, _connectors,\n toolchain=toolchain)\n", (1724, 1793), False, 'from litex.build.lattice import LatticePla... |
#!/usr/bin/env python3
# -*- coding: utf-8 -*-
# Copyright (C) 2022 Antmicro
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either ... | [
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.builder.Builder",
"litex.build.generic_platform.Pins",
"litex.build.sim.platform.SimPlatform.__init__"
] | [((5523, 5599), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'output_dir': 'output_dir', 'csr_csv': 'csr_csv', 'compile_software': '(False)'}), '(soc, output_dir=output_dir, csr_csv=csr_csv, compile_software=False)\n', (5530, 5599), False, 'from litex.soc.integration.builder import Builder\n'), ((5746... |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
from shutil import which
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.quicklog... | [
"litex.build.tools.write_to_file"
] | [((882, 927), 'litex.build.tools.write_to_file', 'tools.write_to_file', (["(build_name + '.pcf')", 'pcf'], {}), "(build_name + '.pcf', pcf)\n", (901, 927), False, 'from litex.build import tools\n'), ((1858, 1879), 'shutil.which', 'which', (['"""ql_symbiflow"""'], {}), "('ql_symbiflow')\n", (1863, 1879), False, 'from sh... |
#
# This file is part of LiteX-Boards.
# FPGA Board Info : http://www.e-elements.com/product/show/id/11.shtml
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((5476, 5569), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35ticsg324-1L"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7a35ticsg324-1L', _io, _connectors,\n toolchain=toolchain)\n", (5499, 5569), False, 'from litex.build.xilinx import XilinxPlatfo... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# Copyright (c) 2014-2015 <NAME> <<EMAIL>>
# Copyright (c) 2014-2020 <NAME> <<EMAIL>>
# Copyright (c) 2014-2015 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex_boar... | [
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((5709, 5779), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on AliExpress STLV7325"""'}), "(description='LiteX SoC on AliExpress STLV7325')\n", (5731, 5779), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((2214, 2244), 'lit... |
#!/usr/bin/env python3
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["ris... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.soc.cores.gpio.GPIOOut",
"litex.soc.cores.clock.common.period_ns",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.doc.generate_docs"
] | [((8869, 8945), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX based Bootloader on ButterStick"""'}), "(description='LiteX based Bootloader on ButterStick')\n", (8892, 8945), False, 'import argparse\n'), ((8975, 8995), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['... |
import logging
import os
from migen import *
from litex.soc.interconnect.csr_eventmanager import EventManager, EventSourceLevel
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
class CenJT51(Module):
def __init__(self, tuning_word):
self.cen = Signal()
self.cen_p1 ... | [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.csr_eventmanager.EventManager",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr_eventmanager.EventSourceLevel"
] | [((1776, 1829), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {'reset_less': '(True)', 'description': '"""Data in"""'}), "(8, reset_less=True, description='Data in')\n", (1786, 1829), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1851, 1887), 'litex.so... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Support for the ZTEX USB-FGPA Module 2.13:https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html.
# With (no-so-optional) expansi... | [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((3915, 3976), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Ztex 2.13"""'}), "(description='LiteX SoC on Ztex 2.13')\n", (3938, 3976), False, 'import argparse\n'), ((4621, 4646), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parse... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.interconnect import wishbone
# TestWishbone -------------------------------------------------------------------------------------
class TestWishbone(uni... | [
"litex.soc.interconnect.wishbone.UpConverter",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.wishbone.DownConverter",
"litex.soc.interconnect.wishbone.SRAM"
] | [((999, 1032), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(16)'}), '(data_width=16)\n', (1017, 1032), False, 'from litex.soc.interconnect import wishbone\n'), ((1061, 1094), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(da... |
#!/usr/bin/env python3
#
# This file is part of LiteHelloWorld.
#
"""
LiteHelloWorld standalone core manager
LiteHelloWorld aims to be directly used as a python package when the SoC is created using LiteX. However,
for some use cases it could be interesting to generate a standalone verilog file of the core or use it ... | [
"litex.build.lattice.platform.LatticePlatform",
"litex.build.sim.config.SimConfig",
"litex.build.sim.SimPlatform",
"litex.build.altera.platform.AlteraPlatform",
"litex.build.xilinx.platform.XilinxPlatform"
] | [((6301, 6378), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteHelloWorld standalone core manager"""'}), "(description='LiteHelloWorld standalone core manager')\n", (6324, 6378), False, 'import argparse\n'), ((5852, 5947), 'litescope.LiteScopeAnalyzer', 'LiteScopeAnalyzer', (['analyz... |
import subprocess
from migen import Module
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField
class Version(Module, AutoCSR, AutoDoc):
def __init__(self, model, hw_platform, parent, seed=0, models=[]):
self.intro = Modul... | [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.integration.doc.ModuleDoc"
] | [((315, 514), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""SoC Version Information\n\n This block contains various information about the state of the source code\n repository when this SoC was built.\n """'], {}), '(\n """SoC Version Information\n\n This block... |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((2810, 2830), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2828, 2830), False, 'from litex.soc.interconnect import wishbone\n'), ((5592, 5603), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (5601, 5603), False, 'import os\n'), ((5793, 5817), 'os.path.exists', 'os.path.exists', (... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.interconnect import wishbone
# TestWishbone -------------------------------------------------------------------------------------
class TestWishbone(uni... | [
"litex.soc.interconnect.wishbone.UpConverter",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.wishbone.DownConverter",
"litex.soc.interconnect.wishbone.SRAM"
] | [((999, 1032), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(16)'}), '(data_width=16)\n', (1017, 1032), False, 'from litex.soc.interconnect import wishbone\n'), ((1061, 1094), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(da... |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by a... | [
"litex.build.lattice.programmer.IceStormProgrammer"
] | [((1303, 1342), 'litex.build.lattice.programmer.IceStormProgrammer', 'lattice_programmer.IceStormProgrammer', ([], {}), '()\n', (1340, 1342), True, 'from litex.build.lattice import programmer as lattice_programmer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((6308, 6400), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-fgg484-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-fgg484-2', _io, _connectors,\n toolchain='vivado')\n", (6331, 6400), False, 'from litex.build.xilinx import XilinxPlat... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# clock
("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
# leds
("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
("use... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((8639, 8714), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', "(part + '-fgg484-2')", '_io'], {'toolchain': 'toolchain'}), "(self, part + '-fgg484-2', _io, toolchain=toolchain)\n", (8662, 8714), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((9415, 946... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs --------------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4178, 4256), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu7ev-ffvc1156-2-e"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xczu7ev-ffvc1156-2-e', _io, toolchain='vivado')\n", (4201, 4256), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'),... |
from migen import *
from litex.build.generic_platform import Subsignal, Pins, IOStandard
from litex_boards.platforms import lambdaconcept_ecpix5
from ..crg_ecp5 import CRG
from ..serial_led import SerialLedController
from litespi.opcodes import SpiNorFlashOpCodes as Codes
from ..flash_modules import IS25LP256D
clas... | [
"litex.build.generic_platform.Pins"
] | [((2526, 2583), 'litex_boards.platforms.lambdaconcept_ecpix5.Platform.do_finalize', 'lambdaconcept_ecpix5.Platform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2567, 2583), False, 'from litex_boards.platforms import lambdaconcept_ecpix5\n'), ((1342, 1357), 'litex.build.generic_platform.Pins', 'Pins'... |
#
# This file is part of LiteX.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import subprocess
import sys
from shutil import which
from migen.fhdl.structure import _Fragment
from litex.b... | [
"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file"
] | [((5798, 5865), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(False)'}), '(script_file, script_contents, force_unix=False)\n', (5817, 5865), False, 'from litex.build import tools\n'), ((6253, 6286), 'subprocess.call', 'subprocess.call', (['(shell + [scri... |
from litex.tools.litex_server import RemoteServer
def litex_srv():
from litex.tools.remote.comm_udp import CommUDP
udp_ip = '192.168.100.50'
udp_port = 1234
comm = CommUDP(udp_ip, udp_port, debug=False)
server = RemoteServer(comm, '127.0.0.1', 1234)
server.open()
server.start(4)
| [
"litex.tools.litex_server.RemoteServer",
"litex.tools.remote.comm_udp.CommUDP"
] | [((181, 219), 'litex.tools.remote.comm_udp.CommUDP', 'CommUDP', (['udp_ip', 'udp_port'], {'debug': '(False)'}), '(udp_ip, udp_port, debug=False)\n', (188, 219), False, 'from litex.tools.remote.comm_udp import CommUDP\n'), ((234, 271), 'litex.tools.litex_server.RemoteServer', 'RemoteServer', (['comm', '"""127.0.0.1"""',... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from litex.build.generic_platform import *
from litex.build.efinix.platform import EfinixPlatform
from litex.build.efinix.programmer import EfinixAtmelP... | [
"litex.build.efinix.platform.EfinixPlatform.do_finalize",
"litex.build.efinix.platform.EfinixPlatform.__init__",
"litex.build.efinix.programmer.EfinixAtmelProgrammer"
] | [((2365, 2444), 'litex.build.efinix.platform.EfinixPlatform.__init__', 'EfinixPlatform.__init__', (['self', '"""T8F81C2"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'T8F81C2', _io, _connectors, toolchain=toolchain)\n", (2388, 2444), False, 'from litex.build.efinix.platform import EfinixPlatform\n'),... |
#!/usr/bin/env python3
from litex import RemoteClient
import time
wb = RemoteClient()
wb.open()
# Test patterns: 4 (words) x 32 (bits)
#pattern = 0xffffffffffffffffffffffffffffffff
#pattern = 0x00000000000000000000000000000000
pattern = 0xa5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5
#pattern = 0x5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a... | [
"litex.RemoteClient"
] | [((73, 87), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (85, 87), False, 'from litex import RemoteClient\n'), ((957, 982), 'time.sleep', 'time.sleep', (['(1 / 1000000.0)'], {}), '(1 / 1000000.0)\n', (967, 982), False, 'import time\n')] |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.