code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
import os
from distutils.dir_util import copy_tree
from litex.build import tools
from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header
def copy_litepcie_software(dst):
src = os.path.abspath(os.path.dirname(__file__))
copy_tree(src, dst)
def generate_litepcie_software_headers(soc, dst):
csr_header = get_csr_header(soc.csr_regions, soc.constants, with_access_functions=False)
tools.write_to_file(os.path.join(dst, "csr.h"), csr_header)
soc_header = get_soc_header(soc.constants, with_access_functions=False)
tools.write_to_file(os.path.join(dst, "soc.h"), soc_header)
mem_header = get_mem_header(soc.mem_regions)
tools.write_to_file(os.path.join(dst, "mem.h"), mem_header)
def generate_litepcie_software(soc, dst):
copy_litepcie_software(dst)
generate_litepcie_software_headers(soc, os.path.join(dst, "kernel"))
| [
"litex.soc.integration.export.get_mem_header",
"litex.soc.integration.export.get_csr_header",
"litex.soc.integration.export.get_soc_header"
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from migen import *
from litex.soc.interconnect.stream import Endpoint, Pipeline, Converter, Cast, CombinatorialActor
class Output(Module):
def __init__(self):
self.sink = sink = Endpoint([('data', 1)])
self.out = out = Signal()
self.submodules.fsm = fsm = FSM()
data = Signal()
last = Signal()
cnt = Signal(13)
cnt_done = Signal()
self.comb += cnt_done.eq(cnt == 0)
self.sync += If(~cnt_done, cnt.eq(cnt - 1))
time_bit_4 = round(75e6 * 0.3e-6)
time_end = round(75e6 * 80e-6)
fsm.act('IDLE',
out.eq(0),
If(sink.valid,
NextState('HIGH'),
NextValue(cnt, time_bit_4),
),
)
fsm.act('HIGH',
out.eq(1),
If(cnt_done,
NextState('DATA'),
NextValue(cnt, time_bit_4),
sink.ready.eq(1),
NextValue(data, sink.data),
NextValue(last, sink.last),
),
)
fsm.act('DATA',
out.eq(data),
If(cnt_done,
NextState('LOW'),
NextValue(cnt, 2 * time_bit_4),
),
)
fsm.act('LOW',
out.eq(0),
If(cnt_done,
If(last,
NextState('END'),
NextValue(cnt, time_end),
).Else(
NextState('HIGH'),
NextValue(cnt, time_bit_4),
)
),
)
fsm.act('END',
out.eq(0),
If(cnt_done,
NextState('IDLE'),
),
)
class Generator(Module):
def __init__(self, num):
self.leds = leds = Array(Record([('r', 1), ('g', 1), ('b', 1)]) for i in range(num))
self.source = source = Endpoint([('r', 1), ('g', 1), ('b', 1)])
cnt = Signal(max = num)
self.comb += [
source.r.eq(leds[cnt].r),
source.g.eq(leds[cnt].g),
source.b.eq(leds[cnt].b),
source.valid.eq(1),
source.first.eq(cnt == 0),
source.last.eq(cnt == num - 1),
]
self.sync += If(source.ready,
cnt.eq(cnt + 1),
If(source.last,
cnt.eq(0),
),
)
class BrightnessController(CombinatorialActor):
def __init__(self, brightness):
self.sink = sink = Endpoint([('r', 1), ('g', 1), ('b', 1)])
self.source = source = Endpoint([('r', 8), ('g', 8), ('b', 8)])
self.comb += [
If(sink.r, source.r.eq(brightness)),
If(sink.g, source.g.eq(brightness)),
If(sink.b, source.b.eq(brightness)),
]
super().__init__()
class SerialLedController(Module):
def __init__(self, pad, num):
self.submodules.generator = Generator(num)
self.leds = self.generator.leds
self.submodules.brightness_controller = BrightnessController(8)
self.submodules.cast = Cast([('b', 8), ('r', 8), ('g', 8)], [('data', 24)])
self.submodules.converter = Converter(24, 1, reverse = True)
self.submodules.output = Output()
self.submodules.pipeline = Pipeline(
self.generator,
self.brightness_controller,
self.cast,
self.converter,
self.output,
)
self.comb += pad.eq(self.output.out)
| [
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.Cast",
"litex.soc.interconnect.stream.Converter"
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#!/usr/bin/env python3
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import nfcard
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import colorer
from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, USPMMCM
from litex.soc.interconnect import axi, wishbone
from litex.soc.cores.bitbang import I2CMaster
from litedram.phy import usddrphy
from liteeth.phy.usrgmii import LiteEthPHYRGMII
from rowhammer_tester.targets import common
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
IODELAYCTRL_REFCLK_RANGE = (300e6, 800e6) # according to Zynq US+ MPSoC datasheet
def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_uart = ClockDomain()
# # #
self.submodules.pll = pll = USPMMCM(speedgrade=-2)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk125"), 100e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
pll.create_clkout(self.cd_uart, sys_clk_freq, with_reset=False)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
p_BUFGCE_DIVIDE=4,
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
]
fmin, fmax = self.IODELAYCTRL_REFCLK_RANGE
assert fmin <= iodelay_clk_freq <= fmax, \
f"IDELAYCTRL refclk must be in range ({fmin/1e6}, {fmax/1e6}) MHz, got {iodelay_clk_freq/1e6} MHz"
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
@classmethod
def find_iodelay_clk_freq(cls, sys_clk_freq):
# try to find IODELAYCTRL refclk as a multiple of sysclk so that a PLL config almost always is found
fmin, fmax = cls.IODELAYCTRL_REFCLK_RANGE
mul = 4
while sys_clk_freq * mul < fmin:
mul *= 2
while sys_clk_freq * mul > fmax and mul >= 1:
mul //= 2
return sys_clk_freq * mul
# SoC ----------------------------------------------------------------------------------------------
class ZynqUSPS(Module):
# For full address map see UG1085, ZynqUS+ TRM, Table 10-1
_KB = 2**10
_MB = 2**10 * _KB
_GB = 2**10 * _MB
PS_MEMORY_MAP = {
'gp_lpd_master': [[
# M_AXI_HPM0_LPD
# (base, size)
(0x8000_0000, 512*_MB),
]],
'gp_fpd_master': [
[ # M_AXI_HPM0_FPD regions
( 0xa400_0000, 192*_MB), # (32-bit), may be different (see TRM notes)
(0x0004_0000_0000, 4*_GB), # (36-bit)
(0x0010_0000_0000, 224*_GB), # (40-bit)
],
[ # M_AXI_HPM1_FPD regions
( 0xb000_0000, 256*_MB), # (32-bit)
(0x0005_0000_0000, 4*_GB), # (36-bit)
(0x0048_0000_0000, 224*_GB), # (40-bit)
],
],
}
def __init__(self):
self.params = {}
# fpd/lpd = full/low power domain
self.axi_gp_fpd_masters = []
self.axi_gp_lpd_masters = []
self.axi_gp_fpd_slaves = []
self.axi_gp_lpd_slaves = []
self.axi_acp_fpd_slaves = []
def add_axi_gp_fpd_master(self, **kwargs): # MAXIGP0 - MAXIGP1
return self._append_axi(attr='axi_gp_fpd_masters', maxn=2, name='MAXIGP{n}', **kwargs)
def add_axi_gp_lpd_master(self, **kwargs): # MAXIGP2
return self._append_axi(attr='axi_gp_lpd_masters', maxn=1, name='MAXIGP2', **kwargs)
def add_axi_gp_fpd_slave(self, **kwargs): # SAXIGP0 - SAXIGP5
return self._append_axi(attr='axi_gp_fpd_slaves', maxn=6, name='SAXIGP{n}', **kwargs)
def add_axi_gp_lpd_slave(self, **kwargs): # SAXIGP6
return self._append_axi(attr='axi_gp_lpd_slaves', maxn=1, name='SAXIGP6', **kwargs)
def add_axi_acp_fpd_slave(self, **kwargs): # SAXIACP
return self._append_axi(attr='axi_acp_fpd_slaves', maxn=1, name='SAXIACP', **kwargs)
def _append_axi(self, attr, maxn, name, **kwargs):
axis = getattr(self, attr)
n = len(axis)
assert n < maxn, 'Maximum number of AXIs for {} is {}'.format(attr, maxn)
ax = self._add_axi(name=name.format(n=n), **kwargs)
axis.append(ax)
return ax
def _add_axi(self, name, data_width=128, address_width=40, id_width=16):
assert data_width <= 128
assert address_width <= 40
assert id_width <= 16
ax = axi.AXIInterface(data_width=data_width, address_width=address_width, id_width=id_width)
self.params.update({
f'o_{name}ACLK': ClockSignal(),
# aw
f'o_{name}AWVALID': ax.aw.valid,
f'i_{name}AWREADY': ax.aw.ready,
f'o_{name}AWADDR': ax.aw.addr,
f'o_{name}AWBURST': ax.aw.burst,
f'o_{name}AWLEN': ax.aw.len,
f'o_{name}AWSIZE': ax.aw.size[:3], # need to match size exactly
f'o_{name}AWID': ax.aw.id,
f'o_{name}AWLOCK': ax.aw.lock[:1], # need to match size exactly
f'o_{name}AWPROT': ax.aw.prot,
f'o_{name}AWCACHE': ax.aw.cache,
f'o_{name}AWQOS': ax.aw.qos,
# w
f'o_{name}WVALID': ax.w.valid,
f'o_{name}WLAST': ax.w.last,
f'i_{name}WREADY': ax.w.ready,
# f'o_{name}WID': ax.w.id, # does not exist
f'o_{name}WDATA': ax.w.data,
f'o_{name}WSTRB': ax.w.strb,
# b
f'i_{name}BVALID': ax.b.valid,
f'o_{name}BREADY': ax.b.ready,
f'i_{name}BID': ax.b.id,
f'i_{name}BRESP': ax.b.resp,
# ar
f'o_{name}ARVALID': ax.ar.valid,
f'i_{name}ARREADY': ax.ar.ready,
f'o_{name}ARADDR': ax.ar.addr,
f'o_{name}ARBURST': ax.ar.burst,
f'o_{name}ARLEN': ax.ar.len,
f'o_{name}ARID': ax.ar.id,
f'o_{name}ARLOCK': ax.ar.lock[:1],
f'o_{name}ARSIZE': ax.ar.size[:3],
f'o_{name}ARPROT': ax.ar.prot,
f'o_{name}ARCACHE': ax.ar.cache,
f'o_{name}ARQOS': ax.ar.qos,
# r
f'i_{name}RVALID': ax.r.valid,
f'o_{name}RREADY': ax.r.ready,
f'i_{name}RLAST': ax.r.last,
f'i_{name}RID': ax.r.id,
f'i_{name}RRESP': ax.r.resp,
f'i_{name}RDATA': ax.r.data,
})
return ax
def do_finalize(self):
self.specials += Instance('PS8', **self.params)
class SoC(common.RowHammerSoC):
def __init__(self, **kwargs):
min_rom = 0x9000
if kwargs["integrated_rom_size"] < min_rom:
kwargs["integrated_rom_size"] = min_rom
super().__init__(**kwargs)
if self.args.sim:
return
# SPD EEPROM I2C ---------------------------------------------------------------------------
# self.submodules.i2c = I2CMaster(self.platform.request("i2c"))
# self.add_csr("i2c")
# ZynqUS+ PS -------------------------------------------------------------------------------
self.submodules.ps = ZynqUSPS()
# Configure PS->PL AXI
# AXI(32) -> AXILite(32) -> WishBone(32) -> SoC Interconnect
axi_ps = self.ps.add_axi_gp_fpd_master(data_width=32)
axi_lite_ps = axi.AXILiteInterface(data_width=32, address_width=40)
self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps)
# Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000)
base_address = None
for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]:
if size >= 2**30-1:
base_address = base
break
assert base_address is not None
def chunks(lst, n):
for i in range(0, len(lst), n):
yield lst[i:i + n]
addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4))
self.logger.info("Connecting PS AXI master from PS address {}.".format(colorer('0x' + addr_str)))
wb_ps = wishbone.Interface(adr_width=40-2) # AXILite2Wishbone requires the same address widths
self.submodules += axi.AXILite2Wishbone(axi_lite_ps, wb_ps, base_address=base_address)
# silently ignores address bits above 30
self.bus.add_master(name='ps_axi', master=wb_ps)
def get_platform(self):
return nfcard.Platform()
def get_crg(self):
return CRG(self.platform, self.sys_clk_freq, iodelay_clk_freq=self.iodelay_clk_freq)
def get_ddrphy(self):
return usddrphy.USPDDRPHY(
pads = self.platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = self.sys_clk_freq,
iodelay_clk_freq = self.iodelay_clk_freq)
def get_sdram_ratio(self):
return "1:4"
def add_host_bridge(self):
self.add_uartbone(name="serial", clk_freq=self.sys_clk_freq, baudrate=1e6, cd="uart")
@property
def iodelay_clk_freq(self):
if not hasattr(self, '_iodelay_clk_freq'):
if self.args.iodelay_clk_freq is None:
self._iodelay_clk_freq = CRG.find_iodelay_clk_freq(float(self.args.sys_clk_freq))
else:
self._iodelay_clk_freq = self.args.iodelay_clk_freq
return self._iodelay_clk_freq
# Build --------------------------------------------------------------------------------------------
def main():
parser = common.ArgumentParser(
description = "LiteX SoC on NFCard",
sys_clk_freq = '125e6',
module = 'MTA16ATF2G64HZ'
)
g = parser.add_argument_group(title="NFCard")
g.add_argument("--iodelay-clk-freq", type=float, help="Use given exact IODELAYCTRL reference clock frequency")
g.set_defaults(from_spd="SPDDetails.csv")
vivado_build_args(g)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'nfcard'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.clock.USPMMCM",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc_core.colorer",
"litex.soc.interconnect.axi.AXILiteInterface",
"litex.soc.cores.clock.USIDELAYCTRL",
... | [((10346, 10454), 'rowhammer_tester.targets.common.ArgumentParser', 'common.ArgumentParser', ([], {'description': '"""LiteX SoC on NFCard"""', 'sys_clk_freq': '"""125e6"""', 'module': '"""MTA16ATF2G64HZ"""'}), "(description='LiteX SoC on NFCard', sys_clk_freq=\n '125e6', module='MTA16ATF2G64HZ')\n", (10367, 10454), False, 'from rowhammer_tester.targets import common\n'), ((10708, 10728), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['g'], {}), '(g)\n', (10725, 10728), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((10778, 10805), 'rowhammer_tester.targets.common.get_soc_kwargs', 'common.get_soc_kwargs', (['args'], {}), '(args)\n', (10799, 10805), False, 'from rowhammer_tester.targets import common\n'), ((10883, 10939), 'rowhammer_tester.targets.common.get_builder_kwargs', 'common.get_builder_kwargs', (['args'], {'target_name': 'target_name'}), '(args, target_name=target_name)\n', (10908, 10939), False, 'from rowhammer_tester.targets import common\n'), ((10954, 10984), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {}), '(soc, **builder_kwargs)\n', (10961, 10984), False, 'from litex.soc.integration.builder import Builder\n'), ((11060, 11124), 'rowhammer_tester.targets.common.run', 'common.run', (['args', 'builder', 'build_kwargs'], {'target_name': 'target_name'}), '(args, builder, build_kwargs, target_name=target_name)\n', (11070, 11124), False, 'from rowhammer_tester.targets import common\n'), ((1263, 1285), 'litex.soc.cores.clock.USPMMCM', 'USPMMCM', ([], {'speedgrade': '(-2)'}), '(speedgrade=-2)\n', (1270, 1285), False, 'from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, USPMMCM\n'), ((2312, 2367), 'litex.soc.cores.clock.USIDELAYCTRL', 'USIDELAYCTRL', ([], {'cd_ref': 'self.cd_idelay', 'cd_sys': 'self.cd_sys'}), '(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)\n', (2324, 2367), False, 'from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, USPMMCM\n'), ((5261, 5352), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': 'data_width', 'address_width': 'address_width', 'id_width': 'id_width'}), '(data_width=data_width, address_width=address_width,\n id_width=id_width)\n', (5277, 5352), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((8183, 8236), 'litex.soc.interconnect.axi.AXILiteInterface', 'axi.AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(40)'}), '(data_width=32, address_width=40)\n', (8203, 8236), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((8264, 8300), 'litex.soc.interconnect.axi.AXI2AXILite', 'axi.AXI2AXILite', (['axi_ps', 'axi_lite_ps'], {}), '(axi_ps, axi_lite_ps)\n', (8279, 8300), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((8932, 8968), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'adr_width': '(40 - 2)'}), '(adr_width=40 - 2)\n', (8950, 8968), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((9047, 9114), 'litex.soc.interconnect.axi.AXILite2Wishbone', 'axi.AXILite2Wishbone', (['axi_lite_ps', 'wb_ps'], {'base_address': 'base_address'}), '(axi_lite_ps, wb_ps, base_address=base_address)\n', (9067, 9114), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((9265, 9282), 'litex_boards.platforms.nfcard.Platform', 'nfcard.Platform', ([], {}), '()\n', (9280, 9282), False, 'from litex_boards.platforms import nfcard\n'), ((11004, 11030), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (11024, 11030), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((8888, 8912), 'litex.soc.integration.soc_core.colorer', 'colorer', (["('0x' + addr_str)"], {}), "('0x' + addr_str)\n", (8895, 8912), False, 'from litex.soc.integration.soc_core import colorer\n')] |
#!/usr/bin/env python3
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import arty
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
clk = platform.request("clk100")
rst_n = platform.request("cpu_reset")
self.comb += self.cd_sys.clk.eq(clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
platform.add_period_constraint(clk, 1e9/100e6)
# Design -------------------------------------------------------------------------------------------
class Tuto(Module):
def __init__(self, platform):
crg = CRG(platform)
self.submodules += crg
led = platform.request("user_led", 1)
blink = Blink(24)
self.submodules += blink
self.comb += led.eq(blink.out)
data = platform.request("do")
ring = RingSerialCtrl()
self.submodules += ring
self.comb += data.eq(ring.do)
# Blinker -------------------------------------------------------------------------------------------
class Blink(Module):
def __init__(self, bit):
self.out = Signal()
###
counter = Signal(25)
self.comb += self.out.eq(counter[bit])
self.sync += counter.eq(counter + 1)
# RingSerialCtrl -------------------------------------------------------------------------------------------
# ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
# │DI DO│ │DI DO│ │DI DO│ │DI DO│ │DI DO│ Next leds
# FPGA ───► ├───► ├───► ├───► ├───► ├───► or
# │ LED0 │ │ LED1 │ │ LED2 │ │ LED3 │ │ LED4 │ end of chain.
# └──────┘ └──────┘ └──────┘ └──────┘ └──────┘
# 24-bit 24-bit 24-bit 24-bit 24-bit
#
# WS2812/NeoPixel Leds are smart RGB Leds controlled over a simple one wire protocol:
# - Each Led will "digest" a 24-bit control word: (MSB) G-R-B (LSB).
# - Leds can be chained through DIN->DOUT connection.
#
# Each control sequence is separated by a reset code: Line low for > 50us.
# Zeros are transmitted as:
# ┌─────┐
# │ T0H │ │ T0H = 400ns +-150ns
# │ │ T0L │ T0L = 800ns +-150ns
# └───────────┘
# Ones are transmitted as:
# ┌──────────┐
# │ T1H │ │ T1H = 850ns +-150ns
# │ │ T1L │ T1L = 450ns +-150ns
# └──────┘
# You have to send 24 pulses like this:
#
# ┌──────────┐
# │ T1H │ │ T1H = 850ns
# │ │ T1L │ T1L = 450ns
# └──────┘
#
#
# You can send 24 pulses every 'period' of time
#
# Note: 850ns is 85 clock cycles @100MHz
# 450ns is 45 clock cycles @100MHz
class RingSerialCtrl(Module):
def __init__(self):
self.do = Signal()
###
# Add your internal signals here
# If you want a signal that can hold a maximum value of "my_value":
# t_high_cnt = Signal(max=my_value)
# Signals are always initialized to '0' unless you explicitely
# assign a reset value:
# az = Signal(8, reset=0x25)
# Assign a value to a signal is done with .eq
# my_signal.eq(1)
self.sync += [
If( # have we sent 24 bits ?,
If( # We are sending a 'high' level,
# set do to 1,
# increment clock count,
# done ?
# reset clock count
# We are sending a 'low' level
).Else(
# set do to 0,
# increment clock count,
# done ?
# reset clock count
# We are sending a 'high' level
# increment bit counter
),
)
]
# Test -------------------------------------------------------------------------------------------
def test():
loop = 0
while (loop < 10000):
yield
loop = loop + 1
# Build --------------------------------------------------------------------------------------------
def main():
build_dir= 'gateware'
platform = arty.Platform(variant="a7-35", toolchain="vivado")
from litex.build.generic_platform import Pins, IOStandard
platform.add_extension([("do", 0, Pins("B7"), IOStandard("LVCMOS33"))])
if "load" in sys.argv[1: ]:
prog = platform.create_programmer()
prog.load_bitstream(build_dir + "/top.bit")
exit()
if "sim" in sys.argv[1: ]:
ring = RingSerialCtrl()
run_simulation(ring, test(), clocks={"sys": 1e9/100e6}, vcd_name="sim.vcd")
exit()
design = Tuto(platform)
platform.build(design, build_dir=build_dir)
if __name__ == "__main__":
main()
| [
"litex.build.generic_platform.IOStandard",
"litex.build.generic_platform.Pins"
] | [((4683, 4733), 'litex_boards.platforms.arty.Platform', 'arty.Platform', ([], {'variant': '"""a7-35"""', 'toolchain': '"""vivado"""'}), "(variant='a7-35', toolchain='vivado')\n", (4696, 4733), False, 'from litex_boards.platforms import arty\n'), ((565, 608), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~rst_n)'], {}), '(self.cd_sys, ~rst_n)\n', (587, 608), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((4835, 4845), 'litex.build.generic_platform.Pins', 'Pins', (['"""B7"""'], {}), "('B7')\n", (4839, 4845), False, 'from litex.build.generic_platform import Pins, IOStandard\n'), ((4847, 4869), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (4857, 4869), False, 'from litex.build.generic_platform import Pins, IOStandard\n')] |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
import sys
wb = RemoteClient(debug=True)
wb.open()
wb.regs.j2_pins_oe.write(int(sys.argv[1], 0))
print("0x{:08x}".format(wb.regs.j2_pins_oe.read()))
wb.regs.j2_pins_out.write(int(sys.argv[2], 0))
print("0x{:08x}".format(wb.regs.j2_pins_out.read()))
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((90, 114), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'debug': '(True)'}), '(debug=True)\n', (102, 114), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
import sys
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
class DMARecorder:
def __init__(self, name):
self._start = getattr(wb.regs, name + "_start")
self._done = getattr(wb.regs, name + "_done")
self._base = getattr(wb.regs, name + "_base")
self._length = getattr(wb.regs, name + "_length")
def capture(self, base, length):
print("Capture of {} bytes to @0x{:08x}...".format(length, base))
self._base.write(base)
self._length.write(length)
self._start.write(1)
print("Waiting...")
while self._done.read() != 1:
pass
print("Done...")
def upload(self, base, length):
print("Upload of {} bytes to @0x{:08x}...".format(length, base))
datas = []
for i in range(length//4):
datas.append(wb.read(base + 4*i))
return datas
rx_recorder = DMARecorder("rx_dma_recorder")
rx_recorder.capture(0x0000, 32)
datas = rx_recorder.upload(wb.mems.main_ram.base, 32)
for data in datas:
print("{:08x}".format(data))
tx_recorder = DMARecorder("tx_dma_recorder")
tx_recorder.capture(0x0000, 32)
datas = tx_recorder.upload(wb.mems.main_ram.base, 32)
for data in datas:
print("{:08x}".format(data))
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((73, 87), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (85, 87), False, 'from litex import RemoteClient\n')] |
import logging
from migen import *
from litex.soc.cores.dma import WishboneDMAReader
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
from gateware.jtframe.sound.pole import Pole
class CenJT6295(Module):
def __init__(self, tuning_word):
self.cen = Signal()
phase = Signal(32, reset_less=True)
self.sync += Cat(phase, self.cen).eq(phase + tuning_word)
MSM6295_FREQ = 1e6
class JT6295RomWishboneDMAReader(Module, AutoCSR):
"""ROM DMA
"""
def __init__(self, bus, base_address=0, with_csr=False):
assert isinstance(bus, wishbone.Interface)
assert bus.data_width == 8
self.bus = bus
self.i_rom_addr = Signal(18)
self.o_rom_data = Signal(8)
self.o_rom_ok = Signal()
self.base_address = Signal(bus.adr_width, reset=base_address)
# Submodules
self.submodules.dma = WishboneDMAReader(bus)
data_valid = Signal()
new_address = Signal()
current_address = Signal(bus.adr_width)
prev_address = Signal(bus.adr_width)
self.sync += [
prev_address.eq(current_address),
If(self.dma.source.valid, data_valid.eq(1))
]
self.comb += [
new_address.eq(current_address != prev_address),
current_address.eq(self.i_rom_addr + self.base_address),
self.dma.sink.address.eq(current_address)
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
self.o_rom_ok.eq(data_valid),
If(new_address, self.o_rom_ok.eq(0), NextState("CMD"))
)
fsm.act("CMD",
self.dma.source.ready.eq(1),
self.dma.sink.valid.eq(1),
self.dma.sink.last.eq(1),
If(self.dma.sink.valid & self.dma.sink.ready, NextState("IDLE"))
)
self.sync += If(self.dma.source.valid & self.dma.source.ready, self.o_rom_data.eq(self.dma.source.data))
if with_csr:
self.add_csr(default_base=base_address)
def add_csr(self, default_base=0):
self._base = CSRStorage(self.bus.adr_width, reset=default_base)
self.comb += self.base_address.eq(self._base.storage)
class JT6295(Module, AutoCSR):
"""JT6295 4 channel ADPCM decoder compatible with OKI 6295, by <NAME> (aka jotego)
Parameters:
interpol : 0 = no interpolator, 1 = 4x upsampling, LPF at 0.25*pi, 2 = 4x upsampling, LPF at 0.5*pi
"""
def __init__(self, platform, clk_freq, interpol=1):
self.platform = platform
self.o_rom_addr = Signal(18)
self.i_rom_data = Signal(8)
self.i_rom_ok = Signal()
self.ss = Signal()
self.sample = Signal()
self.sound = Signal(14)
self._control = CSRStorage(description="jt6295 control", fields=[
CSRField('reset', reset=1, size=1, description='Reset'),
CSRField('ss', reset=0, size=1, description='Sample rate select'),
CSRField('wr_n', reset=1, size=1, description='Write enable'),
CSRField('enable_filter', size=1, description="Enable LPF")
])
reset = Signal()
wr_n = Signal()
enable_filter = Signal()
self.comb += [
reset.eq(self._control.fields.reset),
self.ss.eq(self._control.fields.ss),
wr_n.eq(self._control.fields.wr_n),
enable_filter.eq(self._control.fields.enable_filter)
]
self._din = CSRStorage(8, reset_less=True, description="Data in")
self._dout = CSRStatus(8, description="Data out")
din = Signal(8)
dout = Signal(8)
self.comb += [
din.eq(self._din.storage),
self._dout.status.eq(dout)
]
self.logger = logging.getLogger("JT6295")
self.logger.info(f'JT6295 clock {MSM6295_FREQ}Hz from {clk_freq}Hz')
cen = Signal()
self.submodules.clock_enable = CenJT6295(tuning_word=int((MSM6295_FREQ / clk_freq) * 2 ** 32))
self.comb += cen.eq(self.clock_enable.cen)
sound_raw = Signal(len(self.sound))
self.jt6295_params = dict(
p_INTERPOL=interpol,
i_rst=ResetSignal() | reset,
i_clk=ClockSignal(),
i_cen=cen,
i_ss=self.ss,
i_wrn=wr_n,
i_din=din,
o_dout=dout,
o_rom_addr=self.o_rom_addr,
i_rom_data=self.i_rom_data,
i_rom_ok=self.i_rom_ok,
o_sample=self.sample,
o_sound=sound_raw
)
sound_filtered = Signal(len(self.sound))
self.submodules.low_pass_filter = low_pass_filter = Pole(platform, ws=len(self.sound))
self.comb += [
low_pass_filter.i_sample.eq(self.sample),
low_pass_filter.sin.eq(sound_raw),
low_pass_filter.a.eq(Mux(self.ss, 108, 104)),
sound_filtered.eq(low_pass_filter.sout)
]
self.sync += [
self.sound.eq(Mux(enable_filter, sound_filtered, sound_raw))
]
self.add_sources(platform)
@staticmethod
def add_sources(platform):
platform.add_source_dir("gateware/rtl/jt6295/hdl", recursive=False)
platform.add_verilog_include_path("gateware/rtl/jt6295/hdl")
platform.add_source("gateware/rtl/jtframe/hdl/sound/jtframe_fir_mono.v")
platform.add_source("gateware/rtl/jtframe/hdl/ram/jtframe_dual_ram.v")
@staticmethod
def fir_init_paths():
return [
"gateware/rtl/jt6295/hdl/jt6295_up4.hex",
"gateware/rtl/jt6295/hdl/jt6295_up4_soft.hex"
]
def do_finalize(self):
self.specials += Instance("jt6295", **self.jt6295_params) | [
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.cores.dma.WishboneDMAReader",
"litex.soc.interconnect.csr.CSRStorage"
] | [((957, 979), 'litex.soc.cores.dma.WishboneDMAReader', 'WishboneDMAReader', (['bus'], {}), '(bus)\n', (974, 979), False, 'from litex.soc.cores.dma import WishboneDMAReader\n'), ((2193, 2243), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['self.bus.adr_width'], {'reset': 'default_base'}), '(self.bus.adr_width, reset=default_base)\n', (2203, 2243), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((3573, 3626), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {'reset_less': '(True)', 'description': '"""Data in"""'}), "(8, reset_less=True, description='Data in')\n", (3583, 3626), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((3648, 3684), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(8)'], {'description': '"""Data out"""'}), "(8, description='Data out')\n", (3657, 3684), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((3868, 3895), 'logging.getLogger', 'logging.getLogger', (['"""JT6295"""'], {}), "('JT6295')\n", (3885, 3895), False, 'import logging\n'), ((2931, 2986), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""reset"""'], {'reset': '(1)', 'size': '(1)', 'description': '"""Reset"""'}), "('reset', reset=1, size=1, description='Reset')\n", (2939, 2986), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((3000, 3065), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""ss"""'], {'reset': '(0)', 'size': '(1)', 'description': '"""Sample rate select"""'}), "('ss', reset=0, size=1, description='Sample rate select')\n", (3008, 3065), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((3079, 3140), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""wr_n"""'], {'reset': '(1)', 'size': '(1)', 'description': '"""Write enable"""'}), "('wr_n', reset=1, size=1, description='Write enable')\n", (3087, 3140), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((3154, 3213), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""enable_filter"""'], {'size': '(1)', 'description': '"""Enable LPF"""'}), "('enable_filter', size=1, description='Enable LPF')\n", (3162, 3213), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n')] |
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import GenericPlatform
from litex.build.microsemi import common, libero_soc
class MicrosemiPlatform(GenericPlatform):
bitstream_ext = ".bit"
def __init__(self, *args, toolchain="libero_soc_polarfire", **kwargs):
GenericPlatform.__init__(self, *args, **kwargs)
if toolchain == "libero_soc_polarfire":
self.toolchain = libero_soc.MicrosemiLiberoSoCPolarfireToolchain()
else:
raise ValueError("Unknown toolchain")
def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict()
so.update(self.toolchain.special_overrides)
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so,
attr_translate=self.toolchain.attr_translate,
**kwargs)
def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs)
def add_period_constraint(self, clk, period):
if hasattr(clk, "p"):
clk = clk.p
self.toolchain.add_period_constraint(self, clk, period)
def add_false_path_constraint(self, from_, to):
if hasattr(from_, "p"):
from_ = from_.p
if hasattr(to, "p"):
to = to.p
self.toolchain.add_false_path_constraint(self, from_, to)
| [
"litex.build.microsemi.libero_soc.MicrosemiLiberoSoCPolarfireToolchain",
"litex.build.generic_platform.GenericPlatform.__init__",
"litex.build.generic_platform.GenericPlatform.get_verilog"
] | [((332, 379), 'litex.build.generic_platform.GenericPlatform.__init__', 'GenericPlatform.__init__', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (356, 379), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((766, 888), 'litex.build.generic_platform.GenericPlatform.get_verilog', 'GenericPlatform.get_verilog', (['self', '*args'], {'special_overrides': 'so', 'attr_translate': 'self.toolchain.attr_translate'}), '(self, *args, special_overrides=so,\n attr_translate=self.toolchain.attr_translate, **kwargs)\n', (793, 888), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((457, 506), 'litex.build.microsemi.libero_soc.MicrosemiLiberoSoCPolarfireToolchain', 'libero_soc.MicrosemiLiberoSoCPolarfireToolchain', ([], {}), '()\n', (504, 506), False, 'from litex.build.microsemi import common, libero_soc\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Cam Link 4K PCB and IOs have been documented by @GregDavill and @ApertusOSCinema:
# https://wiki.apertus.org/index.php/Elgato_CAM_LINK_4K
# The FX3 exploration tool (and FPGA loader) has been developed by @ktemkin:
# https://github.com/ktemkin/camlink-re
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk27", 0, Pins("B11"), IOStandard("LVCMOS25")),
# Leds
("user_led", 0, Pins("A6"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("A9"), IOStandard("LVCMOS25")),
# Serial
("serial", 0,
Subsignal("tx", Pins("A6")), # led0
Subsignal("rx", Pins("A9")), # led1
IOStandard("LVCMOS25")
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"P2 L2 N1 P1 N5 M1 M3 N4",
"L3 L1 P5 N2 N3"),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("C4 A3 B4"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("D3"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("C3"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("D5"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("B5"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"L5 F1 K4 G1 L4 H1 G2 J3",
"D1 C1 E2 C2 F3 A2 E1 B1"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("K2 H4"),
Misc("TERMINATION=OFF"),
Misc("DIFFRESISTOR=100"),
IOStandard("SSTL135D_I")),
Subsignal("clk_p", Pins("A4"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("E4"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("B3"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("C5"), IOStandard("SSTL135_I")),
Misc("SLEWRATE=FAST"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk27"
default_clk_period = 1e9/27e6
def __init__(self, toolchain="trellis", **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-8BG381C", _io, toolchain=toolchain, **kwargs)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)
| [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((2420, 2512), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8BG381C"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'LFE5U-25F-8BG381C', _io, toolchain=\n toolchain, **kwargs)\n", (2444, 2512), False, 'from litex.build.lattice import LatticePlatform\n'), ((2554, 2597), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2581, 2597), False, 'from litex.build.lattice import LatticePlatform\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("G13"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("D14"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("T14"), IOStandard("LVCMOS33")),
# K17 - QSPI_DQ0 - MOSI
# K18 - QSPI_DQ1 - MISO
# L14 - QSPI_DQ2 - ~WP
# M15 - QSPI_DQ3 - ~HOLD
# M13 - QSPI_CS - ~CS
# C8 - CCLK
("spiflash_4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("dq", Pins("K17", "K18", "L14", "M15")),
IOStandard("LVCMOS33")
),
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("M13")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M15")),
IOStandard("LVCMOS33")
),
("serial", 0,
Subsignal("tx", Pins("N13")),
Subsignal("rx", Pins("L13")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"P5 P6 T3 R4 V4 V5 V2 V3",
"U2 U3 U1 T1 T2 R3"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("T6 V6 V7"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("T5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("R7"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R6"), IOStandard("SSTL15")),
Subsignal("dm", Pins("K4 M3"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"L4 K3 K2 K6 L6 L5 M4 M6",
"M2 M1 N1 N5 N4 P2 P1 R2"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("K1 N3"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("L1 N2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("R5"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("T4"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("U6"), IOStandard("SSTL15")),
Subsignal("odt", Pins("P7"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("U7"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("M5"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]
_connectors = []
class Platform(XilinxPlatform):
name = "narvi"
default_clk_name = "clk100"
default_clk_period = 10.0
# From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
# 17,536,096 bits == 2192012 bytes == 0x21728C -- Therefore 0x220000
gateware_size = 0x220000
# Numonyx N25Q128A
spiflash_read_dummy_bits = 10
spiflash_clock_div = 4
spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
spiflash_model = "n25q128"
def __init__(self, toolchain="vivado", programmer="openocd"):
XilinxPlatform.__init__(self, "xc7s50csga324-1", _io, _connectors,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/numato_narvi.cfg", flash_proxy_basename=proxy)
elif self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
| [
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((2975, 3066), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7s50csga324-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7s50csga324-1', _io, _connectors,\n toolchain=toolchain)\n", (2998, 3066), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((3838, 3856), 'litex.build.xilinx.XC3SProg', 'XC3SProg', (['"""nexys4"""'], {}), "('nexys4')\n", (3846, 3856), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((3918, 3974), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""n25q128-3.3v-spi-x1_x2_x4"""'}), "(flash_part='n25q128-3.3v-spi-x1_x2_x4')\n", (3934, 3974), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Avalon support for LiteX"""
from migen import *
from litex.soc.interconnect import stream
# Avalon-ST to/from native LiteX's stream ----------------------------------------------------------
# In native LiteX's streams, ready signal has no latency (similar to AXI). In Avalon-ST streams the
# ready signal has a latency: If ready is asserted on cycle n, then cycle n + latency is a "ready"
# in the LiteX/AXI's sense) cycle. This means that:
# - when converting to Avalon-ST, we need to add this latency on datas.
# - when converting from Avalon-ST, we need to make sure we are able to store datas for "latency"
# cycles after ready deassertion on the native interface.
class Native2AvalonST(Module):
"""Native LiteX's stream to Avalon-ST stream"""
def __init__(self, layout, latency=2):
self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout)
# # #
_from = sink
for n in range(latency):
_to = stream.Endpoint(layout)
self.sync += _from.connect(_to, omit={"ready"})
if n == 0:
self.sync += _to.valid.eq(sink.valid & source.ready)
_from = _to
self.comb += _to.connect(source, omit={"ready"})
self.comb += sink.ready.eq(source.ready)
class AvalonST2Native(Module):
"""Avalon-ST Stream to native LiteX's stream"""
def __init__(self, layout, latency=2):
self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout)
# # #
buf = stream.SyncFIFO(layout, latency)
self.submodules += buf
self.comb += sink.connect(buf.sink, omit={"ready"})
self.comb += sink.ready.eq(source.ready)
self.comb += buf.source.connect(source)
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((953, 976), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (968, 976), False, 'from litex.soc.interconnect import stream\n'), ((1008, 1031), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (1023, 1031), False, 'from litex.soc.interconnect import stream\n'), ((1585, 1608), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (1600, 1608), False, 'from litex.soc.interconnect import stream\n'), ((1640, 1663), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (1655, 1663), False, 'from litex.soc.interconnect import stream\n'), ((1694, 1726), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (['layout', 'latency'], {}), '(layout, latency)\n', (1709, 1726), False, 'from litex.soc.interconnect import stream\n'), ((1120, 1143), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['layout'], {}), '(layout)\n', (1135, 1143), False, 'from litex.soc.interconnect import stream\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Work-In-Progress...
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst.
# TODO.
# Debug.
("debug", 0, Pins("A15"), IOStandard("LVCMOS33")),
("debug", 1, Pins("C14"), IOStandard("LVCMOS33")),
("debug", 2, Pins("B14"), IOStandard("LVCMOS33")),
("debug", 3, Pins("A14"), IOStandard("LVCMOS33")),
# Fan.
("fan", 0, Pins(""), IOStandard("LVCMOS33")),
# Flash.
("flash_cs_n", 0, Pins("C23"), IOStandard("LVCMOS33")),
("flash", 0,
Subsignal("mosi", Pins("B24")),
Subsignal("miso", Pins("A25")),
Subsignal("vpp", Pins("B22")),
Subsignal("hold", Pins("A22")),
IOStandard("LVCMOS33")
),
# PCIe.
("pcie_x4", 0,
Subsignal("rst_n", Pins("K21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4 L4 N4 R4")),
Subsignal("rx_n", Pins("J3 L3 N3 R3")),
Subsignal("tx_p", Pins("H2 K2 M2 P2")),
Subsignal("tx_n", Pins("H1 K1 M1 P1"))
),
# DRAM (MT47H64M16).
# HDMI Out.
# TODO.
# HDMI In.
# TODO.
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "debug" # FIXME.
default_clk_period = 1e9/100e6 # FIXME.
def __init__(self):
XilinxPlatform.__init__(self, "xc7k70t-fbg676-1", _io, toolchain="vivado")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a70t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
| [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((1741, 1815), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k70t-fbg676-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7k70t-fbg676-1', _io, toolchain='vivado')\n", (1764, 1815), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1865, 1922), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft232.cfg"""', '"""bscan_spi_xc7a70t.bit"""'], {}), "('openocd_xc7_ft232.cfg', 'bscan_spi_xc7a70t.bit')\n", (1872, 1922), False, 'from litex.build.openocd import OpenOCD\n'), ((1969, 2011), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1995, 2011), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# GPIOs
("gpio", 0, Pins("K13"), IOStandard("LVCMOS18")),
("gpio", 1, Pins("M12"), IOStandard("LVCMOS18")),
("gpio", 2, Pins("R10"), IOStandard("LVCMOS18")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7z010clg225-1", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
| [
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((821, 912), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z010clg225-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7z010clg225-1', _io, _connectors,\n toolchain=toolchain)\n", (844, 912), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((959, 977), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (975, 977), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((1024, 1066), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1050, 1066), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk12", 0, Pins("C8"), IOStandard("LVCMOS33")),
("rst_n", 0, Pins("B3"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("H11"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("J11"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("L12"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("K11"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("L13"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("N15"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("P16"), IOStandard("LVCMOS33")),
("user_dip_btn", 0, Pins("N2"), IOStandard("LVCMOS33")),
("user_dip_btn", 1, Pins("P1"), IOStandard("LVCMOS33")),
("user_dip_btn", 2, Pins("M3"), IOStandard("LVCMOS33")),
("user_dip_btn", 3, Pins("N1"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("C11"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("A11"), IOStandard("LVCMOS33")),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self):
LatticePlatform.__init__(self, "LCMXO3L-6900C-5BG256C", _io)
def create_programmer(self):
_xcf_template = """
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.6.0">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>MachXO3L</Family>
<Name>LCMXO3L-6900C</Name>
<IDCode>0x412bd043</IDCode>
<Package>All</Package>
<PON>LCMXO3L-6900C</PON>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
<File>{bitstream_file}</File>
<JedecChecksum>N/A</JedecChecksum>
<Operation>SRAM Fast Configuration</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<IOState>HighZ</IOState>
<PreloadLength>664</PreloadLength>
<IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
<Usercode>0x00000000</Usercode>
<AccessMode>SRAM</AccessMode>
</Option>
</Device>
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>Lattice XO3L Starter Kit A Location 0000 Serial A</USBID>
</CableOptions>
</ispXCF>
"""
return LatticeProgrammer(_xcf_template)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
| [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.LatticeProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((1594, 1654), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LCMXO3L-6900C-5BG256C"""', '_io'], {}), "(self, 'LCMXO3L-6900C-5BG256C', _io)\n", (1618, 1654), False, 'from litex.build.lattice import LatticePlatform\n'), ((3576, 3608), 'litex.build.lattice.programmer.LatticeProgrammer', 'LatticeProgrammer', (['_xcf_template'], {}), '(_xcf_template)\n', (3593, 3608), False, 'from litex.build.lattice.programmer import LatticeProgrammer\n'), ((3655, 3698), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3682, 3698), False, 'from litex.build.lattice import LatticePlatform\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
import os
import sys
import json
from litex.build import tools
def main():
if len(sys.argv) < 2:
print("usage: litex_read_verilog verilog_file [module]")
exit(1)
verilog_file = sys.argv[1]
json_file = verilog_file + ".json"
module = None if len(sys.argv) < 3 else sys.argv[2]
# use yosys to convert verilog to json
yosys_v2j = "\n".join([
"read_verilog -sv {}".format(verilog_file),
"write_json {}.json".format(verilog_file)
])
tools.write_to_file("yosys_v2j.ys", yosys_v2j)
os.system("yosys -q yosys_v2j.ys")
# load json and convert to migen module
f = open(json_file, "r")
j = json.load(f)
# create list of modules
modules = [module] if module is not None else j["modules"].keys()
# create migen definitions
for module in modules:
migen_def = []
migen_def.append("class {}(Module):".format(module))
migen_def.append(" "*4 + "def __init__(self):")
for name, info in j["modules"][module]["ports"].items():
length = "" if len(info["bits"]) == 1 else len(info["bits"])
migen_def.append(" " * 8 + "self.{} = Signal({})".format(name, length))
migen_def.append("")
migen_def.append(" "*8 + "# # #")
migen_def.append("")
migen_def.append(" "*8 + "self.specials += Instance(\"{}\",".format(module))
for name, info in j["modules"][module]["ports"].items():
io_prefix = {
"input": "i",
"output": "o",
"inout": "io"
}[info["direction"]]
migen_def.append(" "*12 + "{}_{}=self.{},".format(io_prefix, name, name))
migen_def.append(" "*8 + ")")
migen_def.append("")
print("\n".join(migen_def))
# keep things clean after us
os.system("rm " + json_file)
if __name__ == "__main__":
main()
| [
"litex.build.tools.write_to_file"
] | [((592, 638), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['"""yosys_v2j.ys"""', 'yosys_v2j'], {}), "('yosys_v2j.ys', yosys_v2j)\n", (611, 638), False, 'from litex.build import tools\n'), ((643, 677), 'os.system', 'os.system', (['"""yosys -q yosys_v2j.ys"""'], {}), "('yosys -q yosys_v2j.ys')\n", (652, 677), False, 'import os\n'), ((760, 772), 'json.load', 'json.load', (['f'], {}), '(f)\n', (769, 772), False, 'import json\n'), ((1921, 1949), 'os.system', 'os.system', (["('rm ' + json_file)"], {}), "('rm ' + json_file)\n", (1930, 1949), False, 'import os\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("K12"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("K13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("R10"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("R13"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("T13"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("R12"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("T12"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("R11"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("F5"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("J4"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("M6"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("N6"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("N11"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("N6"), IOStandard("LVCMOS33")),
# J13 - QSPI_DQ0 - MOSI
# J14 - QSPI_DQ1 - MISO
# K15 - QSPI_DQ2 - ~WP
# K16 - QSPI_DQ3 - ~HOLD
# L12 - QSPI_CS - ~CS
# E8 - CCLK
("spiflash_4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L12")),
Subsignal("dq", Pins("J13", "J14", "K15", "K16")),
IOStandard("LVCMOS33")
),
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L12")),
Subsignal("mosi", Pins("J13")),
Subsignal("miso", Pins("J14")),
Subsignal("wp", Pins("K15")),
Subsignal("hold", Pins("K16")),
IOStandard("LVCMOS33")
),
("serial", 0,
Subsignal("tx", Pins("N16")),
Subsignal("rx", Pins("M16")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"C7 B1 C1 D6 A3 C6 A2 B6",
"B2 B5 E2 C2 C3 B4"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("D3 E3 D1"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("D4"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("C4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("B7"), IOStandard("SSTL15")),
Subsignal("dm", Pins("E5 J5"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"G2 F3 H4 G5 G1 F4 H5 G4",
"H2 H1 K1 J1 L3 L2 K3 K2"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("F2 J3"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("E1 H3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("A5"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("A4"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("D5"), IOStandard("SSTL15")),
Subsignal("odt", Pins("A7"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("E6"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("K5"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]
class Platform(XilinxPlatform):
name = "mimas_a7_mini"
default_clk_name = "clk100"
default_clk_period = 10.0
# From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
# 17,536,096 bits == 2192012 bytes == 0x21728c -- Therefore 0x220000
gateware_size = 0x220000
# Spansion S25FL256S (ID 0x00190201)
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_read_dummy_bits = 10
spiflash_clock_div = 4
spiflash_total_size = int((128/8)*1024*1024) # 256Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
spiflash_model = "n25q128"
def __init__(self, toolchain="vivado", programmer="openocd"):
XilinxPlatform.__init__(self, "xc7a35t-ftg256-1", _io,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/numato_mimas_a7_mini.cfg", flash_proxy_basename=proxy)
elif self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") # FIXME: Spansion S25FL256S
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
| [
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((3723, 3798), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-ftg256-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a35t-ftg256-1', _io, toolchain=toolchain)\n", (3746, 3798), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((4582, 4600), 'litex.build.xilinx.XC3SProg', 'XC3SProg', (['"""nexys4"""'], {}), "('nexys4')\n", (4590, 4600), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((4662, 4718), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""n25q128-3.3v-spi-x1_x2_x4"""'}), "(flash_part='n25q128-3.3v-spi-x1_x2_x4')\n", (4678, 4718), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n')] |
# -*- coding: utf-8 -*-
# Copyright (C) 2022 Antmicro
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.fifo import SyncFIFO
from litex.soc.interconnect import wishbone
class TestFIFOTransceiver(Module):
# Example module supporting constant address burst cycles,
# could be later adapted into Wishbone2CSR
def __init__(self, pads, fifo_depth=8, wait=True):
# Wishbone bus
self.bus = bus = wishbone.Interface()
rd_ack = Signal()
wr_ack = Signal()
bus_sel = Signal()
# Select ACK source
self.comb += [
bus_sel.eq(bus.cyc & bus.stb),
If(bus_sel,
If(bus.we,
bus.ack.eq(wr_ack & bus.stb),
).Else(
bus.ack.eq(rd_ack & bus.stb),
),
).Else(
bus.ack.eq(0)
)
]
# Receiver FIFO (outside -> SoC)
self.submodules.fifo_rx = fifo_rx = SyncFIFO(bus.data_width, fifo_depth)
self.comb += [
# Connect RX FIFO input with pads
fifo_rx.din.eq(pads.dat_rx),
pads.wait_rx.eq(fifo_rx.writable),
fifo_rx.we.eq(pads.stb_rx),
]
# Transmitter FIFO (SoC -> outside)
self.submodules.fifo_tx = fifo_tx = SyncFIFO(bus.data_width, fifo_depth)
bus_write = Signal()
self.comb += [
# Connect TX FIFO output with pads
pads.dat_tx.eq(fifo_tx.dout),
pads.wait_tx.eq(fifo_tx.readable),
fifo_tx.re.eq(pads.stb_tx),
]
# Wishbone FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(bus_sel,
If(bus.we,
NextState("WRITE")
).Else(
NextState("READ")
)
)
)
fsm.act("READ",
If(bus_sel & fifo_rx.readable,
bus.dat_r.eq(fifo_rx.dout),
fifo_rx.re.eq(1),
rd_ack.eq(1),
).Else(
bus.dat_r.eq(0xdeadbeef),
fifo_rx.re.eq(0),
rd_ack.eq(0),
),
# If constant addr. burst, then repeat, else return to idle
If(bus_sel & (bus.cti == 0b001),
NextState("READ")
).Else(
NextState("IDLE")
)
)
fsm.act("WRITE",
fifo_tx.din.eq(bus.dat_w),
If(fifo_tx.writable,
# ACK on WB and TX FIFO input
fifo_tx.we.eq(1),
wr_ack.eq(1),
).Else(
fifo_tx.we.eq(0),
wr_ack.eq(0),
),
# If constant addr. burst, then repeat, else return to idle
If(bus_sel & (bus.cti == 0b001),
NextState("WRITE")
).Else(
NextState("IDLE")
)
) | [
"litex.soc.interconnect.wishbone.Interface"
] | [((856, 876), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (874, 876), False, 'from litex.soc.interconnect import wishbone\n'), ((1405, 1441), 'migen.genlib.fifo.SyncFIFO', 'SyncFIFO', (['bus.data_width', 'fifo_depth'], {}), '(bus.data_width, fifo_depth)\n', (1413, 1441), False, 'from migen.genlib.fifo import SyncFIFO\n'), ((1738, 1774), 'migen.genlib.fifo.SyncFIFO', 'SyncFIFO', (['bus.data_width', 'fifo_depth'], {}), '(bus.data_width, fifo_depth)\n', (1746, 1774), False, 'from migen.genlib.fifo import SyncFIFO\n')] |
#
# This file is part of LiteSPI
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.fsm import FSM, NextState
from litex.soc.interconnect import stream
from litespi.common import *
class LiteSPIPHYModel(Module):
"""LiteSPI PHY simulation model.
The ``LiteSPIPHYModel`` class provides a simulation model that can be used instead of the real PHY.
Parameters
----------
size : int
Simulated flash memory size.
init : []
Initialization data for the flash contents.
Attributes
----------
source : Endpoint(spi_phy_data_layout), out
Data stream.
sink : Endpoint(spi_phy_ctl_layout), in
Control stream.
cs_n : Signal()
Dummy flash CS signal.
"""
def __init__(self, size, init=None):
self.source = source = stream.Endpoint(spi_phy_data_layout)
self.sink = sink = stream.Endpoint(spi_phy_ctl_layout)
mem = Memory(32, size//4, init=init)
read_addr = Signal(32)
self.cs_n = Signal()
read_port = mem.get_port(async_read=True)
self.comb += read_port.adr.eq(read_addr)
self.specials += mem, read_port
commands = {
CMD: [NextValue(read_addr, sink.data[2:31])], # word addressed memory
READ: [NextState("DATA")],
}
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
sink.ready.eq(1),
If(sink.ready & sink.valid,
Case(sink.cmd, commands),
),
)
fsm.act("DATA",
source.valid.eq(1),
source.data.eq(read_port.dat_r),
If(source.ready & source.valid,
NextValue(read_addr, read_addr+1),
NextState("IDLE"),
),
)
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((887, 923), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy_data_layout'], {}), '(spi_phy_data_layout)\n', (902, 923), False, 'from litex.soc.interconnect import stream\n'), ((955, 990), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy_ctl_layout'], {}), '(spi_phy_ctl_layout)\n', (970, 990), False, 'from litex.soc.interconnect import stream\n'), ((1442, 1465), 'migen.genlib.fsm.FSM', 'FSM', ([], {'reset_state': '"""IDLE"""'}), "(reset_state='IDLE')\n", (1445, 1465), False, 'from migen.genlib.fsm import FSM, NextState\n'), ((1375, 1392), 'migen.genlib.fsm.NextState', 'NextState', (['"""DATA"""'], {}), "('DATA')\n", (1384, 1392), False, 'from migen.genlib.fsm import FSM, NextState\n'), ((1839, 1856), 'migen.genlib.fsm.NextState', 'NextState', (['"""IDLE"""'], {}), "('IDLE')\n", (1848, 1856), False, 'from migen.genlib.fsm import FSM, NextState\n')] |
#!/usr/bin/env python3
# This script generates dut.v file for testing TinyFPGA Bootloader
# Disable pylint's E1101, which breaks completely on migen
# pylint:disable=E1101
from migen import Module, Signal, Instance, ClockDomain, If
from migen.fhdl.specials import TSTriple
from migen.fhdl.structure import ResetSignal
from litex.build.generic_platform import Pins, Subsignal
from litex.build.sim.platform import SimPlatform
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import SoCCore
import argparse
_io = [
# Wishbone
("wishbone", 0,
Subsignal("adr", Pins(30)),
Subsignal("dat_r", Pins(32)),
Subsignal("dat_w", Pins(32)),
Subsignal("sel", Pins(4)),
Subsignal("cyc", Pins(1)),
Subsignal("stb", Pins(1)),
Subsignal("ack", Pins(1)),
Subsignal("we", Pins(1)),
Subsignal("cti", Pins(3)),
Subsignal("bte", Pins(2)),
Subsignal("err", Pins(1))
),
("usb", 0,
Subsignal("d_p", Pins(1)),
Subsignal("d_n", Pins(1)),
Subsignal("pullup", Pins(1)),
Subsignal("tx_en", Pins(1)),
),
("clk", 0,
Subsignal("clk48", Pins(1)),
Subsignal("clk12", Pins(1)),
Subsignal("clk16", Pins(1)),
),
("reset", 0, Pins(1)),
]
_connectors = []
class Platform(SimPlatform):
def __init__(self, toolchain="verilator"):
SimPlatform.__init__(self, "sim", _io, _connectors,
toolchain="verilator")
def create_programmer(self):
raise ValueError("programming is not supported")
class _CRG(Module):
def __init__(self, platform):
clk = platform.request("clk")
rst = platform.request("reset")
clk12 = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_16 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
self.clock_domains.cd_usb_48_to_12 = ClockDomain()
clk48 = clk.clk48
clk16 = clk.clk16
self.comb += clk.clk12.eq(clk12)
self.comb += self.cd_usb_16.clk.eq(clk16)
self.comb += self.cd_usb_48.clk.eq(clk48)
self.comb += self.cd_usb_48_to_12.clk.eq(clk48)
clk12_counter = Signal(2)
self.sync.usb_48_to_12 += clk12_counter.eq(clk12_counter + 1)
self.comb += clk12.eq(clk12_counter[1])
self.comb += self.cd_sys.clk.eq(clk12)
self.comb += self.cd_usb_12.clk.eq(clk12)
self.comb += [
ResetSignal("sys").eq(rst),
ResetSignal("usb_12").eq(rst),
ResetSignal("usb_48").eq(rst),
]
class BaseSoC(SoCCore):
SoCCore.csr_map = {
"ctrl": 0, # provided by default (optional)
"crg": 1, # user
"cpu_or_bridge": 8,
"usb": 9,
}
interrupt_map = {
"usb": 3,
}
interrupt_map.update(SoCCore.interrupt_map)
def __init__(self, platform, output_dir="build", **kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
integrated_rom_size=0x0,
integrated_sram_size=0x0,
integrated_main_ram_size=0x0,
csr_address_width=14, csr_data_width=8,
with_uart=False, with_timer=False)
# USB signals
usb_p_tx = Signal()
usb_n_tx = Signal()
usb_p_rx = Signal()
usb_n_rx = Signal()
usb_tx_en = Signal()
usb_p_t = TSTriple()
usb_n_t = TSTriple()
usb_pads = platform.request("usb")
# Assign signals to triple
self.comb += [
If(usb_tx_en,
usb_p_rx.eq(0b1),
usb_n_rx.eq(0b0),
).Else(
usb_p_rx.eq(usb_p_t.i),
usb_n_rx.eq(usb_n_t.i),
),
usb_p_t.oe.eq(usb_tx_en),
usb_n_t.oe.eq(usb_tx_en),
usb_p_t.o.eq(usb_p_tx),
usb_n_t.o.eq(usb_n_tx),
]
# Assign pads to triple
self.specials += usb_p_t.get_tristate(usb_pads.d_p)
self.specials += usb_n_t.get_tristate(usb_pads.d_n)
self.comb += usb_pads.tx_en.eq(usb_tx_en)
self.comb += usb_pads.pullup.eq(0b1)
platform.add_source("../tinyfpga/common/tinyfpga_bootloader.v")
self.specials += Instance("tinyfpga_bootloader",
i_clk_48mhz=self.crg.cd_usb_48.clk,
i_clk=self.crg.cd_usb_48.clk,
i_reset=self.crg.cd_sys.rst,
# USB lines
o_usb_p_tx=usb_p_tx,
o_usb_n_tx=usb_n_tx,
i_usb_p_rx=usb_p_rx,
i_usb_n_rx=usb_n_rx,
o_usb_tx_en=usb_tx_en
)
def main():
parser = argparse.ArgumentParser(
description="Build test file for dummy or eptri module")
parser.add_argument('--dir', metavar='DIRECTORY',
default='build',
help='Output directory (default: %(default)s)')
parser.add_argument('--csr', metavar='CSR',
default='csr.csv',
help='csr file (default: %(default)s)')
args = parser.parse_args()
output_dir = args.dir
platform = Platform()
soc = BaseSoC(platform,
cpu_type=None, cpu_variant=None,
output_dir=output_dir)
builder = Builder(soc, output_dir=output_dir,
csr_csv=args.csr,
compile_software=False)
vns = builder.build(run=False,
build_name="dut")
soc.do_exit(vns)
print("""Simulation build complete. Output files:
{}/gateware/dut.v Source Verilog file. Run this under Cocotb.
""".format(output_dir))
if __name__ == "__main__":
main()
| [
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"litex.build.sim.platform.SimPlatform.__init__",
"litex.soc.integration.builder.Builder",
"litex.soc.integration.soc_core.SoCCore.__init__"
] | [((5337, 5422), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build test file for dummy or eptri module"""'}), "(description='Build test file for dummy or eptri module'\n )\n", (5360, 5422), False, 'import argparse\n'), ((5967, 6044), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'output_dir': 'output_dir', 'csr_csv': 'args.csr', 'compile_software': '(False)'}), '(soc, output_dir=output_dir, csr_csv=args.csr, compile_software=False)\n', (5974, 6044), False, 'from litex.soc.integration.builder import Builder\n'), ((1325, 1332), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (1329, 1332), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((1441, 1515), 'litex.build.sim.platform.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""sim"""', '_io', '_connectors'], {'toolchain': '"""verilator"""'}), "(self, 'sim', _io, _connectors, toolchain='verilator')\n", (1461, 1515), False, 'from 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'o_usb_n_tx': 'usb_n_tx', 'i_usb_p_rx': 'usb_p_rx', 'i_usb_n_rx': 'usb_n_rx', 'o_usb_tx_en': 'usb_tx_en'}), "('tinyfpga_bootloader', i_clk_48mhz=self.crg.cd_usb_48.clk, i_clk=\n self.crg.cd_usb_48.clk, i_reset=self.crg.cd_sys.rst, o_usb_p_tx=\n usb_p_tx, o_usb_n_tx=usb_n_tx, i_usb_p_rx=usb_p_rx, i_usb_n_rx=usb_n_rx,\n o_usb_tx_en=usb_tx_en)\n", (4731, 4970), False, 'from migen import Module, Signal, Instance, ClockDomain, If\n'), ((616, 624), 'litex.build.generic_platform.Pins', 'Pins', (['(30)'], {}), '(30)\n', (620, 624), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((654, 662), 'litex.build.generic_platform.Pins', 'Pins', (['(32)'], {}), '(32)\n', (658, 662), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((692, 700), 'litex.build.generic_platform.Pins', 'Pins', (['(32)'], {}), '(32)\n', (696, 700), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((730, 737), 'litex.build.generic_platform.Pins', 'Pins', (['(4)'], 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# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk12", 0, Pins("H6"), IOStandard("3.3-V LVTTL")), # 12MHz clock
("user_led", 0, Pins("C5"), IOStandard("3.3-V LVTTL")), # CONF Done, inverted polarity
("sw", 0, Pins("E6"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("E7"), IOStandard("3.3-V LVTTL")), # nConfig
("serial", 0,
Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("A4"), IOStandard("3.3-V LVTTL"))
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("B3")),
Subsignal("clk", Pins("A3")),
Subsignal("dq", Pins("A2", "B2", "B9", "C4")),
IOStandard("3.3-V LVTTL")
),
("spiflash", 0,
Subsignal("cs_n", Pins("B3")),
Subsignal("clk", Pins("A3")),
Subsignal("mosi", Pins("A2")),
Subsignal("miso", Pins("B2")),
Subsignal("wp", Pins("B9")),
Subsignal("hold", Pins("C4")),
IOStandard("3.3-V LVTTL"),
),
("vga", 0,
Subsignal("red", Pins("K11", "J13", "J12", "L12", "N3", "N2")),
Subsignal("green", Pins("K2", "K1", "J2", "J1", "H4", "H5")),
Subsignal("blue", Pins("K10", "H8", "E4", "F1", "E3", "D1")),
Subsignal("hsync", Pins("C2")),
Subsignal("vsync", Pins("C1")),
IOStandard("3.3-V LVTTL"),
),
("sdram_clock", 0, Pins("M9"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("K6 M5 N5 J8 N10 M11 N9 L10 M13 N8 N4 M10")), #0, 1, ...
Subsignal("ba", Pins("N6 K8")),
Subsignal("cs_n", Pins("M4")),
Subsignal("cke", Pins("M8")),
Subsignal("ras_n", Pins("M7")),
Subsignal("cas_n", Pins("N7")),
Subsignal("we_n", Pins("K7")),
Subsignal("dq", Pins("D11 G10 F10 F9 E10 D9 G9 F8 F13 E12 E13 D12 C12 B12 B13 A12")),
Subsignal("dm", Pins("E9 F12")),
IOStandard("3.3-V LVTTL")
),
# ("epcs", 0,
# Subsignal("data0", Pins("H2")),
# Subsignal("dclk", Pins("A3")),
# Subsignal("ncs0", Pins("B3")),
# Subsignal("asd0", Pins("C1")),
# IOStandard("3.3-V LVTTL")
# ),
# ("i2c", 0,
# Subsignal("sclk", Pins("F2")),
# Subsignal("sdat", Pins("F1")),
# IOStandard("3.3-V LVTTL")
# ),
# ("g_sensor", 0,
# Subsignal("cs_n", Pins("G5")),
# Subsignal("int", Pins("M2")),
# IOStandard("3.3-V LVTTL")
# ),
("gpio_leds", 0,
Pins("D8 A8 A9 C9 A10 B10 A11 C10"),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk12"
default_clk_period = 83
def __init__(self, device):
AlteraPlatform.__init__(self, device, _io)
self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
def create_programmer(self):
return USBBlaster()
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"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.programmer.USBBlaster"
] | [((3082, 3124), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', 'device', '_io'], {}), '(self, device, _io)\n', (3105, 3124), False, 'from litex.build.altera import AlteraPlatform\n'), ((3471, 3483), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (3481, 3483), False, 'from litex.build.altera.programmer import USBBlaster\n')] |
#!/usr/bin/env python3
import sys
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
class BIST:
def __init__(self, tx_name, rx_name):
self._tx_enable = getattr(wb.regs, tx_name + "_enable")
self._rx_enable = getattr(wb.regs, rx_name + "_enable")
self._rx_errors = getattr(wb.regs, rx_name + "_errors")
def run(self):
self._tx_enable.write(0)
self._rx_enable.write(0)
self._tx_enable.write(1)
time.sleep(0.1)
self._rx_enable.write(1)
time.sleep(1)
return self._rx_errors.read()
print("GTP0 TX Clk: {:d}".format(wb.regs.gtp0_tx_freq_value.read()))
print("GTP0 RX Clk: {:d}".format(wb.regs.gtp0_rx_freq_value.read()))
print("GTP0 TX Clk: {:d}".format(wb.regs.gtp1_tx_freq_value.read()))
print("GTP0 RX Clk: {:d}".format(wb.regs.gtp1_rx_freq_value.read()))
print("Running GTP0 BIST...")
gtp0_bist = BIST("gtp0_tx_bist", "gtp0_rx_bist")
errors = gtp0_bist.run()
print("Errors: {}".format(errors))
print("Running GTP1 BIST...")
gtp1_bist = BIST("gtp1_tx_bist", "gtp1_rx_bist")
errors = gtp1_bist.run()
print("Errors: {}".format(errors))
# # #
wb.close()
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"litex.RemoteClient"
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#
# This file is part of LiteDRAM.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.gen.sim import run_simulation
from litex.soc.interconnect import wishbone
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
from litedram.common import LiteDRAMNativePort
from test.common import DRAMMemory, MemoryTestDataMixin
class TestWishbone(MemoryTestDataMixin, unittest.TestCase):
def wishbone_readback_test(self, pattern, mem_expected, wishbone, port, base_address=0):
class DUT(Module):
def __init__(self):
self.port = port
self.wb = wishbone
self.submodules += LiteDRAMWishbone2Native(
wishbone = self.wb,
port = self.port,
base_address = base_address)
self.mem = DRAMMemory(port.data_width, len(mem_expected))
def main_generator(dut):
for adr, data in pattern:
yield from dut.wb.write(adr, data)
data_r = (yield from dut.wb.read(adr))
self.assertEqual(data_r, data)
dut = DUT()
generators = [
main_generator(dut),
dut.mem.write_handler(dut.port),
dut.mem.read_handler(dut.port),
]
run_simulation(dut, generators, vcd_name='sim.vcd')
self.assertEqual(dut.mem.mem, mem_expected)
def test_wishbone_8bit(self):
# Verify Wishbone with 8-bit data width.
data = self.pattern_test_data["8bit"]
wb = wishbone.Interface(adr_width=30, data_width=8)
port = LiteDRAMNativePort("both", address_width=30, data_width=8)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_32bit(self):
# Verify Wishbone with 32-bit data width.
data = self.pattern_test_data["32bit"]
wb = wishbone.Interface(adr_width=30, data_width=32)
port = LiteDRAMNativePort("both", address_width=30, data_width=32)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_64bit(self):
# Verify Wishbone with 64-bit data width.
data = self.pattern_test_data["64bit"]
wb = wishbone.Interface(adr_width=30, data_width=64)
port = LiteDRAMNativePort("both", address_width=30, data_width=64)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_64bit_to_32bit(self):
# Verify Wishbone with 64-bit data width down-converted to 32-bit data width.
data = self.pattern_test_data["64bit_to_32bit"]
wb = wishbone.Interface(adr_width=30, data_width=64)
port = LiteDRAMNativePort("both", address_width=30, data_width=32)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_32bit_to_8bit(self):
# Verify Wishbone with 32-bit data width down-converted to 8-bit data width.
data = self.pattern_test_data["32bit_to_8bit"]
wb = wishbone.Interface(adr_width=30, data_width=32)
port = LiteDRAMNativePort("both", address_width=30, data_width=8)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_8bit_to_32bit(self):
# Verify Wishbone with 8-bit data width up-converted to 32-bit data width.
data = self.pattern_test_data["8bit_to_32bit"]
wb = wishbone.Interface(adr_width=30, data_width=8)
port = LiteDRAMNativePort("both", address_width=30, data_width=32)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_32bit_to_64bit(self):
# Verify Wishbone with 32-bit data width up-converted to 64-bit data width.
data = self.pattern_test_data["32bit_to_64bit"]
wb = wishbone.Interface(adr_width=30, data_width=32)
port = LiteDRAMNativePort("both", address_width=30, data_width=64)
self.wishbone_readback_test(data["pattern"], data["expected"], wb, port)
def test_wishbone_32bit_base_address(self):
# Verify Wishbone with 32-bit data width and non-zero base address.
data = self.pattern_test_data["32bit"]
wb = wishbone.Interface(adr_width=30, data_width=32)
port = LiteDRAMNativePort("both", address_width=30, data_width=32)
origin = 0x10000000
# add offset (in data words)
pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
def test_wishbone_64bit_to_32bit_base_address(self):
# Verify Wishbone with 64-bit data width down-converted to 32-bit data width and non-zero base address.
data = self.pattern_test_data["64bit_to_32bit"]
wb = wishbone.Interface(adr_width=30, data_width=64)
port = LiteDRAMNativePort("both", address_width=30, data_width=32)
origin = 0x10000000
pattern = [(adr + origin//(64//8), data) for adr, data in data["pattern"]]
self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
def test_wishbone_32bit_to_8bit_base_address(self):
# Verify Wishbone with 32-bit data width down-converted to 8-bit data width and non-zero base address.
data = self.pattern_test_data["32bit_to_8bit"]
wb = wishbone.Interface(adr_width=30, data_width=32)
port = LiteDRAMNativePort("both", address_width=30, data_width=8)
origin = 0x10000000
pattern = [(adr + origin//(32//8), data) for adr, data in data["pattern"]]
self.wishbone_readback_test(pattern, data["expected"], wb, port, base_address=origin)
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wishbone\n'), ((5640, 5698), 'litedram.common.LiteDRAMNativePort', 'LiteDRAMNativePort', (['"""both"""'], {'address_width': '(30)', 'data_width': '(8)'}), "('both', address_width=30, data_width=8)\n", (5658, 5698), False, 'from litedram.common import LiteDRAMNativePort\n'), ((779, 868), 'litedram.frontend.wishbone.LiteDRAMWishbone2Native', 'LiteDRAMWishbone2Native', ([], {'wishbone': 'self.wb', 'port': 'self.port', 'base_address': 'base_address'}), '(wishbone=self.wb, port=self.port, base_address=\n base_address)\n', (802, 868), False, 'from litedram.frontend.wishbone import LiteDRAMWishbone2Native\n')] |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import general
from litex.soc.integration import soc as litex_soc
from litex.soc.integration import builder
from litex.build.xilinx import vivado
class DigilentArtySoCWorkflow(general.GeneralSoCWorkflow):
"""Specializes the general workflow for the Digilent Arty."""
def make_soc(self, **kwargs) -> litex_soc.LiteXSoC:
"""Runs the general make_soc with a l2_size parameter,"""
""" and jtagbone disabled. """
return super().make_soc(l2_size=8 * 1024, with_jtagbone = False, **kwargs)
def build_soc(self, soc: litex_soc.LiteXSoC, **kwargs) -> builder.Builder:
"""Specializes build_soc to add Vivado args if needed."""
if isinstance(soc.platform.toolchain, vivado.XilinxVivadoToolchain):
kwargs.update(vivado.vivado_build_argdict(self.args))
return super().build_soc(soc, **kwargs)
| [
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((1408, 1446), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado.vivado_build_argdict', (['self.args'], {}), '(self.args)\n', (1435, 1446), False, 'from litex.build.xilinx import vivado\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "nextpnr-ecp5", "yosys"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
import sys
import argparse
import optparse
import subprocess
import os
import shutil
from migen import *
from rtl.platform import bosonHDMI_r0d3
from litex.build.generic_platform import *
from litex.soc.cores.clock import *
from rtl.ecp5_dynamic_pll import ECP5PLL, period_ns
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.gpio import GPIOOut, GPIOIn
from litex.soc.interconnect import stream, wishbone
from litex.soc.interconnect.stream import Endpoint, EndpointDescription, SyncFIFO, AsyncFIFO, Monitor
from litex.soc.interconnect.csr import *
from migen.genlib.misc import timeline
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from rtl.prbs import PRBSStream
from rtl.edge_detect import EdgeDetect
from rtl.wb_streamer import StreamReader, StreamWriter, StreamBuffers
from rtl.hdmi import HDMI
from rtl.rgb_led import RGB
from rtl.reboot import Reboot
from rtl.buttons import Button
from rtl.streamable_hyperram import StreamableHyperRAM
from rtl.buffered_csr_block import BufferedCSRBlock
from rtl.video.terminal import Terminal
from rtl.video.boson import Boson
from rtl.video.YCrCb import YCbCr2RGB, YCbCr422to444, ycbcr444_layout
from rtl.video.simulated_video import SimulatedVideo
from rtl.video.video_debug import VideoDebug
from rtl.video.video_stream import VideoStream
from rtl.video.framer import Framer, framer_params
from rtl.video.scaler import Scaler
class _CRG(Module, AutoCSR):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_video = ClockDomain()
self.clock_domains.cd_video_shift = ClockDomain()
self.clock_domains.cd_hr = ClockDomain()
self.clock_domains.cd_hr_90 = ClockDomain()
self.clock_domains.cd_hr2x = ClockDomain()
self.clock_domains.cd_hr2x_90 = ClockDomain()
self.clock_domains.cd_hr2x_ = ClockDomain()
self.clock_domains.cd_hr2x_90_ = ClockDomain()
self.clock_domains.cd_init = ClockDomain()
# # #
# clk / rst
clk48 = platform.request("clk48")
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_hr2x, sys_clk_freq*2, margin=0)
pll.create_clkout(self.cd_hr2x_90, sys_clk_freq*2, phase=1, margin=0) # SW tunes this phase during init
self.specials += [
]
self.comb += self.cd_sys.clk.eq(self.cd_hr.clk)
self.comb += self.cd_init.clk.eq(clk48)
pixel_clk = 40e6
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
self.submodules.video_pll = video_pll = ECP5PLL()
video_pll.register_clkin(clk48, 48e6)
video_pll.create_clkout(self.cd_video, pixel_clk, margin=0)
video_pll.create_clkout(self.cd_video_shift, pixel_clk*5, margin=0)
video_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
self.comb += self.cd_usb_48.clk.eq(clk48)
platform.add_period_constraint(self.cd_usb_12.clk, period_ns(12e6))
platform.add_period_constraint(self.cd_usb_48.clk, period_ns(48e6))
platform.add_period_constraint(self.cd_sys.clk, period_ns(sys_clk_freq))
platform.add_period_constraint(clk48, period_ns(48e6))
platform.add_period_constraint(self.cd_video.clk, period_ns(pixel_clk))
platform.add_period_constraint(self.cd_video_shift.clk, period_ns(pixel_clk * 5))
self._slip_hr2x = CSRStorage()
self._slip_hr2x90 = CSRStorage()
# ECLK stuff
self.specials += [
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = self._slip_hr2x.storage,
i_CLKI = self.cd_hr2x.clk,
i_RST = ~pll.locked,
o_CDIVX = self.cd_hr.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = self._slip_hr2x90.storage,
i_CLKI = self.cd_hr2x_90.clk,
i_RST = ~pll.locked,
o_CDIVX = self.cd_hr_90.clk),
#AsyncResetSynchronizer(self.cd_hr, reset),
#AsyncResetSynchronizer(self.cd_sys, reset)
]
self._phase_sel = CSRStorage(2)
self._phase_dir = CSRStorage()
self._phase_step = CSRStorage()
self._phase_load = CSRStorage()
self.comb += [
self.pll.phase_sel.eq(self._phase_sel.storage),
self.pll.phase_dir.eq(self._phase_dir.storage),
self.pll.phase_step.eq(self._phase_step.storage),
self.pll.phase_load.eq(self._phase_load.storage),
]
# OSC-G for simulated video streams
oscg_clk = Signal()
self.clock_domains.cd_oscg_38M = ClockDomain()
self.specials += Instance("OSCG",
p_DIV=8,
o_OSC=oscg_clk
)
self.comb += self.cd_oscg_38M.clk.eq(oscg_clk)
class DiVA_SoC(SoCCore):
csr_map = {
"rgb" : 10,
"crg" : 11,
"hyperram" : 12,
"terminal" : 13,
"analyzer" : 14,
"hdmi_i2c" : 15,
"i2c0" : 16,
"button" : 18,
"reader" : 19,
"writer" : 20,
"buffers" : 21,
"prbs" : 23,
"reboot" : 25,
"video_debug": 26,
"framer" : 27,
"scaler" : 28,
"boson" : 29,
"pipeline_config" : 30,
}
csr_map.update(SoCCore.csr_map)
mem_map = {
"hyperram" : 0x10000000,
"terminal" : 0x30000000,
}
mem_map.update(SoCCore.mem_map)
interrupt_map = {
}
interrupt_map.update(SoCCore.interrupt_map)
def __init__(self):
self.platform = platform = bosonHDMI_r0d3.Platform()
sys_clk_freq = 82.5e6
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
cpu_type='serv', with_uart=True, uart_name='stream',
csr_data_width=32,
ident="Boson DiVA SoC", ident_version=True, wishbone_timeout_cycles=128,
integrated_rom_size=32*1024)
self.platform.toolchain.build_template[0] = "yosys -q -l {build_name}.rpt {build_name}.ys"
self.platform.toolchain.build_template[1] += f" --log {platform.name}.log --router router1"
# Fake a UART stream, to enable easy firmware reuse.
self.comb += self.uart.source.ready.eq(1)
# crg
self.submodules.crg = _CRG(platform, sys_clk_freq)
## Create VGA terminal
self.submodules.terminal = terminal = ClockDomainsRenamer({'vga':'video'})(Terminal())
self.register_mem("terminal", self.mem_map["terminal"], terminal.bus, size=0x100000)
# User inputs
button = platform.request("button")
self.submodules.button = Button(button)
self.submodules.rgb = RGB(platform.request("rgb_led"))
# HyperRAM
self.submodules.writer = writer = StreamWriter()
self.submodules.reader = reader = StreamReader()
# Attach a StreamBuffer module to handle buffering of frames
self.submodules.buffers = buffers = StreamBuffers()
self.comb += [
buffers.rx_release.eq(reader.evt_done),
reader.start_address.eq(buffers.rx_buffer),
writer.start_address.eq(buffers.tx_buffer),
]
self.submodules.hyperram = hyperram = StreamableHyperRAM(platform.request("hyperRAM"), devices=[reader, writer])
self.register_mem("hyperram", self.mem_map['hyperram'], hyperram.bus, size=0x800000)
# Boson video stream
self.submodules.boson = boson = Boson(platform, platform.request("boson"), sys_clk_freq)
self.submodules.YCbCr = ycrcb = ClockDomainsRenamer({"sys":"boson_rx"})(ResetInserter()(YCbCr2RGB()))
self.submodules.YCbCr422_444 = ycrcb422_444 = ClockDomainsRenamer({"sys":"boson_rx"})(YCbCr422to444())
fifo = AsyncFIFO([("data", 32)], depth=512)
fifo = ResetInserter(["read","write"])(fifo)
fifo = ClockDomainsRenamer({"read":"sys","write":"boson_rx"})(fifo)
self.submodules.video_debug = video_debug = ClockDomainsRenamer({"pixel":"boson_rx"})(VideoDebug(int(self.clk_freq)))
self.submodules.pipeline_config = pipeline_config = BufferedCSRBlock(
[
("scaler_enable", 1),
("scaler_fill", 1),
("scaler_bank", 1),
] + framer_params()
)
self.submodules.framer = framer = Framer()
self.comb += [
framer.params.x_start.eq(pipeline_config.x_start),
framer.params.y_start.eq(pipeline_config.y_start),
framer.params.x_stop.eq(pipeline_config.x_stop),
framer.params.y_stop.eq(pipeline_config.y_stop),
]
self.submodules.scaler = scaler = ResetInserter(["video"])(ClockDomainsRenamer({"sys":"video", "cpu":"sys"})((Scaler())))
self.submodules.fifo2 = fifo2 = ResetInserter()(ClockDomainsRenamer({"sys":"video"})(SyncFIFO([("data", 32)], depth=32)))
self.submodules += fifo
self.comb += [
video_debug.vsync.eq(boson.vsync),
video_debug.hsync.eq(boson.hsync),
boson.source.connect(ycrcb422_444.sink, omit=['data']),
ycrcb422_444.source.connect(ycrcb.sink),
ycrcb.source.connect(fifo.sink, omit=['r','g','b']),
ycrcb422_444.sink.y.eq(boson.source.data[0:8]),
ycrcb422_444.sink.cb_cr.eq(boson.source.data[8:16]),
fifo.sink.data[0:8].eq(ycrcb.source.r),
fifo.sink.data[8:16].eq(ycrcb.source.g),
fifo.sink.data[16:24].eq(ycrcb.source.b),
fifo.source.connect(reader.sink),
]
boson_stream_start = Signal()
reader.add_source(fifo.source, "boson_stream", boson_stream_start)
## HDMI output
hdmi_pins = platform.request('hdmi')
self.submodules.hdmi = hdmi = HDMI(platform, hdmi_pins)
self.submodules.hdmi_i2c = I2CMaster(platform.request("hdmi_i2c"))
# I2C
self.submodules.i2c0 = I2CMaster(platform.request("i2c"))
self.submodules.reboot = Reboot(platform.request("rst_n"))
fifo0 = AsyncFIFO([("data", 32)], depth=128)
fifo0 = ResetInserter(["read","write"])(fifo0)
fifo0 = ClockDomainsRenamer({"read":"video","write":"sys"})(fifo0)
self.submodules += fifo0
self.comb += [
If(pipeline_config.scaler_enable,
fifo0.source.connect(scaler.sink),
scaler.source.connect(fifo2.sink),
fifo2.source.connect(framer.sink),
).Else(
fifo0.source.connect(framer.sink),
),
writer.short.eq(pipeline_config.scaler_fill),
scaler.bank.eq(pipeline_config.scaler_bank)
]
boson_sink_start = Signal()
writer.add_sink(fifo0.sink, "boson", boson_sink_start)
# prbs tester
self.submodules.prbs = PRBSStream()
reader.add_source(self.prbs.source.source, "prbs")
writer.add_sink(self.prbs.sink.sink, "prbs")
# enable
self.submodules.vsync_rise = vsync_rise = EdgeDetect(mode="rise", input_cd="video", output_cd="sys")
self.comb += vsync_rise.i.eq(terminal.vsync)
self.submodules.vsync_rise_term = vsync_rise_term = EdgeDetect(mode="rise", input_cd="video", output_cd="video")
self.comb += vsync_rise_term.i.eq(terminal.vsync)
self.submodules.vsync_fall_term = vsync_fall_term = EdgeDetect(mode="fall", input_cd="video", output_cd="video")
self.comb += vsync_fall_term.i.eq(terminal.vsync)
self.submodules.vsync_boson = vsync_boson = EdgeDetect(mode="fall", input_cd="boson_rx", output_cd="sys")
self.comb += vsync_boson.i.eq(boson.vsync)
self.comb += [
scaler.reset_video.eq(vsync_rise_term.o),
fifo2.reset.eq(vsync_rise_term.o),
fifo0.reset_read.eq(vsync_rise_term.o),
fifo0.reset_write.eq(vsync_rise.o),
pipeline_config.csr_sync.eq(vsync_rise_term.o)
]
reader_ps = PulseSynchronizer("video", "sys")
self.comb += reader_ps.i.eq(vsync_rise_term.o)
self.comb += boson_sink_start.eq(reader_ps.o)
self.submodules += reader_ps
# delay vsync pulse from boson by 500 clocks, then use it to reset the fifo
fifo_rst = Signal()
self.sync += [
timeline(vsync_boson.o, [
(101, [fifo_rst.eq(1)]), # Reset FIFO
(102, [fifo_rst.eq(0)]), # Clear Reset
(110, [boson_stream_start.eq(1)]),
(111, [boson_stream_start.eq(0)])
])
]
#self.specials += MultiReg(fifo_rst, fifo.reset_write, odomain="boson_rx")
fifo_rst_ps = PulseSynchronizer("sys", "boson_rx")
self.comb += fifo_rst_ps.i.eq(fifo_rst)
self.comb += fifo.reset_write.eq(fifo_rst_ps.o)
self.comb += fifo.reset_read.eq(fifo_rst)
self.submodules += fifo_rst_ps
terminal_mask = Signal()
## Connect VGA pins
self.comb += [
fifo.reset_read.eq(fifo_rst),
ycrcb.reset.eq(fifo_rst),
ycrcb422_444.reset.eq(fifo_rst),
# attach framer to video generator
framer.vsync.eq(terminal.vsync),
framer.hsync.eq(terminal.hsync),
hdmi.vsync.eq(terminal.vsync),
hdmi.hsync.eq(terminal.hsync),
hdmi.blank.eq(terminal.blank),
# Mask Through on 0xFFFF00 pixels
terminal_mask.eq((terminal.red == 0xaa) & (terminal.green == 0x00) & (terminal.blue == 0xaa)),
If(terminal_mask,
If(framer.data_valid,
hdmi.r.eq(framer.red),
hdmi.g.eq(framer.green),
hdmi.b.eq(framer.blue),
)
).Else(
hdmi.r.eq(terminal.red),
hdmi.g.eq(terminal.green),
hdmi.b.eq(terminal.blue),
)
]
usb_pads = self.platform.request("usb")
# Select Boson as USB target
if hasattr(usb_pads, "sw_sel"):
self.comb += usb_pads.sw_sel.eq(0)
# Enable USB
if hasattr(usb_pads, "sw_oe"):
self.comb += usb_pads.sw_oe.eq(0)
analyser = False
if analyser:
# USB with Clock-Domain-Crossing support
import os
import sys
os.system("git clone https://github.com/gregdavill/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
import valentyusb.usbcore.io as usbio
import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
usb_pads = self.platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.uart_usb = cdc_eptri.CDCUsb(usb_iobuf)
# Select ECP5 as USB target
if hasattr(usb_pads, "sw_sel"):
self.comb += usb_pads.sw_sel.eq(1)
# Enable USB
if hasattr(usb_pads, "sw_oe"):
self.comb += usb_pads.sw_oe.eq(0)
self.submodules.bridge = Stream2Wishbone(self.uart_usb, sys_clk_freq)
self.add_wb_master(self.bridge.wishbone)
self.submodules.analyzer = LiteScopeAnalyzer(hyperram.dbg, 64)
# Add git version into firmware
def get_git_revision():
try:
r = subprocess.check_output(["git", "rev-parse", "--short", "HEAD"],
stderr=subprocess.DEVNULL)[:-1].decode("utf-8")
except:
r = "--------"
return r
self.add_constant("DIVA_GIT_SHA1", get_git_revision())
def do_exit(self, vns):
if hasattr(self, "analyzer"):
self.analyzer.export_csv(vns, "test/analyzer.csv")
def PackageFirmware(self, builder):
self.finalize()
os.makedirs(builder.output_dir, exist_ok=True)
src_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "firmware", "DiVA-fw"))
builder.add_software_package("DiVA-fw", src_dir)
builder._prepare_rom_software()
builder._generate_includes()
builder._generate_rom_software(compile_bios=False)
firmware_file = os.path.join(builder.output_dir, "software", "DiVA-fw","DiVA-fw.bin")
firmware_data = get_mem_data(firmware_file, self.cpu.endianness)
self.initialize_rom(firmware_data)
# lock out compiling firmware during build steps
builder.compile_software = False
def CreateFirmwareInit(init, output_file):
content = ""
for d in init:
content += "{:08x}\n".format(d)
with open(output_file, "w") as o:
o.write(content)
def main():
parser = argparse.ArgumentParser(
description="Build DiVA Gateware")
parser.add_argument(
"--update-firmware", default=False, action='store_true',
help="compile firmware and update existing gateware"
)
args = parser.parse_args()
soc = DiVA_SoC()
builder = Builder(soc, output_dir="build", csr_csv="build/csr.csv")
# Build firmware
soc.PackageFirmware(builder)
# Check if we have the correct files
firmware_file = os.path.join(builder.output_dir, "software", "DiVA-fw", "DiVA-fw.bin")
firmware_data = get_mem_data(firmware_file, soc.cpu.endianness)
firmware_init = os.path.join(builder.output_dir, "software", "DiVA-fw", "DiVA-fw.init")
CreateFirmwareInit(firmware_data, firmware_init)
rand_rom = os.path.join(builder.output_dir, "gateware", "rand.data")
input_config = os.path.join(builder.output_dir, "gateware", f"{soc.platform.name}.config")
output_config = os.path.join(builder.output_dir, "gateware", f"{soc.platform.name}_patched.config")
# If we don't have a random file, create one, and recompile gateware
if (os.path.exists(rand_rom) == False) or (args.update_firmware == False):
os.makedirs(os.path.join(builder.output_dir,'gateware'), exist_ok=True)
os.makedirs(os.path.join(builder.output_dir,'software'), exist_ok=True)
os.system(f"ecpbram --generate {rand_rom} --seed {0} --width {32} --depth {soc.integrated_rom_size}")
# patch random file into BRAM
data = []
with open(rand_rom, 'r') as inp:
for d in inp.readlines():
data += [int(d, 16)]
soc.initialize_rom(data)
# Build gateware
vns = builder.build(nowidelut=False)
soc.do_exit(vns)
# Insert Firmware into Gateware
os.system(f"ecpbram --input {input_config} --output {output_config} --from {rand_rom} --to {firmware_init}")
# create a compressed bitstream
output_bit = os.path.join(builder.output_dir, "gateware", "DiVA.dfu")
os.system(f"ecppack --freq 38.8 --compress --input {output_config} --bit {output_bit}")
# Add DFU suffix
os.system(f"dfu-suffix -p 16d0 -d 0fad -a {output_bit}")
print(
f"""DiVA build complete! Output files:
Bitstream file. (Compressed, Higher CLK) Load this into FLASH.
{builder.output_dir}/gateware/DiVA.bit
Source Verilog file. Useful for debugging issues.
{builder.output_dir}/gateware/top.v
""")
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.AsyncFIFO"
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import terasic_sockit
from litex.soc.cores.clock import CycloneVPLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.video import VideoVGAPHY
from litex.build.io import DDROutput
from litedram.modules import AS4C32M16
from litedram.phy import HalfRateGENSDRPHY, GENSDRPHY
# DRAM Module for XS board v2.2 ----------------------------------------------------------------------
# FIXME: Move to litedram.modules.
from litedram.modules import _TechnologyTimings, _SpeedgradeTimings, SDRModule
class W9825G6KH6(SDRModule):
"""
Winbond W9825G6KH-6 chip on Mister SDRAM XS board v2.2
This is the smallest and cheapest module.
running it at 100MHz (1:2 if system clock is 50MHz)
works well on my SoCKit and all 32MB test error free
I get a number of data errors if I run it at 50MHz,
so this defaults to 1:2. If you want to use a higher
system clock (eg 100MHz), you might want to consider
using 1:1 clocking, because the -6 speedgrade
can be clocked up to 166MHz (CL3) or 133MHz (CL2)
"""
# geometry
nbanks = 4
nrows = 8192
ncols = 512
@staticmethod
def clock_cycles_to_ns(cycles, clk_freq, sdram_rate) -> float:
d = {
"1:1" : 1,
"1:2" : 2,
"1:4" : 4
}
return cycles / (d[sdram_rate] * clk_freq) / 1e-9
def __init__(self, clk_freq, sdram_rate):
# The datasheet specifies tWr in clock cycles, not in
# ns but to me it looks like litedram expects
# ns for these two parameters, so I have to convert them
# to ns first.
tWr = self.clock_cycles_to_ns(2, clk_freq, sdram_rate)
tRRD = self.clock_cycles_to_ns(2, clk_freq, sdram_rate)
self.technology_timings = _TechnologyTimings(tREFI=64e6/8000, tWTR=(2, None), tCCD=(1, None), tRRD=(None, tRRD))
self.speedgrade_timings = {"default": _SpeedgradeTimings(tRP=15, tRCD=15, tWR=tWr, tRFC=(None, 60), tFAW=None, tRAS=42)}
super().__init__(clk_freq, sdram_rate)
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_sdram=False, sdram_rate="1:2", with_video_terminal=False):
self.sdram_rate = sdram_rate
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
if with_video_terminal:
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
if with_sdram:
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# Clk / Rst
clk50 = platform.request("clk50")
# PLL
self.submodules.pll = pll = CycloneVPLL(speedgrade="-C6")
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if with_video_terminal:
pll.create_clkout(self.cd_vga, 65e6)
if with_sdram:
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
# SDRAM clock
if with_sdram:
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), revision="revd", sdram_rate="1:2", mister_sdram=None, with_video_terminal=False, **kwargs):
platform = terasic_sockit.Platform(revision)
# Defaults to UART over JTAG because serial is attached to the HPS and cannot be used.
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "jtag_atlantic"
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on the Terasic SoCKit",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_sdram=mister_sdram != None, sdram_rate=sdram_rate, with_video_terminal=with_video_terminal)
# SDR SDRAM --------------------------------------------------------------------------------
if mister_sdram is not None:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
sdrphy_mod = {"xs_v22": W9825G6KH6, "xs_v24": AS4C32M16}[mister_sdram]
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdrphy_mod(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Video Terminal ---------------------------------------------------------------------------
if with_video_terminal:
vga_pads = platform.request("vga")
self.comb += [ vga_pads.sync_n.eq(0), vga_pads.blank_n.eq(1) ]
self.specials += DDROutput(i1=1, i2=0, o=vga_pads.clk, clk=ClockSignal("vga"))
self.submodules.videophy = VideoVGAPHY(vga_pads, clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="1024x768@60Hz", clock_domain="vga")
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on the Terasic SoCKit")
parser.add_argument("--single-rate-sdram", action="store_true", help="clock SDRAM with 1x the sytem clock (instead of 2x)")
parser.add_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card")
parser.add_argument("--mister-sdram-xs-v24", action="store_true", help="Use optional MiSTer SDRAM module XS v2.4 on J2 on GPIO daughter card")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--revision", default="revd", help="Board revision: revb (default), revc or revd")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
revision = args.revision,
sdram_rate = "1:1" if args.single_rate_sdram else "1:2",
mister_sdram = "xs_v22" if args.mister_sdram_xs_v22 else "xs_v24" if args.mister_sdram_xs_v24 else None,
with_video_terminal = args.with_video_terminal,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof"))
if __name__ == "__main__":
main()
| [
"litex.soc.cores.clock.CycloneVPLL",
"litex.soc.cores.video.VideoVGAPHY"
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# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from migen.genlib.cdc import MultiReg
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO
from litex.soc.interconnect.stream import *
def rgb_layout(dw):
return [("r", dw), ("g", dw), ("b", dw)]
def W(x):
a = -0.5
if abs(x) <= 1:
return (a+2)*abs(x)**3 - (a+3)*abs(x)**2 + 1
if abs(x) < 2:
return (a)*abs(x)**3 - (5*a)*abs(x)**2 + 8*a*abs(x) - 4*a
return 0
class StallablePipelineActor(BinaryActor):
def __init__(self, latency):
self.latency = latency
self.pipe_ce = Signal()
self.busy = Signal()
self.stall = Signal()
self.output_hold = Signal()
BinaryActor.__init__(self, latency)
def build_binary_control(self, sink, source, latency):
busy = 0
valid = sink.valid
stall_n = Signal()
for i in range(latency):
valid_n = Signal()
self.sync += If(self.pipe_ce & ~(~stall_n & self.stall), valid_n.eq(valid))
valid = valid_n
busy = busy | valid
self.comb += [
self.pipe_ce.eq((source.ready | ~valid)),
sink.ready.eq(self.pipe_ce & ~self.stall),
source.valid.eq(valid & ~self.output_hold),
self.busy.eq(busy)
]
self.sync += [
If(self.pipe_ce,
stall_n.eq(self.stall)
)
]
first = sink.valid & sink.first
last = sink.valid & sink.last
for i in range(latency):
first_n = Signal(reset_less=True)
last_n = Signal(reset_less=True)
self.sync += \
If(self.pipe_ce & ~self.stall,
first_n.eq(first),
last_n.eq(last)
)
first = first_n
last = last_n
self.comb += [
source.first.eq(first),
source.last.eq(last)
]
# Simple datapath that create n-taps of a delayed signal.
@CEInserter()
class MultiTapDatapath(Module):
def __init__(self, taps):
self.sink = sink = Record(rgb_layout(8))
self.source = source = Record(rgb_layout(8))
self.ntaps = taps
# # #
# delay rgb signals
rgb_delayed = [sink]
for i in range(taps):
rgb_n = Record(rgb_layout(8))
for name in ["r", "g", "b"]:
self.sync += getattr(rgb_n, name).eq(getattr(rgb_delayed[-1], name))
rgb_delayed.append(rgb_n)
self.tap = rgb_delayed
class FilterElement(Module):
latency = 1
def __init__(self, dw=8):
self.sink = sink = Signal(dw)
self.source = source = Signal((24, True))
self.coef = coef = Signal((10,True))
sig_in = Signal((dw+1, True))
sig_out = Signal((24,True))
mult = Signal(24)
self.comb += [
sig_in[:dw].eq(sink),
sig_in[-1].eq(0),
source.eq(sig_out)
]
self.sync += mult.eq(sig_in * coef)
self.comb += sig_out.eq(mult)
@CEInserter()
class RGBFilterElement(Module):
def __init__(self):
self.sink = sink = Record(rgb_layout(8))
self.source = source = Record(rgb_layout((24, True)))
self.coef = coef = Signal((10,True))
fr = FilterElement()
fg = FilterElement()
fb = FilterElement()
self.submodules += fr, fg, fb
# Inputs
self.comb += [
fr.sink.eq(sink.r),
fg.sink.eq(sink.g),
fb.sink.eq(sink.b),
fr.coef.eq(coef),
fg.coef.eq(coef),
fb.coef.eq(coef),
]
# Outputs
self.comb += [
source.r.eq(fr.source),
source.g.eq(fg.source),
source.b.eq(fb.source),
]
class MultiTapFilter(Module, AutoCSR):
def __init__(self, n_taps, n_phase):
self.filters = filters = []
for i in range(n_taps):
f = RGBFilterElement()
filters += [f]
self.submodules += f
self.comb += f.ce.eq(self.pipe_ce & self.busy)
self.phase_ce = Signal()
self.bank = Signal()
self.coeff_data = CSRStorage(32)
cfg_coeff_stall = self.coeff_data.storage[31]
cfg_coeff_bank = self.coeff_data.storage[30]
cfg_coeff_tap = self.coeff_data.storage[24:30]
cfg_coeff_phase = self.coeff_data.storage[16:24]
cfg_coeff_dat = self.coeff_data.storage[0:10]
_coeff_data_we_ps = PulseSynchronizer('cpu', 'sys')
self.comb += _coeff_data_we_ps.i.eq(self.coeff_data.re)
self.submodules += _coeff_data_we_ps
coeff_memory = Memory(10*n_taps + 1, n_phase * 2)
self.specials += coeff_memory
coeff_memory_we_port = coeff_memory.get_port(write_capable=True)
# Give CSR storage time to load, and then coeff_memory a cycle to have dat_r prepared
self.comb += [
coeff_memory_we_port.we.eq(_coeff_data_we_ps.o),
If(cfg_coeff_bank,
coeff_memory_we_port.adr.eq(cfg_coeff_phase + n_phase),
).Else(
coeff_memory_we_port.adr.eq(cfg_coeff_phase),
)
]
for i in range(n_taps):
self.comb += If(cfg_coeff_tap == i,
coeff_memory_we_port.dat_w.eq(coeff_memory_we_port.dat_r),
coeff_memory_we_port.dat_w[i*10:(i+1)*10].eq(cfg_coeff_dat),
coeff_memory_we_port.dat_w[-1].eq(cfg_coeff_stall),
)
coeff_memory_port = coeff_memory.get_port(has_re=True)
self.specials += coeff_memory_port, coeff_memory_we_port
self.phases = phases = CSRStorage(8)
self.starting_phase = starting_phase = CSRStorage(8)
self.phase = phase = Signal(8, reset=0)
self.sync += [
If(self.phase_ce,
phase.eq(phase + 1),
If((phase >= (phases.storage - 1)) | (phase >= n_phase),
phase.eq(0),
),
self.stall.eq(coeff_memory_port.dat_r[-1])
),
]
self.comb += [
coeff_memory_port.re.eq(self.pipe_ce),
If(self.bank,
coeff_memory_port.adr.eq(phase + n_phase),
).Else(
coeff_memory_port.adr.eq(phase),
)
]
# Connect up CSRs to filters
for t in range(n_taps):
self.comb += filters[t].coef.eq(coeff_memory_port.dat_r[t*10:((t+1)*10)])
self.out_r = Signal(8)
self.out_g = Signal(8)
self.out_b = Signal(8)
for ch in ['r', 'g', 'b']:
# Sum up output from all filter taps
sum0 = Signal(24)
v = 0
for f in filters:
v += getattr(f.source, ch)
self.sync += If(self.pipe_ce & self.busy,
sum0.eq(v)
)
# Combine that into an 8bit output,
# take care of negative, overflow, underflow, and fixed point multiplication scaling
bitnarrow = Signal(8)
self.comb += [
If(sum0[-1] == 1,
bitnarrow.eq(0), # Saturate negative values to 0
).Elif(sum0[8:] > 255,
bitnarrow.eq(255),
).Else(
bitnarrow.eq(sum0[8:]),
)
]
# Connect channel to output
self.comb += {
'r': self.out_r,
'g': self.out_g,
'b': self.out_b,
}[ch].eq(bitnarrow)
class ScalerWidth(StallablePipelineActor, MultiTapFilter, AutoCSR):
def __init__(self):
self.sink = sink = Endpoint([("data", 32)])
self.source = source = Endpoint([("data", 32)])
n_taps = 4
n_phase = 128
StallablePipelineActor.__init__(self, n_taps + 1)
MultiTapFilter.__init__(self, n_taps, n_phase)
self.comb += [
self.phase_ce.eq(self.pipe_ce & self.busy)
]
self.submodules.tap_datapath = tap_dp = MultiTapDatapath(n_taps)
self.comb += self.tap_datapath.ce.eq(self.pipe_ce & ~self.stall)
for i in range(n_taps):
self.comb += self.filters[i].sink.eq(tap_dp.tap[i])
# Connect data into pipeline
self.comb += [
self.tap_datapath.sink.r.eq(sink.data[0:8]),
self.tap_datapath.sink.g.eq(sink.data[8:16]),
self.tap_datapath.sink.b.eq(sink.data[16:24]),
source.data[0:8].eq(self.out_r),
source.data[8:16].eq(self.out_g),
source.data[16:24].eq(self.out_b),
source.data[24:32].eq(0),
]
class ScaleHeight(StallablePipelineActor, MultiTapFilter, AutoCSR):
def __init__(self, line_length = 640):
self.sink = sink = Endpoint([("data", 32)])
self.source = source = Endpoint([("data", 32)])
n_taps = 4
n_phase = 128
StallablePipelineActor.__init__(self, n_taps + 1)
MultiTapFilter.__init__(self, n_taps, n_phase)
input_idx = Signal(16)
line_count = Signal(16)
first_line = Signal()
line_end = Signal()
ports = []
_outputs = []
tap_outputs = []
# delay data
sink_delayed = [sink.data]
for i in range(6):
data_n = Signal(24)
self.sync += If(self.pipe_ce & self.busy,
data_n.eq(sink_delayed[-1])
)
sink_delayed.append(data_n)
stall = Signal(n_taps)
self.sync += [
If(self.pipe_ce & self.busy,
stall.eq(Cat(self.stall,stall[:-1]))
)
]
for i in range(n_taps):
linebuffer = Memory(24, line_length, name=f'linebuffer{i}')
self.specials += linebuffer
# Fill line-buffer
wr = linebuffer.get_port(write_capable=True, mode=READ_FIRST, has_re=True)
ports += [wr]
self.specials += wr
self.comb += [
wr.adr.eq(input_idx),
wr.we.eq(self.pipe_ce & self.busy & ~Cat(self.stall,stall[:-1])[i]),
wr.re.eq(self.pipe_ce & self.busy),
]
# delay output by tap_number
s = wr.dat_r
for _ in range(n_taps - i):
_s = Signal(24)
self.sync += If(self.pipe_ce & self.busy, _s.eq(s))
s = _s
_outputs += [s]
for i in range(n_taps):
tap_outputs += [Signal(24, name=f'tap_out{i}')]
self.comb += tap_outputs[i].eq(_outputs[i])
self.comb += [
self.filters[i].sink.r.eq(tap_outputs[i][0:8]),
self.filters[i].sink.g.eq(tap_outputs[i][8:16]),
self.filters[i].sink.b.eq(tap_outputs[i][16:24]),
]
self.comb += [
ports[0].dat_w.eq(sink.data),
self.output_hold.eq(first_line)
]
for i in range(n_taps-1):
self.comb += If(first_line & (i == 0),
ports[i+1].dat_w.eq(sink_delayed[i+1])
).Else(
ports[i+1].dat_w.eq(ports[i].dat_r)
)
# Increment input address, along with an address per line
self.sync += [
self.phase_ce.eq(0),
If(self.pipe_ce & self.busy,
input_idx.eq(input_idx + 1),
If(input_idx == (line_length - 3),
self.phase_ce.eq(1),
),
If(input_idx >= (line_length - 1),
input_idx.eq(0),
line_count.eq(line_count + 1)
),
)
]
# Load new coefs at the end of each line.
self.comb += line_end.eq(input_idx == (line_length - 1))
self.comb += first_line.eq((line_count == 0) | ((line_count == 1) & (input_idx < 4)))
self.comb += [
]
# Connect data into pipeline
self.comb += [
source.data[0:8].eq(self.out_r),
source.data[8:16].eq(self.out_g),
source.data[16:24].eq(self.out_b),
source.data[24:32].eq(0),
]
class Scaler(Module, AutoCSR):
def __init__(self,line_length=640):
self.sink = sink = Endpoint([("data", 32)])
self.source = source = Endpoint([("data", 32)])
self.submodules.height = ScaleHeight(line_length)
self.submodules.width = ScalerWidth()
self.submodules.fifo = SyncFIFO([("data", 32)], 8, True)
# Filter coeff bank selection
self.bank = bank = Signal()
self.comb += [
self.height.bank.eq(bank),
self.width.bank.eq(bank),
]
self.submodules.pipeline = Pipeline(
sink,
self.height,
self.fifo,
self.width,
source,
)
## Unit tests
import unittest
from litex.soc.interconnect.stream_sim import PacketStreamer, PacketLogger, Packet, Randomizer
from litex.soc.interconnect.stream import Pipeline
from .stream_utils import StreamAppend, StreamPrepend
class TestScaler(unittest.TestCase):
def __init__(self, methodName='runTest'):
self.data = [int(math.sin(i/4)*127 + 127) for i in range(16)]
self.golden = [150, 169, 192, 213, 229, 242, 250, 253, 251, 244, 232, 216, 197, 175, 150, 125, 100, 75, 54, 53]
unittest.TestCase.__init__(self, methodName=methodName)
def testWidth(self):
def generator(dut):
d = Packet(self.data)
yield from dut.scaler.phases.write(5)
yield from dut.scaler.starting_phase.write(1)
yield dut.scaler.reset.eq(1)
yield
yield dut.scaler.reset.eq(0)
yield
yield from dut.streamer.send_blocking(d)
def checker(dut):
yield from dut.logger.receive()
print(dut.logger.packet)
assert(self.golden == dut.logger.packet)
class DUT(Module):
def __init__(self):
self.submodules.scaler = ScalerWidth()
self.sink = Endpoint([("data", 32)])
self.submodules.streamer = PacketStreamer([("data", 32)])
self.submodules.logger = PacketLogger([("data", 32)])
self.submodules.pipeline = Pipeline(
self.streamer,
self.scaler,
self.logger
)
dut = DUT()
generators = {
"sys" : [generator(dut),
checker(dut),
dut.streamer.generator(),
dut.logger.generator(),
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name='test0.vcd')
def testWidthRandom(self):
def generator(dut):
d = Packet(self.data)
yield from dut.scaler.phases.write(5)
yield from dut.scaler.starting_phase.write(1)
yield dut.scaler.reset.eq(1)
yield
yield dut.scaler.reset.eq(0)
yield
yield from dut.streamer.send_blocking(d)
def checker(dut):
yield from dut.logger.receive()
assert(self.golden == dut.logger.packet)
class DUT(Module):
def __init__(self):
self.submodules.scaler = ScalerWidth()
self.sink = Endpoint([("data", 32)])
self.submodules.streamer = PacketStreamer([("data", 32)])
self.submodules.loggerrandomiser = Randomizer([("data", 32)], level=50)
self.submodules.logger = PacketLogger([("data", 32)])
self.submodules.pipeline = Pipeline(
self.streamer,
self.scaler,
self.loggerrandomiser,
self.logger
)
dut = DUT()
generators = {
"sys" : [generator(dut),
checker(dut),
dut.streamer.generator(),
dut.logger.generator(),
dut.loggerrandomiser.generator()
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name='test.vcd')
class TestLineBuffer(unittest.TestCase):
def test0(self):
self.data = [i for i in range(16)]
self.data += [0x10 + i for i in range(16)]
self.data += [0x20 + i for i in range(16)]
self.data += [0x30 + i for i in range(16)]
self.data += [0x40 + i for i in range(16)]
self.data += [0x50 + i for i in range(16)]
self.data += [0x60 + i for i in range(16)]
self.data += [0x70 + i for i in range(16)]
def generator(dut):
d = Packet(self.data)
yield dut.scaler.reset.eq(1)
yield
yield dut.scaler.reset.eq(0)
yield
yield from dut.scaler.phases.write(4)
yield from dut.streamer.send_blocking(d)
yield
yield
yield
def checker(dut):
yield from dut.logger.receive()
print(dut.logger.packet)
#golden = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43]
# [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45]
#assert(dut.logger.packet == golden)
class DUT(Module):
def __init__(self):
self.submodules.scaler = ScaleHeight(line_length=16)
self.sink = Endpoint([("data", 32)])
self.submodules.streamer = PacketStreamer([("data", 32)])
self.submodules.loggerrandomiser = Randomizer([("data", 32)], level=50)
self.submodules.logger = PacketLogger([("data", 32)])
self.submodules.pipeline = Pipeline(
self.streamer,
self.scaler,
#self.loggerrandomiser,
self.logger
)
dut = DUT()
generators = {
"sys" : [generator(dut),
checker(dut),
dut.streamer.generator(),
dut.logger.generator(),
dut.loggerrandomiser.generator()
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name='test1.vcd')
class TestCombine(unittest.TestCase):
def test0(self):
self.data = [i for i in range(16)]
self.data += [0x10 + i for i in range(16)]
self.data += [0x20 + i for i in range(16)]
self.data += [0x30 + i for i in range(16)]
self.data += [0x40 + i for i in range(16)]
self.data += [0x50 + i for i in range(16)]
def coeff_load(dut, t, p, data, skip):
yield from dut.coeff_tap.write(t)
yield from dut.coeff_phase.write(p)
yield from dut.coeff_data.write(data)
yield from dut.coeff_stall.write(skip)
yield from dut.coeff_en.write(1)
yield from dut.coeff_en.write(0)
def load_width(dut):
for i in range(5):
yield from coeff_load(dut, 1, i, 256, i == 4)
def load_height(dut):
for i in range(3):
yield from coeff_load(dut, 1, i, 256, i == 2)
def generator(dut):
d = Packet(self.data)
yield dut.scaler.reset.eq(1)
yield
yield dut.scaler.reset.eq(0)
yield
yield from dut.scaler.width.phases.write(5)
yield from dut.scaler.height.phases.write(3)
yield from load_width(dut.scaler.width)
yield from load_height(dut.scaler.height)
yield from dut.scaler.width.starting_phase.write(1)
yield from dut.streamer.send_blocking(d)
yield
yield
yield
def checker(dut):
yield from dut.logger.receive()
print(dut.logger.packet)
#assert(dut.logger.packet == golden)
class DUT(Module):
def __init__(self):
self.submodules.scaler = Scaler(line_length=16)
self.sink = Endpoint([("data", 32)])
self.submodules.streamer = PacketStreamer([("data", 32)])
self.submodules.loggerrandomiser = Randomizer([("data", 32)], level=50)
self.submodules.logger = PacketLogger([("data", 32)])
self.submodules.pipeline = Pipeline(
self.streamer,
self.scaler,
#self.loggerrandomiser,
self.logger
)
dut = DUT()
generators = {
"sys" : [generator(dut),
checker(dut),
dut.streamer.generator(),
dut.logger.generator(),
dut.loggerrandomiser.generator()
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name='test1.vcd')
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream_sim.PacketLogger",
"litex.soc.interconnect.stream_sim.PacketStreamer",
"litex.soc.interconnect.stream_sim.Randomizer",
"litex.soc.interconnect.stream_sim.Packet",
"litex.soc.interconnect.stream.Pipeline",
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import random
from operator import or_
from functools import reduce
from collections import defaultdict
from sdram_init import *
# DRAM commands ----------------------------------
def sdram_software_control(wb):
wb.regs.sdram_dfii_control.write(dfii_control_cke|dfii_control_odt|dfii_control_reset_n)
def sdram_cmd(wb, a, ba, command):
sdram_software_control(wb)
wb.regs.sdram_dfii_pi0_baddress.write(ba)
wb.regs.sdram_dfii_pi0_address.write(a)
wb.regs.sdram_dfii_pi0_command.write(command)
wb.regs.sdram_dfii_pi0_command_issue.write(1)
def dfii_px(wb, phase, signal):
return getattr(wb.regs, "sdram_dfii_pi{}_{}".format(phase, signal))
def dfii_write(wb, phase_datas, wrphase):
for p, data in enumerate(phase_datas):
dfii_px(wb, p, "wrdata").write(data)
dfii_px(wb, wrphase, "address").write(0)
dfii_px(wb, wrphase, "baddress").write(0)
dfii_px(wb, wrphase, "command").write(dfii_command_cas|dfii_command_we|dfii_command_cs|dfii_command_wrdata)
dfii_px(wb, wrphase, "command_issue").write(1)
def dfii_read(wb, nphases, rdphase):
dfii_px(wb, rdphase, "address").write(0)
dfii_px(wb, rdphase, "baddress").write(0)
dfii_px(wb, rdphase, "command").write(dfii_command_cas|dfii_command_cs|dfii_command_rddata)
dfii_px(wb, rdphase, "command_issue").write(1)
return [dfii_px(wb, p, "rddata").read() for p in range(nphases)]
# PHY delay/bitslip settings ---------------------
def delay_select_modules(wb, modules):
sel = reduce(or_, ((1 << m) for m in modules))
wb.regs.ddrphy_dly_sel.write(sel)
def read_bitslip_rst(wb):
wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
def read_bitslip_inc(wb):
wb.regs.ddrphy_rdly_dq_bitslip.write(1)
def read_bitslip_set(wb, value):
read_bitslip_rst(wb)
for _ in range(value):
read_bitslip_inc(wb)
def read_delay_rst(wb):
wb.regs.ddrphy_rdly_dq_rst.write(1)
def read_delay_inc(wb):
wb.regs.ddrphy_rdly_dq_inc.write(1)
def read_delay_set(wb, value):
read_delay_rst(wb)
for _ in range(value):
read_delay_inc(wb)
# Read leveling (software control) ---------------
def get_byte(i, data):
return (data & (0xff << (8*i))) >> (8*i)
class Settings:
def __init__(self, nmodules, bitslips, delays, nphases, wrphase, rdphase):
# Defined by:
# `#define SDRAM_PHY_MODULES` in sdram_phy.h
# `#define DFII_PIX_DATA_BYTES DFII_PIX_DATA_SIZE*CSR_DATA_BYTES` in sdram.c
# `#define CSR_DATA_BYTES CONFIG_CSR_DATA_WIDTH/8` in sdram.c
# `#define CONFIG_CSR_DATA_WIDTH` in soc.h
# `#define DFII_PIX_DATA_SIZE` in soc.h
# `#define DFII_PIX_DATA_SIZE CSR_SDRAM_DFII_PI0_WRDATA_SIZE` in sdram_phy.h
# `#define CSR_SDRAM_DFII_PI0_WRDATA_SIZE 8` in csr.h
self.nmodules = nmodules
# Defined by:
# `#define SDRAM_PHY_DELAYS` in sdram_phy.h
self.bitslips = bitslips
# Defined by:
# `#define SDRAM_PHY_BITSLIPS` in sdram_phy.h
self.delays = delays
# from PhySettings
self.nphases = nphases
self.wrphase = wrphase
self.rdphase = rdphase
# Perform single read+write and return number of errors
def read_level_test(wb, settings, module, seed=42, verbose=None):
rng = random.Random(seed)
# generate pattern
data_pattern = []
phase_bytes = wb.regs.sdram_dfii_pi0_wrdata.data_width // 8
for p in range(settings.nphases):
for b in range(phase_bytes):
data_pattern.append(rng.randint(0, 256))
def per_phase(data):
for p in range(settings.nphases):
val = 0
for b in range(phase_bytes):
val <<= 8
val |= data_pattern[p*phase_bytes + b]
yield val
# activate row
sdram_cmd(wb, 0, 0, dfii_command_ras | dfii_command_cs)
# send write command
dfii_write(wb, list(per_phase(data_pattern)), wrphase=settings.wrphase)
# send read command
rdatas = dfii_read(wb, settings.nphases, rdphase=settings.rdphase)
if verbose is not None:
print()
errors = 0
for rdata, wdata in zip(rdatas, per_phase(data_pattern)):
for i in [1, 2]:
rbyte = get_byte(i*settings.nmodules + module, rdata)
wbyte = get_byte(i*settings.nmodules + module, wdata)
if rbyte != wbyte:
errors += 1
if verbose is not None:
_compare(rbyte, wbyte, fmt=verbose, nbytes=1)
# precharge row
sdram_cmd(wb, 0, 0, dfii_command_ras | dfii_command_we | dfii_command_cs)
return errors
# Find best bitslip+delay configuration based on leveling results
# scores: {bitslip: {delay: errors}, ...}
def read_level_find_best(scores):
bs_windows = {}
for bs, dly_scores in scores.items():
# find read windows
windows = []
window_start = None
in_window = False
for dly, errors in dly_scores.items():
if errors == 0 and not in_window:
window_start = dly
in_window = True
elif in_window and errors != 0:
windows.append((window_start, dly))
in_window = False
if in_window:
windows.append((window_start, dly))
# find longest window
best_window = None
if len(windows):
best_window = max(windows, key=lambda win_range: win_range[1] - win_range[0])
bs_windows[bs] = best_window
def cmp_bs_windows(bs):
if bs_windows[bs] is None:
return -1
length = bs_windows[bs][1] - bs_windows[bs][0]
return length
best_bs = max(bs_windows, key=cmp_bs_windows)
if bs_windows[best_bs] is None:
return None
# best delay is in the middle of the window
best_delay = (bs_windows[best_bs][0] + bs_windows[best_bs][1]) // 2
best_length = bs_windows[best_bs][1] - bs_windows[best_bs][0]
return best_bs, best_delay, best_length
# Read level current module
def read_level_module(wb, settings, module, delays_step=1, **kwargs):
read_bitslip_rst(wb)
scores = defaultdict(dict) # {bitslip: {delay: errors}, ...}
for bs in range(settings.bitslips):
read_delay_rst(wb)
print("Bitslip {:02d}: |".format(bs), end="", flush=True)
for dly in range(settings.delays):
if dly % delays_step == 0:
errors = read_level_test(wb, settings, module, **kwargs)
scores[bs][dly] = errors
print("1" if errors == 0 else "0", end="", flush=True)
read_delay_inc(wb)
print("|")
read_bitslip_inc(wb)
best = read_level_find_best(scores)
if best is None:
print("Read leveling failed")
return
best_bs, best_dly, best_len = best
print("Best: bitslip = {}, delay = {} (+-{})".format(best_bs, best_dly, best_len//2))
read_bitslip_set(wb, best_bs)
read_delay_set(wb, best_dly)
# Perform whole read leveling procedure
def read_level(wb, settings, **kwargs):
sdram_software_control(wb)
for module in range(settings.nmodules):
print("Module {}".format(module))
delay_select_modules(wb, [module])
read_level_module(wb, settings, module, **kwargs)
# -----------------------
def default_arty_settings():
return Settings(
nmodules = 2,
bitslips = 8,
delays = 32,
nphases = 4,
rdphase = 2,
wrphase = 3,
)
if __name__ == "__main__":
from litex import RemoteClient
wb = RemoteClient()
wb.open()
read_level(wb, default_arty_settings())
wb.close()
| [
"litex.RemoteClient"
] | [((1502, 1540), 'functools.reduce', 'reduce', (['or_', '(1 << m for m in modules)'], {}), '(or_, (1 << m for m in modules))\n', (1508, 1540), False, 'from functools import reduce\n'), ((3272, 3291), 'random.Random', 'random.Random', (['seed'], {}), '(seed)\n', (3285, 3291), False, 'import random\n'), ((6120, 6137), 'collections.defaultdict', 'defaultdict', (['dict'], {}), '(dict)\n', (6131, 6137), False, 'from collections import defaultdict\n'), ((7555, 7569), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (7567, 7569), False, 'from litex import RemoteClient\n')] |
#!/usr/bin/env python3
import os
import subprocess
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.cores.spi_flash import SpiFlash
from litex.soc.cores.gpio import GPIOOut, GPIOIn
from litex.soc.cores.spi import SPIMaster
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.xadc import XADC
from litex.soc.cores.pwm import PWM
from litex.soc.cores.icap import ICAPBitstream
from litevideo.output import VideoOut
# Predefined values --------------------------------------------------------------------------------
video_resolutions = {
"1920x1080_60Hz" : {
"pix_clk" : 148.5e6,
"h-active" : 1920,
"h-blanking" : 280,
"h-sync" : 44,
"h-front-porch" : 148,
"v-active" : 1080,
"v-blanking" : 45,
"v-sync" : 5,
"v-front-porch" : 36,
},
"1280x720_60Hz" : {
"pix_clk" : 74.25e6,
"h-active" : 1280,
"h-blanking" : 370,
"h-sync" : 40,
"h-front-porch" : 220,
"v-active" : 720,
"v-blanking" : 30,
"v-sync" : 5,
"v-front-porch" : 20,
},
"640x480_75Hz" : {
"pix_clk" : 31.5e6,
"h-active" : 640,
"h-blanking" : 200,
"h-sync" : 64,
"h-front-porch" : 16,
"v-active" : 480,
"v-blanking" : 20,
"v-sync" : 3,
"v-front-porch" : 1,
}
}
# Helpers ------------------------------------------------------------------------------------------
def platform_request_all(platform, name):
from litex.build.generic_platform import ConstraintError
r = []
while True:
try:
r += [platform.request(name, len(r))]
except ConstraintError:
break
if r == []:
raise ValueError
return r
# SoCLinux -----------------------------------------------------------------------------------------
def SoCLinux(soc_cls, **kwargs):
class _SoCLinux(soc_cls):
csr_map = {**soc_cls.csr_map, **{
"ctrl": 0,
"uart": 2,
"timer0": 3,
}}
interrupt_map = {**soc_cls.interrupt_map, **{
"uart": 0,
"timer0": 1,
}}
mem_map = {**soc_cls.mem_map, **{
"emulator_ram": 0x20000000,
"ethmac": 0xb0000000,
"spiflash": 0xd0000000,
"csr": 0xf0000000,
}}
def __init__(self, cpu_variant="linux", **kwargs):
soc_cls.__init__(self,
cpu_type = "vexriscv",
cpu_variant = cpu_variant,
uart_baudrate = 1e6,
max_sdram_size = 0x10000000, # Limit mapped SDRAM to 256MB for now
**kwargs)
# machine mode emulator ram
self.submodules.emulator_ram = wishbone.SRAM(0x4000)
self.register_mem("emulator_ram", self.mem_map["emulator_ram"], self.emulator_ram.bus, 0x4000)
def add_spi_flash(self):
# TODO: add spiflash1x support
spiflash_pads = self.platform.request("spiflash4x")
self.submodules.spiflash = SpiFlash(
spiflash_pads,
dummy=11,
div=2,
with_bitbang=True,
endianness=self.cpu.endianness)
self.spiflash.add_clk_primitive(self.platform.device)
self.add_wb_slave(mem_decoder(self.mem_map["spiflash"]), self.spiflash.bus)
self.add_memory_region("spiflash", self.mem_map["spiflash"], 0x1000000)
self.add_csr("spiflash")
def add_leds(self):
self.submodules.leds = GPIOOut(Cat(platform_request_all(self.platform, "user_led")))
self.add_csr("leds")
def add_rgb_led(self):
rgb_led_pads = self.platform.request("rgb_led", 0)
for n in "rgb":
setattr(self.submodules, "rgb_led_{}0".format(n), PWM(getattr(rgb_led_pads, n)))
self.add_csr("rgb_led_{}0".format(n))
def add_switches(self):
self.submodules.switches = GPIOOut(Cat(platform_request_all(self.platform, "user_sw")))
self.add_csr("switches")
def add_spi(self, data_width, spi_clk_freq):
spi_pads = self.platform.request("spi")
self.add_csr("spi")
self.submodules.spi = SPIMaster(spi_pads, data_width, self.clk_freq, spi_clk_freq)
def add_i2c(self):
self.submodules.i2c0 = I2CMaster(self.platform.request("i2c", 0))
self.add_csr("i2c0")
def add_xadc(self):
self.submodules.xadc = XADC()
self.add_csr("xadc")
def add_framebuffer(self, video_settings):
platform = self.platform
assert platform.device[:4] == "xc7a"
dram_port = self.sdram.crossbar.get_port(
mode="read",
data_width=32,
clock_domain="pix",
reverse=True)
framebuffer = VideoOut(
device=platform.device,
pads=platform.request("hdmi_out"),
dram_port=dram_port)
self.submodules.framebuffer = framebuffer
self.add_csr("framebuffer")
framebuffer.driver.clocking.cd_pix.clk.attr.add("keep")
framebuffer.driver.clocking.cd_pix5x.clk.attr.add("keep")
platform.add_period_constraint(framebuffer.driver.clocking.cd_pix.clk, 1e9/video_settings["pix_clk"])
platform.add_period_constraint(framebuffer.driver.clocking.cd_pix5x.clk, 1e9/(5*video_settings["pix_clk"]))
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
framebuffer.driver.clocking.cd_pix.clk,
framebuffer.driver.clocking.cd_pix5x.clk)
self.add_constant("litevideo_pix_clk", video_settings["pix_clk"])
self.add_constant("litevideo_h_active", video_settings["h-active"])
self.add_constant("litevideo_h_blanking", video_settings["h-blanking"])
self.add_constant("litevideo_h_sync", video_settings["h-sync"])
self.add_constant("litevideo_h_front_porch", video_settings["h-front-porch"])
self.add_constant("litevideo_v_active", video_settings["v-active"])
self.add_constant("litevideo_v_blanking", video_settings["v-blanking"])
self.add_constant("litevideo_v_sync", video_settings["v-sync"])
self.add_constant("litevideo_v_front_porch", video_settings["v-front-porch"])
def add_icap_bitstream(self):
self.submodules.icap_bit = ICAPBitstream();
self.add_csr("icap_bit")
def configure_ethernet(self, local_ip, remote_ip):
local_ip = local_ip.split(".")
remote_ip = remote_ip.split(".")
self.add_constant("LOCALIP1", int(local_ip[0]))
self.add_constant("LOCALIP2", int(local_ip[1]))
self.add_constant("LOCALIP3", int(local_ip[2]))
self.add_constant("LOCALIP4", int(local_ip[3]))
self.add_constant("REMOTEIP1", int(remote_ip[0]))
self.add_constant("REMOTEIP2", int(remote_ip[1]))
self.add_constant("REMOTEIP3", int(remote_ip[2]))
self.add_constant("REMOTEIP4", int(remote_ip[3]))
def configure_boot(self):
if hasattr(self, "spiflash"):
self.add_constant("FLASH_BOOT_ADDRESS", 0x00400000)
def generate_dts(self, board_name):
json = os.path.join("build", board_name, "csr.json")
dts = os.path.join("build", board_name, "{}.dts".format(board_name))
subprocess.check_call(
"./json2dts.py {} > {}".format(json, dts), shell=True)
def compile_dts(self, board_name):
dts = os.path.join("build", board_name, "{}.dts".format(board_name))
dtb = os.path.join("buildroot", "rv32.dtb")
subprocess.check_call(
"dtc -O dtb -o {} {}".format(dtb, dts), shell=True)
def compile_emulator(self, board_name):
os.environ["BOARD"] = board_name
subprocess.check_call("cd emulator && make", shell=True)
return _SoCLinux(**kwargs)
| [
"litex.soc.cores.spi.SPIMaster",
"litex.soc.integration.soc_core.mem_decoder",
"litex.soc.cores.icap.ICAPBitstream",
"litex.soc.interconnect.wishbone.SRAM",
"litex.soc.cores.spi_flash.SpiFlash",
"litex.soc.cores.xadc.XADC"
] | [((3060, 3080), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(16384)'], {}), '(16384)\n', (3073, 3080), False, 'from litex.soc.interconnect import wishbone\n'), ((3369, 3465), 'litex.soc.cores.spi_flash.SpiFlash', 'SpiFlash', (['spiflash_pads'], {'dummy': '(11)', 'div': '(2)', 'with_bitbang': '(True)', 'endianness': 'self.cpu.endianness'}), '(spiflash_pads, dummy=11, div=2, with_bitbang=True, endianness=self\n .cpu.endianness)\n', (3377, 3465), False, 'from litex.soc.cores.spi_flash import SpiFlash\n'), ((4592, 4652), 'litex.soc.cores.spi.SPIMaster', 'SPIMaster', (['spi_pads', 'data_width', 'self.clk_freq', 'spi_clk_freq'], {}), '(spi_pads, data_width, self.clk_freq, spi_clk_freq)\n', (4601, 4652), False, 'from litex.soc.cores.spi import SPIMaster\n'), ((4856, 4862), 'litex.soc.cores.xadc.XADC', 'XADC', ([], {}), '()\n', (4860, 4862), False, 'from litex.soc.cores.xadc import XADC\n'), ((6862, 6877), 'litex.soc.cores.icap.ICAPBitstream', 'ICAPBitstream', ([], {}), '()\n', (6875, 6877), False, 'from litex.soc.cores.icap import ICAPBitstream\n'), ((7763, 7808), 'os.path.join', 'os.path.join', (['"""build"""', 'board_name', '"""csr.json"""'], {}), "('build', board_name, 'csr.json')\n", (7775, 7808), False, 'import os\n'), ((8139, 8176), 'os.path.join', 'os.path.join', (['"""buildroot"""', '"""rv32.dtb"""'], {}), "('buildroot', 'rv32.dtb')\n", (8151, 8176), False, 'import os\n'), ((8386, 8442), 'subprocess.check_call', 'subprocess.check_call', (['"""cd emulator && make"""'], {'shell': '(True)'}), "('cd emulator && make', shell=True)\n", (8407, 8442), False, 'import subprocess\n'), ((3638, 3675), 'litex.soc.integration.soc_core.mem_decoder', 'mem_decoder', (["self.mem_map['spiflash']"], {}), "(self.mem_map['spiflash'])\n", (3649, 3675), False, 'from litex.soc.integration.soc_core import mem_decoder\n')] |
import nmigen
from litex.soc.interconnect.stream import Endpoint
from .. import dfu
class DFUHandler:
def __init__(self, if_num, areas):
self.source = Endpoint([('data', 8), ('addr', 24)])
self.handler = dfu.DFUHandler(if_num, areas)
def wrap(self, wrapper):
wrapper.connect(self.source.data, self.handler.source.data)
wrapper.connect(self.source.addr, self.handler.source.addr)
wrapper.connect(self.source.valid, self.handler.source.valid)
wrapper.connect(self.source.ready, self.handler.source.ready)
wrapper.connect(self.source.first, self.handler.source.first)
wrapper.connect(self.source.last, self.handler.source.last)
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((166, 203), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 8), ('addr', 24)]"], {}), "([('data', 8), ('addr', 24)])\n", (174, 203), False, 'from litex.soc.interconnect.stream import Endpoint\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = {
"standard": "firev",
}
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32i -mabi=ilp32",
}
# FireV ------------------------------------------------------------------------------------------
class FireV(CPU):
category = "softcore"
family = "riscv"
name = "firev"
human_name = "firev"
variants = CPU_VARIANTS
data_width = 32
endianness = "little"
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # Origin, Length.
# GCC Flags.
@property
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += " -D__firev__ "
return flags
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.human_name = f"FireV-{variant.upper()}"
self.reset = Signal()
self.idbus = idbus = wishbone.Interface()
self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
# FireV Mem Bus.
# ----------------
mbus = Record([
("out_ram_addr", 32),
("out_ram_in_valid", 1),
("out_ram_wmask", 4),
("out_ram_rw", 1),
("out_ram_data_in", 32),
("in_ram_done", 1),
("in_ram_data_out", 32),
("in_boot_at", 32),
])
# FireV Instance.
# -----------------
self.cpu_params = dict(
# Clk / Rst.
i_clock = ClockSignal("sys"),
i_reset = (ResetSignal("sys") | self.reset),
# Reset Address.
i_in_boot_at = Constant(0, 32),
# I/D Bus.
o_out_ram_addr = mbus.out_ram_addr,
o_out_ram_in_valid = mbus.out_ram_in_valid,
o_out_ram_wmask = mbus.out_ram_wmask,
o_out_ram_data_in = mbus.out_ram_data_in,
o_out_ram_rw = mbus.out_ram_rw,
i_in_ram_done = mbus.in_ram_done,
i_in_ram_data_out = mbus.in_ram_data_out,
)
# Adapt FireV Mem Bus to Wishbone.
# --------------------------------
self.submodules.fsm = fsm = FSM(reset_state="WAIT")
fsm.act("WAIT",
If(mbus.out_ram_in_valid,
idbus.stb.eq(1),
idbus.cyc.eq(1),
NextState("WB-ACCESS")
)
)
fsm.act("WB-ACCESS",
idbus.stb.eq(1),
idbus.cyc.eq(1),
If(idbus.ack,
NextState("WAIT")
)
)
self.comb += [
idbus.we.eq(mbus.out_ram_rw),
idbus.adr.eq(mbus.out_ram_addr[2:]),
idbus.sel.eq(mbus.out_ram_wmask),
idbus.dat_w.eq(mbus.out_ram_data_in),
mbus.in_ram_data_out.eq(idbus.dat_r),
mbus.in_ram_done.eq(idbus.ack),
]
# Add Verilog sources.
# --------------------
self.add_sources(platform, variant)
def set_reset_address(self, reset_address):
self.reset_address = reset_address
self.cpu_params.update(i_in_boot_at=Constant(reset_address, 32))
@staticmethod
def add_sources(platform, variant):
platform.add_verilog_include_path(os.getcwd())
cpu_file = f"{CPU_VARIANTS[variant]}.v"
if not os.path.exists(cpu_file):
os.system(f"wget https://raw.githubusercontent.com/sylefeb/Silice/draft/projects/fire-v/export-verilog/{cpu_file}")
platform.add_source(cpu_file)
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("M_rv32i_cpu", **self.cpu_params)
| [
"litex.soc.interconnect.wishbone.Interface"
] | [((1921, 1941), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1939, 1941), False, 'from litex.soc.interconnect import wishbone\n'), ((4386, 4397), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (4395, 4397), False, 'import os\n'), ((4462, 4486), 'os.path.exists', 'os.path.exists', (['cpu_file'], {}), '(cpu_file)\n', (4476, 4486), False, 'import os\n'), ((4500, 4625), 'os.system', 'os.system', (['f"""wget https://raw.githubusercontent.com/sylefeb/Silice/draft/projects/fire-v/export-verilog/{cpu_file}"""'], {}), "(\n f'wget https://raw.githubusercontent.com/sylefeb/Silice/draft/projects/fire-v/export-verilog/{cpu_file}'\n )\n", (4509, 4625), False, 'import os\n')] |
#!/usr/bin/env python3
import time
import random
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
# test buttons
print("Testing Buttons/Switches...")
while True:
buttons = wb.regs.buttons_in.read()
switches = wb.regs.switches_in.read()
print("buttons: {:02x} / switches: {:02x}".format(buttons, switches))
time.sleep(0.5)
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((88, 102), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (100, 102), False, 'from litex import RemoteClient\n'), ((345, 360), 'time.sleep', 'time.sleep', (['(0.5)'], {}), '(0.5)\n', (355, 360), False, 'import time\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2019 Antmicro <www.antmicro.com>
# Copyright (c) 2019 Tim 'mithro' Ansell <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = ["minimal", "standard"]
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"minimal": "-march=rv32i -mabi=ilp32 ",
"standard": "-march=rv32im -mabi=ilp32 ",
}
# PicoRV32 -----------------------------------------------------------------------------------------
class PicoRV32(CPU):
category = "softcore"
family = "riscv"
name = "picorv32"
human_name = "PicoRV32"
variants = CPU_VARIANTS
data_width = 32
endianness = "little"
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # origin, length
# GCC Flags.
@property
def gcc_flags(self):
flags = "-mno-save-restore "
flags += GCC_FLAGS[self.variant]
flags += "-D__picorv32__ "
return flags
# Reserved Interrupts.
@property
def reserved_interrupts(self):
return {
"timer": 0,
"ebreak_ecall_illegal": 1,
"bus_error": 2
}
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.trap = Signal()
self.reset = Signal()
self.interrupt = Signal(32)
self.idbus = idbus = wishbone.Interface()
self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
# # #
mem_valid = Signal()
mem_instr = Signal()
mem_ready = Signal()
mem_addr = Signal(32)
mem_wdata = Signal(32)
mem_wstrb = Signal(4)
mem_rdata = Signal(32)
# PicoRV32 parameters, change the desired parameters to create a create a new variant.
self.cpu_params = dict(
p_ENABLE_COUNTERS = 1,
p_ENABLE_COUNTERS64 = 1,
p_ENABLE_REGS_16_31 = 1, # Changing REGS has no effect as on FPGAs, the regs are
p_ENABLE_REGS_DUALPORT = 1, # implemented using a register file stored in DPRAM.
p_LATCHED_MEM_RDATA = 0,
p_TWO_STAGE_SHIFT = 1,
p_TWO_CYCLE_COMPARE = 0,
p_TWO_CYCLE_ALU = 0,
p_CATCH_MISALIGN = 1,
p_CATCH_ILLINSN = 1,
p_ENABLE_PCPI = 0,
p_ENABLE_MUL = 1,
p_ENABLE_DIV = 1,
p_ENABLE_FAST_MUL = 0,
p_ENABLE_IRQ = 1,
p_ENABLE_IRQ_QREGS = 1,
p_ENABLE_IRQ_TIMER = 1,
p_ENABLE_TRACE = 0,
p_MASKED_IRQ = 0x00000000,
p_LATCHED_IRQ = 0xffffffff,
p_STACKADDR = 0xffffffff,
)
# Enforce default parameters for Minimal variant.
if variant == "minimal":
self.cpu_params.update(
p_ENABLE_COUNTERS = 0,
p_ENABLE_COUNTERS64 = 0,
p_TWO_STAGE_SHIFT = 0,
p_CATCH_MISALIGN = 0,
p_ENABLE_MUL = 0,
p_ENABLE_DIV = 0,
p_ENABLE_IRQ_TIMER = 0,
)
self.cpu_params.update(
# Clk / Rst.
i_clk = ClockSignal("sys"),
i_resetn = ~(ResetSignal("sys") | self.reset),
# Trap.
o_trap = self.trap,
# Memory Interface.
o_mem_valid = mem_valid,
o_mem_instr = mem_instr,
i_mem_ready = mem_ready,
o_mem_addr = mem_addr,
o_mem_wdata = mem_wdata,
o_mem_wstrb = mem_wstrb,
i_mem_rdata = mem_rdata,
# Look Ahead Interface (not used).
o_mem_la_read = Signal(),
o_mem_la_write = Signal(),
o_mem_la_addr = Signal(32),
o_mem_la_wdata = Signal(32),
o_mem_la_wstrb = Signal(4),
# Co-Processor interface (not used).
o_pcpi_valid = Signal(),
o_pcpi_insn = Signal(32),
o_pcpi_rs1 = Signal(32),
o_pcpi_rs2 = Signal(32),
i_pcpi_wr = 0,
i_pcpi_rd = 0,
i_pcpi_wait = 0,
i_pcpi_ready = 0,
# IRQ interface.
i_irq = self.interrupt,
o_eoi = Signal(32)) # not used
# Adapt Memory Interface to Wishbone.
self.comb += [
idbus.adr.eq(mem_addr[2:]),
idbus.dat_w.eq(mem_wdata),
idbus.we.eq(mem_wstrb != 0),
idbus.sel.eq(mem_wstrb),
idbus.cyc.eq(mem_valid),
idbus.stb.eq(mem_valid),
idbus.cti.eq(0),
idbus.bte.eq(0),
mem_ready.eq(idbus.ack),
mem_rdata.eq(idbus.dat_r),
]
# Add Verilog sources
self.add_sources(platform)
def set_reset_address(self, reset_address):
self.reset_address = reset_address
self.cpu_params.update(
p_PROGADDR_RESET = reset_address,
p_PROGADDR_IRQ = reset_address + 0x00000010
)
@staticmethod
def add_sources(platform):
vdir = get_data_mod("cpu", "picorv32").data_location
platform.add_source(os.path.join(vdir, "picorv32.v"))
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("picorv32", **self.cpu_params)
| [
"litex.soc.interconnect.wishbone.Interface",
"litex.get_data_mod"
] | [((2543, 2563), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2561, 2563), False, 'from litex.soc.interconnect import wishbone\n'), ((6504, 6535), 'litex.get_data_mod', 'get_data_mod', (['"""cpu"""', '"""picorv32"""'], {}), "('cpu', 'picorv32')\n", (6516, 6535), False, 'from litex import get_data_mod\n'), ((6578, 6610), 'os.path.join', 'os.path.join', (['vdir', '"""picorv32.v"""'], {}), "(vdir, 'picorv32.v')\n", (6590, 6610), False, 'import os\n')] |
import sys
import struct
import os.path
import argparse
from migen import *
from litex.build.generic_platform import Pins, Subsignal, IOStandard
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from gateware import cas
from gateware import spi_flash
from targets.utils import dict_set_max, define_flash_constants
from .crg import _CRG
serial = [
("serial", 0,
Subsignal("rx", Pins("GPIO:0")), # Pin 1 - A2 - Silkscreen 1
Subsignal("tx", Pins("GPIO:1")), # Pin 2 - A1 - Silkscreen 2
IOStandard("LVCMOS33")
)
]
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{
"spiflash": 0x20000000, # (default shadow @0xa0000000)
}}
def __init__(self, platform, **kwargs):
dict_set_max(kwargs, 'integrated_sram_size', 0x2800)
# We save the ROM size passed in as the BIOS size, and then force the
# integrated ROM size to 0 to avoid integrated ROM.
bios_size = kwargs['integrated_rom_size']
kwargs['integrated_rom_size'] = 0x0
# FIXME: Force either lite or minimal variants of CPUs; full is too big.
platform.add_extension(serial)
clk_freq = int(16e6)
# Extra 0x28000 is due to bootloader bitstream.
kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size+platform.bootloader_size
SoCCore.__init__(self, platform, clk_freq, **kwargs)
self.submodules.crg = _CRG(platform)
self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/clk_freq)
# Control and Status
self.submodules.cas = cas.ControlAndStatus(platform, clk_freq)
self.add_csr("cas")
# SPI flash peripheral
self.submodules.spiflash = spi_flash.SpiFlashSingle(
platform.request("spiflash"),
dummy=platform.spiflash_read_dummy_bits,
div=platform.spiflash_clock_div)
self.add_csr("spiflash")
self.add_constant("SPIFLASH_PAGE_SIZE", platform.spiflash_page_size)
self.add_constant("SPIFLASH_SECTOR_SIZE", platform.spiflash_sector_size)
self.register_mem("spiflash", self.mem_map["spiflash"],
self.spiflash.bus, size=platform.spiflash_total_size)
self.add_constant("ROM_DISABLE", 1)
self.add_memory_region(
"rom", kwargs['cpu_reset_address'], bios_size,
type="cached+linker")
self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size+platform.bootloader_size
define_flash_constants(self)
# We don't have a DRAM, so use the remaining SPI flash for user
# program.
self.add_memory_region("user_flash",
self.flash_boot_address,
# Leave a grace area- possible one-by-off bug in add_memory_region?
# Possible fix: addr < origin + length - 1
platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100,
type="cached+linker")
# Disable USB activity until we switch to a USB UART.
self.comb += [platform.request("usb").pullup.eq(0)]
SoC = BaseSoC
| [
"litex.build.generic_platform.Pins",
"litex.build.generic_platform.IOStandard"
] | [((557, 579), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (567, 579), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard\n'), ((776, 827), 'targets.utils.dict_set_max', 'dict_set_max', (['kwargs', '"""integrated_sram_size"""', '(10240)'], {}), "(kwargs, 'integrated_sram_size', 10240)\n", (788, 827), False, 'from targets.utils import dict_set_max, define_flash_constants\n'), ((1626, 1666), 'gateware.cas.ControlAndStatus', 'cas.ControlAndStatus', (['platform', 'clk_freq'], {}), '(platform, clk_freq)\n', (1646, 1666), False, 'from gateware import cas\n'), ((2544, 2572), 'targets.utils.define_flash_constants', 'define_flash_constants', (['self'], {}), '(self)\n', (2566, 2572), False, 'from targets.utils import dict_set_max, define_flash_constants\n'), ((435, 449), 'litex.build.generic_platform.Pins', 'Pins', (['"""GPIO:0"""'], {}), "('GPIO:0')\n", (439, 449), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard\n'), ((504, 518), 'litex.build.generic_platform.Pins', 'Pins', (['"""GPIO:1"""'], {}), "('GPIO:1')\n", (508, 518), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# FIXME: Cleanup/Move.
import os
from migen import *
from migen.genlib.cdc import *
from migen import ClockDomain
from litex.build.generic_platform import *
from litex.soc.interconnect import axi
from litex.build import tools
# Efinix DDR ---------------------------------------------------------------------------------------
class EfinixDDR(Module):
def __init__(self, platform, config, cd):
self.blocks = []
self.platform = platform
self.config = config
self.nb_ports = 1
if config["ports"] != None:
self.nb_ports = self.config["ports"]
# TODO: set clock_domain ?
self.port0 = port0 = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
if self.nb_ports == 2:
self.port1 = port1 = axi.AXIInterface(data_width=256, address_width=32, id_width=8)
for i in range(self.nb_ports):
ios = [('axi', i,
Subsignal('wdata', Pins(256)),
Subsignal('wready', Pins(1)),
Subsignal('wid', Pins(8)),
Subsignal('bready', Pins(1)),
Subsignal('rdata', Pins(256)),
Subsignal('aid', Pins(8)),
Subsignal('bvalid', Pins(1)),
Subsignal('rlast', Pins(1)),
Subsignal('bid', Pins(8)),
Subsignal('asize', Pins(3)),
Subsignal('atype', Pins(1)),
Subsignal('aburst', Pins(2)),
Subsignal('wvalid', Pins(1)),
Subsignal('aaddr', Pins(32)),
Subsignal('rid', Pins(8)),
Subsignal('avalid', Pins(1)),
Subsignal('rvalid', Pins(1)),
Subsignal('alock', Pins(2)),
Subsignal('rready', Pins(1)),
Subsignal('rresp', Pins(2)),
Subsignal('wstrb', Pins(32)),
Subsignal('aready', Pins(1)),
Subsignal('alen', Pins(8)),
Subsignal('wlast', Pins(1)),
)]
io = platform.add_iface_ios(ios)
port = port0
if i == 1:
port = port1
is_read = port.ar.valid
self.comb += [
io.aaddr.eq(Mux(is_read, port.ar.addr, port.aw.addr)),
io.aid.eq(Mux(is_read, port.ar.id, port.aw.id)),
io.alen.eq(Mux(is_read, port.ar.len, port.aw.len)),
io.asize.eq(Mux(is_read, port.ar.size[0:4], port.aw.size[0:4])), #TODO: check
io.aburst.eq(Mux(is_read, port.ar.burst, port.aw.burst)),
io.alock.eq(Mux(is_read, port.ar.lock, port.aw.lock)),
io.avalid.eq(Mux(is_read, port.ar.valid, port.aw.valid)),
io.atype.eq(~is_read),
port.aw.ready.eq(io.aready),
port.ar.ready.eq(io.aready),
io.wid.eq(port.w.id),
io.wstrb.eq(port.w.strb),
io.wdata.eq(port.w.data),
io.wlast.eq(port.w.last),
io.wvalid.eq(port.w.valid),
port.w.ready.eq(io.wready),
port.r.id.eq(io.rid),
port.r.data.eq(io.rdata),
port.r.last.eq(io.rlast),
port.r.resp.eq(io.rresp),
port.r.valid.eq(io.rvalid),
io.rready.eq(port.r.ready),
port.b.id.eq(io.bid),
port.b.valid.eq(io.bvalid),
io.bready.eq(port.b.ready),
# port.b.resp ??
]
| [
"litex.soc.interconnect.axi.AXIInterface"
] | [((785, 847), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': '(256)', 'address_width': '(32)', 'id_width': '(8)'}), '(data_width=256, address_width=32, id_width=8)\n', (801, 847), False, 'from litex.soc.interconnect import axi\n'), ((913, 975), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': '(256)', 'address_width': '(32)', 'id_width': '(8)'}), '(data_width=256, address_width=32, id_width=8)\n', (929, 975), False, 'from litex.soc.interconnect import axi\n')] |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk48", 0, Pins("M1"), IOStandard("LVCMOS18")),
("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("L16"), IOStandard("LVCMOS33")),
Subsignal("g", Pins("J16"), IOStandard("LVCMOS33")),
Subsignal("b", Pins("J17"), IOStandard("LVCMOS33")),
),
("usb", 0,
Subsignal("d_p", Pins("G15")),
Subsignal("d_n", Pins("K15")),
Subsignal("pullup", Pins("G16")),
IOStandard("LVCMOS33")
),
("hdmi_i2c", 0,
Subsignal("sda", Pins("M16")),
Subsignal("scl", Pins("M17")),
),
("hdmi", 0,
Subsignal("p", Pins("J18 G18 K17 F17"), IOStandard("LVCMOS33D"), Misc("SLEWRATE=FAST"), Misc("DRIVE=8")),
#Subsignal("n", Pins("K18 H17 L18 F16"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")),
),
("i2c", 0,
Subsignal("sda", Pins("N15")),
Subsignal("scl", Pins("N16")),
),
("hyperRAM", 0,
Subsignal("rst_n", Pins("F4"), IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("clk_p", Pins("G4"), IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("clk_n", Pins("H4"), IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("cs_n", Pins("F3"), IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("dq", Pins("K4 L4 J3 K3 L1 M3 N4 N3"), IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("rwds", Pins("H3"), IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
),
("boson", 0,
Subsignal("data", Pins("D15 C17 C13 B17 A2 A10 A11 C2 \
D1 C15 B11 A15 C3 A8 C1 B13 \
B12 B1 D13 B10 B15 A16 A4 A12"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("clk", Pins("A17"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("vsync", Pins("A13"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("hsync", Pins("D16"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("valid", Pins("C16"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("tx", Pins("A3"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("rx", Pins("B9"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("reset", Pins("B2"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("ext_sync", Pins("B18"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
),
("button", 0,
Subsignal("a", Pins("F2"),IOStandard("LVCMOS33"),Misc("PULLMODE=UP")),
Subsignal("b", Pins("J1"),IOStandard("LVCMOS33"),Misc("PULLMODE=UP")),
),
("spiflash", 0,
Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")),
#Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block
Subsignal("miso", Pins("T18"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("U18"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("R18"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("N18"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")),
#Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("U18 T18 R18 N18"), IOStandard("LVCMOS33")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, _connectors, toolchain='trellis', **kwargs)
| [
"litex.build.lattice.LatticePlatform.__init__"
] | [((4033, 4137), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8MG285C"""', '_io', '_connectors'], {'toolchain': '"""trellis"""'}), "(self, 'LFE5U-25F-8MG285C', _io, _connectors,\n toolchain='trellis', **kwargs)\n", (4057, 4137), False, 'from litex.build.lattice import LatticePlatform\n')] |
# Copyright 2020 <NAME> <<EMAIL>>
# Adapted from code by <NAME> <<EMAIL>> https://github.com/smunaut/ice40-playground/blob/icepick/projects/icepick_test/rtl/sense.v
from migen import *
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
from litex.soc.doc.module import ModuleDoc
from litex.build.io import DDRInput
class PWM(Module):
def __init__(self, bitwidth, tick, offset):
...
class AnalogSense(Module, AutoCSR, ModuleDoc):
"""Basic Analog to Digital converter.
Making use of external RC circuit and FPGA differential inputs.
An external Analog Mux is used to enable multilp channels.
"""
def __init__(self, pads):
charge_measurement = Signal(24)
sense_mux = Signal(4)
sense_enable_n = Signal(1)
sense_ctrl = Signal(1)
self.comb += [
pads.mux.eq(sense_mux),
pads.enable.eq(sense_enable_n),
pads.ctrl.eq(sense_ctrl)
]
# CPU interface exposed through CSRs
self._control = CSRStorage(fields=[
CSRField("start", size=1, offset=0, pulse=True, description="Write ``1`` to start a conversion"),
CSRField("chan", size=4, offset=8, description="Channel selector for ADC", values= [
("0b0000", "GND"),
("0b0001", "A0", "analog0"),
("0b0010", "A1", "analog1"),
("0b0011", "A2", "analog2"),
("0b0100", "A3", "analog3"),
("0b0101", "A4", "analog4"),
("0b0110", "A5", "analog5"),
("0b0111", "AREF"),
("0b1000", "3v3"),
("0b1100", "1v35"),
("0b1101", "2v5"),
("0b1110", "1v1"),
("0b1111", "VBAT"), # Through 1/2 divider
]),
])
self._status = CSRStatus(fields=[
CSRField("idle", size=1, offset=0, description="Measurement complete when read as ``1``.")
], description="AnalogSense Status.")
self._result = CSRStatus(24, description="Conversion result.")
# FSM
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
timer = Signal(18)
timer_trig = Signal()
fsm.act("IDLE", If(self._control.fields.start, NextState("SETUP")), NextValue(timer, 0x18000)) # 680us
fsm.act("SETUP", If(timer_trig, NextState("CHARGE"), NextValue(timer, 0x18000))) # 680us
fsm.act("CHARGE", If(timer_trig, NextState("DISCHARGE"),NextValue(timer, 0x0) )) # 2.73ms
fsm.act("DISCHARGE", If(timer_trig, NextState("IDLE")))
# Timers
self.sync += timer.eq(timer + 1)
self.comb += timer_trig.eq(timer[17])
# Input
sense_iob = Signal(2)
self.specials += DDRInput(pads.sense_p, sense_iob[0], sense_iob[1])
sense_value = Signal(2)
self.sync += sense_value.eq(Cat(
sense_iob[0] ^ sense_iob[1],
sense_iob[0] & sense_iob[1]
))
# Measurement Counters
sense_counter = Signal(24)
self.sync += [
If(timer_trig,
sense_counter.eq(0)
).Else(
sense_counter.eq(sense_counter + sense_value)
)
]
# Control Hardware
self.sync += [
If(fsm.ongoing("IDLE"),
sense_mux.eq(Mux(self._control.fields.start,
self._control.fields.chan, 0)),
sense_enable_n.eq(~self._control.fields.start)
),
sense_ctrl.eq(fsm.ongoing("CHARGE")),
]
# IF
self.comb += [
self._status.fields.idle.eq(fsm.ongoing("IDLE")),
self._result.status.eq(charge_measurement)
]
# Save result of charge time
self.sync += If(fsm.ongoing("CHARGE") & timer_trig,
charge_measurement.eq(sense_counter)) | [
"litex.build.io.DDRInput",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr.CSRStatus"
] | [((2185, 2232), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(24)'], {'description': '"""Conversion result."""'}), "(24, description='Conversion result.')\n", (2194, 2232), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((2995, 3045), 'litex.build.io.DDRInput', 'DDRInput', (['pads.sense_p', 'sense_iob[0]', 'sense_iob[1]'], {}), '(pads.sense_p, sense_iob[0], sense_iob[1])\n', (3003, 3045), False, 'from litex.build.io import DDRInput\n'), ((1093, 1194), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""start"""'], {'size': '(1)', 'offset': '(0)', 'pulse': '(True)', 'description': '"""Write ``1`` to start a conversion"""'}), "('start', size=1, offset=0, pulse=True, description=\n 'Write ``1`` to start a conversion')\n", (1101, 1194), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1203, 1618), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""chan"""'], {'size': '(4)', 'offset': '(8)', 'description': '"""Channel selector for ADC"""', 'values': "[('0b0000', 'GND'), ('0b0001', 'A0', 'analog0'), ('0b0010', 'A1', 'analog1'\n ), ('0b0011', 'A2', 'analog2'), ('0b0100', 'A3', 'analog3'), ('0b0101',\n 'A4', 'analog4'), ('0b0110', 'A5', 'analog5'), ('0b0111', 'AREF'), (\n '0b1000', '3v3'), ('0b1100', '1v35'), ('0b1101', '2v5'), ('0b1110',\n '1v1'), ('0b1111', 'VBAT')]"}), "('chan', size=4, offset=8, description='Channel selector for ADC',\n values=[('0b0000', 'GND'), ('0b0001', 'A0', 'analog0'), ('0b0010', 'A1',\n 'analog1'), ('0b0011', 'A2', 'analog2'), ('0b0100', 'A3', 'analog3'), (\n '0b0101', 'A4', 'analog4'), ('0b0110', 'A5', 'analog5'), ('0b0111',\n 'AREF'), ('0b1000', '3v3'), ('0b1100', '1v35'), ('0b1101', '2v5'), (\n '0b1110', '1v1'), ('0b1111', 'VBAT')])\n", (1211, 1618), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((2023, 2118), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""idle"""'], {'size': '(1)', 'offset': '(0)', 'description': '"""Measurement complete when read as ``1``."""'}), "('idle', size=1, offset=0, description=\n 'Measurement complete when read as ``1``.')\n", (2031, 2118), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import argparse
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict
from litex.soc.integration.common import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.integration.soc import *
from litex.soc.cores.bitbang import *
from litex.soc.cores.gpio import GPIOTristate
from litex.soc.cores.cpu import CPUS
from litedram import modules as litedram_modules
from litedram.modules import parse_spd_hexdump
from litedram.phy.model import sdram_module_nphases, get_sdram_phy_settings
from litedram.phy.model import SDRAMPHYModel
from liteeth.phy.gmii import LiteEthPHYGMII
from liteeth.phy.xgmii import LiteEthPHYXGMII
from liteeth.phy.model import LiteEthPHYModel
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
from liteeth.common import *
from litescope import LiteScopeAnalyzer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst.
("sys_clk", 0, Pins(1)),
("sys_rst", 0, Pins(1)),
# Serial.
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
# Ethernet (Stream Endpoint).
("eth_clocks", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
),
("eth", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
# Ethernet (XGMII).
("xgmii_eth", 0,
Subsignal("rx_data", Pins(64)),
Subsignal("rx_ctl", Pins(8)),
Subsignal("tx_data", Pins(64)),
Subsignal("tx_ctl", Pins(8)),
),
# Ethernet (GMII).
("gmii_eth", 0,
Subsignal("rx_data", Pins(8)),
Subsignal("rx_dv", Pins(1)),
Subsignal("rx_er", Pins(1)),
Subsignal("tx_data", Pins(8)),
Subsignal("tx_en", Pins(1)),
Subsignal("tx_er", Pins(1)),
),
# I2C.
("i2c", 0,
Subsignal("scl", Pins(1)),
Subsignal("sda_out", Pins(1)),
Subsignal("sda_in", Pins(1)),
),
# SPI-Flash (X1).
("spiflash", 0,
Subsignal("cs_n", Pins(1)),
Subsignal("clk", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
Subsignal("wp", Pins(1)),
Subsignal("hold", Pins(1)),
),
# SPI-Flash (X4).
("spiflash4x", 0,
Subsignal("cs_n", Pins(1)),
Subsignal("clk", Pins(1)),
Subsignal("dq", Pins(4)),
),
# Tristate GPIOs (for sim control/status).
("gpio", 0,
Subsignal("oe", Pins(32)),
Subsignal("o", Pins(32)),
Subsignal("i", Pins(32)),
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(SimPlatform):
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
# Simulation SoC -----------------------------------------------------------------------------------
class SimSoC(SoCCore):
def __init__(self,
with_sdram = False,
with_ethernet = False,
ethernet_phy_model = "sim",
with_etherbone = False,
etherbone_mac_address = 0x10e2d5000001,
etherbone_ip_address = "192.168.1.51",
with_analyzer = False,
sdram_module = "MT48LC16M16",
sdram_init = [],
sdram_data_width = 32,
sdram_spd_data = None,
sdram_verbosity = 0,
with_i2c = False,
with_sdcard = False,
with_spi_flash = False,
spi_flash_init = [],
with_gpio = False,
sim_debug = False,
trace_reset_on = False,
**kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteX Simulation",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# SDRAM ------------------------------------------------------------------------------------
if not self.integrated_main_ram_size and with_sdram:
sdram_clk_freq = int(100e6) # FIXME: use 100MHz timings
if sdram_spd_data is None:
sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
else:
sdram_module = litedram_modules.SDRAMModule.from_spd_data(sdram_spd_data, sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(
module = sdram_module,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq,
verbosity = sdram_verbosity,
init = sdram_init)
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_module,
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False
)
if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents.
self.add_constant("SDRAM_TEST_DISABLE")
else:
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
# Ethernet / Etherbone PHY -----------------------------------------------------------------
if with_ethernet or with_etherbone:
if ethernet_phy_model == "sim":
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth", 0))
elif ethernet_phy_model == "xgmii":
self.submodules.ethphy = LiteEthPHYXGMII(None, self.platform.request("xgmii_eth", 0), model=True)
elif ethernet_phy_model == "gmii":
self.submodules.ethphy = LiteEthPHYGMII(None, self.platform.request("gmii_eth", 0), model=True)
else:
raise ValueError("Unknown Ethernet PHY model:", ethernet_phy_model)
# Ethernet and Etherbone -------------------------------------------------------------------
if with_ethernet and with_etherbone:
etherbone_ip_address = convert_ip(etherbone_ip_address)
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8)
self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8)
self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8)
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.bus.add_master(master=self.etherbone.wishbone.bus)
# Ethernet ---------------------------------------------------------------------------------
elif with_ethernet:
# Ethernet MAC
self.submodules.ethmac = ethmac = LiteEthMAC(
phy = self.ethphy,
dw = 64 if ethernet_phy_model == "xgmii" else 32,
interface = "wishbone",
endianness = self.cpu.endianness)
ethmac_region_size = (ethmac.rx_slots.read() + ethmac.tx_slots.read()) * ethmac.slot_size.read()
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), ethmac_region_size, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus, ethmac_region_size)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Etherbone --------------------------------------------------------------------------------
elif with_etherbone:
self.add_etherbone(
phy = self.ethphy,
ip_address = etherbone_ip_address,
mac_address = etherbone_mac_address
)
# I2C --------------------------------------------------------------------------------------
if with_i2c:
pads = platform.request("i2c", 0)
self.submodules.i2c = I2CMasterSim(pads)
# SDCard -----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard("sdcard", use_emulator=True)
# SPI Flash --------------------------------------------------------------------------------
if with_spi_flash:
from litespi.phy.model import LiteSPIPHYModel
from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes
spiflash_module = S25FL128L(Codes.READ_1_1_4)
if spi_flash_init is None:
platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/iddr_verilog.v")
platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/oddr_verilog.v")
self.submodules.spiflash_phy = LiteSPIPHYModel(spiflash_module, init=spi_flash_init)
self.add_spi_flash(phy=self.spiflash_phy, mode="4x", module=spiflash_module, with_master=True)
# GPIO --------------------------------------------------------------------------------------
if with_gpio:
self.submodules.gpio = GPIOTristate(platform.request("gpio"), with_irq=True)
self.irq.add("gpio", use_loc_if_exists=True)
# Simulation debugging ----------------------------------------------------------------------
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
else:
self.comb += platform.trace.eq(1)
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# IBus (could also just added as self.cpu.ibus)
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
# DBus (could also just added as self.cpu.dbus)
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
# Build --------------------------------------------------------------------------------------------
def generate_gtkw_savefile(builder, vns, trace_fst):
from litex.build.sim import gtkwave as gtkw
dumpfile = os.path.join(builder.gateware_dir, "sim.{}".format("fst" if trace_fst else "vcd"))
savefile = os.path.join(builder.gateware_dir, "sim.gtkw")
soc = builder.soc
with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile) as save:
save.clocks()
save.fsm_states(soc)
if "main_ram" in soc.bus.slaves.keys():
save.add(soc.bus.slaves["main_ram"], mappers=[gtkw.wishbone_sorter(), gtkw.wishbone_colorer()])
if hasattr(soc, "sdrphy"):
# all dfi signals
save.add(soc.sdrphy.dfi, mappers=[gtkw.dfi_sorter(), gtkw.dfi_in_phase_colorer()])
# each phase in separate group
with save.gtkw.group("dfi phaseX", closed=True):
for i, phase in enumerate(soc.sdrphy.dfi.phases):
save.add(phase, group_name="dfi p{}".format(i), mappers=[
gtkw.dfi_sorter(phases=False),
gtkw.dfi_in_phase_colorer(),
])
# only dfi command/data signals
def dfi_group(name, suffixes):
save.add(soc.sdrphy.dfi, group_name=name, mappers=[
gtkw.regex_filter(gtkw.suffixes2re(suffixes)),
gtkw.dfi_sorter(),
gtkw.dfi_per_phase_colorer(),
])
dfi_group("dfi commands", ["cas_n", "ras_n", "we_n"])
dfi_group("dfi commands", ["wrdata"])
dfi_group("dfi commands", ["wrdata_mask"])
dfi_group("dfi commands", ["rddata"])
def sim_args(parser):
builder_args(parser)
soc_core_args(parser)
verilator_build_args(parser)
parser.add_argument("--rom-init", default=None, help="ROM init file (.bin or .json).")
parser.add_argument("--ram-init", default=None, help="RAM init file (.bin or .json).")
parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support.")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip.")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width.")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file (.bin or .json).")
parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump.")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity.")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
parser.add_argument("--ethernet-phy-model", default="sim", help="Ethernet PHY to simulate (sim, xgmii or gmii).")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC.")
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server.")
parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support.")
parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).")
parser.add_argument("--spi_flash-init", default=None, help="SPI Flash init file.")
parser.add_argument("--with-gpio", action="store_true", help="Enable Tristate GPIO (32 pins).")
parser.add_argument("--sim-debug", action="store_true", help="Add simulation debugging modules.")
parser.add_argument("--gtkwave-savefile", action="store_true", help="Generate GTKWave savefile.")
parser.add_argument("--non-interactive", action="store_true", help="Run simulation without user input.")
def main():
parser = argparse.ArgumentParser(description="LiteX SoC Simulation utility")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
verilator_build_kwargs = verilator_build_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
# UART.
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
# ROM.
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, endianness=cpu.endianness)
# RAM / SDRAM.
soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
if args.integrated_main_ram_size:
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, endianness=cpu.endianness)
elif args.with_sdram:
assert args.ram_init is None
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(args.sdram_from_spd_dump)
# Ethernet.
if args.with_ethernet or args.with_etherbone:
if args.ethernet_phy_model == "sim":
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
elif args.ethernet_phy_model == "xgmii":
sim_config.add_module("xgmii_ethernet", "xgmii_eth", args={"interface": "tap0", "ip": args.remote_ip})
elif args.ethernet_phy_model == "gmii":
sim_config.add_module("gmii_ethernet", "gmii_eth", args={"interface": "tap0", "ip": args.remote_ip})
else:
raise ValueError("Unknown Ethernet PHY model: " + args.ethernet_phy_model)
# I2C.
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(
with_sdram = args.with_sdram,
with_ethernet = args.with_ethernet,
ethernet_phy_model = args.ethernet_phy_model,
with_etherbone = args.with_etherbone,
with_analyzer = args.with_analyzer,
with_i2c = args.with_i2c,
with_sdcard = args.with_sdcard,
with_spi_flash = args.with_spi_flash,
with_gpio = args.with_gpio,
sim_debug = args.sim_debug,
trace_reset_on = int(float(args.trace_start)) > 0 or int(float(args.trace_end)) > 0,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, endianness=cpu.endianness),
spi_flash_init = None if args.spi_flash_init is None else get_mem_data(args.spi_flash_init, endianness="big"),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i+1), int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
def pre_run_callback(vns):
if args.trace:
generate_gtkw_savefile(builder, vns, args.trace_fst)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
builder.build(
sim_config = sim_config,
interactive = not args.non_interactive,
pre_run_callback = pre_run_callback,
**verilator_build_kwargs,
)
if __name__ == "__main__":
main()
| [
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"litex.build.sim.verilator.verilator_build_argdict",
"litex.build.sim.gtkwave.dfi_in_phase_colorer",
"litex.build.sim.SimPlatform.__init__",
"litex.build.sim.gtkwave.wishbone_sorter",
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("23"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("84"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("85"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("86"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("87"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
# Uses the 9 pin serial connector
Subsignal("tx", Pins("114"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("115"), IOStandard("3.3-V LVTTL"))
),
# SDRAM
("sdram_clock", 0, Pins("43"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"76 77 80 83 68 67 66 65",
"64 60 75 59")),
Subsignal("ba", Pins("73 74")),
Subsignal("cs_n", Pins("72")),
Subsignal("cke", Pins("58")),
Subsignal("ras_n", Pins("71")),
Subsignal("cas_n", Pins("70")),
Subsignal("we_n", Pins("69")),
Subsignal("dq", Pins(
"28 30 31 32 33 34 38 39",
"54 53 52 51 50 49 46 44")),
Subsignal("dm", Pins("42 55")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP4CE6E22C8", _io, toolchain=toolchain)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster"
] | [((1784, 1854), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE6E22C8"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'EP4CE6E22C8', _io, toolchain=toolchain)\n", (1807, 1854), False, 'from litex.build.altera import AlteraPlatform\n'), ((1904, 1916), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (1914, 1916), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((1963, 2005), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1989, 2005), False, 'from litex.build.altera import AlteraPlatform\n')] |
from migen import *
from targets.netv2.base import SoC as BaseSoC
from litex.soc.interconnect import wishbone
from litex.soc.cores.freqmeter import FreqMeter
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
from litevideo.input import HDMIIn
from litevideo.output import VideoOut
from targets.utils import period_ns, csr_map_update
class WishboneEndianSwap(Module):
def __init__(self, wb_if):
self.wishbone = wishbone.Interface()
self.sync += [
self.wishbone.adr.eq(wb_if.adr),
self.wishbone.dat_w[0:8].eq(wb_if.dat_w[24:32]),
self.wishbone.dat_w[8:16].eq(wb_if.dat_w[16:24]),
self.wishbone.dat_w[16:24].eq(wb_if.dat_w[8:16]),
self.wishbone.dat_w[24:32].eq(wb_if.dat_w[0:8]),
#self.wishbone.dat_w.eq(wb_if.dat_w),
wb_if.dat_r[0:8].eq(self.wishbone.dat_r[24:32]),
wb_if.dat_r[8:16].eq(self.wishbone.dat_r[16:24]),
wb_if.dat_r[16:24].eq(self.wishbone.dat_r[8:16]),
wb_if.dat_r[24:32].eq(self.wishbone.dat_r[0:8]),
#wb_if.dat_r.eq(self.wishbone.dat_r),
self.wishbone.sel[3].eq(wb_if.sel[0]),
self.wishbone.sel[2].eq(wb_if.sel[1]),
self.wishbone.sel[1].eq(wb_if.sel[2]),
self.wishbone.sel[0].eq(wb_if.sel[3]),
#self.wishbone.sel.eq(wb_if.sel),
self.wishbone.cyc.eq(wb_if.cyc),
self.wishbone.stb.eq(wb_if.stb),
wb_if.ack.eq(self.wishbone.ack),
self.wishbone.we.eq(wb_if.we),
self.wishbone.cti.eq(wb_if.cti),
self.wishbone.bte.eq(wb_if.bte),
wb_if.err.eq(self.wishbone.err),
]
class HDMI2PCIeSoC(BaseSoC):
csr_peripherals = [
"pcie_phy",
"pcie_dma0",
"pcie_dma1",
"pcie_msi",
"hdmi_out0",
"hdmi_in0",
"hdmi_in0_freq",
"hdmi_in0_edid_mem",
]
csr_map_update(BaseSoC.csr_map, csr_peripherals)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, csr_data_width=32, *args, **kwargs)
sys_clk_freq = int(100e6)
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), bar0_size=32*1024*1024)
platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy)
# pcie wishbone bridge
self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1, shadow_base=0x40000000)
self.submodules.wb_swap = WishboneEndianSwap(self.pcie_bridge.wishbone)
self.add_wb_master(self.wb_swap.wishbone)
# pcie dma
self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
# pcie msi
self.submodules.pcie_msi = LitePCIeMSI()
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq,
"PCIE_DMA0_READER": self.pcie_dma0.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# hdmi in 0
hdmi_in0_pads = platform.request("hdmi_in", 0)
self.submodules.hdmi_in0_freq = FreqMeter(period=sys_clk_freq)
self.submodules.hdmi_in0 = HDMIIn(
hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=1024,
device="xc7",
split_mmcm=True)
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk),
for clk in [self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
self.platform.add_period_constraint(platform.lookup_request("hdmi_in", 0).clk_p, period_ns(148.5e6))
# hdmi out 0
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(
platform.device,
platform.request("hdmi_out", 0),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
for clk in [self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk]:
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, clk)
for name, value in sorted(self.platform.hdmi_infos.items()):
self.add_constant(name, value)
self.add_interrupt("hdmi_in0")
SoC = HDMI2PCIeSoC
| [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.freqmeter.FreqMeter"
] | [((2088, 2136), 'targets.utils.csr_map_update', 'csr_map_update', (['BaseSoC.csr_map', 'csr_peripherals'], {}), '(BaseSoC.csr_map, csr_peripherals)\n', (2102, 2136), False, 'from targets.utils import period_ns, csr_map_update\n'), ((587, 607), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (605, 607), False, 'from litex.soc.interconnect import wishbone\n'), ((2197, 2265), 'targets.netv2.base.SoC.__init__', 'BaseSoC.__init__', (['self', 'platform', '*args'], {'csr_data_width': '(32)'}), '(self, platform, *args, csr_data_width=32, **kwargs)\n', (2213, 2265), True, 'from targets.netv2.base import SoC as BaseSoC\n'), ((2611, 2642), 'litepcie.core.LitePCIeEndpoint', 'LitePCIeEndpoint', (['self.pcie_phy'], {}), '(self.pcie_phy)\n', (2627, 2642), False, 'from litepcie.core import LitePCIeEndpoint, LitePCIeMSI\n'), ((2713, 2792), 'litepcie.frontend.wishbone.LitePCIeWishboneBridge', 'LitePCIeWishboneBridge', (['self.pcie_endpoint', '(lambda a: 1)'], {'shadow_base': '(1073741824)'}), '(self.pcie_endpoint, lambda a: 1, shadow_base=1073741824)\n', (2735, 2792), False, 'from litepcie.frontend.wishbone import LitePCIeWishboneBridge\n'), ((2979, 3045), 'litepcie.frontend.dma.LitePCIeDMA', 'LitePCIeDMA', (['self.pcie_phy', 'self.pcie_endpoint'], {'with_loopback': '(True)'}), '(self.pcie_phy, self.pcie_endpoint, with_loopback=True)\n', (2990, 3045), False, 'from litepcie.frontend.dma import LitePCIeDMA\n'), ((3101, 3114), 'litepcie.core.LitePCIeMSI', 'LitePCIeMSI', ([], {}), '()\n', (3112, 3114), False, 'from litepcie.core import LitePCIeEndpoint, LitePCIeMSI\n'), ((3634, 3664), 'litex.soc.cores.freqmeter.FreqMeter', 'FreqMeter', ([], {'period': 'sys_clk_freq'}), '(period=sys_clk_freq)\n', (3643, 3664), False, 'from litex.soc.cores.freqmeter import FreqMeter\n'), ((4299, 4321), 'targets.utils.period_ns', 'period_ns', (['(148500000.0)'], {}), '(148500000.0)\n', (4308, 4321), False, 'from targets.utils import period_ns, csr_map_update\n')] |
from migen import *
from litespi.common import spi_phy_ctl_layout, spi_phy_data_layout, USER
from litex.soc.interconnect.stream import Endpoint
PROGRAM_SIZE = 256
#ERASE_CMD = 0x20
#ERASE_SIZE = 4096
ERASE_CMD = 0xd8
ERASE_SIZE = 65536
class FlashWriter(Module):
def __init__(self):
# PHY interface
self.phy_source = phy_source = Endpoint(spi_phy_ctl_layout)
self.phy_sink = phy_sink = Endpoint(spi_phy_data_layout)
self.cs = cs = Signal()
self.request = request = Signal()
# Write interface
self.sink = sink = Endpoint([('data', 8), ('addr', 24)])
self.comb += [
phy_source.cmd.eq(USER),
]
erase_required = sink.addr & (ERASE_SIZE - 1) == 0
erase_done = Signal()
program_done = Signal()
self.submodules.fsm = fsm = FSM()
fsm.act('IDLE',
If(sink.valid,
NextState('WREN'),
)
)
fsm.act('WREN',
cs.eq(1),
request.eq(1),
phy_source.data.eq(0x06),
phy_source.len.eq(8),
phy_source.width.eq(1),
phy_source.mask.eq(1),
phy_source.valid.eq(1),
If(phy_source.ready,
NextState('WREN_WAIT'),
),
)
fsm.act('WREN_WAIT',
cs.eq(1),
request.eq(1),
phy_sink.ready.eq(1),
If(phy_sink.valid,
cs.eq(0),
If(erase_required & ~erase_done,
NextState('ERASE'),
NextValue(erase_done, 1)
).Else(
NextState('PROGRAM'),
NextValue(erase_done, 0)
)
),
)
fsm.act('ERASE',
cs.eq(1),
request.eq(1),
phy_source.data.eq(Cat(sink.addr, ERASE_CMD)),
phy_source.len.eq(8 + 24),
phy_source.width.eq(1),
phy_source.mask.eq(1),
phy_source.valid.eq(1),
If(phy_source.ready,
NextState('ERASE_WAIT'),
),
)
fsm.act('ERASE_WAIT',
cs.eq(1),
request.eq(1),
phy_sink.ready.eq(1),
If(phy_sink.valid,
cs.eq(0),
NextState('READ_STATUS'),
),
)
fsm.act('READ_STATUS',
cs.eq(1),
request.eq(1),
phy_source.data.eq(0x0500),
phy_source.len.eq(16),
phy_source.width.eq(1),
phy_source.mask.eq(1),
phy_source.valid.eq(1),
If(phy_source.ready,
NextState('READ_STATUS_WAIT'),
),
)
fsm.act('READ_STATUS_WAIT',
cs.eq(1),
request.eq(1),
phy_sink.ready.eq(1),
If(phy_sink.valid,
cs.eq(0),
If(phy_sink.data[0],
NextState('READ_STATUS'),
).Elif(sink.valid,
NextState('WREN'),
).Else(
NextState('IDLE'),
),
),
)
fsm.act('PROGRAM',
cs.eq(1),
request.eq(1),
phy_source.data.eq(Cat(sink.addr, 0x02)),
phy_source.len.eq(8 + 24),
phy_source.width.eq(1),
phy_source.mask.eq(1),
phy_source.valid.eq(1),
If(phy_source.ready,
NextState('PROGRAM_DATA'),
),
)
fsm.act('PROGRAM_DATA',
cs.eq(1),
request.eq(1),
phy_source.data.eq(sink.data),
phy_source.len.eq(8),
phy_source.width.eq(1),
phy_source.mask.eq(1),
phy_source.valid.eq(sink.valid),
sink.ready.eq(phy_source.ready),
phy_sink.ready.eq(1),
If(sink.valid & sink.ready & (sink.last | (sink.addr & (PROGRAM_SIZE - 1) == (PROGRAM_SIZE - 1))),
NextState('PROGRAM_WAIT'),
),
)
fsm.act('PROGRAM_WAIT',
cs.eq(1),
request.eq(1),
phy_sink.ready.eq(1),
If(program_done,
cs.eq(0),
NextState('READ_STATUS'),
),
)
outstanding_transfers = Signal(max = PROGRAM_SIZE + 2)
transfer_out = phy_source.valid & phy_source.ready
transfer_in = phy_sink.valid & phy_sink.ready
self.sync += [
If(fsm.ongoing('PROGRAM'),
outstanding_transfers.eq(1),
),
If(fsm.ongoing('PROGRAM_DATA') | fsm.ongoing('PROGRAM_WAIT'),
If(transfer_out & ~transfer_in,
outstanding_transfers.eq(outstanding_transfers + 1),
),
If(~transfer_out & transfer_in,
outstanding_transfers.eq(outstanding_transfers - 1),
),
),
]
self.comb += program_done.eq(outstanding_transfers == 0)
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((356, 384), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (['spi_phy_ctl_layout'], {}), '(spi_phy_ctl_layout)\n', (364, 384), False, 'from litex.soc.interconnect.stream import Endpoint\n'), ((420, 449), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (['spi_phy_data_layout'], {}), '(spi_phy_data_layout)\n', (428, 449), False, 'from litex.soc.interconnect.stream import Endpoint\n'), ((578, 615), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 8), ('addr', 24)]"], {}), "([('data', 8), ('addr', 24)])\n", (586, 615), False, 'from litex.soc.interconnect.stream import Endpoint\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteSPI
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litespi.modules import W25Q32JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
from litespi.phy.generic import LiteSPIPHY
from litespi import LiteSPI
from litex.build.io import DDROutput
from litedram.modules import M12L16161A
from litedram.phy import GENSDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from litex.build.generic_platform import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_rst=True):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys_ps = ClockDomain()
# # #
clk25 = platform.request("clk25")
rst_n = 1 if not with_rst else platform.request("user_btn_n", 0)
platform.add_period_constraint(clk25, 1e9/25e6)
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked | ~rst_n)
# SDRAM clock
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), ClockSignal("sys_ps"))
# BaseSoC ------------------------------------------------------------------------------------------
ios = [
# Alternative pins for UART to avoid reset button conflict with user_btn_n and user_led_n
# Requires modification to the Colorlight board to allow input on rx
("uart", 0,
Subsignal("tx", Pins("j9:1")),
Subsignal("rx", Pins("j9:0")),
IOStandard("LVCMOS33")
)
]
class BaseSoC(SoCCore):
def __init__(self,
sys_clk_freq = int(60e6),
with_ethernet = False,
with_etherbone = False,
with_spiflash = False,
ip_address = None,
mac_address = None,
**kwargs):
platform = colorlight_5a_75e.Platform()
platform.add_extension(ios)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform,
clk_freq = sys_clk_freq,
ident = "LiteX LiteSPI SoC",
ident_version = True,
csr_data_width = 32,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_rst=(kwargs["uart_name"] != "serial"))
# SDRAM ------------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram("sdram",
phy = self.sdrphy,
module = M12L16161A(sys_clk_freq, "1:1"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True)
# SPIFlash ---------------------------------------------------------------------------------
if with_spiflash:
flash = W25Q32JV(Codes.READ_1_1_1)
self.submodules.spiflash_phy = LiteSPIPHY(
pads = platform.request("spiflash"),
flash = flash,
device = platform.device)
self.submodules.spiflash_mmap = LiteSPI(
phy = self.spiflash_phy,
clk_freq = sys_clk_freq,
mmap_endianness = self.cpu.endianness)
self.add_csr("spiflash_mmap")
self.add_csr("spiflash_phy")
spiflash_region = SoCRegion(
origin = self.mem_map.get("spiflash", None),
size = flash.total_size,
cached = False)
self.bus.add_slave(
name = "spiflash",
slave = self.spiflash_mmap.bus,
region = spiflash_region)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_ethernet(
phy = self.ethphy,
ip_address = ip_address,
mac_address = mac_address)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
self.add_etherbone(
phy = self.ethphy,
ip_address = ip_address,
mac_address = mac_address)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX LiteSPI SoC on Colorlight")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--with-spiflash", action="store_true", help="Enable SPIFlash support")
parser.add_argument("--ip-address", default="192.168.1.20", help="Ethernet IP address of the board.")
parser.add_argument("--mac-address", default="0x726b895bc2e2", help="Ethernet MAC address of the board.")
args = parser.parse_args()
assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_spiflash = args.with_spiflash,
ip_address = args.ip_address,
mac_address = int(args.mac_address, 0),
**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
| [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((6036, 6106), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX LiteSPI SoC on Colorlight"""'}), "(description='LiteX LiteSPI SoC on Colorlight')\n", (6059, 6106), False, 'import argparse\n'), ((6322, 6342), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (6334, 6342), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((2567, 2595), 'litex_boards.platforms.colorlight_5a_75e.Platform', 'colorlight_5a_75e.Platform', ([], {}), '()\n', (2593, 2595), False, 'from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e\n'), ((4050, 4076), 'litespi.modules.W25Q32JV', 'W25Q32JV', (['Codes.READ_1_1_1'], {}), '(Codes.READ_1_1_1)\n', (4058, 4076), False, 'from litespi.modules import W25Q32JV\n'), ((4313, 4408), 'litespi.LiteSPI', 'LiteSPI', ([], {'phy': 'self.spiflash_phy', 'clk_freq': 'sys_clk_freq', 'mmap_endianness': 'self.cpu.endianness'}), '(phy=self.spiflash_phy, clk_freq=sys_clk_freq, mmap_endianness=self.\n cpu.endianness)\n', (4320, 4408), False, 'from litespi import LiteSPI\n'), ((7322, 7343), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (7337, 7343), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((7456, 7515), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (7468, 7515), False, 'import os\n'), ((3518, 3549), 'litedram.modules.M12L16161A', 'M12L16161A', (['sys_clk_freq', '"""1:1"""'], {}), "(sys_clk_freq, '1:1')\n", (3528, 3549), False, 'from litedram.modules import M12L16161A\n')] |
# This file is Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016 <NAME> <<EMAIL>>
# License: BSD
from functools import reduce
from operator import and_
from migen import *
from migen.genlib.cdc import MultiReg, ElasticBuffer
from migen.genlib.misc import WaitTimer
from migen.genlib.io import DifferentialInput, DifferentialOutput
from migen.genlib.fifo import SyncFIFO
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
from litejesd204b.transport import LiteJESD204BTransportTX, LiteJESD204BTransportRX
from litejesd204b.transport import LiteJESD204BSTPLGenerator, LiteJESD204BSTPLChecker
from litejesd204b.link import LiteJESD204BLinkTX, LiteJESD204BLinkRX
# Clock Domain Crossing ----------------------------------------------------------------------------
class LiteJESD204BTXCDC(Module):
def __init__(self, phy, phy_cd):
assert len(phy.sink.data) in [16, 32]
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", len(phy.sink.data)), ("ctrl", len(phy.sink.ctrl))])
# # #
use_ebuf = (len(phy.sink.data) == 32)
if use_ebuf:
ebuf = ElasticBuffer(len(phy.sink.data) + len(phy.source.ctrl), 4, "jesd", phy_cd)
self.submodules.ebuf = ebuf
self.comb += [
sink.ready.eq(1),
ebuf.din[:32].eq(sink.data),
ebuf.din[32:].eq(sink.ctrl),
source.valid.eq(1),
source.data.eq(ebuf.dout[:32]),
source.ctrl.eq(ebuf.dout[32:])
]
else:
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 4)
cdc = ClockDomainsRenamer({"write": "jesd", "read": phy_cd})(cdc)
self.submodules += cdc
converter = stream.StrideConverter(
[("data", 32), ("ctrl", 4)],
[("data", len(phy.sink.data)), ("ctrl", len(phy.sink.ctrl))],
reverse=False)
converter = ClockDomainsRenamer(phy_cd)(converter)
self.submodules += converter
self.comb += [
sink.connect(cdc.sink),
cdc.source.connect(converter.sink),
converter.source.connect(source)
]
class LiteJESD204BRXCDC(Module):
def __init__(self, phy, phy_cd):
assert len(phy.source.data) in [16, 32]
self.sink = sink = stream.Endpoint([("data", len(phy.source.data)), ("ctrl", len(phy.source.ctrl))])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
# # #
use_ebuf = (len(phy.source.data) == 32)
if use_ebuf:
ebuf = ElasticBuffer(len(phy.source.data) + len(phy.source.ctrl), 4, phy_cd, "jesd")
self.submodules.ebuf = ebuf
self.comb += [
sink.ready.eq(1),
ebuf.din[:32].eq(sink.data),
ebuf.din[32:].eq(sink.ctrl),
source.valid.eq(1),
source.data.eq(ebuf.dout[:32]),
source.ctrl.eq(ebuf.dout[32:])
]
else:
converter = stream.StrideConverter(
[("data", len(phy.source.data)), ("ctrl", len(phy.source.ctrl))],
[("data", 32), ("ctrl", 4)],
reverse=False)
converter = ClockDomainsRenamer(phy_cd)(converter)
self.submodules += converter
cdc = stream.AsyncFIFO([("data", 32), ("ctrl", 4)], 4)
cdc = ClockDomainsRenamer({"write": phy_cd, "read": "jesd"})(cdc)
self.submodules += cdc
self.comb += [
sink.connect(converter.sink),
converter.source.connect(cdc.sink),
cdc.source.connect(source)
]
# Core TX ------------------------------------------------------------------------------------------
class LiteJESD204BCoreTX(Module):
def __init__(self, phys, jesd_settings, converter_data_width):
self.enable = Signal()
self.jsync = Signal()
self.jref = Signal()
self.ready = Signal()
self.restart = Signal()
self.stpl_enable = Signal()
self.sink = Record([("converter"+str(i), converter_data_width)
for i in range(jesd_settings.nconverters)])
# # #
# Restart when disabled...
self.comb += If(~self.enable, self.restart.eq(1))
# ... or on re-synchronization request from the DAC.
jsync = Signal()
jsync_timer = ClockDomainsRenamer("jesd")(WaitTimer(256))
self.submodules += jsync_timer
self.comb += jsync_timer.wait.eq(~jsync)
self.specials += MultiReg(self.jsync, jsync, "jesd")
self.comb += If(self.ready & jsync_timer.done, self.restart.eq(1))
# transport layer
transport = LiteJESD204BTransportTX(jesd_settings, converter_data_width)
transport = ClockDomainsRenamer("jesd")(transport)
self.submodules.transport = transport
# stpl
stpl = LiteJESD204BSTPLGenerator(jesd_settings, converter_data_width)
stpl = ClockDomainsRenamer("jesd")(stpl)
self.submodules.stpl = stpl
self.comb += \
If(self.stpl_enable,
transport.sink.eq(stpl.source)
).Else(
transport.sink.eq(self.sink)
)
self.links = links = []
for n, (phy, lane) in enumerate(zip(phys, transport.source.flatten())):
phy_name = "jesd_phy{}".format(n if not hasattr(phy, "n") else phy.n)
phy_cd = phy_name + "_tx"
cdc = LiteJESD204BTXCDC(phy, phy_cd)
setattr(self.submodules, "cdc"+str(n), cdc)
link = LiteJESD204BLinkTX(32, jesd_settings, n)
link = ClockDomainsRenamer("jesd")(link)
self.submodules += link
links.append(link)
self.comb += [
link.reset.eq(self.restart),
link.jsync.eq(self.jsync),
link.jref.eq(self.jref)
]
# connect data
self.comb += [
link.sink.data.eq(lane),
cdc.sink.valid.eq(1),
cdc.sink.data.eq(link.source.data),
cdc.sink.ctrl.eq(link.source.ctrl),
cdc.source.connect(phy.sink)
]
self.sync.jesd += self.ready.eq(reduce(and_, [link.ready for link in links]))
def register_jsync(self, jsync):
self.jsync_registered = True
if isinstance(jsync, Signal):
self.comb += self.jsync.eq(jsync)
elif isinstance(jsync, Record):
self.specials += DifferentialInput(jsync.p, jsync.n, self.jsync)
else:
raise ValueError
def register_jref(self, jref):
self.jref_registered = True
if isinstance(jref, Signal):
self.comb += self.jref.eq(jref)
elif isinstance(jref, Record):
self.specials += DifferentialInput(jref.p, jref.n, self.jref)
else:
raise ValueError
def do_finalize(self):
assert hasattr(self, "jsync_registered")
assert hasattr(self, "jref_registered")
# Core RX ------------------------------------------------------------------------------------------
class LiteJESD204BCoreRX(Module):
def __init__(self, phys, jesd_settings, converter_data_width, ilas_check=True):
self.enable = Signal()
self.jsync = Signal()
self.jref = Signal()
self.ready = Signal()
self.restart = Signal()
self.stpl_enable = Signal()
self.source = Record([("converter"+str(i), converter_data_width)
for i in range(jesd_settings.nconverters)])
# # #
# Restart when disabled.
self.comb += If(~self.enable, self.restart.eq(1))
# transport layer
transport = LiteJESD204BTransportRX(jesd_settings, converter_data_width)
transport = ClockDomainsRenamer("jesd")(transport)
self.submodules.transport = transport
# stpl
stpl = LiteJESD204BSTPLChecker(jesd_settings, converter_data_width)
stpl = ClockDomainsRenamer("jesd")(stpl)
self.submodules.stpl = stpl
self.comb += \
If(self.stpl_enable,
stpl.sink.eq(transport.source)
).Else(
self.source.eq(transport.source)
)
self.links = links = []
self.skew_fifos = skew_fifos = []
for n, (phy, lane) in enumerate(zip(phys, transport.sink.flatten())):
phy_name = "jesd_phy{}".format(n if not hasattr(phy, "n") else phy.n)
phy_cd = phy_name + "_rx"
cdc = LiteJESD204BRXCDC(phy, phy_cd)
setattr(self.submodules, "cdc"+str(n), cdc)
link = LiteJESD204BLinkRX(32, jesd_settings, n, ilas_check)
link = ClockDomainsRenamer("jesd")(link)
self.submodules += link
links.append(link)
self.comb += [
link.reset.eq(self.restart),
link.jref.eq(self.jref),
phy.rx_align.eq(link.align)
]
skew_fifo = SyncFIFO(32, 2*jesd_settings.lmfc_cycles)
skew_fifo = ClockDomainsRenamer("jesd")(skew_fifo)
skew_fifo = ResetInserter()(skew_fifo)
skew_fifos.append(skew_fifo)
self.submodules += skew_fifo
self.comb += [
skew_fifo.reset.eq(~link.ready),
skew_fifo.we.eq(1),
skew_fifo.re.eq(self.ready),
]
# connect data
self.comb += [
phy.source.connect(cdc.sink),
link.sink.data.eq(cdc.source.data),
link.sink.ctrl.eq(cdc.source.ctrl),
cdc.source.ready.eq(1),
skew_fifo.din.eq(link.source.data),
lane.eq(skew_fifo.dout)
]
self.sync.jesd += [
self.jsync.eq(reduce(and_, [link.jsync for link in links])),
self.ready.eq(reduce(and_, [link.ready for link in links])),
]
def register_jsync(self, jsync):
self.jsync_registered = True
if isinstance(jsync, Signal):
self.comb += jsync.eq(self.jsync)
elif isinstance(jsync, Record):
self.specials += DifferentialOutput(self.jsync, jsync.p, jsync.n)
else:
raise ValueError
def register_jref(self, jref):
self.jref_registered = True
if isinstance(jref, Signal):
self.comb += self.jref.eq(jref)
elif isinstance(jref, Record):
self.specials += DifferentialInput(jref.p, jref.n, self.jref)
else:
raise ValueError
def do_finalize(self):
assert hasattr(self, "jsync_registered")
assert hasattr(self, "jref_registered")
# Core Control ----------------------------------------------------------------------------------
class LiteJESD204BCoreControl(Module, AutoCSR):
def __init__(self, core, sys_clk_freq):
self.enable = CSRStorage()
self.ready = CSRStatus()
self.stpl_enable = CSRStorage()
self.stpl_errors = CSRStatus(32)
self.jsync = CSRStatus()
# # #
self.core = core
self.specials += [
MultiReg(self.enable.storage, core.enable, "jesd"),
MultiReg(self.stpl_enable.storage, core.stpl_enable, "jesd"),
MultiReg(core.stpl.errors, self.stpl_errors.status, "sys"),
MultiReg(core.ready, self.ready.status, "sys")
]
jsync_timer = WaitTimer(int(1e-3*sys_clk_freq))
self.submodules += jsync_timer
self.specials += MultiReg(core.jsync, jsync_timer.wait, "sys")
self.comb += self.jsync.status.eq(jsync_timer.done)
def add_advanced_controls(self):
self.jsync_toggles = CSRStatus(32)
self.lmfc_load = CSRStorage(
size = len(self.core.links[0].lmfc.load),
reset = self.core.links[0].lmfc.load.reset)
if isinstance(self.core, LiteJESD204BCoreRX):
for n in range(len(self.core.skew_fifos)):
csr = CSRStatus(len(self.core.skew_fifos[n].level),
name="skew_fifo{}_level".format(n))
setattr(self, "skew_fifo{}_level".format(n), csr)
# # #
# JSYNC toggles
jsync = Signal()
jsync_d = Signal()
jsync_toggle = Signal()
jsync_toggles = Signal(32)
self.specials += MultiReg(self.core.jsync, jsync)
self.sync += jsync_d.eq(jsync)
self.comb += jsync_toggle.eq(jsync ^ jsync_d)
self.sync += [
If(~self.enable.storage,
jsync_toggles.eq(0)
).Elif(jsync_toggle,
If(jsync_toggles != (2**32-1),
jsync_toggles.eq(jsync_toggles + 1)
)
)
]
self.comb += self.jsync_toggles.status.eq(jsync_toggles)
# LMFC load on SYSREF
for n in range(len(self.core.links)):
self.comb += self.core.links[n].lmfc.load.eq(self.lmfc_load.storage)
# Skew FIFOs level (RX only)
if isinstance(self.core, LiteJESD204BCoreRX):
for n in range(len(self.core.skew_fifos)):
csr_status = getattr(self, "skew_fifo{}_level".format(n))
self.specials += MultiReg(self.core.skew_fifos[n].level, csr_status.status)
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"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((971, 1015), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (986, 1015), False, 'from litex.soc.interconnect import stream\n'), ((2586, 2630), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (2601, 2630), False, 'from litex.soc.interconnect import stream\n'), ((4740, 4775), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['self.jsync', 'jsync', '"""jesd"""'], {}), "(self.jsync, jsync, 'jesd')\n", (4748, 4775), False, 'from migen.genlib.cdc import MultiReg, ElasticBuffer\n'), ((4898, 4958), 'litejesd204b.transport.LiteJESD204BTransportTX', 'LiteJESD204BTransportTX', (['jesd_settings', 'converter_data_width'], {}), '(jesd_settings, converter_data_width)\n', (4921, 4958), False, 'from litejesd204b.transport import LiteJESD204BTransportTX, LiteJESD204BTransportRX\n'), ((5095, 5157), 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#
# This file is part of USB3-PIPE project.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from functools import reduce
from operator import xor
from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.common import COM
# Scrambler Unit (Appendix B) ----------------------------------------------------------------------
@ResetInserter()
@CEInserter()
class ScramblerUnit(Module):
"""Scrambler Unit
This module generates the scrambled datas for the USB3.0 link (X^16 + X^5 + X^4 + X^3 + 1 polynom).
"""
def __init__(self, reset=0xffff):
self.value = Signal(32)
# # #
new = Signal(16)
cur = Signal(16, reset=reset)
self.comb += [
new[0].eq(cur[0] ^ cur[6] ^ cur[8] ^ cur[10]),
new[1].eq(cur[1] ^ cur[7] ^ cur[9] ^ cur[11]),
new[2].eq(cur[2] ^ cur[8] ^ cur[10] ^ cur[12]),
new[3].eq(cur[3] ^ cur[6] ^ cur[8] ^ cur[9] ^ cur[10] ^ cur[11] ^ cur[13]),
new[4].eq(cur[4] ^ cur[6] ^ cur[7] ^ cur[8] ^ cur[9] ^ cur[11] ^ cur[12] ^ cur[14]),
new[5].eq(cur[5] ^ cur[6] ^ cur[7] ^ cur[9] ^ cur[12] ^ cur[13] ^ cur[15]),
new[6].eq(cur[0] ^ cur[6] ^ cur[7] ^ cur[8] ^ cur[10] ^ cur[13] ^ cur[14]),
new[7].eq(cur[1] ^ cur[7] ^ cur[8] ^ cur[9] ^ cur[11] ^ cur[14] ^ cur[15]),
new[8].eq(cur[0] ^ cur[2] ^ cur[8] ^ cur[9] ^ cur[10] ^ cur[12] ^ cur[15]),
new[9].eq(cur[1] ^ cur[3] ^ cur[9] ^ cur[10] ^ cur[11] ^ cur[13]),
new[10].eq(cur[0] ^ cur[2] ^ cur[4] ^ cur[10] ^ cur[11] ^ cur[12] ^ cur[14]),
new[11].eq(cur[1] ^ cur[3] ^ cur[5] ^ cur[11] ^ cur[12] ^ cur[13] ^ cur[15]),
new[12].eq(cur[2] ^ cur[4] ^ cur[6] ^ cur[12] ^ cur[13] ^ cur[14]),
new[13].eq(cur[3] ^ cur[5] ^ cur[7] ^ cur[13] ^ cur[14] ^ cur[15]),
new[14].eq(cur[4] ^ cur[6] ^ cur[8] ^ cur[14] ^ cur[15]),
new[15].eq(cur[5] ^ cur[7] ^ cur[9] ^ cur[15]),
self.value[0].eq(cur[15]),
self.value[1].eq(cur[14]),
self.value[2].eq(cur[13]),
self.value[3].eq(cur[12]),
self.value[4].eq(cur[11]),
self.value[5].eq(cur[10]),
self.value[6].eq(cur[9]),
self.value[7].eq(cur[8]),
self.value[8].eq(cur[7]),
self.value[9].eq(cur[6]),
self.value[10].eq(cur[5]),
self.value[11].eq(cur[4] ^ cur[15]),
self.value[12].eq(cur[3] ^ cur[14] ^ cur[15]),
self.value[13].eq(cur[2] ^ cur[13] ^ cur[14] ^ cur[15]),
self.value[14].eq(cur[1] ^ cur[12] ^ cur[13] ^ cur[14]),
self.value[15].eq(cur[0] ^ cur[11] ^ cur[12] ^ cur[13]),
self.value[16].eq(cur[10] ^ cur[11] ^ cur[12] ^ cur[15]),
self.value[17].eq(cur[9] ^ cur[10] ^ cur[11] ^ cur[14]),
self.value[18].eq(cur[8] ^ cur[9] ^ cur[10] ^ cur[13]),
self.value[19].eq(cur[7] ^ cur[8] ^ cur[9] ^ cur[12]),
self.value[20].eq(cur[6] ^ cur[7] ^ cur[8] ^ cur[11]),
self.value[21].eq(cur[5] ^ cur[6] ^ cur[7] ^ cur[10]),
self.value[22].eq(cur[4] ^ cur[5] ^ cur[6] ^ cur[9] ^ cur[15]),
self.value[23].eq(cur[3] ^ cur[4] ^ cur[5] ^ cur[8] ^ cur[14]),
self.value[24].eq(cur[2] ^ cur[3] ^ cur[4] ^ cur[7] ^ cur[13] ^ cur[15]),
self.value[25].eq(cur[1] ^ cur[2] ^ cur[3] ^ cur[6] ^ cur[12] ^ cur[14]),
self.value[26].eq(cur[0] ^ cur[1] ^ cur[2] ^ cur[5] ^ cur[11] ^ cur[13] ^ cur[15]),
self.value[27].eq(cur[0] ^ cur[1] ^ cur[4] ^ cur[10] ^ cur[12] ^ cur[14]),
self.value[28].eq(cur[0] ^ cur[3] ^ cur[9] ^ cur[11] ^ cur[13]),
self.value[29].eq(cur[2] ^ cur[8] ^ cur[10] ^ cur[12]),
self.value[30].eq(cur[1] ^ cur[7] ^ cur[9] ^ cur[11]),
self.value[31].eq(cur[0] ^ cur[6] ^ cur[8] ^ cur[10]),
]
self.sync += cur.eq(new)
# Scrambler (Appendix B) ---------------------------------------------------------------------------
class Scrambler(Module):
"""Scrambler
This module scrambles the TX data/ctrl stream. K codes shall not be scrambled.
"""
def __init__(self, reset=0x7dbd):
self.enable = Signal(reset=1)
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
# # #
self.submodules.unit = unit = ScramblerUnit(reset=reset)
self.comb += unit.ce.eq(sink.valid & sink.ready)
self.comb += sink.connect(source)
for i in range(4):
self.comb += [
If(~self.enable | sink.ctrl[i], # K codes shall not be scrambled.
source.data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)])
).Else(
source.data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)] ^ unit.value[8*i:8*(i+1)])
)
]
# Descrambler (Scrambler + Auto-Synchronization) (Appendix B) --------------------------------------
class Descrambler(Module):
"""Descrambler
This module descrambles the RX data/ctrl stream. K codes shall not be scrambled. The descrambler
automatically synchronizes itself to the incoming stream and resets the scrambler unit when COM
characters are seen.
"""
def __init__(self, reset=0xffff):
self.enable = Signal(reset=1)
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
# # #
scrambler = Scrambler(reset=reset)
self.submodules += scrambler
self.comb += scrambler.enable.eq(self.enable)
# Synchronize on COM
for i in range(4):
self.comb += [
If(sink.valid &
sink.ready &
(sink.data[8*i:8*(i+1)] == COM.value) &
sink.ctrl[i],
scrambler.unit.reset.eq(1)
)
]
# Descramble data
self.comb += [
sink.connect(scrambler.sink),
scrambler.source.connect(source)
]
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((4422, 4466), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (4437, 4466), False, 'from litex.soc.interconnect import stream\n'), ((4498, 4542), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (4513, 4542), False, 'from litex.soc.interconnect import stream\n'), ((5576, 5620), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (5591, 5620), False, 'from litex.soc.interconnect import stream\n'), ((5652, 5696), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (5667, 5696), False, 'from litex.soc.interconnect import stream\n')] |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2017-2018 <NAME> <<EMAIL>>
# License: BSD
import os
import subprocess
from litex.build.generic_programmer import GenericProgrammer
from litex.build import tools
class LatticeProgrammer(GenericProgrammer):
needs_bitreverse = False
def __init__(self, xcf_template):
self.xcf_template = xcf_template
def load_bitstream(self, bitstream_file):
xcf_file = bitstream_file.replace(".bit", ".xcf")
xcf_content = self.xcf_template.format(bitstream_file=bitstream_file)
tools.write_to_file(xcf_file, xcf_content)
subprocess.call(["pgrcmd", "-infile", xcf_file])
class IceStormProgrammer(GenericProgrammer):
needs_bitreverse = False
def flash(self, address, bitstream_file):
subprocess.call(["iceprog", "-o", str(address), bitstream_file])
def load_bitstream(self, bitstream_file):
subprocess.call(["iceprog", "-S", bitstream_file])
class IceBurnProgrammer(GenericProgrammer):
def __init__(self, iceburn_path):
GenericProgrammer.__init__(self)
self.iceburn = iceburn_path
needs_bitreverse = False
def load_bitstream(self, bitstream_file):
subprocess.call([self.iceburn, "-evw", bitstream_file])
class TinyFpgaBProgrammer(GenericProgrammer):
needs_bitreverse = False
# The default flash address you probably want is 0x30000; the image at
# address 0 is for the bootloader.
def flash(self, address, bitstream_file):
subprocess.call(["tinyfpgab", "-a", str(address), "-p",
bitstream_file])
# Force user image to boot if a user reset tinyfpga, the bootloader
# is active, and the user image need not be reprogrammed.
def boot(self):
subprocess.call(["tinyfpgab", "-b"])
# Different bootloader protocol requires different application. In the basic
# case, command-line arguments are the same. Note that this programmer can
# also be used with TinyFPGA B2 if you have updated its bootloader.
class TinyProgProgrammer(GenericProgrammer):
needs_bitreverse = False
# You probably want to pass address="None" for this programmer
# unless you know what you're doing.
def flash(self, address, bitstream_file, user_data=False):
if address is None:
if not user_data:
# tinyprog looks at spi flash metadata to figure out where to
# program your bitstream.
subprocess.call(["tinyprog", "-p", bitstream_file])
else:
# Ditto with user data.
subprocess.call(["tinyprog", "-u", bitstream_file])
else:
# Provide override so user can program wherever they wish.
subprocess.call(["tinyprog", "-a", str(address), "-p",
bitstream_file])
# Force user image to boot if a user reset tinyfpga, the bootloader
# is active, and the user image need not be reprogrammed.
def boot(self):
subprocess.call(["tinyprog", "-b"])
class MyStormProgrammer(GenericProgrammer):
def __init__(self, serial_port):
self.serial_port = serial_port
def load_bitstream(self, bitstream_file):
import serial
with serial.Serial(self.serial_port) as port:
with open(bitstream_file, "rb") as f:
port.write(f.read())
| [
"litex.build.generic_programmer.GenericProgrammer.__init__",
"litex.build.tools.write_to_file"
] | [((594, 636), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['xcf_file', 'xcf_content'], {}), '(xcf_file, xcf_content)\n', (613, 636), False, 'from litex.build import tools\n'), ((645, 693), 'subprocess.call', 'subprocess.call', (["['pgrcmd', '-infile', xcf_file]"], {}), "(['pgrcmd', '-infile', xcf_file])\n", (660, 693), False, 'import subprocess\n'), ((945, 995), 'subprocess.call', 'subprocess.call', (["['iceprog', '-S', bitstream_file]"], {}), "(['iceprog', '-S', bitstream_file])\n", (960, 995), False, 'import subprocess\n'), ((1088, 1120), 'litex.build.generic_programmer.GenericProgrammer.__init__', 'GenericProgrammer.__init__', (['self'], {}), '(self)\n', (1114, 1120), False, 'from litex.build.generic_programmer import GenericProgrammer\n'), ((1242, 1297), 'subprocess.call', 'subprocess.call', (["[self.iceburn, '-evw', bitstream_file]"], {}), "([self.iceburn, '-evw', bitstream_file])\n", (1257, 1297), False, 'import subprocess\n'), ((1804, 1840), 'subprocess.call', 'subprocess.call', (["['tinyfpgab', '-b']"], {}), "(['tinyfpgab', '-b'])\n", (1819, 1840), False, 'import subprocess\n'), ((3041, 3076), 'subprocess.call', 'subprocess.call', (["['tinyprog', '-b']"], {}), "(['tinyprog', '-b'])\n", (3056, 3076), False, 'import subprocess\n'), ((3281, 3312), 'serial.Serial', 'serial.Serial', (['self.serial_port'], {}), '(self.serial_port)\n', (3294, 3312), False, 'import serial\n'), ((2503, 2554), 'subprocess.call', 'subprocess.call', (["['tinyprog', '-p', bitstream_file]"], {}), "(['tinyprog', '-p', bitstream_file])\n", (2518, 2554), False, 'import subprocess\n'), ((2629, 2680), 'subprocess.call', 'subprocess.call', (["['tinyprog', '-u', bitstream_file]"], {}), "(['tinyprog', '-u', bitstream_file])\n", (2644, 2680), False, 'import subprocess\n')] |
#!/usr/bin/env python3
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# Trigger a reset of the SoC
#wb.regs.ctrl_reset.write(1)
# Dump all CSR registers of the SoC
for name, reg in wb.regs.__dict__.items():
print("0x{:08x} : 0x{:08x} {}".format(reg.addr, reg.read(), name))
wb.close()
| [
"litex.RemoteClient"
] | [((61, 75), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (73, 75), False, 'from litex import RemoteClient\n')] |
#!/usr/bin/env python3
import argparse
import os
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from liteeth.phy.model import LiteEthPHYModel
from ring import *
# IOs ----------------------------------------------------------------------------------------------
_io = [
("sys_clk", 0, Pins(1)),
("sys_rst", 0, Pins(1)),
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
("eth_clocks", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
),
("eth", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
# This is the ring data out. Our C++ model will be
# connected to this pin
("data_out", 0, Pins(1)),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(SimPlatform):
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = Platform()
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC Simulation",
ident_version = True,
uart_name = "sim",
integrated_rom_size = 0x10000,
**kwargs
)
self.submodules.crg = CRG(platform.request("sys_clk"))
led = RingControl(platform.request("data_out"), mode.DOUBLE, 12, sys_clk_freq, sim=True)
self.submodules.ledring = led
self.add_csr("ledring")
#-------------------------------------------------------------------------------
# Using the etherbone bridge, we can run litescope on the simulated platform
#-------------------------------------------------------------------------------
#self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
#self.add_etherbone(phy=self.ethphy, ip_address="192.168.1.98")
#analyzer_signals = [
# led.ring.do,
# led.ring.fsm,
#]
#from litescope import LiteScopeAnalyzer
#self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
# depth = 1000,
# clock_domain = "sys",
# csr_csv = "analyzer.csv")
# Build --------------------------------------------------------------------------------------------
def main():
sim_config = SimConfig()
sys_clk_freq = int(20e6)
# Needed to create the simulated clock
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Needed to create the simulated serial port + terminal
sim_config.add_module("serial2console", "serial")
# This is our LedRing model
sim_config.add_module("ledring", "data_out", args={"freq" : sys_clk_freq})
# In case we want Ethernet
#sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
soc = BaseSoC(sys_clk_freq)
builder = Builder(soc, csr_csv="csr.csv")
builder.build(
extra_mods = ["ledring"],
extra_mods_path = os.path.abspath(os.getcwd()) + "/modules",
sim_config=sim_config
)
if __name__ == "__main__":
main()
| [
"litex.build.sim.config.SimConfig",
"litex.build.sim.SimPlatform.__init__"
] | [((3115, 3126), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {}), '()\n', (3124, 3126), False, 'from litex.build.sim.config import SimConfig\n'), ((1479, 1517), 'litex.build.sim.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""SIM"""', '_io'], {}), "(self, 'SIM', _io)\n", (1499, 1517), False, 'from litex.build.sim import SimPlatform\n'), ((3794, 3805), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (3803, 3805), False, 'import os\n')] |
#!/usr/bin/env python3
import sys
import os
cmd, prog = sys.argv[:2]
if len(sys.argv) == 3:
fname = sys.argv[2]
else:
p = os.environ['PLATFORM']
t = os.environ['TARGET']
c = os.environ['CPU']
fname = "build/{p}_{t}_{c}/gateware/top.bit".format(
p=p, t=t, c=c)
if prog == 'ise':
from litex.build.xilinx import iMPACT
prog = iMPACT()
elif prog == 'vivado':
from litex.build.xilinx import VivadoProgrammer
prog = VivadoProgrammer()
else:
raise SystemError('Unknown programmer {}'.format(prog))
if not os.path.exists(fname):
raise SystemError('File {} not found'.format(fname))
if not fname.endswith('.bit'):
raise SystemError('Use the .bit file')
prog.load_bitstream(fname)
| [
"litex.build.xilinx.iMPACT",
"litex.build.xilinx.VivadoProgrammer"
] | [((363, 371), 'litex.build.xilinx.iMPACT', 'iMPACT', ([], {}), '()\n', (369, 371), False, 'from litex.build.xilinx import iMPACT\n'), ((551, 572), 'os.path.exists', 'os.path.exists', (['fname'], {}), '(fname)\n', (565, 572), False, 'import os\n'), ((458, 476), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (474, 476), False, 'from litex.build.xilinx import VivadoProgrammer\n')] |
import os
from migen import *
from litex.soc.interconnect import csr_bus, wishbone
class MCS51(Module):
"""
8051 CPU core. This is a wrapper around Verilog turbo8051 model.
"""
def __init__(self, platform, ea=Constant(0)):
self.platform = platform
self.interrupt = Signal(2)
self.ibus = i = csr_bus.Interface(data_width=32, address_width=16, alignment=8)
self.dbus = d = wishbone.Interface(data_width=8, adr_width=16)
# connect to the verilog 8051 core
cpu_connections = dict(
# clock and reset
i_wb_rst_i = ResetSignal(),
i_wb_clk_i = ClockSignal(),
# 2 interrupt pins
i_int0_i = self.interrupt[0],
i_int1_i = self.interrupt[1],
# external access, EA=1 means that internal ROM is also used
i_ea_in = ea,
# ROM interface, we do not use wishbone so some signals are not used
o_wbi_adr_o = i.adr,
i_wbi_dat_i = i.dat_r, # slave to master
i_wbi_ack_i = Constant(1), # data is always valid
# i_wbi_err_i = Signal(),
# o_wbi_stb_o = Signal(),
# o_wbi_cyc_o = Signal(),
# external data RAM interface
o_wbd_adr_o = d.adr,
o_wbd_dat_o = d.dat_w,
i_wbd_dat_i = d.dat_r,
o_wbd_we_o = d.we,
i_wbd_ack_i = d.ack,
i_wbd_err_i = d.err,
o_wbd_stb_o = d.stb,
o_wbd_cyc_o = d.cyc,
)
self.specials += Instance("oc8051_top", **cpu_connections)
vdir = os.path.join(
os.path.abspath(os.path.dirname(__file__)), "verilog")
platform.add_sources(os.path.join(vdir, "rtl", "8051", "oc8051_top.v"))
platform.add_verilog_include_path(os.path.join(vdir, "rtl", "8051"))
platform.add_verilog_include_path(os.path.join(vdir, "rtl", "defs"))
| [
"litex.soc.interconnect.csr_bus.Interface",
"litex.soc.interconnect.wishbone.Interface"
] | [((336, 399), 'litex.soc.interconnect.csr_bus.Interface', 'csr_bus.Interface', ([], {'data_width': '(32)', 'address_width': '(16)', 'alignment': '(8)'}), '(data_width=32, address_width=16, alignment=8)\n', (353, 399), False, 'from litex.soc.interconnect import csr_bus, wishbone\n'), ((424, 470), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(8)', 'adr_width': '(16)'}), '(data_width=8, adr_width=16)\n', (442, 470), False, 'from litex.soc.interconnect import csr_bus, wishbone\n'), ((1743, 1792), 'os.path.join', 'os.path.join', (['vdir', '"""rtl"""', '"""8051"""', '"""oc8051_top.v"""'], {}), "(vdir, 'rtl', '8051', 'oc8051_top.v')\n", (1755, 1792), False, 'import os\n'), ((1836, 1869), 'os.path.join', 'os.path.join', (['vdir', '"""rtl"""', '"""8051"""'], {}), "(vdir, 'rtl', '8051')\n", (1848, 1869), False, 'import os\n'), ((1913, 1946), 'os.path.join', 'os.path.join', (['vdir', '"""rtl"""', '"""defs"""'], {}), "(vdir, 'rtl', 'defs')\n", (1925, 1946), False, 'import os\n'), ((1675, 1700), 'os.path.dirname', 'os.path.dirname', (['__file__'], {}), '(__file__)\n', (1690, 1700), False, 'import os\n')] |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2017 <NAME> <<EMAIL>>
# License: BSD
from migen.fhdl.structure import Signal
from migen.genlib.record import Record
from litex.build.generic_platform import GenericPlatform
from litex.build.sim import common, verilator
class SimPlatform(GenericPlatform):
def __init__(self, *args, toolchain="verilator", **kwargs):
GenericPlatform.__init__(self, *args, **kwargs)
self.sim_requested = []
if toolchain == "verilator":
self.toolchain = verilator.SimVerilatorToolchain()
else:
raise ValueError("Unknown toolchain")
def request(self, name, number=None):
index = ""
if number is not None:
index = str(number)
obj = GenericPlatform.request(self, name, number=number)
siglist = []
if isinstance(obj, Signal):
siglist.append((name, obj.nbits, name))
elif isinstance(obj, Record):
for subsignal, dummy in obj.iter_flat():
subfname = subsignal.backtrace[-1][0]
prefix = "{}{}_".format(name, index)
subname = subfname.split(prefix)[1]
siglist.append((subname, subsignal.nbits, subfname))
self.sim_requested.append((name, index, siglist))
return obj
def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.sim_special_overrides)
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs)
| [
"litex.build.generic_platform.GenericPlatform.__init__",
"litex.build.generic_platform.GenericPlatform.request",
"litex.build.sim.verilator.SimVerilatorToolchain",
"litex.build.generic_platform.GenericPlatform.get_verilog"
] | [((416, 463), 'litex.build.generic_platform.GenericPlatform.__init__', 'GenericPlatform.__init__', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (440, 463), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((799, 849), 'litex.build.generic_platform.GenericPlatform.request', 'GenericPlatform.request', (['self', 'name'], {'number': 'number'}), '(self, name, number=number)\n', (822, 849), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((1526, 1598), 'litex.build.generic_platform.GenericPlatform.get_verilog', 'GenericPlatform.get_verilog', (['self', '*args'], {'special_overrides': 'so'}), '(self, *args, special_overrides=so, **kwargs)\n', (1553, 1598), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((562, 595), 'litex.build.sim.verilator.SimVerilatorToolchain', 'verilator.SimVerilatorToolchain', ([], {}), '()\n', (593, 595), False, 'from litex.build.sim import common, verilator\n')] |
#!/usr/bin/env python3
import sys
import os
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.boards.platforms import arty
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores import dna, xadc
from litedram.modules import MT41J128M16
from litedram.phy import a7ddrphy
from litedram.core import ControllerSettings
from gateware.dma import DMAWriter, DMAReader
def csr_map_update(csr_map, csr_peripherals):
csr_map.update(dict((n, v)
for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1)))
def period_ns(freq):
return 1e9/freq
class CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk50 = ClockDomain()
clk100 = platform.request("clk100")
rst = ~platform.request("cpu_reset")
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys4x = Signal()
pll_sys4x_dqs = Signal()
pll_clk200 = Signal()
pll_clk50 = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1600 MHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=10.0,
p_CLKFBOUT_MULT=16, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk100, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 100 MHz
p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
# 400 MHz
p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=pll_sys4x,
# 400 MHz dqs
p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0,
o_CLKOUT2=pll_sys4x_dqs,
# 200 MHz
p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
o_CLKOUT3=pll_clk200,
# 50MHz
p_CLKOUT4_DIVIDE=32, p_CLKOUT4_PHASE=0.0,
o_CLKOUT4=pll_clk50
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
Instance("BUFG", i_I=pll_clk50, o_O=self.cd_clk50.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk50, ~pll_locked | rst),
]
reset_counter = Signal(4, reset=15)
ic_reset = Signal(reset=1)
self.sync.clk200 += \
If(reset_counter != 0,
reset_counter.eq(reset_counter - 1)
).Else(
ic_reset.eq(0)
)
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
class BaseSoC(SoCSDRAM):
csr_peripherals = {
"ddrphy",
"dna",
"xadc",
}
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
l2_size=32,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="Arty DMA Test SoC",
ident_version=True,
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
class DMATestSoC(BaseSoC):
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
# parameters
slot_length = 1280*720*32
slot_offset = 0x00000000
slot0_base = slot_offset + 0*slot_length
slot1_base = slot_offset + 1*slot_length
# create fake pixel clock
self.clock_domains.cd_pix = ClockDomain() # Remove once hdmi in integrated
self.comb += [
self.cd_pix.clk.eq(ClockSignal()),
self.cd_pix.rst.eq(ResetSignal())
]
# dram dmas
dma_writer = DMAWriter(self.sdram.crossbar.get_port(mode="write", dw=32, cd="pix"))
dma_writer = ClockDomainsRenamer("pix")(dma_writer)
dma_reader = DMAReader(self.sdram.crossbar.get_port(mode="read", dw=32, cd="pix"))
dma_reader = ClockDomainsRenamer("pix")(dma_reader)
self.submodules += dma_writer, dma_reader
# quick "user manual" :)
# user_sw0 : dma writer enable
# user_sw1 : dma writer valid
# user sw2 : dma reader enable
# user sw3 : dma reader ready
# user_btn0: dma writer start
# user_btn1: dma_reader start
# user_btn2: error injection
# user_led0: dma_writer idle
# user_led1: dma_writer ready
# user_led2: dma_reader idle
# user_led3: dma_reader valid
# test
idata0 = Signal(10)
idata1 = Signal(10)
idata2 = Signal(10)
self.sync.pix += [
If(~platform.request("user_btn", 2),
idata0.eq(idata0 + 1),
idata1.eq(idata1 + 2),
idata2.eq(idata2 + 4)
).Else(
idata0.eq(0),
idata1.eq(0),
idata2.eq(0)
)
]
# dma
self.comb += [
# control
dma_writer.enable.eq(platform.request("user_sw", 0)),
dma_writer.slot0_base.eq(slot0_base),
dma_writer.slot1_base.eq(slot1_base),
dma_writer.length.eq(slot_length),
# stream
dma_writer.start.eq(platform.request("user_btn", 0)),
platform.request("user_led", 0).eq(dma_writer.idle),
dma_writer.sink.valid.eq(platform.request("user_sw", 1)),
platform.request("user_led", 1).eq(dma_writer.sink.ready),
dma_writer.sink.data[0:10].eq(idata0),
dma_writer.sink.data[10:20].eq(idata1),
dma_writer.sink.data[20:30].eq(idata2),
]
# test
odata0 = Signal(10)
odata1 = Signal(10)
odata2 = Signal(10)
# hdmi out dma
self.comb += [
# control
dma_reader.enable.eq(platform.request("user_sw", 2)),
dma_reader.slot0_base.eq(slot0_base),
dma_reader.slot1_base.eq(slot1_base),
dma_reader.length.eq(slot_length),
# stream
dma_reader.start.eq(platform.request("user_btn", 1)),
platform.request("user_led", 2).eq(dma_reader.idle),
platform.request("user_led", 3).eq(dma_reader.source.valid),
dma_reader.source.ready.eq(platform.request("user_sw", 3)),
odata0.eq(dma_reader.source.data[0:10]),
odata1.eq(dma_reader.source.data[10:20]),
odata2.eq(dma_reader.source.data[20:30]),
]
# check
odata0_d = Signal(10)
odata1_d = Signal(10)
odata2_d = Signal(10)
errors = platform.request("rgb_leds")
self.sync.pix += [
errors.r.eq(0b000),
errors.g.eq(0b111),
odata0_d.eq(odata0),
odata1_d.eq(odata1),
odata2_d.eq(odata2),
If(odata0 != (odata0_d + 1),
errors.r[0].eq(1),
errors.g[0].eq(0)),
If(odata1 != (odata1_d + 2),
errors.r[1].eq(1),
errors.g[1].eq(0)),
If(odata2 != (odata2_d + 4),
errors.r[2].eq(1),
errors.g[2].eq(0)),
]
def do_exit(self, vns):
pass
def main():
platform = arty.Platform()
soc = DMATestSoC(platform)
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
vns = builder.build()
soc.do_exit(vns)
if __name__ == "__main__":
main()
| [
"litex.gen.genlib.resetsync.AsyncResetSynchronizer",
"litex.soc.cores.xadc.XADC",
"litex.soc.cores.dna.DNA",
"litex.boards.platforms.arty.Platform"
] | [((9017, 9032), 'litex.boards.platforms.arty.Platform', 'arty.Platform', ([], {}), '()\n', (9030, 9032), False, 'from litex.boards.platforms import arty\n'), ((3977, 3986), 'litex.soc.cores.dna.DNA', 'dna.DNA', ([], {}), '()\n', (3984, 3986), False, 'from litex.soc.cores import dna, xadc\n'), ((4018, 4029), 'litex.soc.cores.xadc.XADC', 'xadc.XADC', ([], {}), '()\n', (4027, 4029), False, 'from litex.soc.cores import dna, xadc\n'), ((4277, 4310), 'litedram.modules.MT41J128M16', 'MT41J128M16', (['self.clk_freq', '"""1:4"""'], {}), "(self.clk_freq, '1:4')\n", (4288, 4310), False, 'from litedram.modules import MT41J128M16\n'), ((2811, 2865), 'litex.gen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~pll_locked | rst)'], {}), '(self.cd_sys, ~pll_locked | rst)\n', (2833, 2865), False, 'from litex.gen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2879, 2936), 'litex.gen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_clk200', '(~pll_locked | rst)'], {}), '(self.cd_clk200, ~pll_locked | rst)\n', (2901, 2936), False, 'from litex.gen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2950, 3006), 'litex.gen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_clk50', '(~pll_locked | rst)'], {}), '(self.cd_clk50, ~pll_locked | rst)\n', (2972, 3006), False, 'from litex.gen.genlib.resetsync import AsyncResetSynchronizer\n'), ((4621, 4699), 'litedram.core.ControllerSettings', 'ControllerSettings', ([], {'with_bandwidth': '(True)', 'cmd_buffer_depth': '(8)', 'with_refresh': '(True)'}), '(with_bandwidth=True, cmd_buffer_depth=8, with_refresh=True)\n', (4639, 4699), False, 'from litedram.core import ControllerSettings\n')] |
#!/usr/bin/env python3
from migen import *
from migen.genlib.cdc import MultiReg
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from tick import *
from display import *
from bcd import *
from core import *
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
("user_btn_r", 0, Pins("M17"), IOStandard("LVCMOS33")),
("user_btn_l", 0, Pins("P17"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
("display_cs_n", 0, Pins("J17"), IOStandard("LVCMOS33")),
("display_abcdefg", 0, Pins("T10 R10 K16 K13 P15 T11 L18 H15"), IOStandard("LVCMOS33")),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-csg324-1", _io, toolchain="vivado")
# Design -------------------------------------------------------------------------------------------
# User button detection
class UserButtonPress(Module):
def __init__(self, user_btn):
self.rising = Signal()
# # #
_user_btn = Signal()
_user_btn_d = Signal()
# resynchronize user_btn
self.specials += MultiReg(user_btn, _user_btn)
# detect rising edge
self.sync += [
_user_btn_d.eq(user_btn),
self.rising.eq(_user_btn & ~_user_btn_d)
]
# Create our platform (fpga interface)
platform = Platform()
# Create our main module (fpga description)
class Clock(Module):
sys_clk_freq = int(100e6)
def __init__(self):
# -- TO BE COMPLETED --
# Tick generation : timebase
# SevenSegmentDisplay
# Core : counts ss/mm/hh
# set mm/hh
# Binary Coded Decimal: convert ss/mm/hh to decimal values
# use the generated verilog file
# combinatorial assignement
self.comb += [
# Connect tick to core (core timebase)
# Set minutes/hours
# Convert core seconds to bcd and connect
# to display
# Convert core minutes to bcd and connect
# to display
# Convert core hours to bcd and connect
# to display
# Connect display to pads
]
# -- TO BE COMPLETED --
module = Clock()
# Build --------------------------------------------------------------------------------------------
platform.build(module)
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((1114, 1189), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (1137, 1189), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1548, 1577), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['user_btn', '_user_btn'], {}), '(user_btn, _user_btn)\n', (1556, 1577), False, 'from migen.genlib.cdc import MultiReg\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("G27"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("W12"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("AJ22"), IOStandard("LVCMOS33")), # D3
("user_led", 1, Pins("AJ21"), IOStandard("LVCMOS33")), # D4
("user_led", 2, Pins("AK21"), IOStandard("LVCMOS33")), # D5
("user_led", 3, Pins("AK20"), IOStandard("LVCMOS33")), # D6
("user_led", 4, Pins("AK19"), IOStandard("LVCMOS33")), # D7
("user_led", 5, Pins("AJ19"), IOStandard("LVCMOS33")), # D8
("user_led", 6, Pins("AK18"), IOStandard("LVCMOS33")), # D9
("user_led", 7, Pins("AJ18"), IOStandard("LVCMOS33")), # D10
# Buttons
("user_btn_k3", 0, Pins("AK15"), IOStandard("LVCMOS33")),
("user_btn_k2", 0, Pins("AK16"), IOStandard("LVCMOS33")),
# Serial (CH340)
("serial", 0,
Subsignal("tx", Pins("AK23")),
Subsignal("rx", Pins("AJ23")),
IOStandard("LVCMOS33")
),
# SPIFlash (Micron N25Q256A (32MB))
("spiflash", 0,
Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("R30"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("T30"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("R28"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("T28"), IOStandard("LVCMOS33"))
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("V26"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("R30 T30 R28 T28"), IOStandard("LVCMOS33"))
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# main board connector, pins as marked
( "main", {
# usb- 1 2 usb+ not used U3 usb3320 don't use
# GND 3 4 GND
# QSPI_CS 5 6 QSPI_D1
# QSPI_D0 7 8 QSPI_CLK
9: "B29",
# 10: "Program_B" key3 reset button
11: "A28",
12: "B27",
13: "A27",
14: "A26",
15: "B25",
16: "A25",
17: "B24",
18: "B23",
19: "A23",
20: "B22",
21: "A22",
22: "A21",
23: "B20",
24: "A20",
# 25,26,27,28: GND
# 29,30,31,32: V12
})
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k420tl-ffg901", _io, toolchain=toolchain)
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a420t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2749, 2824), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k420tl-ffg901"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7k420tl-ffg901', _io, toolchain=toolchain)\n", (2772, 2824), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((2874, 2933), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a420t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a420t.bit')\n", (2881, 2933), False, 'from litex.build.openocd import OpenOCD\n'), ((2980, 3022), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3006, 3022), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [ # Documented by https://github.com/360nosc0pe project.
# Leds
("user_led", 0, Pins("G16"), IOStandard("LVCMOS33")),
# Beeper
("beeper", 0, Pins("W17"), IOStandard("LVCMOS33")),
# Led Frontpanel
("led_frontpanel", 0,
Subsignal("rclk", Pins("N22")),
Subsignal("clk", Pins("R20")),
Subsignal("mosi", Pins("P22")),
Subsignal("oe", Pins("R21")),
IOStandard("LVCMOS33"),
),
# Button Frontpanel
("btn_frontpanel", 0,
Subsignal("clk", Pins("H18")),
Subsignal("clr", Pins("G19")),
Subsignal("miso", Pins("G17")),
IOStandard("LVCMOS33")
),
# LCD
("lcd", 0,
Subsignal("clk", Pins("D20")),
Subsignal("vsync", Pins("A21")),
Subsignal("hsync", Pins("A22")),
Subsignal("r", Pins("G22 F22 F21 F19 F18 F17")),
Subsignal("g", Pins("F16 E21 E20 E19 E18 E16")),
Subsignal("b", Pins("D22 D21 C22 C20 B22 B21")),
IOStandard("LVCMOS33"),
),
# MII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("B19")),
Subsignal("rx", Pins("C17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("R6")),
Subsignal("mdio", Pins("E15")),
Subsignal("mdc", Pins("D15")),
Subsignal("rx_dv", Pins("A16")),
Subsignal("rx_er", Pins("C15")),
Subsignal("rx_data", Pins("D16 A17 B17 D17")),
Subsignal("tx_en", Pins("A18")),
Subsignal("tx_data", Pins("C18 A19 C19 B20")),
Subsignal("col", Pins("B16")),
Subsignal("crs", Pins("B15")),
IOStandard("LVCMOS33"),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"J21 K18 J18 R16 P16 T18 R18 T19",
"R19 P18 P17 P15 N15"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("K21 J20 J22"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("L21"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("L22"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("K19"), IOStandard("SSTL135")),
#Subsignal("cs_n", Pins(""), IOStandard("SSTL135")), # Pulled low.
#Subsignal("dm", Pins(""), IOStandard("SSTL135")), # Pulled low.
Subsignal("dq", Pins(
" T21 U21 T22 U22 W20 W21 U20 V20",
"AA22 AB22 AA21 AB21 AB19 AB20 Y19 AA19",
" W16 Y16 U17 V17 AA17 AB17 AA16 AB16",
" V14 V13 W13 Y14 AA14 Y13 AA13 AB14"),
IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("V22 Y20 U15 W15"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("W22 Y21 U16 Y15"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("T16"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("T17"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("M21"), IOStandard("SSTL135")),
Subsignal("odt", Pins("M22"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("V18"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg484-1", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/25e6)
self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/25e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3901, 3992), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020-clg484-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7z020-clg484-1', _io, _connectors,\n toolchain='vivado')\n", (3924, 3992), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((4039, 4057), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (4055, 4057), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((4104, 4146), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4130, 4146), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# https://www.crowdsupply.com/fairwaves/xtrx
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk/Rst.
("clk60", 0, Pins("C16"), IOStandard("LVCMOS25")),
# Leds.
("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")),
# PCIe.
("pcie_x1", 0,
Subsignal("rst_n", Pins("T3"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("B8")),
Subsignal("clk_n", Pins("A8")),
Subsignal("rx_p", Pins("B10")),
Subsignal("rx_n", Pins("A10")),
Subsignal("tx_p", Pins("B6")),
Subsignal("tx_n", Pins("A6")),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk60"
default_clk_period = 1e9/60e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain="vivado")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk60", loose=True), 1e9/60e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((1151, 1224), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50tcpg236-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a50tcpg236-2', _io, toolchain='vivado')\n", (1174, 1224), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1757, 1814), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft232.cfg"""', '"""bscan_spi_xc7a50t.bit"""'], {}), "('openocd_xc7_ft232.cfg', 'bscan_spi_xc7a50t.bit')\n", (1764, 1814), False, 'from litex.build.openocd import OpenOCD\n'), ((1861, 1903), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1887, 1903), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0, Pins("K17"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M14"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("M15"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("G14"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D18"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("Y11")),
Subsignal("g", Pins("T5")),
Subsignal("b", Pins("Y12")),
IOStandard("LVCMOS33")
),
("rgb_led", 1,
Subsignal("r", Pins("V16")),
Subsignal("g", Pins("F17")),
Subsignal("b", Pins("M17")),
IOStandard("LVCMOS33")
),
# Switches
("user_sw", 0, Pins("G15"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("P15"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("W13"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("T16"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("R18"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("P16"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("V16"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("Y16"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("T17")),
Subsignal("rx", Pins("Y17")),
IOStandard("LVCMOS33")
),
("usb_uart", 0,
Subsignal("tx", Pins("H15")),
Subsignal("rx", Pins("J15")),
IOStandard("LVCMOS33")
),
]
_ps7_io = [
# PS7
("ps7_clk", 0, Pins(1)),
("ps7_porb", 0, Pins(1)),
("ps7_srstb", 0, Pins(1)),
("ps7_mio", 0, Pins(54)),
("ps7_ddram", 0,
Subsignal("addr", Pins(15)),
Subsignal("ba", Pins(3)),
Subsignal("cas_n", Pins(1)),
Subsignal("ck_n", Pins(1)),
Subsignal("ck_p", Pins(1)),
Subsignal("cke", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("dm", Pins(4)),
Subsignal("dq", Pins(32)),
Subsignal("dqs_n", Pins(4)),
Subsignal("dqs_p", Pins(4)),
Subsignal("odt", Pins(1)),
Subsignal("ras_n", Pins(1)),
Subsignal("reset_n", Pins(1)),
Subsignal("we_n", Pins(1)),
Subsignal("vrn", Pins(1)),
Subsignal("vrp", Pins(1)),
),
]
_usb_uart_pmod_io = [
# USB-UART PMOD on JB:
# - https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/
("usb_uart", 0,
Subsignal("tx", Pins("pmodb:1")),
Subsignal("rx", Pins("pmodb:2")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("pmoda", "N15 L14 K16 K14 N16 L15 J16 J14"), # XADC
("pmodb", "T20 U20 V20 W20 Y18 Y19 W18 W19"),
("pmodc", "V15 W15 T11 T10 W14 Y14 T12 U12"),
("pmodd", "T14 T15 P14 R14 U14 U15 V17 V18"),
("pmode", "V12 W16 J15 H15 V13 U17 T17 Y17"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain="vivado")
self.add_extension(_ps7_io)
#self.add_extension(_usb_uart_pmod_io)
def create_programmer(self):
return VivadoProgrammer(flash_part="mt25ql128-spi-x1_x2_x4")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3503, 3594), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020-clg400-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7z020-clg400-1', _io, _connectors,\n toolchain='vivado')\n", (3526, 3594), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((3723, 3776), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""mt25ql128-spi-x1_x2_x4"""'}), "(flash_part='mt25ql128-spi-x1_x2_x4')\n", (3739, 3776), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((3823, 3865), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3849, 3865), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
("clk100", 0, Pins("V10"), IOStandard("LVCMOS33")),
("clk12", 0, Pins("D9"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("B8"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("rx", Pins("A8"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST"))),
("spiflash", 0,
Subsignal("cs_n", Pins("V3")),
Subsignal("clk", Pins("R15")),
Subsignal("mosi", Pins("T13")),
Subsignal("miso", Pins("R13"), Misc("PULLUP")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("ddram_clock", 0,
Subsignal("p", Pins("G3")),
Subsignal("n", Pins("G1")),
IOStandard("MOBILE_DDR")),
("ddram", 0,
Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
Subsignal("ba", Pins("F2 F1")),
Subsignal("cke", Pins("H7")),
Subsignal("ras_n", Pins("L5")),
Subsignal("cas_n", Pins("K5")),
Subsignal("we_n", Pins("E3")),
Subsignal(
"dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")
),
Subsignal("dqs", Pins("L4 P2")),
Subsignal("dm", Pins("K3 K4")),
IOStandard("MOBILE_DDR")),
# Small DIP switches
# DP1 (user_sw:0) -> DP8 (user_sw:7)
("user_sw", 0, Pins("F17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 1, Pins("F18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 2, Pins("E16"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 3, Pins("E18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 4, Pins("D18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 5, Pins("D17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 6, Pins("C18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_sw", 7, Pins("C17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
# Despite being marked as "sw" these are actually buttons which need
# debouncing.
# sw1 (user_btn:0) through sw6 (user_btn:5)
("user_btn", 0, Pins("M18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_btn", 1, Pins("L18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_btn", 2, Pins("M16"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_btn", 3, Pins("L17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
("user_btn", 4, Pins("K17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
# Use SW6 as the reset button for now.
("user_btn", 5, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLUP")),
# LEDs 1 through 8
("user_led", 0, Pins("P15"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 1, Pins("P16"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 2, Pins("N15"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 3, Pins("N16"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 4, Pins("U17"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 5, Pins("U18"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 6, Pins("T17"), IOStandard("LVCMOS33"), Drive(8)),
("user_led", 7, Pins("T18"), IOStandard("LVCMOS33"), Drive(8)),
("mmc", 0,
Subsignal("dat", Pins("K14 G18 J13 L13"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("cmd", Pins("G16"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("clk", Pins("L12"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST"))),
("sevenseg", 0,
Subsignal("segment7", Pins("A3"), IOStandard("LVCMOS33")), # A
Subsignal("segment6", Pins("B4"), IOStandard("LVCMOS33")), # B
Subsignal("segment5", Pins("A4"), IOStandard("LVCMOS33")), # C
Subsignal("segment4", Pins("C4"), IOStandard("LVCMOS33")), # D
Subsignal("segment3", Pins("C5"), IOStandard("LVCMOS33")), # E
Subsignal("segment2", Pins("D6"), IOStandard("LVCMOS33")), # F
Subsignal("segment1", Pins("C6"), IOStandard("LVCMOS33")), # G
Subsignal("segment0", Pins("A5"), IOStandard("LVCMOS33")), # Dot
Subsignal("enable0", Pins("B2"), IOStandard("LVCMOS33")), # EN0
Subsignal("enable1", Pins("A2"), IOStandard("LVCMOS33")), # EN1
Subsignal("enable2", Pins("B3"), IOStandard("LVCMOS33"))), # EN2
("audio", 0,
Subsignal("channel1", Pins("B16"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("channel2", Pins("A16"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST"))),
("vga_out", 0,
Subsignal("hsync_n", Pins("B12"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("vsync_n", Pins("A12"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("r", Pins("A9 B9 C9"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("g", Pins("C10 A10 C11"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")),
Subsignal("b", Pins("B11 A11"), IOStandard("LVCMOS33"),
Misc("SLEW=FAST")))
]
_connectors = [
("P6", "T3 R3 V5 U5 V4 T4 V7 U7"),
("P7", "V11 U11 V13 U13 T10 R10 T11 R11"),
("P8", "L16 L15 K16 K15 J18 J16 H18 H17")
]
class Platform(XilinxPlatform):
name = "mimasv2"
default_clk_name = "clk100"
default_clk_period = 10
# The MimasV2 has a XC6SLX9 which bitstream takes up ~2.6Mbit (1484472 bytes)
# 0x80000 offset (4Mbit) gives plenty of space
gateware_size = 0x80000
# M25P16 - component U1
# 16Mb - 75 MHz clock frequency
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
# /* name, erase_cmd, chip_erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
# FLASH_ID("st m25p16", 0xd8, 0xc7, 0x00152020, 0x100, 0x10000, 0x200000),
spiflash_model = "m25p16"
spiflash_read_dummy_bits = 8
spiflash_clock_div = 4
spiflash_total_size = int((16/8)*1024*1024) # 16Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx9-csg324-2", _io, _connectors)
def create_programmer(self):
raise NotImplementedError
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((6125, 6192), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx9-csg324-2"""', '_io', '_connectors'], {}), "(self, 'xc6slx9-csg324-2', _io, _connectors)\n", (6148, 6192), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import mini_4k
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoS7GTPHDMIPHY
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_hdmi = ClockDomain()
# # #
# Clk.
clk100 = platform.request("clk100")
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk100_IBUF]")
platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_s7pll0_clkin]")
# Main PLL.
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6, margin=1e-1) # FIXME: Re-arrange clocking.
pll.create_clkout(self.cd_hdmi, 148.5e6, margin=2e-2) # FIXME: Use a second PLL or move to clkout0 that has fractional support.
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
# IDELAY Ctrl.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# SATA PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.submodules.sata_pll = sata_pll = S7PLL(speedgrade=-1)
self.comb += sata_pll.reset.eq(self.rst)
sata_pll.register_clkin(clk100, 100e6)
sata_pll.create_clkout(self.cd_sata_refclk, 150e6)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCMini):
def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, with_video_terminal=False, with_video_framebuffer=False, **kwargs):
if with_video_terminal or with_video_framebuffer:
sys_clk_freq = int(148.5e6) # FIXME: For now requires sys_clk >= video_clk.
platform = mini_4k.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "jtag_uart"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Blackmagic Decklink Mini 4K",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# IOs
_sata_io = [
# PCIe 2 SATA Custom Adapter (With PCIe Riser / SATA cable mod).
("pcie2sata", 0,
Subsignal("tx_p", Pins("B7")),
Subsignal("tx_n", Pins("A7")),
Subsignal("rx_p", Pins("B11")),
Subsignal("rx_n", Pins("A11")),
),
]
platform.add_extension(_sata_io)
# RefClk, Generate 150MHz from PLL.
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = ClockSignal("sata_refclk"),
pads = platform.request("pcie2sata"),
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Video ------------------------------------------------------------------------------------
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoS7GTPHDMIPHY(platform.request("hdmi_out"),
sys_clk_freq = sys_clk_freq,
clock_domain = "hdmi"
)
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="hdmi")
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-49]") # FIXME: Use GTP refclk.
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC Blackmagic Decklink Mini 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.")
pcieopts = parser.add_mutually_exclusive_group()
pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
parser.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
pcieopts.add_argument("--with-sata", action="store_true", help="Enable SATA support (over PCIe2SATA).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
with_sata = args.with_sata,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
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"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("AC18"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
Subsignal("rx", Pins("Y17"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
),
("sdram_clock", 0, Pins("AH12"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"AK14 AH14 AG15 AE14 AB15 AC14 AD14 AF15",
"AH15 AG13 AG12 AH13 AJ14")),
Subsignal("ba", Pins("AF13 AJ12")),
Subsignal("cs_n", Pins("AG11")),
Subsignal("cke", Pins("AK13")),
Subsignal("ras_n", Pins("AE13")),
Subsignal("cas_n", Pins("AF11")),
Subsignal("we_n", Pins("AA13")),
Subsignal("dq", Pins(
"AK6 AJ7 AK7 AK8 AK9 AG10 AK11 AJ11",
"AH10 AJ10 AJ9 AH9 AH8 AH7 AJ6 AJ5")),
Subsignal("dm", Pins("AB13 AK12")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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#
# This file is part of LiteX-Boards.
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import TinyProgProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("61"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("28 29 31 32"), IOStandard("LVCMOS33")),
("user_btn_n", 0, Pins( "25"), IOStandard("LVCMOS33")),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("71"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("70"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("67"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("68"), IOStandard("LVCMOS33")),
),
# SDR SDRAM
("sdram_clock", 0, Pins("93"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins("118 117 116 101 81 83 90 91 82 84 119 85 87")),
Subsignal("dq", Pins("96 97 98 99 95 80 79 78")),
Subsignal("we_n", Pins("128")),
Subsignal("ras_n", Pins("124")),
Subsignal("cas_n", Pins("125")),
Subsignal("cs_n", Pins("122")),
Subsignal("cke", Pins("88")),
Subsignal("ba", Pins("121 120")),
Subsignal("dm", Pins("94")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# A2-H2, Pins 1-13
# H9-A6, Pins 14-24
# G1-J2, Pins 25-31
("GPIO", "37 39 42 44 38 41 43 45"),
("GPIO1", "47 49 55 60 48 52 56 62"),
("GPIO2", "107 112 114 129 110 113 115 130"),
("GPIO3", "7 9 15 12 4 8 10 11"),
("grove", "73 74 75 76 104 102 106 105")
]
# Default peripherals
serial = [
("serial", 0,
Subsignal("tx", Pins("GPIO:0")),
Subsignal("rx", Pins("GPIO:1")),
IOStandard("LVCMOS33")
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="icestorm"):
LatticePlatform.__init__(self, "ice40-hx8k-tq144:4k", _io, _connectors, toolchain=toolchain)
self.add_extension(serial)
def create_programmer(self):
return TinyProgProgrammer()
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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"litex.build.lattice.LatticePlatform.__init__"
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#!/usr/bin/env python3
import argparse
from migen import *
from migen.genlib.io import CRG
from litex.build.generic_platform import IOStandard, Subsignal, Pins
from litex_boards.platforms import colorlight_5a_75b
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
class BaseSoC(SoCCore):
def __init__(self, revision, cpu):
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = int(25e6)
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type = cpu,
clk_freq = sys_clk_freq,
ident = "LiteX SoC on Colorlight 5A-75B",
ident_version = True,
integrated_rom_size = 0x8000,
integrated_main_ram_size = 0x4000,
uart_name = "serial"
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk25"))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75B")
parser.add_argument("--revision", action="store", default="7.0", help="Colorlight 5A-75B board revision (6.1 / 7.0)")
parser.add_argument("--cpu", action="store", default="vexriscv", help="SoC CPU (vexriscv / picorv32)")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
revision = args.revision,
cpu = args.cpu
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=True)
if __name__ == "__main__": main()
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"litex.build.lattice.trellis.trellis_args",
"litex.build.lattice.trellis.trellis_argdict"
] | [((1111, 1180), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Colorlight 5A-75B"""'}), "(description='LiteX SoC on Colorlight 5A-75B')\n", (1134, 1180), False, 'import argparse\n'), ((1465, 1485), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (1477, 1485), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((462, 498), 'litex_boards.platforms.colorlight_5a_75b.Platform', 'colorlight_5a_75b.Platform', (['revision'], {}), '(revision)\n', (488, 498), False, 'from litex_boards.platforms import colorlight_5a_75b\n'), ((1682, 1703), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (1697, 1703), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
("clk50", 0, Pins("A10"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("T9"), IOStandard("LVCMOS33")), # D1
("user_led", 1, Pins("R9"), IOStandard("LVCMOS33")), # D3
("user_sw", 0, Pins("T8"), IOStandard("LVCMOS33")), # SW2
# ("user_sw", 1, Pins("R7"), IOStandard("LVCMOS33")), # SW3
("cpu_reset", 0, Pins("R7"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("C13"), Misc("SLEW=SLOW")),
Subsignal("rx", Pins("A14"), Misc("PULLUP")),
IOStandard("LVCMOS33")
),
("ddram_clock", 0,
# mcb3_dram_ck, mcb3_dram_ck_n
Subsignal("p", Pins("E2")),
Subsignal("n", Pins("E1")),
IOStandard("DIFF_SSTL15_II"),
),
("ddram", 0,
# mcb3_dram_a
Subsignal("a", Pins(
"K5 K6 D1 L4 G5 H4 H3 D3",
"B2 A2 G6 E3 F3 F6 F5"),
IOStandard("SSTL15_II")),
# mcb3_dram_ba
Subsignal("ba", Pins("C3 C2 B1"), IOStandard("SSTL15_II")),
# mcb3_dram_ras_n
Subsignal("ras_n", Pins("J6"), IOStandard("SSTL15_II")),
# mcb3_dram_cas_n
Subsignal("cas_n", Pins("H5"), IOStandard("SSTL15_II")),
# mcb3_dram_we_n
Subsignal("we_n", Pins("C1"), IOStandard("SSTL15_II")),
# mcb3_dram_dm, mcb3_dram_udm
Subsignal("dm", Pins("J4 K3"), IOStandard("SSTL15_II")),
# mcb3_dram_dq
Subsignal("dq", Pins(
"K2 K1 J3 J1 F2 F1 G3 G1",
"L3 L1 M2 M1 P2 P1 R2 R1"),
IOStandard("SSTL15_II")),
# mcb3_dram_dqs, mcb3_dram_udqs
Subsignal("dqs", Pins("H2 N3"), IOStandard("DIFF_SSTL15_II")),
# mcb3_dram_dqs_n, mcb3_dram_udqs_n
Subsignal("dqs_n", Pins("H1 N1"), IOStandard("DIFF_SSTL15_II")),
# mcb3_dram_cke
Subsignal("cke", Pins("F4"), IOStandard("SSTL15_II")),
# mcb3_dram_odt
Subsignal("odt", Pins("L5"), IOStandard("SSTL15_II")),
# mcb3_dram_reset_n
Subsignal("reset_n", Pins("E4"), IOStandard("LVCMOS15")),
# mcb3_rzq
Subsignal("rzq", Pins("M4"), IOStandard("SSTL15_II")),
# mcb3_zio
Subsignal("zio", Pins("M5"), IOStandard("SSTL15_II")),
),
]
class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 20.0
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-ftg256-2", _io)
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2428, 2483), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx16-ftg256-2"""', '_io'], {}), "(self, 'xc6slx16-ftg256-2', _io)\n", (2451, 2483), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
import random
from utils import *
from read_level import read_level, default_arty_settings
def _compare(val, ref, fmt, nbytes=4):
assert fmt in ["bin", "hex"]
if fmt == "hex":
print("0x{:0{n}x} {cmp} 0x{:0{n}x}".format(
val, ref, n=nbytes*2, cmp="==" if val == ref else "!="))
if fmt == "bin":
print("{:0{n}b} xor {:0{n}b} = {:0{n}b}".format(
val, ref, val ^ ref, n=nbytes*8))
# Perform a memory test using a random data pattern and linear addressing
def memtest_random(wb, base=None, length=0x80, inc=8, seed=42, verbose=None):
sdram_hardware_control(wb)
if base is None:
base = wb.mems.main_ram.base
rng = random.Random(seed)
refdata = []
for i in range(length//inc):
data = [rng.randint(0, 2**32 - 1) for _ in range(inc)]
wb.write(base + 4*inc*i, data)
refdata += data
data = []
for i in range(length//inc):
data += wb.read(base + 4*inc*i, inc)
assert len(refdata) == len(data)
errors = 0
for val, ref in zip(data, refdata):
if val != ref:
errors += 1
if verbose is not None:
print()
_compare(val, ref, fmt=verbose, nbytes=4)
return errors
def memtest_basic(wb, base=None, seed=42):
sdram_hardware_control(wb)
if base is None:
base = wb.mems.main_ram.base
rng = random.Random(seed)
sdram_pattern = rng.randrange(0x0, 0x100000000)
wb.write(base, sdram_pattern)
value = wb.read(base)
if value != sdram_pattern:
print('Mem error at 0x{:08x} : 0x{:08x} != 0x{:08x}'
.format(base, value, sdram_pattern))
print('x: ' + str(["0x{:08x}".format(w) for w in wb.read(base, 4)]))
else:
for i in range(0, 1024):
wb.write(base + i, 0x55555555)
for i in range(1024, 2048):
wb.write(base + i, 0xaaaaaaaa)
for i in range(0, 1024):
val = wb.read(base + i)
assert(val == 0x55555555)
for i in range(1024, 2048):
val = wb.read(base + i)
assert(val == 0xaaaaaaaa)
print('1. ' + str(["0x{:08x}".format(w) for w in wb.read(base + 1024 - 2 * 4, 4)]))
for i in range(0, 1024):
wb.write(base + i, 0xaaaaaaaa)
for i in range(1024, 2048):
wb.write(base + i, 0x55555555)
for i in range(0, 1024):
val = wb.read(base + i)
assert(val == 0xaaaaaaaa)
for i in range(1024, 2048):
val = wb.read(base + i)
assert(val == 0x55555555)
print('2. ' + str(["0x{:08x}".format(w) for w in wb.read(base + 1024 - 2 * 4, 4)]))
print("Mem ok!")
# ###########################################################################
if __name__ == "__main__":
import sys
from litex import RemoteClient
if '--srv' in sys.argv[1:]:
from wrapper import litex_srv
litex_srv()
wb = RemoteClient()
wb.open()
if '--no-init' not in sys.argv[1:]:
print('SDRAM initialization:')
sdram_init(wb)
print('\nRead leveling:')
read_level(wb, default_arty_settings())
print('\nMemtest (basic):')
memtest_basic(wb)
print('\nMemtest (random):')
errors = memtest_random(wb, length=0x2000)
print('OK' if errors == 0 else 'FAIL: errors = {}'.format(errors))
if '--memspeed' in sys.argv[1:]:
for n in [0x1000//4, 0x10000//4, 0x100000//4]:
print('Size = 0x{:08x}'.format(n*4))
memspeed(wb, n)
# Example results:
# Size = 0x00001000
# Write speed: 48.14 KB/s (0.0 sec)
# Read speed: 2.08 KB/s (0.1 sec)
# Size = 0x00010000
# Write speed: 82.45 KB/s (0.0 sec)
# Read speed: 3.09 KB/s (1.3 sec)
# Size = 0x00100000
# Write speed: 123.88 KB/s (0.5 sec)
# Read speed: 3.04 KB/s (21.6 sec)
# Size = 0x01000000
# Write speed: 47.24 KB/s (22.2 sec)
# So reading 1MB takes ~21.6 seconds.
# We have 256MB DRAM on board, so it should take ~1.5 hour to read.
# Writing is an order of magnitude faster.
wb.close()
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"litex.RemoteClient"
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#!/usr/bin/env python3
import os
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
# Info
# #########################
# - Completer le questionnaire (en commentant les réponses avec #)
# - Completer le code manquant (indiqué par TODO). (Ne pas oublier la déclaration
# des submodules: self.submodules += [...])
# - Renvoyer le code complété à <EMAIL>
# Si migen n'est pas installé, décommenter les lignes suivantes pour l'installer
#os.system("rm -rf migen")
#os.system("git clone http://github.com/m-labs/migen")
#os.system("mv migen migen_tmp")
#os.system("mv migen_tmp/migen migen")
#os.system("rm -rf migen_tmp")
# Evaluation cours FPGA
# #####################
# Nom / Prenom
# 1) Décrire en quelques phrases ce qu'est un FPGA et en quoi ce type de composant
# se distingue des autres composants plus traditionnels.
# 2) Donner 3 exemples d'applications où vous utiliseriez un FPGA, en expliquer les
# raisons/avantages.
# 3) Décrire les différentes étapes d'un flot de conception FPGA.
# 4) Dans un FPGA utilisant des LUT4 (4 entrées, 1 sortie)
# estimez les ressources (LUTs et Registres) des codes suivants:
# a)
# a = Signal()
# b = Signal()
# c = Signal()
# d = Signal()
# e = Signal()
# f = Signal()
# g = Signal()
# self.comb += f.eq(a & b & c & d & e)
# self.sync += g.eq(f)
# b)
# a = Signal(32)
# b = Signal(32)
# comp = Signal()
# r = Signal()
# self.comb += comp.eq(a == b)
# self.sync += r.eq(comp)
# ###### NE PAS MODIFIER ######
_io = [
("rst", 0, Pins("C12"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("serial_tx", 0, Pins("D4"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("L16"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("M13"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("R15"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("R17"), IOStandard("LVCMOS33")),
]
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 10.0
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-csg324-1", _io, toolchain="vivado")
class Tick(Module):
def __init__(self, sys_clk_freq, period):
# Module's interface
self.ce = ce = Signal() # output
# # #
counter_preload = int(period*sys_clk_freq - 1)
counter = Signal(max=int(period*sys_clk_freq - 1))
# Combinatorial assignements
self.comb += ce.eq(counter == 0)
# Synchronous assignments
self.sync += \
If(ce,
counter.eq(counter_preload)
).Else(
counter.eq(counter - 1)
)
# ###### NE PAS MODIFIER ######
# 5) Créer un Module qui à chaque pulse sur start serialize les données sur tx.
# La première donnée est un bit de start (0), suivi de data[0], data[n], data[7]
# et d'un bit de stop (1). Pour chaque data de 8 bits, 10 bits serialisés sont donc
# transmis.
class Serializer(Module):
"""Serialize input data at 115200 bauds"""
def __init__(self):
# Module's interface
self.start = start = Signal() # input
self.data = data = Signal(8) # input
self.tx = tx = Signal() # output
# # #
tick = Tick(100e6, 1/115200)
self.submodules += tick
run = Signal()
count = Signal(4)
self.sync += [
# If start, set run and clear count
# TODO
# If tick and run, check if count != 9 and increment it if it's the
# case / clear run it if not.
# TODO
]
# tx multiplexing
cases = {
0 : tx.eq(0b0), # start bit
1 : tx.eq(data[0]),
2 : tx.eq(0b0), # TODO
3 : tx.eq(0b0), # TODO
4 : tx.eq(0b0), # TODO
5 : tx.eq(0b0), # TODO
6 : tx.eq(0b0), # TODO
7 : tx.eq(0b0), # TODO
8 : tx.eq(0b0), # TODO
9 : tx.eq(0b0) # TODO
}
self.sync += If(tick.ce & run, Case(count, cases))
# ###### NE PAS MODIFIER ######
content = [
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0x6a, 0x25, 0x6b, 0x66, 0x6e, 0x77, 0x6a, 0x25,
0x6a, 0x79, 0x25, 0x6a, 0x73, 0x25, 0x7b, 0x74,
0x7a, 0x78, 0x25, 0x78, 0x74, 0x7a, 0x6d, 0x66,
0x6e, 0x79, 0x66, 0x73, 0x79, 0x25, 0x75, 0x71,
0x6a, 0x6e, 0x73, 0x25, 0x69, 0x6a, 0x25, 0x78,
0x7a, 0x68, 0x68, 0x6a, 0x78, 0x0f, 0x69, 0x66,
0x73, 0x78, 0x25, 0x7b, 0x74, 0x79, 0x77, 0x6a,
0x25, 0x6b, 0x7a, 0x79, 0x7a, 0x77, 0x6a, 0x25,
0x68, 0x66, 0x77, 0x77, 0x6e, 0x6a, 0x77, 0x6a,
0x26, 0x0f, 0x4b, 0x71, 0x74, 0x77, 0x6a, 0x73,
0x79, 0x0f
]
class Transmitter(Module):
"""Send sequence of data"""
def __init__(self):
# Module's interface
self.start = start = Signal() # output
self.data = data = Signal(8) # output
self.decode = Signal(4) # input (only to be used after step 6)
# # #
lut = Memory(8, depth=len(content), init=content)
port = lut.get_port(async_read=True)
self.specials += lut, port
tick = Tick(100e6, 0.005)
self.submodules += tick
count = Signal(max=len(content))
self.comb += port.adr.eq(count)
fsm = FSM(reset_state="START")
self.submodules.fsm = fsm
fsm.act("START",
If(tick.ce,
NextValue(start, 1),
If(count >= 152,
NextValue(data, port.dat_r - self.decode),
).Else(
NextValue(data, port.dat_r),
),
NextState("WAIT")
)
)
fsm.act("WAIT",
NextValue(start, 0),
If(count >= (len(content) - 1),
NextState("DONE")
).Else(
NextValue(count, count + 1),
NextState("START")
)
)
fsm.act("DONE",
NextValue(start, 0),
)
self.comb += port.adr.eq(count)
# ###### NE PAS MODIFIER ######
# 6) Instancier les modules Transmitter et Serializer dans le design et les
# connecter entre eux (start/data). Connecter la pin serial_tx à la sortie tx
# du module Serializer. Implémenter le design et tester sur carte.
#
# Pour visualiser ce que transmet le FPGA, lancer le script:
# lxterm /dev/ttyUSBX
#
# Pour reseter le FPGA, appuyer sur le bouton cpu_reset
# 7) Renseigner ci-dessous le message transmis par la carte et envoyer par mail
# ce fichier complété pour terminer l'évaluation.
class Design(Module):
def __init__(self, platform):
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst"))
# Transmitter
# TODO
# Serializer
# TODO
serializer = Serializer()
self.submodules += serializer
# Connection
self.comb += [
# TODO
]
# Build --------------------------------------------------------------------------------------------
platform = Platform()
design = Design(platform)
platform.build(design)
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2181, 2256), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (2204, 2256), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
from migen import *
from migen.genlib.misc import WaitTimer
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import orangecrab
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41K64M16, MT41K128M16, MT41K256M16, MT41K512M16
from litedram.phy import ECP5DDRPHY
# CRG ---------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.rst = Signal()
self.clock_domains.cd_por = ClockDomain()
self.clock_domains.cd_sys = ClockDomain()
# # #
# Clk / Rst
clk48 = platform.request("clk48")
rst_n = platform.request("usr_btn", loose=True)
if rst_n is None: rst_n = 1
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# USB PLL
if with_usb_pll:
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll = ECP5PLL()
self.submodules += usb_pll
self.comb += usb_pll.reset.eq(~por_done)
usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
reset_timer = WaitTimer(int(48e6))
reset_timer = ClockDomainsRenamer("por")(reset_timer)
self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n)
self.comb += platform.request("rst_n").eq(~reset_timer.done)
class _CRGSDRAM(Module):
def __init__(self, platform, sys_clk_freq, with_usb_pll=False):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain()
# # #
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk48 = platform.request("clk48")
rst_n = platform.request("usr_btn", loose=True)
if rst_n is None: rst_n = 1
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6)
self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
i_SEL = 0,
o_ECSOUT = sys2x_clk_ecsout),
Instance("ECLKSYNCB",
i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
]
# USB PLL
if with_usb_pll:
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll = ECP5PLL()
self.submodules += usb_pll
self.comb += usb_pll.reset.eq(~por_done)
usb_pll.register_clkin(clk48, 48e6)
usb_pll.create_clkout(self.cd_usb_48, 48e6)
usb_pll.create_clkout(self.cd_usb_12, 12e6)
# FPGA Reset (press usr_btn for 1 second to fallback to bootloader)
reset_timer = WaitTimer(int(48e6))
reset_timer = ClockDomainsRenamer("por")(reset_timer)
self.submodules += reset_timer
self.comb += reset_timer.wait.eq(~rst_n)
self.comb += platform.request("rst_n").eq(~reset_timer.done)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, revision="0.2", device="25F", sdram_device="MT41K64M16",
sys_clk_freq=int(48e6), toolchain="trellis", with_led_chaser=True, **kwargs):
platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain)
# Serial -----------------------------------------------------------------------------------
if kwargs["uart_name"] in ["serial", "usb_acm"]:
kwargs["uart_name"] = "usb_acm"
# Defaults to USB ACM through ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on OrangeCrab",
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
crg_cls = _CRGSDRAM if not self.integrated_main_ram_size else _CRG
self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
available_sdram_modules = {
"MT41K64M16": MT41K64M16,
"MT41K128M16": MT41K128M16,
"MT41K256M16": MT41K256M16,
"MT41K512M16": MT41K512M16,
}
sdram_module = available_sdram_modules.get(sdram_device)
ddram_pads = platform.request("ddram")
self.submodules.ddrphy = ECP5DDRPHY(
pads = ddram_pads,
sys_clk_freq = sys_clk_freq,
dm_remapping = {0:1, 1:0},
cmd_delay = 0 if sys_clk_freq > 64e6 else 100)
self.ddrphy.settings.rtt_nom = "disabled"
if hasattr(ddram_pads, "vccio"):
self.comb += ddram_pads.vccio.eq(0b111111)
if hasattr(ddram_pads, "gnd"):
self.comb += ddram_pads.gnd.eq(0)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = sdram_module(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on OrangeCrab")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency.")
target_group.add_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).")
target_group.add_argument("--device", default="25F", help="ECP5 device (25F, 45F or 85F).")
target_group.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (MT41K64M16, MT41K128M16, MT41K256M16 or MT41K512M16).")
target_group.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
revision = args.revision,
device = args.device,
sdram_device = args.sdram_device,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args))
if args.with_spi_sdcard:
soc.add_spi_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()
| [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((8240, 8301), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on OrangeCrab"""'}), "(description='LiteX SoC on OrangeCrab')\n", (8262, 8301), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((9328, 9348), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (9340, 9348), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((5402, 5476), 'litex_boards.platforms.orangecrab.Platform', 'orangecrab.Platform', ([], {'revision': 'revision', 'device': 'device', 'toolchain': 'toolchain'}), '(revision=revision, device=device, toolchain=toolchain)\n', (5421, 5476), False, 'from litex_boards.platforms import orangecrab\n'), ((9773, 9794), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (9788, 9794), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((4227, 4288), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~pll.locked | self.reset)'], {}), '(self.cd_sys, ~pll.locked | self.reset)\n', (4249, 4288), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((5746, 5824), 'os.system', 'os.system', (['"""git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri"""'], {}), "('git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri')\n", (5755, 5824), False, 'import os\n'), ((5837, 5866), 'sys.path.append', 'sys.path.append', (['"""valentyusb"""'], {}), "('valentyusb')\n", (5852, 5866), False, 'import sys\n'), ((6947, 7087), 'litedram.phy.ECP5DDRPHY', 'ECP5DDRPHY', ([], {'pads': 'ddram_pads', 'sys_clk_freq': 'sys_clk_freq', 'dm_remapping': '{(0): 1, (1): 0}', 'cmd_delay': '(0 if sys_clk_freq > 64000000.0 else 100)'}), '(pads=ddram_pads, sys_clk_freq=sys_clk_freq, dm_remapping={(0): 1,\n (1): 0}, cmd_delay=0 if sys_clk_freq > 64000000.0 else 100)\n', (6957, 7087), False, 'from litedram.phy import ECP5DDRPHY\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import timeline
from migen.genlib.cdc import PulseSynchronizer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
# Xilinx 7-series ----------------------------------------------------------------------------------
class ICAP(Module, AutoCSR):
"""ICAP
Allow sending commands to ICAPE2 of Xilinx 7-Series FPGAs, the bistream can for example be
reloaded from SPI Flash by writing 0x00000000 at address @0x4.
"""
def __init__(self, with_csr=True, simulation=False):
self.addr = Signal(5)
self.data = Signal(32)
self.send = Signal()
self.done = Signal()
# # #
# Create slow icap clk (sys_clk/16) ---------------------------------------------------------
self.clock_domains.cd_icap = ClockDomain()
icap_clk_counter = Signal(4)
self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
self.sync += self.cd_icap.clk.eq(icap_clk_counter[3])
# Resynchronize send pulse to icap domain ---------------------------------------------------
ps_send = PulseSynchronizer("sys", "icap")
self.submodules += ps_send
self.comb += ps_send.i.eq(self.send)
# Generate icap bitstream write sequence
self._csib = _csib = Signal(reset=1)
self._i = _i = Signal(32)
_addr = self.addr << 13
_data = self.data
self.sync.icap += [
_i.eq(0xffffffff), # dummy
timeline(ps_send.o, [
(1, [_csib.eq(1), self.done.eq(0)]),
(2, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(3, [_csib.eq(0), _i.eq(0xaa995566)]), # sync word
(4, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(5, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(6, [_csib.eq(0), _i.eq(0x30000001 | _addr)]), # write command
(7, [_csib.eq(0), _i.eq(_data)]), # write value
(8, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(9, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(10, [_csib.eq(0), _i.eq(0x30008001)]), # write to cmd register
(11, [_csib.eq(0), _i.eq(0x0000000d)]), # desync command
(12, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(13, [_csib.eq(0), _i.eq(0x20000000)]), # noop
(14, [_csib.eq(1), self.done.eq(1)]),
])
]
# ICAP instance
if not simulation:
self.specials += Instance("ICAPE2",
p_ICAP_WIDTH = "X32",
i_CLK = ClockSignal("icap"),
i_CSIB = _csib,
i_RDWRB = 0,
i_I = Cat(*[_i[8*i:8*(i+1)][::-1] for i in range(4)]),
)
# CSR
if with_csr:
self.add_csr()
def add_csr(self):
self._addr = CSRStorage(5, reset_less=True, description="ICAP Write Address.")
self._data = CSRStorage(32, reset_less=True, description="ICAP Write Data.")
self._send = CSRStorage(description="ICAP Control.\n\n Write ``1`` send a write command to the ICAP.")
self._done = CSRStatus(reset=1, description="ICAP Status.\n\n Write command done when read as ``1``.")
self.comb += [
self.addr.eq(self._addr.storage),
self.data.eq(self._data.storage),
self.send.eq(self._send.re),
self._done.status.eq(self.done)
]
def add_reload(self):
self.reload = Signal() # Set to 1 to reload FPGA from logic.
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(self.reload,
NextState("RELOAD")
)
)
fsm.act("RELOAD",
self.addr.eq(0x4),
self.data.eq(0xf),
self.send.eq(1),
)
def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
platform.add_period_constraint(self.cd_icap.clk, 16*1e9/sys_clk_freq)
platform.add_false_path_constraints(self.cd_icap.clk, sys_clk)
class ICAPBitstream(Module, AutoCSR):
"""ICAP Bitstream
Allow sending bitstreams to ICAPE2 of Xilinx 7-Series FPGAs.
The CPU can push stream of data to the ICAPE2 by reading `sink_ready` CSR to verify that there is
space available in the FIFO; then write the data to `sink_data` register. Each word written to the
FIFO is transmitted to the ICAPE2 using the slow icap_clk (with expected bit/byte reordering).
The CPU accesses/FIFO must be fast/large enough to ensure there is no gap in the stream sent to
the ICAPE2.
"""
def __init__(self, fifo_depth=8, icap_clk_div=4, simulation=False):
self.sink_data = CSRStorage(32, reset_less=True)
self.sink_ready = CSRStatus()
# # #
# Create slow icap_clk (sys_clk/4) ---------------------------------------------------------
icap_clk_counter = Signal(log2_int(icap_clk_div))
self.clock_domains.cd_icap = ClockDomain()
self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
self.sync += self.cd_icap.clk.eq(icap_clk_counter[-1])
# FIFO (sys_clk to icap_clk) ---------------------------------------------------------------
fifo = stream.AsyncFIFO([("data", 32)], fifo_depth)
fifo = ClockDomainsRenamer({"write": "sys", "read": "icap"})(fifo)
self.submodules += fifo
self.comb += [
fifo.sink.valid.eq(self.sink_data.re),
fifo.sink.data.eq(self.sink_data.storage),
self.sink_ready.status.eq(fifo.sink.ready),
]
# Generate ICAP commands -------------------------------------------------------------------
self._csib = _csib = Signal(reset=1)
self._i = _i = Signal(32, reset=0xffffffff)
self.comb += [
fifo.source.ready.eq(1),
If(fifo.source.valid,
_csib.eq(0),
_i.eq(fifo.source.data)
)
]
# ICAP instance ----------------------------------------------------------------------------
if not simulation:
self.specials += Instance("ICAPE2",
p_ICAP_WIDTH = "X32",
i_CLK = ClockSignal("icap"),
i_CSIB = _csib,
i_RDWRB = 0,
i_I = Cat(*[_i[8*i:8*(i+1)][::-1] for i in range(4)])
)
def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
platform.add_period_constraint(self.cd_icap.clk, 16*1e9/sys_clk_freq)
platform.add_false_path_constraints(self.cd_icap.clk, sys_clk)
| [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((1252, 1284), 'migen.genlib.cdc.PulseSynchronizer', 'PulseSynchronizer', (['"""sys"""', '"""icap"""'], {}), "('sys', 'icap')\n", (1269, 1284), False, 'from migen.genlib.cdc import PulseSynchronizer\n'), ((5541, 5585), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', 32)]", 'fifo_depth'], {}), "([('data', 32)], fifo_depth)\n", (5557, 5585), False, 'from litex.soc.interconnect import stream\n')] |
from itertools import product, count
import itertools
from sys import stdout
import time
import json
import ctypes
from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('--samples', type=int, default=-1)
parser.add_argument('--dumpfile', default='dump.py')
args = parser.parse_args()
samples_iter = range(args.samples) if args.samples >= 0 else count()
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True, config_csv="test/analyzer.csv")
analyzer.run(length=2**20) ### CHANGE THIS TO MATCH DEPTH offset=32 by default
with open('entropy.dat', 'ab') as f:
for _ in samples_iter:
wb.regs.trng_update_value.write(1)
while not wb.regs.trng_ready.read():
pass
random_word = wb.regs.trng_random_word.read()
print(hex(random_word))
f.write(random_word.to_bytes(4, 'big'))
analyzer.wait_done()
analyzer.upload()
analyzer.save(f"test/{args.dumpfile}")
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((263, 288), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (286, 288), False, 'import argparse\n'), ((501, 537), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (513, 537), False, 'from litex.tools.litex_client import RemoteClient\n'), ((560, 653), 'litescope.software.driver.analyzer.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (['wb.regs', '"""analyzer"""'], {'debug': '(True)', 'config_csv': '"""test/analyzer.csv"""'}), "(wb.regs, 'analyzer', debug=True, config_csv=\n 'test/analyzer.csv')\n", (583, 653), False, 'from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver\n'), ((486, 493), 'itertools.count', 'count', ([], {}), '()\n', (491, 493), False, 'from itertools import product, count\n')] |
#
# This file is part of LiteHyperBus
#
# Copyright (c) 2019-2022 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import timeline
from litex.build.io import DifferentialOutput
from litex.soc.interconnect import wishbone
# HyperRAM -----------------------------------------------------------------------------------------
class HyperRAM(Module):
"""HyperRAM
Provides a very simple/minimal HyperRAM core that should work with all FPGA/HyperRam chips:
- FPGA vendor agnostic.
- no setup/chip configuration (use default latency).
This core favors portability and ease of use over performance.
"""
def __init__(self, pads, latency=6):
self.pads = pads
self.bus = bus = wishbone.Interface()
# # #
clk = Signal()
clk_phase = Signal(2)
cs = Signal()
ca = Signal(48)
ca_active = Signal()
sr = Signal(48)
sr_new = Signal(48)
dq = self.add_tristate(pads.dq) if not hasattr(pads.dq, "oe") else pads.dq
rwds = self.add_tristate(pads.rwds) if not hasattr(pads.rwds, "oe") else pads.rwds
dw = len(pads.dq) if not hasattr(pads.dq, "oe") else len(pads.dq.o)
assert dw in [8, 16]
# Drive Control Signals --------------------------------------------------------------------
# Rst.
if hasattr(pads, "rst_n"):
self.comb += pads.rst_n.eq(1)
# CSn.
self.comb += pads.cs_n[0].eq(~cs)
assert len(pads.cs_n) <= 2
if len(pads.cs_n) == 2:
self.comb += pads.cs_n[1].eq(1)
# Clk.
if hasattr(pads, "clk"):
self.comb += pads.clk.eq(clk)
else:
self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n)
# Clock Generation (sys_clk/4) -------------------------------------------------------------
self.sync += clk_phase.eq(clk_phase + 1)
cases = {}
cases[1] = clk.eq(cs) # Set pads clk on 90° (if cs is set)
cases[3] = clk.eq(0) # Clear pads clk on 270°
self.sync += Case(clk_phase, cases)
# Data Shift-In Register -------------------------------------------------------------------
dqi = Signal(dw)
self.sync += dqi.eq(dq.i) # Sample on 90° and 270°
self.comb += [
sr_new.eq(Cat(dqi, sr[:-dw])),
If(ca_active,
sr_new.eq(Cat(dqi[:8], sr[:-8])) # Only 8-bit during Command/Address.
)
]
self.sync += If(clk_phase[0] == 0, sr.eq(sr_new)) # Shift on 0° and 180°
# Data Shift-Out Register ------------------------------------------------------------------
self.comb += [
bus.dat_r.eq(sr_new),
If(dq.oe,
dq.o.eq(sr[-dw:]),
If(ca_active,
dq.o.eq(sr[-8:]) # Only 8-bit during Command/Address.
)
)
]
# Command generation -----------------------------------------------------------------------
ashift = {8:1, 16:0}[dw]
self.comb += [
ca[47].eq(~bus.we), # R/W#
ca[45].eq(1), # Burst Type (Linear)
ca[16:45].eq(bus.adr[3-ashift:]), # Row & Upper Column Address
ca[ashift:3].eq(bus.adr), # Lower Column Address
]
# Latency count starts from the middle of the command (thus the -4). In fixed latency mode
# (default), latency is 2 x Latency count. We have 4 x sys_clk per RAM clock:
latency_cycles = (latency * 2 * 4) - 4
# Bus Latch --------------------------------------------------------------------------------
bus_adr = Signal(32)
bus_we = Signal()
bus_sel = Signal(4)
bus_latch = Signal()
self.sync += If(bus_latch,
If(bus.we,
sr.eq(Cat(Signal(16), bus.dat_w)),
),
bus_we.eq(bus.we),
bus_sel.eq(bus.sel),
bus_adr.eq(bus.adr)
)
# FSM (Sequencer) --------------------------------------------------------------------------
cycles = Signal(8)
first = Signal()
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
NextValue(first, 1),
If(bus.cyc & bus.stb,
If(clk_phase == 0,
NextValue(sr, ca),
NextState("SEND-COMMAND-ADDRESS")
)
)
)
fsm.act("SEND-COMMAND-ADDRESS",
# Set CSn.
cs.eq(1),
# Send Command on DQ.
ca_active.eq(1),
dq.oe.eq(1),
# Wait for 6*2 cycles...
If(cycles == (6*2 - 1),
NextState("WAIT-LATENCY")
)
)
fsm.act("WAIT-LATENCY",
# Set CSn.
cs.eq(1),
# Wait for Latency cycles...
If(cycles == (latency_cycles - 1),
# Latch Bus.
bus_latch.eq(1),
# Early Write Ack (to allow bursting).
bus.ack.eq(bus.we),
NextState("READ-WRITE-DATA0")
)
)
states = {8:4, 16:2}[dw]
for n in range(states):
fsm.act(f"READ-WRITE-DATA{n}",
# Set CSn.
cs.eq(1),
# Send Data on DQ/RWDS (for write).
If(bus_we,
dq.oe.eq(1),
rwds.oe.eq(1),
*[rwds.o[dw//8-1-i].eq(~bus_sel[4-1-n*dw//8-i]) for i in range(dw//8)],
),
# Wait for 2 cycles (since HyperRAM's Clk = sys_clk/4).
If(cycles == (2 - 1),
# Set next default state (with rollover for bursts).
NextState(f"READ-WRITE-DATA{(n + 1)%states}"),
# On last state, see if we can continue the burst or if we should end it.
If(n == (states - 1),
NextValue(first, 0),
# Continue burst when a consecutive access is ready.
If(bus.stb & bus.cyc & (bus.we == bus_we) & (bus.adr == (bus_adr + 1)),
# Latch Bus.
bus_latch.eq(1),
# Early Write Ack (to allow bursting).
bus.ack.eq(bus.we)
# Else end the burst.
).Elif(bus_we | ~first,
NextState("IDLE")
)
),
# Read Ack (when dat_r ready).
If((n == 0) & ~first,
bus.ack.eq(~bus_we),
)
)
)
fsm.finalize()
self.sync += cycles.eq(cycles + 1)
self.sync += If(fsm.next_state != fsm.state, cycles.eq(0))
def add_tristate(self, pad):
t = TSTriple(len(pad))
self.specials += t.get_tristate(pad)
return t
| [
"litex.build.io.DifferentialOutput",
"litex.soc.interconnect.wishbone.Interface"
] | [((844, 864), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (862, 864), False, 'from litex.soc.interconnect import wishbone\n'), ((1910, 1957), 'litex.build.io.DifferentialOutput', 'DifferentialOutput', (['clk', 'pads.clk_p', 'pads.clk_n'], {}), '(clk, pads.clk_p, pads.clk_n)\n', (1928, 1957), False, 'from litex.build.io import DifferentialOutput\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2016 whitequark <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import signal
import os
import time
import serial
import threading
import multiprocessing
import argparse
import json
import socket
# Console ------------------------------------------------------------------------------------------
if sys.platform == "win32":
import ctypes
import msvcrt
class Console:
def configure(self):
# https://stackoverflow.com/a/36760881
# ENABLE_VIRTUAL_TERMINAL_PROCESSING
kernel32 = ctypes.windll.kernel32
kernel32.SetConsoleMode(kernel32.GetStdHandle(-11), 7)
def unconfigure(self):
pass
def getkey(self):
return msvcrt.getch()
# getch doesn't return Virtual Keycodes, but rather
# PS/2 Scan Codes. Keycodes starting with 0xE0 are
# worth handling.
def escape_char(self, b):
return b == b"\xe0"
def handle_escape(self, b):
return {
b"H" : b"\x1b[A", # Up
b"P" : b"\x1b[B", # Down
b"K" : b"\x1b[D", # Left
b"M" : b"\x1b[C", # Right
b"G" : b"\x1b[H", # Home
b"O" : b"\x1b[F", # End
b"R" : b"\x1b[2~", # Insert
b"S" : b"\x1b[3~", # Delete
}.get(b, None) # TODO: Handle ESC? Others?
else:
import termios
import pty
class Console:
def __init__(self):
self.fd = sys.stdin.fileno()
self.default_settings = termios.tcgetattr(self.fd)
def configure(self):
settings = termios.tcgetattr(self.fd)
settings[3] = settings[3] & ~termios.ICANON & ~termios.ECHO
settings[6][termios.VMIN] = 1
settings[6][termios.VTIME] = 0
termios.tcsetattr(self.fd, termios.TCSANOW, settings)
def unconfigure(self):
termios.tcsetattr(self.fd, termios.TCSAFLUSH, self.default_settings)
def getkey(self):
return os.read(self.fd, 1)
def escape_char(self, b):
return False
def handle_escape(self, b):
return None
# Bridge UART -------------------------------------------------------------------------------------
from litex import RemoteClient
class BridgeUART:
def __init__(self, name="uart_xover", host="localhost", base_address=None, csr_csv=None):
self.bus = RemoteClient(host=host, base_address=base_address, csr_csv=csr_csv)
present = False
for k, v in self.bus.regs.d.items():
if f"{name}_" in k:
setattr(self, k.replace(f"{name}_", ""), v)
present = True
if not present:
raise ValueError(f"CrossoverUART {name} not present in design.")
# FIXME: On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
if base_address is None and hasattr(self.bus.bases, "pcie_phy"):
self.bus.base_address = -self.bus.mems.csr.base
def open(self):
self.bus.open()
self.file, self.name = pty.openpty()
self.pty2crossover_thread = multiprocessing.Process(target=self.pty2crossover)
self.crossover2pty_thread = multiprocessing.Process(target=self.crossover2pty)
self.pty2crossover_thread.start()
self.crossover2pty_thread.start()
def close(self):
self.bus.close()
self.pty2crossover_thread.terminate()
self.crossover2pty_thread.terminate()
def pty2crossover(self):
while True:
r = os.read(self.file, 1)
self.rxtx.write(ord(r))
def crossover2pty(self):
while True:
if self.rxfull.read():
length = 16
elif not self.rxempty.read():
length = 1
else:
time.sleep(1e-3)
continue
r = self.bus.read(self.rxtx.addr, length=length, burst="fixed")
for v in r:
os.write(self.file, bytes(chr(v).encode("utf-8")))
# JTAG UART ----------------------------------------------------------------------------------------
from litex.build.openocd import OpenOCD
class JTAGUART:
def __init__(self, config="openocd_xc7_ft2232.cfg", port=20000, chain=1):
self.config = config
self.port = port
self.chain = chain
def open(self):
self.file, self.name = pty.openpty()
self.jtag2tcp_thread = multiprocessing.Process(target=self.jtag2tcp)
self.jtag2tcp_thread.start()
time.sleep(0.5)
self.pty2tcp_thread = multiprocessing.Process(target=self.pty2tcp)
self.tcp2pty_thread = multiprocessing.Process(target=self.tcp2pty)
self.tcp = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
self.tcp.connect(("localhost", self.port))
self.pty2tcp_thread.start()
self.tcp2pty_thread.start()
def close(self):
self.jtag2tcp_thread.terminate()
self.pty2tcp_thread.terminate()
self.tcp2pty_thread.terminate()
def jtag2tcp(self):
prog = OpenOCD(self.config)
prog.stream(self.port, self.chain)
def pty2tcp(self):
while True:
r = os.read(self.file, 1)
self.tcp.send(r)
def tcp2pty(self):
while True:
r = self.tcp.recv(1)
os.write(self.file, bytes(r))
# Intel/Altera JTAG UART via nios2-terminal
class Nios2Terminal():
def __init__(self):
from subprocess import Popen, PIPE
p = Popen("nios2-terminal", stdin=PIPE, stdout=PIPE)
self.p = p
def read(self):
return self.p.stdout.read(1)
def in_waiting(self):
# unfortunately p.stdout does not provide
# information about awaiting input
return False
def write(self, data):
if data is not None:
self.p.stdin.write(data)
try:
self.p.stdin.flush()
except BrokenPipeError:
print("nios2-terminal has terminated, exiting...\n")
sys.exit(1)
def close(self):
self.p.terminate()
# SFL ----------------------------------------------------------------------------------------------
sfl_prompt_req = b"F7: boot from serial\n"
sfl_prompt_ack = b"\x06"
sfl_magic_req = b"sL5DdSMmkekro\n"
sfl_magic_ack = b"z6IHG7cYDID6o\n"
sfl_payload_length = 255
sfl_outstanding = 128
# General commands
sfl_cmd_abort = b"\x00"
sfl_cmd_load = b"\x01"
sfl_cmd_jump = b"\x02"
# Replies
sfl_ack_success = b"K"
sfl_ack_crcerror = b"C"
sfl_ack_unknown = b"U"
sfl_ack_error = b"E"
class SFLFrame:
def __init__(self):
self.cmd = bytes()
self.payload = bytes()
def compute_crc(self):
return crc16(self.cmd + self.payload)
def encode(self):
packet = bytes([len(self.payload)])
packet += self.compute_crc().to_bytes(2, "big")
packet += self.cmd
packet += self.payload
return packet
# CRC16 --------------------------------------------------------------------------------------------
crc16_table = [
0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
]
def crc16(l):
crc = 0
for d in l:
crc = crc16_table[((crc >> 8) ^ d) & 0xff] ^ (crc << 8)
return crc & 0xffff
# LiteXTerm ----------------------------------------------------------------------------------------
class LiteXTerm:
def __init__(self, serial_boot, kernel_image, kernel_address, json_images):
self.serial_boot = serial_boot
assert not (kernel_image is not None and json_images is not None)
self.mem_regions = {}
if kernel_image is not None:
self.mem_regions = {kernel_image: kernel_address}
self.boot_address = kernel_address
if json_images is not None:
f = open(json_images, "r")
json_dir = os.path.dirname(json_images)
for k, v in json.load(f).items():
self.mem_regions[os.path.join(json_dir, k)] = v
self.boot_address = self.mem_regions[list(self.mem_regions.keys())[-1]]
f.close()
self.reader_alive = False
self.writer_alive = False
self.prompt_detect_buffer = bytes(len(sfl_prompt_req))
self.magic_detect_buffer = bytes(len(sfl_magic_req))
self.console = Console()
signal.signal(signal.SIGINT, self.sigint)
self.sigint_time_last = 0
def open(self, port, baudrate):
if hasattr(self, "port"):
return
# FIXME: https://github.com/enjoy-digital/litex/issues/720
if "ttyACM" in port:
self.payload_length = sfl_payload_length
self.delay = 1e-4
elif "tty.usbmodem" in port:
self.payload_length = sfl_payload_length
self.delay = 1e-3
else:
self.payload_length = 64
self.delay = 1e-5
self.port = serial.serial_for_url(port, baudrate)
def close(self):
if not hasattr(self, "port"):
return
self.port.close()
del self.port
def sigint(self, sig, frame):
if hasattr(self, "port"):
self.port.write(b"\x03")
sigint_time_current = time.time()
# Exit term if 2 CTRL-C pressed in less than 0.5s.
if (sigint_time_current - self.sigint_time_last < 0.5):
self.console.unconfigure()
self.close()
sys.exit()
else:
self.sigint_time_last = sigint_time_current
def send_frame(self, frame):
retry = 1
while retry:
self.port.write(frame.encode())
# Get the reply from the device
reply = self.port.read()
if reply == sfl_ack_success:
retry = 0
elif reply == sfl_ack_crcerror:
retry = 1
else:
print("[LXTERM] Got unknown reply '{}' from the device, aborting.".format(reply))
return 0
return 1
def receive_upload_response(self):
reply = self.port.read()
if reply == sfl_ack_success:
return True
elif reply == sfl_ack_crcerror:
print("[LXTERM] Upload to device failed due to data corruption (CRC error)")
else:
print(f"[LXTERM] Got unexpected response from device '{reply}'")
sys.exit(1)
def upload(self, filename, address):
f = open(filename, "rb")
f.seek(0, 2)
length = f.tell()
f.seek(0, 0)
print(f"[LXTERM] Uploading {filename} to 0x{address:08x} ({length} bytes)...")
# Prepare parameters
current_address = address
position = 0
start = time.time()
remaining = length
outstanding = 0
while remaining:
# Show progress
sys.stdout.write("|{}>{}| {}%\r".format(
"=" * (20*position//length),
" " * (20-20*position//length),
100*position//length))
sys.stdout.flush()
# Send frame if max outstanding not reached.
if outstanding <= sfl_outstanding:
# Prepare frame.
frame = SFLFrame()
frame.cmd = sfl_cmd_load
frame_data = f.read(min(remaining, self.payload_length-4))
frame.payload = current_address.to_bytes(4, "big")
frame.payload += frame_data
# Encode frame and send it.
self.port.write(frame.encode())
# Update parameters
current_address += len(frame_data)
position += len(frame_data)
remaining -= len(frame_data)
outstanding += 1
# Inter-frame delay.
time.sleep(self.delay)
# Read response if available.
while self.port.in_waiting:
ack = self.receive_upload_response()
if ack:
outstanding -= 1
break
# Get remaining responses.
for _ in range(outstanding):
self.receive_upload_response()
# Compute speed.
end = time.time()
elapsed = end - start
print("[LXTERM] Upload complete ({0:.1f}KB/s).".format(length/(elapsed*1024)))
f.close()
return length
def boot(self):
print("[LXTERM] Booting the device.")
frame = SFLFrame()
frame.cmd = sfl_cmd_jump
frame.payload = int(self.boot_address, 16).to_bytes(4, "big")
self.send_frame(frame)
def detect_prompt(self, data):
if len(data):
self.prompt_detect_buffer = self.prompt_detect_buffer[1:] + data
return self.prompt_detect_buffer == sfl_prompt_req
else:
return False
def answer_prompt(self):
print("[LXTERM] Received serial boot prompt from the device.")
self.port.write(sfl_prompt_ack)
def detect_magic(self, data):
if len(data):
self.magic_detect_buffer = self.magic_detect_buffer[1:] + data
return self.magic_detect_buffer == sfl_magic_req
else:
return False
def answer_magic(self):
print("[LXTERM] Received firmware download request from the device.")
if(len(self.mem_regions)):
self.port.write(sfl_magic_ack)
for filename, base in self.mem_regions.items():
self.upload(filename, int(base, 16))
self.boot()
print("[LXTERM] Done.")
def reader(self):
try:
while self.reader_alive:
c = self.port.read()
sys.stdout.buffer.write(c)
sys.stdout.flush()
if len(self.mem_regions):
if self.serial_boot and self.detect_prompt(c):
self.answer_prompt()
if self.detect_magic(c):
self.answer_magic()
except serial.SerialException:
self.reader_alive = False
self.console.unconfigure()
raise
def start_reader(self):
self.reader_alive = True
self.reader_thread = threading.Thread(target=self.reader)
self.reader_thread.setDaemon(True)
self.reader_thread.start()
def stop_reader(self):
self.reader_alive = False
self.reader_thread.join()
def writer(self):
try:
while self.writer_alive:
b = self.console.getkey()
if b == b"\x03":
self.stop()
elif b == b"\n":
self.port.write(b"\x0a")
elif self.console.escape_char(b):
b = self.console.getkey()
ansi_seq = self.console.handle_escape(b)
self.port.write(ansi_seq)
else:
self.port.write(b)
except:
self.writer_alive = False
self.console.unconfigure()
raise
def start_writer(self):
self.writer_alive = True
self.writer_thread = threading.Thread(target=self.writer)
self.writer_thread.setDaemon(True)
self.writer_thread.start()
def stop_writer(self):
self.writer_alive = False
self.writer_thread.join()
def start(self):
self.start_reader()
self.start_writer()
def stop(self):
self.reader_alive = False
self.writer_alive = False
def join(self, writer_only=False):
self.writer_thread.join()
if not writer_only:
self.reader_thread.join()
# Run ----------------------------------------------------------------------------------------------
def _get_args():
parser = argparse.ArgumentParser()
parser.add_argument("port", help="Serial port (eg /dev/tty*, bridge, jtag)")
parser.add_argument("--speed", default=115200, help="Serial baudrate")
parser.add_argument("--serial-boot", default=False, action='store_true', help="Automatically initiate serial boot")
parser.add_argument("--kernel", default=None, help="Kernel image")
parser.add_argument("--kernel-adr", default="0x40000000", help="Kernel address")
parser.add_argument("--images", default=None, help="JSON description of the images to load to memory")
parser.add_argument("--csr-csv", default=None, help="SoC CSV file")
parser.add_argument("--base-address", default=None, help="CSR base address")
parser.add_argument("--bridge-name", default="uart_xover", help="Bridge UART name to use (present in design/csr.csv)")
parser.add_argument("--jtag-name", default="jtag_uart", help="JTAG UART type: jtag_uart (default), jtag_atlantic")
parser.add_argument("--jtag-config", default="openocd_xc7_ft2232.cfg", help="OpenOCD JTAG configuration file for jtag_uart")
parser.add_argument("--jtag-chain", default=1, help="JTAG chain.")
return parser.parse_args()
def main():
args = _get_args()
term = LiteXTerm(args.serial_boot, args.kernel, args.kernel_adr, args.images)
if sys.platform == "win32":
if args.port in ["bridge", "jtag"]:
raise NotImplementedError
if args.port in ["bridge", "crossover"]: # FIXME: 2021-02-18, crossover for retro-compatibility remove and update targets?
base_address = None if args.base_address is None else int(args.base_address)
bridge = BridgeUART(base_address=base_address, csr_csv=args.csr_csv, name=args.bridge_name)
bridge.open()
port = os.ttyname(bridge.name)
elif args.port in ["jtag"]:
if args.jtag_name == "jtag_atlantic":
term.port = Nios2Terminal()
port = args.port
term.payload_length = 128
term.delay = 1e-6
elif args.jtag_name == "jtag_uart":
bridge = JTAGUART(config=args.jtag_config, chain=int(args.jtag_chain))
bridge.open()
port = os.ttyname(bridge.name)
else:
raise NotImplementedError
else:
port = args.port
term.open(port, int(float(args.speed)))
term.console.configure()
term.start()
term.join(True)
if __name__ == "__main__":
main()
| [
"litex.build.openocd.OpenOCD",
"litex.RemoteClient"
] | [((18233, 18258), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (18256, 18258), False, 'import argparse\n'), ((2627, 2694), 'litex.RemoteClient', 'RemoteClient', ([], {'host': 'host', 'base_address': 'base_address', 'csr_csv': 'csr_csv'}), '(host=host, base_address=base_address, csr_csv=csr_csv)\n', (2639, 2694), False, 'from litex import RemoteClient\n'), ((3273, 3286), 'pty.openpty', 'pty.openpty', ([], {}), '()\n', (3284, 3286), False, 'import pty\n'), ((3323, 3373), 'multiprocessing.Process', 'multiprocessing.Process', ([], {'target': 'self.pty2crossover'}), '(target=self.pty2crossover)\n', (3346, 3373), False, 'import multiprocessing\n'), ((3410, 3460), 'multiprocessing.Process', 'multiprocessing.Process', ([], {'target': 'self.crossover2pty'}), '(target=self.crossover2pty)\n', (3433, 3460), False, 'import multiprocessing\n'), ((4607, 4620), 'pty.openpty', 'pty.openpty', ([], {}), '()\n', (4618, 4620), False, 'import pty\n'), ((4652, 4697), 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sys\n'), ((14235, 14257), 'time.sleep', 'time.sleep', (['self.delay'], {}), '(self.delay)\n', (14245, 14257), False, 'import time\n'), ((16116, 16142), 'sys.stdout.buffer.write', 'sys.stdout.buffer.write', (['c'], {}), '(c)\n', (16139, 16142), False, 'import sys\n'), ((16159, 16177), 'sys.stdout.flush', 'sys.stdout.flush', ([], {}), '()\n', (16175, 16177), False, 'import sys\n'), ((4024, 4041), 'time.sleep', 'time.sleep', (['(0.001)'], {}), '(0.001)\n', (4034, 4041), False, 'import time\n'), ((6263, 6274), 'sys.exit', 'sys.exit', (['(1)'], {}), '(1)\n', (6271, 6274), False, 'import sys\n'), ((10282, 10294), 'json.load', 'json.load', (['f'], {}), '(f)\n', (10291, 10294), False, 'import json\n'), ((10337, 10362), 'os.path.join', 'os.path.join', (['json_dir', 'k'], {}), '(json_dir, k)\n', (10349, 10362), False, 'import os\n'), ((20685, 20708), 'os.ttyname', 'os.ttyname', (['bridge.name'], {}), '(bridge.name)\n', (20695, 20708), False, 'import os\n')] |
#!/usr/bin/env python3
import sys
import os
import argparse
import subprocess
import struct
import importlib
from migen.fhdl import verilog
from migen.fhdl.structure import _Fragment
from litex.build.tools import write_to_file
from litex.build.xilinx.common import *
from litex.soc.integration import cpu_interface
def autotype(s):
if s == "True":
return True
elif s == "False":
return False
try:
return int(s, 0)
except ValueError:
pass
return s
def _import(default, name):
return importlib.import_module(default + "." + name)
def _get_args():
parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
description="""\
LiteScope - based on Migen.
This program builds and/or loads LiteScope components.
One or several actions can be specified:
clean delete previous build(s).
build-core build verilog core.
build-bitstream build-bitstream build FPGA bitstream.
build-csr-csv save CSR map into CSV file.
load-bitstream load bitstream into volatile storage.
all clean, build-csr-csv, build-bitstream, load-bitstream.
""")
parser.add_argument("-t", "--target", default="simple", help="Core type to build")
parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
parser.add_argument("-p", "--platform", default=None, help="platform to build for")
parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")
parser.add_argument("action", nargs="+", help="specify an action")
return parser.parse_args()
if __name__ == "__main__":
args = _get_args()
# create top-level Core object
target_module = _import("targets", args.target)
if args.sub_target:
top_class = getattr(target_module, args.sub_target)
else:
top_class = target_module.default_subtarget
if hasattr(top_class, "platform"):
platform = top_class.platform
platform_name = top_class.platform.name
else:
if args.platform is None:
if hasattr(top_class, "default_platform"):
platform_name = top_class.default_platform
else:
raise ValueError("Target has no default platform, specify a platform with -p your_platform")
else:
platform_name = args.platform
try:
platform_module = _import("litex.boards.platforms", platform_name)
except:
platform_module = _import("migen.build.platforms", platform_name)
platform_kwargs = dict((k, autotype(v)) for k, v in args.platform_option)
platform = platform_module.Platform(**platform_kwargs)
build_name = top_class.__name__.lower() + "_" + platform_name
top_kwargs = dict((k, autotype(v)) for k, v in args.target_option)
soc = top_class(platform, **top_kwargs)
soc.finalize()
try:
memory_regions = soc.get_memory_regions()
csr_regions = soc.get_csr_regions()
csr_constants = soc.get_constants()
except:
pass
# decode actions
action_list = ["clean", "build-csr-csv", "build-core", "build-bitstream", "load-bitstream", "all"]
actions = {k: False for k in action_list}
for action in args.action:
if action in actions:
actions[action] = True
else:
print("Unknown action: "+action+". Valid actions are:")
for a in action_list:
print(" "+a)
sys.exit(1)
print("""
__ _ __ ____
/ / (_) /____ / __/______ ___ ___
/ /__/ / __/ -_)\ \/ __/ _ \/ _ \/ -_)
/____/_/\__/\__/___/\__/\___/ .__/\__/
/_/
A small footprint and configurable embedded FPGA
logic analyzer core powered by LiteX
====== Building parameters: ======""")
if hasattr(soc, "io"):
print("""
LiteScopeIO
-----------
Width: {}
""".format(soc.io.data_width)
)
if hasattr(soc, "analyzer"):
print("""
LiteScopeAnalyzer
-----------------
Width: {}
Depth: {}
===============================""".format(
soc.analyzer.data_width,
soc.analyzer.depth
)
)
# dependencies
if actions["all"]:
actions["build-csr-csv"] = True
actions["build-bitstream"] = True
actions["load-bitstream"] = True
if actions["build-bitstream"]:
actions["build-csr-csv"] = True
if actions["clean"]:
subprocess.call(["rm", "-rf", "build/*"])
if actions["build-csr-csv"]:
csr_csv = cpu_interface.get_csr_csv(csr_regions, csr_constants)
write_to_file(args.csr_csv, csr_csv)
if actions["build-core"]:
soc_fragment = soc.get_fragment()
platform.finalize(soc_fragment)
v_output = platform.get_verilog(soc_fragment, name="litescope",
special_overrides=xilinx_special_overrides)
if not os.path.exists("build"):
os.makedirs("build")
v_output.write("build/litescope.v")
if actions["build-bitstream"]:
build_kwargs = dict((k, autotype(v)) for k, v in args.build_option)
vns = platform.build(soc, build_name=build_name, **build_kwargs)
if hasattr(soc, "do_exit") and vns is not None:
if hasattr(soc.do_exit, '__call__'):
soc.do_exit(vns)
if actions["load-bitstream"]:
prog = platform.create_programmer()
prog.load_bitstream("build/" + build_name + platform.bitstream_ext)
| [
"litex.build.tools.write_to_file",
"litex.soc.integration.cpu_interface.get_csr_csv"
] | [((546, 591), 'importlib.import_module', 'importlib.import_module', (["(default + '.' + name)"], {}), "(default + '.' + name)\n", (569, 591), False, 'import importlib\n'), ((624, 1165), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'formatter_class': 'argparse.RawDescriptionHelpFormatter', 'description': '"""LiteScope - based on Migen.\n\nThis program builds and/or loads LiteScope components.\nOne or several actions can be specified:\n\nclean delete previous build(s).\nbuild-core build verilog core.\nbuild-bitstream build-bitstream build FPGA bitstream.\nbuild-csr-csv save CSR map into CSV file.\n\nload-bitstream load bitstream into volatile storage.\n\nall clean, build-csr-csv, build-bitstream, load-bitstream.\n"""'}), '(formatter_class=argparse.\n RawDescriptionHelpFormatter, description=\n """LiteScope - based on Migen.\n\nThis program builds and/or loads LiteScope components.\nOne or several actions can be specified:\n\nclean delete previous build(s).\nbuild-core build verilog core.\nbuild-bitstream build-bitstream build FPGA bitstream.\nbuild-csr-csv save CSR map into CSV file.\n\nload-bitstream load bitstream into volatile storage.\n\nall clean, build-csr-csv, build-bitstream, load-bitstream.\n"""\n )\n', (647, 1165), False, 'import argparse\n'), ((4822, 4863), 'subprocess.call', 'subprocess.call', (["['rm', '-rf', 'build/*']"], {}), "(['rm', '-rf', 'build/*'])\n", (4837, 4863), False, 'import subprocess\n'), ((4916, 4969), 'litex.soc.integration.cpu_interface.get_csr_csv', 'cpu_interface.get_csr_csv', (['csr_regions', 'csr_constants'], {}), '(csr_regions, csr_constants)\n', (4941, 4969), False, 'from litex.soc.integration import cpu_interface\n'), ((4978, 5014), 'litex.build.tools.write_to_file', 'write_to_file', (['args.csr_csv', 'csr_csv'], {}), '(args.csr_csv, csr_csv)\n', (4991, 5014), False, 'from litex.build.tools import write_to_file\n'), ((3889, 3900), 'sys.exit', 'sys.exit', (['(1)'], {}), '(1)\n', (3897, 3900), False, 'import sys\n'), ((5271, 5294), 'os.path.exists', 'os.path.exists', (['"""build"""'], {}), "('build')\n", (5285, 5294), False, 'import os\n'), ((5308, 5328), 'os.makedirs', 'os.makedirs', (['"""build"""'], {}), "('build')\n", (5319, 5328), False, 'import os\n')] |
#!/usr/bin/python3
from litex.build.tools import write_to_file
from litex.build.tools import replace_in_file
from litedram.gen import *
import subprocess
import os
import shutil
def make_new_dir(base, added):
r = os.path.join(base, added)
if os.path.exists(r):
shutil.rmtree(r)
os.mkdir(r)
return r
gen_src_dir = os.path.dirname(os.path.realpath(__file__))
base_dir = os.path.normpath(os.path.join(gen_src_dir, os.pardir))
build_top_dir = make_new_dir(base_dir, "build")
gen_src_dir = os.path.join(base_dir, "gen-src")
gen_dir = make_new_dir(base_dir, "generated")
# Build the init code for microwatt-initialized DRAM
def build_init_code(build_dir, is_sim):
# More path fudging
sw_dir = os.path.join(build_dir, "software");
sw_inc_dir = os.path.join(sw_dir, "include")
gen_inc_dir = os.path.join(sw_inc_dir, "generated")
src_dir = os.path.join(gen_src_dir, "sdram_init")
lxbios_src_dir = os.path.join(soc_directory, "software")
print(" sw dir:", sw_dir)
print("gen_inc_dir:", gen_inc_dir)
print(" src dir:", src_dir)
print(" lx src dir:", lxbios_src_dir)
# Generate mem.h (hard wire size, it's not important)
mem_h = "#define MAIN_RAM_BASE 0x40000000UL\n#define MAIN_RAM_SIZE 0x10000000UL\n"
write_to_file(os.path.join(gen_inc_dir, "mem.h"), mem_h)
# Environment
env_vars = []
def _makefile_escape(s): # From LiteX
return s.replace("\\", "\\\\")
def add_var(k, v):
env_vars.append("{}={}\n".format(k, _makefile_escape(v)))
makefile = os.path.join(src_dir, "Makefile")
cmd = ["make", "-C", build_dir, "-f", makefile]
cmd.append("BUILD_DIR=%s" % sw_dir)
cmd.append("SRC_DIR=%s" % src_dir)
cmd.append("GENINC_DIR=%s" % sw_inc_dir)
cmd.append("LXSRC_DIR=%s" % lxbios_src_dir)
if is_sim:
cmd.append("EXTRA_CFLAGS=%s" % "-D__SIM__")
# Build init code
print(" Generating init software...")
r = subprocess.check_call(cmd)
print("Make result:", r)
return os.path.join(sw_dir, "obj", "sdram_init.hex")
def generate_one(t):
print("Generating target:", t)
# Is it a simulation ?
is_sim = "sim" in t
# Muck with directory path
build_dir = make_new_dir(build_top_dir, t)
t_dir = make_new_dir(gen_dir, t)
cmd = ["litedram_gen", "--output-dir=%s" % build_dir]
if is_sim:
cmd.append("--sim")
cmd.append("%s.yml" % t)
subprocess.check_call(cmd)
# Grab generated gatewar dir
gw_dir = os.path.join(build_dir, "gateware")
# Generate init code
src_init_file = build_init_code(build_dir, is_sim)
src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
# Copy generated files to target dir, amend them if necessary
initfile_name = "litedram_core.init"
core_file = os.path.join(gw_dir, "litedram_core.v")
dst_init_file = os.path.join(t_dir, initfile_name)
dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
shutil.copyfile(src_init_file, dst_init_file)
shutil.copyfile(src_initram_file, dst_initram_file)
if is_sim:
initfile_path = os.path.join("litedram", "generated", "sim", initfile_name)
replace_in_file(dst_initram_file, initfile_name, initfile_path)
shutil.copy(core_file, t_dir)
def main():
targets = ['arty','nexys-video', 'genesys2', 'acorn-cle-215', 'wukong-v2', 'orangecrab-85-0.2', 'sim']
for t in targets:
generate_one(t)
if __name__ == "__main__":
main()
| [
"litex.build.tools.replace_in_file"
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#!/usr/bin/env python3
'''
---------------------
LiteX SoC on Marble
---------------------
with support for SO-DIMM DDR3, ethernet and UART.
To synthesize, add --build, to configure the FPGA over jtag, add --load.
-----------------
Example configs
-----------------
with ethernet and DDR3, default IP: 192.168.1.50/24
./marble.py --with-ethernet --with-bist --spd-dump VR7PU286458FBAMJT.txt
lightweight config
./marble.py --integrated-main-ram-size 16384 --cpu-type serv
etherbone: access wishbone over ethernet
./marble.py --with-etherbone --csr-csv build/csr.csv
make sure reset is not asserted (RTS signal), set PC IP to 192.168.1.100/24,
then test and benchmark the etherbone link:
cd build
litex/liteeth/bench/test_etherbone.py --udp --ident --access --sram --speed
'''
from migen import *
from litex_boards.platforms import berkeleylab_marble
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster
from litedram.modules import MT8JTF12864, parse_spd_hexdump, SDRAMModule
from litedram.phy import s7ddrphy
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, resets=[]):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain()
self.clock_domains.cd_sys4x_dqs = ClockDomain()
self.clock_domains.cd_idelay = ClockDomain()
# # #
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
resets.append(self.rst)
self.comb += pll.reset.eq(reduce(or_, resets))
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(125e6),
with_ethernet = False,
with_etherbone = False,
with_rts_reset = False,
with_led_chaser = True,
spd_dump = None,
**kwargs
):
platform = berkeleylab_marble.Platform()
# CRG, resettable over USB serial RTS signal -----------------------------------------------
resets = []
if with_rts_reset:
ser_pads = platform.lookup_request('serial')
resets.append(ser_pads.rts)
self.submodules.crg = _CRG(platform, sys_clk_freq, resets)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Berkeley-Lab Marble", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(
platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq
)
if spd_dump is not None:
ram_spd = parse_spd_hexdump(spd_dump)
ram_module = SDRAMModule.from_spd_data(ram_spd, sys_clk_freq)
print('DDR3: loaded config from', spd_dump)
else:
ram_module = MT8JTF12864(sys_clk_freq, "1:4") # KC705 chip, 1 GB
print('DDR3: No spd data specified, falling back to MT8JTF12864')
self.add_sdram("sdram",
phy = self.ddrphy,
module = ram_module,
# size=0x40000000, # Limit its size to 1 GB
l2_cache_size = kwargs.get("l2_size", 8192),
with_bist = kwargs.get("with_bist", False)
)
# Ethernet ---------------------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
tx_delay = 0
)
if with_ethernet:
self.add_ethernet(
phy = self.ethphy,
dynamic_ip = True,
software_debug = False
)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, buffer_depth=255)
# System I2C (behing multiplexer) ----------------------------------------------------------
i2c_pads = platform.request('i2c_fpga')
self.submodules.i2c = I2CMaster(i2c_pads)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on BerkeleyLab Marble")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.")
target_group.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
target_group.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--with-rts-reset", action="store_true", help="Connect UART RTS line to sys_clk reset.")
target_group.add_argument("--with-bist", action="store_true", help="Add DDR3 BIST Generator/Checker.")
target_group.add_argument("--spd-dump", type=str, help="DDR3 configuration file, dumped using the `spdread` command in LiteX BIOS.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_bist = args.with_bist,
spd_dump = args.spd_dump,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()
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"litex.soc.cores.bitbang.I2CMaster",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((5686, 5755), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on BerkeleyLab Marble"""'}), "(description='LiteX SoC on BerkeleyLab Marble')\n", (5708, 5755), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((2694, 2723), 'litex_boards.platforms.berkeleylab_marble.Platform', 'berkeleylab_marble.Platform', ([], {}), '()\n', (2721, 2723), False, 'from litex_boards.platforms import berkeleylab_marble\n'), ((5187, 5206), 'litex.soc.cores.bitbang.I2CMaster', 'I2CMaster', (['i2c_pads'], {}), '(i2c_pads)\n', (5196, 5206), False, 'from litex.soc.cores.bitbang import I2CMaster\n'), ((3688, 3715), 'litedram.modules.parse_spd_hexdump', 'parse_spd_hexdump', (['spd_dump'], {}), '(spd_dump)\n', (3705, 3715), False, 'from litedram.modules import MT8JTF12864, parse_spd_hexdump, SDRAMModule\n'), ((3745, 3793), 'litedram.modules.SDRAMModule.from_spd_data', 'SDRAMModule.from_spd_data', (['ram_spd', 'sys_clk_freq'], {}), '(ram_spd, sys_clk_freq)\n', (3770, 3793), False, 'from litedram.modules import MT8JTF12864, parse_spd_hexdump, SDRAMModule\n'), ((3901, 3933), 'litedram.modules.MT8JTF12864', 'MT8JTF12864', (['sys_clk_freq', '"""1:4"""'], {}), "(sys_clk_freq, '1:4')\n", (3912, 3933), False, 'from litedram.modules import MT8JTF12864, parse_spd_hexdump, SDRAMModule\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
import argparse
import sys
import socket
import time
import threading
from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites
from litex.tools.remote.etherbone import EtherboneIPC
class RemoteServer(EtherboneIPC):
def __init__(self, comm, bind_ip, bind_port=1234):
self.comm = comm
self.bind_ip = bind_ip
self.bind_port = bind_port
self.lock = False
def open(self):
if hasattr(self, "socket"):
return
socket_flags = 0
if hasattr(socket, "SO_REUSEADDR"):
socket_flags = socket_flags | socket.SO_REUSEADDR
if hasattr(socket, "SO_REUSEPORT"):
socket_flags = socket_flags | socket.SO_REUSEPORT
self.socket = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
self.socket.setsockopt(socket.SOL_SOCKET, socket_flags, 1)
self.socket.bind((self.bind_ip, self.bind_port))
print("tcp port: {:d}".format(self.bind_port))
self.socket.listen(1)
self.comm.open()
def close(self):
self.comm.close()
if not hasattr(self, "socket"):
return
self.socket.close()
del self.socket
def _serve_thread(self):
while True:
client_socket, addr = self.socket.accept()
print("Connected with " + addr[0] + ":" + str(addr[1]))
try:
while True:
try:
packet = self.receive_packet(client_socket)
if packet == 0:
break
except:
break
packet = EtherbonePacket(packet)
packet.decode()
record = packet.records.pop()
# wait for lock
while self.lock:
time.sleep(0.01)
# set lock
self.lock = True
# handle writes:
if record.writes != None:
self.comm.write(record.writes.base_addr, record.writes.get_datas())
# handle reads
if record.reads != None:
reads = []
for addr in record.reads.get_addrs():
reads.append(self.comm.read(addr))
record = EtherboneRecord()
record.writes = EtherboneWrites(datas=reads)
record.wcount = len(record.writes)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
self.send_packet(client_socket, packet)
# release lock
self.lock = False
finally:
print("Disconnect")
client_socket.close()
def start(self, nthreads):
for i in range(nthreads):
self.serve_thread = threading.Thread(target=self._serve_thread)
self.serve_thread.setDaemon(True)
self.serve_thread.start()
def main():
print("LiteX remote server")
parser = argparse.ArgumentParser()
# Common arguments
parser.add_argument("--bind-ip", default="localhost",
help="Host bind address")
parser.add_argument("--bind-port", default=1234,
help="Host bind port")
# UART arguments
parser.add_argument("--uart", action="store_true",
help="Select UART interface")
parser.add_argument("--uart-port", default=None,
help="Set UART port")
parser.add_argument("--uart-baudrate", default=115200,
help="Set UART baudrate")
# UDP arguments
parser.add_argument("--udp", action="store_true",
help="Select UDP interface")
parser.add_argument("--udp-ip", default="192.168.1.50",
help="Set UDP remote IP address")
parser.add_argument("--udp-port", default=1234,
help="Set UDP remote port")
# PCIe arguments
parser.add_argument("--pcie", action="store_true",
help="Select PCIe interface")
parser.add_argument("--pcie-bar", default=None,
help="Set PCIe BAR")
# USB arguments
parser.add_argument("--usb", action="store_true",
help="Select USB interface")
parser.add_argument("--usb-vid", default=None,
help="Set USB vendor ID")
parser.add_argument("--usb-pid", default=None,
help="Set USB product ID")
parser.add_argument("--usb-max-retries", default=10,
help="Number of times to try reconnecting to USB")
args = parser.parse_args()
if args.uart:
from litex.tools.remote.comm_uart import CommUART
if args.uart_port is None:
print("Need to specify --uart-port, exiting.")
exit()
uart_port = args.uart_port
uart_baudrate = int(float(args.uart_baudrate))
print("[CommUART] port: {} / baudrate: {} / ".format(uart_port, uart_baudrate), end="")
comm = CommUART(uart_port, uart_baudrate)
elif args.udp:
from litex.tools.remote.comm_udp import CommUDP
udp_ip = args.udp_ip
udp_port = int(args.udp_port)
print("[CommUDP] ip: {} / port: {} / ".format(udp_ip, udp_port), end="")
comm = CommUDP(udp_ip, udp_port)
elif args.pcie:
from litex.tools.remote.comm_pcie import CommPCIe
pcie_bar = args.pcie_bar
if args.pcie_bar is None:
print("Need to speficy --pcie-bar, exiting.")
exit()
print("[CommPCIe] bar: {} / ".format(args.pcie_bar), end="")
comm = CommPCIe(args.pcie_bar)
elif args.usb:
from litex.tools.remote.comm_usb import CommUSB
if args.usb_pid is None and args.usb_vid is None:
print("Need to speficy --usb-vid or --usb-pid, exiting.")
exit()
print("[CommUSB] vid: {} / pid: {} / ".format(args.usb_vid, args.usb_pid), end="")
pid = args.usb_pid
if pid is not None:
pid = int(pid, base=0)
vid = args.usb_vid
if vid is not None:
vid = int(vid, base=0)
comm = CommUSB(vid=vid, pid=pid, max_retries=args.usb_max_retries)
else:
parser.print_help()
exit()
server = RemoteServer(comm, args.bind_ip, int(args.bind_port))
server.open()
server.start(4)
try:
import time
while True: time.sleep(100)
except KeyboardInterrupt:
pass
if __name__ == "__main__":
main()
| [
"litex.tools.remote.comm_uart.CommUART",
"litex.tools.remote.comm_pcie.CommPCIe",
"litex.tools.remote.comm_usb.CommUSB",
"litex.tools.remote.comm_udp.CommUDP",
"litex.tools.remote.etherbone.EtherboneWrites",
"litex.tools.remote.etherbone.EtherbonePacket",
"litex.tools.remote.etherbone.EtherboneRecord"
] | [((3427, 3452), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (3450, 3452), False, 'import argparse\n'), ((958, 1007), 'socket.socket', 'socket.socket', (['socket.AF_INET', 'socket.SOCK_STREAM'], {}), '(socket.AF_INET, socket.SOCK_STREAM)\n', (971, 1007), False, 'import socket\n'), ((5487, 5521), 'litex.tools.remote.comm_uart.CommUART', 'CommUART', (['uart_port', 'uart_baudrate'], {}), '(uart_port, uart_baudrate)\n', (5495, 5521), False, 'from litex.tools.remote.comm_uart import CommUART\n'), ((3239, 3282), 'threading.Thread', 'threading.Thread', ([], {'target': 'self._serve_thread'}), '(target=self._serve_thread)\n', (3255, 3282), False, 'import threading\n'), ((5760, 5785), 'litex.tools.remote.comm_udp.CommUDP', 'CommUDP', (['udp_ip', 'udp_port'], {}), '(udp_ip, udp_port)\n', (5767, 5785), False, 'from litex.tools.remote.comm_udp import CommUDP\n'), ((6892, 6907), 'time.sleep', 'time.sleep', (['(100)'], {}), '(100)\n', (6902, 6907), False, 'import time\n'), ((6092, 6115), 'litex.tools.remote.comm_pcie.CommPCIe', 'CommPCIe', (['args.pcie_bar'], {}), '(args.pcie_bar)\n', (6100, 6115), False, 'from litex.tools.remote.comm_pcie import CommPCIe\n'), ((1873, 1896), 'litex.tools.remote.etherbone.EtherbonePacket', 'EtherbonePacket', (['packet'], {}), '(packet)\n', (1888, 1896), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites\n'), ((6624, 6683), 'litex.tools.remote.comm_usb.CommUSB', 'CommUSB', ([], {'vid': 'vid', 'pid': 'pid', 'max_retries': 'args.usb_max_retries'}), '(vid=vid, pid=pid, max_retries=args.usb_max_retries)\n', (6631, 6683), False, 'from litex.tools.remote.comm_usb import CommUSB\n'), ((2082, 2098), 'time.sleep', 'time.sleep', (['(0.01)'], {}), '(0.01)\n', (2092, 2098), False, 'import time\n'), ((2619, 2636), 'litex.tools.remote.etherbone.EtherboneRecord', 'EtherboneRecord', ([], {}), '()\n', (2634, 2636), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites\n'), ((2677, 2705), 'litex.tools.remote.etherbone.EtherboneWrites', 'EtherboneWrites', ([], {'datas': 'reads'}), '(datas=reads)\n', (2692, 2705), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites\n'), ((2799, 2816), 'litex.tools.remote.etherbone.EtherbonePacket', 'EtherbonePacket', ([], {}), '()\n', (2814, 2816), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord, EtherboneWrites\n')] |
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import IceStormProgrammer
_io = [
("rgb_led", 0,
Subsignal("r", Pins("41")),
Subsignal("g", Pins("40")),
Subsignal("b", Pins("39")),
IOStandard("LVCMOS33")
),
("user_sw", 0, Pins("23"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("25"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("34"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("43"), IOStandard("LVCMOS33")),
("clk12", 0, Pins("35"), IOStandard("LVCMOS33"))
]
spiflash = [
# Only usable in PROG FLASH mode and J7 attached (see PCB silkscreen).
("spiflash", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
),
]
# The ICE40UP5K-B-EVN does not use the provided FT2232H chip to provide a
# UART port. One must use their own USB-to-serial cable instead to get a UART.
# We have chosen to use 48B and 51A for "tx" and "rx" respectively on Header B
# to implement UART connections. The board comes unpopulated and will need to
# have headers soldered.
serial = [
("serial", 0,
Subsignal("tx", Pins("J2:3")),
Subsignal("rx", Pins("J2:5")),
IOStandard("LVCMOS33")
)
]
_connectors = [
# Many pins on the AARDVARK, PMOD, J52/HEADER A, and J2/HEADER B connectors
# are multiplexed with other I/O or connector pins. For completeness, all
# pins are exposed here except Vdd, NC, and GND. Pin order is as specified
# on the schematic (except for PMOD, which uses Digilent's numbering).
# AARDVARK connector omitted- although sysCONFIG pins are exposed on this
# header (which can be used as GPIO), it is meant for flashing using an
# external programmer rather than as an I/O port.
# PMOD connector shares pins with sysCONFIG- make sure to remove jumper
# J7 if using the PMOD. TODO: Perhaps it would be better to split into two
# single 6-pin PMODs.
#
# PMOD pinout (using ICE40 pin names):
# 1, 2, 3, 4- SPI_SS, SPI_SI, SPI_SO, SPI_SCK
# 5, 6, 7, 8- Free
("PMOD", "16 17 14 15 27 26 32 31"),
# J52 exposes LEDs and sysCONFIG pins (yet again). Make sure to remove
# jumper J7 if using the PMOD. Pin order is as follows (right to left):
# 12 10 8 6 4 2
# 11 9 7 5 3 1
#
# J52's pinout (using ICE40 pin names for SPI flash):
# 1, 2- Vdd
# 3, 4- rgb_led.b, SPI_SI
# 5, 6- rgb_led.g, SPI_SO
# 7, 8- GND, SPI_SCK
# 9, 10- rgb_led.r, SPI_SS
# 11, 12- GND
# 3 4 5 6 8 9 10
("J52", "39 17 40 14 15 41 16"),
# Pin order of J2, and J3 are as follows (left to right/top to bottom):
# 2 4 6 8 10 12 14 16 18 20
# 1 3 5 7 9 11 13 15 17 19
#
# J2's pinout is shared by many things. Entire pinout listed follows:
# 1, 2- Vdd
# 3, 4- user_sw0, NC
# 5, 6- user_sw1, NC
# 7, 8- PMOD D5, Free
# 9, 10- PMOD D4, Free
# 11, 12- PMOD D6, Free
# 13, 14- PMOD D7, Free
# 15, 16- Free, 12.00 clock
# 17, 18- user_sw2, GND
# 19, 20- user_sw3, GND
# 3 5 7 8 9 10 11 12 13 14 15 16 17 19
("J2", "23 25 26 36 27 42 32 38 31 28 37 35 34 43"),
# Bank2: 4 3 48 45 47 44 46 2
# Bank1: 12 21 13 20 19 18 11 10 9 6
# J3's pinout is all Free, except 1 (Vdd) and 19 (GND).
# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20
("J3", "12 4 21 3 13 48 20 45 19 47 18 44 11 46 10 2 9 6"),
]
class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 83.333
gateware_size = 0x20000
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
spiflash_model = "n25q32"
spiflash_read_dummy_bits = 8
spiflash_clock_div = 2
spiflash_total_size = int((32/8)*1024*1024) # 32Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
def __init__(self):
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors,
toolchain="icestorm")
def create_programmer(self):
return IceStormProgrammer()
| [
"litex.build.lattice.programmer.IceStormProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((4137, 4230), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-sg48', _io, _connectors,\n toolchain='icestorm')\n", (4161, 4230), False, 'from litex.build.lattice import LatticePlatform\n'), ((4309, 4329), 'litex.build.lattice.programmer.IceStormProgrammer', 'IceStormProgrammer', ([], {}), '()\n', (4327, 4329), False, 'from litex.build.lattice.programmer import IceStormProgrammer\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import quicklogic_quickfeather
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.gpio import *
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, with_eos_s3=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
if with_eos_s3:
# Use clocks generated by the EOS-S3 CPU.
self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0"))
self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst)
else:
# Use clocks generated by the qlal4s3b_cell_macro.
class Open(Signal): pass
self.specials += Instance("qlal4s3b_cell_macro",
o_Sys_Clk0 = self.cd_sys.clk,
o_Sys_Clk0_Rst = self.cd_sys.rst,
o_Sys_Clk1 = Open(),
o_Sys_Clk1_Rst = Open(),
)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(10e6), with_led_chaser=True, with_gpio_in=True, **kwargs):
platform = quicklogic_quickfeather.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["with_uart"] = False
if kwargs.get("cpu_type", None) == "eos_s3":
kwargs['integrated_sram_size'] = 0
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on QuickLogic QuickFeather",
**kwargs)
if kwargs.get("cpu_type", None) == "eos_s3":
# in fact SRAM starts at 0x2000_0000 - but for some reason
# this does not work and most QORC SDK linker scripts
# use 0x2002_7000 + 0x0003_c800
self.bus.add_region("sram", SoCRegion(
origin=0x2002_7000,
size=0x0003_c800)
)
self.bus.add_region("rom", SoCRegion(
origin=self.mem_map["rom"],
size=4 * 128 * 1024,
linker=True)
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, with_eos_s3=kwargs["cpu_type"] == "eos_s3")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# GPIOIn (Interrupt test) ------------------------------------------------------------------
if with_gpio_in:
self.submodules.gpio = GPIOIn(platform.request_all("user_btn_n"), with_irq=True)
if kwargs["cpu_type"] == "eos_s3":
self.irq.add("gpio", use_loc_if_exists=True)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on QuickLogic QuickFeather")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
soc_core_args(parser)
parser.set_defaults(cpu_type="eos_s3")
args = parser.parse_args()
soc = BaseSoC(**soc_core_argdict(args))
builder = Builder(soc)
if args.cpu_type == "eos_s3":
if not os.path.exists("libeos"):
os.system("wget https://github.com/litex-hub/litex-boards/files/7880350/libeos.zip")
os.system("unzip libeos.zip -d libeos")
builder.add_software_package("libeos", src_dir="libeos")
builder.add_software_library("libeos")
builder.build(run=args.build)
if __name__ == "__main__":
main()
| [
"litex.soc.integration.soc.SoCRegion"
] | [((3511, 3586), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on QuickLogic QuickFeather"""'}), "(description='LiteX SoC on QuickLogic QuickFeather')\n", (3534, 3586), False, 'import argparse\n'), ((1623, 1657), 'litex_boards.platforms.quicklogic_quickfeather.Platform', 'quicklogic_quickfeather.Platform', ([], {}), '()\n', (1655, 1657), False, 'from litex_boards.platforms import quicklogic_quickfeather\n'), ((3889, 3913), 'os.path.exists', 'os.path.exists', (['"""libeos"""'], {}), "('libeos')\n", (3903, 3913), False, 'import os\n'), ((3927, 4016), 'os.system', 'os.system', (['"""wget https://github.com/litex-hub/litex-boards/files/7880350/libeos.zip"""'], {}), "(\n 'wget https://github.com/litex-hub/litex-boards/files/7880350/libeos.zip')\n", (3936, 4016), False, 'import os\n'), ((4024, 4063), 'os.system', 'os.system', (['"""unzip libeos.zip -d libeos"""'], {}), "('unzip libeos.zip -d libeos')\n", (4033, 4063), False, 'import os\n'), ((2309, 2349), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(537030656)', 'size': '(247808)'}), '(origin=537030656, size=247808)\n', (2318, 2349), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((2443, 2514), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': "self.mem_map['rom']", 'size': '(4 * 128 * 1024)', 'linker': '(True)'}), "(origin=self.mem_map['rom'], size=4 * 128 * 1024, linker=True)\n", (2452, 2514), False, 'from litex.soc.integration.soc import SoCRegion\n')] |
#
# This file is part of LiteX.
#
# This file is Copyright (c) 2014-2021 <NAME> <<EMAIL>>
# This file is Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import time
import logging
import datetime
from math import log2, ceil
from migen import *
from litex.soc.cores import cpu
from litex.soc.interconnect.csr import *
from litex.soc.interconnect.csr_eventmanager import *
from litex.soc.interconnect import csr_bus
from litex.soc.interconnect import stream
from litex.soc.interconnect import wishbone
from litex.soc.interconnect import axi
logging.basicConfig(level=logging.INFO)
# Helpers ------------------------------------------------------------------------------------------
def auto_int(x):
return int(x, 0)
def colorer(s, color="bright"):
header = {
"bright": "\x1b[1m",
"green": "\x1b[32m",
"cyan": "\x1b[36m",
"red": "\x1b[31m",
"yellow": "\x1b[33m",
"underline": "\x1b[4m"}[color]
trailer = "\x1b[0m"
return header + str(s) + trailer
def build_time(with_time=True):
fmt = "%Y-%m-%d %H:%M:%S" if with_time else "%Y-%m-%d"
return datetime.datetime.fromtimestamp(time.time()).strftime(fmt)
# SoCError -----------------------------------------------------------------------------------------
class SoCError(Exception):
def __init__(self):
sys.stderr = None # Error already described, avoid traceback/exception.
# SoCConstant --------------------------------------------------------------------------------------
def SoCConstant(value):
return value
# SoCRegion ----------------------------------------------------------------------------------------
class SoCRegion:
def __init__(self, origin=None, size=None, mode="rw", cached=True, linker=False):
self.logger = logging.getLogger("SoCRegion")
self.origin = origin
self.size = size
if size != 2**log2_int(size, False):
self.logger.info("Region size {} internally from {} to {}.".format(
colorer("rounded", color="cyan"),
colorer("0x{:08x}".format(size)),
colorer("0x{:08x}".format(2**log2_int(size, False)))))
self.size_pow2 = 2**log2_int(size, False)
self.mode = mode
self.cached = cached
self.linker = linker
def decoder(self, bus):
origin = self.origin
size = self.size_pow2
if (origin & (size - 1)) != 0:
self.logger.error("Origin needs to be aligned on size:")
self.logger.error(self)
raise SoCError()
if (origin == 0) and (size == 2**bus.address_width):
return lambda a : True
origin >>= int(log2(bus.data_width//8)) # bytes to words aligned.
size >>= int(log2(bus.data_width//8)) # bytes to words aligned.
return lambda a: (a[log2_int(size):] == (origin >> log2_int(size)))
def __str__(self):
r = ""
if self.origin is not None:
r += "Origin: {}, ".format(colorer("0x{:08x}".format(self.origin)))
if self.size is not None:
r += "Size: {}, ".format(colorer("0x{:08x}".format(self.size)))
r += "Mode: {}, ".format(colorer(self.mode.upper()))
r += "Cached: {} ".format(colorer(self.cached))
r += "Linker: {}".format(colorer(self.linker))
return r
class SoCIORegion(SoCRegion): pass
# SoCCSRRegion -------------------------------------------------------------------------------------
class SoCCSRRegion:
def __init__(self, origin, busword, obj):
self.origin = origin
self.busword = busword
self.obj = obj
# SoCBusHandler ------------------------------------------------------------------------------------
class SoCBusHandler(Module):
supported_standard = ["wishbone", "axi-lite"]
supported_data_width = [32, 64]
supported_address_width = [32]
# Creation -------------------------------------------------------------------------------------
def __init__(self, name="SoCBusHandler", standard="wishbone", data_width=32, address_width=32, timeout=1e6, reserved_regions={}):
self.logger = logging.getLogger(name)
self.logger.info("Creating Bus Handler...")
# Check Bus Standard.
if standard not in self.supported_standard:
self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
colorer("Bus standard", color="red"),
colorer(standard),
colorer(", ".join(self.supported_standard))))
raise SoCError()
# Check Bus Data Width.
if data_width not in self.supported_data_width:
self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
colorer("Data Width", color="red"),
colorer(data_width),
colorer(", ".join(str(x) for x in self.supported_data_width))))
raise SoCError()
# Check Bus Address Width.
if address_width not in self.supported_address_width:
self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
colorer("Address Width", color="red"),
colorer(address_width),
colorer(", ".join(str(x) for x in self.supported_address_width))))
raise SoCError()
# Create Bus
self.standard = standard
self.data_width = data_width
self.address_width = address_width
self.masters = {}
self.slaves = {}
self.regions = {}
self.io_regions = {}
self.timeout = timeout
self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
# Add reserved regions.
self.logger.info("Adding {} Bus Regions...".format(colorer("reserved", color="cyan")))
for name, region in reserved_regions.items():
if isinstance(region, int):
region = SoCRegion(origin=region, size=0x1000000)
self.add_region(name, region)
self.logger.info("Bus Handler {}.".format(colorer("created", color="green")))
# Add/Allog/Check Regions ----------------------------------------------------------------------
def add_region(self, name, region):
allocated = False
if name in self.regions.keys() or name in self.io_regions.keys():
self.logger.error("{} already declared as Region:".format(colorer(name, color="red")))
self.logger.error(self)
raise SoCError()
# Check if is SoCIORegion.
if isinstance(region, SoCIORegion):
self.io_regions[name] = region
# Check for overlap with others IO regions.
overlap = self.check_regions_overlap(self.io_regions)
if overlap is not None:
self.logger.error("IO Region {} between {} and {}:".format(
colorer("overlap", color="red"),
colorer(overlap[0]),
colorer(overlap[1])))
self.logger.error(str(self.io_regions[overlap[0]]))
self.logger.error(str(self.io_regions[overlap[1]]))
raise SoCError()
self.logger.info("{} Region {} at {}.".format(
colorer(name, color="underline"),
colorer("added", color="green"),
str(region)))
# Check if is SoCRegion
elif isinstance(region, SoCRegion):
# If no Origin specified, allocate Region.
if region.origin is None:
allocated = True
region = self.alloc_region(name, region.size, region.cached)
self.regions[name] = region
# Else add Region.
else:
# If Region is an IO Region is not cached.
if not region.cached:
if not self.check_region_is_io(region):
self.logger.error("{} Region {}: {}.".format(
colorer(name),
colorer("not in IO region", color="red"),
str(region)))
self.logger.error(self)
raise SoCError()
self.regions[name] = region
# Check for overlab with others IO regions.
overlap = self.check_regions_overlap(self.regions)
if overlap is not None:
self.logger.error("Region {} between {} and {}:".format(
colorer("overlap", color="red"),
colorer(overlap[0]),
colorer(overlap[1])))
self.logger.error(str(self.regions[overlap[0]]))
self.logger.error(str(self.regions[overlap[1]]))
raise SoCError()
self.logger.info("{} Region {} at {}.".format(
colorer(name, color="underline"),
colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
str(region)))
else:
self.logger.error("{} is not a supported Region.".format(colorer(name, color="red")))
raise SoCError()
def alloc_region(self, name, size, cached=True):
self.logger.info("Allocating {} Region of size {}...".format(
colorer("Cached" if cached else "IO"),
colorer("0x{:08x}".format(size))))
# Limit Search Regions.
if cached == False:
search_regions = self.io_regions
else:
search_regions = {"main": SoCRegion(origin=0x00000000, size=2**self.address_width-1)}
# Iterate on Search_Regions to find a Candidate.
for _, search_region in search_regions.items():
origin = search_region.origin
while (origin + size) < (search_region.origin + search_region.size_pow2):
# Align Origin on Size.
if (origin%size):
origin += (origin - origin%size)
continue
# Create a Candidate.
candidate = SoCRegion(origin=origin, size=size, cached=cached)
overlap = False
# Check Candidate does not overlap with allocated existing regions.
for _, allocated in self.regions.items():
if self.check_regions_overlap({"0": allocated, "1": candidate}) is not None:
origin += size
overlap = True
break
if not overlap:
# If no overlap, the Candidate is selected.
return candidate
self.logger.error("Not enough Address Space to allocate Region.")
raise SoCError()
def check_regions_overlap(self, regions, check_linker=False):
i = 0
while i < len(regions):
n0 = list(regions.keys())[i]
r0 = regions[n0]
for n1 in list(regions.keys())[i+1:]:
r1 = regions[n1]
if r0.linker or r1.linker:
if not check_linker:
continue
if r0.origin >= (r1.origin + r1.size_pow2):
continue
if r1.origin >= (r0.origin + r0.size_pow2):
continue
return (n0, n1)
i += 1
return None
def check_region_is_in(self, region, container):
is_in = True
if not (region.origin >= container.origin):
is_in = False
if not ((region.origin + region.size) < (container.origin + container.size)):
is_in = False
return is_in
def check_region_is_io(self, region):
is_io = False
for _, io_region in self.io_regions.items():
if self.check_region_is_in(region, io_region):
is_io = True
return is_io
# Add Master/Slave -----------------------------------------------------------------------------
def add_adapter(self, name, interface, direction="m2s"):
assert direction in ["m2s", "s2m"]
# Data width conversion.
if interface.data_width != self.data_width:
interface_cls = type(interface)
converter_cls = {
wishbone.Interface: wishbone.Converter,
axi.AXILiteInterface: axi.AXILiteConverter,
}[interface_cls]
converted_interface = interface_cls(data_width=self.data_width)
if direction == "m2s":
master, slave = interface, converted_interface
elif direction == "s2m":
master, slave = converted_interface, interface
converter = converter_cls(master=master, slave=slave)
self.submodules += converter
else:
converted_interface = interface
# Wishbone <-> AXILite bridging.
main_bus_cls = {
"wishbone": wishbone.Interface,
"axi-lite": axi.AXILiteInterface,
}[self.standard]
if isinstance(converted_interface, main_bus_cls):
bridged_interface = converted_interface
else:
bridged_interface = main_bus_cls(data_width=self.data_width)
if direction == "m2s":
master, slave = converted_interface, bridged_interface
elif direction == "s2m":
master, slave = bridged_interface, converted_interface
bridge_cls = {
(wishbone.Interface, axi.AXILiteInterface): axi.Wishbone2AXILite,
(axi.AXILiteInterface, wishbone.Interface): axi.AXILite2Wishbone,
}[type(master), type(slave)]
bridge = bridge_cls(master, slave)
self.submodules += bridge
if type(interface) != type(bridged_interface) or interface.data_width != bridged_interface.data_width:
fmt = "{name} Bus {converted} from {from_bus} {from_bits}-bit to {to_bus} {to_bits}-bit."
bus_names = {
wishbone.Interface: "Wishbone",
axi.AXILiteInterface: "AXI Lite",
}
self.logger.info(fmt.format(
name = colorer(name),
converted = colorer("converted", color="cyan"),
from_bus = colorer(bus_names[type(interface)]),
from_bits = colorer(interface.data_width),
to_bus = colorer(bus_names[type(bridged_interface)]),
to_bits = colorer(bridged_interface.data_width)))
return bridged_interface
def add_master(self, name=None, master=None):
if name is None:
name = "master{:d}".format(len(self.masters))
if name in self.masters.keys():
self.logger.error("{} {} as Bus Master:".format(
colorer(name),
colorer("already declared", color="red")))
self.logger.error(self)
raise SoCError()
master = self.add_adapter(name, master, "m2s")
self.masters[name] = master
self.logger.info("{} {} as Bus Master.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
def add_slave(self, name=None, slave=None, region=None):
no_name = name is None
no_region = region is None
if no_name and no_region:
self.logger.error("Please {} {} or/and {} of Bus Slave.".format(
colorer("specify", color="red"),
colorer("name"),
colorer("region")))
raise SoCError()
if no_name:
name = "slave{:d}".format(len(self.slaves))
if no_region:
region = self.regions.get(name, None)
if region is None:
self.logger.error("{} Region {}.".format(
colorer(name),
colorer("not found", color="red")))
raise SoCError()
else:
self.add_region(name, region)
if name in self.slaves.keys():
self.logger.error("{} {} as Bus Slave:".format(
colorer(name),
colorer("already declared", color="red")))
self.logger.error(self)
raise SoCError()
slave = self.add_adapter(name, slave, "s2m")
self.slaves[name] = slave
self.logger.info("{} {} as Bus Slave.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
# Str ------------------------------------------------------------------------------------------
def __str__(self):
r = "{}-bit {} Bus, {}GiB Address Space.\n".format(
colorer(self.data_width), colorer(self.standard), colorer(2**self.address_width/2**30))
r += "IO Regions: ({})\n".format(len(self.io_regions.keys())) if len(self.io_regions.keys()) else ""
io_regions = {k: v for k, v in sorted(self.io_regions.items(), key=lambda item: item[1].origin)}
for name, region in io_regions.items():
r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
r += "Bus Regions: ({})\n".format(len(self.regions.keys())) if len(self.regions.keys()) else ""
regions = {k: v for k, v in sorted(self.regions.items(), key=lambda item: item[1].origin)}
for name, region in regions.items():
r += colorer(name, color="underline") + " "*(20-len(name)) + ": " + str(region) + "\n"
r += "Bus Masters: ({})\n".format(len(self.masters.keys())) if len(self.masters.keys()) else ""
for name in self.masters.keys():
r += "- {}\n".format(colorer(name, color="underline"))
r += "Bus Slaves: ({})\n".format(len(self.slaves.keys())) if len(self.slaves.keys()) else ""
for name in self.slaves.keys():
r += "- {}\n".format(colorer(name, color="underline"))
r = r[:-1]
return r
# SoCLocHandler ------------------------------------------------------------------------------------
class SoCLocHandler(Module):
# Creation -------------------------------------------------------------------------------------
def __init__(self, name, n_locs):
self.name = name
self.locs = {}
self.n_locs = n_locs
# Add ------------------------------------------------------------------------------------------
def add(self, name, n=None, use_loc_if_exists=False):
allocated = False
if not (use_loc_if_exists and name in self.locs.keys()):
if name in self.locs.keys():
self.logger.error("{} {} name {}.".format(
colorer(name), self.name, colorer("already used", color="red")))
self.logger.error(self)
raise SoCError()
if n in self.locs.values():
self.logger.error("{} {} Location {}.".format(
colorer(n), self.name, colorer("already used", color="red")))
self.logger.error(self)
raise SoCError()
if n is None:
allocated = True
n = self.alloc(name)
else:
if n < 0:
self.logger.error("{} {} Location should be {}.".format(
colorer(n),
self.name,
colorer("positive", color="red")))
raise SoCError()
if n > self.n_locs:
self.logger.error("{} {} Location {} than maximum: {}.".format(
colorer(n),
self.name,
colorer("higher", color="red"),
colorer(self.n_locs)))
raise SoCError()
self.locs[name] = n
else:
n = self.locs[name]
self.logger.info("{} {} {} at Location {}.".format(
colorer(name, color="underline"),
self.name,
colorer("allocated" if allocated else "added", color="cyan" if allocated else "green"),
colorer(n)))
# Alloc ----------------------------------------------------------------------------------------
def alloc(self, name):
for n in range(self.n_locs):
if n not in self.locs.values():
return n
self.logger.error("Not enough Locations.")
self.logger.error(self)
raise SoCError()
# Str ------------------------------------------------------------------------------------------
def __str__(self):
r = "{} Locations: ({})\n".format(self.name, len(self.locs.keys())) if len(self.locs.keys()) else ""
locs = {k: v for k, v in sorted(self.locs.items(), key=lambda item: item[1])}
length = 0
for name in locs.keys():
if len(name) > length: length = len(name)
for name in locs.keys():
r += "- {}{}: {}\n".format(colorer(name, color="underline"), " "*(length + 1 - len(name)), colorer(self.locs[name]))
return r
# SoCCSRHandler ------------------------------------------------------------------------------------
class SoCCSRHandler(SoCLocHandler):
supported_data_width = [8, 32]
supported_address_width = [14+i for i in range(4)]
supported_alignment = [32]
supported_paging = [0x800*2**i for i in range(4)]
supported_ordering = ["big", "little"]
# Creation -------------------------------------------------------------------------------------
def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, ordering="big", reserved_csrs={}):
SoCLocHandler.__init__(self, "CSR", n_locs=alignment//8*(2**address_width)//paging)
self.logger = logging.getLogger("SoCCSRHandler")
self.logger.info("Creating CSR Handler...")
# Check CSR Data Width.
if data_width not in self.supported_data_width:
self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
colorer("Data Width", color="red"),
colorer(data_width),
colorer(", ".join(str(x) for x in self.supported_data_width))))
raise SoCError()
# Check CSR Address Width.
if address_width not in self.supported_address_width:
self.logger.error("Unsupported {} {} supporteds: {:s}".format(
colorer("Address Width", color="red"),
colorer(address_width),
colorer(", ".join(str(x) for x in self.supported_address_width))))
raise SoCError()
# Check CSR Alignment.
if alignment not in self.supported_alignment:
self.logger.error("Unsupported {}: {} supporteds: {:s}".format(
colorer("Alignment", color="red"),
colorer(alignment),
colorer(", ".join(str(x) for x in self.supported_alignment))))
raise SoCError()
if data_width > alignment:
self.logger.error("Alignment ({}) {} Data Width ({})".format(
colorer(alignment),
colorer("should be >=", color="red"),
colorer(data_width)))
raise SoCError()
# Check CSR Paging.
if paging not in self.supported_paging:
self.logger.error("Unsupported {} 0x{}, supporteds: {:s}".format(
colorer("Paging", color="red"),
colorer("{:x}".format(paging)),
colorer(", ".join("0x{:x}".format(x) for x in self.supported_paging))))
raise SoCError()
# Check CSR Ordering.
if ordering not in self.supported_ordering:
self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
colorer("Ordering", color="red"),
colorer("{}".format(paging)),
colorer(", ".join("{}".format(x) for x in self.supported_ordering))))
raise SoCError()
# Create CSR Handler.
self.data_width = data_width
self.address_width = address_width
self.alignment = alignment
self.paging = paging
self.ordering = ordering
self.masters = {}
self.regions = {}
self.logger.info("{}-bit CSR Bus, {}-bit Aligned, {}KiB Address Space, {}B Paging, {} Ordering (Up to {} Locations).".format(
colorer(self.data_width),
colorer(self.alignment),
colorer(2**self.address_width/2**10),
colorer(self.paging),
colorer(self.ordering),
colorer(self.n_locs)))
# Add reserved CSRs.
self.logger.info("Adding {} CSRs...".format(colorer("reserved", color="cyan")))
for name, n in reserved_csrs.items():
self.add(name, n)
self.logger.info("CSR Handler {}.".format(colorer("created", color="green")))
# Add Master -----------------------------------------------------------------------------------
def add_master(self, name=None, master=None):
if name is None:
name = "master{:d}".format(len(self.masters))
if name in self.masters.keys():
self.logger.error("{} {} as CSR Master:".format(
colorer(name),
colorer("already declared", color="red")))
self.logger.error(self)
raise SoCError()
if master.data_width != self.data_width:
self.logger.error("{} Master/Handler Data Width {} ({} vs {}).".format(
colorer(name),
colorer("missmatch", color="red"),
colorer(master.data_width),
colorer(self.data_width)))
raise SoCError()
self.masters[name] = master
self.logger.info("{} {} as CSR Master.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
# Add Region -----------------------------------------------------------------------------------
def add_region(self, name, region):
# FIXME: add checks
self.regions[name] = region
# Address map ----------------------------------------------------------------------------------
def address_map(self, name, memory):
if memory is not None:
name = name + "_" + memory.name_override
if self.locs.get(name, None) is None:
self.add(name, use_loc_if_exists=True)
return self.locs[name]
# Str ------------------------------------------------------------------------------------------
def __str__(self):
r = "{}-bit CSR Bus, {}-bit Aligned, {}KiB Address Space, {}B Paging, {} Ordering (Up to {} Locations).\n".format(
colorer(self.data_width),
colorer(self.alignment),
colorer(2**self.address_width/2**10),
colorer(self.paging),
colorer(self.ordering),
colorer(self.n_locs))
r += SoCLocHandler.__str__(self)
r = r[:-1]
return r
# SoCIRQHandler ------------------------------------------------------------------------------------
class SoCIRQHandler(SoCLocHandler):
# Creation -------------------------------------------------------------------------------------
def __init__(self, n_irqs=32, reserved_irqs={}):
SoCLocHandler.__init__(self, "IRQ", n_locs=n_irqs)
self.logger = logging.getLogger("SoCIRQHandler")
self.logger.info("Creating IRQ Handler...")
self.enabled = False
# Check IRQ Number.
if n_irqs > 32:
self.logger.error("Unsupported IRQs number: {} supporteds: {:s}".format(
colorer(n_irqs, color="red"), colorer("Up to 32", color="green")))
raise SoCError()
# Create IRQ Handler.
self.logger.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs)))
# Adding reserved IRQs.
self.logger.info("Adding {} IRQs...".format(colorer("reserved", color="cyan")))
for name, n in reserved_irqs.items():
self.add(name, n)
self.logger.info("IRQ Handler {}.".format(colorer("created", color="green")))
# Enable ---------------------------------------------------------------------------------------
def enable(self):
self.enabled = True
# Add ------------------------------------------------------------------------------------------
def add(self, name, *args, **kwargs):
if self.enabled:
SoCLocHandler.add(self, name, *args, **kwargs)
else:
self.logger.error("Attempted to add {} IRQ but SoC does {}.".format(
colorer(name), colorer("not support IRQs", color="red")))
raise SoCError()
# Str ------------------------------------------------------------------------------------------
def __str__(self):
r ="IRQ Handler (up to {} Locations).\n".format(colorer(self.n_locs))
r += SoCLocHandler.__str__(self)
r = r[:-1]
return r
# SoCController ------------------------------------------------------------------------------------
class SoCController(Module, AutoCSR):
def __init__(self, with_reset=True, with_scratch=True, with_errors=True):
if with_reset:
self._reset = CSRStorage(fields=[
CSRField("soc_rst", size=1, offset=0, pulse=True, description="""Write `1` to this register to reset the full SoC (Pulse Reset)"""),
CSRField("cpu_rst", size=1, offset=1, description="""Write `1` to this register to reset the CPU(s) of the SoC (Hold Reset)"""),
])
if with_scratch:
self._scratch = CSRStorage(32, reset=0x12345678, description="""
Use this register as a scratch space to verify that software read/write accesses
to the Wishbone/CSR bus are working correctly. The initial reset value of 0x1234578
can be used to verify endianness.""")
if with_errors:
self._bus_errors = CSRStatus(32, description="Total number of Wishbone bus errors (timeouts) since start.")
# # #
# Reset
if with_reset:
self.soc_rst = self._reset.fields.soc_rst
self.cpu_rst = self._reset.fields.cpu_rst
# Errors
if with_errors:
self.bus_error = Signal()
bus_errors = Signal(32)
self.sync += [
If(bus_errors != (2**len(bus_errors)-1),
If(self.bus_error, bus_errors.eq(bus_errors + 1))
)
]
self.comb += self._bus_errors.status.eq(bus_errors)
# SoC ----------------------------------------------------------------------------------------------
class SoC(Module):
mem_map = {}
def __init__(self, platform, sys_clk_freq,
bus_standard = "wishbone",
bus_data_width = 32,
bus_address_width = 32,
bus_timeout = 1e6,
bus_reserved_regions = {},
csr_data_width = 32,
csr_address_width = 14,
csr_paging = 0x800,
csr_ordering = "big",
csr_reserved_csrs = {},
irq_n_irqs = 32,
irq_reserved_irqs = {},
):
self.logger = logging.getLogger("SoC")
self.logger.info(colorer(" __ _ __ _ __ ", color="bright"))
self.logger.info(colorer(" / / (_) /____ | |/_/ ", color="bright"))
self.logger.info(colorer(" / /__/ / __/ -_)> < ", color="bright"))
self.logger.info(colorer(" /____/_/\\__/\\__/_/|_| ", color="bright"))
self.logger.info(colorer(" Build your hardware, easily!", color="bright"))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Creating SoC... ({})".format(build_time())))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info("FPGA device : {}.".format(platform.device))
self.logger.info("System clock: {:3.3f}MHz.".format(sys_clk_freq/1e6))
# SoC attributes ---------------------------------------------------------------------------
self.platform = platform
self.sys_clk_freq = sys_clk_freq
self.constants = {}
self.csr_regions = {}
# SoC Bus Handler --------------------------------------------------------------------------
self.submodules.bus = SoCBusHandler(
standard = bus_standard,
data_width = bus_data_width,
address_width = bus_address_width,
timeout = bus_timeout,
reserved_regions = bus_reserved_regions,
)
# SoC Bus Handler --------------------------------------------------------------------------
self.submodules.csr = SoCCSRHandler(
data_width = csr_data_width,
address_width = csr_address_width,
alignment = 32,
paging = csr_paging,
ordering = csr_ordering,
reserved_csrs = csr_reserved_csrs,
)
# SoC IRQ Handler --------------------------------------------------------------------------
self.submodules.irq = SoCIRQHandler(
n_irqs = irq_n_irqs,
reserved_irqs = irq_reserved_irqs
)
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Initial SoC:"))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(self.bus)
self.logger.info(self.csr)
self.logger.info(self.irq)
self.logger.info(colorer("-"*80, color="bright"))
self.add_config("CLOCK_FREQUENCY", int(sys_clk_freq))
# SoC Helpers ----------------------------------------------------------------------------------
def check_if_exists(self, name):
if hasattr(self, name):
self.logger.error("{} SubModule already {}.".format(
colorer(name),
colorer("declared", color="red")))
raise SoCError()
def add_constant(self, name, value=None):
name = name.upper()
if name in self.constants.keys():
self.logger.error("{} Constant already {}.".format(
colorer(name),
colorer("declared", color="red")))
raise SoCError()
self.constants[name] = SoCConstant(value)
def add_config(self, name, value=None):
name = "CONFIG_" + name
if isinstance(value, str):
self.add_constant(name + "_" + value)
else:
self.add_constant(name, value)
def check_bios_requirements(self):
# Check for required Peripherals.
for periph in [ "timer0"]:
if periph not in self.csr.locs.keys():
self.logger.error("BIOS needs {} peripheral to be {}.".format(
colorer(periph),
colorer("used", color="red")))
self.logger.error(self.bus)
raise SoCError()
# Check for required Memory Regions.
for mem in ["rom", "sram"]:
if mem not in self.bus.regions.keys():
self.logger.error("BIOS needs {} Region to be {} as Bus or Linker Region.".format(
colorer(mem),
colorer("defined", color="red")))
self.logger.error(self.bus)
raise SoCError()
# SoC Main Components --------------------------------------------------------------------------
def add_controller(self, name="ctrl", **kwargs):
self.check_if_exists(name)
setattr(self.submodules, name, SoCController(**kwargs))
def add_ram(self, name, origin, size, contents=[], mode="rw"):
ram_cls = {
"wishbone": wishbone.SRAM,
"axi-lite": axi.AXILiteSRAM,
}[self.bus.standard]
interface_cls = {
"wishbone": wishbone.Interface,
"axi-lite": axi.AXILiteInterface,
}[self.bus.standard]
ram_bus = interface_cls(data_width=self.bus.data_width)
ram = ram_cls(size, bus=ram_bus, init=contents, read_only=(mode == "r"))
self.bus.add_slave(name, ram.bus, SoCRegion(origin=origin, size=size, mode=mode))
self.check_if_exists(name)
self.logger.info("RAM {} {} {}.".format(
colorer(name),
colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
def add_rom(self, name, origin, size, contents=[], mode="r"):
self.add_ram(name, origin, size, contents, mode=mode)
def init_rom(self, name, contents=[], auto_size=True):
self.logger.info("Initializing ROM {} with contents (Size: {}).".format(
colorer(name),
colorer(f"0x{4*len(contents):x}")))
getattr(self, name).mem.init = contents
if auto_size and self.bus.regions[name].mode == "r":
self.logger.info("Auto-Resizing ROM {} from {} to {}.".format(
colorer(name),
colorer(f"0x{self.bus.regions[name].size:x}"),
colorer(f"0x{4*len(contents):x}")))
getattr(self, name).mem.depth = len(contents)
def add_csr_bridge(self, origin, register=False):
csr_bridge_cls = {
"wishbone": wishbone.Wishbone2CSR,
"axi-lite": axi.AXILite2CSR,
}[self.bus.standard]
self.check_if_exists("csr_bridge")
self.submodules.csr_bridge = csr_bridge_cls(
bus_csr = csr_bus.Interface(
address_width = self.csr.address_width,
data_width = self.csr.data_width),
register = register)
csr_size = 2**(self.csr.address_width + 2)
csr_region = SoCRegion(origin=origin, size=csr_size, cached=False)
bus = getattr(self.csr_bridge, self.bus.standard.replace('-', '_'))
self.bus.add_slave("csr", bus, csr_region)
self.csr.add_master(name="bridge", master=self.csr_bridge.csr)
self.add_config("CSR_DATA_WIDTH", self.csr.data_width)
self.add_config("CSR_ALIGNMENT", self.csr.alignment)
def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None, cfu=None):
# Check that CPU is supported.
if name not in cpu.CPUS.keys():
self.logger.error("{} CPU {}, supporteds: {}.".format(
colorer(name),
colorer("not supported", color="red"),
colorer(", ".join(cpu.CPUS.keys()))))
raise SoCError()
# Add CPU.
if name == "external" and cls is None:
self.logger.error("{} CPU requires {} to be specified.".format(
colorer(name),
colorer("cpu_cls", color="red")))
raise SoCError()
cpu_cls = cls if cls is not None else cpu.CPUS[name]
if (variant not in cpu_cls.variants) and (cpu_cls is not cpu.CPUNone):
self.logger.error("{} CPU variant {}, supporteds: {}.".format(
colorer(variant),
colorer("not supported", color="red"),
colorer(", ".join(cpu_cls.variants))))
raise SoCError()
self.check_if_exists("cpu")
self.submodules.cpu = cpu_cls(self.platform, variant)
# Add optional CFU plugin.
if "cfu" in variant and hasattr(self.cpu, "add_cfu"):
self.cpu.add_cfu(cfu_filename=cfu)
# Update SoC with CPU constraints.
# IOs regions.
for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
# Mapping.
if isinstance(self.cpu, cpu.CPUNone):
# With CPUNone, give priority to User's mapping.
self.mem_map = {**self.cpu.mem_map, **self.mem_map}
else:
# Override User's mapping with CPU constrainted mapping (and warn User).
for n, origin in self.cpu.mem_map.items():
if n in self.mem_map.keys():
self.logger.info("CPU {} {} mapping from {} to {}.".format(
colorer("overriding", color="cyan"),
colorer(n),
colorer(f"0x{self.mem_map[n]:x}"),
colorer(f"0x{self.cpu.mem_map[n]:x}")))
self.mem_map.update(self.cpu.mem_map)
# Add Bus Masters/CSR/IRQs.
if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
if hasattr(self.cpu, "set_reset_address"):
if reset_address is None:
reset_address = self.mem_map["rom"]
self.cpu.set_reset_address(reset_address)
for n, cpu_bus in enumerate(self.cpu.periph_buses):
self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
if hasattr(self.cpu, "interrupt"):
self.irq.enable()
for name, loc in self.cpu.interrupts.items():
self.irq.add(name, loc)
self.add_config("CPU_HAS_INTERRUPT")
# Create optional DMA Bus (for Cache Coherence).
if hasattr(self.cpu, "dma_bus"):
self.submodules.dma_bus = SoCBusHandler(
name = "SoCDMABusHandler",
standard = "wishbone",
data_width = self.bus.data_width,
address_width = self.bus.address_width,
)
dma_bus = wishbone.Interface(data_width=self.bus.data_width)
self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only
self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus)
# Connect SoCController's reset to CPU reset.
if hasattr(self, "ctrl"):
self.comb += self.cpu.reset.eq(
# Reset the CPU on...
getattr(self.ctrl, "soc_rst", 0) | # Full SoC Reset command...
getattr(self.ctrl, "cpu_rst", 0) # or on CPU Reset command.
)
self.add_config("CPU_RESET_ADDR", reset_address)
# Add CPU's SoC components (if any).
if hasattr(self.cpu, "add_soc_components"):
self.cpu.add_soc_components(soc=self, soc_region_cls=SoCRegion) # FIXME: avoid passing SoCRegion.
# Add constants.
self.add_config("CPU_TYPE", str(name))
self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown"))
if hasattr(self.cpu, "nop"):
self.add_constant("CONFIG_CPU_NOP", self.cpu.nop)
def add_timer(self, name="timer0"):
from litex.soc.cores.timer import Timer
self.check_if_exists(name)
setattr(self.submodules, name, Timer())
if self.irq.enabled:
self.irq.add(name, use_loc_if_exists=True)
# SoC finalization -----------------------------------------------------------------------------
def do_finalize(self):
interconnect_p2p_cls = {
"wishbone": wishbone.InterconnectPointToPoint,
"axi-lite": axi.AXILiteInterconnectPointToPoint,
}[self.bus.standard]
interconnect_shared_cls = {
"wishbone": wishbone.InterconnectShared,
"axi-lite": axi.AXILiteInterconnectShared,
}[self.bus.standard]
# SoC Reset --------------------------------------------------------------------------------
# Connect soc_rst to CRG's rst if presents.
if hasattr(self, "ctrl") and hasattr(self, "crg"):
crg_rst = getattr(self.crg, "rst", None)
if isinstance(crg_rst, Signal):
self.comb += crg_rst.eq(getattr(self.ctrl, "soc_rst", 0))
# SoC CSR bridge ---------------------------------------------------------------------------
# FIXME: for now, use registered CSR bridge when SDRAM is present; find the best compromise.
self.add_csr_bridge(self.mem_map["csr"], register=hasattr(self, "sdram"))
# SoC Bus Interconnect ---------------------------------------------------------------------
if len(self.bus.masters) and len(self.bus.slaves):
# If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
if ((len(self.bus.masters) == 1) and
(len(self.bus.slaves) == 1) and
(next(iter(self.bus.regions.values())).origin == 0)):
self.submodules.bus_interconnect = interconnect_p2p_cls(
master = next(iter(self.bus.masters.values())),
slave = next(iter(self.bus.slaves.values())))
# Otherwise, use InterconnectShared.
else:
self.submodules.bus_interconnect = interconnect_shared_cls(
masters = self.bus.masters.values(),
slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()],
register = True,
timeout_cycles = self.bus.timeout)
if hasattr(self, "ctrl") and self.bus.timeout is not None:
if hasattr(self.ctrl, "bus_error"):
self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
self.bus.logger.info("Interconnect: {} ({} <-> {}).".format(
colorer(self.bus_interconnect.__class__.__name__),
colorer(len(self.bus.masters)),
colorer(len(self.bus.slaves))))
self.add_constant("CONFIG_BUS_STANDARD", self.bus.standard.upper())
self.add_constant("CONFIG_BUS_DATA_WIDTH", self.bus.data_width)
self.add_constant("CONFIG_BUS_ADDRESS_WIDTH", self.bus.address_width)
# SoC DMA Bus Interconnect (Cache Coherence) -----------------------------------------------
if hasattr(self, "dma_bus"):
if len(self.dma_bus.masters) and len(self.dma_bus.slaves):
# If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
if ((len(self.dma_bus.masters) == 1) and
(len(self.dma_bus.slaves) == 1) and
(next(iter(self.dma_bus.regions.values())).origin == 0)):
self.submodules.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
master = next(iter(self.dma_bus.masters.values())),
slave = next(iter(self.dma_bus.slaves.values())))
# Otherwise, use InterconnectShared.
else:
self.submodules.dma_bus_interconnect = wishbone.InterconnectShared(
masters = self.dma_bus.masters.values(),
slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()],
register = True)
self.bus.logger.info("DMA Interconnect: {} ({} <-> {}).".format(
colorer(self.dma_bus_interconnect.__class__.__name__),
colorer(len(self.dma_bus.masters)),
colorer(len(self.dma_bus.slaves))))
self.add_constant("CONFIG_CPU_HAS_DMA_BUS")
# SoC CSR Interconnect ---------------------------------------------------------------------
self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
address_map = self.csr.address_map,
data_width = self.csr.data_width,
address_width = self.csr.address_width,
alignment = self.csr.alignment,
paging = self.csr.paging,
ordering = self.csr.ordering,
soc_bus_data_width = self.bus.data_width)
if len(self.csr.masters):
self.submodules.csr_interconnect = csr_bus.InterconnectShared(
masters = list(self.csr.masters.values()),
slaves = self.csr_bankarray.get_buses())
# Add CSRs regions.
for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
self.csr.add_region(name, SoCCSRRegion(
origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
busword = self.csr.data_width,
obj = csrs))
# Add Memory regions.
for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
busword = self.csr.data_width,
obj = memory))
# Sort CSR regions by origin.
self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
# Add CSRs / Config items to constants.
for name, constant in self.csr_bankarray.constants:
self.add_constant(name + "_" + constant.name, constant.value.value)
# SoC CPU Check ----------------------------------------------------------------------------
if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000, cpu.EOS_S3)):
cpu_reset_address_valid = False
for name, container in self.bus.regions.items():
if self.bus.check_region_is_in(
region = SoCRegion(origin=self.cpu.reset_address, size=self.bus.data_width//8),
container = container):
cpu_reset_address_valid = True
if name == "rom":
self.cpu.use_rom = True
if not cpu_reset_address_valid:
self.logger.error("CPU needs {} to be in a {} Region.".format(
colorer("reset address 0x{:08x}".format(self.cpu.reset_address)),
colorer("defined", color="red")))
self.logger.error(self.bus)
raise SoCError()
# SoC IRQ Interconnect ---------------------------------------------------------------------
if hasattr(self, "cpu") and hasattr(self.cpu, "interrupt"):
for name, loc in sorted(self.irq.locs.items()):
if name in self.cpu.interrupts.keys():
continue
if hasattr(self, name):
module = getattr(self, name)
ev = None
if hasattr(module, "ev"):
ev = module.ev
elif isinstance(module, EventManager):
ev = module
else:
self.logger.error("EventManager {} in {} SubModule.".format(
colorer("not found", color="red"),
colorer(name)))
raise SoCError()
self.comb += self.cpu.interrupt[loc].eq(ev.irq)
self.add_constant(name + "_INTERRUPT", loc)
# SoC Infos --------------------------------------------------------------------------------
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(colorer("Finalized SoC:"))
self.logger.info(colorer("-"*80, color="bright"))
self.logger.info(self.bus)
if hasattr(self, "dma_bus"):
self.logger.info(self.dma_bus)
self.logger.info(self.csr)
self.logger.info(self.irq)
self.logger.info(colorer("-"*80, color="bright"))
# SoC build ------------------------------------------------------------------------------------
def build(self, *args, **kwargs):
self.build_name = kwargs.pop("build_name", self.platform.name)
if self.build_name[0].isdigit():
self.build_name = f"_{self.build_name}"
kwargs.update({"build_name": self.build_name})
return self.platform.build(self, *args, **kwargs)
# LiteXSoC -----------------------------------------------------------------------------------------
class LiteXSoC(SoC):
# Add Identifier -------------------------------------------------------------------------------
def add_identifier(self, name="identifier", identifier="LiteX SoC", with_build_time=True):
from litex.soc.cores.identifier import Identifier
self.check_if_exists(name)
if with_build_time:
identifier += " " + build_time()
self.add_config("WITH_BUILD_TIME")
setattr(self.submodules, name, Identifier(identifier))
# Add UART -------------------------------------------------------------------------------------
def add_uart(self, name, baudrate=115200, fifo_depth=16):
from litex.soc.cores import uart
self.check_if_exists("uart")
# Stub / Stream.
if name in ["stub", "stream"]:
self.submodules.uart = uart.UART(tx_fifo_depth=0, rx_fifo_depth=0)
if name == "stub":
self.comb += self.uart.sink.ready.eq(1)
# UARTBone / Bridge.
elif name in ["uartbone", "bridge"]:
self.add_uartbone(baudrate=baudrate)
# Crossover.
elif name in ["crossover"]:
self.submodules.uart = uart.UARTCrossover(
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# Crossover + Bridge.
elif name in ["crossover+bridge"]:
self.add_uartbone(baudrate=baudrate)
self.submodules.uart = uart.UARTCrossover(
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# Model/Sim.
elif name in ["model", "sim"]:
self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# JTAG Atlantic.
elif name in ["jtag_atlantic"]:
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# JTAG UART.
elif name in ["jtag_uart"]:
from litex.soc.cores.jtag import JTAGPHY
self.clock_domains.cd_sys_jtag = ClockDomain() # Run JTAG-UART in sys_jtag clock domain similar to
self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys")) # sys clock domain but with rst disconnected.
self.submodules.uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag")
self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
# USB ACM (with ValentyUSB core).
elif name in ["usb_acm"]:
import valentyusb.usbcore.io as usbio
import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
usb_pads = self.platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.clock_domains.cd_sys_usb = ClockDomain() # Run USB ACM in sys_usb clock domain similar to
self.comb += self.cd_sys_usb.clk.eq(ClockSignal("sys")) # sys clock domain but with rst disconnected.
self.submodules.uart = ClockDomainsRenamer("sys_usb")(cdc_eptri.CDCUsb(usb_iobuf))
# Classical UART.
else:
self.submodules.uart_phy = uart.UARTPHY(
pads = self.platform.request(name),
clk_freq = self.sys_clk_freq,
baudrate = baudrate)
self.submodules.uart = uart.UART(self.uart_phy,
tx_fifo_depth = fifo_depth,
rx_fifo_depth = fifo_depth)
if self.irq.enabled:
self.irq.add("uart", use_loc_if_exists=True)
else:
self.add_constant("UART_POLLING")
# Add UARTbone ---------------------------------------------------------------------------------
def add_uartbone(self, name="serial", clk_freq=None, baudrate=115200, cd="sys"):
from litex.soc.cores import uart
if clk_freq is None:
clk_freq = self.sys_clk_freq
self.check_if_exists("uartbone")
self.submodules.uartbone_phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
self.submodules.uartbone = uart.UARTBone(phy=self.uartbone_phy, clk_freq=clk_freq, cd=cd)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# Add JTAGbone ---------------------------------------------------------------------------------
def add_jtagbone(self, chain=1):
from litex.soc.cores import uart
from litex.soc.cores.jtag import JTAGPHY
self.check_if_exists("jtabone")
self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain)
self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)
# Add SDRAM ------------------------------------------------------------------------------------
def add_sdram(self, name, phy, module, origin=None, size=None, with_bist=False, with_soc_interconnect=True,
l2_cache_size = 8192,
l2_cache_min_data_width = 128,
l2_cache_reverse = True,
l2_cache_full_memory_we = True,
**kwargs):
# Imports.
from litedram.common import LiteDRAMNativePort
from litedram.core import LiteDRAMCore
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
from litedram.frontend.axi import LiteDRAMAXI2Native
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
# LiteDRAM core.
self.check_if_exists("sdram")
self.submodules.sdram = LiteDRAMCore(
phy = phy,
geom_settings = module.geom_settings,
timing_settings = module.timing_settings,
clk_freq = self.sys_clk_freq,
**kwargs)
# Save SPD data to be able to verify it at runtime.
if hasattr(module, "_spd_data"):
# Pack the data into words of bus width.
bytes_per_word = self.bus.data_width // 8
mem = [0] * ceil(len(module._spd_data) / bytes_per_word)
for i in range(len(mem)):
for offset in range(bytes_per_word):
mem[i] <<= 8
if self.cpu.endianness == "little":
offset = bytes_per_word - 1 - offset
spd_byte = i * bytes_per_word + offset
if spd_byte < len(module._spd_data):
mem[i] |= module._spd_data[spd_byte]
self.add_rom(
name = "spd",
origin = self.mem_map.get("spd", None),
size = len(module._spd_data),
contents = mem,
)
# LiteDRAM BIST.
if with_bist:
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
self.submodules.sdram_checker = LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
if not with_soc_interconnect: return
# Compute/Check SDRAM size.
sdram_size = 2**(module.geom_settings.bankbits +
module.geom_settings.rowbits +
module.geom_settings.colbits)*phy.settings.nranks*phy.settings.databits//8
if size is not None:
sdram_size = min(sdram_size, size)
# Add SDRAM region.
self.bus.add_region("main_ram", SoCRegion(origin=self.mem_map.get("main_ram", origin), size=sdram_size))
# Add CPU's direct memory buses (if not already declared) ----------------------------------
if hasattr(self.cpu, "add_memory_buses"):
self.cpu.add_memory_buses(
address_width = 32,
data_width = self.sdram.crossbar.controller.data_width
)
# Connect CPU's direct memory buses to LiteDRAM --------------------------------------------
if len(self.cpu.memory_buses):
# When CPU has at least a direct memory bus, connect them directly to LiteDRAM.
for mem_bus in self.cpu.memory_buses:
# Request a LiteDRAM native port.
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
# Check if bus is an AXI bus and connect it.
if isinstance(mem_bus, axi.AXIInterface):
# If same data_width, connect it directly.
if port.data_width == mem_bus.data_width:
self.logger.info("Matching AXI MEM data width ({})\n".format(port.data_width))
self.submodules += LiteDRAMAXI2Native(
axi = self.cpu.mem_axi,
port = port,
base_address = self.bus.regions["main_ram"].origin)
# If different data_width, do the adaptation and connect it via Wishbone.
else:
self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
port.data_width,
self.cpu.mem_axi.data_width))
# FIXME: Replace WB data-width converter with native AXI converter.
mem_wb = wishbone.Interface(
data_width = self.cpu.mem_axi.data_width,
adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8))
mem_a2w = axi.AXI2Wishbone(
axi = self.cpu.mem_axi,
wishbone = mem_wb,
base_address = 0)
self.submodules += mem_a2w
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += LiteDRAMWishbone2Native(
wishbone = litedram_wb,
port = port,
base_address = self.bus.regions["main_ram"].origin)
self.submodules += wishbone.Converter(mem_wb, litedram_wb)
# Check if bus is a Native bus and connect it.
if isinstance(mem_bus, LiteDRAMNativePort):
# If same data_width, connect it directly.
if port.data_width == mem_bus.data_width:
self.comb += mem_bus.cmd.connect(port.cmd)
self.comb += mem_bus.wdata.connect(port.wdata)
self.comb += port.rdata.connect(mem_bus.rdata)
# Else raise Error.
else:
raise NotImplementedError
# Connect Main bus to LiteDRAM (with optional L2 Cache) ------------------------------------
connect_main_bus_to_dram = (
# No memory buses.
(not len(self.cpu.memory_buses)) or
# Memory buses but no DMA bus.
(len(self.cpu.memory_buses) and not hasattr(self.cpu, "dma_bus"))
)
if connect_main_bus_to_dram:
# Request a LiteDRAM native port.
port = self.sdram.crossbar.get_port()
port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2.
# Create Wishbone Slave.
wb_sdram = wishbone.Interface()
self.bus.add_slave("main_ram", wb_sdram)
# L2 Cache
if l2_cache_size != 0:
# Insert L2 cache inbetween Wishbone bus and LiteDRAM
l2_cache_size = max(l2_cache_size, int(2*port.data_width/8)) # Use minimal size if lower
l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
l2_cache_data_width = max(port.data_width, l2_cache_min_data_width)
l2_cache = wishbone.Cache(
cachesize = l2_cache_size//4,
master = wb_sdram,
slave = wishbone.Interface(l2_cache_data_width),
reverse = l2_cache_reverse)
if l2_cache_full_memory_we:
l2_cache = FullMemoryWE()(l2_cache)
self.submodules.l2_cache = l2_cache
litedram_wb = self.l2_cache.slave
else:
litedram_wb = wishbone.Interface(port.data_width)
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
self.add_config("L2_SIZE", l2_cache_size)
# Wishbone Slave <--> LiteDRAM bridge.
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(
wishbone = litedram_wb,
port = port,
base_address = self.bus.regions["main_ram"].origin)
# Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False,
nrxslots = 2,
ntxslots = 2,
with_timestamp = False,
with_timing_constraints = True):
# Imports
from liteeth.mac import LiteEthMAC
from liteeth.phy.model import LiteEthPHYModel
# MAC.
self.check_if_exists(name)
if with_timestamp:
self.timer0.add_uptime()
ethmac = LiteEthMAC(
phy = phy,
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness,
nrxslots = nrxslots,
ntxslots = ntxslots,
timestamp = None if not with_timestamp else self.timer0.uptime_cycles,
with_preamble_crc = not software_debug)
# Use PHY's eth_tx/eth_rx clock domains.
ethmac = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethmac)
setattr(self.submodules, name, ethmac)
# Compute Regions size and add it to the SoC.
ethmac_region_size = (ethmac.rx_slots.read() + ethmac.tx_slots.read())*ethmac.slot_size.read()
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
# Add IRQs (if enabled).
if self.irq.enabled:
self.irq.add(name, use_loc_if_exists=True)
# Dynamic IP (if enabled).
if dynamic_ip:
self.add_constant("ETH_DYNAMIC_IP")
# Software Debug
if software_debug:
self.add_constant("ETH_UDP_TX_DEBUG")
self.add_constant("ETH_UDP_RX_DEBUG")
# Timing constraints
if with_timing_constraints:
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None, phy_cd="eth",
mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50",
udp_port = 1234,
buffer_depth = 4,
with_timing_constraints = True):
# Imports
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
from liteeth.phy.model import LiteEthPHYModel
# Core
self.check_if_exists(name)
ethcore = LiteEthUDPIPCore(
phy = phy,
mac_address = mac_address,
ip_address = ip_address,
clk_freq = self.clk_freq)
# Use PHY's eth_tx/eth_rx clock domains.
ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx",
"sys": phy_cd + "_rx"})(ethcore)
self.submodules.ethcore = ethcore
# Create Etherbone clock domain and run it from sys clock domain.
self.clock_domains.cd_etherbone = ClockDomain("etherbone")
self.comb += self.cd_etherbone.clk.eq(ClockSignal("sys"))
self.comb += self.cd_etherbone.rst.eq(ResetSignal("sys"))
# Etherbone
etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd="etherbone")
setattr(self.submodules, name, etherbone)
self.add_wb_master(etherbone.wishbone.bus)
# Timing constraints
if with_timing_constraints:
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel) and not getattr(phy, "model", False):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, phy=None, rate="1:1", **kwargs):
if module is None:
# Use previous LiteX SPI Flash core with compat, will be deprecated at some point.
from litex.compat.soc_add_spi_flash import add_spi_flash
add_spi_flash(self, name, mode, dummy_cycles)
# LiteSPI.
else:
# Imports.
from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY
from litespi.opcodes import SpiNorFlashOpCodes
# Checks/Parameters.
assert mode in ["1x", "4x"]
if clk_freq is None: clk_freq = self.sys_clk_freq
# PHY.
spiflash_phy = phy
if spiflash_phy is None:
self.check_if_exists(name + "_phy")
spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate)
setattr(self.submodules, name + "_phy", spiflash_phy)
# Core.
self.check_if_exists(name + "_mmap")
spiflash_core = LiteSPI(spiflash_phy, mmap_endianness=self.cpu.endianness, **kwargs)
setattr(self.submodules, name + "_core", spiflash_core)
spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
self.bus.add_slave(name=name, slave=spiflash_core.bus, region=spiflash_region)
# Constants.
self.add_constant("SPIFLASH_PHY_FREQUENCY", clk_freq)
self.add_constant("SPIFLASH_MODULE_NAME", module.name.upper())
self.add_constant("SPIFLASH_MODULE_TOTAL_SIZE", module.total_size)
self.add_constant("SPIFLASH_MODULE_PAGE_SIZE", module.page_size)
if SpiNorFlashOpCodes.READ_1_1_4 in module.supported_opcodes:
self.add_constant("SPIFLASH_MODULE_QUAD_CAPABLE")
if SpiNorFlashOpCodes.READ_4_4_4 in module.supported_opcodes:
self.add_constant("SPIFLASH_MODULE_QPI_CAPABLE")
# Add SPI SDCard -------------------------------------------------------------------------------
def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3, software_debug=False):
# Imports.
from litex.soc.cores.spi import SPIMaster
# Pads.
pads = self.platform.request(name)
if hasattr(pads, "rst"):
self.comb += pads.rst.eq(0)
# Core.
self.check_if_exists(name)
spisdcard = SPIMaster(pads, 8, self.sys_clk_freq, spi_clk_freq)
spisdcard.add_clk_divider()
setattr(self.submodules, name, spisdcard)
# Debug.
if software_debug:
self.add_constant("SPISDCARD_DEBUG")
# Add SDCard -----------------------------------------------------------------------------------
def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False, software_debug=False):
# Imports.
from litesdcard.emulator import SDEmulator
from litesdcard.phy import SDPHY
from litesdcard.core import SDCore
from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
# Checks.
assert mode in ["read", "write", "read+write"]
# Emulator / Pads.
if use_emulator:
sdemulator = SDEmulator(self.platform)
self.submodules += sdemulator
sdcard_pads = sdemulator.pads
else:
sdcard_pads = self.platform.request(name)
# Core.
self.check_if_exists("sdphy")
self.check_if_exists("sdcore")
self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
self.submodules.sdcore = SDCore(self.sdphy)
# Block2Mem DMA.
if "read" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sdblock2mem", master=bus)
# Mem2Block DMA.
if "write" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sdmem2block", master=bus)
# Interrupts.
self.submodules.sdirq = EventManager()
self.sdirq.card_detect = EventSourcePulse(description="SDCard has been ejected/inserted.")
if "read" in mode:
self.sdirq.block2mem_dma = EventSourcePulse(description="Block2Mem DMA terminated.")
if "write" in mode:
self.sdirq.mem2block_dma = EventSourcePulse(description="Mem2Block DMA terminated.")
self.sdirq.cmd_done = EventSourceLevel(description="Command completed.")
self.sdirq.finalize()
if "read" in mode:
self.comb += self.sdirq.block2mem_dma.trigger.eq(self.sdblock2mem.irq)
if "write" in mode:
self.comb += self.sdirq.mem2block_dma.trigger.eq(self.sdmem2block.irq)
self.comb += [
self.sdirq.card_detect.trigger.eq(self.sdphy.card_detect_irq),
self.sdirq.cmd_done.trigger.eq(self.sdcore.cmd_event.fields.done)
]
if self.irq.enabled:
self.irq.add("sdirq", use_loc_if_exists=True)
# Debug.
if software_debug:
self.add_constant("SDCARD_DEBUG")
# Add SATA -------------------------------------------------------------------------------------
def add_sata(self, name="sata", phy=None, mode="read+write"):
# Imports.
from litesata.core import LiteSATACore
from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA
# Checks.
assert mode in ["read", "write", "read+write"]
sata_clk_freqs = {
"gen1": 75e6,
"gen2": 150e6,
"gen3": 300e6,
}
sata_clk_freq = sata_clk_freqs[phy.gen]
assert self.clk_freq >= sata_clk_freq/2 # FIXME: /2 for 16-bit data-width, add support for 32-bit.
# Core.
self.check_if_exists("sata_core")
self.submodules.sata_core = LiteSATACore(phy)
# Crossbar.
self.check_if_exists("sata_crossbar")
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Sector2Mem DMA.
if "read" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sata_sector2mem = LiteSATASector2MemDMA(
port = self.sata_crossbar.get_port(),
bus = bus,
endianness = self.cpu.endianness)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sata_sector2mem", master=bus)
# Mem2Sector DMA.
if "write" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(
bus = bus,
port = self.sata_crossbar.get_port(),
endianness = self.cpu.endianness)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sata_mem2sector", master=bus)
# Timing constraints.
self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/sata_clk_freq)
self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk, 1e9/sata_clk_freq)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_rx.clk)
# Add PCIe -------------------------------------------------------------------------------------
def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8,
with_dma_buffering = True, dma_buffering_depth=1024,
with_dma_loopback = True,
with_msi = True):
# Imports
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneMaster
# Checks.
assert self.csr.data_width == 32
# Endpoint.
self.check_if_exists(f"{name}_endpoint")
endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests, endianness=phy.endianness)
setattr(self.submodules, f"{name}_endpoint", endpoint)
# MMAP.
self.check_if_exists(f"{name}_mmap")
mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
self.add_wb_master(mmap.wishbone)
setattr(self.submodules, f"{name}_mmap", mmap)
# MSI.
if with_msi:
self.check_if_exists(f"{name}_msi")
msi = LitePCIeMSI()
setattr(self.submodules, f"{name}_msi", msi)
self.comb += msi.source.connect(phy.msi)
self.msis = {}
# DMAs.
for i in range(ndmas):
assert with_msi
self.check_if_exists(f"{name}_dma{i}")
dma = LitePCIeDMA(phy, endpoint,
with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth,
with_loopback = with_dma_loopback)
setattr(self.submodules, f"{name}_dma{i}", dma)
self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq
self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq
self.add_constant("DMA_CHANNELS", ndmas)
# Map/Connect IRQs.
if with_msi:
for i, (k, v) in enumerate(sorted(self.msis.items())):
self.comb += msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# Timing constraints.
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, phy.cd_pcie.clk)
# Add Video ColorBars Pattern ------------------------------------------------------------------
def add_video_colorbars(self, name="video_colorbars", phy=None, timings="800x600@60Hz", clock_domain="sys"):
# Imports.
from litex.soc.cores.video import VideoTimingGenerator, ColorBarsPattern
# Video Timing Generator.
self.check_if_exists(f"{name}_vtg")
vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
vtg = ClockDomainsRenamer(clock_domain)(vtg)
setattr(self.submodules, f"{name}_vtg", vtg)
# ColorsBars Pattern.
self.check_if_exists(name)
colorbars = ClockDomainsRenamer(clock_domain)(ColorBarsPattern())
setattr(self.submodules, name, colorbars)
# Connect Video Timing Generator to ColorsBars Pattern.
self.comb += [
vtg.source.connect(colorbars.vtg_sink),
colorbars.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
]
# Add Video Terminal ---------------------------------------------------------------------------
def add_video_terminal(self, name="video_terminal", phy=None, timings="800x600@60Hz", clock_domain="sys"):
# Imports.
from litex.soc.cores.video import VideoTimingGenerator, VideoTerminal
# Video Timing Generator.
self.check_if_exists(f"{name}_vtg")
vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
vtg = ClockDomainsRenamer(clock_domain)(vtg)
setattr(self.submodules, f"{name}_vtg", vtg)
# Video Terminal.
timings = timings if isinstance(timings, str) else timings[0]
vt = VideoTerminal(
hres = int(timings.split("@")[0].split("x")[0]),
vres = int(timings.split("@")[0].split("x")[1]),
)
vt = ClockDomainsRenamer(clock_domain)(vt)
setattr(self.submodules, name, vt)
# Connect Video Timing Generator to Video Terminal.
self.comb += vtg.source.connect(vt.vtg_sink)
# Connect UART to Video Terminal.
uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain)
setattr(self.submodules, f"{name}_uart_cdc", uart_cdc)
self.comb += [
uart_cdc.sink.valid.eq(self.uart.tx_fifo.source.valid & self.uart.tx_fifo.source.ready),
uart_cdc.sink.data.eq(self.uart.tx_fifo.source.data),
uart_cdc.source.connect(vt.uart_sink),
]
# Connect Video Terminal to Video PHY.
self.comb += vt.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
# Add Video Framebuffer ------------------------------------------------------------------------
def add_video_framebuffer(self, name="video_framebuffer", phy=None, timings="800x600@60Hz", clock_domain="sys", format="rgb888"):
# Imports.
from litex.soc.cores.video import VideoTimingGenerator, VideoFrameBuffer
# Video Timing Generator.
vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
vtg = ClockDomainsRenamer(clock_domain)(vtg)
setattr(self.submodules, f"{name}_vtg", vtg)
# Video FrameBuffer.
timings = timings if isinstance(timings, str) else timings[0]
base = self.mem_map.get(name, 0x40c00000)
hres = int(timings.split("@")[0].split("x")[0])
vres = int(timings.split("@")[0].split("x")[1])
vfb = VideoFrameBuffer(self.sdram.crossbar.get_port(),
hres = hres,
vres = vres,
base = base,
format = format,
clock_domain = clock_domain,
clock_faster_than_sys = vtg.video_timings["pix_clk"] > self.sys_clk_freq,
)
setattr(self.submodules, name, vfb)
# Connect Video Timing Generator to Video FrameBuffer.
self.comb += vtg.source.connect(vfb.vtg_sink)
# Connect Video FrameBuffer to Video PHY.
self.comb += vfb.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
# Constants.
self.add_constant("VIDEO_FRAMEBUFFER_BASE", base)
self.add_constant("VIDEO_FRAMEBUFFER_HRES", hres)
self.add_constant("VIDEO_FRAMEBUFFER_VRES", vres)
self.add_constant("VIDEO_FRAMEBUFFER_DEPTH", vfb.depth)
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litex.soc.cores import uart\n'), ((61139, 61160), 'math.log2', 'log2', (['port.data_width'], {}), '(port.data_width)\n', (61143, 61160), False, 'from math import log2, ceil\n'), ((61584, 61690), 'litedram.frontend.axi.LiteDRAMAXI2Native', 'LiteDRAMAXI2Native', ([], {'axi': 'self.cpu.mem_axi', 'port': 'port', 'base_address': "self.bus.regions['main_ram'].origin"}), "(axi=self.cpu.mem_axi, port=port, base_address=self.bus.\n regions['main_ram'].origin)\n", (61602, 61690), False, 'from litedram.frontend.axi import LiteDRAMAXI2Native\n'), ((62453, 62524), 'litex.soc.interconnect.axi.AXI2Wishbone', 'axi.AXI2Wishbone', ([], {'axi': 'self.cpu.mem_axi', 'wishbone': 'mem_wb', 'base_address': '(0)'}), '(axi=self.cpu.mem_axi, wishbone=mem_wb, base_address=0)\n', (62469, 62524), False, 'from litex.soc.interconnect import axi\n'), ((62718, 62753), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', (['port.data_width'], {}), '(port.data_width)\n', (62736, 62753), False, 'from litex.soc.interconnect import wishbone\n'), ((62797, 62908), 'litedram.frontend.wishbone.LiteDRAMWishbone2Native', 'LiteDRAMWishbone2Native', ([], {'wishbone': 'litedram_wb', 'port': 'port', 'base_address': "self.bus.regions['main_ram'].origin"}), "(wishbone=litedram_wb, port=port, base_address=self.\n bus.regions['main_ram'].origin)\n", (62820, 62908), False, 'from litedram.frontend.wishbone import LiteDRAMWishbone2Native\n'), ((63050, 63089), 'litex.soc.interconnect.wishbone.Converter', 'wishbone.Converter', (['mem_wb', 'litedram_wb'], {}), '(mem_wb, litedram_wb)\n', (63068, 63089), False, 'from litex.soc.interconnect import wishbone\n'), ((64644, 64663), 'math.log2', 'log2', (['l2_cache_size'], {}), '(l2_cache_size)\n', (64648, 64663), False, 'from math import log2, ceil\n'), ((64963, 65002), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', (['l2_cache_data_width'], {}), '(l2_cache_data_width)\n', (64981, 65002), False, 'from litex.soc.interconnect import wishbone\n'), ((38827, 38842), 'litex.soc.cores.cpu.CPUS.keys', 'cpu.CPUS.keys', ([], {}), '()\n', (38840, 38842), False, 'from litex.soc.cores import cpu\n'), ((54312, 54388), 'litex.soc.cores.uart.UART', 'uart.UART', (['self.uart_phy'], {'tx_fifo_depth': 'fifo_depth', 'rx_fifo_depth': 'fifo_depth'}), '(self.uart_phy, tx_fifo_depth=fifo_depth, rx_fifo_depth=fifo_depth)\n', (54321, 54388), False, 'from litex.soc.cores import uart\n'), ((54588, 54602), 'litex.soc.cores.jtag.JTAGAtlantic', 'JTAGAtlantic', ([], {}), '()\n', (54600, 54602), False, 'from litex.soc.cores.jtag import JTAGAtlantic\n'), ((54638, 54714), 'litex.soc.cores.uart.UART', 'uart.UART', (['self.uart_phy'], {'tx_fifo_depth': 'fifo_depth', 'rx_fifo_depth': 'fifo_depth'}), '(self.uart_phy, tx_fifo_depth=fifo_depth, rx_fifo_depth=fifo_depth)\n', (54647, 54714), False, 'from litex.soc.cores import uart\n'), ((55136, 55197), 'litex.soc.cores.jtag.JTAGPHY', 'JTAGPHY', ([], {'device': 'self.platform.device', 'clock_domain': '"""sys_jtag"""'}), "(device=self.platform.device, clock_domain='sys_jtag')\n", (55143, 55197), False, 'from litex.soc.cores.jtag import JTAGPHY\n'), ((55233, 55309), 'litex.soc.cores.uart.UART', 'uart.UART', (['self.uart_phy'], {'tx_fifo_depth': 'fifo_depth', 'rx_fifo_depth': 'fifo_depth'}), '(self.uart_phy, tx_fifo_depth=fifo_depth, rx_fifo_depth=fifo_depth)\n', (55242, 55309), False, 'from litex.soc.cores import uart\n'), ((55614, 55670), 'valentyusb.usbcore.io.IoBuf', 'usbio.IoBuf', (['usb_pads.d_p', 'usb_pads.d_n', 'usb_pads.pullup'], {}), '(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)\n', (55625, 55670), True, 'import valentyusb.usbcore.io as usbio\n'), ((56265, 56341), 'litex.soc.cores.uart.UART', 'uart.UART', (['self.uart_phy'], {'tx_fifo_depth': 'fifo_depth', 'rx_fifo_depth': 'fifo_depth'}), '(self.uart_phy, tx_fifo_depth=fifo_depth, rx_fifo_depth=fifo_depth)\n', (56274, 56341), False, 'from litex.soc.cores import uart\n'), ((55968, 55995), 'valentyusb.usbcore.cpu.cdc_eptri.CDCUsb', 'cdc_eptri.CDCUsb', (['usb_iobuf'], {}), '(usb_iobuf)\n', (55984, 55995), True, 'import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri\n')] |
import argparse
import os
import sys
import threading
from litex.tools.litex_server import RemoteServer
from litex.tools.litex_client import RemoteClient
TOP_DIR=os.path.join(os.path.dirname(__file__), "..")
sys.path.append(TOP_DIR)
from make import get_args, get_testdir
class ServerProxy(threading.Thread):
daemon = True
def __init__(self, args):
threading.Thread.__init__(self)
self.args = args
self.ready = False
def run(self):
args = self.args
if args.uart:
from litex.tools.remote.comm_uart import CommUART
if args.uart_port is None:
print("Need to specify --uart-port, exiting.")
exit()
uart_port = args.uart_port
uart_baudrate = int(float(args.uart_baudrate))
print("[CommUART] port: {} / baudrate: {} / ".format(uart_port, uart_baudrate), end="")
comm = CommUART(uart_port, uart_baudrate)
elif args.udp:
from litex.tools.remote.comm_udp import CommUDP
udp_ip = args.udp_ip
udp_port = int(args.udp_port)
print("[CommUDP] ip: {} / port: {} / ".format(udp_ip, udp_port), end="")
comm = CommUDP(udp_ip, udp_port)
elif args.pcie:
from litex.tools.remote.comm_pcie import CommPCIe
pcie_bar = args.pcie_bar
if args.pcie_bar is None:
print("Need to speficy --pcie-bar, exiting.")
exit()
print("[CommPCIe] bar: {} / ".format(args.pcie_bar), end="")
comm = CommPCIe(args.pcie_bar)
elif args.usb:
from litex.tools.remote.comm_usb import CommUSB
if args.usb_pid is None and args.usb_vid is None:
print("Need to speficy --usb-vid or --usb-pid, exiting.")
exit()
print("[CommUSB] vid: {} / pid: {} / ".format(args.usb_vid, args.usb_pid), end="")
pid = args.usb_pid
if pid is not None:
pid = int(pid, base=0)
vid = args.usb_vid
if vid is not None:
vid = int(vid, base=0)
comm = CommUSB(vid=vid, pid=pid, max_retries=args.usb_max_retries)
else:
exit()
self.server = RemoteServer(comm, args.bind_ip, int(args.bind_port))
self.server.open()
self.server.start(4)
self.ready = True
def connect(desc, *args, add_args=None, **kw):
parser = argparse.ArgumentParser(description=desc)
get_args(parser, *args, **kw)
# Common arguments
parser.add_argument("--bind-ip", default="localhost",
help="Host bind address")
parser.add_argument("--bind-port", default=1234,
help="Host bind port")
# UART arguments
parser.add_argument("--uart", action="store_true",
help="Select UART interface")
parser.add_argument("--uart-port", default=None,
help="Set UART port")
#parser.add_argument("--uart-baudrate", default=115200,
# help="Set UART baudrate")
# UDP arguments
parser.add_argument("--udp", action="store_true",
help="Select UDP interface")
parser.add_argument("--udp-ip", default="192.168.100.50",
help="Set UDP remote IP address")
parser.add_argument("--udp-port", default=1234,
help="Set UDP remote port")
# PCIe arguments
parser.add_argument("--pcie", action="store_true",
help="Select PCIe interface")
parser.add_argument("--pcie-bar", default=None,
help="Set PCIe BAR")
# USB arguments
parser.add_argument("--usb", action="store_true",
help="Select USB interface")
parser.add_argument("--usb-vid", default=None,
help="Set USB vendor ID")
parser.add_argument("--usb-pid", default=None,
help="Set USB product ID")
parser.add_argument("--usb-max-retries", default=10,
help="Number of times to try reconnecting to USB")
if add_args is not None:
add_args(parser)
args = parser.parse_args()
s = ServerProxy(args)
s.start()
while not s.ready:
continue
test_dir = os.path.join(TOP_DIR, get_testdir(args))
wb = RemoteClient(args.bind_ip, int(args.bind_port), csr_csv="{}/csr.csv".format(test_dir), debug=True)
wb.open()
print()
print("Device DNA: {}".format(get_dna(wb)))
print(" Git Rev: {}".format(get_git(wb)))
print(" Platform: {}".format(get_platform(wb)))
print(" Analyzer: {}".format(["No", "Yes"][hasattr(wb.regs, "analyzer")]))
print(" XADC: {}".format(get_xadc(wb)))
print()
return args, wb
def print_memmap(wb):
print("Memory Map")
print("-"*20)
for n, mem in sorted(wb.mems.d.items(), key=lambda i: i[1].base):
mb = mem.size/1024/1024
if mb > 1.0:
extra_str = " ({:4} Mbytes)".format(int(mb))
else:
extra_str = ""
print("{:20} @ 0x{:08x} -- {: 12} kbytes {}".format(n, mem.base, int(mem.size/1024), extra_str))
def get_dna(wb):
try:
dna = wb.regs.info_dna_id.read()
return hex(dna)
except (KeyError, AttributeError) as e:
return 'Unknown'
def get_git(wb):
try:
commit = wb.regs.info_git_commit.read()
return hex(commit)[2:]
except (KeyError, AttributeError) as e:
return 'Unknown'
# xadc stuff
def xadc2volts(v):
return (v/4096.0*3)
def xadc2c(v):
return (v*503.975/4096 - 273.15)
def get_xadc(wb):
try:
temp = xadc2c(wb.regs.xadc_temperature.read())
vccaux = xadc2volts(wb.regs.xadc_vccaux.read())
vccbram = xadc2volts(wb.regs.xadc_vccbram.read())
vccint = xadc2volts(wb.regs.xadc_vccint.read())
return "{:.1f}°C -- vccint: {:.2f}V vccaux: {:.2f}V vccbram: {:.2f}V".format(
temp, vccaux, vccbram, vccint)
except (KeyError, AttributeError) as e:
return 'Unknown'
def stringify(reg):
d = reg.read()
chars = []
for i in range(0, reg.length):
b = (d >> (8 * i)) & 0xff
if b > 0:
chars.append(chr(b))
chars.reverse()
return ''.join(chars)
def get_platform(wb):
try:
target = stringify(wb.regs.info_platform_target)
platform = stringify(wb.regs.info_platform_platform)
return "{} on {}".format(target, platform)
except (KeyError, AttributeError) as e:
return 'Unknown on Unknown'
def write_and_check(reg, value):
reg.write(value)
r = reg.read()
assert r == value, "Wanted {}, got {}".format(value, r)
def memdump(wb, start, length):
data = wb.read(start, length)
for i, d in enumerate(data):
address = i*4 + start
if address % 32 == 0:
print()
print("0x{:04x} ".format(address), sep=' ', end='')
for b in struct.pack('>I', d):
print("{:02x}".format(b), end=' ')
import struct
BLOCK_SIZE=64
def cmpflash(wb, start, filename, skip=0, max=1024):
assert skip%4==0
with open(filename, 'rb') as f:
local_data=f.read()[:skip+max]
j = skip
while j < len(local_data):
mem_data_len = min(BLOCK_SIZE, len(local_data)-j)
mem_data = b"".join(struct.pack('>I', k) for k in wb.read(start+j, mem_data_len))
for i in range(0, mem_data_len):
addr, expected, actual = j+i+start, local_data[j+i], mem_data[i]
if addr % 8 == 0:
print()
print("0x{:08x} ".format(addr), sep=' ', end='')
if expected != actual:
print()
print("{:08x} {:02x} != {:02x}".format(addr, expected, actual))
else:
print(".", end="", flush=True)
j += BLOCK_SIZE
| [
"litex.tools.remote.comm_uart.CommUART",
"litex.tools.remote.comm_pcie.CommPCIe",
"litex.tools.remote.comm_usb.CommUSB",
"litex.tools.remote.comm_udp.CommUDP"
] | [((212, 236), 'sys.path.append', 'sys.path.append', (['TOP_DIR'], {}), '(TOP_DIR)\n', (227, 236), False, 'import sys\n'), ((178, 203), 'os.path.dirname', 'os.path.dirname', (['__file__'], {}), '(__file__)\n', (193, 203), False, 'import os\n'), ((2486, 2527), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': 'desc'}), '(description=desc)\n', (2509, 2527), False, 'import argparse\n'), ((2532, 2561), 'make.get_args', 'get_args', (['parser', '*args'], {}), '(parser, *args, **kw)\n', (2540, 2561), False, 'from make import get_args, get_testdir\n'), ((372, 403), 'threading.Thread.__init__', 'threading.Thread.__init__', (['self'], {}), '(self)\n', (397, 403), False, 'import threading\n'), ((4383, 4400), 'make.get_testdir', 'get_testdir', (['args'], {}), '(args)\n', (4394, 4400), False, 'from make import get_args, get_testdir\n'), ((7042, 7062), 'struct.pack', 'struct.pack', (['""">I"""', 'd'], {}), "('>I', d)\n", (7053, 7062), False, 'import struct\n'), ((927, 961), 'litex.tools.remote.comm_uart.CommUART', 'CommUART', (['uart_port', 'uart_baudrate'], {}), '(uart_port, uart_baudrate)\n', (935, 961), False, 'from litex.tools.remote.comm_uart import CommUART\n'), ((1224, 1249), 'litex.tools.remote.comm_udp.CommUDP', 'CommUDP', (['udp_ip', 'udp_port'], {}), '(udp_ip, udp_port)\n', (1231, 1249), False, 'from litex.tools.remote.comm_udp import CommUDP\n'), ((7421, 7441), 'struct.pack', 'struct.pack', (['""">I"""', 'k'], {}), "('>I', k)\n", (7432, 7441), False, 'import struct\n'), ((1588, 1611), 'litex.tools.remote.comm_pcie.CommPCIe', 'CommPCIe', (['args.pcie_bar'], {}), '(args.pcie_bar)\n', (1596, 1611), False, 'from litex.tools.remote.comm_pcie import CommPCIe\n'), ((2172, 2231), 'litex.tools.remote.comm_usb.CommUSB', 'CommUSB', ([], {'vid': 'vid', 'pid': 'pid', 'max_retries': 'args.usb_max_retries'}), '(vid=vid, pid=pid, max_retries=args.usb_max_retries)\n', (2179, 2231), False, 'from litex.tools.remote.comm_usb import CommUSB\n')] |
# This file is Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2017 <NAME> <<EMAIL>>
# License: BSD
import os
import sys
import subprocess
from migen.fhdl.structure import _Fragment
from litex.build import tools
from litex.build.generic_platform import *
sim_directory = os.path.abspath(os.path.dirname(__file__))
core_directory = os.path.join(sim_directory, 'core')
def _generate_sim_h_struct(name, index, siglist):
content = ''
content += 'struct pad_s {}{}[] = {{\n'.format(name, index)
for signame, sigbits, dummy in siglist:
content += ' {{ (char*)"{}", {}, NULL }},\n'.format(signame, sigbits)
content += ' { NULL, 0, NULL }\n'
content += '};\n\n'
return content
def _generate_sim_h(platform):
content = """\
#ifndef __SIM_CORE_H_
#define __SIM_CORE_H_
#include "pads.h"
"""
for args in platform.sim_requested:
content += _generate_sim_h_struct(*args)
content += """\
#ifndef __cplusplus
void litex_sim_init(void **out);
#endif
#endif /* __SIM_CORE_H_ */
"""
tools.write_to_file("dut_header.h", content)
def _generate_sim_cpp_struct(name, index, siglist):
content = ''
for i, (signame, sigbits, sigfname) in enumerate(siglist):
content += ' {}{}[{}].signal = &dut->{};\n'.format(name, index, i, sigfname)
idx_int = 0 if not index else int(index)
content += ' litex_sim_register_pads({}{}, (char*)"{}", {});\n\n'.format(name, index, name, idx_int)
return content
def _generate_sim_cpp(platform, trace=False, trace_start=0, trace_end=-1):
content = """\
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "Vdut.h"
#include <verilated.h>
#include "dut_header.h"
extern "C" void litex_sim_init_tracer(void *vdut, long start, long end);
extern "C" void litex_sim_tracer_dump();
extern "C" void litex_sim_dump()
{
"""
if trace:
content += """\
litex_sim_tracer_dump();
"""
content += """\
}}
extern "C" void litex_sim_init(void **out)
{{
Vdut *dut;
dut = new Vdut;
litex_sim_init_tracer(dut, {},{});
""".format(trace_start, trace_end)
for args in platform.sim_requested:
content += _generate_sim_cpp_struct(*args)
content += """\
*out=dut;
}
"""
tools.write_to_file("dut_init.cpp", content)
def _generate_sim_variables(include_paths):
include = ""
for path in include_paths:
include += "-I"+path+" "
content = """\
SRC_DIR = {}
INC_DIR = {}
""".format(core_directory, include)
tools.write_to_file("variables.mak", content)
def _generate_sim_config(config):
content = config.get_json()
tools.write_to_file("sim_config.js", content)
def _build_sim(build_name, sources, threads, coverage, opt_level="O3"):
makefile = os.path.join(core_directory, 'Makefile')
cc_srcs = []
for filename, language, library in sources:
cc_srcs.append("--cc " + filename + " ")
build_script_contents = """\
rm -rf obj_dir/
make -C . -f {} {} {} {} {}
mkdir -p modules && cp obj_dir/*.so modules
""".format(makefile,
"CC_SRCS=\"{}\"".format("".join(cc_srcs)),
"THREADS={}".format(threads) if int(threads) > 1 else "",
"COVERAGE=1" if coverage else "",
"OPT_LEVEL={}".format(opt_level),
)
build_script_file = "build_" + build_name + ".sh"
tools.write_to_file(build_script_file, build_script_contents, force_unix=True)
def _compile_sim(build_name, verbose):
build_script_file = "build_" + build_name + ".sh"
p = subprocess.Popen(["bash", build_script_file], stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
output, _ = p.communicate()
output = output.decode('utf-8')
if p.returncode != 0:
error_messages = []
for l in output.splitlines():
if verbose or "error" in l.lower():
error_messages.append(l)
raise OSError("Subprocess failed with {}\n{}".format(p.returncode, "\n".join(error_messages)))
if verbose:
print(output)
def _run_sim(build_name, as_root=False):
run_script_contents = "sudo " if as_root else ""
run_script_contents += "obj_dir/Vdut"
run_script_file = "run_" + build_name + ".sh"
tools.write_to_file(run_script_file, run_script_contents, force_unix=True)
if sys.platform != "win32":
import termios
termios_settings = termios.tcgetattr(sys.stdin.fileno())
try:
r = subprocess.call(["bash", run_script_file])
if r != 0:
raise OSError("Subprocess failed")
except:
pass
if sys.platform != "win32":
termios.tcsetattr(sys.stdin.fileno(), termios.TCSAFLUSH, termios_settings)
class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", build=True, run=True, threads=1,
verbose=True, sim_config=None, coverage=False, opt_level="O0",
trace=False, trace_start=0, trace_end=-1):
# create build directory
os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir)
if build:
# finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# generate top module
top_output = platform.get_verilog(fragment,
name=build_name, dummy_signal=False, regular_comb=False, blocking_assign=True)
named_sc, named_pc = platform.resolve_signals(top_output.ns)
top_file = build_name + ".v"
top_output.write(top_file)
platform.add_source(top_file)
# generate cpp header/main/variables
_generate_sim_h(platform)
_generate_sim_cpp(platform, trace, trace_start, trace_end)
_generate_sim_variables(platform.verilog_include_paths)
# generate sim config
if sim_config:
_generate_sim_config(sim_config)
# build
_build_sim(build_name, platform.sources, threads, coverage, opt_level)
# run
if run:
_compile_sim(build_name, verbose)
_run_sim(build_name, as_root=sim_config.has_module("ethernet"))
os.chdir("../../")
if build:
return top_output.ns | [
"litex.build.tools.write_to_file"
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#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# License: BSD
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores import up5kspram
from litex.soc.integration import SoCCore
from litex.soc.integration.builder import Builder, builder_argdict, builder_args
from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
from valentyusb.usbcore import io as usbio
from valentyusb.usbcore.cpu import dummyusb, epfifo
import os, shutil, subprocess
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform):
clk48_raw = platform.request("clk48")
clk12 = Signal()
reset_delay = Signal(12, reset=4095)
self.clock_domains.cd_por = ClockDomain()
self.reset = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
platform.add_period_constraint(clk48_raw, 1e9/48e6)
# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
# reset.
self.comb += [
self.cd_por.clk.eq(self.cd_sys.clk),
self.cd_sys.rst.eq(reset_delay != 0),
self.cd_usb_12.rst.eq(reset_delay != 0),
]
# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
# reset.
self.comb += [
self.cd_usb_48.rst.eq(reset_delay != 0),
]
self.comb += self.cd_usb_48.clk.eq(clk48_raw)
self.specials += Instance(
"SB_PLL40_CORE",
# Parameters
p_DIVR = 0,
p_DIVF = 15,
p_DIVQ = 5,
p_FILTER_RANGE = 1,
p_FEEDBACK_PATH = "SIMPLE",
p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
p_FDA_FEEDBACK = 15,
p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
p_FDA_RELATIVE = 0,
p_SHIFTREG_DIV_MODE = 1,
p_PLLOUT_SELECT = "GENCLK_HALF",
p_ENABLE_ICEGATE = 0,
# IO
i_REFERENCECLK = clk48_raw,
o_PLLOUTCORE = clk12,
# o_PLLOUTGLOBAL = clk12,
#i_EXTFEEDBACK,
#i_DYNAMICDELAY,
#o_LOCK,
i_BYPASS = 0,
i_RESETB = 1,
#i_LATCHINPUTVALUE,
#o_SDO,
#i_SDI,
)
self.comb += self.cd_sys.clk.eq(clk12)
self.comb += self.cd_usb_12.clk.eq(clk12)
self.sync.por += \
If(reset_delay != 0,
reset_delay.eq(reset_delay - 1)
)
self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
"""A SoC on Fomu, optionally with a softcore CPU"""
# Create a default CSR map to prevent values from getting reassigned.
# This increases consistency across litex versions.
SoCCore.csr_map = {
"ctrl": 0, # provided by default (optional)
"crg": 1, # user
"uart_phy": 2, # provided by default (optional)
"uart": 3, # provided by default (optional)
"identifier_mem": 4, # provided by default (optional)
"timer0": 5, # provided by default (optional)
"cpu_or_bridge": 8,
"usb": 9,
"picorvspi": 10,
"touch": 11,
"reboot": 12,
"rgb": 13,
"version": 14,
}
# Statically-define the memory map, to prevent it from shifting across
# various litex versions.
SoCCore.mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0xa0000000)
"spiflash": 0x20000000, # (default shadow @0xa0000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"csr": 0x60000000, # (default shadow @0xe0000000)
}
def __init__(self, board,
pnr_placer="heap", pnr_seed=0, usb_core="dummyusb", usb_bridge=False,
**kwargs):
"""Create a basic SoC for Fomu.
Create a basic SoC for Fomu, including a 48 MHz and 12 MHz clock
domain called `usb_48` and `usb_12`. The `sys` frequency will
run at 12 MHz.
The USB core will optionally have a bridge to the Wishbone bus.
Args:
board (str): Which Fomu board to build for: pvt, evt, or hacker
pnr_placer (str): Which placer to use in nextpnr
pnr_seed (int): Which seed to use in nextpnr
usb_core (str): The name of the USB core to use, if any: dummyusb, epfifo
usb_bridge (bool): Whether to include a USB-to-Wishbone bridge
Raises:
ValueError: If either the `usb_core` or `board` are unrecognized
Returns:
Newly-constructed SoC
"""
if board == "pvt":
from litex_boards.partner.platforms.fomu_pvt import Platform
elif board == "hacker":
from litex_boards.partner.platforms.fomu_hacker import Platform
elif board == "evt":
from litex_boards.partner.platforms.fomu_evt import Platform
else:
raise ValueError("unrecognized fomu board: {}".format(board))
platform = Platform()
if "cpu_type" not in kwargs:
kwargs["cpu_type"] = None
kwargs["cpu_variant"] = None
clk_freq = int(12e6)
SoCCore.__init__(self, platform, clk_freq,
integrated_sram_size=0,
with_uart=False,
with_ctrl=False,
**kwargs)
self.submodules.crg = _CRG(platform)
# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
# Use this as CPU RAM.
spram_size = 128*1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
if usb_core is not None:
# Add USB pads. We use DummyUsb, which simply enumerates as a USB
# device. Then all interaction is done via the wishbone bridge.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if usb_core == "dummyusb":
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_bridge)
elif usb_core == "epfifo":
self.submodules.usb = epfifo.PerEndpointFifo(usb_iobuf, debug=usb_bridge)
else:
raise ValueError("unrecognized usb_core: {}".args(usb_core))
if usb_bridge:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# "-reult" adds an additional LUT pass to pack more stuff in, and
# "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[2] += " -relut -dffe_min_ce_use 4"
# Allow us to set the nextpnr seed, because some values don't meet timing.
platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed)
# Different placers can improve packing efficiency, however not all placers
# are enabled on all builds of nextpnr-ice40. Let the user override which
# placer they want to use.
if pnr_placer is not None:
platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(pnr_placer)
class USBSoC(BaseSoC):
"""A SoC for Fomu with interrupts for a softcore CPU"""
interrupt_map = {
"usb": 3,
}
interrupt_map.update(SoCCore.interrupt_map)
# Build --------------------------------------------------------------------------------------------
def add_dfu_suffix(fn):
fn_base, _ext = os.path.splitext(fn)
fn_dfu = fn_base + '.dfu'
shutil.copyfile(fn, fn_dfu)
subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu])
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
parser.add_argument(
"--board", choices=["evt", "pvt", "hacker"], required=True,
help="build for a particular hardware board"
)
parser.add_argument(
"--seed", default=0, help="seed to use in nextpnr"
)
parser.add_argument(
"--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr"
)
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed,
debug=True, **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build()
if __name__ == "__main__":
main()
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#
# This file is part of LiteX-Boards.
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2022 Lone Dynamics Corporation <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Krote FPGA board: https://github.com/machdyne/krote
#
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("B6"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("E2 F1 G2 J2"), IOStandard("LVCMOS33")),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("K10"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("L10"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("K9"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("J9"), IOStandard("LVCMOS33")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("PMODA", "E1 B1 A2 A4 D1 C1 A1 A3"),
("PMODB", "L3 L1 H1 G3 L2 K1 J1 F2"),
("PMODC", "A8 A10 C11 A9 D10 B11 D11"),
("PMODD", "E9 G10 F10 H11 E11 G11 G9"),
("PMODE", "L8 K5 K3 L5 L7 K4 K2 L4")
]
# Default peripherals
serial = [
("serial", 0,
Subsignal("tx", Pins("PMODE:1")),
Subsignal("rx", Pins("PMODE:2")),
IOStandard("LVCMOS33")
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="icestorm"):
LatticePlatform.__init__(self, "ice40-hx8k-bg121", _io, _connectors, toolchain=toolchain)
self.add_extension(serial)
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
# Copyright (C) 2022 Antmicro
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
from migen import Module, Signal, ClockDomain
from migen.fhdl.structure import ClockSignal, ResetSignal
from litex.build.sim.platform import SimPlatform
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.integration.soc_core import SoCCore
from litex.soc.integration.builder import Builder
from litex.soc.interconnect import wishbone
from fifo_transceiver import TestFIFOTransceiver
import argparse
_io = [
# Wishbone
("wishbone", 0,
Subsignal("adr", Pins(30)),
Subsignal("dat_r", Pins(32)),
Subsignal("dat_w", Pins(32)),
Subsignal("sel", Pins(4)),
Subsignal("cyc", Pins(1)),
Subsignal("stb", Pins(1)),
Subsignal("ack", Pins(1)),
Subsignal("we", Pins(1)),
Subsignal("cti", Pins(3)),
Subsignal("bte", Pins(2)),
Subsignal("err", Pins(1))),
("fifo", 0,
Subsignal("dat_rx", Pins(32)),
Subsignal("dat_tx", Pins(32)),
Subsignal("stb_rx", Pins(1)),
Subsignal("stb_tx", Pins(1)),
Subsignal("wait_rx", Pins(1)),
Subsignal("wait_tx", Pins(1))),
("sram", 0,
Subsignal("adr", Pins(6)),
Subsignal("dat_r", Pins(32)),
Subsignal("dat_w", Pins(32)),
Subsignal("we", Pins(1))),
("clk", 0, Pins(1)),
("reset", 0, Pins(1)),
]
_connectors = []
class _CRG(Module):
def __init__(self, platform):
clk = platform.request("clk")
rst = ~platform.request("reset")
self.clock_domains.cd_sys = ClockDomain()
self.comb += [
ClockSignal("sys").eq(clk),
ResetSignal("sys").eq(rst),
]
class Platform(SimPlatform):
def __init__(self, toolchain="verilator"):
SimPlatform.__init__(self, "sim",
_io, _connectors,
toolchain=toolchain)
def create_programmer(self):
raise ValueError("Programming is not supported")
def copy_layout_directions(source, target):
# update target.layout direction values from source.layout
# as _io does not provide them
for i, (name, width) in enumerate(target.layout):
found = list(filter(lambda entry: entry[0] == name, source.layout))
assert len(found) == 1, 'Layout element not found in source: ' + name
direction = found[0][2]
target.layout[i] = (name, width, direction)
class BaseSoC(SoCCore):
SoCCore.csr_map = {
"ctrl": 0, # provided by default (optional)
"crg": 1, # user
"uart_phy": 2, # provided by default (optional)
"uart": 3, # provided by default (optional)
"identifier_mem": 4, # provided by default (optional)
"timer0": 5, # provided by default (optional)
}
SoCCore.mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0xa0000000)
"spiflash": 0x20000000, # (default shadow @0xa0000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"fifo": 0xd0000000,
"csr": 0xe0000000,
}
def __init__(self, platform, output_dir="build", **kwargs):
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None, integrated_rom_size=0x0,
integrated_sram_size=0x100,
bus_bursting=True,
integrated_main_ram_size=0x0,
csr_address_width=14, csr_data_width=32,
with_uart=False, with_timer=False
)
class _WishboneBridge(Module):
def __init__(self, interface):
self.wishbone = interface
# expose wishbone master for simulation purpose
sim_wishbone = wishbone.Interface()
# connect wishbone to io pins
wb = self.platform.request('wishbone')
copy_layout_directions(source=sim_wishbone, target=wb)
self.comb += wb.connect(sim_wishbone)
self.add_wb_master(sim_wishbone)
# SRAM port
sram_pins = self.platform.request('sram')
sram_port = self.sram.mem.get_port(write_capable=True)
self.specials += sram_port
self.comb += [
sram_port.adr.eq(sram_pins.adr),
sram_port.dat_w.eq(sram_pins.dat_w),
sram_pins.dat_r.eq(sram_port.dat_r),
sram_port.we.eq(sram_pins.we),
]
# FIFO
fifo_pins = self.platform.request('fifo')
self.submodules.fifo = TestFIFOTransceiver(fifo_pins, 8)
self.add_memory_region("fifo", self.mem_map["fifo"], self.bus.data_width//8, type=[])
self.add_wb_slave(self.mem_map["fifo"], self.fifo.bus)
def generate(output_dir, csr_csv):
platform = Platform()
soc = BaseSoC(platform, cpu_type=None, cpu_variant=None,
output_dir=output_dir
)
builder = Builder(soc, output_dir=output_dir,
csr_csv=csr_csv, compile_software=False
)
vns = builder.build(run=False, build_name="dut")
soc.do_exit(vns)
def main():
parser = argparse.ArgumentParser(
description="Build test file for SRAM")
parser.add_argument('--dir',
metavar='DIRECTORY',
default='build',
help='Output directory (defauilt: %(default)s)')
parser.add_argument('--csr',
metavar='CSR',
default='csr.csv',
help='csr file (default: %(default)s)')
args = parser.parse_args()
output_dir = args.dir
generate(output_dir, args.csr)
print("""Simulation build complete. Output files:
{}/gateware/dut.v Source Verilog file. Run this under Cocotb.
""".format(output_dir))
if __name__ == "__main__":
main()
| [
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.builder.Builder",
"litex.build.generic_platform.Pins",
"litex.build.sim.platform.SimPlatform.__init__"
] | [((5523, 5599), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'output_dir': 'output_dir', 'csr_csv': 'csr_csv', 'compile_software': '(False)'}), '(soc, output_dir=output_dir, csr_csv=csr_csv, compile_software=False)\n', (5530, 5599), False, 'from litex.soc.integration.builder import Builder\n'), ((5746, 5809), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build test file for SRAM"""'}), "(description='Build test file for SRAM')\n", (5769, 5809), False, 'import argparse\n'), ((1792, 1799), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (1796, 1799), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((1819, 1826), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (1823, 1826), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((2021, 2034), 'migen.ClockDomain', 'ClockDomain', ([], {}), '()\n', (2032, 2034), False, 'from migen import Module, Signal, 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(['"""sys"""'], {}), "('sys')\n", (2082, 2089), False, 'from migen.fhdl.structure import ClockSignal, ResetSignal\n'), ((2111, 2129), 'migen.fhdl.structure.ResetSignal', 'ResetSignal', (['"""sys"""'], {}), "('sys')\n", (2122, 2129), False, 'from migen.fhdl.structure import ClockSignal, ResetSignal\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
from shutil import which
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.quicklogic import common
# IO Constraints (.pcf) ----------------------------------------------------------------------------
def _format_io_pcf(signame, pin, others):
r = f"set_io {signame} {Pins(pin).identifiers[0]}\n"
return r
def _build_io_pcf(named_sc, named_pc, build_name):
pcf = ""
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
pcf += _format_io_pcf(sig + "(" + str(i) + ")", p, others)
else:
pcf += _format_io_pcf(sig, pins[0], others)
tools.write_to_file(build_name + ".pcf", pcf)
# Build Makefile -----------------------------------------------------------------------------------
def _build_makefile(platform, sources, build_dir, build_name):
makefile = []
# Define Paths.
makefile.append("mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))")
makefile.append("current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))")
# Create Project.
# FIXME: Only use top file for now and ignore .init files.
makefile.append("all:")
makefile.append("\tql_symbiflow -compile -d {device} -P {part} -v {verilog} -t {top} -p {pcf}".format(
device = platform.device,
part = {"ql-eos-s3": "pd64"}.get(platform.device),
verilog = f"{build_name}.v",
top = build_name,
pcf = f"{build_name}.pcf"
))
# Generate Makefile.
tools.write_to_file("Makefile", "\n".join(makefile))
def _run_make():
make_cmd = ["make", "-j1"]
if which("ql_symbiflow") is None:
msg = "Unable to find QuickLogic Symbiflow toolchain, please:\n"
msg += "- Add QuickLogic Symbiflow toolchain to your $PATH."
raise OSError(msg)
if subprocess.call(make_cmd) != 0:
raise OSError("Error occured during QuickLogic Symbiflow's script execution.")
# SymbiflowToolchain -------------------------------------------------------------------------------
class SymbiflowToolchain:
attr_translate = {}
special_overrides = common.quicklogic_special_overrides
def __init__(self):
self.clocks = dict()
self.false_paths = set()
def build(self, platform, fragment,
build_dir = "build",
build_name = "top",
run = False,
**kwargs):
# Create build directory.
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
# Finalize design.
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# Generate verilog.
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
top_file = build_name + ".v"
v_output.write(top_file)
platform.add_source(top_file)
# Generate .pcf IO constraints file.
_build_io_pcf(named_sc, named_pc, build_name)
# Generate Makefie.
_build_makefile(platform, platform.sources, build_dir, build_name)
# Run.
if run:
_run_make()
os.chdir(cwd)
return v_output.ns
| [
"litex.build.tools.write_to_file"
] | [((882, 927), 'litex.build.tools.write_to_file', 'tools.write_to_file', (["(build_name + '.pcf')", 'pcf'], {}), "(build_name + '.pcf', pcf)\n", (901, 927), False, 'from litex.build import tools\n'), ((1858, 1879), 'shutil.which', 'which', (['"""ql_symbiflow"""'], {}), "('ql_symbiflow')\n", (1863, 1879), False, 'from shutil import which\n'), ((2066, 2091), 'subprocess.call', 'subprocess.call', (['make_cmd'], {}), '(make_cmd)\n', (2081, 2091), False, 'import subprocess\n'), ((2697, 2734), 'os.makedirs', 'os.makedirs', (['build_dir'], {'exist_ok': '(True)'}), '(build_dir, exist_ok=True)\n', (2708, 2734), False, 'import os\n'), ((2749, 2760), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (2758, 2760), False, 'import os\n'), ((2769, 2788), 'os.chdir', 'os.chdir', (['build_dir'], {}), '(build_dir)\n', (2777, 2788), False, 'import os\n'), ((3498, 3511), 'os.chdir', 'os.chdir', (['cwd'], {}), '(cwd)\n', (3506, 3511), False, 'import os\n')] |
#
# This file is part of LiteX-Boards.
# FPGA Board Info : http://www.e-elements.com/product/show/id/11.shtml
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("P17"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("P15"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("K3"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("M1"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("L1"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("K6"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("J5"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("H5"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("H6"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("K1"), IOStandard("LVCMOS33")),
("user_led", 8, Pins("K2"), IOStandard("LVCMOS33")),
("user_led", 9, Pins("J2"), IOStandard("LVCMOS33")),
("user_led", 10, Pins("J3"), IOStandard("LVCMOS33")),
("user_led", 11, Pins("H4"), IOStandard("LVCMOS33")),
("user_led", 12, Pins("J4"), IOStandard("LVCMOS33")),
("user_led", 13, Pins("G3"), IOStandard("LVCMOS33")),
("user_led", 14, Pins("G4"), IOStandard("LVCMOS33")),
("user_led", 15, Pins("F6"), IOStandard("LVCMOS33")),
# Switches
("user_sw", 0, Pins("R1"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("N4"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("M4"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("R2"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("P2"), IOStandard("LVCMOS33")),
("user_sw", 5, Pins("P3"), IOStandard("LVCMOS33")),
("user_sw", 6, Pins("P4"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("P5"), IOStandard("LVCMOS33")),
("user_sw", 8, Pins("T5"), IOStandard("LVCMOS33")),
("user_sw", 9, Pins("T3"), IOStandard("LVCMOS33")),
("user_sw", 10, Pins("R3"), IOStandard("LVCMOS33")),
("user_sw", 11, Pins("V4"), IOStandard("LVCMOS33")),
("user_sw", 12, Pins("V5"), IOStandard("LVCMOS33")),
("user_sw", 13, Pins("V2"), IOStandard("LVCMOS33")),
("user_sw", 14, Pins("U2"), IOStandard("LVCMOS33")),
("user_sw", 15, Pins("U3"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("R11"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("R17"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("R15"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("V1"), IOStandard("LVCMOS33")),
("user_btn", 4, Pins("U4"), IOStandard("LVCMOS33")),
# Seven Segment
("seven_seg_ctl", 0, Pins("G2"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 1, Pins("C2"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 2, Pins("C1"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 3, Pins("H1"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 4, Pins("G1"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 5, Pins("F1"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 6, Pins("E1"), IOStandard("LVCMOS33")),
("seven_seg_ctl", 7, Pins("G6"), IOStandard("LVCMOS33")),
("seven_seg", 0, Pins("B4 A4 A3 B1 A1 B3 B2 D5"), IOStandard("LVCMOS33")),
("seven_seg", 1, Pins("D4 E3 D3 F4 F3 E2 D2 H2"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("T4")),
Subsignal("rx", Pins("N5")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("E9")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("E9")),
Subsignal("dq", Pins("K17 K18 L14 M14")),
IOStandard("LVCMOS33")
),
# VGA
("vga", 0,
Subsignal("r", Pins("F5 C6 C5 B7")),
Subsignal("g", Pins("B6 A6 A5 D8")),
Subsignal("b", Pins("C7 E6 E5 E7")),
Subsignal("hsync", Pins("D7")),
Subsignal("vsync", Pins("C4")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("j5", "B16 B17 A15 A16 A13 A14 A18 B18",
"F13 F14 B13 B14 C14 D14 A11 B11",
"E15 E16 D15 C15 H16 G16 F15 F16",
"H14 G14 E17 D17 K13 J13 H17 G17",),
]
# PMODS --------------------------------------------------------------------------------------------
'''
# SPI
("spi", 0,
Subsignal("clk", Pins("F1")),
Subsignal("cs_n", Pins("C1")),
Subsignal("mosi", Pins("H1")),
Subsignal("miso", Pins("G1")),
IOStandard("LVCMOS33"),
),
# I2C
("i2c", 0,
Subsignal("scl", Pins("L18")),
Subsignal("sda", Pins("M18")),
Subsignal("scl_pup", Pins("A14")),
Subsignal("sda_pup", Pins("A13")),
IOStandard("LVCMOS33"),
),
'''
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a35ticsg324-1L", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16"
" -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks UCIO-1]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((5476, 5569), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35ticsg324-1L"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7a35ticsg324-1L', _io, _connectors,\n toolchain=toolchain)\n", (5499, 5569), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((6019, 6077), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a35t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a35t.bit')\n", (6026, 6077), False, 'from litex.build.openocd import OpenOCD\n'), ((6124, 6166), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (6150, 6166), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# Copyright (c) 2014-2015 <NAME> <<EMAIL>>
# Copyright (c) 2014-2020 <NAME> <<EMAIL>>
# Copyright (c) 2014-2015 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex_boards.platforms import aliexpress_stlv7325
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster
from litedram.modules import MT8JTF12864
from litedram.phy import s7ddrphy
from liteeth.phy import LiteEthPHY
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain()
self.clock_domains.cd_idelay = ClockDomain()
# # #
# Clk/Rst.
clk200 = platform.request("clk200")
rst_n = platform.request("cpu_reset_n")
# PLL.
self.submodules.pll = pll = S7MMCM(speedgrade=-2)
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk200, 200e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6),
with_ethernet = False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_led_chaser = True,
with_pcie = False,
with_sata = False,
**kwargs):
platform = aliexpress_stlv7325.Platform()
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on AliExpress STLV7325", **kwargs)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq,
)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT8JTF12864(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHY(
clock_pads = self.platform.request("eth_clocks", 0),
pads = self.platform.request("eth", 0),
clk_freq = self.clk_freq)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# PCIe -------------------------------------------------------------------------------------
if with_pcie:
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
data_width = 128,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# TODO verify / test
# SATA -------------------------------------------------------------------------------------
if with_sata:
from litex.build.generic_platform import Subsignal, Pins
from litesata.phy import LiteSATAPHY
# RefClk, Generate 150MHz from PLL.
self.clock_domains.cd_sata_refclk = ClockDomain()
self.crg.pll.create_clkout(self.cd_sata_refclk, 150e6)
sata_refclk = ClockSignal("sata_refclk")
platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-52]")
# PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = sata_refclk,
pads = platform.request("sata", 0),
gen = "gen2",
clk_freq = sys_clk_freq,
data_width = 16)
# Core
self.add_sata(phy=self.sata_phy, mode="read+write")
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
# I2C --------------------------------------------------------------------------------------
self.submodules.i2c = I2CMaster(platform.request("i2c"))
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on AliExpress STLV7325")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
target_group.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
target_group.add_argument("--with-sata", action="store_true", help="Enable SATA support.")
sdopts = target_group.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_pcie = args.with_pcie,
with_sata = args.with_sata,
**soc_core_argdict(args)
)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()
| [
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((5709, 5779), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on AliExpress STLV7325"""'}), "(description='LiteX SoC on AliExpress STLV7325')\n", (5731, 5779), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((2214, 2244), 'litex_boards.platforms.aliexpress_stlv7325.Platform', 'aliexpress_stlv7325.Platform', ([], {}), '()\n', (2242, 2244), False, 'from litex_boards.platforms import aliexpress_stlv7325\n'), ((7959, 8001), 'os.path.join', 'os.path.join', (['builder.output_dir', '"""driver"""'], {}), "(builder.output_dir, 'driver')\n", (7971, 8001), False, 'import os\n'), ((3090, 3122), 'litedram.modules.MT8JTF12864', 'MT8JTF12864', (['sys_clk_freq', '"""1:4"""'], {}), "(sys_clk_freq, '1:4')\n", (3101, 3122), False, 'from litedram.modules import MT8JTF12864\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "nextpnr-ecp5", "yosys"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
import os
import shutil
import argparse
import subprocess
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.interconnect.csr import *
from litex.soc.cores.clock import *
from litex.soc.cores.clock.common import period_ns
from litex.soc.cores.gpio import GPIOOut, GPIOIn
from litex.soc.cores.spi_flash import SpiFlashDualQuad
from rtl.platform import butterstick_r1d0
from rtl.eptri import LunaEpTriWrapper
from rtl.rgb import Leds
from rtl.vccio import VccIo
# CRG ---------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_usb = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain()
# # #
self.stop = Signal()
self.reset = Signal()
# Use OSCG for generating por clocks.
osc_g = Signal()
self.specials += Instance("OSCG",
p_DIV=7, # 38MHz
o_OSC=osc_g
)
# Clk
clk30 = platform.request("clk30")
por_done = Signal()
platform.add_period_constraint(clk30, period_ns(30e6))
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
# Power on reset 10ms.
por_count = Signal(24, reset=int(30e6 * 10e-3))
self.comb += self.cd_por.clk.eq(osc_g)
self.comb += por_done.eq(pll.locked & (por_count == 0))
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
usb_por_done = Signal()
usb_por_count = Signal(24, reset=int(60e6 * 10e-3))
self.comb += usb_por_done.eq(usb_por_count == 0)
self.comb += self.cd_usb.clk.eq(self.cd_sys.clk)
self.comb += self.cd_usb.rst.eq(~usb_por_done)
self.sync.init += If(~usb_por_done, usb_por_count.eq(usb_por_count - 1))
# PLL
pll.register_clkin(clk30, 30e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq, with_reset=False)
pll.create_clkout(self.cd_init, 30e6, with_reset=False)
self.specials += [
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
i_SEL = 0,
o_ECSOUT = sys2x_clk_ecsout),
Instance("ECLKSYNCB",
i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~por_done | ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x_i, ~por_done | ~pll.locked | self.reset),
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0xa0000000)
"spiflash": 0x20000000, # (default shadow @0xa0000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"csr": 0xf0000000, # (default shadow @0xe0000000)
"usb": 0xf0010000,
}
mem_map.update(SoCCore.mem_map)
interrupt_map = {
"timer0": 0,
"uart": 1,
}
interrupt_map.update(SoCCore.interrupt_map)
def __init__(self, sys_clk_freq=int(60e6), toolchain="trellis", **kwargs):
# Board Revision ---------------------------------------------------------------------------
revision = kwargs.get("revision", "0.2")
device = kwargs.get("device", "25F")
platform = butterstick_r1d0.ButterStickPlatform()
# Serial -----------------------------------------------------------------------------------
platform.add_extension(butterstick_r1d0._uart_debug)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width=32, integrated_rom_size=32*1024, integrated_sram_size=16*1024, uart_baudrate=1000000)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = crg = CRG(platform, sys_clk_freq)
# VCCIO Control ----------------------------------------------------------------------------
self.submodules.vccio = VccIo(platform.request("vccio_ctrl"))
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
# Leds -------------------------------------------------------------------------------------
led = platform.request("led_rgb_multiplex")
self.submodules.leds = Leds(led.a, led.c)
self.add_csr("leds")
# Self Reset -------------------------------------------------------------------------------
rst = Signal()
self.submodules.reset = GPIOOut(rst)
self.comb += platform.request("rst_n").eq(~rst)
# Buttons ----------------------------------------------------------------------------------
self.submodules.button = GPIOIn(platform.request("user_btn"))
# USB --------------------------------------------------------------------------------------
self.submodules.usb = LunaEpTriWrapper(self.platform, base_addr=self.mem_map['usb'])
self.add_memory_region("usb", self.mem_map['usb'], 0x10000, type="");
self.add_wb_slave(self.mem_map['usb'], self.usb.bus)
for name, irq in self.usb.irqs.items():
name = 'usb_{}'.format(name)
class DummyIRQ(Module):
def __init__(self, irq):
class DummyEV(Module):
def __init__(self, irq):
self.irq = irq
self.submodules.ev = DummyEV(irq)
setattr(self.submodules, name, DummyIRQ(irq))
self.add_interrupt(name)
#Add GIT repo to the firmware
git_rev_cmd = subprocess.Popen("git describe --tags --first-parent --always".split(),
stdout=subprocess.PIPE,
stderr=subprocess.PIPE)
(git_stdout, _) = git_rev_cmd.communicate()
self.add_constant('CONFIG_REPO_GIT_DESC',git_stdout.decode('ascii').strip('\n'))
# This function will build our software and create a oc-fw.init file that can be patched directly into blockram in the FPGA
def PackageFirmware(self, builder):
self.finalize()
os.makedirs(builder.output_dir, exist_ok=True)
src_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "firmware"))
builder.add_software_package("fw", src_dir)
builder._prepare_rom_software()
builder._generate_includes()
builder._generate_rom_software(compile_bios=False)
firmware_file = os.path.join(builder.output_dir, "software", "fw","oc-fw.bin")
firmware_data = get_mem_data(firmware_file, self.cpu.endianness)
self.initialize_rom(firmware_data)
# lock out compiling firmware during build steps
builder.compile_software = False
def CreateFirmwareInit(init, output_file):
content = ""
for d in init:
content += "{:08x}\n".format(d)
with open(output_file, "w") as o:
o.write(content)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX based Bootloader on ButterStick")
builder_args(parser)
trellis_args(parser)
# parser.add_argument("--device", default="25F",
# help="ECP5 device (default=25F)")
# parser.add_argument("--sdram-device", default="MT41K64M16",
# help="ECP5 device (default=MT41K64M16)")
parser.add_argument(
"--update-firmware", default=False, action='store_true',
help="compile firmware and update existing gateware"
)
args = parser.parse_args()
soc = BaseSoC(**argdict(args))
builder = Builder(soc, **builder_argdict(args))
# Build firmware
soc.PackageFirmware(builder)
#generate_docs(soc, "build/documentation/", project_name="OrangeCrab Test SoC", author="<NAME>")
# Check if we have the correct files
firmware_file = os.path.join(builder.output_dir, "software", "fw", "oc-fw.bin")
firmware_data = get_mem_data(firmware_file, soc.cpu.endianness)
firmware_init = os.path.join(builder.output_dir, "software", "fw", "oc-fw.init")
CreateFirmwareInit(firmware_data, firmware_init)
rand_rom = os.path.join(builder.output_dir, "gateware", "rand.data")
# If we don't have a random file, create one, and recompile gateware
if (os.path.exists(rand_rom) == False) or (args.update_firmware == False):
os.makedirs(os.path.join(builder.output_dir,'gateware'), exist_ok=True)
os.makedirs(os.path.join(builder.output_dir,'software'), exist_ok=True)
os.system(f"ecpbram --generate {rand_rom} --seed {0} --width {32} --depth {soc.integrated_rom_size // 4}")
# patch random file into BRAM
data = []
with open(rand_rom, 'r') as inp:
for d in inp.readlines():
data += [int(d, 16)]
soc.initialize_rom(data)
# Build gateware
builder_kargs = trellis_argdict(args)
vns = builder.build(**builder_kargs)
soc.do_exit(vns)
from litex.soc.doc import generate_docs
generate_docs(soc, "build/docs/")
os.system("sphinx-build -M html build/docs/ build/docs/_build")
input_config = os.path.join(builder.output_dir, "gateware", f"{soc.platform.name}.config")
output_config = os.path.join(builder.output_dir, "gateware", f"{soc.platform.name}_patched.config")
# Insert Firmware into Gateware
os.system(f"ecpbram --input {input_config} --output {output_config} --from {rand_rom} --to {firmware_init}")
# create compressed config (ECP5 specific)
output_bitstream = os.path.join(builder.gateware_dir, f"{soc.platform.name}.bit")
#os.system(f"ecppack --freq 38.8 --spimode qspi --compress --input {output_config} --bit {output_bitstream}")
os.system(f"ecppack --freq 38.8 --bootaddr 0x200000 --compress --input {output_config} --bit {output_bitstream}")
dfu_file = os.path.join(builder.gateware_dir, f"{soc.platform.name}.dfu")
shutil.copyfile(output_bitstream, dfu_file)
os.system(f"dfu-suffix -v 1209 -p 5bf0 -a {dfu_file}")
def argdict(args):
r = soc_core_argdict(args)
for a in ["device", "revision", "sdram_device"]:
arg = getattr(args, a, None)
if arg is not None:
r[a] = arg
return r
if __name__ == "__main__":
main()
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"litex.build.lattice.trellis.trellis_argdict",
"litex.soc.cores.gpio.GPIOOut",
"litex.soc.cores.clock.common.period_ns",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.doc.generate_docs"
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(['Codes.READ_1_1_4'], {}), '(Codes.READ_1_1_4)\n', (5890, 5908), False, 'from litespi.modules import W25Q128JV\n'), ((8015, 8040), 'os.path.dirname', 'os.path.dirname', (['__file__'], {}), '(__file__)\n', (8030, 8040), False, 'import os\n')] |
import logging
import os
from migen import *
from litex.soc.interconnect.csr_eventmanager import EventManager, EventSourceLevel
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
class CenJT51(Module):
def __init__(self, tuning_word):
self.cen = Signal()
self.cen_p1 = Signal()
phase = Signal(32, reset_less=True)
self.sync += Cat(phase, self.cen).eq(phase + tuning_word)
half = Signal(reset=1)
self.sync += If(self.cen, half.eq(~half))
self.comb += self.cen_p1.eq(self.cen & half)
YM2151_FREQ = 3570000
class JT51(Module, AutoCSR):
def __init__(self, platform, clk_freq, with_irq=False):
assert(clk_freq > YM2151_FREQ)
self.platform = platform
self.ct1 = Signal()
self.ct2 = Signal()
self.irq_n = Signal()
self.sample = Signal()
self.left = Signal(16)
self.right = Signal(16)
self.xleft = Signal(16)
self.xright = Signal(16)
self.dacleft = Signal(16)
self.dacright = Signal(16)
self._control = CSRStorage(description="jt51 control", fields=[
CSRField('reset', reset=1, size=1, description='Reset'),
CSRField('cs_n', reset=1, size=1, description='Chip select'),
CSRField('wr_n', reset=1, size=1, description='Write'),
CSRField('a0', reset=1, size=1, description='A0'),
])
reset = Signal()
cs_n = Signal()
wr_n = Signal()
a0 = Signal()
self.comb += [
reset.eq(self._control.fields.reset),
cs_n.eq(self._control.fields.cs_n),
wr_n.eq(self._control.fields.wr_n),
a0.eq(self._control.fields.a0)
]
self._din = CSRStorage(8, reset_less=True, description="Data in")
self._dout = CSRStatus(8, description="Data out")
din = Signal(8)
dout = Signal(8)
self.comb += [
din.eq(self._din.storage),
self._dout.status.eq(dout)
]
self.logger = logging.getLogger("JT51")
self.logger.info(f'JT51 clock {YM2151_FREQ}Hz from {clk_freq}Hz')
cen = Signal()
cen_p1 = Signal()
self.submodules.clock_enable = CenJT51(tuning_word=int((YM2151_FREQ / clk_freq) * 2 ** 32))
self.comb += [
cen.eq(self.clock_enable.cen),
cen_p1.eq(self.clock_enable.cen_p1),
]
self.jt51_params = dict(
i_rst=ResetSignal() | reset,
i_clk=ClockSignal(),
i_cen=cen,
i_cen_p1=cen_p1,
i_cs_n=cs_n,
i_wr_n=wr_n,
i_a0=a0,
i_din=din,
o_dout=dout,
o_ct1=self.ct1,
o_ct2=self.ct2,
o_irq_n=self.irq_n,
o_sample=self.sample,
o_left=self.left,
o_right=self.right,
o_xleft=self.xleft,
o_xright=self.xright,
o_dacleft=self.dacleft,
o_dacright=self.dacright
)
self.add_sources(platform)
if with_irq:
self.submodules.ev = EventManager()
self.ev.j51_irq = EventSourceLevel(description="JT51 irq")
self.ev.finalize()
self.comb += self.ev.j51_irq.trigger.eq(~self.irq_n)
@staticmethod
def add_sources(platform):
vdir = "gateware/rtl/jt51"
platform.add_source_dir(os.path.join(vdir, "hdl"), recursive=False)
platform.add_verilog_include_path(os.path.join(vdir, "hdl"))
def do_finalize(self):
self.specials += Instance("jt51", **self.jt51_params) | [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.csr_eventmanager.EventManager",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr_eventmanager.EventSourceLevel"
] | [((1776, 1829), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {'reset_less': '(True)', 'description': '"""Data in"""'}), "(8, reset_less=True, description='Data in')\n", (1786, 1829), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1851, 1887), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(8)'], {'description': '"""Data out"""'}), "(8, description='Data out')\n", (1860, 1887), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((2071, 2096), 'logging.getLogger', 'logging.getLogger', (['"""JT51"""'], {}), "('JT51')\n", (2088, 2096), False, 'import logging\n'), ((3148, 3162), 'litex.soc.interconnect.csr_eventmanager.EventManager', 'EventManager', ([], {}), '()\n', (3160, 3162), False, 'from litex.soc.interconnect.csr_eventmanager import EventManager, EventSourceLevel\n'), ((3193, 3233), 'litex.soc.interconnect.csr_eventmanager.EventSourceLevel', 'EventSourceLevel', ([], {'description': '"""JT51 irq"""'}), "(description='JT51 irq')\n", (3209, 3233), False, 'from litex.soc.interconnect.csr_eventmanager import EventManager, EventSourceLevel\n'), ((3457, 3482), 'os.path.join', 'os.path.join', (['vdir', '"""hdl"""'], {}), "(vdir, 'hdl')\n", (3469, 3482), False, 'import os\n'), ((3543, 3568), 'os.path.join', 'os.path.join', (['vdir', '"""hdl"""'], {}), "(vdir, 'hdl')\n", (3555, 3568), False, 'import os\n'), ((1165, 1220), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""reset"""'], {'reset': '(1)', 'size': '(1)', 'description': '"""Reset"""'}), "('reset', reset=1, size=1, description='Reset')\n", (1173, 1220), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1234, 1294), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""cs_n"""'], {'reset': '(1)', 'size': '(1)', 'description': '"""Chip select"""'}), "('cs_n', reset=1, size=1, description='Chip select')\n", (1242, 1294), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1308, 1362), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""wr_n"""'], {'reset': '(1)', 'size': '(1)', 'description': '"""Write"""'}), "('wr_n', reset=1, size=1, description='Write')\n", (1316, 1362), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1376, 1425), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""a0"""'], {'reset': '(1)', 'size': '(1)', 'description': '"""A0"""'}), "('a0', reset=1, size=1, description='A0')\n", (1384, 1425), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Support for the ZTEX USB-FGPA Module 2.13:https://www.ztex.de/usb-fpga-2/usb-fpga-2.13.e.html.
# With (no-so-optional) expansion, either the ZTEX Debug board:
# https://www.ztex.de/usb-fpga-2/debug.e.html
# Or the SBusFPGA adapter board:
# https://github.com/rdolbeau/SBusFPGA
import os
import argparse
from migen import *
from litex_boards.platforms import ztex213
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41J128M16
from litedram.phy import s7ddrphy
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
clk48 = platform.request("clk48")
self.submodules.pll = pll = S7MMCM(speedgrade=-1)
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk48)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
self.comb += pll.reset.eq(~por_done)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, variant="ztex2.13a", sys_clk_freq=int(100e6), expansion="debug",
with_led_chaser=True, **kwargs):
platform = ztex213.Platform(variant=variant, expansion=expansion)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Ztex 2.13",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J128M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Ztex 2.13")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--expansion", default="debug", help="Expansion board (debug or sbus).")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), expansion=args.expansion, **soc_core_argdict(args))
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard() # SBus only
if args.with_sdcard:
soc.add_sdcard() # SBus only
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
| [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((3915, 3976), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Ztex 2.13"""'}), "(description='LiteX SoC on Ztex 2.13')\n", (3938, 3976), False, 'import argparse\n'), ((4621, 4646), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (4638, 4646), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((2441, 2495), 'litex_boards.platforms.ztex213.Platform', 'ztex213.Platform', ([], {'variant': 'variant', 'expansion': 'expansion'}), '(variant=variant, expansion=expansion)\n', (2457, 2495), False, 'from litex_boards.platforms import ztex213\n'), ((5056, 5082), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (5076, 5082), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((5195, 5254), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (5207, 5254), False, 'import os\n'), ((3393, 3425), 'litedram.modules.MT41J128M16', 'MT41J128M16', (['sys_clk_freq', '"""1:4"""'], {}), "(sys_clk_freq, '1:4')\n", (3404, 3425), False, 'from litedram.modules import MT41J128M16\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.interconnect import wishbone
# TestWishbone -------------------------------------------------------------------------------------
class TestWishbone(unittest.TestCase):
def test_upconverter_16_32(self):
def generator(dut):
yield from dut.wb16.write(0x0000, 0x1234)
yield from dut.wb16.write(0x0001, 0x5678)
yield from dut.wb16.write(0x0002, 0xdead)
yield from dut.wb16.write(0x0003, 0xbeef)
self.assertEqual((yield from dut.wb16.read(0x0000)), 0x1234)
self.assertEqual((yield from dut.wb16.read(0x0001)), 0x5678)
self.assertEqual((yield from dut.wb16.read(0x0002)), 0xdead)
self.assertEqual((yield from dut.wb16.read(0x0003)), 0xbeef)
class DUT(Module):
def __init__(self):
self.wb16 = wishbone.Interface(data_width=16)
wb32 = wishbone.Interface(data_width=32)
up_converter = wishbone.UpConverter(self.wb16, wb32)
self.submodules += up_converter
wishbone_mem = wishbone.SRAM(32, bus=wb32)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
def test_converter_32_64_32(self):
def generator(dut):
yield from dut.wb32.write(0x0000, 0x12345678)
yield from dut.wb32.write(0x0001, 0xdeadbeef)
self.assertEqual((yield from dut.wb32.read(0x0000)), 0x12345678)
self.assertEqual((yield from dut.wb32.read(0x0001)), 0xdeadbeef)
class DUT(Module):
def __init__(self):
self.wb32 = wishbone.Interface(data_width=32)
wb64 = wishbone.Interface(data_width=64)
wb32 = wishbone.Interface(data_width=32)
up_converter = wishbone.UpConverter(self.wb32, wb64)
down_converter = wishbone.DownConverter(wb64, wb32)
self.submodules += up_converter, down_converter
wishbone_mem = wishbone.SRAM(32, bus=wb32)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
| [
"litex.soc.interconnect.wishbone.UpConverter",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.wishbone.DownConverter",
"litex.soc.interconnect.wishbone.SRAM"
] | [((999, 1032), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(16)'}), '(data_width=16)\n', (1017, 1032), False, 'from litex.soc.interconnect import wishbone\n'), ((1061, 1094), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (1079, 1094), False, 'from litex.soc.interconnect import wishbone\n'), ((1126, 1163), 'litex.soc.interconnect.wishbone.UpConverter', 'wishbone.UpConverter', (['self.wb16', 'wb32'], {}), '(self.wb16, wb32)\n', (1146, 1163), False, 'from litex.soc.interconnect import wishbone\n'), ((1243, 1270), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'wb32'}), '(32, bus=wb32)\n', (1256, 1270), False, 'from litex.soc.interconnect import wishbone\n'), ((1810, 1843), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (1828, 1843), False, 'from litex.soc.interconnect import wishbone\n'), ((1872, 1905), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(64)'}), '(data_width=64)\n', (1890, 1905), False, 'from litex.soc.interconnect import wishbone\n'), ((1934, 1967), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (1952, 1967), False, 'from litex.soc.interconnect import wishbone\n'), ((2001, 2038), 'litex.soc.interconnect.wishbone.UpConverter', 'wishbone.UpConverter', (['self.wb32', 'wb64'], {}), '(self.wb32, wb64)\n', (2021, 2038), False, 'from litex.soc.interconnect import wishbone\n'), ((2072, 2106), 'litex.soc.interconnect.wishbone.DownConverter', 'wishbone.DownConverter', (['wb64', 'wb32'], {}), '(wb64, wb32)\n', (2094, 2106), False, 'from litex.soc.interconnect import wishbone\n'), ((2202, 2229), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'wb32'}), '(32, bus=wb32)\n', (2215, 2229), False, 'from litex.soc.interconnect import wishbone\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteHelloWorld.
#
"""
LiteHelloWorld standalone core manager
LiteHelloWorld aims to be directly used as a python package when the SoC is created using LiteX. However,
for some use cases it could be interesting to generate a standalone verilog file of the core or use it as standalone:
- integration of the core in a SoC using a more traditional flow.
- core development/tests.
- need to version/package the core.
- avoid Migen/LiteX dependencies.
- etc...
The standalone core is generated from a YAML configuration file that allows the user to generate
easily a custom configuration of the core.
"""
import argparse
import os
import yaml
from migen import *
#Litex build tools
from litex.build.generic_platform import *
from litex.build.altera.platform import AlteraPlatform
from litex.build.lattice.platform import LatticePlatform
from litex.build.xilinx.platform import XilinxPlatform
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
#Litex SoC tools
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
#Debug tools
from litex.soc.cores import uart
from litescope import LiteScopeAnalyzer
#Custom core classes here
from litehelloworld.core.dummy import DummyLitexModel
# IOs ----------------------------------------------------------------------------------------------
#DOC/QUESTION: WHERE CAN WE GET INFOS ON I/O PARAMETERS AND USAGE-DESCRIPTION?
#There seems to be something like: name, logic (0=active high? 1=active low or on rising edge / and falling edge?), pin(s) used / number of pins only if sim, technology*?
#*: optional
# FPGA I/O
_io = [
("sys_clock", 0, Pins("K23"), IOStandard("LVCMOS33")),
("sys_reset", 1, Pins("N5"), IOStandard("LVCMOS33")),
("input_bus", 1, Pins("T25 U25 U24 V24 T26 U26 V26 W26"), IOStandard("LVCMOS33")),
("output_bus", 1, Pins("U23 V23 U22 V21 W25 W24 W23 W22"), IOStandard("LVCMOS33")),
("uart_bridge", 0,
Subsignal("rx", Pins("R26")),
Subsignal("tx", Pins("R24")),
IOStandard("LVCMOS33")
),
]
# Predefined Litex-Boards I/O
#TODO HERE: LINK TO BOARD PREDEFINED CONNECTORS LIKE PMOD OR GENERIC IOs AND SERIAL FOR THE BRIDGE?
#_io = [
#]
# Simulation I/O
_sim_io = [
("sys_clock", 0, Pins(1)),
("sys_reset", 1, Pins(1)),
("input_bus", 1, Pins(8)),
("output_bus", 1, Pins(8)),
("uart_bridge", 0,
Subsignal("rx", Pins(1)),
Subsignal("tx", Pins(1)),
),
]
class GenericCore(SoCMini):
def __init__(self, platform, core_config):
# SoC parameters ---------------------------------------------------------------------------
soc_args = {}
if "soc" in core_config:
soc_config = core_config["soc"]
for arg in soc_config:
#QUESTION: IS THERE SOME DOCS ON THESE ARGS (*_map)?
if arg in ("csr_map", "interrupt_map", "mem_map"):
getattr(self, arg).update(soc_config[arg])
else:
soc_args[arg] = soc_config[arg]
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=core_config["clk_freq"], **soc_args)
# Clock Reset Generator --------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clock"), platform.request("sys_reset"))
def generate_documentation(self, build_name, **kwargs):
#Infos: https://github.com/enjoy-digital/litex/wiki/SoC-Documentation
from litex.soc.doc import generate_docs
generate_docs(self, "documentation".format(build_name),
project_name = "LiteHelloWorld standalone core",
author = "<PASSWORD>")
os.system("sphinx-build -M html documentation/ documentation/_build".format(build_name, build_name))
# Dummy Litex Core --------------------------------------------------------------------------------
class DummyLitexCore(GenericCore):
def __init__(self, platform, core_config):
GenericCore.__init__(self, platform, core_config)
# DummyPhy --------------------------------------------------------------------------------
self.submodules.dummyphy = DummyLitexModel(
inputs=platform.request("input_bus"),
outputs=platform.request("output_bus"),
)
# Wishbone slave connexion
self.add_wb_slave(self.mem_map["dummyphy"], self.dummyphy.bus)
self.add_memory_region("dummyphy", self.mem_map["dummyphy"], 0x2000, type="io")
#QUESTION: WHAT MEANS CSR ACRONYM IN THE FRAME OF LITEX?
#Infos: https://github.com/enjoy-digital/litex/wiki/CSR-Bus
self.add_csr("dummyphy")
# UART BRIDGE TO CONTROL WISHBONE BUS ------------------------------------------------------
# QUESTION: NO PROBLEM TO USE IT IN SIM MODE ALSO? IS THERE A TRICK ALSO TO HAVE A VIRTUAL UART IN SIM MODE LIKE FOR ETH TAP? CF QUESTION ALSO IN MAIN RELATED TO serial2console
#Infos: https://github.com/enjoy-digital/litex/wiki/Use-Host-Bridge-to-control-debug-a-SoC
self.submodules.uart_bridge = uart.UARTWishboneBridge(
pads=platform.request("uart_bridge"),
clk_freq=core_config["clk_freq"],
baudrate=115200,
)
self.add_wb_master(self.uart_bridge.wishbone)
# LITESCOPE TO DEBUG CORE INTERNALS --------------------------------------------------------
#Infos: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC
analyzer_signals = [
self.dummyphy.sink,
self.dummyphy.source,
self.dummyphy.bus,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals,
depth=512,
clock_domain="sys",
csr_csv="analyzer.csv"
)
self.add_csr("analyzer")
# Build --------------------------------------------------------------------------------------------
def main():
core_name = "litehelloworld_core"
# Parameters available -------------------------------------------------------------------------
parser = argparse.ArgumentParser(description="LiteHelloWorld standalone core manager")
parser.set_defaults(output_dir="build")
parser.add_argument("config", help="YAML config file")
parser.add_argument("--build", action="store_true", help="Generate RTL and gateware bitstream")
parser.add_argument("--doc", action="store_true", help="Generate documentation")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--generate", action="store_true", help="Generate RTL code")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sim", action="store_true", help="Simulate core")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing (for sim mode)")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing (for sim mode)")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing (for sim mode)")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level (for sim mode)")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
if k == "clk_freq" or k == "clk_sim":
core_config[k] = int(float(core_config[k]))
# Generate core --------------------------------------------------------------------------------
if args.sim:
platform = SimPlatform("Simulation", io=_sim_io)
#QUESTION: MIGHT/NEED BE DIRECTLY ADDED TO io PARAM BEFORE??
platform.add_extension(_sim_io)
#QUESTION: OK/NEEDED TO OVERLOAD CLK HERE OR HAS TO BE DIFFERENT CLOCKS OR JUST NOT USED IN SIM MODE?
core_config["clk_freq"] = core_config["clk_sim"]
else:
if core_config["vendor"] == "altera":
platform = AlteraPlatform(device=core_config["device"], io=[], toolchain=core_config["toolchain"])
elif core_config["vendor"] == "lattice":
platform = LatticePlatform(device=core_config["device"], io=[], toolchain=core_config["toolchain"])
elif core_config["vendor"] == "xilinx":
platform = XilinxPlatform(device=core_config["device"], io=[], toolchain=core_config["toolchain"])
else:
raise ValueError("Unsupported vendor: {}".format(core_config["vendor"]))
platform.add_extension(_io)
soc = DummyLitexCore(platform, core_config)
if args.sim:
if args.build or args.load or args.flash:
raise ValueError("Cannot build/load/flash while simulating the core. Please use --sim option alone")
sim_config = SimConfig(default_clk="sys_clock")
#QUESTION: IF POSSIBLE TO USE UART BRIDGE, THIS IS HOW TO ADD A VIRTUAL TTY? WHAT WILL BE ITS NAME? BUT THERE IS A SEG FAULT WITH THIS LINE. SOMETHING IS MISSING?
#sim_config.add_module("serial2console", "uart_bridge", clocks="sys_clock")
builder = Builder(soc, csr_csv="csr.csv")
#QUESTION/FIXME: NO TRACE TAKEN (vcd file empty)
builder.build(
sim_config=sim_config,
run = True,
opt_level = args.opt_level,
trace = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end)
)
else:
if args.build:
#FIXME/QUESTION: WHY FINAL TIMING ANALYSIS TELLS ME 12MHz REQUIRED INSTEAD OF 100MHz? ("Info: Max frequency for clock '$glbnet$sys_clock$TRELLIS_IO_IN': 117.36 MHz (PASS at 12.00 MHz)")
builder = Builder(soc, csr_csv="csr.csv")
builder.build(build_name=core_name)
if args.flash or args.load:
#TODO/QUESTION: SPECIFIC BOARD INSTANTIATION + PINOUT OR TO BE TAKEN IN ACCOUNT IN PLATFORM INSTANTIATION??
prog = soc.platform.create_programmer()
if args.flash:
prog.flash(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.load:
prog.load(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.generate:
builder = Builder(soc, compile_gateware=False)
builder.build(build_name=core_name)
if args.doc:
soc.generate_documentation(core_name)
if __name__ == "__main__":
main()
| [
"litex.build.lattice.platform.LatticePlatform",
"litex.build.sim.config.SimConfig",
"litex.build.sim.SimPlatform",
"litex.build.altera.platform.AlteraPlatform",
"litex.build.xilinx.platform.XilinxPlatform"
] | [((6301, 6378), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteHelloWorld standalone core manager"""'}), "(description='LiteHelloWorld standalone core manager')\n", (6324, 6378), False, 'import argparse\n'), ((5852, 5947), 'litescope.LiteScopeAnalyzer', 'LiteScopeAnalyzer', (['analyzer_signals'], {'depth': '(512)', 'clock_domain': '"""sys"""', 'csr_csv': '"""analyzer.csv"""'}), "(analyzer_signals, depth=512, clock_domain='sys', csr_csv=\n 'analyzer.csv')\n", (5869, 5947), False, 'from litescope import LiteScopeAnalyzer\n'), ((8042, 8079), 'litex.build.sim.SimPlatform', 'SimPlatform', (['"""Simulation"""'], {'io': '_sim_io'}), "('Simulation', io=_sim_io)\n", (8053, 8079), False, 'from litex.build.sim import SimPlatform\n'), ((9229, 9263), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {'default_clk': '"""sys_clock"""'}), "(default_clk='sys_clock')\n", (9238, 9263), False, 'from litex.build.sim.config import SimConfig\n'), ((8435, 8527), 'litex.build.altera.platform.AlteraPlatform', 'AlteraPlatform', ([], {'device': "core_config['device']", 'io': '[]', 'toolchain': "core_config['toolchain']"}), "(device=core_config['device'], io=[], toolchain=core_config[\n 'toolchain'])\n", (8449, 8527), False, 'from litex.build.altera.platform import AlteraPlatform\n'), ((8595, 8688), 'litex.build.lattice.platform.LatticePlatform', 'LatticePlatform', ([], {'device': "core_config['device']", 'io': '[]', 'toolchain': "core_config['toolchain']"}), "(device=core_config['device'], io=[], toolchain=core_config[\n 'toolchain'])\n", (8610, 8688), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((8755, 8847), 'litex.build.xilinx.platform.XilinxPlatform', 'XilinxPlatform', ([], {'device': "core_config['device']", 'io': '[]', 'toolchain': "core_config['toolchain']"}), "(device=core_config['device'], io=[], toolchain=core_config[\n 'toolchain'])\n", (8769, 8847), False, 'from litex.build.xilinx.platform import XilinxPlatform\n'), ((10478, 10537), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (10490, 10537), False, 'import os\n'), ((10591, 10650), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (10603, 10650), False, 'import os\n')] |
import subprocess
from migen import Module
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField
class Version(Module, AutoCSR, AutoDoc):
def __init__(self, model, hw_platform, parent, seed=0, models=[]):
self.intro = ModuleDoc("""SoC Version Information
This block contains various information about the state of the source code
repository when this SoC was built.
""")
def makeint(i, base=10):
try:
return int(i, base=base)
except:
return 0
def get_gitver():
major = 0
minor = 0
rev = 0
gitrev = 0
gitextra = 0
dirty = 0
def decode_version(v):
version = v.split(".")
major = 0
minor = 0
rev = 0
if len(version) >= 3:
rev = makeint(version[2])
if len(version) >= 2:
minor = makeint(version[1])
if len(version) >= 1:
major = makeint(version[0])
return (major, minor, rev)
git_rev_cmd = subprocess.Popen(["git", "describe", "--tags", "--long", "--dirty=+", "--abbrev=8"],
stdout=subprocess.PIPE,
stderr=subprocess.PIPE)
(git_stdout, _) = git_rev_cmd.communicate()
if git_rev_cmd.wait() != 0:
print('unable to get git version')
return (major, minor, rev, gitrev, gitextra, dirty)
raw_git_rev = git_stdout.decode().strip()
parts = raw_git_rev.split("-")
if raw_git_rev[-1] == "+":
raw_git_rev = raw_git_rev[:-1]
dirty = 1
if len(parts) >= 3:
if parts[0].startswith("v"):
version = parts[0]
if version.startswith("v"):
version = parts[0][1:]
(major, minor, rev) = decode_version(version)
gitextra = makeint(parts[1])
if parts[2].startswith("g"):
gitrev = makeint(parts[2][1:], base=16)
elif len(parts) >= 2:
if parts[1].startswith("g"):
gitrev = makeint(parts[1][1:], base=16)
version = parts[0]
if version.startswith("v"):
version = parts[0][1:]
(major, minor, rev) = decode_version(version)
elif len(parts) >= 1:
version = parts[0]
if version.startswith("v"):
version = parts[0][1:]
(major, minor, rev) = decode_version(version)
return (major, minor, rev, gitrev, gitextra, dirty)
model_val = 0x3f # '?'
if hw_platform == "fomu":
parent.config["FOMU_REV"] = model.upper()
if model == "evt":
model_val = 0x45 # 'E'
elif model == "dvt":
model_val = 0x44 # 'D'
elif model == "pvt":
model_val = 0x50 # 'P'
elif model == "hacker":
model_val = 0x48 # 'H'
elif hw_platform == "orangecrab":
parent.config["ORANGECRAB_REV"] = model.upper().replace('.', '_')
if model == "r0_1":
model_val = 0x10 # 'r0.1'
elif model == "r0_2":
model_val = 0x11 # 'r0.2'
(major, minor, rev, gitrev, gitextra, dirty) = get_gitver()
self.major = CSRStatus(8, reset=major, description="Major git tag version. For example, this firmware was built from git tag ``v{}.{}.{}``, so this value is ``{}``.".format(major, minor, rev, major))
self.minor = CSRStatus(8, reset=minor, description="Minor git tag version. For example, this firmware was built from git tag ``v{}.{}.{}``, so this value is ``{}``.".format(major, minor, rev, minor))
self.revision = CSRStatus(8, reset=rev, description="Revision git tag version. For example, this firmware was built from git tag ``v{}.{}.{}``, so this value is ``{}``.".format(major, minor, rev, rev))
self.gitrev = CSRStatus(32, reset=gitrev, description="First 32-bits of the git revision. This documentation was built from git rev ``{:08x}``, so this value is {}, which should be enough to check out the exact git version used to build this firmware.".format(gitrev, gitrev))
self.gitextra = CSRStatus(10, reset=gitextra, description="The number of additional commits beyond the git tag. For example, if this value is ``1``, then the repository this was built from has one additional commit beyond the tag indicated in `MAJOR`, `MINOR`, and `REVISION`.")
self.dirty = CSRStatus(fields=[
CSRField("dirty", reset=dirty, description="Set to ``1`` if this device was built from a git repo with uncommitted modifications.")
])
self.model = CSRStatus(fields=[
CSRField("model", reset=model_val, size=8, description="Contains information on which model device this was built for.", values=models)
])
self.seed = CSRStatus(32, reset=seed, description="32-bit seed used for the place-and-route.")
self.comb += [
self.major.status.eq(major),
self.minor.status.eq(minor),
self.revision.status.eq(rev),
self.gitrev.status.eq(gitrev),
self.gitextra.status.eq(gitextra),
self.dirty.fields.dirty.eq(dirty),
self.model.fields.model.eq(model_val),
self.seed.status.eq(seed),
]
| [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.csr.CSRField",
"litex.soc.integration.doc.ModuleDoc"
] | [((315, 514), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""SoC Version Information\n\n This block contains various information about the state of the source code\n repository when this SoC was built.\n """'], {}), '(\n """SoC Version Information\n\n This block contains various information about the state of the source code\n repository when this SoC was built.\n """\n )\n', (324, 514), False, 'from litex.soc.integration.doc import AutoDoc, ModuleDoc\n'), ((4623, 4896), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(10)'], {'reset': 'gitextra', 'description': '"""The number of additional commits beyond the git tag. For example, if this value is ``1``, then the repository this was built from has one additional commit beyond the tag indicated in `MAJOR`, `MINOR`, and `REVISION`."""'}), "(10, reset=gitextra, description=\n 'The number of additional commits beyond the git tag. For example, if this value is ``1``, then the repository this was built from has one additional commit beyond the tag indicated in `MAJOR`, `MINOR`, and `REVISION`.'\n )\n", (4632, 4896), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField\n'), ((5301, 5388), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(32)'], {'reset': 'seed', 'description': '"""32-bit seed used for the place-and-route."""'}), "(32, reset=seed, description=\n '32-bit seed used for the place-and-route.')\n", (5310, 5388), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField\n'), ((1278, 1414), 'subprocess.Popen', 'subprocess.Popen', (["['git', 'describe', '--tags', '--long', '--dirty=+', '--abbrev=8']"], {'stdout': 'subprocess.PIPE', 'stderr': 'subprocess.PIPE'}), "(['git', 'describe', '--tags', '--long', '--dirty=+',\n '--abbrev=8'], stdout=subprocess.PIPE, stderr=subprocess.PIPE)\n", (1294, 1414), False, 'import subprocess\n'), ((4939, 5080), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""dirty"""'], {'reset': 'dirty', 'description': '"""Set to ``1`` if this device was built from a git repo with uncommitted modifications."""'}), "('dirty', reset=dirty, description=\n 'Set to ``1`` if this device was built from a git repo with uncommitted modifications.'\n )\n", (4947, 5080), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField\n'), ((5134, 5278), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""model"""'], {'reset': 'model_val', 'size': '(8)', 'description': '"""Contains information on which model device this was built for."""', 'values': 'models'}), "('model', reset=model_val, size=8, description=\n 'Contains information on which model device this was built for.',\n values=models)\n", (5142, 5278), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = {
"standard": "femtorv32_quark",
"quark": "femtorv32_quark", # Quark: Most elementary version of FemtoRV32.
"tachyon": "femtorv32_tachyon", # Tachyon: Like Quark but supporting higher freq.
"electron": "femtorv32_electron", # Electron: Adds M support.
"intermissum": "femtorv32_intermissum", # Intermissum: Adds Interrupt + CSR.
"gracilis": "femtorv32_gracilis", # Gracilis: Adds C support.
"petitbateau": "femtorv32_petitbateau", # PetitBateau: Adds F support.
}
# GCC Flags ----------------------------------------------------------------------------------------
GCC_FLAGS = {
# /-------- Base ISA
# |/------- Hardware Multiply + Divide
# ||/----- Atomics
# |||/---- Compressed ISA
# ||||/--- Single-Precision Floating-Point
# |||||/-- Double-Precision Floating-Point
# imacfd
"standard": "-march=rv32i -mabi=ilp32",
"quark": "-march=rv32i -mabi=ilp32",
"tachyon": "-march=rv32i -mabi=ilp32",
"electron": "-march=rv32im -mabi=ilp32",
"intermissum": "-march=rv32im -mabi=ilp32",
"gracilis": "-march=rv32imc -mabi=ilp32",
"petitbateau": "-march=rv32imfc -mabi=ilp32f",
}
# FemtoRV ------------------------------------------------------------------------------------------
class FemtoRV(CPU):
family = "riscv"
name = "femtorv"
human_name = "FemtoRV"
variants = CPU_VARIANTS
data_width = 32
endianness = "little"
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # Origin, Length.
# GCC Flags.
@property
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += " -D__femtorv__ "
return flags
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.human_name = f"FemtoRV-{variant.upper()}"
self.reset = Signal()
self.idbus = idbus = wishbone.Interface()
self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
# # #
# FemtoRV Mem Bus.
# ----------------
mbus = Record([
("addr", 32),
("wdata", 32),
("wmask", 4),
("rdata", 32),
("rstrb", 1),
("rbusy", 1),
("wbusy", 1),
])
# FemtoRV Instance.
# -----------------
self.cpu_params = dict(
# Parameters.
p_ADDR_WIDTH = 32,
p_RESET_ADDR = Constant(0, 32),
# Clk / Rst.
i_clk = ClockSignal("sys"),
i_reset = ~(ResetSignal("sys") | self.reset), # Active Low.
# I/D Bus.
o_mem_addr = mbus.addr,
o_mem_wdata = mbus.wdata,
o_mem_wmask = mbus.wmask,
i_mem_rdata = mbus.rdata,
o_mem_rstrb = mbus.rstrb,
i_mem_rbusy = mbus.rbusy,
i_mem_wbusy = mbus.wbusy,
)
# Adapt FemtoRV Mem Bus to Wishbone.
# ----------------------------------
latch = Signal()
write = mbus.wmask != 0
read = mbus.rstrb
self.submodules.fsm = fsm = FSM(reset_state="WAIT")
fsm.act("WAIT",
# Latch Address + Bytes to Words conversion.
NextValue(idbus.adr, mbus.addr[2:]),
# Latch Wdata/WMask.
NextValue(idbus.dat_w, mbus.wdata),
NextValue(idbus.sel, mbus.wmask),
# If Read or Write, jump to access.
If(read | write,
NextValue(idbus.we, write),
NextState("WB-ACCESS")
)
)
fsm.act("WB-ACCESS",
idbus.stb.eq(1),
idbus.cyc.eq(1),
mbus.wbusy.eq(1),
mbus.rbusy.eq(1),
If(idbus.ack,
mbus.wbusy.eq(0),
mbus.rbusy.eq(0),
latch.eq(1),
NextState("WAIT")
)
)
# Latch RData on Wishbone ack.
mbus_rdata = Signal(32)
self.sync += If(latch, mbus_rdata.eq(idbus.dat_r))
self.comb += mbus.rdata.eq(mbus_rdata) # Latched value.
self.comb += If(latch, mbus.rdata.eq(idbus.dat_r)) # Immediate value.
# Add Verilog sources.
# --------------------
self.add_sources(platform, variant)
def set_reset_address(self, reset_address):
self.reset_address = reset_address
self.cpu_params.update(p_RESET_ADDR=Constant(reset_address, 32))
@staticmethod
def add_sources(platform, variant):
platform.add_verilog_include_path(os.getcwd())
cpu_files = [f"{CPU_VARIANTS[variant]}.v"]
if variant == "petitbateau":
cpu_files.append("petitbateau.v")
for cpu_file in cpu_files:
if not os.path.exists(cpu_file):
os.system(f"wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/{cpu_file}")
platform.add_source(cpu_file)
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("FemtoRV32", **self.cpu_params)
| [
"litex.soc.interconnect.wishbone.Interface"
] | [((2810, 2830), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2828, 2830), False, 'from litex.soc.interconnect import wishbone\n'), ((5592, 5603), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (5601, 5603), False, 'import os\n'), ((5793, 5817), 'os.path.exists', 'os.path.exists', (['cpu_file'], {}), '(cpu_file)\n', (5807, 5817), False, 'import os\n'), ((5835, 5958), 'os.system', 'os.system', (['f"""wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/{cpu_file}"""'], {}), "(\n f'wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/{cpu_file}'\n )\n", (5844, 5958), False, 'import os\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.interconnect import wishbone
# TestWishbone -------------------------------------------------------------------------------------
class TestWishbone(unittest.TestCase):
def test_upconverter_16_32(self):
def generator(dut):
yield from dut.wb16.write(0x0000, 0x1234)
yield from dut.wb16.write(0x0001, 0x5678)
yield from dut.wb16.write(0x0002, 0xdead)
yield from dut.wb16.write(0x0003, 0xbeef)
self.assertEqual((yield from dut.wb16.read(0x0000)), 0x1234)
self.assertEqual((yield from dut.wb16.read(0x0001)), 0x5678)
self.assertEqual((yield from dut.wb16.read(0x0002)), 0xdead)
self.assertEqual((yield from dut.wb16.read(0x0003)), 0xbeef)
class DUT(Module):
def __init__(self):
self.wb16 = wishbone.Interface(data_width=16)
wb32 = wishbone.Interface(data_width=32)
up_converter = wishbone.UpConverter(self.wb16, wb32)
self.submodules += up_converter
wishbone_mem = wishbone.SRAM(32, bus=wb32)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
def test_converter_32_64_32(self):
def generator(dut):
yield from dut.wb32.write(0x0000, 0x12345678)
yield from dut.wb32.write(0x0001, 0xdeadbeef)
self.assertEqual((yield from dut.wb32.read(0x0000)), 0x12345678)
self.assertEqual((yield from dut.wb32.read(0x0001)), 0xdeadbeef)
class DUT(Module):
def __init__(self):
self.wb32 = wishbone.Interface(data_width=32)
wb64 = wishbone.Interface(data_width=64)
wb32 = wishbone.Interface(data_width=32)
up_converter = wishbone.UpConverter(self.wb32, wb64)
down_converter = wishbone.DownConverter(wb64, wb32)
self.submodules += up_converter, down_converter
wishbone_mem = wishbone.SRAM(32, bus=wb32)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
def test_sram_burst(self):
def generator(dut):
yield from dut.wb.write(0x0000, 0x01234567, cti=wishbone.CTI_BURST_INCREMENTING)
yield from dut.wb.write(0x0001, 0x89abcdef, cti=wishbone.CTI_BURST_INCREMENTING)
yield from dut.wb.write(0x0002, 0xdeadbeef, cti=wishbone.CTI_BURST_INCREMENTING)
yield from dut.wb.write(0x0003, 0xc0ffee00, cti=wishbone.CTI_BURST_END)
self.assertEqual((yield from dut.wb.read(0x0000, cti=wishbone.CTI_BURST_INCREMENTING)), 0x01234567)
self.assertEqual((yield from dut.wb.read(0x0001, cti=wishbone.CTI_BURST_INCREMENTING)), 0x89abcdef)
self.assertEqual((yield from dut.wb.read(0x0002, cti=wishbone.CTI_BURST_INCREMENTING)), 0xdeadbeef)
self.assertEqual((yield from dut.wb.read(0x0003, cti=wishbone.CTI_BURST_END)), 0xc0ffee00)
class DUT(Module):
def __init__(self):
self.wb = wishbone.Interface(bursting=True)
wishbone_mem = wishbone.SRAM(32, bus=self.wb)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
def test_sram_burst_wrap(self):
def generator(dut):
bte = 0b01
yield from dut.wb.write(0x0001, 0x01234567, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)
yield from dut.wb.write(0x0002, 0x89abcdef, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)
yield from dut.wb.write(0x0003, 0xdeadbeef, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)
yield from dut.wb.write(0x0000, 0xc0ffee00, cti=wishbone.CTI_BURST_END, bte=bte)
self.assertEqual((yield from dut.wb.read(0x0001, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)), 0x01234567)
self.assertEqual((yield from dut.wb.read(0x0002, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)), 0x89abcdef)
self.assertEqual((yield from dut.wb.read(0x0003, cti=wishbone.CTI_BURST_INCREMENTING, bte=bte)), 0xdeadbeef)
self.assertEqual((yield from dut.wb.read(0x0000, cti=wishbone.CTI_BURST_END, bte=bte)), 0xc0ffee00)
class DUT(Module):
def __init__(self):
self.wb = wishbone.Interface(bursting=True)
wishbone_mem = wishbone.SRAM(32, bus=self.wb)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
def test_sram_burst_constant(self):
def generator(dut):
yield from dut.wb.write(0x0001, 0x01234567, cti=wishbone.CTI_BURST_CONSTANT)
yield from dut.wb.write(0x0002, 0x89abcdef, cti=wishbone.CTI_BURST_CONSTANT)
yield from dut.wb.write(0x0003, 0xdeadbeef, cti=wishbone.CTI_BURST_CONSTANT)
yield from dut.wb.write(0x0000, 0xc0ffee00, cti=wishbone.CTI_BURST_END)
self.assertEqual((yield from dut.wb.read(0x0001, cti=wishbone.CTI_BURST_CONSTANT)), 0x01234567)
self.assertEqual((yield from dut.wb.read(0x0002, cti=wishbone.CTI_BURST_CONSTANT)), 0x89abcdef)
self.assertEqual((yield from dut.wb.read(0x0003, cti=wishbone.CTI_BURST_CONSTANT)), 0xdeadbeef)
self.assertEqual((yield from dut.wb.read(0x0000, cti=wishbone.CTI_BURST_END)), 0xc0ffee00)
class DUT(Module):
def __init__(self):
self.wb = wishbone.Interface(bursting=True)
wishbone_mem = wishbone.SRAM(32, bus=self.wb)
self.submodules += wishbone_mem
dut = DUT()
run_simulation(dut, generator(dut))
| [
"litex.soc.interconnect.wishbone.UpConverter",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.wishbone.DownConverter",
"litex.soc.interconnect.wishbone.SRAM"
] | [((999, 1032), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(16)'}), '(data_width=16)\n', (1017, 1032), False, 'from litex.soc.interconnect import wishbone\n'), ((1061, 1094), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (1079, 1094), False, 'from litex.soc.interconnect import wishbone\n'), ((1126, 1163), 'litex.soc.interconnect.wishbone.UpConverter', 'wishbone.UpConverter', (['self.wb16', 'wb32'], {}), '(self.wb16, wb32)\n', (1146, 1163), False, 'from litex.soc.interconnect import wishbone\n'), ((1243, 1270), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'wb32'}), '(32, bus=wb32)\n', (1256, 1270), False, 'from litex.soc.interconnect import wishbone\n'), ((1810, 1843), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (1828, 1843), False, 'from litex.soc.interconnect import wishbone\n'), ((1872, 1905), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(64)'}), '(data_width=64)\n', (1890, 1905), False, 'from litex.soc.interconnect import wishbone\n'), ((1934, 1967), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (1952, 1967), False, 'from litex.soc.interconnect import wishbone\n'), ((2001, 2038), 'litex.soc.interconnect.wishbone.UpConverter', 'wishbone.UpConverter', (['self.wb32', 'wb64'], {}), '(self.wb32, wb64)\n', (2021, 2038), False, 'from litex.soc.interconnect import wishbone\n'), ((2072, 2106), 'litex.soc.interconnect.wishbone.DownConverter', 'wishbone.DownConverter', (['wb64', 'wb32'], {}), '(wb64, wb32)\n', (2094, 2106), False, 'from litex.soc.interconnect import wishbone\n'), ((2202, 2229), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'wb32'}), '(32, bus=wb32)\n', (2215, 2229), False, 'from litex.soc.interconnect import wishbone\n'), ((3291, 3324), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'bursting': '(True)'}), '(bursting=True)\n', (3309, 3324), False, 'from litex.soc.interconnect import wishbone\n'), ((3356, 3386), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'self.wb'}), '(32, bus=self.wb)\n', (3369, 3386), False, 'from litex.soc.interconnect import wishbone\n'), ((4548, 4581), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'bursting': '(True)'}), '(bursting=True)\n', (4566, 4581), False, 'from litex.soc.interconnect import wishbone\n'), ((4613, 4643), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'self.wb'}), '(32, bus=self.wb)\n', (4626, 4643), False, 'from litex.soc.interconnect import wishbone\n'), ((5690, 5723), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'bursting': '(True)'}), '(bursting=True)\n', (5708, 5723), False, 'from litex.soc.interconnect import wishbone\n'), ((5755, 5785), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(32)'], {'bus': 'self.wb'}), '(32, bus=self.wb)\n', (5768, 5785), False, 'from litex.soc.interconnect import wishbone\n')] |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import ice40up5k
from litex.build import generic_programmer
from litex.build.lattice import programmer as lattice_programmer
from litex.soc.integration import soc as litex_soc
from litex.soc.integration import builder
def flash(offset: int,
filename: str,
programmer: generic_programmer.GenericProgrammer = None) -> None:
"""Flashes a file at a specific offset for the iCEbreaker.
Args:
offset: The offset (in bytes) of the start of the file in flash.
filename: The file to be flashed.
programmer: The programmer to flash the board. If none provided,
the IceStormProgrammer will be used.
"""
prog = programmer or lattice_programmer.IceStormProgrammer()
prog.flash(offset, filename)
class IcebreakerSoCWorkflow(ice40up5k.Ice40UP5KWorkflow):
"""Workflow for the iCEbreaker board."""
def load(self,
soc: litex_soc.LiteXSoC,
soc_builder: builder.Builder,
programmer: generic_programmer.GenericProgrammer = None) -> None:
"""Loads gateware and bios onto the board.
Args:
soc: The SoC to be loaded.
soc_builder: The Builder that generated the SoC.
programmer: The programmer to flash the board. If none provided,
the IceStormProgrammer will be used.
"""
flash(0x0, f'{soc_builder.output_dir}/gateware/{soc.build_name}.bin',
programmer)
# Flashing bios perhaps unnecessary if we always plan to overwrite it.
flash(self.bios_flash_offset,
f'{soc_builder.output_dir}/software/bios/bios.bin', programmer)
def software_load(
self,
filename: str,
programmer: generic_programmer.GenericProgrammer = None) -> None:
"""Loads software on top of the bios.
Args:
filename: The file being uploaded over the bios.
programmer: The programmer used to flash the board. If none
specified, the IceStormProgrammer will be used.
"""
flash(self.bios_flash_offset, filename, programmer)
| [
"litex.build.lattice.programmer.IceStormProgrammer"
] | [((1303, 1342), 'litex.build.lattice.programmer.IceStormProgrammer', 'lattice_programmer.IceStormProgrammer', ([], {}), '()\n', (1340, 1342), True, 'from litex.build.lattice import programmer as lattice_programmer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk200", 0,
Subsignal("p", Pins("R4"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("T4"), IOStandard("DIFF_SSTL15"))
),
("clk125", 0,
Subsignal("p", Pins("F6"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("E6"), IOStandard("DIFF_SSTL15"))
),
("cpu_reset", 0, Pins("T6"), IOStandard("SSTL15")),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins("AA4 AB2 AA5 AB5 AB1 U3 W1 T1 V2 U2 Y1 W2 Y2 U1 V3"), IOStandard("SSTL15")),
Subsignal("ba", Pins("AA3 Y3 Y4"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("V4"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("W4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AA1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("D2 G2 M2 M5"), IOStandard("SSTL15")),
Subsignal("dq", Pins("C2 G1 A1 F3 B2 F1 B1 E2 H3 G3 H2 H5 J1 J5 K1 H4 L4 M3 L3 J6 K3 K6 J4 L5 P1 N4 R1 N2 M6 N5 P6 P2"), IOStandard("SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("E1 K2 M1 P5"), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_n", Pins("D1 J2 L1 P4"), IOStandard("DIFF_SSTL15"), Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("T5"), IOStandard("SSTL15")),
Subsignal("odt", Pins("U5"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AB3"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("W6"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
),
# UART
("serial", 0,
Subsignal("tx", Pins("AB15")),
Subsignal("rx", Pins("AA15")),
IOStandard("LVCMOS33"),
),
# GMII Ethernet
("eth_clocks_ext", 0,
Subsignal("tx", Pins("K21")),
Subsignal("gtx", Pins("G21")),
Subsignal("rx", Pins("K18")),
IOStandard("LVCMOS33")
),
("eth1_clocks_ext", 0,
Subsignal("tx", Pins("T14")),
Subsignal("gtx", Pins("M16")),
Subsignal("rx", Pins("J20")),
IOStandard("LVCMOS33")
),
("eth2_clocks_ext", 0,
Subsignal("tx", Pins("V10")),
Subsignal("gtx", Pins("AA21")),
Subsignal("rx", Pins("V13")),
IOStandard("LVCMOS33")
),
("eth3_clocks_ext", 0,
Subsignal("tx", Pins("U16")),
Subsignal("gtx", Pins("P20")),
Subsignal("rx", Pins("Y18")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("G20")),
Subsignal("int_n", Pins("D14"), Misc("KEEPER = TRUE")),
Subsignal("mdio", Pins("L16")),
Subsignal("mdc", Pins("J17")),
Subsignal("rx_dv", Pins("M22")),
Subsignal("rx_er", Pins("N18")),
Subsignal("rx_data", Pins("N22 H18 H17 M21 L21 N20 M20 N19")),
Subsignal("tx_en", Pins("G22")),
Subsignal("tx_er", Pins("K17")),
Subsignal("tx_data", Pins("D22 H20 H22 J22 K22 L19 K19 L20")),
Subsignal("col", Pins("M18")),
Subsignal("crs", Pins("L18")),
IOStandard("LVCMOS33")
),
("eth", 1,
Subsignal("rst_n", Pins("L14")),
Subsignal("int_n", Pins("E14"), Misc("KEEPER = TRUE")),
Subsignal("mdc", Pins("AB21")),
Subsignal("mdio", Pins("AB22")),
Subsignal("rx_dv", Pins("L13")),
Subsignal("rx_er", Pins("G13")),
Subsignal("rx_data", Pins("M13 K14 K13 J14 H14 H15 J15 H13")),
Subsignal("tx_en", Pins("M15")),
Subsignal("tx_er", Pins("T15")),
Subsignal("tx_data", Pins("L15 K16 W15 W16 V17 W17 U15 V15")),
Subsignal("col", Pins("J21")),
Subsignal("crs", Pins("E22")),
IOStandard("LVCMOS33")
),
("eth", 2,
Subsignal("rst_n", Pins("T20")),
Subsignal("int_n", Pins("E13"), Misc("KEEPER = TRUE")),
Subsignal("mdc", Pins("V20")),
Subsignal("mdio", Pins("V19")),
Subsignal("rx_dv", Pins("AA20")),
Subsignal("rx_er", Pins("U21")),
Subsignal("rx_data", Pins("AB20 AA19 AA18 AB18 Y17 W22 W21 T21")),
Subsignal("tx_en", Pins("V14")),
Subsignal("tx_er", Pins("AA9")),
Subsignal("tx_data", Pins("W11 W12 Y11 Y12 W10 AA11 AA10 AB10")),
Subsignal("col", Pins("Y21")),
Subsignal("crs", Pins("Y22")),
IOStandard("LVCMOS33")
),
("eth", 3,
Subsignal("rst_n", Pins("R16")),
Subsignal("int_n", Pins("F13")),
Subsignal("mdc", Pins("V18")),
Subsignal("mdio", Pins("U20")),
Subsignal("rx_dv", Pins("W20")),
Subsignal("rx_er", Pins("N13")),
Subsignal("rx_data", Pins("W19 Y19 V22 U22 T18 R18 R14 P14")),
Subsignal("tx_en", Pins("P16")),
Subsignal("tx_er", Pins("R19")),
Subsignal("tx_data", Pins("R17 P15 N17 P17 T16 U17 U18 P19")),
Subsignal("col", Pins("N14")),
Subsignal("crs", Pins("N15")),
IOStandard("LVCMOS33")
),
("spisdcard", 0,
Subsignal("clk", Pins("J16")),
Subsignal("mosi", Pins("A20"), Misc("PULLUP true")),
Subsignal("cs_n", Pins("B22"), Misc("PULLUP true")),
Subsignal("miso", Pins("F20"), Misc("PULLUP true")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("data", Pins("F20 C22 B20 B22"), Misc("PULLUP true")),
Subsignal("cmd", Pins("A20"), Misc("PULLUP true")),
Subsignal("clk", Pins("J16")),
Subsignal("cd", Pins("F19")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
)
]
_connectors = []
class Platform(XilinxPlatform):
default_clk_name = "clk200"
default_clk_period = 1e9/200e6
def __init__(self) -> None:
XilinxPlatform.__init__(self, "xc7a100t-fgg484-2", _io, _connectors, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
return OpenOCD("openocd_ax7101.cfg", "bscan_spi_xc7a100t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("eth_clocks_ext:gtx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks_ext:tx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks_ext:rx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth1_clocks_ext:gtx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth1_clocks_ext:tx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth1_clocks_ext:rx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth2_clocks_ext:gtx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth2_clocks_ext:tx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth2_clocks_ext:rx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth3_clocks_ext:gtx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth3_clocks_ext:tx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth3_clocks_ext:rx", loose=True), 1e9/125e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((6308, 6400), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-fgg484-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-fgg484-2', _io, _connectors,\n toolchain='vivado')\n", (6331, 6400), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((6621, 6676), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_ax7101.cfg"""', '"""bscan_spi_xc7a100t.bit"""'], {}), "('openocd_ax7101.cfg', 'bscan_spi_xc7a100t.bit')\n", (6628, 6676), False, 'from litex.build.openocd import OpenOCD\n'), ((6723, 6765), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (6749, 6765), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# clock
("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")),
# leds
("user_led", 0, Pins("M21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("N20"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("L21"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("AA21"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("R19"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("M16"), IOStandard("LVCMOS33")),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vpp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33")
),
# serial
("serial", 0,
Subsignal("tx", Pins("E14")),
Subsignal("rx", Pins("E13")),
IOStandard("LVCMOS33"),
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 V4 W5 V5 AA1 Y2 AB1 AB3",
"AB2 Y3 W6 Y1 V2 AA3"),
IOStandard("SSTL15_R")),
Subsignal("ba", Pins("U5 W4 V7"), IOStandard("SSTL15_R")),
Subsignal("ras_n", Pins("Y9"), IOStandard("SSTL15_R")),
Subsignal("cas_n", Pins("Y7"), IOStandard("SSTL15_R")),
Subsignal("we_n", Pins("V8"), IOStandard("SSTL15_R")),
Subsignal("dm", Pins("G1 H4 M5 L3"), IOStandard("SSTL15_R")),
Subsignal("dq", Pins(
"C2 F1 B1 F3 A1 D2 B2 E2",
"J5 H3 K1 H2 J1 G2 H5 G3",
"N2 M6 P1 N5 P2 N4 R1 P6",
"K3 M2 K4 M3 J6 L5 J4 K6"),
IOStandard("SSTL15_R"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("E1 K2 P5 M1"), IOStandard("DIFF_SSTL15_R")),
Subsignal("dqs_n", Pins("D1 J2 P4 L1"), IOStandard("DIFF_SSTL15_R")),
Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL15_R")),
Subsignal("clk_n", Pins("R2"), IOStandard("DIFF_SSTL15_R")),
Subsignal("cke", Pins("Y8"), IOStandard("SSTL15_R")),
Subsignal("odt", Pins("W9"), IOStandard("SSTL15_R")),
Subsignal("reset_n", Pins("AB5"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("V9"), IOStandard("SSTL15_R")),
Misc("SLEW=FAST"),
),
# pcie
("pcie_x1", 0,
Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F10")),
Subsignal("clk_n", Pins("E10")),
Subsignal("rx_p", Pins("D11")),
Subsignal("rx_n", Pins("C11")),
Subsignal("tx_p", Pins("D5")),
Subsignal("tx_n", Pins("C5"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F10")),
Subsignal("clk_n", Pins("E10")),
Subsignal("rx_p", Pins("D11 B10")),
Subsignal("rx_n", Pins("C11 A10")),
Subsignal("tx_p", Pins("D5 B6")),
Subsignal("tx_n", Pins("C5 A6"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F10")),
Subsignal("clk_n", Pins("E10")),
Subsignal("rx_p", Pins("D11 B10 D9 B8")),
Subsignal("rx_n", Pins("C11 A10 C9 A8")),
Subsignal("tx_p", Pins("D5 B6 D7 B4")),
Subsignal("tx_n", Pins("C5 A6 C7 A4"))
),
# ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D17")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("F16")),
Subsignal("rx_data", Pins("A20 B18")),
Subsignal("crs_dv", Pins("C20")),
Subsignal("tx_en", Pins("A19")),
Subsignal("tx_data", Pins("C18 C19")),
Subsignal("mdc", Pins("F14")),
Subsignal("mdio", Pins("F13")),
Subsignal("rx_er", Pins("B20")),
Subsignal("int_n", Pins("D21")),
IOStandard("LVCMOS33")
),
# sdcard
("sdcard", 0,
Subsignal("data", Pins("L15 L16 K14 M13"), Misc("PULLUP True")),
Subsignal("cmd", Pins("L13"), Misc("PULLUP True")),
Subsignal("clk", Pins("K18")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
# hdmi in
("hdmi_in", 0,
Subsignal("clk_p", Pins("L19"), IOStandard("TMDS_33"), Inverted()),
Subsignal("clk_n", Pins("L20"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data0_p", Pins("K21"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data0_n", Pins("K22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data1_p", Pins("J20"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data1_n", Pins("J21"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data2_p", Pins("J22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data2_n", Pins("H22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("scl", Pins("T18"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("V18"), IOStandard("LVCMOS33")),
),
("hdmi_in", 1,
Subsignal("clk_p", Pins("Y18"), IOStandard("TMDS_33"), Inverted()),
Subsignal("clk_n", Pins("Y19"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data0_p", Pins("AA18"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("AB18"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("AA19"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data1_n", Pins("AB20"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data2_p", Pins("AB21"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data2_n", Pins("AB22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("scl", Pins("W17"), IOStandard("LVCMOS33"), Inverted()),
Subsignal("sda", Pins("R17"), IOStandard("LVCMOS33")),
),
# hdmi out
("hdmi_out", 0,
Subsignal("clk_p", Pins("W19"), Inverted(), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("W20"), Inverted(), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("W21"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("W22"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("U20"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("V20"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("T21"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("U21"), IOStandard("TMDS_33"))
),
("hdmi_out", 1,
Subsignal("clk_p", Pins("G21"), IOStandard("TMDS_33"), Inverted()),
Subsignal("clk_n", Pins("G22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data0_p", Pins("E22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data0_n", Pins("D22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data1_p", Pins("C22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data1_n", Pins("B22"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data2_p", Pins("B21"), IOStandard("TMDS_33"), Inverted()),
Subsignal("data2_n", Pins("A21"), IOStandard("TMDS_33"), Inverted()),
Subsignal("scl", Pins("P16"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("R16"), IOStandard("LVCMOS33")),
),
]
_hdmi_infos = {
"HDMI_OUT0_MNEMONIC": "TX1",
"HDMI_OUT0_DESCRIPTION" : (
"HDMI-A connector (marked TX0/J10H on PCB) located in the mounting bracket area, connector is the one closer to the DC Jack\\r\\n"
),
"HDMI_OUT1_MNEMONIC": "TX2",
"HDMI_OUT1_DESCRIPTION" : (
"HDMI-D connector (marked TX1/P10H on PCB) located on the top edge of the board, connector is the one closer to the DC Jack\\r\\n"
),
"HDMI_IN0_MNEMONIC": "RX1",
"HDMI_IN0_DESCRIPTION" : (
"HDMI-A connector (marked RX0/J11H on PCB) located in the mounting bracket area, connector is the one farther from the DC Jack\\r\\n"
),
"HDMI_IN1_MNEMONIC": "RX2",
"HDMI_IN1_DESCRIPTION" : (
"HDMI-A connector (marked OVERLAY/J12H on PCB) located on the top edge of the board, connector is the one farther from the DC Jack\\r\\n"
),
}
class Platform(XilinxPlatform):
name = "netv2"
default_clk_name = "clk50"
default_clk_period = 20.0
hdmi_infos = _hdmi_infos
# From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
gateware_size = 0x400000
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_model = "mx25l6433f"
spiflash_read_dummy_bits = 10
spiflash_clock_div = 2
spiflash_total_size = int((64/8)*1024*1024) # 64Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x1000
def __init__(self, toolchain="vivado", programmer="vivado", part="xc7a35t"):
XilinxPlatform.__init__(self, part + "-fgg484-2", _io,
toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property CONFIG_VOLTAGE 3.3 [current_design]",
"set_property CFGBVS VCCO [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
]
self.toolchain.additional_commands = \
["write_cfgmem -verbose -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer(flash_part="mx25l6433f-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((8639, 8714), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', "(part + '-fgg484-2')", '_io'], {'toolchain': 'toolchain'}), "(self, part + '-fgg484-2', _io, toolchain=toolchain)\n", (8662, 8714), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((9415, 9469), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""mx25l6433f-spi-x1_x2_x4"""'}), "(flash_part='mx25l6433f-spi-x1_x2_x4')\n", (9431, 9469), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("rst", 0, Pins("G13"), IOStandard("LVCMOS18")),
("clk125", 0,
Subsignal("p", Pins("H9"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("G9"), IOStandard("DIFF_SSTL15")),
),
# Leds
("user_led", 0, Pins("AL11"), IOStandard("LVCMOS12")),
("user_led", 1, Pins("AL13"), IOStandard("LVCMOS12")),
("user_led", 2, Pins("AK13"), IOStandard("LVCMOS12")),
("user_led", 3, Pins("AE15"), IOStandard("LVCMOS12")),
("user_led", 4, Pins("AM8"), IOStandard("LVCMOS12")),
("user_led", 5, Pins("AM9"), IOStandard("LVCMOS12")),
("user_led", 6, Pins("AM10"), IOStandard("LVCMOS12")),
("user_led", 7, Pins("AM11"), IOStandard("LVCMOS12")),
# Buttons
("user_btn_c", 0, Pins("AL11"), IOStandard("LVCMOS12")),
("user_btn_n", 0, Pins("AG13"), IOStandard("LVCMOS12")),
("user_btn_s", 0, Pins("AP20"), IOStandard("LVCMOS12")),
("user_btn_w", 0, Pins("AK12"), IOStandard("LVCMOS12")),
("user_btn_e", 0, Pins("AC14"), IOStandard("LVCMOS12")),
# Serial
("serial", 0,
Subsignal("cts", Pins("AP17")),
Subsignal("rts", Pins("AM15")),
Subsignal("tx", Pins("AL17")),
Subsignal("rx", Pins("AH17")),
IOStandard("LVCMOS12")
),
# DDR4 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"AK9 AG11 AJ10 AL8 AK10 AH8 AJ9 AG8",
"AH9 AG10 AH13 AG9 AM13 AF8"),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AK8 AL12"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("AE14"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AF11"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AE12"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AC12"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AD12"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AD14"), IOStandard("SSTL12_DCI")),
# Subsignal("par", Pins("AC13"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AH18 AD15 AM16 AP18 AE18 AH22 AL20 AP19"),
IOStandard("POD12_DCI")),
Subsignal("dq", Pins(
"AF16 AF18 AG15 AF17 AF15 AG18 AG14 AE17",
"AA14 AC16 AB15 AD16 AB16 AC17 AB14 AD17",
"AJ16 AJ17 AL15 AK17 AJ15 AK18 AL16 AL18",
"AP13 AP16 AP15 AN16 AN13 AM18 AN17 AN18",
"AB19 AD19 AC18 AC19 AA20 AE20 AA19 AD20",
"AF22 AH21 AG19 AG21 AE24 AG20 AE23 AF21",
"AL22 AJ22 AL23 AJ21 AK20 AJ19 AK19 AJ20",
"AP22 AN22 AP21 AP23 AM19 AM23 AN19 AN23"),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("AH14 AA16 AK15 AM14 AA18 AF23 AK22 AM21"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("AJ14 AA15 AK14 AN14 AB18 AG23 AK23 AN21"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("AH11"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("AJ11"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("AB13"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("AF10"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AF12"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-e", _io, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4178, 4256), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu7ev-ffvc1156-2-e"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xczu7ev-ffvc1156-2-e', _io, toolchain='vivado')\n", (4201, 4256), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((4306, 4324), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (4322, 4324), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((4371, 4413), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4397, 4413), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
from migen import *
from litex.build.generic_platform import Subsignal, Pins, IOStandard
from litex_boards.platforms import lambdaconcept_ecpix5
from ..crg_ecp5 import CRG
from ..serial_led import SerialLedController
from litespi.opcodes import SpiNorFlashOpCodes as Codes
from ..flash_modules import IS25LP256D
class Platform(lambdaconcept_ecpix5.Platform):
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
self.add_extension([
('debug', 0,
Subsignal('jtck', Pins('pmod6:1')),
Subsignal('jtms', Pins('pmod6:7')),
Subsignal('jtms_dir', Pins('pmod6:3')),
Subsignal('jtdo', Pins('pmod7:3')),
Subsignal('jtdi', Pins('pmod6:6')),
Subsignal('nrst_i', Pins('pmod7:7')),
Subsignal('nrst_o_n', Pins('pmod6:4')),
),
('trace', 0,
Subsignal('clk', Pins('pmod7:2')),
Subsignal('data', Pins('pmod7:6 pmod7:1 pmod7:5 pmod7:4')),
),
('target_power', 0,
Subsignal('vtref_en_n', Pins('pmod6:2')),
Subsignal('vtpwr_en_n', Pins('pmod6:5')),
),
('gpio', 0,
Subsignal('data', Pins('pmod4:0')),
),
('serial_led', 0, Pins('pmod5:0')),
])
def get_crg(self, sys_clk_freq):
return CRG(self, sys_clk_freq)
def get_flash_module(self):
return IS25LP256D(Codes.READ_1_4_4)
def add_leds(self, soc):
soc.submodules.serial_led = SerialLedController(self.request('serial_led'), 5)
soc.led_status = soc.serial_led.leds[0]
soc.led_debug = soc.serial_led.leds[1]
soc.led_trace = soc.serial_led.leds[2]
#soc.led_status = Record([('r', 1), ('g', 1), ('b', 1)])
#soc.led_debug = Record([('r', 1), ('g', 1), ('b', 1)])
#soc.led_trace = Record([('r', 1), ('g', 1), ('b', 1)])
off = Record([('r', 1), ('g', 1), ('b', 1)])
led_map = [
(soc.led_status, self.request('rgb_led', 0)),
(soc.led_debug, self.request('rgb_led', 1)),
(soc.led_trace, self.request('rgb_led', 2)),
(off, self.request('rgb_led', 3)),
]
for led, pads in led_map:
soc.comb += [
pads.r.eq(~led.r),
pads.g.eq(~led.g),
pads.b.eq(~led.b),
]
def do_finalize(self, fragment):
lambdaconcept_ecpix5.Platform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("ulpi:clk", 0, loose=True), 1e9/60e6)
self.add_period_constraint(self.lookup_request("trace:clk", 0, loose=True), 1e9/120e6)
@classmethod
def add_arguments(cls, parser):
parser.add_argument('--device', choices = ['45F', '85F'], default = '85F', help = 'ECP5 device (default: 85F)')
@classmethod
def get_profile(cls, profile):
return {
'default': {},
}[profile]
| [
"litex.build.generic_platform.Pins"
] | [((2526, 2583), 'litex_boards.platforms.lambdaconcept_ecpix5.Platform.do_finalize', 'lambdaconcept_ecpix5.Platform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2567, 2583), False, 'from litex_boards.platforms import lambdaconcept_ecpix5\n'), ((1342, 1357), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod5:0"""'], {}), "('pmod5:0')\n", (1346, 1357), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((535, 550), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:1"""'], {}), "('pmod6:1')\n", (539, 550), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((587, 602), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:7"""'], {}), "('pmod6:7')\n", (591, 602), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((643, 658), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:3"""'], {}), "('pmod6:3')\n", (647, 658), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((695, 710), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod7:3"""'], {}), "('pmod7:3')\n", (699, 710), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((747, 762), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:6"""'], {}), "('pmod6:6')\n", (751, 762), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((802, 817), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod7:7"""'], {}), "('pmod7:7')\n", (806, 817), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((858, 873), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:4"""'], {}), "('pmod6:4')\n", (862, 873), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((949, 964), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod7:2"""'], {}), "('pmod7:2')\n", (953, 964), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((1001, 1040), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod7:6 pmod7:1 pmod7:5 pmod7:4"""'], {}), "('pmod7:6 pmod7:1 pmod7:5 pmod7:4')\n", (1005, 1040), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((1130, 1145), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:2"""'], {}), "('pmod6:2')\n", (1134, 1145), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((1188, 1203), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod6:5"""'], {}), "('pmod6:5')\n", (1192, 1203), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n'), ((1279, 1294), 'litex.build.generic_platform.Pins', 'Pins', (['"""pmod4:0"""'], {}), "('pmod4:0')\n", (1283, 1294), False, 'from litex.build.generic_platform import Subsignal, Pins, IOStandard\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import subprocess
import sys
from shutil import which
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.lattice import common
# IO Constraints (.lpf) ----------------------------------------------------------------------------
def _format_constraint(c):
if isinstance(c, Pins):
return ("LOCATE COMP ", " SITE " + "\"" + c.identifiers[0] + "\"")
elif isinstance(c, IOStandard):
return ("IOBUF PORT ", " IO_TYPE=" + c.name)
elif isinstance(c, Misc):
return ("IOBUF PORT ", " " + c.misc)
def _format_lpf(signame, pin, others, resname):
fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
lpf = []
for pre, suf in fmt_c:
lpf.append(pre + "\"" + signame + "\"" + suf + ";")
return "\n".join(lpf)
def _build_lpf(named_sc, named_pc, build_name):
lpf = []
lpf.append("BLOCK RESETPATHS;")
lpf.append("BLOCK ASYNCPATHS;")
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
lpf.append(_format_lpf(sig + "[" + str(i) + "]", p, others, resname))
else:
lpf.append(_format_lpf(sig, pins[0], others, resname))
if named_pc:
lpf.append("\n\n".join(named_pc))
tools.write_to_file(build_name + ".lpf", "\n".join(lpf))
# Yosys/Nextpnr Helpers/Templates ------------------------------------------------------------------
_yosys_template = [
"verilog_defaults -push",
"verilog_defaults -add -defer",
"{read_files}",
"verilog_defaults -pop",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ecp5 {nwl} {abc} -json {build_name}.json -top {build_name}",
]
def _yosys_import_sources(platform):
includes = ""
reads = []
for path in platform.verilog_include_paths:
includes += " -I" + path
for filename, language, library in platform.sources:
# yosys has no such function read_systemverilog
if language == "systemverilog":
language = "verilog -sv"
reads.append("read_{}{} {}".format(
language, includes, filename))
return "\n".join(reads)
def _build_yosys(template, platform, nowidelut, abc9, build_name):
ys = []
for l in template:
ys.append(l.format(
build_name = build_name,
nwl = "-nowidelut" if nowidelut else "",
abc = "-abc9" if abc9 else "",
read_files = _yosys_import_sources(platform)
))
tools.write_to_file(build_name + ".ys", "\n".join(ys))
def nextpnr_ecp5_parse_device(device):
device = device.lower()
family = device.split("-")[0]
size = device.split("-")[1]
speed_grade = device.split("-")[2][0]
if speed_grade not in ["6", "7", "8"]:
raise ValueError("Invalid speed grade {}".format(speed_grade))
package = device.split("-")[2][1:]
if "256" in package:
package = "CABGA256"
elif "285" in package:
package = "CSFBGA285"
elif "381" in package:
package = "CABGA381"
elif "554" in package:
package = "CABGA554"
elif "756" in package:
package = "CABGA756"
else:
raise ValueError("Invalid package {}".format(package))
return (family, size, speed_grade, package)
nextpnr_ecp5_architectures = {
"lfe5u-12f" : "12k",
"lfe5u-25f" : "25k",
"lfe5u-45f" : "45k",
"lfe5u-85f" : "85k",
"lfe5um-25f" : "um-25k",
"lfe5um-45f" : "um-45k",
"lfe5um-85f" : "um-85k",
"lfe5um5g-25f": "um5g-25k",
"lfe5um5g-45f": "um5g-45k",
"lfe5um5g-85f": "um5g-85k",
}
# Script -------------------------------------------------------------------------------------------
_build_template = [
"yosys -l {build_name}.rpt {build_name}.ys",
"nextpnr-ecp5 --json {build_name}.json --lpf {build_name}.lpf --textcfg {build_name}.config \
--{architecture} --package {package} --speed {speed_grade} {timefailarg} {ignoreloops} --seed {seed}",
"ecppack {build_name}.config --svf {build_name}.svf --bit {build_name}.bit --bootaddr {bootaddr} {spimode} {compress}"
]
def _build_script(source, build_template, build_name, architecture, package, speed_grade, timingstrict, ignoreloops, bootaddr, seed, spimode, compress):
if sys.platform in ("win32", "cygwin"):
script_ext = ".bat"
script_contents = "@echo off\nrem Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n\n"
fail_stmt = " || exit /b"
else:
script_ext = ".sh"
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
fail_stmt = ""
for s in build_template:
s_fail = s + "{fail_stmt}\n" # Required so Windows scripts fail early.
script_contents += s_fail.format(
build_name = build_name,
architecture = architecture,
package = package,
speed_grade = speed_grade,
timefailarg = "--timing-allow-fail" if not timingstrict else "",
ignoreloops = "--ignore-loops" if ignoreloops else "",
bootaddr = bootaddr,
fail_stmt = fail_stmt,
seed = seed,
spimode = "" if spimode is None else "--spimode {}".format(spimode),
compress = "" if not compress else "--compress")
script_file = "build_" + build_name + script_ext
tools.write_to_file(script_file, script_contents, force_unix=False)
return script_file
def _run_script(script):
if sys.platform in ("win32", "cygwin"):
shell = ["cmd", "/c"]
else:
shell = ["bash"]
if which("yosys") is None or which("nextpnr-ecp5") is None:
msg = "Unable to find Yosys/Nextpnr toolchain, please:\n"
msg += "- Add Yosys/Nextpnr toolchain to your $PATH."
raise OSError(msg)
if subprocess.call(shell + [script]) != 0:
raise OSError("Error occured during Yosys/Nextpnr's script execution.")
# LatticeTrellisToolchain --------------------------------------------------------------------------
class LatticeTrellisToolchain:
attr_translate = {
"keep": ("keep", "true"),
}
special_overrides = common.lattice_ecp5_trellis_special_overrides
def __init__(self):
self.yosys_template = _yosys_template
self.build_template = _build_template
self.false_paths = set() # FIXME: use it
def build(self, platform, fragment,
build_dir = "build",
build_name = "top",
run = True,
nowidelut = False,
abc9 = False,
timingstrict = False,
ignoreloops = False,
bootaddr = 0,
seed = 1,
spimode = None,
compress = False,
**kwargs):
# Create build directory
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
# Finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# Generate verilog
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
top_file = build_name + ".v"
v_output.write(top_file)
platform.add_source(top_file)
# Generate design constraints file (.lpf)
_build_lpf(named_sc, named_pc, build_name)
# Generate Yosys script
_build_yosys(self.yosys_template, platform, nowidelut, abc9, build_name)
# Translate device to Nextpnr architecture/package/speed_grade
(family, size, speed_grade, package) = nextpnr_ecp5_parse_device(platform.device)
architecture = nextpnr_ecp5_architectures[(family + "-" + size)]
# Generate build script
script = _build_script(False, self.build_template, build_name, architecture, package,
speed_grade, timingstrict, ignoreloops, bootaddr, seed, spimode, compress)
# Run
if run:
_run_script(script)
os.chdir(cwd)
return v_output.ns
def add_period_constraint(self, platform, clk, period):
platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(
freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
def add_false_path_constraint(self, platform, from_, to):
from_.attr.add("keep")
to.attr.add("keep")
if (to, from_) not in self.false_paths:
self.false_paths.add((from_, to))
def trellis_args(parser):
toolchain_group = parser.add_argument_group("toolchain")
toolchain_group.add_argument("--yosys-nowidelut", action="store_true", help="Use Yosys's nowidelut mode.")
toolchain_group.add_argument("--yosys-abc9", action="store_true", help="Use Yosys's abc9 mode.")
toolchain_group.add_argument("--nextpnr-timingstrict", action="store_true", help="Use strict Timing mode (Build will fail when Timings are not met).")
toolchain_group.add_argument("--nextpnr-ignoreloops", action="store_true", help="Ignore combinatorial loops in Timing Analysis.")
toolchain_group.add_argument("--nextpnr-seed", default=1, type=int, help="Set Nextpnr's seed.")
toolchain_group.add_argument("--ecppack-bootaddr", default=0, help="Set boot address for next image.")
toolchain_group.add_argument("--ecppack-spimode", default=None, help="Set slave SPI programming mode.")
toolchain_group.add_argument("--ecppack-compress", action="store_true", help="Use Bitstream compression.")
def trellis_argdict(args):
return {
"nowidelut": args.yosys_nowidelut,
"abc9": args.yosys_abc9,
"timingstrict": args.nextpnr_timingstrict,
"ignoreloops": args.nextpnr_ignoreloops,
"bootaddr": args.ecppack_bootaddr,
"spimode": args.ecppack_spimode,
"compress": args.ecppack_compress,
"seed": args.nextpnr_seed,
}
| [
"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file"
] | [((5798, 5865), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(False)'}), '(script_file, script_contents, force_unix=False)\n', (5817, 5865), False, 'from litex.build import tools\n'), ((6253, 6286), 'subprocess.call', 'subprocess.call', (['(shell + [script])'], {}), '(shell + [script])\n', (6268, 6286), False, 'import subprocess\n'), ((7257, 7294), 'os.makedirs', 'os.makedirs', (['build_dir'], {'exist_ok': '(True)'}), '(build_dir, exist_ok=True)\n', (7268, 7294), False, 'import os\n'), ((7309, 7320), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (7318, 7320), False, 'import os\n'), ((7329, 7348), 'os.chdir', 'os.chdir', (['build_dir'], {}), '(build_dir)\n', (7337, 7348), False, 'import os\n'), ((8542, 8555), 'os.chdir', 'os.chdir', (['cwd'], {}), '(cwd)\n', (8550, 8555), False, 'import os\n'), ((6033, 6047), 'shutil.which', 'which', (['"""yosys"""'], {}), "('yosys')\n", (6038, 6047), False, 'from shutil import which\n'), ((6059, 6080), 'shutil.which', 'which', (['"""nextpnr-ecp5"""'], {}), "('nextpnr-ecp5')\n", (6064, 6080), False, 'from shutil import which\n'), ((4751, 4781), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (4779, 4781), False, 'from litex.build import tools\n'), ((4925, 4955), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (4953, 4955), False, 'from litex.build import tools\n')] |
from litex.tools.litex_server import RemoteServer
def litex_srv():
from litex.tools.remote.comm_udp import CommUDP
udp_ip = '192.168.100.50'
udp_port = 1234
comm = CommUDP(udp_ip, udp_port, debug=False)
server = RemoteServer(comm, '127.0.0.1', 1234)
server.open()
server.start(4)
| [
"litex.tools.litex_server.RemoteServer",
"litex.tools.remote.comm_udp.CommUDP"
] | [((181, 219), 'litex.tools.remote.comm_udp.CommUDP', 'CommUDP', (['udp_ip', 'udp_port'], {'debug': '(False)'}), '(udp_ip, udp_port, debug=False)\n', (188, 219), False, 'from litex.tools.remote.comm_udp import CommUDP\n'), ((234, 271), 'litex.tools.litex_server.RemoteServer', 'RemoteServer', (['comm', '"""127.0.0.1"""', '(1234)'], {}), "(comm, '127.0.0.1', 1234)\n", (246, 271), False, 'from litex.tools.litex_server import RemoteServer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from litex.build.generic_platform import *
from litex.build.efinix.platform import EfinixPlatform
from litex.build.efinix.programmer import EfinixAtmelProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk33", 0, Pins("C3"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), # net PLL_IN
# Buttons
("user_btn", 0, Pins("G1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
("user_btn", 1, Pins("F1"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("WEAK_PULLUP")),
# Leds
("user_led", 0, Pins("G4"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 1, Pins("J2"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 2, Pins("C2"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 3, Pins("E3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
("user_led", 4, Pins("B3"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")),
# SPIFlash (W25Q80DV)
("spiflash", 0,
Subsignal("cs_n", Pins("J4")), # net SPI_SS
Subsignal("clk", Pins("H4")), # net SPI_SCLK
Subsignal("mosi", Pins("F4")), # net SPI_MOSI
Subsignal("miso", Pins("H3")), # net SPI_MISO
#Subsignal("wp", Pins("")),
#Subsignal("hold", Pins("")),
IOStandard("3.3_V_LVTTL_/_LVCMOS")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# use "j3:1" reference for pin 1 of J3. This makes it a 1:1 translation with connector numbering
("j3", "ZERO #N/A #N/A G5 F1 G4 E1 J3 C2 G3 D2 J2 E3 H2 D3 F3 C3 G1 B3 #N/A #N/A A2 A2"),
("j4", "ZERO #N/A #N/A A5 B8 B5 C8 C5 D6 A6 B9 B6 C9 C6 D7 C7 D8 A8 D9 A9 E8 A2 A2"),
("j5", "ZERO #N/A #N/A F8 J9 E7 J8 F7 G8 E6 H8 F6 J7 F5 G6 G9 H6 H9 J6 #N/A #N/A A2 A2"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(EfinixPlatform):
default_clk_name = "clk33"
default_clk_period = 1e9/33.333e6
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "T8F81C2", _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return EfinixAtmelProgrammer()
def do_finalize(self, fragment):
EfinixPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk33", loose=True), 1e9/33.333e6)
| [
"litex.build.efinix.platform.EfinixPlatform.do_finalize",
"litex.build.efinix.platform.EfinixPlatform.__init__",
"litex.build.efinix.programmer.EfinixAtmelProgrammer"
] | [((2365, 2444), 'litex.build.efinix.platform.EfinixPlatform.__init__', 'EfinixPlatform.__init__', (['self', '"""T8F81C2"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'T8F81C2', _io, _connectors, toolchain=toolchain)\n", (2388, 2444), False, 'from litex.build.efinix.platform import EfinixPlatform\n'), ((2494, 2517), 'litex.build.efinix.programmer.EfinixAtmelProgrammer', 'EfinixAtmelProgrammer', ([], {}), '()\n', (2515, 2517), False, 'from litex.build.efinix.programmer import EfinixAtmelProgrammer\n'), ((2564, 2606), 'litex.build.efinix.platform.EfinixPlatform.do_finalize', 'EfinixPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2590, 2606), False, 'from litex.build.efinix.platform import EfinixPlatform\n')] |
#!/usr/bin/env python3
from litex import RemoteClient
import time
wb = RemoteClient()
wb.open()
# Test patterns: 4 (words) x 32 (bits)
#pattern = 0xffffffffffffffffffffffffffffffff
#pattern = 0x00000000000000000000000000000000
pattern = 0xa5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5
#pattern = 0x5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a
#pattern = 0xaaaaaaaa55555555aaaaaaaa55555555
#pattern = 0xaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
#pattern = 0x55555555555555555555555555555555
# Disable bulk write
wb.regs.bulk_wr_enabled.write(0)
# Reset
wb.regs.bulk_wr_reset.write(1)
wb.regs.bulk_wr_reset.write(0)
# Configure
wb.regs.bulk_wr_address.write(0x00000000) # Without offset
wb.regs.bulk_wr_dataword.write(pattern)
# Arty-A7: 256 MiB DDR3 memory divided by 4 bytes per word and 4 words per write
wb.regs.bulk_wr_count.write(int(256 * 1024 * 1024 / 4 / 4) - 1)
# Enable bulk write
wb.regs.bulk_wr_enabled.write(1)
# Wait until done
while not wb.regs.bulk_wr_done.read():
time.sleep(1 / 1e6) # 1us
# Stop bulk write
wb.regs.bulk_wr_enabled.write(0)
# Dump last words of the memory
#print('rowhammer: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0x0 * 4, 8)]))
#for m in [(int(256 * 1024 * 1024 / 4) - 1 - 4), (int(256 * 1024 * 1024 / 4) - 1)]:
# print('0x{:08x}: 0x{:08x}'.format(0x40000000 + m * 4, wb.read(0x40000000 + m * 4, 1)[0] ))
wb.close()
| [
"litex.RemoteClient"
] | [((73, 87), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (85, 87), False, 'from litex import RemoteClient\n'), ((957, 982), 'time.sleep', 'time.sleep', (['(1 / 1000000.0)'], {}), '(1 / 1000000.0)\n', (967, 982), False, 'import time\n')] |
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