code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
#!/usr/bin/env python3
import argparse
import os
from migen import * # noqa: F403
from litex.build.generic_platform import * # noqa: F403
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integration.common import * # noqa: F403
from litex.soc.integration.soc_cor... | [
"litex.build.sim.config.SimConfig",
"litex.build.sim.SimPlatform.__init__"
] | [((3875, 3907), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {'default_clk': '"""sys_clk"""'}), "(default_clk='sys_clk')\n", (3884, 3907), False, 'from litex.build.sim.config import SimConfig\n'), ((7164, 7190), 'litex_boards.targets.arty.BaseSoC', 'arty.BaseSoC', ([], {}), '(**soc_kwargs)\n', (7176, 7190), Fa... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Built In Self Test (BIST) modules for testing LiteDRAM functionality."""
from functools import reduce
from operator import xor
from migen impor... | [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((4516, 4544), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'LiteDRAMDMAWriter', (['dram_port'], {}), '(dram_port)\n', (4533, 4544), False, 'from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader\n'), ((7161, 7189), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'LiteDRAMDMAWriter', (['dram_port'], {}), '(dr... |
# This file is Copyright (c) 2017-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016-2017 <NAME> <<EMAIL>>
# License: BSD
import unittest
import random
from collections import namedtuple
from migen import *
from litex.soc.cores import code_8b10b
Control = namedtuple("Control", "value")
code_8b10b_data_rd_m =... | [
"litex.soc.cores.code_8b10b.Encoder",
"litex.soc.cores.code_8b10b.disparity",
"litex.soc.cores.code_8b10b.Decoder"
] | [((266, 296), 'collections.namedtuple', 'namedtuple', (['"""Control"""', '"""value"""'], {}), "('Control', 'value')\n", (276, 296), False, 'from collections import namedtuple\n'), ((10898, 10918), 'litex.soc.cores.code_8b10b.Encoder', 'code_8b10b.Encoder', ([], {}), '()\n', (10916, 10918), False, 'from litex.soc.cores ... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs --------------------------------... | [
"litex.build.generic_platform.Misc",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.generic_platform.Pins",
"litex.build.generic_platform.IOStandard"
] | [((425, 436), 'litex.build.generic_platform.Pins', 'Pins', (['"""N11"""'], {}), "('N11')\n", (429, 436), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((438, 460), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (448, 460), F... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import math
from migen import *
from migen.genlib.misc import WaitTimer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
# Led Chaser -----------------------------... | [
"litex.soc.cores.pwm.PWM",
"litex.soc.interconnect.wishbone.Interface"
] | [((1334, 1438), 'litex.soc.cores.pwm.PWM', 'PWM', ([], {'with_csr': 'with_csr', 'default_enable': '(1)', 'default_width': 'default_width', 'default_period': 'default_period'}), '(with_csr=with_csr, default_enable=1, default_width=default_width,\n default_period=default_period)\n', (1337, 1438), False, 'from litex.so... |
# This file is Copyright (c) 2017 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs --------------------------------------... | [
"litex.build.lattice.programmer.LatticeProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((7005, 7092), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5UM5G-45F-8BG381C"""', '_io', '_connectors'], {}), "(self, 'LFE5UM5G-45F-8BG381C', _io, _connectors, **\n kwargs)\n", (7029, 7092), False, 'from litex.build.lattice import LatticePlatform\n'), ((9198, 9230), ... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use ----------------------------------------------------------------------------------------
#
# 1) SoC with regular UART and optional Ethernet connected to the CPU:
# ... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((8325, 8394), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Colorlight 5A-75X"""'}), "(description='LiteX SoC on Colorlight 5A-75X')\n", (8348, 8394), False, 'import argparse\n'), ((9782, 9802), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}),... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# U11F
("clk50", 0, Pins("R2"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("U2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("M5")), # MCU_RX
Subsigna... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4291, 4366), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50t-csg325-2"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a50t-csg325-2', _io, toolchain=toolchain)\n", (4314, 4366), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((5944, 5... |
"""Module for talking to TOFE boards."""
from migen.fhdl import *
from litex.soc.cores.gpio import GPIOIn, GPIOOut
from litex.soc.interconnect.csr import *
from gateware import i2c
class TOFE(Module, AutoCSR):
"""Common TOFE parts."""
def __init__(self, platform):
# TOFE board
tofe_pads = p... | [
"litex.soc.cores.gpio.GPIOIn",
"litex.soc.cores.gpio.GPIOOut"
] | [((374, 392), 'gateware.i2c.I2C', 'i2c.I2C', (['tofe_pads'], {}), '(tofe_pads)\n', (381, 392), False, 'from gateware import i2c\n'), ((688, 710), 'litex.soc.cores.gpio.GPIOOut', 'GPIOOut', (['tofe_reset.oe'], {}), '(tofe_reset.oe)\n', (695, 710), False, 'from litex.soc.cores.gpio import GPIOIn, GPIOOut\n'), ((1108, 112... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
from litex.build import tools
class GenericProgrammer:
def __init__(self, flash_proxy_basename=None):
self.flash_p... | [
"litex.build.tools.cygpath"
] | [((1547, 1571), 'os.path.exists', 'os.path.exists', (['fullname'], {}), '(fullname)\n', (1561, 1571), False, 'import os\n'), ((1682, 1725), 'os.makedirs', 'os.makedirs', (['self.prog_local'], {'exist_ok': '(True)'}), '(self.prog_local, exist_ok=True)\n', (1693, 1725), False, 'import os\n'), ((2301, 2327), 'litex.build.... |
#!/usr/bin/env python3
import sys
import os
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import... | [
"litex.gen.genlib.resetsync.AsyncResetSynchronizer",
"litex.soc.cores.xadc.XADC",
"litex.soc.cores.dna.DNA",
"litex.soc.cores.frequency_meter.FrequencyMeter",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((4422, 4497), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50t-csg325-2"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a50t-csg325-2', _io, toolchain=toolchain)\n", (4445, 4497), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((6075, 6117), 'litex.build... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Load bitstream:
# ./decklink_quad_hdmi_recorder.py --csr-csv=csr.csv --build --load
#
# Use:
# litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg
# litex_term cros... | [
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((4671, 4765), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on Blackmagic Decklink Quad HDMI Recorder"""'}), "(description=\n 'LiteX SoC on Blackmagic Decklink Quad HDMI Recorder')\n", (4693, 4765), False, 'from litex.soc.integration.soc import Lit... |
from itertools import product
from sys import stdout
import time
from collections import defaultdict
import json
import ctypes
from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
analyzer = LiteSc... | [
"litex.tools.litex_client.RemoteClient"
] | [((255, 291), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (267, 291), False, 'from litex.tools.litex_client import RemoteClient\n'), ((314, 407), 'litescope.software.driver.analyzer.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (... |
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
"""
AXI frontend for LiteDRAM
Converts AXI ports to Native ports.
Features:
- Write/Read arbitration.
- Write/Read data buffers (configurable depth).
- Burst support (FIXED/INCR/WRAP).
- ID support (configurable width).
Limitations:
- Response a... | [
"litex.soc.interconnect.stream.SyncFIFO"
] | [((1554, 1607), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[('id', axi.id_width)]", 'buffer_depth'], {}), "([('id', axi.id_width)], buffer_depth)\n", (1569, 1607), False, 'from litex.soc.interconnect import stream\n'), ((1630, 1696), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[... |
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
identifier = ""
for i in range(30):
identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
print("link up : {}".format(wb.r... | [
"litex.RemoteClient"
] | [((37, 51), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (49, 51), False, 'from litex import RemoteClient\n')] |
from migen import Module, Signal, If, Instance
from litex.soc.interconnect.csr import AutoCSR, CSRStorage
class Reboot(Module, AutoCSR):
def __init__(self, rst, ext_rst=None):
self.ctrl = CSRStorage(8)
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b1010110... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((202, 215), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {}), '(8)\n', (212, 215), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage\n'), ((244, 252), 'migen.Signal', 'Signal', ([], {}), '()\n', (250, 252), False, 'from migen import Module, Signal, If, Instance\n'), ((541, 556), '... |
from migen import Module, Instance, Signal
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
class SBWarmBoot(Module, AutoCSR):
def __init__(self, parent):
self.ctrl = CSRStorage(size=8)
self.addr = CSRStorage(size=32)
do_reset = Signal()
self.comb += [
... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((201, 219), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'size': '(8)'}), '(size=8)\n', (211, 219), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((240, 259), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'size': '(32)'}), '(size=32)\n', (250, 259), ... |
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("AB1"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AB8"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("A... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2830, 2904), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-fgg484-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a35t-fgg484-2', _io, toolchain='vivado')\n", (2853, 2904), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ---------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4976, 5068), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg484-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg484-2', _io, _connectors,\n toolchain='vivado')\n", (4999, 5068), False, 'from litex.build.xilinx import XilinxPlat... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Dolu1990 <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from os import path
from migen import *
from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import ... | [
"litex.get_data_mod",
"litex.soc.interconnect.wishbone.Interface"
] | [((12651, 12671), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (12669, 12671), False, 'from litex.soc.interconnect import wishbone\n'), ((17981, 18001), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (17999, 18001), False, 'from litex.soc.int... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
import os
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from axilite2led import AxiLite2Led
from litedram.frontend.adapter import LiteD... | [
"litex.soc.integration.soc.SoCRegion",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((13894, 13957), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Nexys Video"""'}), "(description='LiteX SoC on Nexys Video')\n", (13917, 13957), False, 'import argparse\n'), ((15002, 15027), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ---------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3902, 3977), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg484-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg484-2', _io, toolchain='vivado')\n", (3925, 3977), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((4596, 4654), 'litex.b... |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU
class Open(Signal): pass
# EOS-S3 ... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((1400, 1447), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)', 'adr_width': '(15)'}), '(data_width=32, adr_width=15)\n', (1418, 1447), False, 'from litex.soc.interconnect import wishbone\n')] |
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.gen import *
from litex.soc.interconnect import stream
from litedram.frontend import dma
def _inc(signal, modulo):
if modulo == 2**len(signal):
return signal.eq(signal + 1)
else:
return If(signal == (modulo - ... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((1686, 1725), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (1701, 1725), False, 'from litex.soc.interconnect import stream\n'), ((1784, 1826), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'dma.LiteDRAMDMAWriter', (['port'], {'fifo_depth': '... |
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
_butterstick_r1d0_io = [
("clk30", 0, Pins("B12"), IOStandard("LVCMOS18")),
("rst_n", 0, Pins("R3"), IOStandard("LVCMOS33")),
("user_led", 0, Pi... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((6126, 6250), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5UM5G-85F-8BG381C"""', '_butterstick_r1d0_io', '_connectors'], {'toolchain': '"""trellis"""'}), "(self, 'LFE5UM5G-85F-8BG381C', _butterstick_r1d0_io,\n _connectors, toolchain='trellis', **kwargs)\n", (6150, 6... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import argparse
from migen import *
import radiona_ulx3s
from litex.build.lat... | [
"litex.build.sim.verilator.verilator_build_args",
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.sim.gtkwave.wishbone_sorter",
"litex.build.sim.gtkwave.wishbone_colorer",
"litex.build.sim.verilator.verilator_build_argdict",
"litex.build.sim.gtkwave.dfi_sorter",
"litex.build.sim.gtkwave.dfi_... | [((8350, 8378), 'litex.build.sim.verilator.verilator_build_args', 'verilator_build_args', (['parser'], {}), '(parser)\n', (8370, 8378), False, 'from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict\n'), ((10213, 10279), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentP... |
#!/usr/bin/env python3
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
CTRL_START = (1 << 0)
CTRL_LENGTH = (1 << 8)
STATUS_DONE = (1 << 0)
STATUS_ONGOING = (1 << 0)
# Registers
READ_ID = 0x9F
READ = 0x03
WREN = 0x06
WRDI = 0x04
PP = 0x02
SE = 0xD8
BE ... | [
"litex.RemoteClient"
] | [((74, 88), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (86, 88), False, 'from litex import RemoteClient\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Direct Memory Access (DMA) reader and writer modules."""
from migen ... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((1573, 1623), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', port.address_width)]"], {}), "([('address', port.address_width)])\n", (1588, 1623), False, 'from litex.soc.interconnect import stream\n'), ((1655, 1699), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data',... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import arty
from litex.build.xilinx.vivado imp... | [
"litex.build.generic_platform.Misc",
"litex.build.generic_platform.Pins",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.build.generic_platform.IOStandard"
] | [((7972, 8031), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Arty A7"""'}), "(description='LiteX SoC on Arty A7')\n", (7995, 8031), False, 'import argparse\n'), ((9856, 9881), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n... |
#!/usr/bin/env python3
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("Reboot...")
wb.regs.gpio1_out.write(1)
time.sleep(0.5)
wb.regs.gpio1_out.write(0)
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((74, 88), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (86, 88), False, 'from litex import RemoteClient\n'), ((153, 168), 'time.sleep', 'time.sleep', (['(0.5)'], {}), '(0.5)\n', (163, 168), False, 'import time\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex_boards.platforms import lpddr4_test_board
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.so... | [
"litex.soc.integration.soc.SoCRegion",
"litex.soc.integration.soc.LiteXSoCArgumentParser",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((5282, 5350), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on LPDDR4 Test Board"""'}), "(description='LiteX SoC on LPDDR4 Test Board')\n", (5304, 5350), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((6884, 6909), 'litex.b... |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.stream import Endpoint, EndpointDescrip... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((558, 582), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 32)]"], {}), "([('data', 32)])\n", (566, 582), False, 'from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO\n'), ((1015, 1075), 'rtl.edge_detect.EdgeDetect', 'EdgeDetect', ([], {'mode': '"""fall"""', 'input_cd... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# Copyright (c) 2016-2019 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
CSR-2 bus
=========
The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing
the... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((8120, 8143), 'migen.util.misc.xdir', 'xdir', (['self.source', '(True)'], {}), '(self.source, True)\n', (8124, 8143), False, 'from migen.util.misc import xdir\n'), ((3579, 3634), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['page_bits'], {'name': "(mem.name_override + '_page')"}), "(page_bits, name=mem.na... |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((1261, 1281), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1279, 1281), False, 'from litex.soc.interconnect import wishbone\n'), ((4133, 4168), 'os.path.exists', 'os.path.exists', (['"""femtorv32_quark.v"""'], {}), "('femtorv32_quark.v')\n", (4147, 4168), False, 'import os\n')... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Marble-Mini is a simple AMC FMC carrier board with SFP, 2x FMC, PoE, DDR3:
# https://github.com/BerkeleyLab/Marble-Mini
from litex.build.generic_platform import *
from litex.build.xilinx impor... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((7806, 7898), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-2fgg484"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7a100t-2fgg484', _io, _connectors,\n toolchain=toolchain)\n", (7829, 7898), False, 'from litex.build.xilinx import XilinxPlatform... |
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 msloniewski <<EMAIL>>
# This file is Copyright (c) 2019 vytautasb <<EMAIL>>
# License: BSD
import os
import subprocess
import sys
import math
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import P... | [
"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file",
"litex.build.generic_platform.Pins"
] | [((5447, 5525), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['build_script_file', 'build_script_contents'], {'force_unix': '(True)'}), '(build_script_file, build_script_contents, force_unix=True)\n', (5466, 5525), False, 'from litex.build import tools\n'), ((5582, 5606), 'subprocess.call', 'subprocess.ca... |
#
# This file is part of USB3-PIPE project.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.common import TSEQ, TS1, TS1_INV, TS2
# Training Sequence Checker --------------------------------------------... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((871, 915), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (886, 915), False, 'from litex.soc.interconnect import stream\n'), ((4553, 4597), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2015 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd ... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((19609, 19701), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k325t-ffg900-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7k325t-ffg900-2', _io, _connectors,\n toolchain='vivado')\n", (19632, 19701), False, 'from litex.build.xilinx import Xilinx... |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "nextpnr-ecp5", "yosys"]
# Import lxbuildenv to integrate ... | [
"litex.soc.cores.bitbang.I2CMaster",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__",
"litex.build.generic_platform.Inverted",
"litex.soc.integration.builder.Builder",
"litex.build.generic_platform.Pins",
"litex.build.sim.platform.SimPlatform.__init__",
... | [((20283, 20376), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build the Hack a Day Supercon 2019 Badge firmware"""'}), "(description=\n 'Build the Hack a Day Supercon 2019 Badge firmware')\n", (20306, 20376), False, 'import argparse\n'), ((21940, 22104), 'litex.soc.integration.buil... |
#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.platforms import zcu104
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import colorer
from litex.soc.cores.clock import USM... | [
"litex.soc.interconnect.axi.AXILite2Wishbone",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.axi.AXI2AXILite",
"litex.soc.cores.clock.AsyncResetSynchronizer",
"litex.soc.cores.clock.USIDELAYCTRL",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.builder.Builde... | [((9079, 9137), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on ZCU104"""'}), "(description='LiteX SoC on ZCU104')\n", (9102, 9137), False, 'import argparse\n'), ((9143, 9216), 'rowhammer_tester.targets.common.parser_args', 'common.parser_args', (['parser'], {'sys_clk_freq': ... |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from migen.genlib.roundrobin import *
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from litex.gen import *
from litex.soc.interconnect import stream
# TODO: clean up code below
# XXX
class St... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((4671, 4704), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['sink_description'], {}), '(sink_description)\n', (4686, 4704), False, 'from litex.soc.interconnect import stream\n'), ((4736, 4771), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['source_description'], {}), '(source_descrip... |
from migen import *
from migen.genlib.io import CRG
from targets import *
from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer
... | [
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.build.xilinx.platform.XilinxPlatform.__init__"
] | [((632, 670), 'litex.build.xilinx.platform.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '""""""', '_io'], {}), "(self, '', _io)\n", (655, 670), False, 'from litex.build.xilinx.platform import XilinxPlatform\n'), ((1144, 1293), 'litex.soc.integration.soc_core.SoCCore.__init__', 'SoCCore.__init__', (['s... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3319, 3409), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7s15-ftgb196"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7s15-ftgb196', _io, _connectors, toolchain\n ='vivado')\n", (3342, 3409), False, 'from litex.build.xilinx import XilinxPlatform\... |
import logging
Logger = logging.getLogger(__name__)
import socket
import sys
import time
import numpy as np
from litex import RemoteClient
from misc import ADC, DataBlock
from banyan_ch_find import banyan_ch_find
from get_raw_adcs import collect_adcs
from zest_setup import c_prc
from ltc_setup_litex_client import in... | [
"litex.RemoteClient"
] | [((24, 51), 'logging.getLogger', 'logging.getLogger', (['__name__'], {}), '(__name__)\n', (41, 51), False, 'import logging\n'), ((2021, 2035), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (2033, 2035), False, 'from litex import RemoteClient\n'), ((2115, 2131), 'ltc_setup_litex_client.initLTC', 'initLTC', (['... |
#!/usr/bin/env python3
import sys
import argparse
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
parser = argparse.ArgumentParser()
#parser.add_argument("--ibus_stb", action="store_true", help="Trigger on IBus Stb rising edge.")
#parser.add_argument("--ibus_adr", default=0x00000000, ... | [
"litex.RemoteClient"
] | [((139, 164), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (162, 164), False, 'import argparse\n'), ((548, 562), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (560, 562), False, 'from litex import RemoteClient\n'), ((592, 648), 'litescope.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzer... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2022 Lone Dynamics Corporation <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Krote FPGA board: https://github.com/m... | [
"litex.soc.integration.soc.SoCRegion",
"litex.soc.cores.clock.iCE40PLL"
] | [((3804, 3861), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Kröte"""'}), "(description='LiteX SoC on Kröte')\n", (3827, 3861), False, 'import argparse\n'), ((1526, 1536), 'litex.soc.cores.clock.iCE40PLL', 'iCE40PLL', ([], {}), '()\n', (1534, 1536), False, 'from litex.soc.... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import camlink_4k
from litex.build.latti... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((4028, 4091), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Cam Link 4K"""'}), "(description='LiteX SoC on Cam Link 4K')\n", (4051, 4091), False, 'import argparse\n'), ((4525, 4545), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2022 <NAME> @hubmartin (Twitter)
# Copyright (c) 2022 Raptor Engineering, LLC
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import ... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.cores.video.VideoGenericPHY"
] | [((7265, 7352), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Arctic Tern (BMC card carrier)"""'}), "(description=\n 'LiteX SoC on Arctic Tern (BMC card carrier)')\n", (7288, 7352), False, 'import argparse\n'), ((8198, 8218), 'litex.build.lattice.trellis.trellis_args', '... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ---... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((8365, 8458), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-CSG324-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7a100t-CSG324-1', _io, _connectors,\n toolchain=toolchain)\n", (8388, 8458), False, 'from litex.build.xilinx import XilinxPlatfo... |
#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import versa_ecp5
from litex.build.lattice.... | [
"litex.build.lattice.trellis.trellis_argdict",
"litex.soc.integration.export.get_csr_csv",
"litex.build.tools.write_to_file",
"litex.build.lattice.trellis.trellis_args"
] | [((7679, 7741), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Versa ECP5"""'}), "(description='LiteX SoC on Versa ECP5')\n", (7702, 7741), False, 'import argparse\n'), ((7944, 7964), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n',... |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import ecp5_evn
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import... | [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.cores.dma.WishboneDMAWriter",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.csr.CSRField"
] | [((4525, 4598), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on ECP5 Evaluation Board"""'}), "(description='LiteX SoC on ECP5 Evaluation Board')\n", (4548, 4598), False, 'import argparse\n'), ((1401, 1444), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchroni... |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import argparse
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.soc.cores.clock imp... | [
"litex.build.lattice.LatticePlatform.__init__"
] | [((4504, 4623), 'os.system', 'os.system', (['"""openocd -f openocd.cfg -c "transport select jtag; init; svf build/gateware/ios_stream.svf; exit\\""""'], {}), '(\n \'openocd -f openocd.cfg -c "transport select jtag; init; svf build/gateware/ios_stream.svf; exit"\'\n )\n', (4513, 4623), False, 'import os\n'), ((475... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2022 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen i... | [
"litex.soc.interconnect.stream.AsyncFIFO",
"litex.soc.interconnect.stream.Endpoint"
] | [((12313, 12352), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (12328, 12352), False, 'from litex.soc.interconnect import stream\n'), ((12384, 12423), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"],... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import argparse
from migen import *
from migen.genlib.resetsync import AsyncRe... | [
"litex.soc.integration.soc.SoCRegion",
"litex.soc.cores.ram.Up5kSPRAM",
"litex.build.dfu.DFUProg",
"litex.soc.cores.clock.iCE40PLL"
] | [((5901, 5932), 'litex.build.dfu.DFUProg', 'DFUProg', ([], {'vid': '"""1209"""', 'pid': '"""5bf0"""'}), "(vid='1209', pid='5bf0')\n", (5908, 5932), False, 'from litex.build.dfu import DFUProg\n'), ((6804, 6860), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Fomu"""'}), "(de... |
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs -------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((7349, 7439), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50tfgg484-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a50tfgg484-1', _io, _connectors,\n toolchain='vivado')\n", (7372, 7439), False, 'from litex.build.xilinx import XilinxPlatform... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ---------------------------------------------------... | [
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.AlteraPlatform.do_finalize"
] | [((2510, 2581), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP3C25E144C8"""', '_io'], {'toolchain': '"""quartus"""'}), "(self, 'EP3C25E144C8', _io, toolchain='quartus')\n", (2533, 2581), False, 'from litex.build.altera import AlteraPlatform\n'), ((3979, 3991), 'litex.build.alt... |
#!/usr/bin/env python3
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
("user_sw",... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((970, 1045), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (993, 1045), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2016-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect import stream
from litedram.common import *
# LiteDRAMNativePortCDC -------------------------------... | [
"litex.soc.interconnect.stream.ClockDomainCrossing",
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream.StrideConverter",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((899, 1056), 'litex.soc.interconnect.stream.ClockDomainCrossing', 'stream.ClockDomainCrossing', ([], {'layout': "[('we', 1), ('addr', address_width)]", 'cd_from': 'port_from.clock_domain', 'cd_to': 'port_to.clock_domain', 'depth': 'cmd_depth'}), "(layout=[('we', 1), ('addr', address_width)],\n cd_from=port_from.cl... |
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import AutoCSR
from migen import *
from litex.soc.interconnect import wishbone
class HardSPIWrapper(Module):
def __init__(self, instance):
assert instance in [0, 1]
# CSn
self.mcsnoe = Signal(4)
... | [
"litex.soc.interconnect.wishbone.Interface"
] | [((2723, 2743), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2741, 2743), False, 'from litex.soc.interconnect import wishbone\n')] |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect import stream
from litex.soc.interconnect.csr import Au... | [
"litex.soc.interconnect.stream.AsyncFIFO",
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.stream.Endpoint"
] | [((659, 683), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 32)]"], {}), "([('data', 32)])\n", (667, 683), False, 'from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO\n'), ((1116, 1176), 'rtl.edge_detect.EdgeDetect', 'EdgeDetect', ([], {'mode': '"""fall"""', 'input_cd... |
#
# This file is part of LiteX-on-proFPGA-Systems.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ---------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((1909, 2004), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xcvu19p-fsva3824-2-e"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xcvu19p-fsva3824-2-e', _io, _connectors,\n toolchain='vivado')\n", (1932, 2004), False, 'from litex.build.xilinx import Xili... |
#
# This file is part of LiteSPI
#
# Copyright (c) 2020-2021 Antmicro <www.antmicro.com>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import WaitTimer
from litespi.common import *
from litespi.clkgen import LiteSPIClkGen
from litex.soc.inter... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.build.io.SDROutput",
"litex.build.io.SDRInput"
] | [((1784, 1820), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy2core_layout'], {}), '(spi_phy2core_layout)\n', (1799, 1820), False, 'from litex.soc.interconnect import stream\n'), ((1862, 1898), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_core2phy_layout'], {}), '(spi_cor... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2020-2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integr... | [
"litex.build.sim.gtkwave.dfi_in_phase_colorer",
"litex.build.sim.gtkwave.wishbone_sorter",
"litex.build.sim.gtkwave.wishbone_colorer",
"litex.build.sim.gtkwave.dfi_sorter",
"litex.build.sim.gtkwave.dfi_per_phase_colorer",
"litex.build.sim.config.SimConfig",
"litex.build.sim.gtkwave.GTKWSave",
"litex.b... | [((10250, 10317), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Generic LiteX SoC Simulation"""'}), "(description='Generic LiteX SoC Simulation')\n", (10273, 10317), False, 'import argparse\n'), ((12433, 12444), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {}), '()\n', (12442, ... |
#!/usr/bin/env python3
import time
import numpy as np
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
x = np.linspace(0,2 * np.pi, 1000)
sine = (2**15 * np.sin(x)) + 2**15
sine = sine.astype('int').tolist()
print("artistic sine output...")
i = 0
while(1):
i = (i + 1) % 1000
wb.regs.dac... | [
"litex.RemoteClient"
] | [((93, 107), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (105, 107), False, 'from litex import RemoteClient\n'), ((130, 161), 'numpy.linspace', 'np.linspace', (['(0)', '(2 * np.pi)', '(1000)'], {}), '(0, 2 * np.pi, 1000)\n', (141, 161), True, 'import numpy as np\n'), ((177, 186), 'numpy.sin', 'np.sin', (['x... |
#
# This file is part of LiteX-Boards.
# FPGA Board Info : https://shop.trenz-electronic.de/en/TE0725-03-35-2C-FPGA-Module-with-Xilinx-Artix-7-XC7A35T-2CSG324C-2-x-50-Pin-with-2.54-mm-pitch
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from l... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2645, 2735), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35tcsg324-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a35tcsg324-2', _io, _connectors,\n toolchain='vivado')\n", (2668, 2735), False, 'from litex.build.xilinx import XilinxPlatform... |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys", "nextpnr-ice40"]
# Import lxbuildenv ... | [
"litex.soc.doc.generate_docs",
"litex.soc.integration.builder.Builder",
"litex.build.generic_platform.Pins",
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.soc.cores.spi_flash.SpiFlashDualQuad",
"litex.soc.interconnect.wishbone.SRAM"
] | [((10355, 10418), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build Fomu Main Gateware"""'}), "(description='Build Fomu Main Gateware')\n", (10378, 10418), False, 'import argparse\n'), ((12329, 12354), 'rtl.platform.fomu.add_platform_args', 'add_platform_args', (['parser'], {}), '(par... |
from itertools import product
from sys import stdout
import json
import ctypes
from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=Tru... | [
"litex.tools.litex_client.RemoteClient"
] | [((207, 243), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (219, 243), False, 'from litex.tools.litex_client import RemoteClient\n'), ((266, 359), 'litescope.software.driver.analyzer.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (... |
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