code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
#!/usr/bin/env python3
import argparse
import os
from migen import * # noqa: F403
from litex.build.generic_platform import * # noqa: F403
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integration.common import * # noqa: F403
from litex.soc.integration.soc_core import * # noqa: F403
from litex.soc.integration.soc_sdram import * # noqa: F403
from litex.soc.integration.builder import * # noqa: F403
from litex.soc.integration.soc import * # noqa: F403
from litex.soc.interconnect.csr import * # noqa: F403
from litex.soc.cores.bitbang import * # noqa: F403
from litex.soc.cores.cpu import CPUS
_io = [
("sys_clk", 0, Pins(1)), # noqa: F405
("sys_rst", 0, Pins(1)), # noqa: F405
("serial", 0,
Subsignal("source_valid", Pins(1)), # noqa: F405
Subsignal("source_ready", Pins(1)), # noqa: F405
Subsignal("source_data", Pins(8)), # noqa: F405
Subsignal("sink_valid", Pins(1)), # noqa: F405
Subsignal("sink_ready", Pins(1)), # noqa: F405
Subsignal("sink_data", Pins(8)), ), # noqa: F405
]
class Platform(SimPlatform):
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
class Supervisor(Module, AutoCSR): # noqa: F405
def __init__(self):
self._finish = CSR() # controlled from CPU # noqa: F405
self.finish = Signal() # controlled from logic # noqa: F405
self.sync += If(self._finish.re | self.finish, Finish()) # noqa: F405
class SimSoC(SoCCore): # noqa: F405
def __init__(self, **kwargs):
platform = Platform()
sys_clk_freq = int(1e6)
# SoCCore -------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, # noqa: F405
ident="LiteX Simulation",
ident_version=True, **kwargs)
# Supervisor ----------------------------------------------------------
self.submodules.supervisor = Supervisor()
self.add_csr("supervisor")
# CRG -----------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk")) # noqa: F405
def sim_args(parser):
parser.add_argument("--threads",
default=1,
help="Set number of threads (default=1)")
parser.add_argument("--rom-init",
default=None,
help="rom_init file")
parser.add_argument("--ram-init",
default=None,
help="ram_init file")
parser.add_argument("--trace",
action="store_true",
help="Enable Tracing")
parser.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start",
default=0,
help="Cycle to start tracing")
parser.add_argument("--trace-end",
default=-1,
help="Cycle to end tracing")
parser.add_argument("--opt-level",
default="O3",
help="Compilation optimization level")
parser.add_argument("--run",
default=False,
help="True to run test")
parser.add_argument("--arty",
default=False,
help="True to run test on arty")
parser.add_argument("--use-cache",
default=False,
help="Use caches in rocket chip")
def sim_configuration(args, soc_kwargs, builder_kwargs, test_path):
# Configuration -----------------------------------------------------------
sim_config = SimConfig(default_clk="sys_clk")
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
soc_kwargs['integrated_rom_size'] = 0x10000
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data( # noqa: F405
args.rom_init, cpu.endianness)
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data( # noqa: F405
args.ram_init, cpu.endianness)
# SoC ---------------------------------------------------------------------
if args.cpu_type == 'rocket' and not args.use_cache:
soc_kwargs["user_override"] = {"main_ram": 0x40000000}
soc = SimSoC(
**soc_kwargs)
if args.cpu_type == 'rocket' and args.use_cache:
for bus in soc.cpu.memory_buses:
wb = wishbone.Interface(data_width=bus.data_width,
adr_width=bus.address_width-log2_int(bus.data_width//8))
conv = ResetInserter()(axi.AXI2Wishbone(bus, wb, base_address=0))
soc.submodules += conv
soc.bus.add_master(name="attached memory bus {}".format(wb), master=wb)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
# Build/Run ---------------------------------------------------------------
builder = Builder(soc, **builder_kwargs) # noqa: F405
if args.run:
builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end),
interactive=False)
else:
builder.build(run=False, threads=args.threads, # noqa: F841
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end),
interactive=False)
def arty_configuration(args, soc_kwargs, builder_kwargs, test_path):
from litex_boards.targets import arty
# Configuration -----------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
soc_kwargs['integrated_rom_size'] = 0x10000
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data( # noqa: F405
args.rom_init, cpu.endianness)
soc_kwargs["integrated_main_ram_size"] = 0x20000 # 4KiB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data( # noqa: F405
args.ram_init, cpu.endianness)
# SoC ---------------------------------------------------------------------
if args.cpu_type == 'rocket' and not args.use_cache:
soc_kwargs["user_override"] = {"main_ram": 0x40000000}
soc_kwargs["sys_clk_freq"] = int(100e6)
soc = arty.BaseSoC(
**soc_kwargs)
if args.cpu_type == 'rocket' and args.use_cache:
for bus in soc.cpu.memory_buses:
wb = wishbone.Interface(data_width=bus.data_width,
adr_width=bus.address_width-log2_int(bus.data_width//8))
conv = ResetInserter()(axi.AXI2Wishbone(bus, wb, base_address=0))
soc.submodules += conv
soc.bus.add_master(name="attached memory bus {}".format(wb), master=wb)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
# Build/Run ---------------------------------------------------------------
print(builder_kwargs)
builder = Builder(soc, **builder_kwargs) # noqa: F405
if args.run:
builder.build(run=True)
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
else:
builder.build(run=False)
def main():
print(os.getcwd())
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser) # noqa: F405
soc_sdram_args(parser) # noqa: F405
sim_args(parser) # noqa: F405
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args) # noqa: F405
print(soc_kwargs)
builder_kwargs = builder_argdict(args) # noqa: F405
if not args.arty:
sim_configuration(args, soc_kwargs, builder_kwargs, "")
else:
arty_configuration(args, soc_kwargs, builder_kwargs, "")
if __name__ == "__main__":
main()
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"litex.build.sim.config.SimConfig",
"litex.build.sim.SimPlatform.__init__"
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#
# This file is part of LiteDRAM.
#
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Built In Self Test (BIST) modules for testing LiteDRAM functionality."""
from functools import reduce
from operator import xor
from migen import *
from litex.soc.interconnect import stream
from litex.soc.interconnect.csr import *
from litedram.common import LiteDRAMNativePort
from litedram.frontend.axi import LiteDRAMAXIPort
from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader
# LFSR ---------------------------------------------------------------------------------------------
class LFSR(Module):
"""Linear-Feedback Shift Register to generate a pseudo-random sequence.
Parameters
----------
n_out : int
Width of the output data signal.
n_state : int
LFSR internal state
taps : list of int
LFSR taps (from polynom)
Attributes
----------
o : out
Output data
"""
def __init__(self, n_out, n_state, taps):
self.o = Signal(n_out)
# # #
state = Signal(n_state)
curval = [state[i] for i in range(n_state)]
curval += [0]*(n_out - n_state)
for i in range(n_out):
nv = ~reduce(xor, [curval[tap] for tap in taps])
curval.insert(0, nv)
curval.pop()
self.sync += [
state.eq(Cat(*curval[:n_state])),
self.o.eq(Cat(*curval))
]
# Counter ------------------------------------------------------------------------------------------
class Counter(Module):
"""Simple incremental counter.
Parameters
----------
n_out : int
Width of the output data signal.
Attributes
----------
o : out
Output data
"""
def __init__(self, n_out):
self.o = Signal(n_out)
# # #
self.sync += self.o.eq(self.o + 1)
# Generator ----------------------------------------------------------------------------------------
@CEInserter()
class Generator(Module):
"""Address/Data Generator.
Parameters
----------
n_out : int
Width of the output data signal.
Attributes
----------
random_enable : in
Enable Random (LFSR)
o : out
Output data
"""
def __init__(self, n_out, n_state, taps):
self.random_enable = Signal()
self.o = Signal(n_out)
# # #
lfsr = LFSR(n_out, n_state, taps)
count = Counter(n_out)
self.submodules += lfsr, count
self.comb += \
If(self.random_enable,
self.o.eq(lfsr.o)
).Else(
self.o.eq(count.o)
)
def get_ashift_awidth(dram_port):
if isinstance(dram_port, LiteDRAMNativePort):
ashift = log2_int(dram_port.data_width//8)
awidth = dram_port.address_width + ashift
elif isinstance(dram_port, LiteDRAMAXIPort):
ashift = log2_int(dram_port.data_width//8)
awidth = dram_port.address_width
else:
raise NotImplementedError
return ashift, awidth
# _LiteDRAMBISTGenerator ---------------------------------------------------------------------------
@ResetInserter()
class _LiteDRAMBISTGenerator(Module):
def __init__(self, dram_port):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.base = Signal(awidth)
self.end = Signal(awidth)
self.length = Signal(awidth)
self.random_data = Signal()
self.random_addr = Signal()
self.ticks = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address generators ----------------------------------------------------------------
data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
addr_gen = Generator(31, n_state=31, taps=[27, 30])
self.submodules += data_gen, addr_gen
self.comb += data_gen.random_enable.eq(self.random_data)
self.comb += addr_gen.random_enable.eq(self.random_addr)
# mask random address to the range <base, end), range size must be power of 2
addr_mask = Signal(awidth)
self.comb += addr_mask.eq((self.end - self.base) - 1)
# DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAWriter(dram_port)
self.submodules += dma
cmd_counter = Signal(dram_port.address_width, reset_less=True)
# Data / Address FSM -----------------------------------------------------------------------
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
If(self.start,
NextValue(cmd_counter, 0),
NextState("RUN")
),
NextValue(self.ticks, 0)
)
fsm.act("WAIT",
If(self.run_cascade_in,
NextState("RUN")
)
)
fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.run_cascade_out.eq(1),
data_gen.ce.eq(1),
addr_gen.ce.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (self.length[ashift:] - 1),
NextState("DONE")
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
),
NextValue(self.ticks, self.ticks + 1)
)
fsm.act("DONE",
self.run_cascade_out.eq(1),
self.done.eq(1)
)
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
dma_sink_addr = dma.sink.address[ashift:]
else:
raise NotImplementedError
self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
self.comb += dma.sink.data.eq(data_gen.o)
@ResetInserter()
class _LiteDRAMPatternGenerator(Module):
def __init__(self, dram_port, init=[]):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.ticks = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address pattern -------------------------------------------------------------------
addr_init, data_init = zip(*init)
addr_mem = Memory(dram_port.address_width, len(addr_init), init=addr_init)
data_mem = Memory(dram_port.data_width, len(data_init), init=data_init)
addr_port = addr_mem.get_port(async_read=True)
data_port = data_mem.get_port(async_read=True)
self.specials += addr_mem, data_mem, addr_port, data_port
# DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAWriter(dram_port)
self.submodules += dma
cmd_counter = Signal(dram_port.address_width, reset_less=True)
# Data / Address FSM -----------------------------------------------------------------------
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
fsm.act("IDLE",
If(self.start,
NextValue(cmd_counter, 0),
NextState("RUN")
),
NextValue(self.ticks, 0)
)
fsm.act("WAIT",
If(self.run_cascade_in,
NextState("RUN")
)
)
fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.run_cascade_out.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (len(init) - 1),
NextState("DONE")
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
),
NextValue(self.ticks, self.ticks + 1)
)
fsm.act("DONE",
self.run_cascade_out.eq(1),
self.done.eq(1)
)
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
dma_sink_addr = dma.sink.address[ashift:]
else:
raise NotImplementedError
self.comb += [
addr_port.adr.eq(cmd_counter),
dma_sink_addr.eq(addr_port.dat_r),
data_port.adr.eq(cmd_counter),
dma.sink.data.eq(data_port.dat_r),
]
# LiteDRAMBISTGenerator ----------------------------------------------------------------------------
class LiteDRAMBISTGenerator(Module, AutoCSR):
"""DRAM memory pattern generator.
Attributes
----------
reset : in
Reset the module.
start : in
Start the generation.
done : out
The module has completed writing the pattern.
base : in
DRAM address to start from.
end : in
Max DRAM address.
length : in
Number of DRAM words to write.
random_data : in
Enable random data (LFSR)
random_addr : in
Enable random address (LFSR). Wrapped to (end - base), so may not be unique.
ticks : out
Duration of the generation.
"""
def __init__(self, dram_port):
ashift, awidth = get_ashift_awidth(dram_port)
self.reset = CSR()
self.start = CSR()
self.done = CSRStatus()
self.base = CSRStorage(awidth)
self.end = CSRStorage(awidth)
self.length = CSRStorage(awidth)
self.random = CSRStorage(fields=[
CSRField("data", size=1),
CSRField("addr", size=1),
])
self.ticks = CSRStatus(32)
# # #
clock_domain = dram_port.clock_domain
core = _LiteDRAMBISTGenerator(dram_port)
core = ClockDomainsRenamer(clock_domain)(core)
self.submodules += core
if clock_domain != "sys":
control_layout = [
("reset", 1),
("start", 1),
("base", awidth),
("end", awidth),
("length", awidth),
("random_data", 1),
("random_addr", 1),
]
status_layout = [
("done", 1),
("ticks", 32),
]
control_cdc = stream.AsyncFIFO(control_layout)
control_cdc = ClockDomainsRenamer({"write" : "sys", "read": clock_domain})(control_cdc)
status_cdc = stream.AsyncFIFO(status_layout)
status_cdc = ClockDomainsRenamer({"write" : clock_domain, "read": "sys"})(status_cdc)
self.submodules += control_cdc, status_cdc
# Control CDC In
self.comb += [
control_cdc.sink.valid.eq(self.reset.re | self.start.re),
control_cdc.sink.reset.eq(self.reset.re),
control_cdc.sink.start.eq(self.start.re),
control_cdc.sink.base.eq(self.base.storage),
control_cdc.sink.end.eq(self.end.storage),
control_cdc.sink.length.eq(self.length.storage),
control_cdc.sink.random_data.eq(self.random.fields.data),
control_cdc.sink.random_addr.eq(self.random.fields.addr),
]
# Control CDC Out
self.comb += [
control_cdc.source.ready.eq(1),
core.reset.eq(control_cdc.source.valid & control_cdc.source.reset),
core.start.eq(control_cdc.source.valid & control_cdc.source.start),
]
self.sync += [
If(control_cdc.source.valid,
core.base.eq(control_cdc.source.base),
core.end.eq(control_cdc.source.end),
core.length.eq(control_cdc.source.length),
core.random_data.eq(control_cdc.source.random_data),
core.random_addr.eq(control_cdc.source.random_addr),
)
]
# Status CDC In
self.comb += [
status_cdc.sink.valid.eq(1),
status_cdc.sink.done.eq(core.done),
status_cdc.sink.ticks.eq(core.ticks),
]
# Status CDC Out
self.comb += status_cdc.source.ready.eq(1)
self.sync += [
If(status_cdc.source.valid,
self.done.status.eq(status_cdc.source.done),
self.ticks.status.eq(status_cdc.source.ticks),
)
]
else:
self.comb += [
core.reset.eq(self.reset.re),
core.start.eq(self.start.re),
self.done.status.eq(core.done),
core.base.eq(self.base.storage),
core.end.eq(self.end.storage),
core.length.eq(self.length.storage),
core.random_data.eq(self.random.fields.data),
core.random_addr.eq(self.random.fields.addr),
self.ticks.status.eq(core.ticks)
]
# _LiteDRAMBISTChecker -----------------------------------------------------------------------------
@ResetInserter()
class _LiteDRAMBISTChecker(Module, AutoCSR):
def __init__(self, dram_port):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.base = Signal(awidth)
self.end = Signal(awidth)
self.length = Signal(awidth)
self.random_data = Signal()
self.random_addr = Signal()
self.ticks = Signal(32)
self.errors = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address generators ----------------------------------------------------------------
data_gen = Generator(31, n_state=31, taps=[27, 30]) # PRBS31
addr_gen = Generator(31, n_state=31, taps=[27, 30])
self.submodules += data_gen, addr_gen
self.comb += data_gen.random_enable.eq(self.random_data)
self.comb += addr_gen.random_enable.eq(self.random_addr)
# mask random address to the range <base, end), range size must be power of 2
addr_mask = Signal(awidth)
self.comb += addr_mask.eq((self.end - self.base) - 1)
# DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAReader(dram_port)
self.submodules += dma
# Address FSM ------------------------------------------------------------------------------
cmd_counter = Signal(dram_port.address_width, reset_less=True)
cmd_fsm = FSM(reset_state="IDLE")
self.submodules += cmd_fsm
cmd_fsm.act("IDLE",
If(self.start,
NextValue(cmd_counter, 0),
NextState("WAIT")
)
)
cmd_fsm.act("WAIT",
If(self.run_cascade_in,
NextState("RUN")
)
)
cmd_fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.run_cascade_out.eq(1),
addr_gen.ce.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (self.length[ashift:] - 1),
NextState("DONE")
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
)
)
cmd_fsm.act("DONE")
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
dma_sink_addr = dma.sink.address[ashift:]
else:
raise NotImplementedError
self.comb += dma_sink_addr.eq(self.base[ashift:] + (addr_gen.o & addr_mask))
# Data FSM ---------------------------------------------------------------------------------
data_counter = Signal(dram_port.address_width, reset_less=True)
data_fsm = FSM(reset_state="IDLE")
self.submodules += data_fsm
data_fsm.act("IDLE",
If(self.start,
NextValue(data_counter, 0),
NextValue(self.errors, 0),
NextState("RUN")
),
NextValue(self.ticks, 0)
)
data_fsm.act("RUN",
dma.source.ready.eq(1),
If(dma.source.valid,
data_gen.ce.eq(1),
NextValue(data_counter, data_counter + 1),
If(dma.source.data != data_gen.o[:min(len(data_gen.o), dram_port.data_width)],
NextValue(self.errors, self.errors + 1)
),
If(data_counter == (self.length[ashift:] - 1),
NextState("DONE")
)
),
NextValue(self.ticks, self.ticks + 1)
)
data_fsm.act("DONE",
self.done.eq(1)
)
@ResetInserter()
class _LiteDRAMPatternChecker(Module, AutoCSR):
def __init__(self, dram_port, init=[]):
ashift, awidth = get_ashift_awidth(dram_port)
self.start = Signal()
self.done = Signal()
self.ticks = Signal(32)
self.errors = Signal(32)
self.run_cascade_in = Signal(reset=1)
self.run_cascade_out = Signal()
# # #
# Data / Address pattern -------------------------------------------------------------------
addr_init, data_init = zip(*init)
addr_mem = Memory(dram_port.address_width, len(addr_init), init=addr_init)
data_mem = Memory(dram_port.data_width, len(data_init), init=data_init)
addr_port = addr_mem.get_port(async_read=True)
data_port = data_mem.get_port(async_read=True)
self.specials += addr_mem, data_mem, addr_port, data_port
# DMA --------------------------------------------------------------------------------------
dma = LiteDRAMDMAReader(dram_port)
self.submodules += dma
# Address FSM ------------------------------------------------------------------------------
cmd_counter = Signal(dram_port.address_width, reset_less=True)
cmd_fsm = FSM(reset_state="IDLE")
self.submodules += cmd_fsm
cmd_fsm.act("IDLE",
If(self.start,
NextValue(cmd_counter, 0),
If(self.run_cascade_in,
NextState("RUN")
).Else(
NextState("WAIT")
)
)
)
cmd_fsm.act("WAIT",
If(self.run_cascade_in,
NextState("RUN")
),
NextValue(self.ticks, self.ticks + 1)
)
cmd_fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
self.run_cascade_out.eq(1),
NextValue(cmd_counter, cmd_counter + 1),
If(cmd_counter == (len(init) - 1),
NextState("DONE")
).Elif(~self.run_cascade_in,
NextState("WAIT")
)
)
)
cmd_fsm.act("DONE")
if isinstance(dram_port, LiteDRAMNativePort): # addressing in dwords
dma_sink_addr = dma.sink.address
elif isinstance(dram_port, LiteDRAMAXIPort): # addressing in bytes
dma_sink_addr = dma.sink.address[ashift:]
else:
raise NotImplementedError
self.comb += [
addr_port.adr.eq(cmd_counter),
dma_sink_addr.eq(addr_port.dat_r),
]
# Data FSM ---------------------------------------------------------------------------------
data_counter = Signal(dram_port.address_width, reset_less=True)
expected_data = Signal.like(dma.source.data)
self.comb += [
data_port.adr.eq(data_counter),
expected_data.eq(data_port.dat_r),
]
data_fsm = FSM(reset_state="IDLE")
self.submodules += data_fsm
data_fsm.act("IDLE",
If(self.start,
NextValue(data_counter, 0),
NextValue(self.errors, 0),
NextState("RUN")
),
NextValue(self.ticks, 0)
)
data_fsm.act("RUN",
dma.source.ready.eq(1),
If(dma.source.valid,
NextValue(data_counter, data_counter + 1),
If(dma.source.data != expected_data,
NextValue(self.errors, self.errors + 1)
),
If(data_counter == (len(init) - 1),
NextState("DONE")
)
),
NextValue(self.ticks, self.ticks + 1)
)
data_fsm.act("DONE",
self.done.eq(1)
)
# LiteDRAMBISTChecker ------------------------------------------------------------------------------
class LiteDRAMBISTChecker(Module, AutoCSR):
"""DRAM memory pattern checker.
Attributes
----------
reset : in
Reset the module
start : in
Start the checking
done : out
The module has completed checking
base : in
DRAM address to start from.
end : in
Max DRAM address.
length : in
Number of DRAM words to check.
random_data : in
Enable random data (LFSR)
random_addr : in
Enable random address (LFSR). Wrapped to (end - base), so may not be unique.
ticks: out
Duration of the check.
errors : out
Number of DRAM words which don't match.
"""
def __init__(self, dram_port):
ashift, awidth = get_ashift_awidth(dram_port)
self.reset = CSR()
self.start = CSR()
self.done = CSRStatus()
self.base = CSRStorage(awidth)
self.end = CSRStorage(awidth)
self.length = CSRStorage(awidth)
self.random = CSRStorage(fields=[
CSRField("data", size=1),
CSRField("addr", size=1),
])
self.ticks = CSRStatus(32)
self.errors = CSRStatus(32)
# # #
clock_domain = dram_port.clock_domain
core = _LiteDRAMBISTChecker(dram_port)
core = ClockDomainsRenamer(clock_domain)(core)
self.submodules += core
if clock_domain != "sys":
control_layout = [
("reset", 1),
("start", 1),
("base", awidth),
("end", awidth),
("length", awidth),
("random_data", 1),
("random_addr", 1),
]
status_layout = [
("done", 1),
("ticks", 32),
("errors", 32),
]
control_cdc = stream.AsyncFIFO(control_layout)
control_cdc = ClockDomainsRenamer({"write" : "sys", "read": clock_domain})(control_cdc)
status_cdc = stream.AsyncFIFO(status_layout)
status_cdc = ClockDomainsRenamer({"write" : clock_domain, "read": "sys"})(status_cdc)
self.submodules += control_cdc, status_cdc
# Control CDC In
self.comb += [
control_cdc.sink.valid.eq(self.reset.re | self.start.re),
control_cdc.sink.reset.eq(self.reset.re),
control_cdc.sink.start.eq(self.start.re),
control_cdc.sink.base.eq(self.base.storage),
control_cdc.sink.end.eq(self.end.storage),
control_cdc.sink.length.eq(self.length.storage),
control_cdc.sink.random_data.eq(self.random.fields.data),
control_cdc.sink.random_addr.eq(self.random.fields.addr),
]
# Control CDC Out
self.comb += [
control_cdc.source.ready.eq(1),
core.reset.eq(control_cdc.source.valid & control_cdc.source.reset),
core.start.eq(control_cdc.source.valid & control_cdc.source.start),
]
self.sync += [
If(control_cdc.source.valid,
core.base.eq(control_cdc.source.base),
core.end.eq(control_cdc.source.end),
core.length.eq(control_cdc.source.length),
core.random_data.eq(control_cdc.source.random_data),
core.random_addr.eq(control_cdc.source.random_addr),
)
]
# Status CDC In
self.comb += [
status_cdc.sink.valid.eq(1),
status_cdc.sink.done.eq(core.done),
status_cdc.sink.ticks.eq(core.ticks),
status_cdc.sink.errors.eq(core.errors),
]
# Status CDC Out
self.comb += status_cdc.source.ready.eq(1)
self.sync += [
If(status_cdc.source.valid,
self.done.status.eq(status_cdc.source.done),
self.ticks.status.eq(status_cdc.source.ticks),
self.errors.status.eq(status_cdc.source.errors),
)
]
else:
self.comb += [
core.reset.eq(self.reset.re),
core.start.eq(self.start.re),
self.done.status.eq(core.done),
core.base.eq(self.base.storage),
core.end.eq(self.end.storage),
core.length.eq(self.length.storage),
core.random_data.eq(self.random.fields.data),
core.random_addr.eq(self.random.fields.addr),
self.ticks.status.eq(core.ticks),
self.errors.status.eq(core.errors),
]
| [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((4516, 4544), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'LiteDRAMDMAWriter', (['dram_port'], {}), '(dram_port)\n', (4533, 4544), False, 'from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader\n'), ((7161, 7189), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'LiteDRAMDMAWriter', (['dram_port'], {}), '(dram_port)\n', (7178, 7189), False, 'from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader\n'), ((14868, 14896), 'litedram.frontend.dma.LiteDRAMDMAReader', 'LiteDRAMDMAReader', (['dram_port'], {}), '(dram_port)\n', (14885, 14896), False, 'from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader\n'), ((18444, 18472), 'litedram.frontend.dma.LiteDRAMDMAReader', 'LiteDRAMDMAReader', (['dram_port'], {}), '(dram_port)\n', (18461, 18472), False, 'from litedram.frontend.dma import LiteDRAMDMAWriter, LiteDRAMDMAReader\n'), ((10748, 10780), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (['control_layout'], {}), '(control_layout)\n', (10764, 10780), False, 'from litex.soc.interconnect import stream\n'), ((10907, 10938), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (['status_layout'], {}), '(status_layout)\n', (10923, 10938), False, 'from litex.soc.interconnect import stream\n'), ((23292, 23324), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (['control_layout'], {}), '(control_layout)\n', (23308, 23324), False, 'from litex.soc.interconnect import stream\n'), ((23451, 23482), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (['status_layout'], {}), '(status_layout)\n', (23467, 23482), False, 'from litex.soc.interconnect import stream\n'), ((1304, 1346), 'functools.reduce', 'reduce', (['xor', '[curval[tap] for tap in taps]'], {}), '(xor, [curval[tap] for tap in taps])\n', (1310, 1346), False, 'from functools import reduce\n')] |
# This file is Copyright (c) 2017-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016-2017 <NAME> <<EMAIL>>
# License: BSD
import unittest
import random
from collections import namedtuple
from migen import *
from litex.soc.cores import code_8b10b
Control = namedtuple("Control", "value")
code_8b10b_data_rd_m = [
0b1001110100, 0b0111010100, 0b1011010100, 0b1100011011,
0b1101010100, 0b1010011011, 0b0110011011, 0b1110001011,
0b1110010100, 0b1001011011, 0b0101011011, 0b1101001011,
0b0011011011, 0b1011001011, 0b0111001011, 0b0101110100,
0b0110110100, 0b1000111011, 0b0100111011, 0b1100101011,
0b0010111011, 0b1010101011, 0b0110101011, 0b1110100100,
0b1100110100, 0b1001101011, 0b0101101011, 0b1101100100,
0b0011101011, 0b1011100100, 0b0111100100, 0b1010110100,
0b1001111001, 0b0111011001, 0b1011011001, 0b1100011001,
0b1101011001, 0b1010011001, 0b0110011001, 0b1110001001,
0b1110011001, 0b1001011001, 0b0101011001, 0b1101001001,
0b0011011001, 0b1011001001, 0b0111001001, 0b0101111001,
0b0110111001, 0b1000111001, 0b0100111001, 0b1100101001,
0b0010111001, 0b1010101001, 0b0110101001, 0b1110101001,
0b1100111001, 0b1001101001, 0b0101101001, 0b1101101001,
0b0011101001, 0b1011101001, 0b0111101001, 0b1010111001,
0b1001110101, 0b0111010101, 0b1011010101, 0b1100010101,
0b1101010101, 0b1010010101, 0b0110010101, 0b1110000101,
0b1110010101, 0b1001010101, 0b0101010101, 0b1101000101,
0b0011010101, 0b1011000101, 0b0111000101, 0b0101110101,
0b0110110101, 0b1000110101, 0b0100110101, 0b1100100101,
0b0010110101, 0b1010100101, 0b0110100101, 0b1110100101,
0b1100110101, 0b1001100101, 0b0101100101, 0b1101100101,
0b0011100101, 0b1011100101, 0b0111100101, 0b1010110101,
0b1001110011, 0b0111010011, 0b1011010011, 0b1100011100,
0b1101010011, 0b1010011100, 0b0110011100, 0b1110001100,
0b1110010011, 0b1001011100, 0b0101011100, 0b1101001100,
0b0011011100, 0b1011001100, 0b0111001100, 0b0101110011,
0b0110110011, 0b1000111100, 0b0100111100, 0b1100101100,
0b0010111100, 0b1010101100, 0b0110101100, 0b1110100011,
0b1100110011, 0b1001101100, 0b0101101100, 0b1101100011,
0b0011101100, 0b1011100011, 0b0111100011, 0b1010110011,
0b1001110010, 0b0111010010, 0b1011010010, 0b1100011101,
0b1101010010, 0b1010011101, 0b0110011101, 0b1110001101,
0b1110010010, 0b1001011101, 0b0101011101, 0b1101001101,
0b0011011101, 0b1011001101, 0b0111001101, 0b0101110010,
0b0110110010, 0b1000111101, 0b0100111101, 0b1100101101,
0b0010111101, 0b1010101101, 0b0110101101, 0b1110100010,
0b1100110010, 0b1001101101, 0b0101101101, 0b1101100010,
0b0011101101, 0b1011100010, 0b0111100010, 0b1010110010,
0b1001111010, 0b0111011010, 0b1011011010, 0b1100011010,
0b1101011010, 0b1010011010, 0b0110011010, 0b1110001010,
0b1110011010, 0b1001011010, 0b0101011010, 0b1101001010,
0b0011011010, 0b1011001010, 0b0111001010, 0b0101111010,
0b0110111010, 0b1000111010, 0b0100111010, 0b1100101010,
0b0010111010, 0b1010101010, 0b0110101010, 0b1110101010,
0b1100111010, 0b1001101010, 0b0101101010, 0b1101101010,
0b0011101010, 0b1011101010, 0b0111101010, 0b1010111010,
0b1001110110, 0b0111010110, 0b1011010110, 0b1100010110,
0b1101010110, 0b1010010110, 0b0110010110, 0b1110000110,
0b1110010110, 0b1001010110, 0b0101010110, 0b1101000110,
0b0011010110, 0b1011000110, 0b0111000110, 0b0101110110,
0b0110110110, 0b1000110110, 0b0100110110, 0b1100100110,
0b0010110110, 0b1010100110, 0b0110100110, 0b1110100110,
0b1100110110, 0b1001100110, 0b0101100110, 0b1101100110,
0b0011100110, 0b1011100110, 0b0111100110, 0b1010110110,
0b1001110001, 0b0111010001, 0b1011010001, 0b1100011110,
0b1101010001, 0b1010011110, 0b0110011110, 0b1110001110,
0b1110010001, 0b1001011110, 0b0101011110, 0b1101001110,
0b0011011110, 0b1011001110, 0b0111001110, 0b0101110001,
0b0110110001, 0b1000110111, 0b0100110111, 0b1100101110,
0b0010110111, 0b1010101110, 0b0110101110, 0b1110100001,
0b1100110001, 0b1001101110, 0b0101101110, 0b1101100001,
0b0011101110, 0b1011100001, 0b0111100001, 0b1010110001
]
code_8b10b_data_rd_p = [
0b0110001011, 0b1000101011, 0b0100101011, 0b1100010100,
0b0010101011, 0b1010010100, 0b0110010100, 0b0001110100,
0b0001101011, 0b1001010100, 0b0101010100, 0b1101000100,
0b0011010100, 0b1011000100, 0b0111000100, 0b1010001011,
0b1001001011, 0b1000110100, 0b0100110100, 0b1100100100,
0b0010110100, 0b1010100100, 0b0110100100, 0b0001011011,
0b0011001011, 0b1001100100, 0b0101100100, 0b0010011011,
0b0011100100, 0b0100011011, 0b1000011011, 0b0101001011,
0b0110001001, 0b1000101001, 0b0100101001, 0b1100011001,
0b0010101001, 0b1010011001, 0b0110011001, 0b0001111001,
0b0001101001, 0b1001011001, 0b0101011001, 0b1101001001,
0b0011011001, 0b1011001001, 0b0111001001, 0b1010001001,
0b1001001001, 0b1000111001, 0b0100111001, 0b1100101001,
0b0010111001, 0b1010101001, 0b0110101001, 0b0001011001,
0b0011001001, 0b1001101001, 0b0101101001, 0b0010011001,
0b0011101001, 0b0100011001, 0b1000011001, 0b0101001001,
0b0110000101, 0b1000100101, 0b0100100101, 0b1100010101,
0b0010100101, 0b1010010101, 0b0110010101, 0b0001110101,
0b0001100101, 0b1001010101, 0b0101010101, 0b1101000101,
0b0011010101, 0b1011000101, 0b0111000101, 0b1010000101,
0b1001000101, 0b1000110101, 0b0100110101, 0b1100100101,
0b0010110101, 0b1010100101, 0b0110100101, 0b0001010101,
0b0011000101, 0b1001100101, 0b0101100101, 0b0010010101,
0b0011100101, 0b0100010101, 0b1000010101, 0b0101000101,
0b0110001100, 0b1000101100, 0b0100101100, 0b1100010011,
0b0010101100, 0b1010010011, 0b0110010011, 0b0001110011,
0b0001101100, 0b1001010011, 0b0101010011, 0b1101000011,
0b0011010011, 0b1011000011, 0b0111000011, 0b1010001100,
0b1001001100, 0b1000110011, 0b0100110011, 0b1100100011,
0b0010110011, 0b1010100011, 0b0110100011, 0b0001011100,
0b0011001100, 0b1001100011, 0b0101100011, 0b0010011100,
0b0011100011, 0b0100011100, 0b1000011100, 0b0101001100,
0b0110001101, 0b1000101101, 0b0100101101, 0b1100010010,
0b0010101101, 0b1010010010, 0b0110010010, 0b0001110010,
0b0001101101, 0b1001010010, 0b0101010010, 0b1101000010,
0b0011010010, 0b1011000010, 0b0111000010, 0b1010001101,
0b1001001101, 0b1000110010, 0b0100110010, 0b1100100010,
0b0010110010, 0b1010100010, 0b0110100010, 0b0001011101,
0b0011001101, 0b1001100010, 0b0101100010, 0b0010011101,
0b0011100010, 0b0100011101, 0b1000011101, 0b0101001101,
0b0110001010, 0b1000101010, 0b0100101010, 0b1100011010,
0b0010101010, 0b1010011010, 0b0110011010, 0b0001111010,
0b0001101010, 0b1001011010, 0b0101011010, 0b1101001010,
0b0011011010, 0b1011001010, 0b0111001010, 0b1010001010,
0b1001001010, 0b1000111010, 0b0100111010, 0b1100101010,
0b0010111010, 0b1010101010, 0b0110101010, 0b0001011010,
0b0011001010, 0b1001101010, 0b0101101010, 0b0010011010,
0b0011101010, 0b0100011010, 0b1000011010, 0b0101001010,
0b0110000110, 0b1000100110, 0b0100100110, 0b1100010110,
0b0010100110, 0b1010010110, 0b0110010110, 0b0001110110,
0b0001100110, 0b1001010110, 0b0101010110, 0b1101000110,
0b0011010110, 0b1011000110, 0b0111000110, 0b1010000110,
0b1001000110, 0b1000110110, 0b0100110110, 0b1100100110,
0b0010110110, 0b1010100110, 0b0110100110, 0b0001010110,
0b0011000110, 0b1001100110, 0b0101100110, 0b0010010110,
0b0011100110, 0b0100010110, 0b1000010110, 0b0101000110,
0b0110001110, 0b1000101110, 0b0100101110, 0b1100010001,
0b0010101110, 0b1010010001, 0b0110010001, 0b0001110001,
0b0001101110, 0b1001010001, 0b0101010001, 0b1101001000,
0b0011010001, 0b1011001000, 0b0111001000, 0b1010001110,
0b1001001110, 0b1000110001, 0b0100110001, 0b1100100001,
0b0010110001, 0b1010100001, 0b0110100001, 0b0001011110,
0b0011001110, 0b1001100001, 0b0101100001, 0b0010011110,
0b0011100001, 0b0100011110, 0b1000011110, 0b0101001110
]
def inverse_data_rd(table):
inverse_table = {}
for i in range(256):
inverse_table[table[i]] = i
return inverse_table
code_8b10b_data_rd_m_inverse = inverse_data_rd(code_8b10b_data_rd_m)
code_8b10b_data_rd_p_inverse = inverse_data_rd(code_8b10b_data_rd_p)
code_8b10b_control_rd_m = {
0b00011100: 0b0011110100, #K28.0
0b00111100: 0b0011111001, #K28.1
0b01011100: 0b0011110101, #K28.2
0b01111100: 0b0011110011, #K28.3
0b10011100: 0b0011110010, #K28.4
0b10111100: 0b0011111010, #K28.5
0b11011100: 0b0011110110, #K28.6
0b11111100: 0b0011111000, #K28.7
0b11110111: 0b1110101000, #K23.7
0b11111011: 0b1101101000, #K27.7
0b11111101: 0b1011101000, #K29.7
0b11111110: 0b0111101000 #K30.7
}
code_8b10b_control_rd_p = {
0b00011100: 0b1100001011, #K28.0
0b00111100: 0b1100000110, #K28.1
0b01011100: 0b1100001010, #K28.2
0b01111100: 0b1100001100, #K28.3
0b10011100: 0b1100001101, #K28.4
0b10111100: 0b1100000101, #K28.5
0b11011100: 0b1100001001, #K28.6
0b11111100: 0b1100000111, #K28.7
0b11110111: 0b0001010111, #K23.7
0b11111011: 0b0010010111, #K27.7
0b11111101: 0b0100010111, #K29.7
0b11111110: 0b1000010111 #K30.7
}
def inverse_control_rd(table):
inverse_table = {}
for k, v in table.items():
inverse_table[v] = k
return inverse_table
code_8b10b_control_rd_m_inverse = inverse_control_rd(code_8b10b_control_rd_m)
code_8b10b_control_rd_p_inverse = inverse_control_rd(code_8b10b_control_rd_p)
def encode_model(datas):
encoded_datas = []
table = "m"
change_table = False
for octet in datas:
if change_table:
table = "p" if table == "m" else "m"
if isinstance(octet, Control):
if table == "p":
encoded_octet = code_8b10b_control_rd_p[octet.value]
else:
encoded_octet = code_8b10b_control_rd_m[octet.value]
else:
if table == "p":
encoded_octet = code_8b10b_data_rd_p[octet]
else:
encoded_octet = code_8b10b_data_rd_m[octet]
change_table = (code_8b10b.disparity(encoded_octet, 10) != 0)
encoded_datas.append(encoded_octet)
return encoded_datas
def decode_model(datas):
decoded_datas = []
for encoded_octet in datas:
try:
octet = code_8b10b_data_rd_m_inverse[encoded_octet]
except:
try:
octet = code_8b10b_data_rd_p_inverse[encoded_octet]
except:
try:
octet = Control(code_8b10b_control_rd_p_inverse[encoded_octet])
except:
octet = Control(code_8b10b_control_rd_m_inverse[encoded_octet])
decoded_datas.append(octet)
return decoded_datas
def encode_sequence(seq):
output = []
dut = code_8b10b.Encoder()
def pump():
for w in seq:
if isinstance(w, Control):
yield dut.k[0].eq(1)
yield dut.d[0].eq(w.value)
else:
yield dut.k[0].eq(0)
yield dut.d[0].eq(w)
yield
output.append((yield dut.output[0]))
for _ in range(2):
yield
output.append((yield dut.output[0]))
run_simulation(dut, pump())
return output[2:]
def decode_sequence(seq):
output = []
dut = code_8b10b.Decoder()
def pump():
for w in seq:
yield dut.input.eq(w)
yield
if (yield dut.k):
output.append(Control((yield dut.d)))
else:
output.append((yield dut.d))
yield
if (yield dut.k):
output.append(Control((yield dut.d)))
else:
output.append((yield dut.d))
run_simulation(dut, pump())
return output[1:]
class TestCode8B10B(unittest.TestCase):
@classmethod
def setUpClass(cls):
prng = random.Random(42)
cls.input_sequence = []
for i in 23, 27, 29, 30:
cls.input_sequence += [Control((7 << 5) | i)]*2
for i in range(8):
cls.input_sequence += [Control((i << 5) | 28)]*2
cls.input_sequence += [prng.randrange(256) for _ in range(10000)]
cls.output_sequence = encode_sequence(cls.input_sequence)
def test_coding(self):
reference_sequence = encode_model(self.input_sequence)
self.assertEqual(reference_sequence, self.output_sequence)
def test_comma(self):
control_chars = [
0b1110101000,
0b1101101000,
0b1011101000,
0b0111101000,
0b0011110100,
0b0011111001,
0b0011110101,
0b0011110011,
0b0011110010,
0b0011111010,
0b0011110110,
0b0011111000,
]
for i, c in enumerate(control_chars):
ok = {c, ~c & 0b1111111111}
with self.subTest(i=i):
self.assertIn(self.output_sequence[2*i], ok)
self.assertIn(self.output_sequence[2*i+1], ok)
def test_running_disparity(self):
rd = -1
for w in self.output_sequence:
rd += code_8b10b.disparity(w, 10)
self.assertIn(rd, {-1, 1})
def test_no_spurious_commas(self):
for w1, w2 in zip(self.output_sequence[16+8:], self.output_sequence[16+8+1:]):
for shift in range(10):
cw = (w1 << shift) | (w2 >> (10-shift))
self.assertNotIn(cw, {0b0011111001, 0b1100000110, # K28.1
0b0011111010, 0b1100000101, # K28.5
0b0011111000, 0b1100000111}) # K28.7
def test_roundtrip(self):
self.assertEqual(self.input_sequence,
decode_sequence(self.output_sequence))
| [
"litex.soc.cores.code_8b10b.Encoder",
"litex.soc.cores.code_8b10b.disparity",
"litex.soc.cores.code_8b10b.Decoder"
] | [((266, 296), 'collections.namedtuple', 'namedtuple', (['"""Control"""', '"""value"""'], {}), "('Control', 'value')\n", (276, 296), False, 'from collections import namedtuple\n'), ((10898, 10918), 'litex.soc.cores.code_8b10b.Encoder', 'code_8b10b.Encoder', ([], {}), '()\n', (10916, 10918), False, 'from litex.soc.cores import code_8b10b\n'), ((11439, 11459), 'litex.soc.cores.code_8b10b.Decoder', 'code_8b10b.Decoder', ([], {}), '()\n', (11457, 11459), False, 'from litex.soc.cores import code_8b10b\n'), ((11995, 12012), 'random.Random', 'random.Random', (['(42)'], {}), '(42)\n', (12008, 12012), False, 'import random\n'), ((10176, 10215), 'litex.soc.cores.code_8b10b.disparity', 'code_8b10b.disparity', (['encoded_octet', '(10)'], {}), '(encoded_octet, 10)\n', (10196, 10215), False, 'from litex.soc.cores import code_8b10b\n'), ((13258, 13285), 'litex.soc.cores.code_8b10b.disparity', 'code_8b10b.disparity', (['w', '(10)'], {}), '(w, 10)\n', (13278, 13285), False, 'from litex.soc.cores import code_8b10b\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk50", 0, Pins("N11"), IOStandard("LVCMOS33")),
# The core board does not have a USB serial on it,
# so you will have to attach an USB to serial adapter
# on these pins
("gpio_serial", 0,
Subsignal("tx", Pins("J2:7")),
Subsignal("rx", Pins("J2:8")),
IOStandard("LVCMOS33")
),
# SPIFlash
# MT25QL128
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L12")),
Subsignal("clk", Pins("E8")),
Subsignal("dq", Pins("J13", "J14", "K15", "K16")),
IOStandard("LVCMOS33")
),
# DDR3 SDRAM
# MT41J128M16JT-125K
("ddram", 0,
Subsignal("a", Pins("B14 C8 A14 C14 C9 B10 D9 A12 D8 A13 B12 A9 A8 B11"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("C16 A15 B15"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("B16"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("C11"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("C12"), IOStandard("SSTL135")),
# cs_n is hardwired on the board
#Subsignal("cs_n", Pins("-"), IOStandard("SSTL135")),
Subsignal("dm", Pins("F12 H11"), IOStandard("SSTL135")),
Subsignal("dq", Pins(
"F15 F13 E16 D11 E12 E13 D16 E11",
"G12 J16 G16 J15 H14 H12 H16 H13"),
IOStandard("SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("D14 G14"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_n", Pins("D15 F14"),
IOStandard("DIFF_SSTL135"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("clk_p", Pins("B9"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("A10"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("D13"), IOStandard("SSTL135")),
Subsignal("odt", Pins("C13"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("E15"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
]
# The connectors are named after the daughterboard, not the core board
# because on the different core boards the names vary, but on the
# daughterboard they stay the same, which we need to connect the
# daughterboard peripherals to the core board.
# On this board J2 is U7 and J3 is U8
_connectors = [
("J2", {
# odd row even row
7: "M12", 8: "N13",
9: "N14", 10: "N16",
11: "P15", 12: "P16",
13: "R15", 14: "R16",
15: "T14", 16: "T15",
17: "P13", 18: "P14",
19: "T13", 20: "R13",
21: "T12", 22: "R12",
23: "L13", 24: "N12",
25: "K12", 26: "K13",
27: "P10", 28: "P11",
29: "N9", 30: "P9",
31: "T10", 32: "R11",
33: "T9", 34: "R10",
35: "T8", 36: "R8",
37: "T7", 38: "R7",
39: "T5", 40: "R6",
41: "P6", 42: "R5",
43: "N6", 44: "M6",
45: "L5", 46: "P5",
47: "T4", 48: "T3",
49: "R3", 50: "T2",
51: "R2", 52: "R1",
53: "M5", 54: "N4",
55: "P4", 56: "P3",
57: "N1", 58: "P1",
59: "M2", 60: "M1",
}),
("J3", {
# odd row even row
7: "B7", 8: "A7",
9: "B6", 10: "B5",
11: "E6", 12: "K5",
13: "J5", 14: "J4",
15: "G5", 16: "G4",
17: "C7", 18: "C6",
19: "D6", 20: "D5",
21: "A5", 22: "A4",
23: "B4", 24: "A3",
25: "D4", 26: "C4",
27: "C3", 28: "C2",
29: "B2", 30: "A2",
31: "C1", 32: "B1",
33: "E2", 34: "D1",
35: "E3", 36: "D3",
37: "F5", 38: "E5",
39: "F2", 40: "E1",
41: "F4", 42: "F3",
43: "G2", 44: "G1",
45: "H2", 46: "H1",
47: "K1", 48: "J1",
49: "L3", 50: "L2",
51: "H5", 52: "H4",
53: "J3", 54: "H3",
55: "K3", 56: "K2",
57: "L4", 58: "M4",
59: "N3", 60: "N2",
})
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
# these resources conflict with daughterboard resources
# so they are only used if the daughterboard is not present
core_resources = [
("user_led", 0, Pins("E6"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("K5"), IOStandard("LVCMOS33")),
]
def __init__(self, toolchain="vivado", with_daughterboard=False):
device = "xc7a35tftg256-1"
io = _io
connectors = _connectors
if with_daughterboard:
from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33"))
io += daughterboard.io
connectors += daughterboard.connectors
else:
io += self.core_resources
XilinxPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
self.toolchain.symbiflow_device = device
def create_programmer(self):
bscan_spi = "bscan_spi_xc7a35t.bit"
return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
from litex.build.xilinx import symbiflow
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) | [
"litex.build.generic_platform.Misc",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.generic_platform.Pins",
"litex.build.generic_platform.IOStandard"
] | [((425, 436), 'litex.build.generic_platform.Pins', 'Pins', (['"""N11"""'], {}), "('N11')\n", (429, 436), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((438, 460), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (448, 460), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((706, 728), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (716, 728), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((986, 1008), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (996, 1008), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((2432, 2449), 'litex.build.generic_platform.Misc', 'Misc', (['"""SLEW=FAST"""'], {}), "('SLEW=FAST')\n", (2436, 2449), False, 'from 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#
# This file is part of LiteX.
#
# Copyright (c) 2020-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import math
from migen import *
from migen.genlib.misc import WaitTimer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
# Led Chaser ---------------------------------------------------------------------------------------
_CHASER_MODE = 0
_CONTROL_MODE = 1
class LedChaser(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq, period=1e0):
self.pads = pads
self._out = CSRStorage(len(pads), description="Led Output(s) Control.")
# # #
n = len(pads)
chaser = Signal(n)
mode = Signal(reset=_CHASER_MODE)
timer = WaitTimer(int(period*sys_clk_freq/(2*n)))
self.submodules += timer
self.comb += timer.wait.eq(~timer.done)
self.sync += If(timer.done, chaser.eq(Cat(~chaser[-1], chaser)))
self.sync += If(self._out.re, mode.eq(_CONTROL_MODE))
self.comb += [
If(mode == _CONTROL_MODE,
pads.eq(self._out.storage)
).Else(
pads.eq(chaser)
)
]
def add_pwm(self, default_width=512, default_period=1024, with_csr=True):
from litex.soc.cores.pwm import PWM
self.submodules.pwm = PWM(
with_csr = with_csr,
default_enable = 1,
default_width = default_width,
default_period = default_period
)
# Use PWM as Output Enable for pads.
self.comb += If(~self.pwm.pwm, self.pads.eq(0))
# WS2812/NeoPixel ----------------------------------------------------------------------------------
class WS2812(Module):
"""WS2812/NeoPixel Led Driver.
Description
-----------
┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐ ┌──────┐
│DI DO│ │DI DO│ │DI DO│ │DI DO│ │DI DO│ Next leds
FPGA ───► ├───► ├───► ├───► ├───► ├───► or
│ LED0 │ │ LED1 │ │ LED2 │ │ LED3 │ │ LED4 │ end of chain.
└──────┘ └──────┘ └──────┘ └──────┘ └──────┘
24-bit 24-bit 24-bit 24-bit 24-bit
WS2812/NeoPixel Leds are smart RGB Leds controlled over a simple one wire protocol:
- Each Led will "digest" a 24-bit control word: (MSB) G-R-B (LSB).
- Leds can be chained through DIN->DOUT connection.
Each control sequence is separated by a reset code: Line low for > 50us.
Ones are transmitted as:
┌─────┐
│ T0H │ │ T0H = 400ns +-150ns
│ │ T0L │ T0L = 800ns +-150ns
└───────────┘
Zeros are transmitted as:
┌──────────┐
│ T1H │ │ T1H = 850ns +-150ns
│ │ T1L │ T1L = 450ns +-150ns
└──────┘
Integration
-----------
The core handles the WS2812 protocol and exposes the Led chain as an MMAPed peripheral:
32-bit
00_GG_RR_BB
┌───────────┐
Base + 0 │ LED0 │
├───────────┤
Base + 4 │ LED1 │
├───────────┤
Base + 8 │ LED2 │
└───────────┘
... ...
It can be simply integrated in a LiteX SoC with:
self.submodules.ws2812 = WS2812(platform.request("x"), nleds=32, sys_clk_freq=sys_clk_freq)
self.bus.add_slave(name="ws2812", slave=self.ws2812.bus, region=SoCRegion(
origin = 0x2000_0000,
size = 32*4,
))
Each Led can then be directly controlled from the Bus of the SoC.
Parameters
----------
pad : Signal, in
FPGA DOut.
nleds : int, in
Number of Leds in the chain.
sys_clk_freq: int, in
System Clk Frequency.
"""
def __init__(self, pad, nleds, sys_clk_freq, bus_mastering=False, bus_base=None):
if bus_mastering:
self.bus = bus = wishbone.Interface(data_width=32)
else:
# Memory.
mem = Memory(32, nleds)
port = mem.get_port()
self.specials += mem, port
# Wishone Memory.
self.submodules.wb_mem = wishbone.SRAM(
mem_or_size = mem,
read_only = False,
bus = wishbone.Interface(data_width=32)
)
self.bus = self.wb_mem.bus
# Internal Signals.
led_data = Signal(24)
bit_count = Signal(8)
led_count = Signal(int(math.log2(nleds)))
# Timings.
trst = 75e-6
t0h = 0.40e-6
t0l = 0.85e-6
t1h = 0.80e-6
t1l = 0.45e-6
# Timers.
t0h_timer = WaitTimer(int(t0h*sys_clk_freq))
t0l_timer = WaitTimer(int(t0l*sys_clk_freq))
self.submodules += t0h_timer, t0l_timer
t1h_timer = WaitTimer(int(t1h*sys_clk_freq))
t1l_timer = WaitTimer(int(t1l*sys_clk_freq))
self.submodules += t1h_timer, t1l_timer
trst_timer = WaitTimer(int(trst*sys_clk_freq))
self.submodules += trst_timer
# FSM
self.submodules.fsm = fsm = FSM(reset_state="RST")
fsm.act("RST",
trst_timer.wait.eq(1),
If(trst_timer.done,
NextValue(led_count, 0),
NextState("LED-READ")
)
)
if bus_mastering:
fsm.act("LED-READ",
bus.stb.eq(1),
bus.cyc.eq(1),
bus.we.eq(0),
bus.sel.eq(2**(bus.data_width//8)-1),
bus.adr.eq(bus_base[2:] + led_count),
If(bus.ack,
NextValue(bit_count, 24-1),
NextValue(led_data, bus.dat_r),
NextState("BIT-TEST")
)
)
else:
self.comb += port.adr.eq(led_count)
fsm.act("LED-READ",
NextValue(bit_count, 24-1),
NextValue(led_data, port.dat_r),
NextState("BIT-TEST")
)
fsm.act("BIT-TEST",
If(led_data[-1] == 0,
NextState("ZERO-SEND"),
),
If(led_data[-1] == 1,
NextState("ONE-SEND"),
),
)
fsm.act("ZERO-SEND",
t0h_timer.wait.eq(1),
t0l_timer.wait.eq(t0h_timer.done),
pad.eq(~t0h_timer.done),
If(t0l_timer.done,
NextState("BIT-SHIFT")
)
)
fsm.act("ONE-SEND",
t1h_timer.wait.eq(1),
t1l_timer.wait.eq(t1h_timer.done),
pad.eq(~t1h_timer.done),
If(t1l_timer.done,
NextState("BIT-SHIFT")
)
)
fsm.act("BIT-SHIFT",
NextValue(led_data, Cat(Signal(), led_data)),
NextValue(bit_count, bit_count - 1),
If(bit_count == 0,
NextState("LED-SHIFT")
).Else(
NextState("BIT-TEST")
)
)
fsm.act("LED-SHIFT",
NextValue(led_count, led_count + 1),
If(led_count == (nleds-1),
NextState("RST")
).Else(
NextState("LED-READ")
)
)
| [
"litex.soc.cores.pwm.PWM",
"litex.soc.interconnect.wishbone.Interface"
] | [((1334, 1438), 'litex.soc.cores.pwm.PWM', 'PWM', ([], {'with_csr': 'with_csr', 'default_enable': '(1)', 'default_width': 'default_width', 'default_period': 'default_period'}), '(with_csr=with_csr, default_enable=1, default_width=default_width,\n default_period=default_period)\n', (1337, 1438), False, 'from litex.soc.cores.pwm import PWM\n'), ((4392, 4425), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (4410, 4425), False, 'from litex.soc.interconnect import wishbone\n'), ((4965, 4981), 'math.log2', 'math.log2', (['nleds'], {}), '(nleds)\n', (4974, 4981), False, 'import math\n'), ((4756, 4789), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (4774, 4789), False, 'from litex.soc.interconnect import wishbone\n')] |
# This file is Copyright (c) 2017 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import LatticeProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk100", 0, Pins("P3"), IOStandard("LVDS")),
("rst_n", 0, Pins("T1"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("E16"), IOStandard("LVCMOS25")),
("user_led", 1, Pins("D17"), IOStandard("LVCMOS25")),
("user_led", 2, Pins("D18"), IOStandard("LVCMOS25")),
("user_led", 3, Pins("E18"), IOStandard("LVCMOS25")),
("user_led", 4, Pins("F17"), IOStandard("LVCMOS25")),
("user_led", 5, Pins("F18"), IOStandard("LVCMOS25")),
("user_led", 6, Pins("E17"), IOStandard("LVCMOS25")),
("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
("user_dip_btn", 0, Pins("H2"), IOStandard("LVCMOS15")),
("user_dip_btn", 1, Pins("K3"), IOStandard("LVCMOS15")),
("user_dip_btn", 2, Pins("G3"), IOStandard("LVCMOS15")),
("user_dip_btn", 3, Pins("F2"), IOStandard("LVCMOS15")),
("user_dip_btn", 4, Pins("J18"), IOStandard("LVCMOS25")),
("user_dip_btn", 5, Pins("K18"), IOStandard("LVCMOS25")),
("user_dip_btn", 6, Pins("K19"), IOStandard("LVCMOS25")),
("user_dip_btn", 7, Pins("K20"), IOStandard("LVCMOS25")),
("serial", 0,
Subsignal("rx", Pins("C11"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("A11"), IOStandard("LVCMOS33")),
),
("spiflash", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2")),
Subsignal("mosi", Pins("W2")),
Subsignal("miso", Pins("V2")),
Subsignal("wp", Pins("Y2")),
Subsignal("hold", Pins("W1")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2")),
Subsignal("dq", Pins("W2 V2 Y2 W1")),
IOStandard("LVCMOS33")
),
("ddram", 0,
Subsignal("a", Pins(
"P2 C4 E5 F5 B3 F4 B5 E4",
"C5 E3 D5 B4 C3"),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("P5 N3 M3"), IOStandard("SSTL135_I")),
Subsignal("ras_n", Pins("P1"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("L1"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("M1"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("K1"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("J4 H5"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"L5 F1 K4 G1 L4 H1 G2 J3",
"D1 C1 E2 C2 F3 A2 E1 B1"),
IOStandard("SSTL135_I"),
Misc("TERMINATION=75")),
Subsignal("dqs_p", Pins("K2 H4"), IOStandard("SSTL135D_I"), Misc("TERMINATION=OFF"), Misc("DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("M4"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("N2"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("L2"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("N4"), IOStandard("SSTL135_I")),
Misc("SLEWRATE=FAST"),
),
("eth_clocks", 0,
Subsignal("tx", Pins("P19")),
Subsignal("rx", Pins("L20")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("U17")),
Subsignal("mdio", Pins("U18")),
Subsignal("mdc", Pins("T18")),
Subsignal("rx_ctl", Pins("U19")),
Subsignal("rx_data", Pins("T20 U20 T19 R18")),
Subsignal("tx_ctl", Pins("R20")),
Subsignal("tx_data", Pins("N19 N20 P18 P20")),
IOStandard("LVCMOS25")
),
("eth_clocks", 1,
Subsignal("tx", Pins("C20")),
Subsignal("rx", Pins("J19")),
IOStandard("LVCMOS25")
),
("eth", 1,
Subsignal("rst_n", Pins("F20")),
Subsignal("mdio", Pins("H20")),
Subsignal("mdc", Pins("G19")),
Subsignal("rx_ctl", Pins("F19")),
Subsignal("rx_data", Pins("G18 G16 H18 H17")),
Subsignal("tx_ctl", Pins("E19")),
Subsignal("tx_data", Pins("J17 J16 D19 D20")),
IOStandard("LVCMOS25")
),
("ext_clk", 0,
Subsignal("p", Pins("A4")),
Subsignal("n", Pins("A5")),
IOStandard("LVDS")
),
("pcie_x1", 0,
Subsignal("clk_p", Pins("Y11")),
Subsignal("clk_n", Pins("Y12")),
Subsignal("rx_p", Pins("Y5")),
Subsignal("rx_n", Pins("Y6")),
Subsignal("tx_p", Pins("W4")),
Subsignal("tx_n", Pins("W5")),
Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")),
),
]
_ecp5_soc_hat_io = [
("sdram_clock", 0, Pins("E14"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"C6 E15 A16 B16 D15 C15 B15 E12",
"D12 B10 C7 A9 C10")),
Subsignal("dq", Pins(
"B19 B12 B9 E6 D6 E7 D7 B11",
"C14 A14 E13 D13 C13 B13 A13 A12")),
Subsignal("we_n", Pins("E9")),
Subsignal("ras_n", Pins("B8")),
Subsignal("cas_n", Pins("D9")),
Subsignal("cs_n", Pins("C8")),
Subsignal("cke", Pins("D11")),
Subsignal("ba", Pins("D8 E8")),
Subsignal("dm", Pins("B6 D14")),
IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("X3",
"None", # (no pin 0)
"None", # 1 GND
"None", # 2 N/C
"None", # 3 +2V5
"B19", # 4 EXPCON_IO29
"B12", # 5 EXPCON_IO30
"B9", # 6 EXPCON_IO31
"E6", # 7 EXPCON_IO32
"D6", # 8 EXPCON_IO33
"E7", # 9 EXPCON_IO34
"D7", # 10 EXPCON_IO35
"B11", # 11 EXPCON_IO36
"B6", # 12 EXPCON_IO37
"E9", # 13 EXPCON_IO38
"D9", # 14 EXPCON_IO39
"B8", # 15 EXPCON_IO40
"C8", # 16 EXPCON_IO41
"D8", # 17 EXPCON_IO42
"E8", # 18 EXPCON_IO43
"C7", # 19 EXPCON_IO44
"C6", # 20 EXPCON_IO45
"None", # 21 +5V
"None", # 22 GND
"None", # 23 +2V5
"None", # 24 GND
"None", # 25 +3V3
"None", # 26 GND
"None", # 27 +3V3
"None", # 28 GND
"None", # 29 EXPCON_OSC
"None", # 30 GND
"None", # 31 EXPCON_CLKIN
"None", # 32 GND
"None", # 33 EXPCON_CLKOUT
"None", # 34 GND
"None", # 35 +3V3
"None", # 36 GND
"None", # 37 +3V3
"None", # 38 GND
"None", # 39 +3V3
"None", # 40 GND
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
def do_finalize(self, fragment):
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
except ConstraintError:
pass
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
except ConstraintError:
pass
def create_programmer(self, with_ispclock=True):
_xcf_ispclock = """
<Device>
<SelectedProg value="FALSE"/>
<Pos>2</Pos>
<Vendor>Lattice</Vendor>
<Family>ispCLOCK</Family>
<Name>ispPAC-CLK5406D</Name>
<IDCode>0x00191043</IDCode>
<Operation>Erase,Program,Verify</Operation>
<Bypass>
<InstrLen>8</InstrLen>
<InstrVal>11111111</InstrVal>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
</Device>
"""
_xcf_template = """
<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
<ispXCF version="3.4.1">
<Comment></Comment>
<Chain>
<Comm>JTAG</Comm>
<Device>
<SelectedProg value="TRUE"/>
<Pos>1</Pos>
<Vendor>Lattice</Vendor>
<Family>ECP5UM5G</Family>
<Name>LFE5UM5G-45F</Name>
<IDCode>0x81112043</IDCode>
<File>{{bitstream_file}}</File>
<Operation>Fast Program</Operation>
</Device>{ispclock}
</Chain>
<ProjectOptions>
<Program>SEQUENTIAL</Program>
<Process>ENTIRED CHAIN</Process>
<OperationOverride>No Override</OperationOverride>
<StartTAP>TLR</StartTAP>
<EndTAP>TLR</EndTAP>
<VerifyUsercode value="FALSE"/>
</ProjectOptions>
<CableOptions>
<CableName>USB2</CableName>
<PortAdd>FTUSB-0</PortAdd>
<USBID>LATTICE ECP5_5G VERSA BOARD A Location 0000 Serial Lattice ECP5_5G VERSA Board A</USBID>
</CableOptions>
</ispXCF>
""".format(ispclock=_xcf_ispclock if with_ispclock else "")
return LatticeProgrammer(_xcf_template)
| [
"litex.build.lattice.programmer.LatticeProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((7005, 7092), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5UM5G-45F-8BG381C"""', '_io', '_connectors'], {}), "(self, 'LFE5UM5G-45F-8BG381C', _io, _connectors, **\n kwargs)\n", (7029, 7092), False, 'from litex.build.lattice import LatticePlatform\n'), ((9198, 9230), 'litex.build.lattice.programmer.LatticeProgrammer', 'LatticeProgrammer', (['_xcf_template'], {}), '(_xcf_template)\n', (9215, 9230), False, 'from litex.build.lattice.programmer import LatticeProgrammer\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use ----------------------------------------------------------------------------------------
#
# 1) SoC with regular UART and optional Ethernet connected to the CPU:
# Connect a USB/UART to J19: TX of the FPGA is DATA_LED-, RX of the FPGA is KEY+.
# ./colorlight_5a_75x.py --revision=7.0 (or 6.1) --build (--with-ethernet to add Ethernet capability)
# Note: on revision 6.1, add --uart-baudrate=9600 to lower the baudrate.
# ./colorlight_5a_75x.py --load
# You should see the LiteX BIOS and be able to interact with it.
#
# 2) SoC with UART in crossover mode over Etherbone:
# ./colorlight_5a_75x.py --revision=7.0 (or 6.1) --uart-name=crossover --with-etherbone --csr-csv=csr.csv --build
# ./colorlight_5a_75x.py --load
# ping 192.168.1.50
# Get and install wishbone tool from: https://github.com/litex-hub/wishbone-utils/releases
# wishbone-tool --ethernet-host 192.168.1.50 --server terminal --csr-csv csr.csv
# You should see the LiteX BIOS and be able to interact with it.
#
# 3) SoC with USB-ACM UART (on V7.0):
# - Replace U23 with a SN74CBT3245APWR or remove U23 and place jumper wires to make the ports bi-directional.
# - Place a 15K resistor between J4 pin 2 and J4 pin 4.
# - Place a 15K resistor between J4 pin 3 and J4 pin 4.
# - Place a 1.5K resistor between J4 pin 1 and J4 pin 3.
# - Connect USB DP (Green) to J4 pin 3, USB DN (White) to J4 pin 2.
# ./colorlight_5a_75x.py --revision=7.0 --uart-name=usb_acm --build
# ./colorlight_5a_75x.py --load
# You should see the LiteX BIOS and be able to interact with it.
#
# Note that you can also use a 5A-75E board:
# ./colorlight_5a_75x.py --board=5a-75e --revision=7.1 (or 6.0) --build
#
# Disclaimer: SoC 2) is still a Proof of Concept with large timings violations on the IP/UDP and
# Etherbone stack that need to be optimized. It was initially just used to validate the reversed
# pinout but happens to work on hardware...
import os
import argparse
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.io import DDROutput
from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import M12L16161A, M12L64322A
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_rst=True, sdram_rate="1:1"):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
if sdram_rate == "1:2":
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True)
else:
self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True)
# # #
# Clk / Rst
if not use_internal_osc:
clk = platform.request("clk25")
clk_freq = 25e6
else:
clk = Signal()
div = 5
self.specials += Instance("OSCG",
p_DIV = div,
o_OSC = clk)
clk_freq = 310e6/div
rst_n = 1 if not with_rst else platform.request("user_btn_n", 0)
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk, clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if sdram_rate == "1:2":
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
else:
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
# USB PLL
if with_usb_pll:
self.submodules.usb_pll = usb_pll = ECP5PLL()
self.comb += usb_pll.reset.eq(~rst_n | self.rst)
usb_pll.register_clkin(clk, clk_freq)
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
# SDRAM clock
sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False,
with_etherbone=False, eth_ip="192.168.1.50", eth_phy=0, with_led_chaser=True,
use_internal_osc=False, sdram_rate="1:1", **kwargs):
board = board.lower()
assert board in ["5a-75b", "5a-75e"]
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
if board == "5a-75e" and revision == "6.0" and (with_etherbone or with_ethernet):
assert use_internal_osc, "You cannot use the 25MHz clock as system clock since it is provided by the Ethernet PHY and will stop during PHY reset."
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, int(sys_clk_freq),
ident = "LiteX SoC on Colorlight " + board.upper(),
**kwargs)
# CRG --------------------------------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "crossover"] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
if board == "5a-75e" and revision == "6.0":
sdram_cls = M12L64322A
else:
sdram_cls = M12L16161A
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_full_memory_we = False,
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Leds -------------------------------------------------------------------------------------
# Disable leds when serial is used.
if platform.lookup_request("serial", loose=True) is None and with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).")
parser.add_argument("--revision", default="7.0", type=str, help="Board revision (6.0, 6.1, 7.0 or 8.0).")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(board=args.board, revision=args.revision,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_phy = args.eth_phy,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
if __name__ == "__main__":
main()
| [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((8325, 8394), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Colorlight 5A-75X"""'}), "(description='LiteX SoC on Colorlight 5A-75X')\n", (8348, 8394), False, 'import argparse\n'), ((9782, 9802), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (9794, 9802), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((5388, 5433), 'litex_boards.platforms.colorlight_5a_75b.Platform', 'colorlight_5a_75b.Platform', ([], {'revision': 'revision'}), '(revision=revision)\n', (5414, 5433), False, 'from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e\n'), ((10334, 10355), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (10349, 10355), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((5489, 5534), 'litex_boards.platforms.colorlight_5a_75e.Platform', 'colorlight_5a_75e.Platform', ([], {'revision': 'revision'}), '(revision=revision)\n', (5515, 5534), False, 'from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
# U11F
("clk50", 0, Pins("R2"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("U2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("M5")), # MCU_RX
Subsignal("rx", Pins("N6")), # MCU_TX
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"U15 M17 N18 U16 R18 P18 T18 T17",
"U17 N16 R16 N17 V17 R17"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("T15 M16 P15"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("L18"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("K17"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("P16"), IOStandard("SSTL15")),
Subsignal("dm", Pins("D9 B14 F14 C18"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"D11 B11 D8 C11 C8 B10 C9 A10 "
"A15 A14 E13 B12 C13 A12 D13 A13 "
"H18 G17 G16 F17 G14 E18 H16 H17 "
"C17 D16 B17 E16 C16 E17 D15 D18 "
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("B9 C14 G15 B16"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("A9 B15 F15 A17"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("P14"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("R15"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("K15"), IOStandard("SSTL15")),
Subsignal("odt", Pins("K18"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("V16"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("J16"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("N1"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("D6")),
Subsignal("clk_n", Pins("D5")),
Subsignal("rx_p", Pins("E4")),
Subsignal("rx_n", Pins("E3")),
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1"))
),
("hdmi_in", 0,
Subsignal("clk_p", Pins("P4"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("P3"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("U4"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("V4"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("P6"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("P5"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("R7"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("T7"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("K5"), IOStandard("LVCMOS33")), # FPIO5 (not connected)
Subsignal("sda", Pins("J5"), IOStandard("LVCMOS33")), # FPIO4 (not connected)
),
("hdmi_out", 0,
Subsignal("clk_p", Pins("R3"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("T2"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("T4"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("T3"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("U6"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("U5"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("V7"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("V6"), IOStandard("TMDS_33")),
IOStandard("TMDS_33")
),
("hdmi_sda_over_up", 0, Pins("V7"), IOStandard("LVCMOS33")),
("hdmi_sda_over_dn", 0, Pins("R6"), IOStandard("LVCMOS33")),
("hdmi_hdp_over", 0, Pins("V8"), IOStandard("LVCMOS33")),
]
class Platform(XilinxPlatform):
name = "netv2"
default_clk_name = "clk50"
default_clk_period = 20.0
# From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
# 17536096 bits == 2192012 == 0x21728c -- Therefore 0x220000
gateware_size = 0x220000
# ???
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_read_dummy_bits = 10
spiflash_clock_div = 4
spiflash_total_size = int((256/8)*1024*1024) # 256Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
spiflash_model = "n25q128"
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a50t-csg325-2", _io,
toolchain=toolchain)
self.add_platform_command(
"set_property CONFIG_VOLTAGE 1.5 [current_design]")
self.add_platform_command(
"set_property CFGBVS GND [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]")
self.toolchain.bitstream_commands = [
"set_property CONFIG_VOLTAGE 1.5 [current_design]",
"set_property CFGBVS GND [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
]
self.toolchain.additional_commands = \
["write_cfgmem -verbose -force -format bin -interface spix1 -size 64 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("""
create_clock -name pcie_phy_clk -period 10.0 [get_pins {{pcie_phy/pcie_support_i/pcie_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/TXOUTCLK}}]
""")
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4291, 4366), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50t-csg325-2"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a50t-csg325-2', _io, toolchain=toolchain)\n", (4314, 4366), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((5944, 5986), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (5970, 5986), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((5710, 5766), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""n25q128-3.3v-spi-x1_x2_x4"""'}), "(flash_part='n25q128-3.3v-spi-x1_x2_x4')\n", (5726, 5766), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
"""Module for talking to TOFE boards."""
from migen.fhdl import *
from litex.soc.cores.gpio import GPIOIn, GPIOOut
from litex.soc.interconnect.csr import *
from gateware import i2c
class TOFE(Module, AutoCSR):
"""Common TOFE parts."""
def __init__(self, platform):
# TOFE board
tofe_pads = platform.request('tofe')
self.submodules.i2c = i2c.I2C(tofe_pads)
# Use a proper Tristate for the reset signal so the "pull up" works.
tofe_reset = TSTriple(1)
self.comb += [
tofe_reset.o.eq(0),
]
self.specials += [
tofe_reset.get_tristate(tofe_pads.rst),
]
self.submodules.rst = GPIOOut(tofe_reset.oe)
class TOFELowSpeedIO(TOFE):
"""TOFE LowSpeedIO board."""
def __init__(self, platform, shared_uart):
TOFE.__init__(self, platform)
# UARTs
shared_uart.add_uart_pads(platform.request('tofe_lsio_serial'))
shared_uart.add_uart_pads(platform.request('tofe_lsio_pmod_serial'))
# LEDs
lsio_leds = Signal(4)
self.submodules.lsio_leds = GPIOOut(lsio_leds)
self.comb += [
platform.request('tofe_lsio_user_led', 0).eq(lsio_leds[0]),
platform.request('tofe_lsio_user_led', 1).eq(lsio_leds[1]),
platform.request('tofe_lsio_user_led', 2).eq(lsio_leds[2]),
platform.request('tofe_lsio_user_led', 3).eq(lsio_leds[3]),
]
# Switches
lsio_sws = Signal(4)
self.submodules.lsio_sws = GPIOIn(lsio_sws)
self.comb += [
lsio_sws[0].eq(~platform.request('tofe_lsio_user_sw', 0)),
lsio_sws[1].eq(~platform.request('tofe_lsio_user_sw', 1)),
lsio_sws[2].eq(~platform.request('tofe_lsio_user_sw', 2)),
lsio_sws[3].eq(~platform.request('tofe_lsio_user_sw', 3)),
]
class TOFE2AXIOM(TOFE):
"""TOFE to AXIOM Adapter board."""
pass
def TOFEBoard(name):
if name.lower() == "lowspeedio":
return TOFELowSpeedIO
elif name.lower() == "axiom":
return TOFELowSpeedIO
else:
return TOFE
| [
"litex.soc.cores.gpio.GPIOIn",
"litex.soc.cores.gpio.GPIOOut"
] | [((374, 392), 'gateware.i2c.I2C', 'i2c.I2C', (['tofe_pads'], {}), '(tofe_pads)\n', (381, 392), False, 'from gateware import i2c\n'), ((688, 710), 'litex.soc.cores.gpio.GPIOOut', 'GPIOOut', (['tofe_reset.oe'], {}), '(tofe_reset.oe)\n', (695, 710), False, 'from litex.soc.cores.gpio import GPIOIn, GPIOOut\n'), ((1108, 1126), 'litex.soc.cores.gpio.GPIOOut', 'GPIOOut', (['lsio_leds'], {}), '(lsio_leds)\n', (1115, 1126), False, 'from litex.soc.cores.gpio import GPIOIn, GPIOOut\n'), ((1531, 1547), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', (['lsio_sws'], {}), '(lsio_sws)\n', (1537, 1547), False, 'from litex.soc.cores.gpio import GPIOIn, GPIOOut\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
from litex.build import tools
class GenericProgrammer:
def __init__(self, flash_proxy_basename=None):
self.flash_proxy_basename = flash_proxy_basename
self.flash_proxy_dirs = [
"~/.migen", "/usr/local/share/migen", "/usr/share/migen",
"~/.mlabs", "/usr/local/share/mlabs", "/usr/share/mlabs",
"~/.litex", "/usr/local/share/litex", "/usr/share/litex"
]
self.flash_proxy_repos = [
"https://github.com/quartiq/bscan_spi_bitstreams/raw/master/",
]
self.config_repos = [
"https://raw.githubusercontent.com/litex-hub/litex-boards/master/litex_boards/prog/",
]
self.prog_local = "prog"
def set_flash_proxy_dir(self, flash_proxy_dir):
if flash_proxy_dir is not None:
self.flash_proxy_dirs = [flash_proxy_dir]
def find_flash_proxy(self):
# Search in installed flash_proxy_directories
for d in self.flash_proxy_dirs:
fulldir = os.path.abspath(os.path.expanduser(d))
fullname = tools.cygpath(os.path.join(fulldir, self.flash_proxy_basename))
if os.path.exists(fullname):
return fullname
# Search in local flash_proxy directory
fullname = tools.cygpath(os.path.join(self.prog_local, self.flash_proxy_basename))
if os.path.exists(fullname):
return fullname
# Search in repositories and download it
import requests
os.makedirs(self.prog_local, exist_ok=True)
for d in self.flash_proxy_repos:
fullname = tools.cygpath(os.path.join(self.prog_local, self.flash_proxy_basename))
try:
r = requests.get(d + self.flash_proxy_basename)
if r.status_code != 404:
with open(fullname, "wb") as f:
f.write(r.content)
return fullname
except:
pass
raise OSError("Failed to find flash proxy bitstream")
def find_config(self):
# Search in local directory
fullname = tools.cygpath(self.config)
if os.path.exists(fullname):
return self.config
# Search in local config directory
fullname = tools.cygpath(os.path.join(self.prog_local, self.config))
if os.path.exists(fullname):
return fullname
# Search in repositories and download it
import requests
os.makedirs(self.prog_local, exist_ok=True)
for d in self.config_repos:
fullname = tools.cygpath(os.path.join(self.prog_local, self.config))
try:
r = requests.get(d + self.config)
if r.status_code != 404:
with open(fullname, "wb") as f:
f.write(r.content)
return fullname
except:
pass
raise OSError("Failed to find config file")
# Must be overloaded by specific programmer
def load_bitstream(self, bitstream_file):
raise NotImplementedError
# Must be overloaded by specific programmer
def flash(self, address, data_file):
raise NotImplementedError
def call(self, command, check=True):
if (subprocess.call(command) != 0) and check:
msg = f"Error occured during {self.__class__.__name__}'s call, please check:\n"
msg += f"- {self.__class__.__name__} installation.\n"
msg += f"- access permissions.\n"
msg += f"- hardware and cable."
raise OSError(msg)
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#!/usr/bin/env python3
import sys
import os
from litex.gen import *
from litex.gen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.soc.integration.soc_core import mem_decoder
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores import dna, xadc
from litex.soc.cores.frequency_meter import FrequencyMeter
from litedram.modules import MT41J128M16
from litedram.phy import a7ddrphy
from litedram.core import ControllerSettings
from litepcie.phy.s7pciephy import S7PCIEPHY
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
from litevideo.input import HDMIIn
from litevideo.output import VideoOut
import cpu_interface
_io = [
("clk50", 0, Pins("R2"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("U2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("M5")),
Subsignal("rx", Pins("N6")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"U15 M17 N18 U16 R18 P18 T18 T17",
"U17 N16 R16 N17 V17 R17"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("T15 M16 P15"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("L18"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("K17"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("P16"), IOStandard("SSTL15")),
Subsignal("dm", Pins("D9 B14 F14 C18"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"D11 B11 D8 C11 C8 B10 C9 A10 "
"A15 A14 E13 B12 C13 A12 D13 A13 "
"H18 G17 G16 F17 G14 E18 H16 H17 "
"C17 D16 B17 E16 C16 E17 D15 D18 "
),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("B9 C14 G15 B16"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("A9 B15 F15 A17"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("P14"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("R15"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("K15"), IOStandard("SSTL15")),
Subsignal("odt", Pins("K18"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("V16"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("J16"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("N1"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("D6")),
Subsignal("clk_n", Pins("D5")),
Subsignal("rx_p", Pins("E4")),
Subsignal("rx_n", Pins("E3")),
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1"))
),
("hdmi_in", 0,
Subsignal("clk_p", Pins("P4"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("P3"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("U4"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("V4"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("P6"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("P5"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("R7"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("T7"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("K5"), IOStandard("LVCMOS33")), # FPIO5 (not connected)
Subsignal("sda", Pins("J5"), IOStandard("LVCMOS33")), # FPIO4 (not connected)
),
("hdmi_out", 0,
Subsignal("clk_p", Pins("R3"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("T2"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("T4"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("T3"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("U6"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("U5"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("V7"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("V6"), IOStandard("TMDS_33")),
),
("hdmi_sda_over_up", 0, Pins("V7"), IOStandard("LVCMOS33")),
("hdmi_sda_over_dn", 0, Pins("R6"), IOStandard("LVCMOS33")),
("hdmi_hdp_over", 0, Pins("V8"), IOStandard("LVCMOS33")),
]
class Platform(XilinxPlatform):
def __init__(self, toolchain="vivado", programmer="vivado"):
XilinxPlatform.__init__(self, "xc7a50t-csg325-2", _io,
toolchain=toolchain)
self.add_platform_command(
"set_property CONFIG_VOLTAGE 1.5 [current_design]")
self.add_platform_command(
"set_property CFGBVS GND [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]")
self.add_platform_command(
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]")
self.toolchain.bitstream_commands = [
"set_property CONFIG_VOLTAGE 1.5 [current_design]",
"set_property CFGBVS GND [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]",
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design]",
]
self.toolchain.additional_commands = \
["write_cfgmem -verbose -force -format bin -interface spix1 -size 64 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("""
create_clock -name pcie_phy_clk -period 10.0 [get_pins {{pcie_phy/pcie_support_i/pcie_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i/TXOUTCLK}}]
""")
def create_programmer(self):
if self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
def csr_map_update(csr_map, csr_peripherals):
csr_map.update(dict((n, v)
for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1)))
def period_ns(freq):
return 1e9/freq
class CRG(Module):
def __init__(self, platform):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_clk200 = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
clk50 = platform.request("clk50")
rst = Signal()
pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
pll_sys4x = Signal()
pll_sys4x_dqs = Signal()
pll_clk200 = Signal()
self.specials += [
Instance("PLLE2_BASE",
p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
# VCO @ 1600 MHz
p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=20.0,
p_CLKFBOUT_MULT=32, p_DIVCLK_DIVIDE=1,
i_CLKIN1=clk50, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 100 MHz
p_CLKOUT0_DIVIDE=16, p_CLKOUT0_PHASE=0.0,
o_CLKOUT0=self.pll_sys,
# 400 MHz
p_CLKOUT1_DIVIDE=4, p_CLKOUT1_PHASE=0.0,
o_CLKOUT1=pll_sys4x,
# 400 MHz dqs
p_CLKOUT2_DIVIDE=4, p_CLKOUT2_PHASE=90.0,
o_CLKOUT2=pll_sys4x_dqs,
# 200 MHz
p_CLKOUT3_DIVIDE=8, p_CLKOUT3_PHASE=0.0,
o_CLKOUT3=pll_clk200
),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_clk100.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk100, ~pll_locked | rst)
]
reset_counter = Signal(4, reset=15)
ic_reset = Signal(reset=1)
self.sync.clk200 += \
If(reset_counter != 0,
reset_counter.eq(reset_counter - 1)
).Else(
ic_reset.eq(0)
)
self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
class BaseSoC(SoCSDRAM):
csr_peripherals = {
"ddrphy",
"dna",
"xadc",
}
csr_map_update(SoCSDRAM.csr_map, csr_peripherals)
def __init__(self, platform, **kwargs):
clk_freq = int(100e6)
SoCSDRAM.__init__(self, platform, clk_freq,
integrated_rom_size=0x8000,
integrated_sram_size=0x8000,
ident="NeTV2 LiteX Base SoC",
reserve_nmi_interrupt=False,
**kwargs)
self.submodules.crg = CRG(platform)
self.submodules.dna = dna.DNA()
self.submodules.xadc = xadc.XADC()
self.crg.cd_sys.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, period_ns(100e6))
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41J128M16(self.clk_freq, "1:4")
self.add_constant("READ_LEVELING_BITSLIP", 3)
self.add_constant("READ_LEVELING_DELAY", 14)
self.register_sdram(self.ddrphy,
sdram_module.geom_settings,
sdram_module.timing_settings,
controller_settings=ControllerSettings(with_bandwidth=True,
cmd_buffer_depth=8,
with_refresh=True))
# common led
self.sys_led = Signal()
self.pcie_led = Signal()
self.comb += platform.request("user_led", 0).eq(self.sys_led ^ self.pcie_led)
# sys led
sys_counter = Signal(32)
self.sync += sys_counter.eq(sys_counter + 1)
self.comb += self.sys_led.eq(sys_counter[26])
class PCIeSoC(BaseSoC):
csr_map = {
"pcie_phy": 20,
"dma": 21,
"msi": 22,
}
csr_map.update(BaseSoC.csr_map)
BaseSoC.mem_map["csr"] = 0x00000000
BaseSoC.mem_map["rom"] = 0x20000000
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, csr_data_width=32, **kwargs)
# pcie phy
self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.pcie_phy.cd_pcie.clk)
# pcie endpoint
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, with_reordering=True)
# pcie wishbone bridge
self.submodules.pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, lambda a: 1)
self.add_wb_master(self.pcie_wishbone.wishbone)
# pcie dma
self.submodules.dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, with_loopback=True)
self.dma.source.connect(self.dma.sink)
# pcie msi
self.submodules.msi = LitePCIeMSI()
self.comb += self.msi.source.connect(self.pcie_phy.msi)
self.interrupts = {
"DMA_WRITER": self.dma.writer.irq,
"DMA_READER": self.dma.reader.irq
}
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.msi.irqs[i].eq(v)
self.add_constant(k + "_INTERRUPT", i)
# pcie led
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += self.pcie_led.eq(pcie_counter[26])
def generate_software_header(self):
csr_header = get_csr_header(self.get_csr_regions(),
self.get_constants(),
with_access_functions=False)
tools.write_to_file(os.path.join("software", "pcie", "kernel", "csr.h"), csr_header)
class VideoSoC(BaseSoC):
csr_peripherals = {
"hdmi_out0",
"hdmi_in0",
"hdmi_in0_freq",
"hdmi_in0_edid_mem"
}
csr_map_update(BaseSoC.csr_map, csr_peripherals)
interrupt_map = {
"hdmi_in0": 3,
}
interrupt_map.update(BaseSoC.interrupt_map)
def __init__(self, platform, *args, **kwargs):
BaseSoC.__init__(self, platform, *args, **kwargs)
# # #
pix_freq = 148.50e6
# hdmi in
hdmi_in0_pads = platform.request("hdmi_in")
self.submodules.hdmi_in0_freq = FrequencyMeter(period=self.clk_freq)
self.submodules.hdmi_in0 = HDMIIn(hdmi_in0_pads,
self.sdram.crossbar.get_port(mode="write"),
fifo_depth=512,
device="xc7")
self.comb += self.hdmi_in0_freq.clk.eq(self.hdmi_in0.clocking.cd_pix.clk)
self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix.clk, period_ns(1*pix_freq))
self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix1p25x.clk, period_ns(1.25*pix_freq))
self.platform.add_period_constraint(self.hdmi_in0.clocking.cd_pix5x.clk, period_ns(5*pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.hdmi_in0.clocking.cd_pix.clk,
self.hdmi_in0.clocking.cd_pix1p25x.clk,
self.hdmi_in0.clocking.cd_pix5x.clk)
# hdmi out
hdmi_out0_dram_port = self.sdram.crossbar.get_port(mode="read", dw=16, cd="hdmi_out0_pix", reverse=True)
self.submodules.hdmi_out0 = VideoOut(platform.device,
platform.request("hdmi_out"),
hdmi_out0_dram_port,
"ycbcr422",
fifo_depth=4096)
self.platform.add_period_constraint(self.hdmi_out0.driver.clocking.cd_pix.clk, period_ns(1*pix_freq))
self.platform.add_period_constraint(self.hdmi_out0.driver.clocking.cd_pix5x.clk, period_ns(5*pix_freq))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.hdmi_out0.driver.clocking.cd_pix.clk,
self.hdmi_out0.driver.clocking.cd_pix5x.clk)
# hdmi over
self.comb += [
platform.request("hdmi_sda_over_up").eq(0),
platform.request("hdmi_sda_over_dn").eq(0),
platform.request("hdmi_hdp_over").eq(0),
]
def main():
platform = Platform()
if len(sys.argv) < 2:
print("missing target (base or pcie or video)")
exit()
if sys.argv[1] == "base":
soc = BaseSoC(platform)
elif sys.argv[1] == "pcie":
soc = PCIeSoC(platform)
elif sys.argv[1] == "video":
soc = VideoSoC(platform)
builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv")
vns = builder.build()
if sys.argv[1] == "pcie":
soc.generate_software_header()
if __name__ == "__main__":
main()
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"litex.soc.cores.xadc.XADC",
"litex.soc.cores.dna.DNA",
"litex.soc.cores.frequency_meter.FrequencyMeter",
"litex.build.xilinx.XilinxPlatform.do_finalize",
"litex.build.xilinx.XilinxPlatform.__init__"
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Load bitstream:
# ./decklink_quad_hdmi_recorder.py --csr-csv=csr.csv --build --load
#
# Use:
# litex_server --jtag --jtag-config=openocd_xc7_ft232.cfg
# litex_term crossover
import os
from migen import *
from litex_boards.platforms import quad_hdmi_recorder
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litedram.common import PHYPadsReducer
from litedram.modules import MT41J256M16
from litedram.phy import usddrphy
from litepcie.phy.uspciephy import USPCIEPHY
from litepcie.software import generate_litepcie_software
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
# # #
self.submodules.pll = pll = USMMCM(speedgrade=-2)
pll.register_clkin(platform.request("clk200"), 200e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
p_BUFGCE_DIVIDE=4,
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(200e6), with_pcie=False, pcie_lanes=4, **kwargs):
platform = quad_hdmi_recorder.Platform()
# SoCCore ----------------------------------------------------------------------------------
kwargs["uart_name"] = "crossover"
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Blackmagic Decklink Quad HDMI Recorder",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# JTAGBone --------------------------------------------------------------------------------
self.add_jtagbone()
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = usddrphy.USDDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
memtype = "DDR3",
sys_clk_freq = sys_clk_freq,
iodelay_clk_freq = 200e6)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# PCIe -------------------------------------------------------------------------------------
# FIXME: Does not seem to be working when also enabling DRAM. Has been tested succesfully by
# disabling DRAM with --integrated-main-ram-size=0x100.
if with_pcie:
data_width = {
4 : 128,
8 : 256,
}[pcie_lanes]
self.submodules.pcie_phy = USPCIEPHY(platform, platform.request(f"pcie_x{pcie_lanes}"),
speed = "gen3",
data_width = data_width,
bar0_size = 0x20000)
self.add_pcie(phy=self.pcie_phy, ndmas=1)
# False Paths (FIXME: Improve integration).
platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks sys_clk] -to [get_clocks pcie_clk_1]")
platform.toolchain.pre_placement_commands.append("set_false_path -from [get_clocks pcie_clk_1] -to [get_clocks sys_clk]")
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency.")
target_group.add_argument("--with-pcie", action="store_true", help="Enable PCIe support.")
target_group.add_argument("--driver", action="store_true", help="Generate PCIe driver.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_pcie = args.with_pcie,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.driver:
generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()
| [
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((4671, 4765), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on Blackmagic Decklink Quad HDMI Recorder"""'}), "(description=\n 'LiteX SoC on Blackmagic Decklink Quad HDMI Recorder')\n", (4693, 4765), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((2224, 2253), 'litex_boards.platforms.quad_hdmi_recorder.Platform', 'quad_hdmi_recorder.Platform', ([], {}), '()\n', (2251, 2253), False, 'from litex_boards.platforms import quad_hdmi_recorder\n'), ((5697, 5739), 'os.path.join', 'os.path.join', (['builder.output_dir', '"""driver"""'], {}), "(builder.output_dir, 'driver')\n", (5709, 5739), False, 'import os\n'), ((3384, 3416), 'litedram.modules.MT41J256M16', 'MT41J256M16', (['sys_clk_freq', '"""1:4"""'], {}), "(sys_clk_freq, '1:4')\n", (3395, 3416), False, 'from litedram.modules import MT41J256M16\n')] |
from itertools import product
from sys import stdout
import time
from collections import defaultdict
import json
import ctypes
from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True, config_csv="test/analyzer.csv")
analyzer.configure_subsampler(1024) ## increase this to "skip" cycles, e.g. subsample
analyzer.configure_group(0)
# trigger conditions will depend upon each other in sequence
analyzer.add_falling_edge_trigger("puf_reset")
analyzer.run(offset=8, length=512) ### CHANGE THIS TO MATCH DEPTH offset=32 by default
samples = defaultdict(list)
for s1, s2 in product(range(5), repeat=2):
for sample_idx in range(10): # take n samples
wb.regs.hybridpuf_reset.write(1) # enable reset
wb.regs.hybridpuf_cell0_select.write(s1)
wb.regs.hybridpuf_cell1_select.write(s2)
wb.regs.hybridpuf_reset.write(0) # disable reset
time.sleep(0.1)
bit_value = wb.regs.hybridpuf_bit_value.read()
samples[f'{s1}:{s2}'].append(bit_value)
print(f'Comparator from set {s1} and {s2}: {bit_value}')
dump = json.dumps({
'ident': None,
'dump': samples
})
print(dump)
analyzer.wait_done()
analyzer.upload()
analyzer.save("test/dump.vcd")
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((255, 291), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (267, 291), False, 'from litex.tools.litex_client import RemoteClient\n'), ((314, 407), 'litescope.software.driver.analyzer.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (['wb.regs', '"""analyzer"""'], {'debug': '(True)', 'config_csv': '"""test/analyzer.csv"""'}), "(wb.regs, 'analyzer', debug=True, config_csv=\n 'test/analyzer.csv')\n", (337, 407), False, 'from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver\n'), ((728, 745), 'collections.defaultdict', 'defaultdict', (['list'], {}), '(list)\n', (739, 745), False, 'from collections import defaultdict\n'), ((1250, 1294), 'json.dumps', 'json.dumps', (["{'ident': None, 'dump': samples}"], {}), "({'ident': None, 'dump': samples})\n", (1260, 1294), False, 'import json\n'), ((1058, 1073), 'time.sleep', 'time.sleep', (['(0.1)'], {}), '(0.1)\n', (1068, 1073), False, 'import time\n')] |
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
"""
AXI frontend for LiteDRAM
Converts AXI ports to Native ports.
Features:
- Write/Read arbitration.
- Write/Read data buffers (configurable depth).
- Burst support (FIXED/INCR/WRAP).
- ID support (configurable width).
Limitations:
- Response always okay.
- No reordering.
"""
from migen import *
from migen.genlib.record import *
from migen.genlib.roundrobin import *
from litex.soc.interconnect import stream
from litex.soc.interconnect.axi import *
class LiteDRAMAXIPort(AXIInterface):
pass
class LiteDRAMAXI2NativeW(Module):
def __init__(self, axi, port, buffer_depth, base_address):
assert axi.address_width >= log2_int(base_address)
assert axi.data_width == port.data_width
self.cmd_request = Signal()
self.cmd_grant = Signal()
# # #
ashift = log2_int(port.data_width//8)
# Burst to Beat
aw_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width))
self.submodules += aw_buffer
self.comb += axi.aw.connect(aw_buffer.sink)
aw = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
aw_burst2beat = AXIBurst2Beat(aw_buffer.source, aw)
self.submodules.aw_burst2beat = aw_burst2beat
# Write Buffer
w_buffer = stream.SyncFIFO(w_description(axi.data_width, axi.id_width),
buffer_depth, buffered=True)
self.submodules.w_buffer = w_buffer
# Write ID Buffer & Response
id_buffer = stream.SyncFIFO([("id", axi.id_width)], buffer_depth)
resp_buffer = stream.SyncFIFO([("id", axi.id_width), ("resp", 2)], buffer_depth)
self.submodules += id_buffer, resp_buffer
self.comb += [
id_buffer.sink.valid.eq(aw.valid & aw.first & aw.ready),
id_buffer.sink.id.eq(aw.id),
If(w_buffer.source.valid &
w_buffer.source.last &
w_buffer.source.ready,
resp_buffer.sink.valid.eq(1),
resp_buffer.sink.resp.eq(RESP_OKAY),
resp_buffer.sink.id.eq(id_buffer.source.id),
id_buffer.source.ready.eq(1)
),
resp_buffer.source.connect(axi.b)
]
# Command
# Accept and send command to the controller only if:
# - Address & Data request are *both* valid.
# - Data buffer is not full.
self.comb += [
self.cmd_request.eq(aw.valid & axi.w.valid & w_buffer.sink.ready),
If(self.cmd_request & self.cmd_grant,
port.cmd.valid.eq(1),
port.cmd.we.eq(1),
port.cmd.addr.eq((aw.addr - base_address) >> ashift),
aw.ready.eq(port.cmd.ready),
axi.w.connect(w_buffer.sink, omit={"valid", "ready"}),
If(port.cmd.ready,
w_buffer.sink.valid.eq(1),
axi.w.ready.eq(1)
)
)
]
# Write Data
self.comb += [
w_buffer.source.connect(port.wdata, omit={"strb", "id"}),
port.wdata.we.eq(w_buffer.source.strb)
]
class LiteDRAMAXI2NativeR(Module):
def __init__(self, axi, port, buffer_depth, base_address):
assert axi.address_width >= log2_int(base_address)
assert axi.data_width == port.data_width
self.cmd_request = Signal()
self.cmd_grant = Signal()
# # #
can_read = Signal()
ashift = log2_int(port.data_width//8)
# Burst to Beat
ar_buffer = stream.Buffer(ax_description(axi.address_width, axi.id_width))
self.submodules += ar_buffer
self.comb += axi.ar.connect(ar_buffer.sink)
ar = stream.Endpoint(ax_description(axi.address_width, axi.id_width))
ar_burst2beat = AXIBurst2Beat(ar_buffer.source, ar)
self.submodules.ar_burst2beat = ar_burst2beat
# Read buffer
r_buffer = stream.SyncFIFO(r_description(axi.data_width, axi.id_width), buffer_depth, buffered=True)
self.submodules.r_buffer = r_buffer
# Read Buffer reservation
# - Incremented when data is planned to be queued
# - Decremented when data is dequeued
r_buffer_queue = Signal()
r_buffer_dequeue = Signal()
r_buffer_level = Signal(max=buffer_depth + 1)
self.comb += [
r_buffer_queue.eq(port.cmd.valid & port.cmd.ready & ~port.cmd.we),
r_buffer_dequeue.eq(r_buffer.source.valid & r_buffer.source.ready)
]
self.sync += [
If(r_buffer_queue,
If(~r_buffer_dequeue, r_buffer_level.eq(r_buffer_level + 1))
).Elif(r_buffer_dequeue,
r_buffer_level.eq(r_buffer_level - 1)
)
]
self.comb += can_read.eq(r_buffer_level != buffer_depth)
# Read ID Buffer
id_buffer = stream.SyncFIFO([("id", axi.id_width)], buffer_depth)
self.submodules += id_buffer
self.comb += [
id_buffer.sink.valid.eq(ar.valid & ar.ready),
id_buffer.sink.last.eq(ar.last),
id_buffer.sink.id.eq(ar.id),
axi.r.last.eq(id_buffer.source.last),
axi.r.id.eq(id_buffer.source.id),
id_buffer.source.ready.eq(axi.r.valid & axi.r.ready)
]
# Command
self.comb += [
self.cmd_request.eq(ar.valid & can_read),
If(self.cmd_grant,
port.cmd.valid.eq(ar.valid & can_read),
ar.ready.eq(port.cmd.ready & can_read),
port.cmd.we.eq(0),
port.cmd.addr.eq((ar.addr - base_address) >> ashift)
)
]
# Read data
self.comb += [
port.rdata.connect(r_buffer.sink, omit={"bank"}),
r_buffer.source.connect(axi.r, omit={"id", "last"}),
axi.r.resp.eq(RESP_OKAY)
]
class LiteDRAMAXI2Native(Module):
def __init__(self, axi, port, w_buffer_depth=16, r_buffer_depth=16, base_address=0x00000000):
# # #
# Write path
self.submodules.write = LiteDRAMAXI2NativeW(axi, port, w_buffer_depth, base_address)
# Read path
self.submodules.read = LiteDRAMAXI2NativeR(axi, port, r_buffer_depth, base_address)
# Write / Read arbitration
arbiter = RoundRobin(2, SP_CE)
self.submodules += arbiter
self.comb += arbiter.ce.eq(~port.cmd.valid | port.cmd.ready)
for i, master in enumerate([self.write, self.read]):
self.comb += arbiter.request[i].eq(master.cmd_request)
self.comb += master.cmd_grant.eq(arbiter.grant == i)
| [
"litex.soc.interconnect.stream.SyncFIFO"
] | [((1554, 1607), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[('id', axi.id_width)]", 'buffer_depth'], {}), "([('id', axi.id_width)], buffer_depth)\n", (1569, 1607), False, 'from litex.soc.interconnect import stream\n'), ((1630, 1696), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[('id', axi.id_width), ('resp', 2)]", 'buffer_depth'], {}), "([('id', axi.id_width), ('resp', 2)], buffer_depth)\n", (1645, 1696), False, 'from litex.soc.interconnect import stream\n'), ((4935, 4988), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[('id', axi.id_width)]", 'buffer_depth'], {}), "([('id', axi.id_width)], buffer_depth)\n", (4950, 4988), False, 'from litex.soc.interconnect import stream\n')] |
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
identifier = ""
for i in range(30):
identifier += chr(wb.read(wb.bases.identifier_mem + 4*(i+1))) # TODO: why + 1?
print(identifier)
print("frequency : {}MHz".format(wb.constants.system_clock_frequency/1000000))
print("link up : {}".format(wb.regs.pcie_phy_lnk_up.read()))
print("bus_master_enable : {}".format(wb.regs.pcie_phy_bus_master_enable.read()))
print("msi_enable : {}".format(wb.regs.pcie_phy_msi_enable.read()))
print("max_req_request_size : {}".format(wb.regs.pcie_phy_max_request_size.read()))
print("max_payload_size : {}".format(wb.regs.pcie_phy_max_payload_size.read()))
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((37, 51), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (49, 51), False, 'from litex import RemoteClient\n')] |
from migen import Module, Signal, If, Instance
from litex.soc.interconnect.csr import AutoCSR, CSRStorage
class Reboot(Module, AutoCSR):
def __init__(self, rst, ext_rst=None):
self.ctrl = CSRStorage(8)
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b10101100)
do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
& self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
]
reset_latch = Signal(reset=0)
if ext_rst is None:
self.sync += [
reset_latch.eq(do_reset | reset_latch)
]
else:
self.sync += [
reset_latch.eq(do_reset | reset_latch | ext_rst)
]
self.comb += [
rst.eq(~reset_latch)
]
| [
"litex.soc.interconnect.csr.CSRStorage"
] | [((202, 215), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {}), '(8)\n', (212, 215), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage\n'), ((244, 252), 'migen.Signal', 'Signal', ([], {}), '()\n', (250, 252), False, 'from migen import Module, Signal, If, Instance\n'), ((541, 556), 'migen.Signal', 'Signal', ([], {'reset': '(0)'}), '(reset=0)\n', (547, 556), False, 'from migen import Module, Signal, If, Instance\n')] |
from migen import Module, Instance, Signal
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
class SBWarmBoot(Module, AutoCSR):
def __init__(self, parent):
self.ctrl = CSRStorage(size=8)
self.addr = CSRStorage(size=32)
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b101011xx)
do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
& self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
]
self.specials += Instance("SB_WARMBOOT",
i_S0 = self.ctrl.storage[0],
i_S1 = self.ctrl.storage[1],
i_BOOT = do_reset,
)
parent.config["BITSTREAM_SYNC_HEADER1"] = 0x7e99aa7e
parent.config["BITSTREAM_SYNC_HEADER2"] = 0x7eaa997e
| [
"litex.soc.interconnect.csr.CSRStorage"
] | [((201, 219), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'size': '(8)'}), '(size=8)\n', (211, 219), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((240, 259), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'size': '(32)'}), '(size=32)\n', (250, 259), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((279, 287), 'migen.Signal', 'Signal', ([], {}), '()\n', (285, 287), False, 'from migen import Module, Instance, Signal\n'), ((578, 677), 'migen.Instance', 'Instance', (['"""SB_WARMBOOT"""'], {'i_S0': 'self.ctrl.storage[0]', 'i_S1': 'self.ctrl.storage[1]', 'i_BOOT': 'do_reset'}), "('SB_WARMBOOT', i_S0=self.ctrl.storage[0], i_S1=self.ctrl.storage[1\n ], i_BOOT=do_reset)\n", (586, 677), False, 'from migen import Module, Instance, Signal\n')] |
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
("clk100", 0, Pins("R4"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("AB1"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AB8"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("AA1"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("AB6"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("T1")),
Subsignal("rx", Pins("U1")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"M2 M5 M3 M1 L6 P1 N3 N2",
"M6 R1 L5 N5 N4 P2 P6"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("L3 K6 L4"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("J4"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("K3"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("L1"), IOStandard("SSTL15")),
Subsignal("dm", Pins("G3 F1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"G2 H4 H5 J1 K1 H3 H2 J5",
"E3 B2 F3 D2 C2 A1 E2 B1"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("J6"), IOStandard("SSTL15")),
Subsignal("odt", Pins("K4"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("G1"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("AB7"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B10")),
Subsignal("rx_n", Pins("A10")),
Subsignal("tx_p", Pins("B6")),
Subsignal("tx_n", Pins("A6"))
),
("usb_fifo_clock", 0, Pins("D17"), IOStandard("LVCMOS33")),
("usb_fifo", 0,
Subsignal("rst", Pins("K22")),
Subsignal("data", Pins("A16 F14 A15 F13 A14 E14 A13 E13 B13 C15 C13 C14 B16 E17 B15 F16",
"A20 E18 B20 F18 D19 D21 E19 E21 A21 B21 A19 A18 F20 F19 B18 B17")),
Subsignal("be", Pins("K16 L16 G20 H20")),
Subsignal("rxf_n", Pins("M13")),
Subsignal("txe_n", Pins("L13")),
Subsignal("rd_n", Pins("K19")),
Subsignal("wr_n", Pins("M15")),
Subsignal("oe_n", Pins("K18")),
Subsignal("siwua", Pins("M16")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
]
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 40 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2830, 2904), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-fgg484-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a35t-fgg484-2', _io, toolchain='vivado')\n", (2853, 2904), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk / rst
("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
("rst", 0, Pins("P17"), IOStandard("LVCMOS33")),
# leds (only a single rgb led, aliased here also)
("user_led", 0, Pins("W21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("W22"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("AA20"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("W21")),
Subsignal("g", Pins("W22")),
Subsignal("b", Pins("AA20")),
IOStandard("LVCMOS33"),
),
("serial", 0,
Subsignal("tx", Pins("R14")),
Subsignal("rx", Pins("P14")),
Subsignal("rts", Pins("R18")),
Subsignal("cts", Pins("T18")),
Subsignal("cbus0", Pins("N17")),
IOStandard("LVCMOS33")
),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("vvp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33")
),
("flash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("T19")),
Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
IOStandard("LVCMOS33")
),
# tpm
("tpm", 0,
Subsignal("clk", Pins("Y18")),
Subsignal("rst_n", Pins("AA19")),
Subsignal("cs_n", Pins("Y19")),
Subsignal("mosi", Pins("V18")),
Subsignal("miso", Pins("V19")),
IOStandard("LVCMOS33"),
),
# pcie
("pcie_x1", 0,
Subsignal("rst_n", Pins("W20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8")),
Subsignal("rx_n", Pins("A8")),
Subsignal("tx_p", Pins("B4")),
Subsignal("tx_n", Pins("A4"))
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 T5 Y6 T6 V2 T4 Y2 R2",
"Y1 R4 W5 W1 AA6 U2"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y7 K1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
"H4 G2 J5 H2 H5 G4 J1 G3"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("V9 K2"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("V8 J2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
# sdcard
("sdcard", 0,
Subsignal("data", Pins("P19 Y22 Y21 T21")),
Subsignal("cmd", Pins("U21")),
Subsignal("clk", Pins("R19")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
# sfp0
("sfp_tx", 0,
Subsignal("p", Pins("B6")),
Subsignal("n", Pins("A6"))
),
("sfp_rx", 0,
Subsignal("p", Pins("B10")),
Subsignal("n", Pins("A10"))
),
("sfp_tx_disable_n", 0, Pins("V22"), IOStandard("LVCMOS33")),
("sfp_rx_los", 0, Pins("AB21"), IOStandard("LVCMOS33")),
# sfp1
("sfp_tx", 1,
Subsignal("p", Pins("D7")),
Subsignal("n", Pins("C7")),
),
("sfp_rx", 1,
Subsignal("p", Pins("D9")),
Subsignal("n", Pins("C9")),
),
("sfp_tx_disable_n", 1, Pins("P15"), IOStandard("LVCMOS33")),
("sfp_rx_los", 1, Pins("R17"), IOStandard("LVCMOS33")),
]
# TODO: Add complete LPC IOs
_connectors = [
("LPC", {
# FMC GTP Section
"DP0_M2C_P" : "D11",
"DP0_M2C_N" : "C11",
"GBTCLK0_M2C_P" : "F10",
"GBTCLK0_M2C_N" : "E10",
"DP0_C2M_P" : "D5",
"DP0_C2M_N" : "C5",
}
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, _connectors, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4976, 5068), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg484-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg484-2', _io, _connectors,\n toolchain='vivado')\n", (4999, 5068), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((5770, 5828), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft232.cfg"""', '"""bscan_spi_xc7a200t.bit"""'], {}), "('openocd_xc7_ft232.cfg', 'bscan_spi_xc7a200t.bit')\n", (5777, 5828), False, 'from litex.build.openocd import OpenOCD\n'), ((5875, 5917), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (5901, 5917), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Dolu1990 <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from os import path
from migen import *
from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
import os
class Open(Signal): pass
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = {
"standard": "VexRiscv",
"linux": "VexRiscv", # Similar to standard.
}
# VexRiscv SMP -------------------------------------------------------------------------------------
class VexRiscvSMP(CPU):
family = "riscv"
name = "vexriscv"
human_name = "VexRiscv SMP"
variants = CPU_VARIANTS
data_width = 32
endianness = "little"
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # Origin, Length.
# Default parameters.
cpu_count = 1
dcache_size = 4096
icache_size = 4096
dcache_ways = 1
icache_ways = 1
coherent_dma = False
litedram_width = 32
dcache_width = 32
icache_width = 32
aes_instruction = False
out_of_order_decoder = True
wishbone_memory = False
with_fpu = False
cpu_per_fpu = 4
with_rvc = False
dtlb_size = 4
itlb_size = 4
# Command line configuration arguments.
@staticmethod
def args_fill(parser):
cpu_group = parser.add_argument_group("cpu")
cpu_group.add_argument("--cpu-count", default=1, help="Number of CPU(s) in the cluster.", type=int)
cpu_group.add_argument("--with-coherent-dma", action="store_true", help="Enable Coherent DMA Slave interface.")
cpu_group.add_argument("--without-coherent-dma", action="store_true", help="Disable Coherent DMA Slave interface.")
cpu_group.add_argument("--dcache-width", default=None, help="L1 data cache bus width.")
cpu_group.add_argument("--icache-width", default=None, help="L1 instruction cache bus width.")
cpu_group.add_argument("--dcache-size", default=None, help="L1 data cache size in byte per CPU.")
cpu_group.add_argument("--dcache-ways", default=None, help="L1 data cache ways per CPU.")
cpu_group.add_argument("--icache-size", default=None, help="L1 instruction cache size in byte per CPU.")
cpu_group.add_argument("--icache-ways", default=None, help="L1 instruction cache ways per CPU")
cpu_group.add_argument("--aes-instruction", default=None, help="Enable AES instruction acceleration.")
cpu_group.add_argument("--without-out-of-order-decoder", action="store_true", help="Reduce area at cost of peripheral access speed")
cpu_group.add_argument("--with-wishbone-memory", action="store_true", help="Disable native LiteDRAM interface")
cpu_group.add_argument("--with-fpu", action="store_true", help="Enable the F32/F64 FPU")
cpu_group.add_argument("--cpu-per-fpu", default="4", help="Maximal ratio between CPU count and FPU count. Will instanciate as many FPU as necessary.")
cpu_group.add_argument("--with-rvc", action="store_true", help="Enable RISC-V compressed instruction support")
cpu_group.add_argument("--dtlb-size", default=4, help="Data TLB size.")
cpu_group.add_argument("--itlb-size", default=4, help="Instruction TLB size.")
@staticmethod
def args_read(args):
VexRiscvSMP.cpu_count = args.cpu_count
if int(args.cpu_count) != 1:
VexRiscvSMP.icache_width = 64
VexRiscvSMP.dcache_width = 64
VexRiscvSMP.dcache_size = 8192
VexRiscvSMP.icache_size = 8192
VexRiscvSMP.dcache_ways = 2
VexRiscvSMP.icache_ways = 2
VexRiscvSMP.coherent_dma = True
if(args.with_coherent_dma): VexRiscvSMP.coherent_dma = bool(True)
if(args.without_coherent_dma): VexRiscvSMP.coherent_dma = bool(False)
if(args.dcache_width): VexRiscvSMP.dcache_width = int(args.dcache_width)
if(args.icache_width): VexRiscvSMP.icache_width = int(args.icache_width)
if(args.dcache_size): VexRiscvSMP.dcache_size = int(args.dcache_size)
if(args.icache_size): VexRiscvSMP.icache_size = int(args.icache_size)
if(args.dcache_ways): VexRiscvSMP.dcache_ways = int(args.dcache_ways)
if(args.icache_ways): VexRiscvSMP.icache_ways = int(args.icache_ways)
if(args.aes_instruction): VexRiscvSMP.aes_instruction = bool(args.aes_instruction)
if(args.without_out_of_order_decoder): VexRiscvSMP.out_of_order_decoder = False
if(args.with_wishbone_memory): VexRiscvSMP.wishbone_memory = True
if(args.with_fpu):
VexRiscvSMP.with_fpu = True
VexRiscvSMP.icache_width = 64
VexRiscvSMP.dcache_width = 64 # Required for F64
if(args.cpu_per_fpu):
VexRiscvSMP.cpu_per_fpu = args.cpu_per_fpu
if(args.with_rvc):
VexRiscvSMP.with_rvc = True
if(args.dtlb_size): VexRiscvSMP.dtlb_size = int(args.dtlb_size)
if(args.itlb_size): VexRiscvSMP.itlb_size = int(args.itlb_size)
# ABI.
@staticmethod
def get_abi():
abi = "ilp32"
if VexRiscvSMP.with_fpu:
abi +="d"
return abi
# Arch.
@staticmethod
def get_arch():
arch = "rv32ima"
if VexRiscvSMP.with_fpu:
arch += "fd"
if VexRiscvSMP.with_rvc:
arch += "c"
return arch
# Memory Mapping.
@property
def mem_map(self):
return {
"rom": 0x00000000,
"sram": 0x10000000,
"main_ram": 0x40000000,
"csr": 0xf0000000,
"clint": 0xf0010000,
"plic": 0xf0c00000,
}
# GCC Flags.
@property
def gcc_flags(self):
flags = f" -march={VexRiscvSMP.get_arch()} -mabi={VexRiscvSMP.get_abi()}"
flags += f" -D__vexriscv__"
flags += f" -DUART_POLLING"
return flags
# Cluster Name Generation.
@staticmethod
def generate_cluster_name():
ldw = f"Ldw{VexRiscvSMP.litedram_width}"
VexRiscvSMP.cluster_name = f"VexRiscvLitexSmpCluster_" \
f"Cc{VexRiscvSMP.cpu_count}" \
"_" \
f"Iw{VexRiscvSMP.icache_width}" \
f"Is{VexRiscvSMP.icache_size}" \
f"Iy{VexRiscvSMP.icache_ways}" \
"_" \
f"Dw{VexRiscvSMP.dcache_width}" \
f"Ds{VexRiscvSMP.dcache_size}" \
f"Dy{VexRiscvSMP.dcache_ways}" \
"_" \
f"ITs{VexRiscvSMP.itlb_size}" \
f"DTs{VexRiscvSMP.dtlb_size}" \
f"{'_'+ldw if not VexRiscvSMP.wishbone_memory else ''}" \
f"{'_Cdma' if VexRiscvSMP.coherent_dma else ''}" \
f"{'_Aes' if VexRiscvSMP.aes_instruction else ''}" \
f"{'_Ood' if VexRiscvSMP.out_of_order_decoder else ''}" \
f"{'_Wm' if VexRiscvSMP.wishbone_memory else ''}" \
f"{'_Fpu' + str(VexRiscvSMP.cpu_per_fpu) if VexRiscvSMP.with_fpu else ''}" \
f"{'_Rvc' if VexRiscvSMP.with_rvc else ''}"
# Default Configs Generation.
@staticmethod
def generate_default_configs():
# Single cores.
for data_width in [16, 32, 64, 128]:
VexRiscvSMP.litedram_width = data_width
VexRiscvSMP.icache_width = 32
VexRiscvSMP.dcache_width = 32
VexRiscvSMP.coherent_dma = False
VexRiscvSMP.cpu_count = 1
# Low cache amount.
VexRiscvSMP.dcache_size = 4096
VexRiscvSMP.icache_size = 4096
VexRiscvSMP.dcache_ways = 1
VexRiscvSMP.icache_ways = 1
# Without DMA.
VexRiscvSMP.coherent_dma = False
VexRiscvSMP.generate_cluster_name()
VexRiscvSMP.generate_netlist()
# With DMA.
VexRiscvSMP.coherent_dma = True
VexRiscvSMP.generate_cluster_name()
VexRiscvSMP.generate_netlist()
# High cache amount.
VexRiscvSMP.dcache_size = 8192
VexRiscvSMP.icache_size = 8192
VexRiscvSMP.dcache_ways = 2
VexRiscvSMP.icache_ways = 2
VexRiscvSMP.icache_width = 32 if data_width < 64 else 64
VexRiscvSMP.dcache_width = 32 if data_width < 64 else 64
# Without DMA.
VexRiscvSMP.coherent_dma = False
VexRiscvSMP.generate_cluster_name()
VexRiscvSMP.generate_netlist()
# With DMA.
VexRiscvSMP.coherent_dma = True
VexRiscvSMP.generate_cluster_name()
VexRiscvSMP.generate_netlist()
# Multi cores.
for core_count in [2,4]:
VexRiscvSMP.litedram_width = 128
VexRiscvSMP.icache_width = 64
VexRiscvSMP.dcache_width = 64
VexRiscvSMP.dcache_size = 8192
VexRiscvSMP.icache_size = 8192
VexRiscvSMP.dcache_ways = 2
VexRiscvSMP.icache_ways = 2
VexRiscvSMP.coherent_dma = True
VexRiscvSMP.cpu_count = core_count
VexRiscvSMP.generate_cluster_name()
VexRiscvSMP.generate_netlist()
# Netlist Generation.
@staticmethod
def generate_netlist():
print(f"Generating cluster netlist")
vdir = get_data_mod("cpu", "vexriscv_smp").data_location
gen_args = []
if(VexRiscvSMP.coherent_dma):
gen_args.append("--coherent-dma")
gen_args.append(f"--cpu-count={VexRiscvSMP.cpu_count}")
gen_args.append(f"--ibus-width={VexRiscvSMP.icache_width}")
gen_args.append(f"--dbus-width={VexRiscvSMP.dcache_width}")
gen_args.append(f"--dcache-size={VexRiscvSMP.dcache_size}")
gen_args.append(f"--icache-size={VexRiscvSMP.icache_size}")
gen_args.append(f"--dcache-ways={VexRiscvSMP.dcache_ways}")
gen_args.append(f"--icache-ways={VexRiscvSMP.icache_ways}")
gen_args.append(f"--litedram-width={VexRiscvSMP.litedram_width}")
gen_args.append(f"--aes-instruction={VexRiscvSMP.aes_instruction}")
gen_args.append(f"--out-of-order-decoder={VexRiscvSMP.out_of_order_decoder}")
gen_args.append(f"--wishbone-memory={VexRiscvSMP.wishbone_memory}")
gen_args.append(f"--fpu={VexRiscvSMP.with_fpu}")
gen_args.append(f"--cpu-per-fpu={VexRiscvSMP.cpu_per_fpu}")
gen_args.append(f"--rvc={VexRiscvSMP.with_rvc}")
gen_args.append(f"--netlist-name={VexRiscvSMP.cluster_name}")
gen_args.append(f"--netlist-directory={vdir}")
gen_args.append(f"--dtlb-size={VexRiscvSMP.dtlb_size}")
gen_args.append(f"--itlb-size={VexRiscvSMP.itlb_size}")
cmd = 'cd {path} && sbt "runMain vexriscv.demo.smp.VexRiscvLitexSmpClusterCmdGen {args}"'.format(path=os.path.join(vdir, "ext", "VexRiscv"), args=" ".join(gen_args))
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
def __init__(self, platform, variant):
self.platform = platform
self.variant = "standard"
self.human_name = self.human_name + "-" + variant.upper()
self.reset = Signal()
self.jtag_clk = Signal()
self.jtag_enable = Signal()
self.jtag_capture = Signal()
self.jtag_shift = Signal()
self.jtag_update = Signal()
self.jtag_reset = Signal()
self.jtag_tdo = Signal()
self.jtag_tdi = Signal()
self.interrupt = Signal(32)
self.pbus = pbus = wishbone.Interface()
self.periph_buses = [pbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
# # #
self.cpu_params = dict(
# Clk / Rst.
i_debugCd_external_clk = ClockSignal(),
i_debugCd_external_reset = ResetSignal() | self.reset,
# Interrupts.
i_interrupts = self.interrupt,
# JTAG.
i_jtag_clk = self.jtag_clk,
i_debugPort_enable = self.jtag_enable,
i_debugPort_capture = self.jtag_capture,
i_debugPort_shift = self.jtag_shift,
i_debugPort_update = self.jtag_update,
i_debugPort_reset = self.jtag_reset,
i_debugPort_tdi = self.jtag_tdi,
o_debugPort_tdo = self.jtag_tdo,
# Peripheral Bus (Master).
o_peripheral_CYC = pbus.cyc,
o_peripheral_STB = pbus.stb,
i_peripheral_ACK = pbus.ack,
o_peripheral_WE = pbus.we,
o_peripheral_ADR = pbus.adr,
i_peripheral_DAT_MISO = pbus.dat_r,
o_peripheral_DAT_MOSI = pbus.dat_w,
o_peripheral_SEL = pbus.sel,
i_peripheral_ERR = pbus.err,
o_peripheral_CTI = pbus.cti,
o_peripheral_BTE = pbus.bte
)
if VexRiscvSMP.coherent_dma:
self.dma_bus = dma_bus = wishbone.Interface(data_width=VexRiscvSMP.dcache_width)
dma_bus_stall = Signal()
dma_bus_inhibit = Signal()
self.cpu_params.update(
# DMA Bus (Slave).
i_dma_wishbone_CYC = dma_bus.cyc,
i_dma_wishbone_STB = dma_bus.stb & ~dma_bus_inhibit,
o_dma_wishbone_ACK = dma_bus.ack,
i_dma_wishbone_WE = dma_bus.we,
i_dma_wishbone_SEL = dma_bus.sel,
i_dma_wishbone_ADR = dma_bus.adr,
o_dma_wishbone_DAT_MISO = dma_bus.dat_r,
i_dma_wishbone_DAT_MOSI = dma_bus.dat_w,
o_dma_wishbone_STALL = dma_bus_stall
)
self.sync += [
If(dma_bus.stb & dma_bus.cyc & ~dma_bus_stall,
dma_bus_inhibit.eq(1),
),
If(dma_bus.ack,
dma_bus_inhibit.eq(0)
)
]
def set_reset_address(self, reset_address):
self.reset_address = reset_address
assert reset_address == 0x00000000
def add_sources(self, platform):
vdir = get_data_mod("cpu", "vexriscv_smp").data_location
print(f"VexRiscv cluster : {self.cluster_name}")
if not path.exists(os.path.join(vdir, self.cluster_name + ".v")):
self.generate_netlist()
# Add RAM.
# By default, use Generic RAM implementation.
ram_filename = "Ram_1w_1rs_Generic.v"
# On Altera/Intel platforms, use specific implementation.
from litex.build.altera import AlteraPlatform
if isinstance(platform, AlteraPlatform):
ram_filename = "Ram_1w_1rs_Intel.v"
# On Efinix platforms, use specific implementation.
from litex.build.efinix import EfinixPlatform
if isinstance(platform, EfinixPlatform):
ram_filename = "Ram_1w_1rs_Efinix.v"
platform.add_source(os.path.join(vdir, ram_filename), "verilog")
# Add Cluster.
platform.add_source(os.path.join(vdir, self.cluster_name + ".v"), "verilog")
def add_soc_components(self, soc, soc_region_cls):
# Set UART/Timer0 CSRs/IRQs to the ones used by OpenSBI.
soc.csr.add("uart", n=2)
soc.csr.add("timer0", n=3)
soc.irq.add("uart", n=0)
soc.irq.add("timer0", n=1)
# Add OpenSBI region.
soc.add_memory_region("opensbi", self.mem_map["main_ram"] + 0x00f00000, 0x80000, type="cached+linker")
# Define number of CPUs
soc.add_config("CPU_COUNT", VexRiscvSMP.cpu_count)
soc.add_constant("CPU_ISA", VexRiscvSMP.get_arch())
# Constants for cache so we can add them in the DTS.
if (VexRiscvSMP.dcache_size > 0):
soc.add_constant("cpu_dcache_size", VexRiscvSMP.dcache_size)
soc.add_constant("cpu_dcache_ways", VexRiscvSMP.dcache_ways)
soc.add_constant("cpu_dcache_block_size", 64) # hardwired?
if (VexRiscvSMP.icache_size > 0):
soc.add_constant("cpu_icache_size", VexRiscvSMP.icache_size)
soc.add_constant("cpu_icache_ways", VexRiscvSMP.icache_ways)
soc.add_constant("cpu_icache_block_size", 64) # hardwired?
# Constants for TLB so we can add them in the DTS
# full associative so only the size is described.
if (VexRiscvSMP.dtlb_size > 0):
soc.add_constant("cpu_dtlb_size", VexRiscvSMP.dtlb_size)
soc.add_constant("cpu_dtlb_ways", VexRiscvSMP.dtlb_size)
if (VexRiscvSMP.itlb_size > 0):
soc.add_constant("cpu_itlb_size", VexRiscvSMP.itlb_size)
soc.add_constant("cpu_itlb_ways", VexRiscvSMP.itlb_size)
# Add PLIC as Bus Slave
self.plicbus = plicbus = wishbone.Interface()
self.cpu_params.update(
i_plicWishbone_CYC = plicbus.cyc,
i_plicWishbone_STB = plicbus.stb,
o_plicWishbone_ACK = plicbus.ack,
i_plicWishbone_WE = plicbus.we,
i_plicWishbone_ADR = plicbus.adr,
o_plicWishbone_DAT_MISO = plicbus.dat_r,
i_plicWishbone_DAT_MOSI = plicbus.dat_w
)
soc.bus.add_slave("plic", self.plicbus, region=soc_region_cls(origin=soc.mem_map.get("plic"), size=0x400000, cached=False))
# Add CLINT as Bus Slave
self.clintbus = clintbus = wishbone.Interface()
self.cpu_params.update(
i_clintWishbone_CYC = clintbus.cyc,
i_clintWishbone_STB = clintbus.stb,
o_clintWishbone_ACK = clintbus.ack,
i_clintWishbone_WE = clintbus.we,
i_clintWishbone_ADR = clintbus.adr,
o_clintWishbone_DAT_MISO = clintbus.dat_r,
i_clintWishbone_DAT_MOSI = clintbus.dat_w,
)
soc.bus.add_slave("clint", clintbus, region=soc_region_cls(origin=soc.mem_map.get("clint"), size=0x10000, cached=False))
def add_memory_buses(self, address_width, data_width):
VexRiscvSMP.litedram_width = data_width
from litedram.common import LiteDRAMNativePort
if(not VexRiscvSMP.wishbone_memory):
ibus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)
dbus = LiteDRAMNativePort(mode="both", address_width=32, data_width=VexRiscvSMP.litedram_width)
self.memory_buses.append(ibus)
self.memory_buses.append(dbus)
self.cpu_params.update(
# Instruction Memory Bus (Master).
o_iBridge_dram_cmd_valid = ibus.cmd.valid,
i_iBridge_dram_cmd_ready = ibus.cmd.ready,
o_iBridge_dram_cmd_payload_we = ibus.cmd.we,
o_iBridge_dram_cmd_payload_addr = ibus.cmd.addr,
o_iBridge_dram_wdata_valid = ibus.wdata.valid,
i_iBridge_dram_wdata_ready = ibus.wdata.ready,
o_iBridge_dram_wdata_payload_data = ibus.wdata.data,
o_iBridge_dram_wdata_payload_we = ibus.wdata.we,
i_iBridge_dram_rdata_valid = ibus.rdata.valid,
o_iBridge_dram_rdata_ready = ibus.rdata.ready,
i_iBridge_dram_rdata_payload_data = ibus.rdata.data,
# Data Memory Bus (Master).
o_dBridge_dram_cmd_valid = dbus.cmd.valid,
i_dBridge_dram_cmd_ready = dbus.cmd.ready,
o_dBridge_dram_cmd_payload_we = dbus.cmd.we,
o_dBridge_dram_cmd_payload_addr = dbus.cmd.addr,
o_dBridge_dram_wdata_valid = dbus.wdata.valid,
i_dBridge_dram_wdata_ready = dbus.wdata.ready,
o_dBridge_dram_wdata_payload_data = dbus.wdata.data,
o_dBridge_dram_wdata_payload_we = dbus.wdata.we,
i_dBridge_dram_rdata_valid = dbus.rdata.valid,
o_dBridge_dram_rdata_ready = dbus.rdata.ready,
i_dBridge_dram_rdata_payload_data = dbus.rdata.data,
)
def do_finalize(self):
assert hasattr(self, "reset_address")
# When no Direct Memory Bus, do memory accesses through Wishbone Peripheral Bus.
if len(self.memory_buses) == 0:
VexRiscvSMP.wishbone_memory = True
# Generate cluster name.
VexRiscvSMP.generate_cluster_name()
# Do verilog instance.
self.specials += Instance(self.cluster_name, **self.cpu_params)
# Add verilog sources
self.add_sources(self.platform)
| [
"litex.get_data_mod",
"litex.soc.interconnect.wishbone.Interface"
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#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
import os
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from axilite2led import AxiLite2Led
from litedram.frontend.adapter import LiteDRAMNativePortConverter
from litedram.frontend.dma import *
from litedram.modules import MT41K256M16
from litedram.phy import s7ddrphy
from liteeth.phy.s7rgmii import LiteEthPHYRGMII
from litesata.phy import LiteSATAPHY
from litescope import LiteScopeAnalyzer
from litex.build.generic_platform import Pins, Subsignal
from litex.build.xilinx.vivado import vivado_build_argdict, vivado_build_args
from litex.soc.cores.clock import *
from litex.soc.cores.led import LedChaser
from litex.soc.integration.builder import *
from litex.soc.integration.soc import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.axi import AXILiteInterface
from litex.soc.interconnect.stream import (ClockDomainCrossing, Converter,
Endpoint, SyncFIFO)
from migen import *
from platforms import nexys_video
from pld_axi import PldAXILiteInterface
from rendering.rendering_4_no_bft import Rendering4Mono
from rendering.rendering_4_page import Rendering4Page
from rendering.rendering_6_no_bft import Rendering6Mono
from rendering.rendering_6_no_bft_vitis import Rendering6MonoVitis
from rendering.rendering_6_page import Rendering6Page
from rendering.rendering_6_page_vitis import Rendering6PageVitis
from rendering.rendering_leaf_only import RenderingLeafOnly
from rendering.rendering_mono import RenderingMono
from start import StartWriter
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, toolchain):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_clk100 = ClockDomain()
self.clock_domains.cd_bft = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_clk100, 100e6)
pll.create_clkout(self.cd_bft, 30e6)
platform.add_false_path_constraints(
self.cd_sys.clk, pll.clkin
) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(
self,
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_sata=False,
**kwargs
):
platform = nexys_video.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(
self,
platform,
sys_clk_freq,
ident="LiteX SoC on Nexys Video",
ident_version=True,
**kwargs
)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
cl=7,
cwl=7,
sys_clk_freq=sys_clk_freq,
)
self.add_csr("ddrphy")
self.add_sdram(
"sdram",
phy=self.ddrphy,
module=MT41K256M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get("min_l2_data_width", 128),
l2_cache_reverse=True,
)
# Ethernet ---------------------------------------------------------------------------------
# self.submodules.ethphy = LiteEthPHYRGMII(
# clock_pads = self.platform.request("eth_clocks"),
# pads = self.platform.request("eth"))
# self.add_csr("ethphy")
# self.add_etherbone(
# phy=self.ethphy,
# ip_address = "192.168.1.50"
# )
rst = self.crg.cd_sys.rst
rstn = ~rst
clk = self.crg.cd_sys.clk
rst_bft = self.crg.cd_bft.rst
rst_bftn = ~rst_bft
clk_bft = self.crg.cd_bft.clk
# AXILite2Led ------------------------------------------------------------------------------
# self.submodules.axilite2led = axilite2led = AxiLite2Led(self.crg.cd_sys.clk, ~self.crg.cd_sys.clk, platform, "sys")
# axilite2led_region = SoCRegion(origin=0x02000000, size=0x10000)
# self.bus.add_slave(name="axilite2led", slave=axilite2led.bus, region=axilite2led_region)
# led_pads = Cat([platform.request("user_led", 0), platform.request("user_led", 1)])
# self.comb += led_pads.eq(axilite2led.led)
# sw_pads = Cat([platform.request("user_sw", 0), platform.request("user_sw", 1)])
# self.comb += axilite2led.sw.eq(sw_pads)
# AXILite2BFT ------------------------------------------------------------------------------
axi_bft_bus_sys = axi.AXILiteInterface(
data_width=32, address_width=5, clock_domain="sys"
)
axi_bft_bus_bft = axi.AXILiteInterface(
data_width=32, address_width=5, clock_domain="bft"
)
self.submodules.axil_cdc_sys2bft = axil_cdc_sys2bft = AxilCDC(
clk, rst, clk_bft, rst_bft, self.platform, "sys", "bft"
)
self.comb += axi_bft_bus_sys.connect(axil_cdc_sys2bft.slave)
self.comb += axil_cdc_sys2bft.master.connect(axi_bft_bus_bft)
axilite2bft_region = SoCRegion(origin=0x02010000, size=0x10000)
self.bus.add_slave(
name="axilite2bft", slave=axi_bft_bus_sys, region=axilite2bft_region
)
# mm2s -------------------------------------------------------------------------------------
# litedram_read_32 = LiteDRAMNativePort('both', 27, 32)
# self.submodules.dram_read_converter = LiteDRAMNativePortConverter(litedram_read_32, self.sdram.crossbar.get_port(), reverse=True)
self.submodules.mm2s = mm2s = LiteDRAMDMAReader(
self.sdram.crossbar.get_port(data_width=32, reverse=True), with_csr=True
)
self.add_csr("mm2s")
mm2s_axis = axi.AXIStreamInterface(32)
self.comb += mm2s.source.connect(mm2s_axis)
# self.submodules.input_cross_domain_converter = (
# input_cross_domain_converter
# ) = ClockDomainCrossing(
# mm2s_axis.description, cd_from="sys", cd_to="bft", depth=8
# )
# mm2s_axis_bft = axi.AXIStreamInterface(32)
# self.comb += mm2s_axis.connect(input_cross_domain_converter.sink)
# self.comb += input_cross_domain_converter.source.connect(mm2s_axis_bft)
# s2mm -------------------------------------------------------------------------------------
# litedram_write_32 = LiteDRAMNativePort('both', 27, 32)
# self.submodules.dram_write_converter = LiteDRAMNativePortConverter(litedram_write_32, self.sdram.crossbar.get_port(), reverse=True)
self.submodules.s2mm = s2mm = LiteDRAMDMAWriter(
self.sdram.crossbar.get_port(data_width=32, reverse=True), with_csr=True
)
self.add_csr("s2mm")
s2mm_axis = axi.AXIStreamInterface(32)
self.comb += s2mm_axis.connect(s2mm.sink)
# self.submodules.output_cross_domain_converter = (
# output_cross_domain_converter
# ) = ClockDomainCrossing(
# s2mm_axis.description, cd_from="bft", cd_to="sys", depth=8
# )
# s2mm_axis_bft = axi.AXIStreamInterface(32)
# self.comb += output_cross_domain_converter.source.connect(s2mm_axis)
# self.comb += s2mm_axis_bft.connect(output_cross_domain_converter.sink)
# start ------------------------------------------------------------------------------------
start_signal = Signal()
self.submodules.start = start = StartWriter(start_signal)
self.add_csr("start")
# sync fifo -------------------------------------------------------------------------------
# self.submodules.sync_fifo = sync_fifo = SyncFIFO([("data", 32)], 8, True)
# self.comb += mm2s.source.connect(sync_fifo.sink)
# self.comb += sync_fifo.source.connect(s2mm.sink)
benchmark = kwargs.get("bench", "rendering")
if benchmark == "rendering":
# Rendering6Page ---------------------------------------------------------------------------
# self.submodules.rendering = rendering = RenderingLeafOnly(
# clk, rst, platform, clock_domain="sys", start=start_signal
# )
# self.submodules.rendering = rendering = Rendering6Mono(clk_bft, rst_bft, platform, start=start_signal, clock_domain='bft')
# self.submodules.rendering = rendering = RenderingMono(clk, rst, platform, clock_domain='sys')
self.submodules.rendering = rendering = Rendering4Mono(clk, rst, platform, clock_domain='sys', start=start_signal)
# self.submodules.rendering = rendering = Rendering6MonoVitis(clk_bft, rst_bft, platform, clock_domain='bft', start=start_signal)
rendering.connect_input(mm2s_axis)
rendering.connect_output(s2mm_axis)
#rendering.connect_axil(axi_bft_bus_bft)
elif benchmark == "digit_recognition":
from digit_recognition.digit_recognition_mono import DigitMono
# DigitRecognition10Page ---------------------------------------------------------------------------
self.submodules.digit_recognition = digit_recognition = DigitMono(
clk, rst, platform, clock_domain="sys"
)
digit_recognition.connect_input(mm2s_axis)
digit_recognition.connect_output(s2mm_axis)
# digit_recognition.connect_axil(axi_bft_bus_bft)
elif benchmark == "array_partition":
from array_partition.array_partition_bft import ArrayPartitionBFT
# DigitRecognition10Page ---------------------------------------------------------------------------
self.submodules.array_partition = array_partition = ArrayPartitionBFT(
clk_bft, rst_bft, platform, clock_domain="bft"
)
array_partition.connect_input(mm2s_axis_bft)
array_partition.connect_output(s2mm_axis_bft)
array_partition.connect_axil(axi_bft_bus_bft)
elif benchmark == "digit_recognition_5":
from digit_recognition.digit_recognition_6_page import \
DigitRecognition6Page
# DigitRecognition6Page ---------------------------------------------------------------------------
self.submodules.digit_recognition = (
digit_recognition
) = DigitRecognition6Page(clk_bft, rst_bft, platform, clock_domain="bft")
digit_recognition.connect_input(mm2s_axis_bft)
digit_recognition.connect_output(s2mm_axis_bft)
digit_recognition.connect_axil(axi_bft_bus_bft)
elif benchmark == "spam_filter":
from spam_filter.spam_filter_mono import SpamFilterMono
# SpamFilter11Page ---------------------------------------------------------------------------
self.submodules.spam_filter = spam_filter = SpamFilterMono(
clk, rst, platform, clock_domain="sys"
)
spam_filter.connect_input(mm2s_axis)
spam_filter.connect_output(s2mm_axis)
# spam_filter.connect_axil(axi_bft_bus_bft)
# self.comb += platform.request("user_led", 0).eq(s2mm.fsm.ongoing("RUN"))
# self.comb += platform.request("user_led", 1).eq(s2mm.fsm.ongoing("DONE"))
# mm2s_ever_valid = Signal()
# s2mm_ever_valid = Signal()
# s2mm_handshake = Signal()
# self.sync += If(mm2s.source.valid, mm2s_ever_valid.eq(1))
# self.sync += If(s2mm.sink.valid, s2mm_ever_valid.eq(1))
# self.sync += If(s2mm.sink.valid & s2mm.sink.ready, s2mm_handshake.eq(1))
# self.comb += platform.request("user_led", 2).eq(mm2s.source.valid)
# self.comb += platform.request("user_led", 3).eq(mm2s.source.ready)
# self.comb += platform.request("user_led", 4).eq(s2mm.sink.valid)
# self.comb += platform.request("user_led", 5).eq(s2mm.sink.ready)
# self.comb += platform.request("user_led", 6).eq(s2mm._sink.last)
# self.comb += platform.request("user_led", 7).eq(s2mm_handshake)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument(
"--toolchain", default="vivado", help="Toolchain use to build (default: vivado)"
)
parser.add_argument(
"--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)"
)
parser.add_argument(
"--with-ethernet", action="store_true", help="Enable Ethernet support"
)
parser.add_argument(
"--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support"
)
parser.add_argument(
"--with-sdcard", action="store_true", help="Enable SDCard support"
)
parser.add_argument(
"--with-sata", action="store_true", help="Enable SATA support (over FMCRAID)"
)
parser.add_argument(
"--bench",
default="rendering",
help="Benchmark use to build (default: rendering)",
)
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
toolchain=args.toolchain,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=args.with_ethernet,
with_sata=args.with_sata,
bench=args.bench,
**soc_core_argdict(args)
)
assert not (args.with_spi_sdcard and args.with_sdcard)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# clk / rst
("clk100", 0, Pins("W19"), IOStandard("LVCMOS33")),
# leds (only a single rgb led, aliased here also)
("user_led", 0, Pins("AB21"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AB22"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("U20"), IOStandard("LVCMOS33")),
# rgb led, active-low
("rgb_led", 0,
Subsignal("r", Pins("AB21")),
Subsignal("g", Pins("AB22")),
Subsignal("b", Pins("U20")),
IOStandard("LVCMOS33"),
),
# flash
("flash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("hold", Pins("R21")),
Subsignal("rst_n", Pins("R19")),
IOStandard("LVCMOS33")
),
("flash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("T19")),
Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
IOStandard("LVCMOS33")
),
# tpm
("tpm", 0,
Subsignal("clk", Pins("W20")),
Subsignal("rst_n", Pins("V19")),
Subsignal("cs_n", Pins("Y18")),
Subsignal("mosi", Pins("Y19")),
Subsignal("miso", Pins("V18")),
IOStandard("LVCMOS33"),
),
# pcie
("pcie_x1", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8")),
Subsignal("rx_n", Pins("A8")),
Subsignal("tx_p", Pins("B4")),
Subsignal("tx_n", Pins("A4"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("AB20"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("F6")),
Subsignal("clk_n", Pins("E6")),
Subsignal("rx_p", Pins("B8 D11 B10 D9")),
Subsignal("rx_n", Pins("A8 C11 A10 C9")),
Subsignal("tx_p", Pins("B4 D5 B6 D7")),
Subsignal("tx_n", Pins("A4 C5 A6 C7"))
),
# dram
("ddram", 0,
Subsignal("a", Pins(
"U6 T5 Y6 T6 V2 T4 Y2 R2",
"Y1 R4 W5 W1 AA6 U2"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("U7"), IOStandard("LVCMOS15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3902, 3977), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg484-2"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg484-2', _io, toolchain='vivado')\n", (3925, 3977), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((4596, 4654), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft232.cfg"""', '"""bscan_spi_xc7a200t.bit"""'], {}), "('openocd_xc7_ft232.cfg', 'bscan_spi_xc7a200t.bit')\n", (4603, 4654), False, 'from litex.build.openocd import OpenOCD\n'), ((4701, 4743), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4727, 4743), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU
class Open(Signal): pass
# EOS-S3 -------------------------------------------------------------------------------------------
class EOS_S3(CPU):
variants = ["standard"]
family = "arm"
name = "eos_s3"
human_name = "EOS S3"
data_width = 32
endianness = "little"
reset_address = 0x0000_0000
gcc_triple = "arm-none-eabi"
gcc_flags = "-mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16"
linker_output_format = "elf32-littlearm"
nop = "nop"
io_regions = {0x4000_0000: 0xc000_0000} # Origin, Length.
# Memory Mapping.
@property
def mem_map(self):
return {
"rom": 0x0000_0000,
"sram": 0x2000_0000,
"csr": 0x4002_0000
}
def __init__(self, platform, variant, *args, **kwargs):
super().__init__(*args, **kwargs)
self.platform = platform
self.reset = Signal()
self.interrupt = Signal(4)
self.pbus = wishbone.Interface(data_width=32, adr_width=15)
self.periph_buses = [self.pbus]
self.memory_buses = []
# # #
# EOS-S3 Clocking --------------------------------------------------------------------------
pbus_rst = Signal()
eos_s3_0_clk = Signal()
eos_s3_0_rst = Signal()
eos_s3_1_clk = Signal()
eos_s3_1_rst = Signal()
self.clock_domains.cd_eos_s3_0 = ClockDomain()
self.clock_domains.cd_eos_s3_1 = ClockDomain()
self.specials += Instance("gclkbuff",
i_A = eos_s3_0_clk,
o_Z = ClockSignal("eos_s3_0")
)
self.specials += Instance("gclkbuff",
i_A = eos_s3_0_rst | pbus_rst,
o_Z = ResetSignal("eos_s3_0")
)
self.specials += Instance("gclkbuff",
i_A = eos_s3_1_clk,
o_Z = ClockSignal("eos_s3_1")
)
self.specials += Instance("gclkbuff",
i_A = eos_s3_1_rst | pbus_rst,
o_Z = ResetSignal("eos_s3_1")
)
# EOS-S3 Instance --------------------------------------------------------------------------
self.cpu_params = dict(
# Wishbone Master.
# -----------
i_WB_CLK = ClockSignal("eos_s3_0"),
o_WB_RST = pbus_rst,
o_WBs_ADR = Cat(Signal(2), self.pbus.adr),
o_WBs_CYC = self.pbus.cyc,
o_WBs_BYTE_STB = self.pbus.sel,
o_WBs_WE = self.pbus.we,
o_WBs_STB = self.pbus.stb,
o_WBs_RD = Open(), # Read Enable.
o_WBs_WR_DAT = self.pbus.dat_w,
i_WBs_RD_DAT = self.pbus.dat_r,
i_WBs_ACK = self.pbus.ack,
# SDMA.
# -----
i_SDMA_Req = Signal(4),
i_SDMA_Sreq = Signal(4),
o_SDMA_Done = Open(),
o_SDMA_Active = Open(),
# Interrupts.
# -----------
i_FB_msg_out = self.interrupt,
i_FB_Int_Clr = Signal(8),
o_FB_Start = Open(),
i_FB_Busy = 0,
# Clocking.
# ---------
o_Sys_Clk0 = eos_s3_0_clk,
o_Sys_Clk0_Rst = eos_s3_0_rst,
o_Sys_Clk1 = eos_s3_1_clk,
o_Sys_Clk1_Rst = eos_s3_1_rst,
# Packet FIFO.
# ------------
i_Sys_PKfb_Clk = 0,
o_Sys_PKfb_Rst = Open(),
i_FB_PKfbData = Signal(32),
i_FB_PKfbPush = Signal(4),
i_FB_PKfbSOF = 0,
i_FB_PKfbEOF = 0,
o_FB_PKfbOverflow = Open(),
# Sensor.
# -------
o_Sensor_Int = Open(),
o_TimeStamp = Open(),
# SPI Master (APB).
# -----------------
o_Sys_Pclk = Open(),
o_Sys_Pclk_Rst = Open(),
i_Sys_PSel = 0,
i_SPIm_Paddr = Signal(16),
i_SPIm_PEnable = 0,
i_SPIm_PWrite = 0,
i_SPIm_PWdata = Signal(32),
o_SPIm_Prdata = Open(),
o_SPIm_PReady = Open(),
o_SPIm_PSlvErr = Open(),
# Misc.
# -----
i_Device_ID = 0xCAFE,
# FBIO Signals
o_FBIO_In = Open(),
o_FBIO_In_En = Open(),
o_FBIO_Out = Open(),
o_FBIO_Out_En = Open(),
# ???
io_SFBIO = Signal(14),
i_Device_ID_6S = 0,
i_Device_ID_4S = 0,
i_SPIm_PWdata_26S = 0,
i_SPIm_PWdata_24S = 0,
i_SPIm_PWdata_14S = 0,
i_SPIm_PWdata_11S = 0,
i_SPIm_PWdata_0S = 0,
i_SPIm_Paddr_8S = 0,
i_SPIm_Paddr_6S = 0,
i_FB_PKfbPush_1S = 0,
i_FB_PKfbData_31S = 0,
i_FB_PKfbData_21S = 0,
i_FB_PKfbData_19S = 0,
i_FB_PKfbData_9S = 0,
i_FB_PKfbData_6S = 0,
i_Sys_PKfb_ClkS = 0,
i_FB_BusyS = 0,
i_WB_CLKS = 0
)
def do_finalize(self):
self.specials += Instance("qlal4s3b_cell_macro", **self.cpu_params)
| [
"litex.soc.interconnect.wishbone.Interface"
] | [((1400, 1447), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)', 'adr_width': '(15)'}), '(data_width=32, adr_width=15)\n', (1418, 1447), False, 'from litex.soc.interconnect import wishbone\n')] |
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.gen import *
from litex.soc.interconnect import stream
from litedram.frontend import dma
def _inc(signal, modulo):
if modulo == 2**len(signal):
return signal.eq(signal + 1)
else:
return If(signal == (modulo - 1),
signal.eq(0)
).Else(
signal.eq(signal + 1)
)
class _LiteDRAMFIFOCtrl(Module):
def __init__(self, base, depth, read_threshold, write_threshold):
self.base = base
self.depth = depth
self.level = Signal(max=depth+1)
# # #
# To write buffer
self.writable = Signal()
self.write_address = Signal(max=depth)
# From write buffer
self.write = Signal()
# To read buffer
self.readable = Signal()
self.read_address = Signal(max=depth)
# From read buffer
self.read = Signal()
# # #
produce = self.write_address
consume = self.read_address
self.sync += [
If(self.write,
_inc(produce, depth)
),
If(self.read,
_inc(consume, depth)
),
If(self.write & ~self.read,
self.level.eq(self.level + 1),
).Elif(self.read & ~self.write,
self.level.eq(self.level - 1)
)
]
self.comb += [
self.writable.eq(self.level < write_threshold),
self.readable.eq(self.level > read_threshold)
]
class _LiteDRAMFIFOWriter(Module):
def __init__(self, data_width, port, ctrl):
self.sink = sink = stream.Endpoint([("data", data_width)])
# # #
self.submodules.writer = writer = dma.LiteDRAMDMAWriter(port, fifo_depth=32)
self.comb += [
writer.sink.valid.eq(sink.valid & ctrl.writable),
writer.sink.address.eq(ctrl.base + ctrl.write_address),
writer.sink.data.eq(sink.data),
If(writer.sink.valid & writer.sink.ready,
ctrl.write.eq(1),
sink.ready.eq(1)
)
]
class _LiteDRAMFIFOReader(Module):
def __init__(self, data_width, port, ctrl):
self.source = source = stream.Endpoint([("data", data_width)])
# # #
self.submodules.reader = reader = dma.LiteDRAMDMAReader(port, fifo_depth=32)
self.comb += [
reader.sink.valid.eq(ctrl.readable),
reader.sink.address.eq(ctrl.base + ctrl.read_address),
If(reader.sink.valid & reader.sink.ready,
ctrl.read.eq(1)
)
]
self.comb += reader.source.connect(source)
class LiteDRAMFIFO(Module):
def __init__(self, data_width, base, depth, write_port, read_port,
read_threshold=None, write_threshold=None):
self.sink = stream.Endpoint([("data", data_width)])
self.source = stream.Endpoint([("data", data_width)])
# # #
if read_threshold is None:
read_threshold = 0
if write_threshold is None:
write_threshold = depth
self.submodules.ctrl = _LiteDRAMFIFOCtrl(base, depth, read_threshold, write_threshold)
self.submodules.writer = _LiteDRAMFIFOWriter(data_width, write_port, self.ctrl)
self.submodules.reader = _LiteDRAMFIFOReader(data_width, read_port, self.ctrl)
self.comb += [
self.sink.connect(self.writer.sink),
self.reader.source.connect(self.source)
]
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((1686, 1725), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (1701, 1725), False, 'from litex.soc.interconnect import stream\n'), ((1784, 1826), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'dma.LiteDRAMDMAWriter', (['port'], {'fifo_depth': '(32)'}), '(port, fifo_depth=32)\n', (1805, 1826), False, 'from litedram.frontend import dma\n'), ((2285, 2324), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (2300, 2324), False, 'from litex.soc.interconnect import stream\n'), ((2383, 2425), 'litedram.frontend.dma.LiteDRAMDMAReader', 'dma.LiteDRAMDMAReader', (['port'], {'fifo_depth': '(32)'}), '(port, fifo_depth=32)\n', (2404, 2425), False, 'from litedram.frontend import dma\n'), ((2901, 2940), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (2916, 2940), False, 'from litex.soc.interconnect import stream\n'), ((2963, 3002), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (2978, 3002), False, 'from litex.soc.interconnect import stream\n')] |
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
_butterstick_r1d0_io = [
("clk30", 0, Pins("B12"), IOStandard("LVCMOS18")),
("rst_n", 0, Pins("R3"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("C13 D12 U2 T3 D13 E13 C16"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("U16"), IOStandard("SSTL135_I")),
("user_btn", 1, Pins("T17"), IOStandard("SSTL135_I")),
("led", 0,
#Subsignal("a", Pins("C13 D12 U2 T3 D13 E13 C16")),
Subsignal("c", Pins("T1 R1 U1")),
IOStandard("LVCMOS33")
),
#("serial", 0,
# Subsignal("rx", Pins("G3")),
# Subsignal("tx", Pins("F3")),
# IOStandard("LVCMOS18")
#),
("usb0", 0,
Subsignal("data", Pins("B9 C6 A7 E9 A8 D9 C10 C7")),
Subsignal("clk", Pins("B6")),
Subsignal("dir", Pins("A6")),
Subsignal("nxt", Pins("B8")),
Subsignal("stp", Pins("C8")),
#Subsignal("rst", Pins("C9")),
IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")
),
("eth_clk", 0,
Subsignal("tx", Pins("E15")),
Subsignal("rx", Pins("D11")),
IOStandard("LVCMOS33"),Misc("SLEWRATE=FAST"),
),
("eth", 0,
Subsignal("rst_n", Pins("B20")),
Subsignal("mdio", Pins("D16")),
Subsignal("mdc", Pins("A19")),
Subsignal("rx_data", Pins("A16 C17 B17 A17")),
Subsignal("tx_ctl", Pins("D15")),
Subsignal("rx_ctl", Pins("B18")),
Subsignal("tx_data", Pins("C15 B16 A18 B19")),
IOStandard("LVCMOS33"),Misc("SLEWRATE=FAST")
),
("ddram", 0,
Subsignal("a", Pins(
"G16 E19 E20 F16 F19 E16 F17 L20 "
"M20 E18 G18 D18 H18 C18 D17 G20 "),
IOStandard("SSTL135_I")),
Subsignal("ba", Pins("H16 F20 H20"), IOStandard("SSTL135_I"),),
Subsignal("ras_n", Pins("K18"), IOStandard("SSTL135_I")),
Subsignal("cas_n", Pins("J17"), IOStandard("SSTL135_I")),
Subsignal("we_n", Pins("G19"), IOStandard("SSTL135_I")),
Subsignal("cs_n", Pins("J20 J16"), IOStandard("SSTL135_I")),
Subsignal("dm", Pins("U20 L18"), IOStandard("SSTL135_I")),
Subsignal("dq", Pins(
"U19 T18 U18 R20 P18 P19 P20 N20 ",
"L19 L17 L16 R16 N18 R17 N17 P17 "),
IOStandard("SSTL135_I"),
Misc("TERMINATION=OFF")), # Misc("TERMINATION=75") Disabled to reduce heat
Subsignal("dqs_p", Pins("T19 N16"), IOStandard("SSTL135D_I"),
Misc("TERMINATION=OFF"),
Misc("DIFFRESISTOR=100")),
Subsignal("clk_p", Pins("C20 J19"), IOStandard("SSTL135D_I")),
Subsignal("cke", Pins("F18 J18"), IOStandard("SSTL135_I")),
Subsignal("odt", Pins("K20 H17"), IOStandard("SSTL135_I")),
Subsignal("reset_n", Pins("E17"), IOStandard("SSTL135_I")),
Subsignal("vccio", Pins("K16 K17 M19 M18 N19 T20"), IOStandard("SSTL135_II")),
#Subsignal("gnd", Pins(""), IOStandard("SSTL135_II")),
Misc("SLEWRATE=FAST")
),
("vccio_ctrl", 0,
Subsignal("pdm", Pins("V1 E11 T2")),
Subsignal("en", Pins("E12"))
),
]
_connectors = [
("SYZYGY1", {
# single ended
# diff pairs
"D0P":"E4", "D0N":"D5",
"D1P":"A4", "D1N":"A5",
"D2P":"C4", "D2N":"B4",
"D3P":"B2", "D3N":"C2",
"D4P":"A2", "D4N":"B1",
"D5P":"C1", "D5N":"D1",
"D6P":"F4", "D6N":"E3",
"D7P":"D2", "D7N":"E1",
}
),
("SYZYGY0", {
# single ended
"S0":"G2", "S1":"J3",
"S2":"F1", "S3":"K3",
"S4":"J4", "S5":"K2",
"S6":"J5", "S7":"J1",
"S8":"N2", "S9":"L3",
"S10":"M1", "S11":"L2",
"S12":"N3", "S13":"N4",
"S14":"M3", "S15":"P5",
"S16":"H1", "S17":"K5",
"S18":"K4", "S19":"K1",
"S20":"L4", "S21":"L1",
"S22":"L5", "S23":"M4",
"S24":"N1", "S25":"N5",
"S26":"P3", "S27":"P4",
"S28":"H2", "S29":"P1",
"S30":"G1", "S31":"P2",
# diff pairs
}
),
]
_uart_debug = [
("serial",0,
Subsignal("tx", Pins("SYZYGY1:D1P"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("SYZYGY1:D0P"), IOStandard("LVCMOS33")),
),
]
_i2c =[
("i2c",0,
Subsignal("sda", Pins("C14"), IOStandard("LVCMOS33")),
Subsignal("scl", Pins("E14"), IOStandard("LVCMOS33")),
)
]
_syzygy_boson = [
("boson", 0,
Subsignal("pwr_en", Pins("SYZYGY0:S24"), IOStandard("LVCMOS18")),
Subsignal("data", Pins("SYZYGY0:S27 SYZYGY0:S30 SYZYGY0:S9 SYZYGY0:S26 "
"SYZYGY0:S15 SYZYGY0:S4 SYZYGY0:S6 SYZYGY0:S17 "
"SYZYGY0:S3 SYZYGY0:S16 SYZYGY0:S11 SYZYGY0:S18 "
"SYZYGY0:S31 SYZYGY0:S25 SYZYGY0:S1 SYZYGY0:S12 "
"SYZYGY0:S8 SYZYGY0:S0 SYZYGY0:S14 SYZYGY0:S23 "
"SYZYGY0:S20 SYZYGY0:S22 SYZYGY0:S21 SYZYGY0:S10"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("clk", Pins("SYZYGY0:S28"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("vsync", Pins("SYZYGY0:S7"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("hsync", Pins("SYZYGY0:S5"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("valid", Pins("SYZYGY0:S29"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("tx", Pins("SYZYGY0:S19"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("rx", Pins("SYZYGY0:S13"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("reset", Pins("SYZYGY0:S2"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
#Subsignal("ext_sync", Pins("B18"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
),
]
class ButterStickPlatform(LatticePlatform):
default_clk_name = "clk_sys"
default_clk_period = 1e9 / 30e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5UM5G-85F-8BG381C", _butterstick_r1d0_io, _connectors, toolchain="trellis", **kwargs)
self.toolchain.build_template[2] += ' --compress'
self.toolchain.build_template[1] += ' --log {build_name}.tim'
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
| [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((6126, 6250), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5UM5G-85F-8BG381C"""', '_butterstick_r1d0_io', '_connectors'], {'toolchain': '"""trellis"""'}), "(self, 'LFE5UM5G-85F-8BG381C', _butterstick_r1d0_io,\n _connectors, toolchain='trellis', **kwargs)\n", (6150, 6250), False, 'from litex.build.lattice import LatticePlatform\n'), ((6428, 6471), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (6455, 6471), False, 'from litex.build.lattice import LatticePlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import sys
import argparse
from migen import *
import radiona_ulx3s
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict
from litex.soc.integration.common import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.integration.soc import *
from litex.soc.cores.bitbang import *
from litex.soc.cores.gpio import GPIOTristate
from litex.soc.cores.cpu import CPUS
from litescope import LiteScopeAnalyzer
##############
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.led import LedChaser
from litex.soc.cores.gpio import GPIOOut
from litex.soc.interconnect import *
from litex.soc.integration.soc import SoCRegion
##############
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst.
("sys_clk", 0, Pins(1)),
("sys_rst", 0, Pins(1)),
# Serial.
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
("spi_sclk", 0, Pins(1)),
("spi_cs", 0, Pins(1)),
("spi_sdo", 0, Pins(1))
]
# Platform -----------------------------------------------------------------------------------------
class Platform(SimPlatform):
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
# Clk / Rst
clk25 = platform.request("clk25")
rst = platform.request("rst")
# PLL
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(rst | self.rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# Prevent ESP32 from resetting FPGA
self.comb += platform.request("wifi_gpio0").eq(1)
# Simulation SoC -----------------------------------------------------------------------------------
class MySoC(SoCCore):
def __init__(self,
with_analyzer = False,
with_led_chaser = False,
with_gpio = False,
with_wfg = False,
sim_debug = False,
trace_reset_on = False,
sys_clk_freq = int(50e6),
simulate = False,
device = "LFE5U-85F",
revision = "2.0",
toolchain = "trellis",
**kwargs):
if simulate:
platform = Platform()
else:
platform = radiona_ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "My LiteX SoC",
**kwargs)
# CRG --------------------------------------------------------------------------------------
if simulate:
self.submodules.crg = CRG(platform.request("sys_clk"))
else:
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser: # TODO simulation
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Simulation debugging ----------------------------------------------------------------------
if simulate:
if sim_debug:
platform.add_debug(self, reset=1 if trace_reset_on else 0)
else:
self.comb += platform.trace.eq(1)
if with_wfg:
# Add a wb port for external verilog module
wfg = wishbone.Interface(bursting=False)
#self.bus.add_slave(name="wfg", slave=wfg, region=SoCRegion(origin=0x30000000, size=0x0100000)) #, cached=False)) TODO?
self.add_memory_region("wfg", origin=0x30000000, length=0x0100000, type="cached") # linker
self.add_wb_slave(address=0x30000000, interface=wfg)
if simulate:
spi_sclk = platform.request("spi_sclk")
spi_cs = platform.request("spi_cs")
spi_sdo = platform.request("spi_sdo")
else:
oled_spi = platform.request("oled_spi")
oled_ctl = platform.request("oled_ctl")
spi_sclk = oled_spi.clk
spi_cs = oled_ctl.csn
spi_sdo = oled_spi.mosi
platform.add_source("../../../design/wfg_top/rtl/wfg_top.sv")
platform.add_source("../../../design/wfg_stim_sine/rtl/*.sv")
platform.add_source("../../../design/wfg_drive_spi/rtl/*.sv")
platform.add_source("../../../design/wfg_core/rtl/*.sv")
self.specials += Instance("wfg_top",
i_io_wbs_clk = self.crg.cd_sys.clk,
i_io_wbs_rst = self.crg.cd_sys.rst,
i_io_wbs_adr = (wfg.adr << 2) & 0x000000FF , # add two zeros
i_io_wbs_datwr = wfg.dat_w,
o_io_wbs_datrd = wfg.dat_r,
i_io_wbs_we = wfg.we,
i_io_wbs_stb = (((wfg.adr<<2)[24:32] == 0x30) & wfg.stb),
o_io_wbs_ack = wfg.ack,
i_io_wbs_cyc = wfg.cyc,
o_wfg_drive_spi_sclk_o = spi_sclk,
o_wfg_drive_spi_cs_no = spi_cs,
o_wfg_drive_spi_sdo_o = spi_sdo
)
# Build --------------------------------------------------------------------------------------------
def generate_gtkw_savefile(builder, vns, trace_fst):
from litex.build.sim import gtkwave as gtkw
dumpfile = os.path.join(builder.gateware_dir, "sim.{}".format("fst" if trace_fst else "vcd"))
savefile = os.path.join(builder.gateware_dir, "sim.gtkw")
soc = builder.soc
with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile) as save:
save.clocks()
save.fsm_states(soc)
if "main_ram" in soc.bus.slaves.keys():
save.add(soc.bus.slaves["main_ram"], mappers=[gtkw.wishbone_sorter(), gtkw.wishbone_colorer()])
if hasattr(soc, "sdrphy"):
# all dfi signals
save.add(soc.sdrphy.dfi, mappers=[gtkw.dfi_sorter(), gtkw.dfi_in_phase_colorer()])
# each phase in separate group
with save.gtkw.group("dfi phaseX", closed=True):
for i, phase in enumerate(soc.sdrphy.dfi.phases):
save.add(phase, group_name="dfi p{}".format(i), mappers=[
gtkw.dfi_sorter(phases=False),
gtkw.dfi_in_phase_colorer(),
])
# only dfi command/data signals
def dfi_group(name, suffixes):
save.add(soc.sdrphy.dfi, group_name=name, mappers=[
gtkw.regex_filter(gtkw.suffixes2re(suffixes)),
gtkw.dfi_sorter(),
gtkw.dfi_per_phase_colorer(),
])
dfi_group("dfi commands", ["cas_n", "ras_n", "we_n"])
dfi_group("dfi commands", ["wrdata"])
dfi_group("dfi commands", ["wrdata_mask"])
dfi_group("dfi commands", ["rddata"])
def add_args(parser):
builder_args(parser)
soc_core_args(parser)
verilator_build_args(parser)
soc_group = parser.add_argument_group(title="SoC options")
soc_group.add_argument("--rom-init", default=None, help="ROM init file (.bin or .json).")
soc_group.add_argument("--with-led-chaser", action="store_true", help="Enable LED chaser.")
soc_group.add_argument("--with-gpio", action="store_true", help="Enable Tristate GPIO (32 pins).")
soc_group.add_argument("--with-wfg", action="store_true", help="Enable the waveform generator module")
sim_group = parser.add_argument_group(title="Simulation options")
sim_group.add_argument("--sim-debug", action="store_true", help="Add simulation debugging modules.")
sim_group.add_argument("--gtkwave-savefile", action="store_true", help="Generate GTKWave savefile.")
sim_group.add_argument("--non-interactive", action="store_true", help="Run simulation without user input.")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--simulate", action="store_true", help="Run simulation")
target_group.add_argument("--build", action="store_true", help="Build design")
target_group.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
target_group.add_argument("--device", default="LFE5U-85F", help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).")
target_group.add_argument("--revision", default="2.0", help="Board revision (2.0 or 1.7).")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC Simulation utility")
add_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
verilator_build_kwargs = verilator_build_argdict(args)
trellis_build_kwargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
sys_clk_freq = int(float(args.sys_clk_freq))
if args.simulate:
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
# UART.
if args.simulate and soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
# ROM.
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, endianness=cpu.endianness)
# SoC ------------------------------------------------------------------------------------------
soc = MySoC(
with_led_chaser = args.with_led_chaser,
with_gpio = args.with_gpio,
with_wfg = args.with_wfg,
sim_debug = args.sim_debug,
trace_reset_on = int(float(args.trace_start)) > 0 or int(float(args.trace_end)) > 0,
sys_clk_freq = sys_clk_freq,
simulate = args.simulate,
**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder_kwargs["compile_software"] = True # TODO this is needed for the libraries
builder = Builder(soc, **builder_kwargs)
if args.simulate:
def pre_run_callback(vns):
if args.trace:
generate_gtkw_savefile(builder, vns, args.trace_fst)
builder.build(
sim_config = sim_config,
interactive = not args.non_interactive,
pre_run_callback = pre_run_callback,
**verilator_build_kwargs,
)
elif args.build:
builder.build(**trellis_build_kwargs)
if __name__ == "__main__":
main()
| [
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"litex.build.lattice.trellis.trellis_argdict",
"litex.build.sim.gtkwave.wishbone_sorter",
"litex.build.sim.gtkwave.wishbone_colorer",
"litex.build.sim.verilator.verilator_build_argdict",
"litex.build.sim.gtkwave.dfi_sorter",
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#!/usr/bin/env python3
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
CTRL_START = (1 << 0)
CTRL_LENGTH = (1 << 8)
STATUS_DONE = (1 << 0)
STATUS_ONGOING = (1 << 0)
# Registers
READ_ID = 0x9F
READ = 0x03
WREN = 0x06
WRDI = 0x04
PP = 0x02
SE = 0xD8
BE = 0xC7
RDSR = 0x05
WRSR = 0x01
RDNVCR = 0xB5
WRNVCR = 0xB1
# Flags
WIP = 0x01
def format_mosi(cmd, addr=None, data=0):
if addr is None:
return (cmd<<32) | (data<<24)
else:
return (cmd <<32) | (addr<<8) | data
class SPIFlash:
def __init__(self, regs):
self.regs = regs
def spi_xfer(self, length, mosi):
self.regs.spiflash_spi_mosi.write(mosi)
self.regs.spiflash_spi_control.write((length*CTRL_LENGTH) | CTRL_START)
while not (self.regs.spiflash_spi_status.read() & STATUS_DONE):
pass
return self.regs.spiflash_spi_miso.read()
def read_id(self):
return (self.spi_xfer(32, format_mosi(cmd=READ_ID))) & 0xffffff
def write_enable(self):
self.spi_xfer(8, format_mosi(cmd=WREN))
def write_disable(self):
self.spi_xfer(8, format_mosi(cmd=WRDI))
def read_status(self):
return (self.spi_xfer(16, format_mosi(cmd=RDSR))) & 0xff
def write_status(self, value):
self.spi_xfer(16, format_mosi(cmd=WRSR, data=value))
def erase_sector(self, addr):
self.spi_xfer(32, format_mosi(cmd=SE, addr=addr))
def read_sector_lock(self, addr):
return (self.spi_xfer(40, format_mosi(cmd=RDSR, addr=addr))) & 0xff
def write_sector_lock(self, addr, byte):
self.spi_xfer(40, format_mosi(cmd=WRSR, addr=addr, data=byte))
def read(self, addr):
return (self.spi_xfer(40, format_mosi(cmd=READ, addr=addr))) & 0xff
def write(self, addr, byte):
self.spi_xfer(40, format_mosi(cmd=PP, addr=addr, data=byte))
def read_nvcr(self):
return (self.spi_xfer(24, format_mosi(cmd=RDNVCR))) & 0xffff
def write_nvcr(self, data):
self.spi_xfer(24, format_mosi(cmd=WRNVCR, data=data))
spiflash = SPIFlash(wb.regs)
print("{:08x}".format(spiflash.read_id()))
for i in range(16):
print("{:02x}".format(spiflash.read(i)))
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((74, 88), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (86, 88), False, 'from litex import RemoteClient\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Direct Memory Access (DMA) reader and writer modules."""
from migen import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
from litedram.common import LiteDRAMNativePort
from litedram.frontend.axi import LiteDRAMAXIPort
# LiteDRAMDMAReader --------------------------------------------------------------------------------
class LiteDRAMDMAReader(Module, AutoCSR):
"""Read data from DRAM memory.
For every address written to the sink, one DRAM word will be produced on
the source.
Parameters
----------
port : port
Port on the DRAM memory controller to read from (Native or AXI).
fifo_depth : int
How many request results the output FIFO can contain (and thus how many
read requests can be outstanding at once).
fifo_buffered : bool
Implement FIFO in Block Ram.
Attributes
----------
sink : Record("address")
Sink for DRAM addresses to be read.
source : Record("data")
Source for DRAM word results from reading.
rsv_level: Signal()
FIFO reservation level counter
"""
def __init__(self, port, fifo_depth=16, fifo_buffered=False):
assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
self.port = port
self.sink = sink = stream.Endpoint([("address", port.address_width)])
self.source = source = stream.Endpoint([("data", port.data_width)])
# # #
# Native / AXI selection
is_native = isinstance(port, LiteDRAMNativePort)
is_axi = isinstance(port, LiteDRAMAXIPort)
if is_native:
(cmd, rdata) = port.cmd, port.rdata
elif is_axi:
(cmd, rdata) = port.ar, port.r
else:
raise NotImplementedError
# Request issuance -------------------------------------------------------------------------
request_enable = Signal()
request_issued = Signal()
if is_native:
self.comb += cmd.we.eq(0)
self.comb += [
cmd.addr.eq(sink.address),
cmd.valid.eq(sink.valid & request_enable),
sink.ready.eq(cmd.ready & request_enable),
request_issued.eq(cmd.valid & cmd.ready)
]
# FIFO reservation level counter -----------------------------------------------------------
# incremented when data is planned to be queued
# decremented when data is dequeued
data_dequeued = Signal()
self.rsv_level = rsv_level = Signal(max=fifo_depth+1)
self.sync += [
If(request_issued,
If(~data_dequeued, rsv_level.eq(self.rsv_level + 1))
).Elif(data_dequeued,
rsv_level.eq(rsv_level - 1)
)
]
self.comb += request_enable.eq(rsv_level != fifo_depth)
# FIFO -------------------------------------------------------------------------------------
fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)
self.submodules += fifo
self.comb += [
rdata.connect(fifo.sink, omit={"id", "resp"}),
fifo.source.connect(source),
data_dequeued.eq(source.valid & source.ready)
]
def add_csr(self):
self._base = CSRStorage(32)
self._length = CSRStorage(32)
self._start = CSR()
self._done = CSRStatus()
self._loop = CSRStorage()
# # #
shift = log2_int(self.port.data_width//8)
base = Signal(self.port.address_width)
offset = Signal(self.port.address_width)
length = Signal(self.port.address_width)
self.comb += [
base.eq(self._base.storage[shift:]),
length.eq(self._length.storage[shift:]),
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
self._done.status.eq(1),
If(self._start.re,
NextValue(offset, 0),
NextState("RUN"),
)
)
fsm.act("RUN",
self.sink.valid.eq(1),
self.sink.address.eq(base + offset),
If(self.sink.ready,
NextValue(offset, offset + 1),
If(offset == (length - 1),
If(self._loop.storage,
NextValue(offset, 0)
).Else(
NextState("IDLE")
)
)
)
)
# LiteDRAMDMAWriter --------------------------------------------------------------------------------
class LiteDRAMDMAWriter(Module, AutoCSR):
"""Write data to DRAM memory.
Parameters
----------
port : port
Port on the DRAM memory controller to write to (Native or AXI).
fifo_depth : int
How many requests the input FIFO can contain (and thus how many write
requests can be outstanding at once).
fifo_buffered : bool
Implement FIFO in Block Ram.
Attributes
----------
sink : Record("address", "data")
Sink for DRAM addresses and DRAM data word to be written too.
"""
def __init__(self, port, fifo_depth=16, fifo_buffered=False):
assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
self.port = port
self.sink = sink = stream.Endpoint([("address", port.address_width),
("data", port.data_width)])
# # #
# Native / AXI selection -------------------------------------------------------------------
is_native = isinstance(port, LiteDRAMNativePort)
is_axi = isinstance(port, LiteDRAMAXIPort)
if is_native:
(cmd, wdata) = port.cmd, port.wdata
elif is_axi:
(cmd, wdata) = port.aw, port.w
else:
raise NotImplementedError
# FIFO -------------------------------------------------------------------------------------
fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)
self.submodules += fifo
if is_native:
self.comb += cmd.we.eq(1)
self.comb += [
cmd.addr.eq(sink.address),
cmd.valid.eq(fifo.sink.ready & sink.valid),
sink.ready.eq(fifo.sink.ready & cmd.ready),
fifo.sink.valid.eq(sink.valid & cmd.ready),
fifo.sink.data.eq(sink.data)
]
if is_native:
self.comb += wdata.we.eq(2**(port.data_width//8)-1)
if is_axi:
self.comb += wdata.strb.eq(2**(port.data_width//8)-1)
self.comb += [
wdata.valid.eq(fifo.source.valid),
fifo.source.ready.eq(wdata.ready),
wdata.data.eq(fifo.source.data)
]
def add_csr(self):
self._sink = self.sink
self.sink = stream.Endpoint([("data", self.port.data_width)])
self._base = CSRStorage(32)
self._length = CSRStorage(32)
self._start = CSR()
self._done = CSRStatus()
self._loop = CSRStorage()
# # #
shift = log2_int(self.port.data_width//8)
base = Signal(self.port.address_width)
offset = Signal(self.port.address_width)
length = Signal(self.port.address_width)
self.comb += [
base.eq(self._base.storage[shift:]),
length.eq(self._length.storage[shift:]),
]
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
self._done.status.eq(1),
If(self._start.re,
NextValue(offset, 0),
NextState("RUN"),
)
)
fsm.act("RUN",
self._sink.valid.eq(self.sink.valid),
self._sink.data.eq(self.sink.data),
self._sink.address.eq(base + offset),
self.sink.ready.eq(self._sink.ready),
If(self.sink.valid & self.sink.ready,
NextValue(offset, offset + 1),
If(offset == (length - 1),
If(self._loop.storage,
NextValue(offset, 0)
).Else(
NextState("IDLE")
)
)
)
)
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((1573, 1623), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', port.address_width)]"], {}), "([('address', port.address_width)])\n", (1588, 1623), False, 'from litex.soc.interconnect import stream\n'), ((1655, 1699), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', port.data_width)]"], {}), "([('data', port.data_width)])\n", (1670, 1699), False, 'from litex.soc.interconnect import stream\n'), ((3215, 3286), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[('data', port.data_width)]", 'fifo_depth', 'fifo_buffered'], {}), "([('data', port.data_width)], fifo_depth, fifo_buffered)\n", (3230, 3286), False, 'from litex.soc.interconnect import stream\n'), ((5606, 5683), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', port.address_width), ('data', port.data_width)]"], {}), "([('address', port.address_width), ('data', port.data_width)])\n", (5621, 5683), False, 'from litex.soc.interconnect import stream\n'), ((6259, 6330), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (["[('data', port.data_width)]", 'fifo_depth', 'fifo_buffered'], {}), "([('data', port.data_width)], fifo_depth, fifo_buffered)\n", (6274, 6330), False, 'from litex.soc.interconnect import stream\n'), ((7124, 7173), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', self.port.data_width)]"], {}), "([('data', self.port.data_width)])\n", (7139, 7173), False, 'from litex.soc.interconnect import stream\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.platforms import arty
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.build.generic_platform import Subsignal, Pins, Misc, IOStandard
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.spi import SPIMaster
from litex.soc.cores.gpio import GPIOTristate, GPIOIn
from litedram.modules import MT41K128M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
from litescope import LiteScopeAnalyzer
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_eth = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset") | self.rst)
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_eth, 25e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
self.comb += platform.request("eth_ref_clk").eq(self.cd_eth.clk)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self,
variant="a7-35",
toolchain="vivado",
sys_clk_freq=int(100e6),
with_ethernet=False,
with_etherbone=False,
eth_ip="192.168.1.50",
eth_dynamic_ip=False,
ident_version=True,
analyzer_csv="analyzer.csv",
**kwargs):
platform = arty.Platform(variant=variant, toolchain=toolchain)
kwargs["integrated_rom_size"] = 0x10000 if with_etherbone else 0x8000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Arty A7",
ident_version = ident_version,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K128M16(sys_clk_freq, "1:4"),
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
_dws1000_ardu_io = [
("dw1000_spi", 0,
Subsignal("clk", Pins("ck_io:ck_io13")),
Subsignal("mosi", Pins("ck_io:ck_io11")),
Subsignal("cs_n", Pins("ck_io:ck_io10")),
Subsignal("miso", Pins("ck_io:ck_io12")),
Subsignal("pha", Pins("ck_io:ck_io0"), Misc("PULLDOWN True")),
Subsignal("pol", Pins("ck_io:ck_io1"), Misc("PULLDOWN True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("dw1000_led", 0, Pins("ck_io:ck_io3"), IOStandard("LVCMOS33")), # TX LED on the DWS1000 module
("dw1000_led", 1, Pins("ck_io:ck_io4"), IOStandard("LVCMOS33")), # RX LED on the DWS1000 module
("dw1000_info", 0,
Subsignal("exton", Pins("ck_io:ck_a0")),
Subsignal("wakeup", Pins("ck_io:ck_io9")),
Subsignal("irq", Pins("ck_io:ck_io8")),
IOStandard("LVCMOS33"),
),
("dw1000_rstn", 0,
Pins("ck_io:ck_io7"),
IOStandard("LVCMOS33"),
),
]
platform.add_extension(_dws1000_ardu_io)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("dw1000_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
self.submodules.dw1000_rstn = GPIOTristate(platform.request("dw1000_rstn", 0))
self.add_csr("dw1000_rstn")
self.submodules.dw1000_info = GPIOIn(platform.request("dw1000_info"))
self.add_csr("dw1000_info")
# SPI with LiteScope
self.add_spi_master()
print(dir(self.cpu.ibus))
analyzer_signals = [
self.spi_master._control.storage,
self.spi_master._status.status,
self.spi_master._cs.storage,
self.spi_master.mosi,
self.spi_master.miso,
self.spi_master.pads.clk,
self.spi_master.pads.cs_n,
self.spi_master.pads.mosi,
self.spi_master.pads.miso,
self.dw1000_rstn._oe.storage,
self.dw1000_rstn._in.status,
self.dw1000_rstn._out.storage,
self.dw1000_info._in.status,
self.cpu.ibus.adr,
self.cpu.ibus.stb,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=1024,
clock_domain="sys",
csr_csv=analyzer_csv
)
self.add_csr("analyzer")
def add_spi_master(self):
self.submodules.spi_master = SPIMaster(
pads=self.platform.request("dw1000_spi"),
data_width=8,
sys_clk_freq=self.sys_clk_freq,
spi_clk_freq=2e6,
manual_cs=True)
self.spi_master.add_csr(with_loopback=True)
self.spi_master.add_clk_divider()
self.add_csr("spi_master")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Flash bitstream")
parser.add_argument("--variant", default="a7-35", help="Board variant: a7-35 (default) or a7-100")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
sdopts = parser.add_mutually_exclusive_group()
sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
parser.add_argument("--analyzer-csv", default="analyzer.csv", type=str, help="Analyzer csv file")
builder_args(parser)
soc_sdram_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
analyzer_csv = args.analyzer_csv,
**soc_sdram_argdict(args)
)
if args.with_spi_sdcard or args.with_sdcard:
soc.platform.add_extension(arty._sdcard_pmod_io)
if args.with_spi_sdcard:
soc.add_spi_sdcard()
if args.with_sdcard:
soc.add_sdcard()
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
| [
"litex.build.generic_platform.Misc",
"litex.build.generic_platform.Pins",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.build.generic_platform.IOStandard"
] | [((7972, 8031), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Arty A7"""'}), "(description='LiteX SoC on Arty A7')\n", (7995, 8031), False, 'import argparse\n'), ((9856, 9881), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (9873, 9881), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((2694, 2745), 'litex_boards.platforms.arty.Platform', 'arty.Platform', ([], {'variant': 'variant', 'toolchain': 'toolchain'}), '(variant=variant, toolchain=toolchain)\n', (2707, 2745), False, 'from litex_boards.platforms import arty\n'), ((7286, 7380), 'litescope.LiteScopeAnalyzer', 'LiteScopeAnalyzer', (['analyzer_signals'], {'depth': '(1024)', 'clock_domain': '"""sys"""', 'csr_csv': 'analyzer_csv'}), "(analyzer_signals, depth=1024, clock_domain='sys', csr_csv\n =analyzer_csv)\n", (7303, 7380), False, 'from litescope import LiteScopeAnalyzer\n'), ((10725, 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#!/usr/bin/env python3
import time
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
print("Reboot...")
wb.regs.gpio1_out.write(1)
time.sleep(0.5)
wb.regs.gpio1_out.write(0)
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((74, 88), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (86, 88), False, 'from litex import RemoteClient\n'), ((153, 168), 'time.sleep', 'time.sleep', (['(0.5)'], {}), '(0.5)\n', (163, 168), False, 'import time\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex_boards.platforms import lpddr4_test_board
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT53E256M16D1
from litedram.phy import lpddr4
from liteeth.phy import LiteEthS7PHYRGMII
from litex.soc.cores.hyperbus import HyperRAM
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, iodelay_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys8x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
# # #
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq)
pll.create_clkout(self.cd_sys8x, 8 * sys_clk_freq)
pll.create_clkout(self.cd_idelay, iodelay_clk_freq)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
with_led_chaser=True, **kwargs):
platform = lpddr4_test_board.Platform()
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on LPDDR4 Test Board",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, iodelay_clk_freq=iodelay_clk_freq)
# LDDR4 SDRAM ------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = lpddr4.K7LPDDR4PHY(platform.request("lpddr4"),
iodelay_clk_freq = iodelay_clk_freq,
sys_clk_freq = sys_clk_freq,
)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT53E256M16D1(sys_clk_freq, "1:8"),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = 256,
)
# HyperRAM ---------------------------------------------------------------------------------
if with_hyperram:
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
# SD Card ----------------------------------------------------------------------------------
if with_sdcard:
self.add_sdcard()
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
# Traces between PHY and FPGA introduce ignorable delays of ~0.165ns +/- 0.015ns.
# PHY chip does not introduce delays on TX (FPGA->PHY), however it includes 1.2ns
# delay for RX CLK so we only need 0.8ns to match the desired 2ns.
self.submodules.ethphy = LiteEthS7PHYRGMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"),
rx_delay = 0.8e-9,
)
if with_ethernet:
self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# UartBone ---------------------------------------------------------------------------------
if with_uartbone:
self.add_uartbone("serial", baudrate=1e6)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on LPDDR4 Test Board")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--load", action="store_true", help="Load bitstream.")
target_group.add_argument("--flash", action="store_true", help="Flash bitstream.")
target_group.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.")
target_group.add_argument("--iodelay-clk-freq", default=200e6, help="IODELAYCTRL frequency.")
ethopts = target_group.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone.")
target_group.add_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.")
target_group.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.")
target_group.add_argument("--with-hyperram", action="store_true", help="Add HyperRAM.")
target_group.add_argument("--with-sdcard", action="store_true", help="Add SDCard.")
target_group.add_argument("--with-jtagbone", action="store_true", help="Add JTAGBone.")
target_group.add_argument("--with-uartbone", action="store_true", help="Add UartBone on 2nd serial.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
iodelay_clk_freq = int(float(args.iodelay_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
with_hyperram = args.with_hyperram,
with_sdcard = args.with_sdcard,
with_jtagbone = args.with_jtagbone,
with_uartbone = args.with_uartbone,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
vns = builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash:
prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash"))
if __name__ == "__main__":
main()
| [
"litex.soc.integration.soc.SoCRegion",
"litex.soc.integration.soc.LiteXSoCArgumentParser",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((5282, 5350), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on LPDDR4 Test Board"""'}), "(description='LiteX SoC on LPDDR4 Test Board')\n", (5304, 5350), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((6884, 6909), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (6901, 6909), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((2014, 2042), 'litex_boards.platforms.lpddr4_test_board.Platform', 'lpddr4_test_board.Platform', ([], {}), '()\n', (2040, 2042), False, 'from litex_boards.platforms import lpddr4_test_board\n'), ((7634, 7660), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (7654, 7660), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((2953, 2987), 'litedram.modules.MT53E256M16D1', 'MT53E256M16D1', (['sys_clk_freq', '"""1:8"""'], {}), "(sys_clk_freq, '1:8')\n", (2966, 2987), False, 'from litedram.modules import MT53E256M16D1\n'), ((3402, 3451), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(536870912)', 'size': '(8 * 1024 * 1024)'}), '(origin=536870912, size=8 * 1024 * 1024)\n', (3411, 3451), False, 'from litex.soc.integration.soc import SoCRegion\n')] |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO
def framer_params():
return [
("x_start", 16),
("y_start", 16),
("x_stop", 16),
("y_stop", 16),
]
class Framer(Module, AutoCSR):
def __init__(self):
self.sink = sink = Endpoint([("data", 32)])
self.params = params = Endpoint(framer_params())
self.hsync = hsync = Signal()
self.vsync = vsync = Signal()
# VGA output
self.red = red = Signal(8)
self.green = green = Signal(8)
self.blue = blue = Signal(8)
self.data_valid = data_valid = Signal()
# parameters
pixel_counter = Signal(14)
line_counter = Signal(14)
h_det = EdgeDetect(mode="fall", input_cd="video", output_cd="video")
v_det = EdgeDetect(mode="fall", input_cd="video", output_cd="video")
self.submodules += h_det, v_det
self.comb += [
h_det.i.eq(hsync),
v_det.i.eq(vsync),
]
self.comb += [
If((line_counter >= params.y_start) & (line_counter < params.y_stop),
If((pixel_counter >= params.x_start) & (pixel_counter < params.x_stop),
sink.ready.eq(1)
)
)
]
self.sync.video += [
# Default values
red.eq(0),
green.eq(0),
blue.eq(0),
data_valid.eq(0),
# Show pixels
If((line_counter >= params.y_start) & (line_counter < params.y_stop),
If((pixel_counter >= params.x_start) & (pixel_counter < params.x_stop),
data_valid.eq(1),
If(sink.valid,
red.eq(sink.data[0:8]),
green.eq(sink.data[8:16]),
blue.eq(sink.data[16:24])
).Else(
red.eq(0xFF),
green.eq(0x77),
blue.eq(0xFF)
)
)
),
# Horizontal timing for one line
pixel_counter.eq(pixel_counter + 1),
If(h_det.o,
pixel_counter.eq(0),
line_counter.eq(line_counter + 1),
),
If(v_det.o,
line_counter.eq(0),
)
] | [
"litex.soc.interconnect.stream.Endpoint"
] | [((558, 582), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 32)]"], {}), "([('data', 32)])\n", (566, 582), False, 'from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO\n'), ((1015, 1075), 'rtl.edge_detect.EdgeDetect', 'EdgeDetect', ([], {'mode': '"""fall"""', 'input_cd': '"""video"""', 'output_cd': '"""video"""'}), "(mode='fall', input_cd='video', output_cd='video')\n", (1025, 1075), False, 'from rtl.edge_detect import EdgeDetect\n'), ((1092, 1152), 'rtl.edge_detect.EdgeDetect', 'EdgeDetect', ([], {'mode': '"""fall"""', 'input_cd': '"""video"""', 'output_cd': '"""video"""'}), "(mode='fall', input_cd='video', output_cd='video')\n", (1102, 1152), False, 'from rtl.edge_detect import EdgeDetect\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2015 <NAME> <<EMAIL>>
# Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# Copyright (c) 2016-2019 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
CSR-2 bus
=========
The CSR-2 bus is a low-bandwidth, resource-sensitive bus designed for accessing
the configuration and status registers of cores from software.
"""
from functools import reduce
from operator import or_
from migen import *
from migen.fhdl.specials import Special
from migen.genlib.record import *
from migen.genlib.misc import chooser
from migen.util.misc import xdir
from litex.soc.interconnect import csr
from litex.soc.interconnect.csr import CSRStorage
# CSR Definition -----------------------------------------------------------------------------------
_layout = [
("adr", "address_width", DIR_M_TO_S),
("we", 1, DIR_M_TO_S),
("dat_w", "data_width", DIR_M_TO_S),
("dat_r", "data_width", DIR_S_TO_M)
]
class Interface(Record):
def __init__(self, data_width=8, address_width=14, alignment=32):
self.data_width = data_width
self.address_width = address_width
self.alignment = alignment
Record.__init__(self, set_layout_parameters(_layout,
data_width = data_width,
address_width = address_width))
self.adr.reset_less = True
self.dat_w.reset_less = True
self.dat_r.reset_less = True
@classmethod
def like(self, other):
return Interface(len(other.dat_w),
len(other.adr))
def write(self, adr, dat):
yield self.adr.eq(adr)
yield self.dat_w.eq(dat)
yield self.we.eq(1)
yield
yield self.we.eq(0)
def read(self, adr):
yield self.adr.eq(adr)
yield
yield
return (yield self.dat_r)
# CSR Interconnect ---------------------------------------------------------------------------------
class Interconnect(Module):
def __init__(self, master, slaves):
self.comb += master.connect(*slaves)
class InterconnectShared(Module):
def __init__(self, masters, slaves):
intermediate = Interface.like(masters[0])
self.comb += [
intermediate.adr.eq(reduce(or_, [masters[i].adr for i in range(len(masters))])),
intermediate.we.eq(reduce(or_, [masters[i].we for i in range(len(masters))])),
intermediate.dat_w.eq(reduce(or_, [masters[i].dat_w for i in range(len(masters))]))
]
for i in range(len(masters)):
self.comb += masters[i].dat_r.eq(intermediate.dat_r)
self.comb += intermediate.connect(*slaves)
# CSR SRAM -----------------------------------------------------------------------------------------
class SRAM(Module):
def __init__(self, mem_or_size, address, port=None, read_only=None, init=None, bus=None, paging=0x800, soc_bus_data_width=32):
if bus is None:
bus = Interface()
self.bus = bus
aligned_paging = paging//(soc_bus_data_width//8)
data_width = len(self.bus.dat_w)
if isinstance(mem_or_size, Memory):
mem = mem_or_size
else:
mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
mem_size = int(mem.width*mem.depth/8)
csrw_per_memw = (mem.width + data_width - 1)//data_width
word_bits = log2_int(csrw_per_memw)
page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
if page_bits:
self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
print("WARNING: SRAM CSR memory will require paged access.")
else:
self._page = None
if read_only is None:
if hasattr(mem, "bus_read_only"):
read_only = mem.bus_read_only
else:
read_only = False
# # #
if port is None:
port = mem.get_port(write_capable=not read_only)
self.specials += mem
if isinstance(port, Special):
self.specials += port
sel = Signal()
sel_r = Signal()
self.sync += sel_r.eq(sel)
self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
if word_bits:
word_index = Signal(word_bits, reset_less=True)
word_expanded = Signal(csrw_per_memw*data_width)
self.sync += word_index.eq(self.bus.adr[:word_bits])
self.comb += [
word_expanded.eq(port.dat_r),
If(sel_r,
chooser(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse=True)
)
]
if not read_only:
wregs = []
for i in range(csrw_per_memw-1):
wreg = Signal(data_width, reset_less=True)
self.sync += If(sel & self.bus.we & (self.bus.adr[:word_bits] == i), wreg.eq(self.bus.dat_w))
wregs.append(wreg)
memword_chunks = [self.bus.dat_w] + list(reversed(wregs))
self.comb += [
port.we.eq(sel & self.bus.we & (self.bus.adr[:word_bits] == csrw_per_memw - 1)),
port.dat_w.eq(Cat(*memword_chunks))
]
else:
self.comb += If(sel_r, self.bus.dat_r.eq(port.dat_r))
if not read_only:
self.comb += [
port.we.eq(sel & self.bus.we),
port.dat_w.eq(self.bus.dat_w)
]
if self._page is None:
self.comb += port.adr.eq(self.bus.adr[word_bits:word_bits+len(port.adr)])
else:
pv = self._page.storage
self.comb += port.adr.eq(Cat(self.bus.adr[word_bits:word_bits+len(port.adr)-len(pv)], pv))
def get_csrs(self):
if self._page is None:
return []
else:
return [self._page]
# CSR Bank -----------------------------------------------------------------------------------------
class CSRBank(csr.GenericBank):
def __init__(self, description, address=0, bus=None, paging=0x800, ordering="big", soc_bus_data_width=32):
if bus is None:
bus = Interface()
self.bus = bus
aligned_paging = paging//(soc_bus_data_width//8)
# # #
csr.GenericBank.__init__(self,
description = description,
busword = len(self.bus.dat_w),
ordering = ordering,
)
sel = Signal()
self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
for i, c in enumerate(self.simple_csrs):
self.comb += [
c.r.eq(self.bus.dat_w[:c.size]),
If(sel & (self.bus.adr[:log2_int(aligned_paging)] == i),
c.re.eq( self.bus.we),
c.we.eq(~self.bus.we)
)
]
brcases = dict((i, self.bus.dat_r.eq(c.w)) for i, c in enumerate(self.simple_csrs))
self.sync += [
self.bus.dat_r.eq(0),
If(sel, Case(self.bus.adr[:log2_int(aligned_paging)], brcases))
]
# address_map(name, memory) returns the CSR offset at which to map
# the CSR object (register bank or memory).
# If memory=None, the object is the register bank of object source.name.
# Otherwise, it is a memory object belonging to source.name.
# address_map is called exactly once for each object at each call to
# scan(), so it can have side effects.
class CSRBankArray(Module):
def __init__(self, source, address_map, *ifargs, paging=0x800, ordering="big", soc_bus_data_width=32, **ifkwargs):
self.source = source
self.address_map = address_map
self.paging = paging
self.ordering = ordering
self.soc_bus_data_width = soc_bus_data_width
self.scan(ifargs, ifkwargs)
def scan(self, ifargs, ifkwargs):
self.banks = []
self.srams = []
self.constants = []
for name, obj in xdir(self.source, True):
if hasattr(obj, "get_csrs"):
csrs = obj.get_csrs()
else:
csrs = []
if hasattr(obj, "get_memories"):
memories = obj.get_memories()
for memory in memories:
if isinstance(memory, tuple):
if len(memory) == 2:
read_only, memory = memory
port = None
elif len(memory) == 3:
read_only, memory, port = memory
else:
raise ValueError
else:
read_only = False
mapaddr = self.address_map(name, memory)
if mapaddr is None:
continue
sram_bus = Interface(*ifargs, **ifkwargs)
mmap = SRAM(memory, mapaddr,
port = port,
read_only = read_only,
bus = sram_bus,
paging = self.paging)
self.submodules += mmap
csrs += mmap.get_csrs()
self.srams.append((name, memory, mapaddr, mmap))
if hasattr(obj, "get_constants"):
for constant in obj.get_constants():
self.constants.append((name, constant))
if csrs:
mapaddr = self.address_map(name, None)
if mapaddr is None:
continue
bank_bus = Interface(*ifargs, **ifkwargs)
rmap = CSRBank(csrs, mapaddr,
bus = bank_bus,
paging = self.paging,
ordering = self.ordering,
soc_bus_data_width = self.soc_bus_data_width)
self.submodules += rmap
self.banks.append((name, csrs, mapaddr, rmap))
def get_rmaps(self):
return [rmap for name, csrs, mapaddr, rmap in self.banks]
def get_mmaps(self):
return [mmap for name, memory, mapaddr, mmap in self.srams]
def get_buses(self):
return [i.bus for i in self.get_rmaps() + self.get_mmaps()]
| [
"litex.soc.interconnect.csr.CSRStorage"
] | [((8120, 8143), 'migen.util.misc.xdir', 'xdir', (['self.source', '(True)'], {}), '(self.source, True)\n', (8124, 8143), False, 'from migen.util.misc import xdir\n'), ((3579, 3634), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['page_bits'], {'name': "(mem.name_override + '_page')"}), "(page_bits, name=mem.name_override + '_page')\n", (3589, 3634), False, 'from litex.soc.interconnect.csr import CSRStorage\n'), ((4624, 4710), 'migen.genlib.misc.chooser', 'chooser', (['word_expanded', 'word_index', 'self.bus.dat_r'], {'n': 'csrw_per_memw', 'reverse': '(True)'}), '(word_expanded, word_index, self.bus.dat_r, n=csrw_per_memw, reverse\n =True)\n', (4631, 4710), False, 'from migen.genlib.misc import chooser\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants -----------------------------------------------------------------------------------------
CPU_VARIANTS = ["standard"]
# FemtoRV ------------------------------------------------------------------------------------------
class FemtoRV(CPU):
name = "femtorv"
human_name = "FemtoRV"
variants = CPU_VARIANTS
data_width = 32
endianness = "little"
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # Origin, Length.
# GCC Flags.
@property
def gcc_flags(self):
flags = "-march=rv32i "
flags += "-mabi=ilp32 "
flags += "-D__femtorv__ "
return flags
def __init__(self, platform, variant="standard"):
self.platform = platform
self.variant = variant
self.reset = Signal()
self.idbus = idbus = wishbone.Interface()
self.periph_buses = [idbus] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
# # #
# FemtoRV Mem Bus.
# ----------------
mbus = Record([
("addr", 32),
("wdata", 32),
("wmask", 4),
("rdata", 32),
("rstrb", 1),
("rbusy", 1),
("wbusy", 1),
])
# FemtoRV Instance.
# -----------------
self.cpu_params = dict(
# Parameters.
p_ADDR_WIDTH = 32,
p_RESET_ADDR = Constant(0, 32),
# Clk / Rst.
i_clk = ClockSignal("sys"),
i_reset = ~ResetSignal("sys"), # Active Low.
# I/D Bus.
o_mem_addr = mbus.addr,
o_mem_wdata = mbus.wdata,
o_mem_wmask = mbus.wmask,
i_mem_rdata = mbus.rdata,
o_mem_rstrb = mbus.rstrb,
i_mem_rbusy = mbus.rbusy,
i_mem_wbusy = mbus.wbusy,
)
# Adapt FemtoRV Mem Bus to Wishbone.
# ----------------------------------
# Bytes to Words addressing conversion.
self.comb += idbus.adr.eq(mbus.addr[2:])
# Wdata/WMask direct connection.
self.comb += idbus.dat_w.eq(mbus.wdata)
self.comb += idbus.sel.eq(mbus.wmask)
# Control adaptation.
latch = Signal()
write = mbus.wmask != 0
read = mbus.rstrb
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
idbus.stb.eq(read | write),
idbus.cyc.eq(read | write),
idbus.we.eq(write),
If(read,
mbus.rbusy.eq(1),
NextState("READ")
).Elif(write,
mbus.wbusy.eq(1),
NextState("WRITE")
)
)
fsm.act("READ",
idbus.stb.eq(1),
idbus.cyc.eq(1),
mbus.rbusy.eq(1),
If(idbus.ack,
latch.eq(1),
NextState("IDLE")
)
)
fsm.act("WRITE",
idbus.stb.eq(1),
idbus.cyc.eq(1),
idbus.we.eq(1),
mbus.wbusy.eq(1),
If(idbus.ack,
NextState("IDLE")
)
)
# Latch RData on Wishbone ack.
self.sync += If(latch, mbus.rdata.eq(idbus.dat_r))
# Add Verilog sources.
# --------------------
self.add_sources(platform)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(p_RESET_ADDR=Constant(reset_address, 32))
@staticmethod
def add_sources(platform):
if not os.path.exists("femtorv32_quark.v"):
# Get FemtoRV32 source.
os.system("wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v")
# FIXME: Patch it to fix compilation issue with Verilator, report issue.
os.system(f"patch -p0 < {os.path.dirname(os.path.realpath(__file__))}/femtorv32_quark.patch")
platform.add_source("femtorv32_quark.v")
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("FemtoRV32", **self.cpu_params)
| [
"litex.soc.interconnect.wishbone.Interface"
] | [((1261, 1281), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1279, 1281), False, 'from litex.soc.interconnect import wishbone\n'), ((4133, 4168), 'os.path.exists', 'os.path.exists', (['"""femtorv32_quark.v"""'], {}), "('femtorv32_quark.v')\n", (4147, 4168), False, 'import os\n'), ((4218, 4347), 'os.system', 'os.system', (['"""wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v"""'], {}), "(\n 'wget https://raw.githubusercontent.com/BrunoLevy/learn-fpga/master/FemtoRV/RTL/PROCESSOR/femtorv32_quark.v'\n )\n", (4227, 4347), False, 'import os\n'), ((4476, 4502), 'os.path.realpath', 'os.path.realpath', (['__file__'], {}), '(__file__)\n', (4492, 4502), False, 'import os\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Marble-Mini is a simple AMC FMC carrier board with SFP, 2x FMC, PoE, DDR3:
# https://github.com/BerkeleyLab/Marble-Mini
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# TODO:
# - Add the TMDS lanes for the HDMI connector.
# - Populate the SFPs.
# - verify period constraint on mgt_clk1.
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk20_vcxo", 0, Pins("D17"), IOStandard("LVCMOS33")),
("clk20_vcxo_en", 0, Pins("E13"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), # Set it to 1 to enable clk20_-vcxo.
("mgt_clk", 0,
Subsignal("p", Pins("F6")),
Subsignal("n", Pins("E6"))
),
("mgt_clk", 1,
Subsignal("p", Pins("F10")),
Subsignal("n", Pins("E10"))
),
# Serial
("serial", 0,
Subsignal("rts", Pins("W9")),
Subsignal("rx", Pins("U7")),
Subsignal("tx", Pins("Y9")),
IOStandard("LVCMOS25")
),
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("J15")),
Subsignal("rx", Pins("L19")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("M17")),
Subsignal("rx_ctl", Pins("H15")),
Subsignal("rx_data", Pins("K13 H14 J14 K14")),
Subsignal("tx_ctl", Pins("J16")),
Subsignal("tx_data", Pins("G15 G16 G13 H13")),
IOStandard("LVCMOS25"),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"L6 M5 P6 K6 M1 M3 N2 M6",
"P1 P2 L4 N5 L3 R1 N3 E3"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("L5 M2 N4"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("J4"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("J6"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("K3"), IOStandard("SSTL135")),
Subsignal("dm", Pins("G2 E2"), IOStandard("SSTL135")),
Subsignal("dq", Pins(
"G3 J1 H4 H5 H2 K1 H3 J5",
"G1 B1 F1 F3 C2 A1 D2 B2"),
IOStandard("SSTL135")),
Subsignal("dqs_p", Pins("K2 E1"), IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("J2 D1"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("P5"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("P4"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("L1"), IOStandard("SSTL135")),
Subsignal("odt", Pins("K4"), IOStandard("SSTL135")),
# Subsignal("cs_n", Pins(""), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("G4"), IOStandard("SSTL135"))
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("PMOD0", "C18 D22 E22 G21 D21 E21 F21 G22"),
("PMOD1", "F13 C14 C15 D16 F14 F15 F16 E16"),
("FMC1_LPC", {
"CLK0_M2C_N": "W20",
"CLK0_M2C_P": "W19",
"CLK1_M2C_N": "Y19",
"CLK1_M2C_P": "Y18",
"LA00_N": "V20",
"LA00_P": "U20",
"LA01_N": "V19",
"LA01_P": "V18",
"LA02_N": "R16",
"LA02_P": "P15",
"LA03_N": "N14",
"LA03_P": "N13",
"LA04_N": "W17",
"LA04_P": "V17",
"LA05_N": "R19",
"LA05_P": "P19",
"LA06_N": "AB18",
"LA06_P": "AA18",
"LA07_N": "AA21",
"LA07_P": "AA20",
"LA08_N": "P17",
"LA08_P": "N17",
"LA09_N": "T18",
"LA09_P": "R18",
"LA10_N": "AB20",
"LA10_P": "AA19",
"LA11_N": "R17",
"LA11_P": "P16",
"LA12_N": "U18",
"LA12_P": "U17",
"LA13_N": "W22",
"LA13_P": "W21",
"LA14_N": "AB22",
"LA14_P": "AB21",
"LA15_N": "Y22",
"LA15_P": "Y21",
"LA16_N": "R14",
"LA16_P": "P14",
"LA17_N_CC": "K19",
"LA17_P_CC": "K18",
"LA18_N_CC": "H19",
"LA18_P_CC": "J19",
"LA19_N": "J17",
"LA19_P": "K17",
"LA20_N": "L15",
"LA20_P": "L14",
"LA21_N": "N19",
"LA21_P": "N18",
"LA22_N": "L21",
"LA22_P": "M21",
"LA23_N": "M20",
"LA23_P": "N20",
"LA24_N": "H18",
"LA24_P": "H17",
"LA25_N": "L18",
"LA25_P": "M18",
"LA26_N": "G20",
"LA26_P": "H20",
"LA27_N": "M22",
"LA27_P": "N22",
"LA28_N": "M16",
"LA28_P": "M15",
"LA29_N": "K22",
"LA29_P": "K21",
"LA30_N": "K16",
"LA30_P": "L16",
"LA31_N": "H22",
"LA31_P": "J22",
"LA32_N": "G18",
"LA32_P": "G17",
"LA33_N": "J21",
"LA33_P": "J20"
}),
("FMC2_LPC", {
"CLK0_M2C_N": "W4",
"CLK0_M2C_P": "V4",
"CLK1_M2C_N": "T4",
"CLK1_M2C_P": "R4",
"LA00_N": "U5",
"LA00_P": "T5",
"LA01_N": "AA4",
"LA01_P": "Y4",
"LA02_N": "V3",
"LA02_P": "U3",
"LA03_N": "V2",
"LA03_P": "U2",
"LA04_N": "V5",
"LA04_P": "U6",
"LA05_N": "T6",
"LA05_P": "R6",
"LA06_N": "U1",
"LA06_P": "T1",
"LA07_N": "V8",
"LA07_P": "V9",
"LA08_N": "Y2",
"LA08_P": "W2",
"LA09_N": "AA3",
"LA09_P": "Y3",
"LA10_N": "Y1",
"LA10_P": "W1",
"LA11_N": "AA6",
"LA11_P": "Y6",
"LA12_N": "W5",
"LA12_P": "W6",
"LA13_N": "W7",
"LA13_P": "V7",
"LA14_N": "AB1",
"LA14_P": "AA1",
"LA15_N": "AB5",
"LA15_P": "AA5",
"LA16_N": "AB2",
"LA16_P": "AB3",
"LA17_N": "W12",
"LA17_P": "W11",
"LA18_N": "V14",
"LA18_P": "V13",
"LA19_N": "Y12",
"LA19_P": "Y11",
"LA20_N": "AA11",
"LA20_P": "AA10",
"LA21_N": "AA14",
"LA21_P": "Y13",
"LA22_N": "W16",
"LA22_P": "W15",
"LA23_N": "W10",
"LA23_P": "V10",
"LA24_N": "Y14",
"LA24_P": "W14",
"LA25_N": "AB12",
"LA25_P": "AB11",
"LA26_N": "AA16",
"LA26_P": "Y16",
"LA27_N": "AB10",
"LA27_P": "AA9",
"LA28_N": "T15",
"LA28_P": "T14",
"LA29_N": "U16",
"LA29_P": "T16",
"LA30_N": "V15",
"LA30_P": "U15",
"LA31_N": "AB13",
"LA31_P": "AA13",
"LA32_N": "AB15",
"LA32_P": "AA15",
"LA33_N": "AB17",
"LA33_P": "AB16"
})
]
_pmod0_pins = ["PMOD0:{}".format(i) for i in range(8)]
_pmod1_pins = ["PMOD1:{}".format(i) for i in range(8)]
break_off_pmod = [
("pmod0", 0, Pins(*_pmod0_pins), IOStandard("LVCMOS33")),
("pmod1", 0, Pins(*_pmod1_pins), IOStandard("LVCMOS33")),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk20_vcxo"
default_clk_period = 1e9/20e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-2fgg484", _io, _connectors, toolchain=toolchain)
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"
]
self.toolchain.additional_commands = [
"write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"
]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 35]")
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
def create_programmer(self):
return OpenOCD("openocd_marblemini.cfg")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk20_vcxo", loose=True), 1e9/20e6)
self.add_period_constraint(self.lookup_request("mgt_clk", 0, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("mgt_clk", 1, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((7806, 7898), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-2fgg484"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7a100t-2fgg484', _io, _connectors,\n toolchain=toolchain)\n", (7829, 7898), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((8517, 8550), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_marblemini.cfg"""'], {}), "('openocd_marblemini.cfg')\n", (8524, 8550), False, 'from litex.build.openocd import OpenOCD\n'), ((8597, 8639), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (8623, 8639), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 msloniewski <<EMAIL>>
# This file is Copyright (c) 2019 vytautasb <<EMAIL>>
# License: BSD
import os
import subprocess
import sys
import math
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools
def _format_constraint(c, signame, fmt_r):
if isinstance(c, Pins):
return "set_location_assignment -comment \"{name}\" " \
"-to {signame} Pin_{pin}".format(
signame=signame,
name=fmt_r,
pin=c.identifiers[0])
elif isinstance(c, IOStandard):
return "set_instance_assignment -name io_standard " \
"-comment \"{name}\" \"{std}\" -to {signame}".format(
signame=signame,
name=fmt_r,
std=c.name)
elif isinstance(c, Misc):
if not isinstance(c.misc, str) and len(c.misc) == 2:
return "set_instance_assignment -comment \"{name}\" " \
"-name {misc[0]} \"{misc[1]}\" -to {signame}".format(
signame=signame,
name=fmt_r,
misc=c.misc)
else:
return "set_instance_assignment -comment \"{name}\" " \
"-name {misc} " \
"-to {signame}".format(
signame=signame,
name=fmt_r,
misc=c.misc)
def _format_qsf(signame, pin, others, resname):
fmt_r = "{}:{}".format(*resname[:2])
if resname[2] is not None:
fmt_r += "." + resname[2]
fmt_c = [_format_constraint(c, signame, fmt_r) for c in
([Pins(pin)] + others)]
return '\n'.join(fmt_c)
def _build_qsf(named_sc, named_pc, build_name):
lines = []
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
lines.append(
_format_qsf("{}[{}]".format(sig, i), p, others, resname))
else:
lines.append(_format_qsf(sig, pins[0], others, resname))
if named_pc:
lines.append("")
lines.append("\n\n".join(named_pc))
# Set top level name to "build_name" in .qsf file instead always use "top" name
lines.append("set_global_assignment -name top_level_entity " + build_name)
return "\n".join(lines)
def _build_sdc(clocks, false_paths, vns, build_name):
lines = []
for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
lines.append(
"create_clock -name {clk} -period ".format(clk=vns.get_name(clk)) + str(period) +
" [get_ports {{{clk}}}]".format(clk=vns.get_name(clk)))
for from_, to in sorted(false_paths,
key=lambda x: (x[0].duid, x[1].duid)):
lines.append(
"set_false_path "
"-from [get_clocks {{{from_}}}] "
"-to [get_clocks {{{to}}}]".format(
from_=vns.get_name(from_), to=vns.get_name(to)))
tools.write_to_file("{}.sdc".format(build_name), "\n".join(lines))
def _build_files(device, ips, sources, vincpaths, named_sc, named_pc, build_name):
lines = []
for filename in ips:
lines.append("set_global_assignment -name QSYS_FILE {path} ".format(
path=filename.replace("\\", "/")))
for filename, language, library in sources:
# Enforce use of SystemVerilog since Quartus does not support global parameters in Verilog
if language == "verilog":
language = "systemverilog"
lines.append(
"set_global_assignment -name {lang}_FILE {path} "
"-library {lib}".format(
lang=language.upper(),
path=filename.replace("\\", "/"),
lib=library))
lines.append("set_global_assignment -name SDC_FILE {}.sdc".format(build_name))
for path in vincpaths:
lines.append("set_global_assignment -name SEARCH_PATH {}".format(
path.replace("\\", "/")))
lines.append(_build_qsf(named_sc, named_pc, build_name))
lines.append("set_global_assignment -name DEVICE {}".format(device))
tools.write_to_file("{}.qsf".format(build_name), "\n".join(lines))
def _run_quartus(build_name, quartus_path, create_rbf):
if sys.platform == "win32" or sys.platform == "cygwin":
build_script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"
build_script_file = "build_" + build_name + ".bat"
command = build_script_file
else:
build_script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\nset -e\n"
build_script_file = "build_" + build_name + ".sh"
command = ["bash", build_script_file]
build_script_contents += """
set -e
quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_sta {build_name} -c {build_name}"""
if create_rbf:
build_script_contents +="""
if [ -f "{build_name}.sof" ]
then
quartus_cpf -c {build_name}.sof {build_name}.rbf
fi
"""
build_script_contents = build_script_contents.format(build_name=build_name) # noqa
tools.write_to_file(build_script_file,
build_script_contents,
force_unix=True)
if subprocess.call(command):
raise OSError("Subprocess failed")
class AlteraQuartusToolchain:
def __init__(self):
self.clocks = dict()
self.false_paths = set()
def build(self, platform, fragment, build_dir="build", build_name="top",
toolchain_path=None, run=True, **kwargs):
if toolchain_path is None:
toolchain_path="/opt/Altera"
cwd = os.getcwd()
os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir)
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
platform.add_source(v_file)
_build_files(platform.device,
platform.ips,
platform.sources,
platform.verilog_include_paths,
named_sc,
named_pc,
build_name)
_build_sdc(self.clocks, self.false_paths, v_output.ns, build_name)
if run:
_run_quartus(build_name, toolchain_path, platform.create_rbf)
os.chdir(cwd)
return v_output.ns
def add_period_constraint(self, platform, clk, period):
if clk in self.clocks:
raise ValueError("A period constraint already exists")
period = math.floor(period*1e3)/1e3 # round to lowest picosecond
self.clocks[clk] = period
def add_false_path_constraint(self, platform, from_, to):
if (to, from_) not in self.false_paths:
self.false_paths.add((from_, to))
| [
"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file",
"litex.build.generic_platform.Pins"
] | [((5447, 5525), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['build_script_file', 'build_script_contents'], {'force_unix': '(True)'}), '(build_script_file, build_script_contents, force_unix=True)\n', (5466, 5525), False, 'from litex.build import tools\n'), ((5582, 5606), 'subprocess.call', 'subprocess.call', (['command'], {}), '(command)\n', (5597, 5606), False, 'import subprocess\n'), ((5993, 6004), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (6002, 6004), False, 'import os\n'), ((6013, 6050), 'os.makedirs', 'os.makedirs', (['build_dir'], {'exist_ok': '(True)'}), '(build_dir, exist_ok=True)\n', (6024, 6050), False, 'import os\n'), ((6059, 6078), 'os.chdir', 'os.chdir', (['build_dir'], {}), '(build_dir)\n', (6067, 6078), False, 'import os\n'), ((6893, 6906), 'os.chdir', 'os.chdir', (['cwd'], {}), '(cwd)\n', (6901, 6906), False, 'import os\n'), ((7111, 7138), 'math.floor', 'math.floor', (['(period * 1000.0)'], {}), '(period * 1000.0)\n', (7121, 7138), False, 'import math\n'), ((4476, 4506), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (4504, 4506), False, 'from litex.build import tools\n'), ((4688, 4718), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (4716, 4718), False, 'from litex.build import tools\n'), ((1728, 1737), 'litex.build.generic_platform.Pins', 'Pins', (['pin'], {}), '(pin)\n', (1732, 1737), False, 'from litex.build.generic_platform import Pins, IOStandard, Misc\n')] |
#
# This file is part of USB3-PIPE project.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.common import TSEQ, TS1, TS1_INV, TS2
# Training Sequence Checker ------------------------------------------------------------------------
class TSChecker(Module):
"""Training Sequence Checker
Generic Training Sequence Ordered Set checker.
This module detects a specific Training Sequence Ordered Set by analyzing the RX stream. When N
consecutive Ordered Sets have been detected without errors (N configured by n_ordered_sets), a
detection is reported on detected signals for one cycle. Training config is also reported for
TS1/TS2 Ordered Sets.
"""
def __init__(self, ordered_set, n_ordered_sets=1):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.detected = Signal() # o
self.error = Signal() # o
self.reset = Signal() # o
self.loopback = Signal() # o
self.scrambling = Signal(reset=1) # o
# # #
self.comb += self.sink.ready.eq(1)
# Memory -----------------------------------------------------------------------------------
mem_depth = len(ordered_set.to_bytes())//4
mem_init = [int.from_bytes(ordered_set.to_bytes()[4*i:4*(i+1)], "little") for i in range(mem_depth)]
mem = Memory(32, mem_depth, mem_init)
port = mem.get_port(async_read=True)
self.specials += mem, port
# Data check -------------------------------------------------------------------------------
error = Signal()
error_mask = Signal(32, reset=2**32-1)
first_ctrl = 0b1111
self.comb += If(port.adr == 1, error_mask.eq(0xffff00ff))
self.comb += [
If(self.sink.valid,
# Check Comma
If((port.adr == 0) & (self.sink.ctrl != first_ctrl),
error.eq(1)
),
If((port.adr != 0) & (self.sink.ctrl != 0),
error.eq(1)
),
# Check Word
If((self.sink.data & error_mask) != (port.dat_r & error_mask),
error.eq(1)
)
),
self.error.eq(error)
]
# Link Config ------------------------------------------------------------------------------
self.sync += [
If(self.sink.valid & (port.adr == 1),
self.reset.eq( self.sink.data[ 8]),
self.loopback.eq( self.sink.data[10]),
self.scrambling.eq(~self.sink.data[11])
)
]
# Memory address generation ----------------------------------------------------------------
self.sync += [
If(self.sink.valid,
If(~error,
If(port.adr == (mem_depth - 1),
port.adr.eq(0)
).Else(
port.adr.eq(port.adr + 1)
)
).Else(
port.adr.eq(0)
)
)
]
# Count ------------------------------------------------------------------------------------
count = Signal(max=mem_depth*n_ordered_sets)
count_done = (count == (mem_depth*n_ordered_sets - 1))
self.sync += [
If(self.sink.valid,
If(~error & ~count_done,
count.eq(count + 1)
).Else(
count.eq(0)
)
)
]
# Result -----------------------------------------------------------------------------------
self.comb += self.detected.eq(self.sink.valid & count_done)
# Training Sequence Generator ----------------------------------------------------------------------
class TSGenerator(Module):
"""Training Sequence Generator
Generic Training Sequence Ordered Set generator.
This module generates a specific Training Sequence Ordered Set to the TX stream. For each start,
N consecutive Ordered Sets are generated (N configured by n_ordered_sets). Done signal is assert
on the last cycle of the generation. Training config can also be transmitted for TS1/TS2 Ordered
Sets.
"""
def __init__(self, ordered_set, n_ordered_sets=1):
self.start = Signal() # i
self.done = Signal() # o
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
if ordered_set.name in ["TS1", "TS2"]:
self.reset = Signal() # i
self.loopback = Signal() # i
self.scrambling = Signal(reset=1) # i
# # #
run = Signal()
# Memory --------------------------------------------------------------------------------
mem_depth = len(ordered_set.to_bytes())//4
mem_init = [int.from_bytes(ordered_set.to_bytes()[4*i:4*(i+1)], "little") for i in range(mem_depth)]
mem = Memory(32, mem_depth, mem_init)
port = mem.get_port(async_read=True)
self.specials += mem, port
# Memory address generation ----------------------------------------------------------------
self.sync += [
If(self.source.valid,
If(self.source.ready,
If(port.adr == (mem_depth - 1),
port.adr.eq(0)
).Else(
port.adr.eq(port.adr + 1)
)
)
).Else(
port.adr.eq(0)
)
]
# Link Config ------------------------------------------------------------------------------
link_config = Signal(8)
if ordered_set.name in ["TS1", "TS2"]:
self.comb += [
link_config[0].eq(self.reset),
link_config[2].eq(self.loopback),
link_config[3].eq(~self.scrambling)
]
# Data generation --------------------------------------------------------------------------
if ordered_set.name in ["TS1", "TS2"]:
first_ctrl = 0b1111
else:
first_ctrl = 0b0001
self.comb += [
self.source.valid.eq(self.start | run),
If(port.adr == 0,
self.source.ctrl.eq(first_ctrl),
).Else(
self.source.ctrl.eq(0)
),
self.source.data.eq(port.dat_r)
]
if ordered_set.name in ["TS1", "TS2"]:
self.comb += If(port.adr == 1, self.source.data[8:16].eq(link_config))
# Count ------------------------------------------------------------------------------------
count = Signal(max=mem_depth*n_ordered_sets)
count_done = (count == (mem_depth*n_ordered_sets - 1))
self.sync += [
If(run,
If(self.source.ready,
count.eq(count + 1),
If(count_done,
run.eq(0),
count.eq(0)
)
)
).Elif(self.start,
If(self.source.ready,
run.eq(1),
count.eq(1)
)
)
]
# Delimiters -------------------------------------------------------------------------------
self.comb += [
self.source.first.eq(count == 0),
self.source.last.eq(count_done),
]
# Result -----------------------------------------------------------------------------------
self.comb += self.done.eq(self.source.ready & run & count_done)
# Training Sequence Unit ---------------------------------------------------------------------------
class TSUnit(Module):
"""Training Sequence Unit
Detect/generate the Training Sequence Ordered Sets required for a USB3.0 link with simple
control/status signals.
"""
def __init__(self, serdes):
self.rx_enable = Signal() # i
self.rx_ts1 = Signal() # o
self.rx_ts1_inv = Signal() # o
self.rx_ts2 = Signal() # o
self.tx_enable = Signal() # i
self.tx_tseq = Signal() # i
self.tx_ts1 = Signal() # i
self.tx_ts2 = Signal() # i
self.tx_done = Signal() # o
# # #
# Ordered Set Checkers ---------------------------------------------------------------------
self.submodules.ts1_checker = ts1_checker = TSChecker(ordered_set=TS1, n_ordered_sets=8)
self.submodules.ts1_inv_checker = ts1_inv_checker = TSChecker(ordered_set=TS1_INV, n_ordered_sets=8)
self.submodules.ts2_checker = ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.comb += [
serdes.source.connect(ts1_checker.sink, omit={"ready"}),
serdes.source.connect(ts1_inv_checker.sink, omit={"ready"}),
serdes.source.connect(ts2_checker.sink, omit={"ready"}),
If(self.rx_enable, serdes.source.ready.eq(1)),
self.rx_ts1.eq(ts1_checker.detected),
self.rx_ts1_inv.eq(ts1_inv_checker.detected),
self.rx_ts2.eq(ts2_checker.detected),
]
# Ordered Set Generators -------------------------------------------------------------------
self.submodules.tseq_generator = tseq_generator = TSGenerator(ordered_set=TSEQ, n_ordered_sets=65536)
self.submodules.ts1_generator = ts1_generator = TSGenerator(ordered_set=TS1, n_ordered_sets=16)
self.submodules.ts2_generator = ts2_generator = TSGenerator(ordered_set=TS2, n_ordered_sets=16)
self.comb += [
If(self.tx_enable,
If(self.tx_tseq,
tseq_generator.start.eq(1),
tseq_generator.source.connect(serdes.sink),
),
If(self.tx_ts1,
ts1_generator.start.eq(1),
ts1_generator.source.connect(serdes.sink),
),
If(self.tx_ts2,
ts2_generator.start.eq(1),
ts2_generator.source.connect(serdes.sink),
),
),
self.tx_done.eq(tseq_generator.done | ts1_generator.done | ts2_generator.done),
]
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((871, 915), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (886, 915), False, 'from litex.soc.interconnect import stream\n'), ((4553, 4597), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('ctrl', 4)]"], {}), "([('data', 32), ('ctrl', 4)])\n", (4568, 4597), False, 'from litex.soc.interconnect import stream\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2015 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("AB8"), IOStandard("LVCMOS15")),
("user_led", 1, Pins("AA8"), IOStandard("LVCMOS15")),
("user_led", 2, Pins("AC9"), IOStandard("LVCMOS15")),
("user_led", 3, Pins("AB9"), IOStandard("LVCMOS15")),
("user_led", 4, Pins("AE26"), IOStandard("LVCMOS25")),
("user_led", 5, Pins("G19"), IOStandard("LVCMOS25")),
("user_led", 6, Pins("E18"), IOStandard("LVCMOS25")),
("user_led", 7, Pins("F16"), IOStandard("LVCMOS25")),
("cpu_reset", 0, Pins("AB7"), IOStandard("LVCMOS15")),
("user_btn_c", 0, Pins("G12"), IOStandard("LVCMOS25")),
("user_btn_n", 0, Pins("AA12"), IOStandard("LVCMOS15")),
("user_btn_s", 0, Pins("AB12"), IOStandard("LVCMOS15")),
("user_btn_w", 0, Pins("AC6"), IOStandard("LVCMOS15")),
("user_btn_e", 0, Pins("AG5"), IOStandard("LVCMOS15")),
("user_dip_btn", 0, Pins("Y29"), IOStandard("LVCMOS25")),
("user_dip_btn", 1, Pins("W29"), IOStandard("LVCMOS25")),
("user_dip_btn", 2, Pins("AA28"), IOStandard("LVCMOS25")),
("user_dip_btn", 3, Pins("Y28"), IOStandard("LVCMOS25")),
("user_sma_clock", 0,
Subsignal("p", Pins("L25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE")),
Subsignal("n", Pins("K25"), IOStandard("LVDS_25"),
Misc("DIFF_TERM=TRUE"))
),
("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")),
("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")),
("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS25")),
("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS25")),
("clk200", 0,
Subsignal("p", Pins("AD12"), IOStandard("LVDS")),
Subsignal("n", Pins("AD11"), IOStandard("LVDS"))
),
("clk156", 0,
Subsignal("p", Pins("K28"), IOStandard("LVDS_25")),
Subsignal("n", Pins("K29"), IOStandard("LVDS_25"))
),
("i2c", 0,
Subsignal("scl", Pins("K21")),
Subsignal("sda", Pins("L21")),
IOStandard("LVCMOS25")),
("serial", 0,
Subsignal("cts", Pins("L27")),
Subsignal("rts", Pins("K23")),
Subsignal("tx", Pins("K24")),
Subsignal("rx", Pins("M19")),
IOStandard("LVCMOS25")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("U19")),
Subsignal("dq", Pins("P24", "R25", "R20", "R21")),
IOStandard("LVCMOS25")
),
("sdcard", 0,
Subsignal("clk", Pins("AB23")),
Subsignal("cmd", Pins("AB22"), Misc("PULLUP True")),
Subsignal("data", Pins("AC20 AA23 AA22 AC21"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS25")
),
("spisdcard", 0,
Subsignal("clk", Pins("AB23")),
Subsignal("cs_n", Pins("AC21")),
Subsignal("mosi", Pins("AB22"), Misc("PULLUP")),
Subsignal("miso", Pins("AC20"), Misc("PULLUP")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS25")
),
("lcd", 0,
Subsignal("db", Pins("AA13 AA10 AA11 Y10")),
Subsignal("e", Pins("AB10")),
Subsignal("rs", Pins("Y11")),
Subsignal("rw", Pins("AB13")),
IOStandard("LVCMOS15")),
("rotary", 0,
Subsignal("a", Pins("Y26")),
Subsignal("b", Pins("Y25")),
Subsignal("push", Pins("AA26")),
IOStandard("LVCMOS25")),
("hdmi", 0,
Subsignal("d", Pins(
"B23 A23 E23 D23 F25 E25 E24 D24",
"F26 E26 G23 G24 J19 H19 L17 L18",
"K19 K20")),
Subsignal("de", Pins("H17")),
Subsignal("clk", Pins("K18")),
Subsignal("vsync", Pins("H20")),
Subsignal("hsync", Pins("J18")),
Subsignal("int", Pins("AH24")),
Subsignal("spdif", Pins("J17")),
Subsignal("spdif_out", Pins("G20")),
IOStandard("LVCMOS25")),
("ddram", 0,
Subsignal("a", Pins(
"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC12"), IOStandard("SSTL15")),
Subsignal("dm", Pins(
"Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AG10"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AH10"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AF10"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AD8"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
("ddram_dual_rank", 0,
Subsignal("a", Pins(
"AH12 AG13 AG12 AF12 AJ12 AJ13 AJ14 AH14",
"AK13 AK14 AF13 AE13 AJ11 AH11 AK10 AK11"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("AH9 AG9 AK9"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("AD9"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("AC11"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("AE9"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("AC12 AE8"), IOStandard("SSTL15")),
Subsignal("dm", Pins(
"Y16 AB17 AF17 AE16 AK5 AJ3 AF6 AC7"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AA15 AA16 AC14 AD14 AA17 AB15 AE15 Y15",
"AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18",
"AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19",
"AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15",
"AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6",
"AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1",
"AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5",
"AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"),
IOStandard("SSTL15_T_DCI")),
Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("AC15 Y18 AK18 AJ16 AJ7 AH1 AG3 AD1"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("AG10 AE11"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("AH10 AF11"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("AF10 AE10"), IOStandard("SSTL15")),
Subsignal("odt", Pins("AD8 AC10"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("AK3"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
Misc("VCCAUX_IO=HIGH")
),
("eth_clocks", 0,
Subsignal("tx", Pins("M28")),
Subsignal("gtx", Pins("K30")),
Subsignal("rx", Pins("U27")),
IOStandard("LVCMOS25")
),
("eth", 0,
Subsignal("rst_n", Pins("L20")),
Subsignal("int_n", Pins("N30")),
Subsignal("mdio", Pins("J21")),
Subsignal("mdc", Pins("R23")),
Subsignal("rx_dv", Pins("R28")),
Subsignal("rx_er", Pins("V26")),
Subsignal("rx_data", Pins("U30 U25 T25 U28 R19 T27 T26 T28")),
Subsignal("tx_en", Pins("M27")),
Subsignal("tx_er", Pins("N29")),
Subsignal("tx_data", Pins("N27 N25 M29 L28 J26 K26 L30 J28")),
Subsignal("col", Pins("W19")),
Subsignal("crs", Pins("R30")),
IOStandard("LVCMOS25")
),
("pcie_x1", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6")),
Subsignal("rx_n", Pins("M5")),
Subsignal("tx_p", Pins("L4")),
Subsignal("tx_n", Pins("L3"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6")),
Subsignal("rx_n", Pins("M5 P5")),
Subsignal("tx_p", Pins("L4 M2")),
Subsignal("tx_n", Pins("L3 M1"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6 R4 T6")),
Subsignal("rx_n", Pins("M5 P5 R3 T5")),
Subsignal("tx_p", Pins("L4 M2 N4 P2")),
Subsignal("tx_n", Pins("L3 M1 N3 P1"))
),
("pcie_x8", 0,
Subsignal("rst_n", Pins("G25"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("U8")),
Subsignal("clk_n", Pins("U7")),
Subsignal("rx_p", Pins("M6 P6 R4 T6 V6 W4 Y6 AA4")),
Subsignal("rx_n", Pins("M5 P5 R3 T5 V5 W3 Y5 AA3")),
Subsignal("tx_p", Pins("L4 M2 N4 P2 T2 U4 V2 Y2")),
Subsignal("tx_n", Pins("L3 M1 N3 P1 T1 U3 V1 Y1"))
),
("vadj_on_b", 0, Pins("J27"), IOStandard("LVCMOS25")),
("sgmii_clock", 0,
Subsignal("p", Pins("G8")),
Subsignal("n", Pins("G7"))
),
("user_sma_mgt_refclk", 0,
Subsignal("p", Pins("J8")),
Subsignal("n", Pins("J7"))
),
("user_sma_mgt_tx", 0,
Subsignal("p", Pins("K2")),
Subsignal("n", Pins("K1"))
),
("user_sma_mgt_rx", 0,
Subsignal("p", Pins("K6")),
Subsignal("n", Pins("K5"))
),
("sfp", 0, # inverted prior to HW rev 1.1
Subsignal("txp", Pins("H2")),
Subsignal("txn", Pins("H1")),
Subsignal("rxp", Pins("G4")),
Subsignal("rxn", Pins("G3")),
),
("sfp_tx", 0, # inverted prior to HW rev 1.1
Subsignal("p", Pins("H2")),
Subsignal("n", Pins("H1"))
),
("sfp_rx", 0, # inverted prior to HW rev 1.1
Subsignal("p", Pins("G4")),
Subsignal("n", Pins("G3"))
),
("sfp_tx_disable_n", 0, Pins("Y20"), IOStandard("LVCMOS25")),
("sfp_rx_los", 0, Pins("P19"), IOStandard("LVCMOS25")),
("si5324", 0,
Subsignal("rst_n", Pins("AE20"), IOStandard("LVCMOS25")),
Subsignal("int", Pins("AG24"), IOStandard("LVCMOS25"))
),
("si5324_clkin", 0,
Subsignal("p", Pins("W27"), IOStandard("LVDS_25")),
Subsignal("n", Pins("W28"), IOStandard("LVDS_25"))
),
("si5324_clkout", 0,
Subsignal("p", Pins("L8")),
Subsignal("n", Pins("L7"))
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"DP1_M2C_P" : "D6",
"DP1_M2C_N" : "D5",
"DP2_M2C_P" : "B6",
"DP2_M2C_N" : "B5",
"DP3_M2C_P" : "A8",
"DP3_M2C_N" : "A7",
"DP1_C2M_P" : "C4",
"DP1_C2M_N" : "C3",
"DP2_C2M_P" : "B2",
"DP2_C2M_N" : "B1",
"DP3_C2M_P" : "A4",
"DP3_C2M_N" : "A3",
"DP0_C2M_P" : "D2",
"DP0_C2M_N" : "D1",
"DP0_M2C_P" : "E4",
"DP0_M2C_N" : "E3",
"LA06_P" : "H30",
"LA06_N" : "G30",
"LA10_P" : "D29",
"LA10_N" : "C30",
"LA14_P" : "B28",
"LA14_N" : "A28",
"LA18_CC_P" : "F21",
"LA18_CC_N" : "E21",
"LA27_P" : "C19",
"LA27_N" : "B19",
"HA01_CC_P" : "H14",
"HA01_CC_N" : "G14",
"HA05_P" : "F15",
"HA05_N" : "E16",
"HA09_P" : "F12",
"HA09_N" : "E13",
"HA13_P" : "L16",
"HA13_N" : "K16",
"HA16_P" : "L15",
"HA16_N" : "K15",
"HA20_P" : "K13",
"HA20_N" : "J13",
"CLK1_M2C_P" : "D17",
"CLK1_M2C_N" : "D18",
"LA00_CC_P" : "C25",
"LA00_CC_N" : "B25",
"LA03_P" : "H26",
"LA03_N" : "H27",
"LA08_P" : "E29",
"LA08_N" : "E30",
"LA12_P" : "C29",
"LA12_N" : "B29",
"LA16_P" : "B27",
"LA16_N" : "A27",
"LA20_P" : "E19",
"LA20_N" : "D19",
"LA22_P" : "C20",
"LA22_N" : "B20",
"LA25_P" : "G17",
"LA25_N" : "F17",
"LA29_P" : "C17",
"LA29_N" : "B17",
"LA31_P" : "G22",
"LA31_N" : "F22",
"LA33_P" : "H21",
"LA33_N" : "H22",
"HA03_P" : "C12",
"HA03_N" : "B12",
"HA07_P" : "B14",
"HA07_N" : "A15",
"HA11_P" : "B13",
"HA11_N" : "A13",
"HA14_P" : "J16",
"HA14_N" : "H16",
"HA18_P" : "K14",
"HA18_N" : "J14",
"HA22_P" : "L11",
"HA22_N" : "K11",
"GBTCLK1_M2C_P" : "E8",
"GBTCLK1_M2C_N" : "E7",
"GBTCLK0_M2C_P" : "C8",
"GBTCLK0_M2C_N" : "C7",
"LA01_CC_P" : "D26",
"LA01_CC_N" : "C26",
"LA05_P" : "G29",
"LA05_N" : "F30",
"LA09_P" : "B30",
"LA09_N" : "A30",
"LA13_P" : "A25",
"LA13_N" : "A26",
"LA17_CC_P" : "F20",
"LA17_CC_N" : "E20",
"LA23_P" : "B22",
"LA23_N" : "A22",
"LA26_P" : "B18",
"LA26_N" : "A18",
"PG_M2C" : "J29",
"HA00_CC_P" : "D12",
"HA00_CC_N" : "D13",
"HA04_P" : "F11",
"HA04_N" : "E11",
"HA08_P" : "E14",
"HA08_N" : "E15",
"HA12_P" : "C15",
"HA12_N" : "B15",
"HA15_P" : "H15",
"HA15_N" : "G15",
"HA19_P" : "H11",
"HA19_N" : "H12",
"PRSNT_M2C_B" : "M20",
"CLK0_M2C_P" : "D27",
"CLK0_M2C_N" : "C27",
"LA02_P" : "H24",
"LA02_N" : "H25",
"LA04_P" : "G28",
"LA04_N" : "F28",
"LA07_P" : "E28",
"LA07_N" : "D28",
"LA11_P" : "G27",
"LA11_N" : "F27",
"LA15_P" : "C24",
"LA15_N" : "B24",
"LA19_P" : "G18",
"LA19_N" : "F18",
"LA21_P" : "A20",
"LA21_N" : "A21",
"LA24_P" : "A16",
"LA24_N" : "A17",
"LA28_P" : "D16",
"LA28_N" : "C16",
"LA30_P" : "D22",
"LA30_N" : "C22",
"LA32_P" : "D21",
"LA32_N" : "C21",
"HA02_P" : "D11",
"HA02_N" : "C11",
"HA06_P" : "D14",
"HA06_N" : "C14",
"HA10_P" : "A11",
"HA10_N" : "A12",
"HA17_CC_P" : "G13",
"HA17_CC_N" : "F13",
"HA21_P" : "J11",
"HA21_N" : "J12",
"HA23_P" : "L12",
"HA23_N" : "L13",
}
),
("LPC", {
"GBTCLK0_M2C_P" : "N8",
"GBTCLK0_M2C_N" : "N7",
"DP0_C2M_P" : "F2",
"DP0_C2M_N" : "F1",
"DP0_M2C_P" : "F6",
"DP0_M2C_N" : "F5",
"LA01_CC_P" : "AE23",
"LA01_CC_N" : "AF23",
"LA05_P" : "AG22",
"LA05_N" : "AH22",
"LA09_P" : "AK23",
"LA09_N" : "AK24",
"LA13_P" : "AB24",
"LA13_N" : "AC25",
"LA17_CC_P" : "AB27",
"LA17_CC_N" : "AC27",
"LA23_P" : "AH26",
"LA23_N" : "AH27",
"LA26_P" : "AK29",
"LA26_N" : "AK30",
"CLK0_M2C_P" : "AF22",
"CLK0_M2C_N" : "AG23",
"LA02_P" : "AF20",
"LA02_N" : "AF21",
"LA04_P" : "AH21",
"LA04_N" : "AJ21",
"LA07_P" : "AG25",
"LA07_N" : "AH25",
"LA11_P" : "AE25",
"LA11_N" : "AF25",
"LA15_P" : "AC24",
"LA15_N" : "AD24",
"LA19_P" : "AJ26",
"LA19_N" : "AK26",
"LA21_P" : "AG27",
"LA21_N" : "AG28",
"LA24_P" : "AG30",
"LA24_N" : "AH30",
"LA28_P" : "AE30",
"LA28_N" : "AF30",
"LA30_P" : "AB29",
"LA30_N" : "AB30",
"LA32_P" : "Y30",
"LA32_N" : "AA30",
"LA06_P" : "AK20",
"LA06_N" : "AK21",
"LA10_P" : "AJ24",
"LA10_N" : "AK25",
"LA14_P" : "AD21",
"LA14_N" : "AE21",
"LA18_CC_P" : "AD27",
"LA18_CC_N" : "AD28",
"LA27_P" : "AJ28",
"LA27_N" : "AJ29",
"CLK1_M2C_P" : "AG29",
"CLK1_M2C_N" : "AH29",
"LA00_CC_P" : "AD23",
"LA00_CC_N" : "AE24",
"LA03_P" : "AG20",
"LA03_N" : "AH20",
"LA08_P" : "AJ22",
"LA08_N" : "AJ23",
"LA12_P" : "AA20",
"LA12_N" : "AB20",
"LA16_P" : "AC22",
"LA16_N" : "AD22",
"LA20_P" : "AF26",
"LA20_N" : "AF27",
"LA22_P" : "AJ27",
"LA22_N" : "AK28",
"LA25_P" : "AC26",
"LA25_N" : "AD26",
"LA29_P" : "AE28",
"LA29_N" : "AF28",
"LA31_P" : "AD29",
"LA31_N" : "AE29",
"LA33_P" : "AC29",
"LA33_N" : "AC30",
}
),
("XADC", {
"GPIO0" : "AB25",
"GPIO1" : "AA25",
"GPIO2" : "AB28",
"GPIO3" : "AA27",
"VAUX0_N" : "J24",
"VAUX0_P" : "J23",
"VAUX8_N" : "L23",
"VAUX8_P" : "L22",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado")
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 2.5 [current_design]
""")
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6)
self.add_platform_command("set_property DCI_CASCADE {{32 34}} [get_iobanks 33]")
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((19609, 19701), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k325t-ffg900-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7k325t-ffg900-2', _io, _connectors,\n toolchain='vivado')\n", (19632, 19701), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((20158, 20217), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a325t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a325t.bit')\n", (20165, 20217), False, 'from litex.build.openocd import OpenOCD\n'), ((20264, 20306), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (20290, 20306), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "nextpnr-ecp5", "yosys"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
import argparse
import os
# Disable pylint's E1101, which breaks completely on migen
#pylint:disable=E1101
from migen import *
from litex.build.lattice import LatticePlatform
from litex.build.sim.platform import SimPlatform
from litex.build.generic_platform import Pins, IOStandard, Subsignal, Inverted, Misc
from litex.soc.integration.soc_core import SoCCore
from litex.soc.integration.builder import Builder
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import *
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores import gpio
from litex.soc.cores.spi_flash import SpiFlashDualQuad
from valentyusb.usbcore.cpu.dummyusb import DummyUsb
from valentyusb.usbcore.cpu.eptri import TriEndpointInterface
from valentyusb.usbcore import io as usbio
from rtl.crg import _CRG
from rtl.lcdif import LCDIF
from rtl.messible import Messible
from rtl.reboot import Reboot
from rtl.spi_ram import SpiRamQuad
from rtl.spi_ram_dual import SpiRamDualQuad
from rtl.version import Version
from rtl.picorvspi import PicoRVSpi
import lxsocdoc
_io = [
("clk8", 0, Pins("U18"), IOStandard("LVCMOS33")),
("programn", 0, Pins("R1"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("rx", Pins("U2"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
Subsignal("tx", Pins("U1"), IOStandard("LVCMOS33")),
),
("led", 0, Pins("E3 D3 C3 C4 C2 B1 B20 B19 A18 K20 K19"), IOStandard("LVCMOS33")), # Anodes
("led", 1, Pins("P19 L18 K18"), IOStandard("LVCMOS33")), # Cathodes via FET
("usb", 0,
Subsignal("d_p", Pins("F3")),
Subsignal("d_n", Pins("G3")),
Subsignal("pullup", Pins("E4")),
Subsignal("vbusdet", Pins("F4")),
IOStandard("LVCMOS33")
),
("keypad", 0,
Subsignal("left", Pins("G2"), Misc("PULLMODE=UP")),
Subsignal("right", Pins("F2"), Misc("PULLMODE=UP")),
Subsignal("up", Pins("F1"), Misc("PULLMODE=UP")),
Subsignal("down", Pins("C1"), Misc("PULLMODE=UP")),
Subsignal("start", Pins("E1"), Misc("PULLMODE=UP")),
Subsignal("select", Pins("D2"), Misc("PULLMODE=UP")),
Subsignal("a", Pins("D1"), Misc("PULLMODE=UP")),
Subsignal("b", Pins("E2"), Misc("PULLMODE=UP")),
),
("hdmi_out", 0,
Subsignal("clk_p", Pins("P20"), Inverted(), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("R20"), Inverted(), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("N19"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("N20"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("L20"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("M20"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("L16"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("L17"), IOStandard("TMDS_33")),
Subsignal("hpd_notif", Pins("R18"), IOStandard("LVCMOS33"), Inverted()), # Also called HDMI_HEAC_n
Subsignal("hdmi_heac_p", Pins("T19"), IOStandard("LVCMOS33"), Inverted()),
Misc("DRIVE=4"),
),
("lcd", 0,
Subsignal("db", Pins("J3 H1 K4 J1 K3 K2 L4 K1 L3 L2 M4 L1 M3 M1 N4 N2 N3 N1"), IOStandard("LVCMOS33")),
Subsignal("rd", Pins("P2"), IOStandard("LVCMOS33")),
Subsignal("wr", Pins("P4"), IOStandard("LVCMOS33")),
Subsignal("rs", Pins("P1"), IOStandard("LVCMOS33")),
Subsignal("cs", Pins("P3"), IOStandard("LVCMOS33")),
Subsignal("id", Pins("J4"), IOStandard("LVCMOS33")),
Subsignal("rst", Pins("H2"), IOStandard("LVCMOS33")),
Subsignal("fmark", Pins("G1"), IOStandard("LVCMOS33")),
Subsignal("blen", Pins("P5"), IOStandard("LVCMOS33")),
),
("spiflash", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("W2"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("V2"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("Y2"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("W1"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0, # clock needs to be accessed through USRMCLK
Subsignal("cs_n", Pins("R2"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("W2 V2 Y2 W1"), IOStandard("LVCMOS33")),
),
("spiram4x", 0,
Subsignal("cs_n", Pins("D20"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")),
Subsignal("clk", Pins("E20"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")),
Subsignal("dq", Pins("E19 D19 C20 F19"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP"), Misc("SLEWRATE=SLOW")),
),
("spiram4x", 1,
Subsignal("cs_n", Pins("F20"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")),
Subsignal("clk", Pins("J19"), IOStandard("LVCMOS33"), Misc("SLEWRATE=SLOW")),
Subsignal("dq", Pins("J20 G19 G20 H20"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP"), Misc("SLEWRATE=SLOW")),
),
("sao", 0,
Subsignal("sda", Pins("B3")),
Subsignal("scl", Pins("B2")),
Subsignal("gpio", Pins("A2 A3 B4")),
Subsignal("drm", Pins("A4")),
),
("sao", 1,
Subsignal("sda", Pins("A16")),
Subsignal("scl", Pins("B17")),
Subsignal("gpio", Pins("B18 A17 B16")),
Subsignal("drm", Pins("C17")),
),
("testpts", 0,
Subsignal("a1", Pins("A15")),
Subsignal("a2", Pins("C16")),
Subsignal("a3", Pins("A14")),
Subsignal("a4", Pins("D16")),
Subsignal("b1", Pins("B15")),
Subsignal("b2", Pins("C15")),
Subsignal("b3", Pins("A13")),
Subsignal("b4", Pins("B13")),
),
# Only used for simulation
("wishbone", 0,
Subsignal("adr", Pins(30)),
Subsignal("dat_r", Pins(32)),
Subsignal("dat_w", Pins(32)),
Subsignal("sel", Pins(4)),
Subsignal("cyc", Pins(1)),
Subsignal("stb", Pins(1)),
Subsignal("ack", Pins(1)),
Subsignal("we", Pins(1)),
Subsignal("cti", Pins(3)),
Subsignal("bte", Pins(2)),
Subsignal("err", Pins(1))
),
("reset", 0, Pins(1), IOStandard("LVCMOS33")),
]
_connectors = [
("pmod", "A15 C16 A14 D16 B15 C15 A13 B13"),
("genio", "C5 B5 A5 C6 B6 A6 D6 C7 A7 C8 B8 A8 D9 C9 B9 A9 D10 C10 B10 A10 D11 C11 B11 A11 G18 H17 B12 A12 E17 C14"),
]
_pmod_gpio = [
("pmod_gpio", 0,
Subsignal("p0", Pins("pmod:0")),
Subsignal("p1", Pins("pmod:1")),
Subsignal("p2", Pins("pmod:2")),
Subsignal("p3", Pins("pmod:3")),
Subsignal("p4", Pins("pmod:4")),
Subsignal("p5", Pins("pmod:5")),
Subsignal("p6", Pins("pmod:6")),
Subsignal("p7", Pins("pmod:7")),
IOStandard("LVCMOS33")
),
]
_genio_gpio = [
("genio_gpio", 0,
Subsignal("p0", Pins("genio:0")),
Subsignal("p1", Pins("genio:1")),
Subsignal("p2", Pins("genio:2")),
Subsignal("p3", Pins("genio:3")),
Subsignal("p4", Pins("genio:4")),
Subsignal("p5", Pins("genio:5")),
Subsignal("p6", Pins("genio:6")),
Subsignal("p7", Pins("genio:7")),
Subsignal("p8", Pins("genio:8")),
Subsignal("p9", Pins("genio:9")),
Subsignal("p10", Pins("genio:10")),
Subsignal("p11", Pins("genio:11")),
Subsignal("p12", Pins("genio:12")),
Subsignal("p13", Pins("genio:13")),
Subsignal("p14", Pins("genio:14")),
Subsignal("p15", Pins("genio:15")),
Subsignal("p16", Pins("genio:16")),
Subsignal("p17", Pins("genio:17")),
Subsignal("p18", Pins("genio:18")),
Subsignal("p19", Pins("genio:19")),
Subsignal("p20", Pins("genio:20")),
Subsignal("p21", Pins("genio:21")),
Subsignal("p22", Pins("genio:22")),
Subsignal("p23", Pins("genio:23")),
Subsignal("p24", Pins("genio:24")),
Subsignal("p25", Pins("genio:25")),
Subsignal("p26", Pins("genio:26")),
Subsignal("p27", Pins("genio:27")),
Subsignal("p28", Pins("genio:28")),
Subsignal("p29", Pins("genio:29")),
)
]
class GPIOBidirectional(Module, AutoCSR):
def __init__(self, pads, disable_i2c=False):
pad_count = len(pads)
self._pins_in = CSRStatus(pad_count)
self._pins_out = CSRStorage(pad_count)
self._pins_oe = CSRStorage(pad_count)
gpio_pins_t = [None] * pad_count
bit = 0
for pin_group in pads.layout:
if disable_i2c or (pin_group[0] != "scl" and pin_group[0] != "sda") :
for pin in getattr(pads, pin_group[0]):
gpio_pins_t[bit] = TSTriple()
self.specials += gpio_pins_t[bit].get_tristate(pin)
self.comb += gpio_pins_t[bit].o.eq(self._pins_out.storage[bit])
self.comb += gpio_pins_t[bit].oe.eq(self._pins_oe.storage[bit])
self.comb += self._pins_in.status[bit].eq(gpio_pins_t[bit].i)
bit=bit+1
else:
# skip i2c pins
bit=bit+1
class ShittyAddOn(Module, AutoCSR):
def __init__(self, platform, pads, disable_i2c=False):
pad_count = len(pads)
if not disable_i2c:
self.i2c_master = I2CMaster(pads)
self.gpio = GPIOBidirectional(pads, disable_i2c)
def get_fragment(self):
fragment = super().get_fragment()
if getattr(self, "i2c_master", None):
fragment += self.i2c_master.get_fragment()
fragment += self.gpio.get_fragment()
return fragment
class CocotbPlatform(SimPlatform):
def __init__(self, toolchain="verilator"):
SimPlatform.__init__(self, "sim", _io, _connectors, toolchain="verilator")
def create_programmer(self):
raise ValueError("programming is not supported")
class _CRG(Module):
def __init__(self, platform):
clk8 = platform.request("clk8")
rst = platform.request("reset")
clk12 = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_clk12 = ClockDomain()
self.clock_domains.cd_clk48 = ClockDomain()
self.clock_domains.cd_clk48_to_clk12 = ClockDomain()
clk48 = clk8 # We actually run this at 48 MHz
self.comb += self.cd_clk48.clk.eq(clk48)
self.comb += self.cd_clk48_to_clk12.clk.eq(clk48)
clk12_counter = Signal(2)
self.sync.clk48_to_clk12 += clk12_counter.eq(clk12_counter + 1)
self.comb += clk12.eq(clk12_counter[1])
self.comb += self.cd_sys.clk.eq(clk48)
self.comb += self.cd_clk12.clk.eq(clk12)
self.comb += [
ResetSignal("sys").eq(rst),
ResetSignal("clk12").eq(rst),
ResetSignal("clk48").eq(rst),
]
def add_fsm_state_names():
"""Hack the FSM module to add state names to the output"""
from migen.fhdl.visit import NodeTransformer
from migen.genlib.fsm import NextState, NextValue, _target_eq
from migen.fhdl.bitcontainer import value_bits_sign
class My_LowerNext(NodeTransformer):
def __init__(self, next_state_signal, next_state_name_signal, encoding, aliases):
self.next_state_signal = next_state_signal
self.next_state_name_signal = next_state_name_signal
self.encoding = encoding
self.aliases = aliases
# (target, next_value_ce, next_value)
self.registers = []
def _get_register_control(self, target):
for x in self.registers:
if _target_eq(target, x[0]):
return x[1], x[2]
raise KeyError
def visit_unknown(self, node):
if isinstance(node, NextState):
try:
actual_state = self.aliases[node.state]
except KeyError:
actual_state = node.state
return [
self.next_state_signal.eq(self.encoding[actual_state]),
self.next_state_name_signal.eq(int.from_bytes(actual_state.encode(), byteorder="big"))
]
elif isinstance(node, NextValue):
try:
next_value_ce, next_value = self._get_register_control(node.target)
except KeyError:
related = node.target if isinstance(node.target, Signal) else None
next_value = Signal(bits_sign=value_bits_sign(node.target), related=related)
next_value_ce = Signal(related=related)
self.registers.append((node.target, next_value_ce, next_value))
return next_value.eq(node.value), next_value_ce.eq(1)
else:
return node
import migen.genlib.fsm as fsm
def my_lower_controls(self):
self.state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big"))
self.next_state_name = Signal(len(max(self.encoding,key=len))*8, reset=int.from_bytes(self.reset_state.encode(), byteorder="big"))
self.comb += self.next_state_name.eq(self.state_name)
self.sync += self.state_name.eq(self.next_state_name)
return My_LowerNext(self.next_state, self.next_state_name, self.encoding, self.state_aliases)
fsm.FSM._lower_controls = my_lower_controls
class BadgePlatform(LatticePlatform):
def __init__(self):
LatticePlatform.__init__(self, device="LFE5U-45F-CABGA381", io=_io, connectors=_connectors, toolchain="trellis")
def create_programmer(self):
raise ValueError("{} programmer is not supported"
.format(self.programmer))
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
class BaseSoC(SoCCore, AutoDoc):
SoCCore.csr_map = {
"ctrl": 0, # provided by default (optional)
"crg": 1, # user
"uart_phy": 2, # provided by default (optional)
"uart": 3, # provided by default (optional)
"identifier_mem": 4, # provided by default (optional)
"timer0": 5, # provided by default (optional)
"lcdif": 8,
"usb": 9,
"picorvspi": 10,
"reboot": 12,
"rgb": 13,
"version": 14,
"lxspi": 15,
"messible": 16,
}
# We must define memory offsets here rather than using the litex
# defaults. This is because the mmu only allows for certain
# regions to be unbuffered:
# https://github.com/m-labs/VexRiscv-verilog/blob/master/src/main/scala/vexriscv/GenCoreDefault.scala#L139-L143
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x10000000,
"spiflash": 0x20000000,
"ethmac": 0x30000000,
"main_ram": 0x40000000,
"emulator_ram": 0x50000000,
"csr": 0xe0000000,
}
interrupt_map = {
"timer0": 2,
"usb": 3,
}
interrupt_map.update(SoCCore.interrupt_map)
def __init__(self, platform, is_sim=False, debug=True, **kwargs):
clk_freq = int(12e6)
SoCCore.__init__(self, platform, clk_freq,
integrated_rom_size=16384,
integrated_sram_size=131072,
with_uart=True, uart_stub=True,
**kwargs)
if is_sim:
self.submodules.crg = CocotbPlatform._CRG(self.platform)
else:
self.submodules.crg = _CRG(self.platform, fast_sysclk=False)
# Add a "Version" module so we can see what version of the board this is.
self.submodules.version = Version("proto2", [
(0x02, "proto2", "Prototype Version 2 (red)")
], 0)
# Add a "USB" module to let us debug the device.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb = ClockDomainsRenamer({
"usb_48": "clk48",
"usb_12": "clk12",
# })(DummyUsb(usb_iobuf, debug=debug, product="Hackaday Supercon Badge", cdc=True))
})(TriEndpointInterface(usb_iobuf, debug=debug))
if debug:
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
self.add_wb_master(self.usb.debug_bridge.wishbone)
if self.cpu_type is not None:
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x200)
self.cpu.use_external_variant("rtl/VexRiscv_HaD_Debug.v")
elif self.cpu_type is not None:
self.cpu.use_external_variant("rtl/VexRiscv_HaD.v")
# Add the 16 MB SPI flash as XIP memory at address 0x03000000
if not is_sim:
flash = SpiFlashDualQuad(platform.request("spiflash4x"), dummy=6, endianness="little")
flash.add_clk_primitive(self.platform.device)
self.submodules.lxspi = flash
self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=16 * 1024 * 1024)
# self.submodules.picorvspi = flash = PicoRVSpi(self.platform, pads=platform.request("spiflash"), size=16 * 1024 * 1024)
# self.register_mem("spiflash", self.mem_map["spiflash"], self.picorvspi.bus, size=self.picorvspi.size)
self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["spiflash"] + 0x300000)
# # Add the 16 MB SPI RAM at address 0x40000000 # Value at 40010000: afbfcfef
reset_cycles = 2**14-1
if is_sim:
reset_cycles = 0
ram = SpiRamDualQuad(platform.request("spiram4x", 0), platform.request("spiram4x", 1), dummy=5, reset_cycles=reset_cycles, qpi=True)
self.submodules.ram = ram
self.register_mem("main_ram", self.mem_map["main_ram"], self.ram.bus, size=16 * 1024 * 1024)
# Let us reboot the device
self.submodules.reboot = Reboot(platform.request("programn"))
# Add a Messible for sending messages to the host
self.submodules.messible = Messible()
# Add an LCD so we can see what's up
self.submodules.lcdif = LCDIF(platform.request("lcd"))
# Ensure timing is correctly set up
if not is_sim:
self.platform.toolchain.build_template[1] += " --speed 8" # Add "speed grade 8" to nextpnr-ecp5
self.platform.toolchain.freq_constraints["sys"] = 48
if is_sim:
self.add_wb_master(self.platform.request("wishbone"))
# SAO
self.submodules.sao0 = ShittyAddOn(self.platform, self.platform.request("sao", 0), disable_i2c=kwargs["sao0_disable_i2c"]);
self.add_csr("sao0")
self.submodules.sao1 = ShittyAddOn(self.platform, self.platform.request("sao", 1), disable_i2c=kwargs["sao1_disable_i2c"]);
self.add_csr("sao1")
# PMOD
platform.add_extension(_pmod_gpio)
self.submodules.pmod = GPIOBidirectional(self.platform.request("pmod_gpio"))
self.add_csr("pmod")
# GENIO
platform.add_extension(_genio_gpio)
self.submodules.genio = GPIOBidirectional(self.platform.request("genio_gpio"))
self.add_csr("genio")
# LEDs
self.submodules.led0 = gpio.GPIOOut(self.platform.request("led", 0))
self.add_csr("led0")
self.submodules.led1 = gpio.GPIOOut(self.platform.request("led", 1))
self.add_csr("led1")
# Keypad
self.submodules.keypad = gpio.GPIOIn(Cat(self.platform.request("keypad", 0).flatten()))
self.add_csr("keypad")
def main():
parser = argparse.ArgumentParser(description="Build the Hack a Day Supercon 2019 Badge firmware")
parser.add_argument(
"-D", "--document-only", action="store_true", help="don't build software or gateware, only build documentation",
)
parser.add_argument(
"--sim", help="generate files for simulation", action="store_true"
)
parser.add_argument(
"--no-cpu", help="don't generate a cpu", action="store_true"
)
parser.add_argument(
"--no-debug", help="don't generate the debug bus", action="store_true"
)
parser.add_argument(
"--sao0-disable-i2c", help="Disable i2c on sao0", action="store_true"
)
parser.add_argument(
"--sao1-disable-i2c", help="Disable i2c on sao1", action="store_true"
)
args = parser.parse_args()
compile_gateware = True
compile_software = True
if args.sim:
compile_gateware = False
compile_software = False
platform = CocotbPlatform()
CocotbPlatform.add_fsm_state_names()
else:
platform = BadgePlatform()
if args.document_only:
compile_gateware = False
compile_software = False
cpu_type = "vexriscv"
cpu_variant = "min+debug"
if args.no_debug:
cpu_variant = "min"
if args.no_cpu or args.sim:
cpu_type = None
cpu_variant = None
soc = BaseSoC(platform, is_sim=args.sim, debug=not args.no_debug,
cpu_type=cpu_type, cpu_variant=cpu_variant,
sao0_disable_i2c=args.sao0_disable_i2c,
sao1_disable_i2c=args.sao1_disable_i2c,
)
builder = Builder(soc, output_dir="build",
csr_csv="build/csr.csv",
csr_json="build/csr.json",
compile_software=compile_software,
compile_gateware=compile_gateware)
# # If we comile software, pull the code from somewhere other than
# # the built-in litex "bios" binary, which makes assumptions about
# # what peripherals are available.
# if compile_software:
# builder.software_packages = [
# ("bios", os.path.abspath(os.path.join(os.path.dirname(__file__), "rom")))
# ]
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc, builder.output_dir + "/documentation", project_name="Hack a Day Supercon 2019 Badge", author="Sean \"<NAME>")
lxsocdoc.generate_svd(soc, "build/software", vendor="Foosn", name="Fomu", description="Hack a Day Supercon 2019 Badge")
if __name__ == "__main__":
main()
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"litex.build.generic_platform.Pins",
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#!/usr/bin/env python3
import argparse
from migen import *
from litex_boards.platforms import zcu104
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.integration.builder import Builder
from litex.soc.integration.soc_core import colorer
from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, AsyncResetSynchronizer
from litex.soc.interconnect import axi, wishbone
from litedram.phy import usddrphy
from liteeth.phy.usrgmii import LiteEthPHYRGMII
from rowhammer_tester.targets import common
# CRG ----------------------------------------------------------------------------------------------
class CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_uart = ClockDomain()
# # #
self.submodules.pll = pll = USMMCM(speedgrade=-2)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
pll.create_clkout(self.cd_uart, sys_clk_freq, with_reset=False)
self.specials += [
Instance("BUFGCE_DIV", name="main_bufgce_div",
p_BUFGCE_DIVIDE=4,
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk),
Instance("BUFGCE", name="main_bufgce",
i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk),
AsyncResetSynchronizer(self.cd_idelay, ~pll.locked),
]
self.submodules.idelayctrl = USIDELAYCTRL(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)
# SoC ----------------------------------------------------------------------------------------------
class ZynqUSPS(Module):
# For full address map see UG1085, ZynqUS+ TRM, Table 10-1
_KB = 2**10
_MB = 2**10 * _KB
_GB = 2**10 * _MB
PS_MEMORY_MAP = {
'gp_lpd_master': [[
# M_AXI_HPM0_LPD
# (base, size)
(0x8000_0000, 512*_MB),
]],
'gp_fpd_master': [
[ # M_AXI_HPM0_FPD regions
( 0xa400_0000, 192*_MB), # (32-bit), may be different (see TRM notes)
(0x0004_0000_0000, 4*_GB), # (36-bit)
(0x0010_0000_0000, 224*_GB), # (40-bit)
],
[ # M_AXI_HPM1_FPD regions
( 0xb000_0000, 256*_MB), # (32-bit)
(0x0005_0000_0000, 4*_GB), # (36-bit)
(0x0048_0000_0000, 224*_GB), # (40-bit)
],
],
}
def __init__(self):
self.params = {}
# fpd/lpd = full/low power domain
self.axi_gp_fpd_masters = []
self.axi_gp_lpd_masters = []
self.axi_gp_fpd_slaves = []
self.axi_gp_lpd_slaves = []
self.axi_acp_fpd_slaves = []
def add_axi_gp_fpd_master(self, **kwargs): # MAXIGP0 - MAXIGP1
return self._append_axi(attr='axi_gp_fpd_masters', maxn=2, name='MAXIGP{n}', **kwargs)
def add_axi_gp_lpd_master(self, **kwargs): # MAXIGP2
return self._append_axi(attr='axi_gp_lpd_masters', maxn=1, name='MAXIGP2', **kwargs)
def add_axi_gp_fpd_slave(self, **kwargs): # SAXIGP0 - SAXIGP5
return self._append_axi(attr='axi_gp_fpd_slaves', maxn=6, name='SAXIGP{n}', **kwargs)
def add_axi_gp_lpd_slave(self, **kwargs): # SAXIGP6
return self._append_axi(attr='axi_gp_lpd_slaves', maxn=1, name='SAXIGP6', **kwargs)
def add_axi_acp_fpd_slave(self, **kwargs): # SAXIACP
return self._append_axi(attr='axi_acp_fpd_slaves', maxn=1, name='SAXIACP', **kwargs)
def _append_axi(self, attr, maxn, name, **kwargs):
axis = getattr(self, attr)
n = len(axis)
assert n < maxn, 'Maximum number of AXIs for {} is {}'.format(attr, maxn)
ax = self._add_axi(name=name.format(n=n), **kwargs)
axis.append(ax)
return ax
def _add_axi(self, name, data_width=128, address_width=40, id_width=16):
assert data_width <= 128
assert address_width <= 40
assert id_width <= 16
ax = axi.AXIInterface(data_width=data_width, address_width=address_width, id_width=id_width)
self.params.update({
f'o_{name}ACLK': ClockSignal(),
# aw
f'o_{name}AWVALID': ax.aw.valid,
f'i_{name}AWREADY': ax.aw.ready,
f'o_{name}AWADDR': ax.aw.addr,
f'o_{name}AWBURST': ax.aw.burst,
f'o_{name}AWLEN': ax.aw.len,
f'o_{name}AWSIZE': ax.aw.size[:3], # need to match size exactly
f'o_{name}AWID': ax.aw.id,
f'o_{name}AWLOCK': ax.aw.lock[:1], # need to match size exactly
f'o_{name}AWPROT': ax.aw.prot,
f'o_{name}AWCACHE': ax.aw.cache,
f'o_{name}AWQOS': ax.aw.qos,
# w
f'o_{name}WVALID': ax.w.valid,
f'o_{name}WLAST': ax.w.last,
f'i_{name}WREADY': ax.w.ready,
# f'o_{name}WID': ax.w.id, # does not exist
f'o_{name}WDATA': ax.w.data,
f'o_{name}WSTRB': ax.w.strb,
# b
f'i_{name}BVALID': ax.b.valid,
f'o_{name}BREADY': ax.b.ready,
f'i_{name}BID': ax.b.id,
f'i_{name}BRESP': ax.b.resp,
# ar
f'o_{name}ARVALID': ax.ar.valid,
f'i_{name}ARREADY': ax.ar.ready,
f'o_{name}ARADDR': ax.ar.addr,
f'o_{name}ARBURST': ax.ar.burst,
f'o_{name}ARLEN': ax.ar.len,
f'o_{name}ARID': ax.ar.id,
f'o_{name}ARLOCK': ax.ar.lock[:1],
f'o_{name}ARSIZE': ax.ar.size[:3],
f'o_{name}ARPROT': ax.ar.prot,
f'o_{name}ARCACHE': ax.ar.cache,
f'o_{name}ARQOS': ax.ar.qos,
# r
f'i_{name}RVALID': ax.r.valid,
f'o_{name}RREADY': ax.r.ready,
f'i_{name}RLAST': ax.r.last,
f'i_{name}RID': ax.r.id,
f'i_{name}RRESP': ax.r.resp,
f'i_{name}RDATA': ax.r.data,
})
return ax
def do_finalize(self):
self.specials += Instance('PS8', **self.params)
class SoC(common.RowHammerSoC):
def __init__(self, **kwargs):
super().__init__(**kwargs)
# ZynqUS+ PS -------------------------------------------------------------------------------
if not self.args.sim:
# Add Zynq US+ PS wrapper
self.submodules.ps = ZynqUSPS()
# Configure PS->PL AXI
# AXI(128) -> AXILite(128) -> AXILite(32) -> WishBone(32) -> SoC Interconnect
axi_ps = self.ps.add_axi_gp_fpd_master()
axi_lite_ps = axi.AXILiteInterface(data_width=axi_ps.data_width, address_width=axi_ps.address_width)
self.submodules += axi.AXI2AXILite(axi_ps, axi_lite_ps)
axi_lite_ps_32 = axi.AXILiteInterface(data_width=32, address_width=40)
self.submodules += axi.AXILiteConverter(axi_lite_ps, axi_lite_ps_32)
# Use M_AXI_HPM0_FPD base address thaht will fit our whole address space (0x0004_0000_0000)
base_address = None
for base, size in self.ps.PS_MEMORY_MAP['gp_fpd_master'][0]:
if size >= 2**30-1:
base_address = base
break
assert base_address is not None
def chunks(lst, n):
for i in range(0, len(lst), n):
yield lst[i:i + n]
addr_str = '_'.join(chunks('{:012x}'.format(base_address), 4))
self.logger.info("Connecting PS AXI master from PS address {}.".format(colorer('0x' + addr_str)))
wb_ps = wishbone.Interface(adr_width=40-2) # AXILite2Wishbone requires the same address widths
self.submodules += axi.AXILite2Wishbone(axi_lite_ps_32, wb_ps, base_address=base_address)
# silently ignores address bits above 30
self.bus.add_master(name='ps_axi', master=wb_ps)
def get_platform(self):
return zcu104.Platform()
def get_crg(self):
return CRG(self.platform, self.sys_clk_freq)
def get_ddrphy(self):
return usddrphy.USPDDRPHY(
pads = self.platform.request("ddram"),
memtype = "DDR4",
sys_clk_freq = self.sys_clk_freq,
iodelay_clk_freq = 500e6)
def get_sdram_module(self):
return self.sdram_module_cls(self.sys_clk_freq, "1:4")
def add_host_bridge(self):
self.add_uartbone(name="serial", clk_freq=self.sys_clk_freq, baudrate=1e6, cd="uart")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104")
common.parser_args(parser, sys_clk_freq='125e6', module='MTA4ATF51264HZ')
vivado_build_args(parser)
args = parser.parse_args()
soc_kwargs = common.get_soc_kwargs(args)
soc = SoC(**soc_kwargs)
target_name = 'zcu104'
builder_kwargs = common.get_builder_kwargs(args, target_name=target_name)
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args) if not args.sim else {}
common.run(args, builder, build_kwargs, target_name=target_name)
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.axi.AXILite2Wishbone",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.axi.AXI2AXILite",
"litex.soc.cores.clock.AsyncResetSynchronizer",
"litex.soc.cores.clock.USIDELAYCTRL",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.builder.Builde... | [((9079, 9137), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on ZCU104"""'}), "(description='LiteX SoC on ZCU104')\n", (9102, 9137), False, 'import argparse\n'), ((9143, 9216), 'rowhammer_tester.targets.common.parser_args', 'common.parser_args', (['parser'], {'sys_clk_freq': '"""125e6"""', 'module': '"""MTA4ATF51264HZ"""'}), "(parser, sys_clk_freq='125e6', module='MTA4ATF51264HZ')\n", (9161, 9216), False, 'from rowhammer_tester.targets import common\n'), ((9221, 9246), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (9238, 9246), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((9296, 9323), 'rowhammer_tester.targets.common.get_soc_kwargs', 'common.get_soc_kwargs', (['args'], {}), '(args)\n', (9317, 9323), False, 'from rowhammer_tester.targets import common\n'), ((9401, 9457), 'rowhammer_tester.targets.common.get_builder_kwargs', 'common.get_builder_kwargs', (['args'], {'target_name': 'target_name'}), '(args, target_name=target_name)\n', (9426, 9457), False, 'from rowhammer_tester.targets import common\n'), ((9472, 9502), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {}), '(soc, **builder_kwargs)\n', (9479, 9502), False, 'from litex.soc.integration.builder import Builder\n'), ((9578, 9642), 'rowhammer_tester.targets.common.run', 'common.run', (['args', 'builder', 'build_kwargs'], {'target_name': 'target_name'}), '(args, builder, build_kwargs, target_name=target_name)\n', (9588, 9642), False, 'from rowhammer_tester.targets import common\n'), ((1085, 1106), 'litex.soc.cores.clock.USMMCM', 'USMMCM', ([], {'speedgrade': '(-2)'}), '(speedgrade=-2)\n', (1091, 1106), False, 'from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, AsyncResetSynchronizer\n'), ((1863, 1918), 'litex.soc.cores.clock.USIDELAYCTRL', 'USIDELAYCTRL', ([], {'cd_ref': 'self.cd_idelay', 'cd_sys': 'self.cd_sys'}), '(cd_ref=self.cd_idelay, cd_sys=self.cd_sys)\n', (1875, 1918), False, 'from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, AsyncResetSynchronizer\n'), ((4397, 4488), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': 'data_width', 'address_width': 'address_width', 'id_width': 'id_width'}), '(data_width=data_width, address_width=address_width,\n id_width=id_width)\n', (4413, 4488), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((8382, 8399), 'litex_boards.platforms.zcu104.Platform', 'zcu104.Platform', ([], {}), '()\n', (8397, 8399), False, 'from litex_boards.platforms import zcu104\n'), ((9522, 9548), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (9542, 9548), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((1762, 1813), 'litex.soc.cores.clock.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_idelay', '(~pll.locked)'], {}), '(self.cd_idelay, ~pll.locked)\n', (1784, 1813), False, 'from litex.soc.cores.clock import USMMCM, USIDELAYCTRL, AsyncResetSynchronizer\n'), ((7031, 7122), 'litex.soc.interconnect.axi.AXILiteInterface', 'axi.AXILiteInterface', ([], {'data_width': 'axi_ps.data_width', 'address_width': 'axi_ps.address_width'}), '(data_width=axi_ps.data_width, address_width=axi_ps.\n address_width)\n', (7051, 7122), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((7149, 7185), 'litex.soc.interconnect.axi.AXI2AXILite', 'axi.AXI2AXILite', (['axi_ps', 'axi_lite_ps'], {}), '(axi_ps, axi_lite_ps)\n', (7164, 7185), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((7216, 7269), 'litex.soc.interconnect.axi.AXILiteInterface', 'axi.AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(40)'}), '(data_width=32, address_width=40)\n', (7236, 7269), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((7301, 7350), 'litex.soc.interconnect.axi.AXILiteConverter', 'axi.AXILiteConverter', (['axi_lite_ps', 'axi_lite_ps_32'], {}), '(axi_lite_ps, axi_lite_ps_32)\n', (7321, 7350), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((8034, 8070), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'adr_width': '(40 - 2)'}), '(adr_width=40 - 2)\n', (8052, 8070), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((8153, 8223), 'litex.soc.interconnect.axi.AXILite2Wishbone', 'axi.AXILite2Wishbone', (['axi_lite_ps_32', 'wb_ps'], {'base_address': 'base_address'}), '(axi_lite_ps_32, wb_ps, base_address=base_address)\n', (8173, 8223), False, 'from litex.soc.interconnect import axi, wishbone\n'), ((7986, 8010), 'litex.soc.integration.soc_core.colorer', 'colorer', (["('0x' + addr_str)"], {}), "('0x' + addr_str)\n", (7993, 8010), False, 'from litex.soc.integration.soc_core import colorer\n')] |
# This file is Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from migen.genlib.roundrobin import *
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from litex.gen import *
from litex.soc.interconnect import stream
# TODO: clean up code below
# XXX
class Status(Module):
def __init__(self, endpoint):
self.first = first = Signal(reset=1)
self.last = last = Signal()
self.ongoing = Signal()
ongoing = Signal()
self.comb += \
If(endpoint.valid,
last.eq(endpoint.last & endpoint.ready)
)
self.sync += ongoing.eq((endpoint.valid | ongoing) & ~last)
self.comb += self.ongoing.eq((endpoint.valid | ongoing) & ~last)
self.sync += [
If(last,
first.eq(1)
).Elif(endpoint.valid & endpoint.ready,
first.eq(0)
)
]
class Arbiter(Module):
def __init__(self, masters, slave):
if len(masters) == 0:
pass
elif len(masters) == 1:
self.grant = Signal()
self.comb += masters.pop().connect(slave)
else:
self.submodules.rr = RoundRobin(len(masters))
self.grant = self.rr.grant
cases = {}
for i, master in enumerate(masters):
status = Status(master)
self.submodules += status
self.comb += self.rr.request[i].eq(status.ongoing)
cases[i] = [master.connect(slave)]
self.comb += Case(self.grant, cases)
class Dispatcher(Module):
def __init__(self, master, slaves, one_hot=False):
if len(slaves) == 0:
self.sel = Signal()
elif len(slaves) == 1:
self.comb += master.connect(slaves.pop())
self.sel = Signal()
else:
if one_hot:
self.sel = Signal(len(slaves))
else:
self.sel = Signal(max=len(slaves))
# # #
status = Status(master)
self.submodules += status
sel = Signal.like(self.sel)
sel_ongoing = Signal.like(self.sel)
self.sync += \
If(status.first,
sel_ongoing.eq(self.sel)
)
self.comb += \
If(status.first,
sel.eq(self.sel)
).Else(
sel.eq(sel_ongoing)
)
cases = {}
for i, slave in enumerate(slaves):
if one_hot:
idx = 2**i
else:
idx = i
cases[idx] = [master.connect(slave)]
cases["default"] = [master.ready.eq(1)]
self.comb += Case(sel, cases)
class HeaderField:
def __init__(self, byte, offset, width):
self.byte = byte
self.offset = offset
self.width = width
class Header:
def __init__(self, fields, length, swap_field_bytes=True):
self.fields = fields
self.length = length
self.swap_field_bytes = swap_field_bytes
def get_layout(self):
layout = []
for k, v in sorted(self.fields.items()):
layout.append((k, v.width))
return layout
def get_field(self, obj, name, width):
if "_lsb" in name:
field = getattr(obj, name.replace("_lsb", ""))[:width]
elif "_msb" in name:
field = getattr(obj, name.replace("_msb", ""))[width:2*width]
else:
field = getattr(obj, name)
if len(field) != width:
raise ValueError("Width mismatch on " + name + " field")
return field
def encode(self, obj, signal):
r = []
for k, v in sorted(self.fields.items()):
start = v.byte*8 + v.offset
end = start + v.width
field = self.get_field(obj, k, v.width)
if self.swap_field_bytes:
field = reverse_bytes(field)
r.append(signal[start:end].eq(field))
return r
def decode(self, signal, obj):
r = []
for k, v in sorted(self.fields.items()):
start = v.byte*8 + v.offset
end = start + v.width
field = self.get_field(obj, k, v.width)
if self.swap_field_bytes:
r.append(field.eq(reverse_bytes(signal[start:end])))
else:
r.append(field.eq(signal[start:end]))
return r
class Packetizer(Module):
def __init__(self, sink_description, source_description, header):
self.sink = sink = stream.Endpoint(sink_description)
self.source = source = stream.Endpoint(source_description)
self.header = Signal(header.length*8)
# # #
dw = len(self.sink.data)
header_reg = Signal(header.length*8, reset_less=True)
header_words = (header.length*8)//dw
load = Signal()
shift = Signal()
counter = Signal(max=max(header_words, 2))
counter_reset = Signal()
counter_ce = Signal()
self.sync += \
If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
self.comb += header.encode(sink, self.header)
if header_words == 1:
self.sync += [
If(load,
header_reg.eq(self.header)
)
]
else:
self.sync += [
If(load,
header_reg.eq(self.header)
).Elif(shift,
header_reg.eq(Cat(header_reg[dw:], Signal(dw)))
)
]
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
if header_words == 1:
idle_next_state = "COPY"
else:
idle_next_state = "SEND_HEADER"
fsm.act("IDLE",
sink.ready.eq(1),
counter_reset.eq(1),
If(sink.valid,
sink.ready.eq(0),
source.valid.eq(1),
source.last.eq(0),
source.data.eq(self.header[:dw]),
If(source.valid & source.ready,
load.eq(1),
NextState(idle_next_state)
)
)
)
if header_words != 1:
fsm.act("SEND_HEADER",
source.valid.eq(1),
source.last.eq(0),
source.data.eq(header_reg[dw:2*dw]),
If(source.valid & source.ready,
shift.eq(1),
counter_ce.eq(1),
If(counter == header_words-2,
NextState("COPY")
)
)
)
if hasattr(sink, "error"):
self.comb += source.error.eq(sink.error)
fsm.act("COPY",
source.valid.eq(sink.valid),
source.last.eq(sink.last),
source.data.eq(sink.data),
If(source.valid & source.ready,
sink.ready.eq(1),
If(source.last,
NextState("IDLE")
)
)
)
class Depacketizer(Module):
def __init__(self, sink_description, source_description, header):
self.sink = sink = stream.Endpoint(sink_description)
self.source = source = stream.Endpoint(source_description)
self.header = Signal(header.length*8)
# # #
dw = len(sink.data)
header_reg = Signal(header.length*8, reset_less=True)
header_words = (header.length*8)//dw
shift = Signal()
counter = Signal(max=max(header_words, 2))
counter_reset = Signal()
counter_ce = Signal()
self.sync += \
If(counter_reset,
counter.eq(0)
).Elif(counter_ce,
counter.eq(counter + 1)
)
if header_words == 1:
self.sync += \
If(shift,
header_reg.eq(sink.data)
)
else:
self.sync += \
If(shift,
header_reg.eq(Cat(header_reg[dw:], sink.data))
)
self.comb += self.header.eq(header_reg)
fsm = FSM(reset_state="IDLE")
self.submodules += fsm
if header_words == 1:
idle_next_state = "COPY"
else:
idle_next_state = "RECEIVE_HEADER"
fsm.act("IDLE",
sink.ready.eq(1),
counter_reset.eq(1),
If(sink.valid,
shift.eq(1),
NextState(idle_next_state)
)
)
if header_words != 1:
fsm.act("RECEIVE_HEADER",
sink.ready.eq(1),
If(sink.valid,
counter_ce.eq(1),
shift.eq(1),
If(counter == header_words-2,
NextState("COPY")
)
)
)
no_payload = Signal()
self.sync += \
If(fsm.before_entering("COPY"),
no_payload.eq(sink.last)
)
if hasattr(sink, "error"):
self.comb += source.error.eq(sink.error)
self.comb += [
source.last.eq(sink.last | no_payload),
source.data.eq(sink.data),
header.decode(self.header, source)
]
fsm.act("COPY",
sink.ready.eq(source.ready),
source.valid.eq(sink.valid | no_payload),
If(source.valid & source.ready & source.last,
NextState("IDLE")
)
)
# XXX
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from migen import *
from migen.genlib.io import CRG
from targets import *
from litex.build.generic_platform import *
from litex.build.xilinx.platform import XilinxPlatform
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer
_io = [
("sys_clock", 0, Pins(1)),
("sys_reset", 1, Pins(1)),
("serial", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
),
("bus", 0, Pins(128))
]
class CorePlatform(XilinxPlatform):
name = "core"
default_clk_name = "sys_clk"
def __init__(self):
XilinxPlatform.__init__(self, "", _io)
def do_finalize(self, *args, **kwargs):
pass
class Core(SoCCore):
platform = CorePlatform()
csr_map = {
"analyzer": 16
}
csr_map.update(SoCCore.csr_map)
def __init__(self, platform, clk_freq=100*1000000):
self.clock_domains.cd_sys = ClockDomain("sys")
self.comb += [
self.cd_sys.clk.eq(platform.request("sys_clock")),
self.cd_sys.rst.eq(platform.request("sys_reset"))
]
SoCCore.__init__(self, platform, clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
ident="Litescope example design",
with_timer=False
)
self.add_cpu_or_bridge(UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
self.bus = platform.request("bus")
self.submodules.analyzer = LiteScopeAnalyzer((self.bus), 512)
default_subtarget = Core
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("H4"), IOStandard("LVCMOS33")),
("rst_n", 0, Pins("D14"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("J1"), IOStandard("LVCMOS33")), # Green.
("user_led", 1, Pins("A13"), IOStandard("LVCMOS33")), # Red.
# RGB Leds (2 X SK6805 Leds)
("rgb", 0, Pins("N11"),IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("C3"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("M4"), IOStandard("LVCMOS33")),
# Mini HDMI
("hdmi", 0,
Subsignal("clk_p", Pins("G4"),IOStandard("LVCMOS33")),
Subsignal("clk_n", Pins("F4"),IOStandard("LVCMOS33")),
Subsignal("data0_p", Pins("G1"),IOStandard("LVCMOS33")),
Subsignal("data0_n", Pins("F1"),IOStandard("LVCMOS33")),
Subsignal("data1_p", Pins("E2"),IOStandard("LVCMOS33")),
Subsignal("data1_n", Pins("D2"),IOStandard("LVCMOS33")),
Subsignal("data2_p", Pins("D1"),IOStandard("LVCMOS33")),
Subsignal("data2_n", Pins("C1"),IOStandard("LVCMOS33")),
Subsignal("scl", Pins("F3"),IOStandard("LVCMOS33")),
Subsignal("sda", Pins("F2"),IOStandard("LVCMOS33")),
Subsignal("hpd", Pins("D4"),IOStandard("LVCMOS33")),
Subsignal("cec", Pins("E4"),IOStandard("LVCMOS33"))
),
# MIPI (Untested)
("mipi", 0,
Subsignal("clkp", Pins("G11"), IOStandard("MIPI_DPHY")),
Subsignal("clkn", Pins("F11"), IOStandard("LVCMOS12H")),
Subsignal("dp", Pins("J11 P10"), IOStandard("MIPI_DPHY")),
Subsignal("dn", Pins("J12 P11"), IOStandard("LVCMOS12H")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("j10", {
"j10_0" : "N14",
"j10_1" : "M14",
"j10_2" : "C4",
"j10_3" : "B13",
"j10_4" : "N10",
"j10_5" : "M10",
"j10_6" : "B14",
"j10_7" : "D3",
"j10_8" : "P5",
"j10_9" : "E11",
}
),
("digital_d2",{
"d2_0" : "A10",
"d2_1" : "B6",
}),
("i2c", "P12 P13"), # SCL, SDA
("ar_io", {
# Outer Digital Header
"d0" : "A12",
"d1" : "C12",
"d2" : "A10",
"d3" : "B6",
"d4" : "A5",
"d5" : "B5",
"d6" : "A4",
"d7" : "A3",
"d8" : "B3",
"d9" : "A2",
"d10" : "B2",
"d11" : "B1",
"d12" : "H1",
"d13" : "H2",
# Outer Analog Header as Digital IO
"a0" : "F5",
"a1" : "D8",
"a2" : "C7",
"a3" : "E7",
"a4" : "D7",
"a5" : "D5",
} )
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7s15-ftgb196", _io, _connectors, toolchain="vivado")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
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import logging
Logger = logging.getLogger(__name__)
import socket
import sys
import time
import numpy as np
from litex import RemoteClient
from misc import ADC, DataBlock
from banyan_ch_find import banyan_ch_find
from get_raw_adcs import collect_adcs
from zest_setup import c_prc
from ltc_setup_litex_client import initLTC, get_data
class Carrier():
def test_data(self, *args):
while True:
# https://docs.python.org/3/tutorial/classes.html#private-variables
self._db = DataBlock(
np.array([np.random.random_sample(self.pts_per_ch)
for _ in range(self.n_channels)]),
time.time())
self._process_subscriptions()
time.sleep(0.2)
def acquire_data(self, *args):
raise NotImplementedError
def _process_subscriptions(self):
# TODO: Perhaps implement something to avoid race condition on results
for sub_id, (single_subscribe, fn, *fn_args) in list(self.subscriptions.items()):
self.results[sub_id] = fn(self._db, *fn_args)
if single_subscribe:
self.remove_subscription(sub_id)
def add_subscription(self, sub_id, fn, *fn_args, single_subscribe=False):
# TODO: Add args/kwargs to the function
self.subscriptions[sub_id] = (single_subscribe, fn, *fn_args)
Logger.info('Added subscription {}'.format(sub_id))
def remove_subscription(self, sub_id):
self.subscriptions.pop(sub_id)
Logger.info('Removed subscription {}'.format(sub_id))
class LTCOnMarblemini(Carrier):
def __init__(self,
count=10,
log_decimation_factor=0,
test=False):
ADC.bits = 14
ADC.sample_rate = 120000000.
self.n_channels = 2
self._db = None
self.test = test
self.pts_per_ch = 8192
self.subscriptions, self.results = {}, {}
self.set_log_decimation_factor(log_decimation_factor)
self.wb = RemoteClient()
self.wb.open()
print(self.wb.regs.acq_buf_full.read())
initLTC(self.wb)
def set_log_decimation_factor(self, ldf):
ADC.decimation_factor = 1 << ldf
ADC.fpga_output_rate = ADC.sample_rate / ADC.decimation_factor
if ldf != 0:
'''
This feature is missing in gateware
'''
raise NotImplementedError
def acquire_data(self, *args):
if self.test:
return self.test_data(*args)
while True:
# self.wb.regs.acq_acq_start.write(1)
d = get_data(self.wb)
if d is None:
print('recovering')
time.sleep(0.1)
continue
self._db = DataBlock(d, int(time.time()))
# ADC count / FULL SCALE => [-1.0, 1.]
self._process_subscriptions()
# time.sleep(0.1)
self.wb.close()
class ZestOnBMB7Carrier(Carrier):
'''
Zest on BMB7 or Marblemini
'''
def __init__(self,
ip_addr='192.168.1.121',
port=50006,
mask="0xff",
npt_wish=0,
count=10,
log_decimation_factor=0,
use_spartan=False,
test=False):
self._db = None
self.test = test
self.log_decimation_factor = 0
if self.test:
banyan_aw = 13
self.npt = 2**banyan_aw
self.n_channels = 2
else:
self.carrier = c_prc(
ip_addr,
port,
use_spartan=use_spartan)
self.npt = ZestOnBMB7Carrier.get_npt(self.carrier)
mask_int = int(mask, 0)
self.n_channels, self.channel_order = ZestOnBMB7Carrier.write_mask(self.carrier, mask_int)
self.set_log_decimation_factor(log_decimation_factor)
self.pts_per_ch = self.npt * 8 // self.n_channels
self.subscriptions, self.results = {}, {}
def set_log_decimation_factor(self, ldf):
Logger.info(f'Changed log_decimation factor from {self.log_decimation_factor} to {ldf}')
ADC.decimation_factor = 1 << ldf
if not self.test:
try:
self.carrier.leep.reg_write([('config_adc_downsample_ratio', ldf)])
except socket.timeout:
self.set_log_decimation_factor(ldf)
ADC.fpga_output_rate = ADC.sample_rate / ADC.decimation_factor
self.log_decimation_factor = ldf
def acquire_data(self, *args):
if self.test:
return self.test_data(*args)
while True:
# collect_adcs is not normal:
# It always collects npt * 8 data points.
# Each channel gets [(npt * 8) // n_channels] datapoints
start = time.time()
print('tick ..')
try:
data_raw_, ts = collect_adcs(self.carrier.leep,
self.npt, self.n_channels)
except socket.timeout:
print('foo')
continue
data_raw = [y for _, y in sorted(zip(self.channel_order, data_raw_))]
print(self.npt, self.n_channels, time.time()-start, self.channel_order)
self._db = DataBlock(ADC.counts_to_volts(np.array(data_raw)), ts)
# ADC count / FULL SCALE => [-1.0, 1.]
self._process_subscriptions()
# time.sleep(0.1) # This is now unnecessary, as this routine is the bottleneck
def _process_subscriptions(self):
# TODO: Perhaps implement something to avoid race condition on results
for sub_id, (single_subscribe, fn, *fn_args) in list(self.subscriptions.items()):
self.results[sub_id] = fn(self._db, *fn_args)
if single_subscribe:
self.remove_subscription(sub_id)
def add_subscription(self, sub_id, fn, *fn_args, single_subscribe=False):
# TODO: Add args/kwargs to the function
self.subscriptions[sub_id] = (single_subscribe, fn, *fn_args)
Logger.info('Added subscription {}'.format(sub_id))
def remove_subscription(self, sub_id):
self.subscriptions.pop(sub_id)
Logger.info('Removed subscription {}'.format(sub_id))
@staticmethod
def write_mask(carrier, mask_int):
carrier.leep.reg_write([('banyan_mask', mask_int)])
channels = banyan_ch_find(mask_int)
n_channels = len(channels)
print((channels, 8 / n_channels))
return n_channels, channels
@staticmethod
def get_npt(prc):
banyan_status = prc.leep.reg_read(['banyan_status'])[0]
npt = 1 << ((banyan_status >> 24) & 0x3F)
if npt == 1:
print("aborting since hardware module not present")
sys.exit(2)
return npt
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"litex.RemoteClient"
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#!/usr/bin/env python3
import sys
import argparse
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
parser = argparse.ArgumentParser()
#parser.add_argument("--ibus_stb", action="store_true", help="Trigger on IBus Stb rising edge.")
#parser.add_argument("--ibus_adr", default=0x00000000, help="Trigger on IBus Adr value.")
parser.add_argument("--offset", default=128, help="Capture Offset.")
parser.add_argument("--length", default=512, help="Capture Length.")
args = parser.parse_args()
wb = RemoteClient()
wb.open()
# # #
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True)
analyzer.configure_group(0)
#analyzer.add_rising_edge_trigger("simsoc_cpu_ibus_stb")
#analyzer.configure_trigger(cond={"simsoc_cpu_ibus_adr": int(args.ibus_adr, 0)})
#analyzer.configure_trigger(cond={})
analyzer.configure_trigger(cond={"basesoc_etherbone_liteethetherbonewishbonemaster_bus_adr":'0b10000000000'})
analyzer.run(offset=int(args.offset), length=int(args.length))
analyzer.wait_done()
analyzer.upload()
analyzer.save("dump.vcd")
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((139, 164), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (162, 164), False, 'import argparse\n'), ((548, 562), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (560, 562), False, 'from litex import RemoteClient\n'), ((592, 648), 'litescope.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (['wb.regs', '"""analyzer"""'], {'debug': '(True)'}), "(wb.regs, 'analyzer', debug=True)\n", (615, 648), False, 'from litescope import LiteScopeAnalyzerDriver\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2022 Lone Dynamics Corporation <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
#
# Krote FPGA board: https://github.com/machdyne/krote
#
# TODO:
# - add support for QQSPI PSRAM (32MB) pmod
# - add support for SD card pmod
#
import os
import sys
import argparse
from migen import *
from litex.build.io import CRG
from litex_boards.platforms import ld_krote
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.clock import iCE40PLL
from litex.soc.cores.led import LedChaser
from migen.genlib.resetsync import AsyncResetSynchronizer
kB = 1024
mB = 1024*kB
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# Clk/Rst
clk100 = platform.request("clk100")
platform.add_period_constraint(clk100, 1e9/100e6)
# Power On Reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(clk100)
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# Sys Clk
self.submodules.pll = pll = iCE40PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x20000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
platform = ld_krote.Platform()
# Disable Integrated ROM since too large for iCE40.
kwargs["integrated_rom_size"] = 0
kwargs["integrated_sram_size"] = 4*kB
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Kr\xf6te",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import W25Q32
from litespi.opcodes import SpiNorFlashOpCodes as Codes
self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 32*kB,
linker = True)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Kr\xf6te")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--bios-flash-offset", default="0x021000", help="BIOS offset in SPI Flash (default: 0x21000)")
parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)")
parser.add_argument("--with-led-chaser", action="store_true", help="Enable LED Chaser.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc = BaseSoC(
bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if __name__ == "__main__":
main()
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"litex.soc.integration.soc.SoCRegion",
"litex.soc.cores.clock.iCE40PLL"
] | [((3804, 3861), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Kröte"""'}), "(description='LiteX SoC on Kröte')\n", (3827, 3861), False, 'import argparse\n'), ((1526, 1536), 'litex.soc.cores.clock.iCE40PLL', 'iCE40PLL', ([], {}), '()\n', (1534, 1536), False, 'from litex.soc.cores.clock import iCE40PLL\n'), ((1675, 1735), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~por_done | ~pll.locked)'], {}), '(self.cd_sys, ~por_done | ~pll.locked)\n', (1697, 1735), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2120, 2139), 'litex_boards.platforms.ld_krote.Platform', 'ld_krote.Platform', ([], {}), '()\n', (2137, 2139), False, 'from litex_boards.platforms import ld_krote\n'), ((3247, 3340), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': "(self.mem_map['spiflash'] + bios_flash_offset)", 'size': '(32 * kB)', 'linker': '(True)'}), "(origin=self.mem_map['spiflash'] + bios_flash_offset, size=32 * kB,\n linker=True)\n", (3256, 3340), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((3065, 3089), 'litespi.modules.W25Q32', 'W25Q32', (['Codes.READ_1_1_1'], {}), '(Codes.READ_1_1_1)\n', (3071, 3089), False, 'from litespi.modules import W25Q32\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import camlink_4k
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litedram.modules import MT41K64M16
from litedram.phy import ECP5DDRPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
# clk / rst
clk27 = platform.request("clk27")
# power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# pll
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | self.rst)
pll.register_clkin(clk27, 27e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 27e6)
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI = self.cd_sys2x_i.clk,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked)
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, toolchain="trellis", with_led_chaser=True, **kwargs):
platform = camlink_4k.Platform(toolchain=toolchain)
sys_clk_freq = int(81e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Cam Link 4K",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:2"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Leds -------------------------------------------------------------------------------------
# Disable leds when serial is used.
if platform.lookup_request("serial", loose=True) is None and with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency.")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain (trellis or diamond).")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
toolchain = args.toolchain,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
if __name__ == "__main__":
main()
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"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args"
] | [((4028, 4091), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Cam Link 4K"""'}), "(description='LiteX SoC on Cam Link 4K')\n", (4051, 4091), False, 'import argparse\n'), ((4525, 4545), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (4537, 4545), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((2482, 2522), 'litex_boards.platforms.camlink_4k.Platform', 'camlink_4k.Platform', ([], {'toolchain': 'toolchain'}), '(toolchain=toolchain)\n', (2501, 2522), False, 'from litex_boards.platforms import camlink_4k\n'), ((4801, 4822), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (4816, 4822), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((2196, 2244), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~pll.locked)'], {}), '(self.cd_sys, ~pll.locked)\n', (2218, 2244), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((3405, 3436), 'litedram.modules.MT41K64M16', 'MT41K64M16', (['sys_clk_freq', '"""1:2"""'], {}), "(sys_clk_freq, '1:2')\n", (3415, 3436), False, 'from litedram.modules import MT41K64M16\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2022 <NAME> @hubmartin (Twitter)
# Copyright (c) 2022 Raptor Engineering, LLC
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import versa_ecp5
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex_boards.platforms import rcs_arctic_tern_bmc_card
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.integration.soc import SoCRegion
from litedram.modules import MT41J256M16
from litedram.phy import ECP5DDRPHY
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from litex.soc.cores.video import VideoGenericPHY
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True)
self.clock_domains.cd_dvo = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
self.reset = Signal()
# Clk / Rst
clk125 = platform.request("clk125")
rst_n = platform.request("rst_n")
self.clk_inv_alignwd = Signal()
self.sys_inv_clk_bridge = Signal()
self.sys_inv_clk_syncb = Signal()
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
sys2x_clk_ecsout = Signal()
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~por_done | ~rst_n | self.rst)
pll.register_clkin(clk125, 125e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 24e6)
self.specials += [
Instance("OSCG",
p_DIV = 128, # 2.4MHz
o_OSC = self.cd_por.clk),
Instance("ECLKBRIDGECS",
i_CLK0 = self.cd_sys2x_i.clk,
i_SEL = 0,
o_ECSOUT = sys2x_clk_ecsout),
Instance("ECLKSYNCB",
i_ECLKI = sys2x_clk_ecsout,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.reset,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset),
AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset),
]
# Generate DVO clock
pll.create_clkout(self.cd_dvo, 40e6) # 800x600@60
#pll.create_clkout(self.cd_dvo, 148.35e6) # 1920x1080@60
#pll.create_clkout(self.cd_dvo, 148.2e6) # 1920x1200@60
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(50e6), toolchain="trellis",
with_video_colorbars = False,
with_video_terminal = True,
with_video_framebuffer = False,
with_ethernet = False,
with_etherbone = False,
eth_ip = "192.168.1.50",
**kwargs):
platform = rcs_arctic_tern_bmc_card.Platform(toolchain=toolchain)
#bios_flash_offset = 0x400000
# Set CPU variant / reset address
#kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
kwargs["integrated_rom_size"] = 0x10000
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, irq_n_irqs=16, clk_freq=sys_clk_freq,
ident = "LiteX SoC on Arctic Tern (BMC card carrier)",
#integrated_main_ram_size = 0x40000,
#integrated_main_ram_size = 0,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# DDR3 SDRAM -------------------------------------------------------------------------------
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
self.comb += self.crg.reset.eq(self.ddrphy.init.reset)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41J256M16(sys_clk_freq, "1:2"), # Not MT41J256M16, but the AS4C256M16D3C in use has similar specifications
l2_cache_size = kwargs.get("l2_size", 8192),
)
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", 0),
pads = self.platform.request("eth", 0),
tx_delay = 0e-9,
rx_delay = 0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy, ip_address=eth_ip)
# Video Output -----------------------------------------------------------------------------
if with_video_colorbars or with_video_terminal or with_video_framebuffer:
dvo_pads = platform.request("dvo")
self.submodules.videophy = VideoGenericPHY(dvo_pads, clock_domain="dvo", with_clk_ddr_output=False)
if with_video_terminal:
#self.add_video_terminal(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
#self.add_video_terminal(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvo")
elif with_video_framebuffer:
#self.add_video_framebuffer(phy=self.videophy, timings="1920x1080@60Hz", clock_domain="dvo")
#self.add_video_framebuffer(phy=self.videophy, timings="1920x1200@60Hz", clock_domain="dvo")
self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvo")
else:
self.add_video_colorbars(phy=self.videophy, timings="800x600@60Hz", clock_domain="dvo")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arctic Tern (BMC card carrier)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond")
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(builder.get_bitstream_filename(mode="sram", ext=".svf")) # FIXME
if __name__ == "__main__":
main()
| [
"litex.build.lattice.trellis.trellis_argdict",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.cores.video.VideoGenericPHY"
] | [((7265, 7352), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Arctic Tern (BMC card carrier)"""'}), "(description=\n 'LiteX SoC on Arctic Tern (BMC card carrier)')\n", (7288, 7352), False, 'import argparse\n'), ((8198, 8218), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (8210, 8218), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((3945, 3999), 'litex_boards.platforms.rcs_arctic_tern_bmc_card.Platform', 'rcs_arctic_tern_bmc_card.Platform', ([], {'toolchain': 'toolchain'}), '(toolchain=toolchain)\n', (3978, 3999), False, 'from litex_boards.platforms import rcs_arctic_tern_bmc_card\n'), ((8598, 8619), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (8613, 8619), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((3070, 3131), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~pll.locked | self.reset)'], {}), '(self.cd_sys, ~pll.locked | self.reset)\n', (3092, 3131), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((3147, 3210), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys2x', '(~pll.locked | self.reset)'], {}), '(self.cd_sys2x, ~pll.locked | self.reset)\n', (3169, 3210), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((6226, 6298), 'litex.soc.cores.video.VideoGenericPHY', 'VideoGenericPHY', (['dvo_pads'], {'clock_domain': '"""dvo"""', 'with_clk_ddr_output': '(False)'}), "(dvo_pads, clock_domain='dvo', with_clk_ddr_output=False)\n", (6241, 6298), False, 'from litex.soc.cores.video import VideoGenericPHY\n'), ((5196, 5228), 'litedram.modules.MT41J256M16', 'MT41J256M16', (['sys_clk_freq', '"""1:2"""'], {}), "(sys_clk_freq, '1:2')\n", (5207, 5228), False, 'from litedram.modules import MT41J256M16\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("T8"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("V9"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("R8"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("T6"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("T5"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("T4"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("U7"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("U6"), IOStandard("LVCMOS33")),
("user_led", 8, Pins("V4"), IOStandard("LVCMOS33")),
("user_led", 9, Pins("U3"), IOStandard("LVCMOS33")),
("user_led", 10, Pins("V1"), IOStandard("LVCMOS33")),
("user_led", 11, Pins("R1"), IOStandard("LVCMOS33")),
("user_led", 12, Pins("P5"), IOStandard("LVCMOS33")),
("user_led", 13, Pins("U1"), IOStandard("LVCMOS33")),
("user_led", 14, Pins("R2"), IOStandard("LVCMOS33")),
("user_led", 15, Pins("P2"), IOStandard("LVCMOS33")),
# 7SEG DISPLAY
("segled_an", 0, Pins("N6"), IOStandard("LVCMOS33")),
("segled_an", 1, Pins("M6"), IOStandard("LVCMOS33")),
("segled_an", 2, Pins("M3"), IOStandard("LVCMOS33")),
("segled_an", 3, Pins("N5"), IOStandard("LVCMOS33")),
("segled_an", 4, Pins("N2"), IOStandard("LVCMOS33")),
("segled_an", 5, Pins("N4"), IOStandard("LVCMOS33")),
("segled_an", 6, Pins("L1"), IOStandard("LVCMOS33")),
("segled_an", 7, Pins("M1"), IOStandard("LVCMOS33")),
("segled_ca", 0, Pins("L3"), IOStandard("LVCMOS33")),
("segled_cb", 0, Pins("N1"), IOStandard("LVCMOS33")),
("segled_cc", 0, Pins("L5"), IOStandard("LVCMOS33")),
("segled_cd", 0, Pins("L4"), IOStandard("LVCMOS33")),
("segled_ce", 0, Pins("K3"), IOStandard("LVCMOS33")),
("segled_cf", 0, Pins("M2"), IOStandard("LVCMOS33")),
("segled_cg", 0, Pins("L6"), IOStandard("LVCMOS33")),
("segled_dp", 0, Pins("M4"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("K6")),
Subsignal("g", Pins("H6")),
Subsignal("b", Pins("L16")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("K5")),
Subsignal("g", Pins("F13")),
Subsignal("b", Pins("F6")),
IOStandard("LVCMOS33"),
),
# Switches
("user_sw", 0, Pins("U9"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("U8"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("R7"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("R6"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("R5"), IOStandard("LVCMOS33")),
("user_sw", 5, Pins("V7"), IOStandard("LVCMOS33")),
("user_sw", 6, Pins("V6"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("V5"), IOStandard("LVCMOS33")),
("user_sw", 8, Pins("U4"), IOStandard("LVCMOS33")),
("user_sw", 9, Pins("V2"), IOStandard("LVCMOS33")),
("user_sw", 10, Pins("U2"), IOStandard("LVCMOS33")),
("user_sw", 11, Pins("T3"), IOStandard("LVCMOS33")),
("user_sw", 12, Pins("T1"), IOStandard("LVCMOS33")),
("user_sw", 13, Pins("R3"), IOStandard("LVCMOS33")),
("user_sw", 14, Pins("P3"), IOStandard("LVCMOS33")),
("user_sw", 15, Pins("P4"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("T16"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("R10"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("F15"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("V10"), IOStandard("LVCMOS33")),
("user_btn", 4, Pins("E16"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("D4")),
Subsignal("rx", Pins("C4")),
IOStandard("LVCMOS33"),
),
# SDCard
("spisdcard", 0,
Subsignal("rst", Pins("E2")),
Subsignal("clk", Pins("B1")),
Subsignal("mosi", Pins("C1"), Misc("PULLUP True")),
Subsignal("cs_n", Pins("D2"), Misc("PULLUP True")),
Subsignal("miso", Pins("C2"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("rst", Pins("E2"), Misc("PULLUP True")),
Subsignal("data", Pins("C2 E1 F1 D2"), Misc("PULLUP True")),
Subsignal("cmd", Pins("C1"), Misc("PULLUP True")),
Subsignal("clk", Pins("B1")),
Subsignal("cd", Pins("A1")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
# SRAM
("cellularram", 0,
Subsignal("addr", Pins(
"J18 H17 H15 J17 H16 K15 K13 N15",
"V16 U14 V14 V12 P14 U16 R15 N14",
"N16 M13 V17 U17 T10 M16 U13"),
),
Subsignal("data", Pins(
"R12 T11 U12 R13 U18 R17 T18 R18",
"F18 G18 G17 M18 M17 P18 N17 P17"),
),
Subsignal("oen", Pins("H14")),
Subsignal("wen", Pins("R11")),
Subsignal("clk", Pins("T15")),
Subsignal("adv", Pins("T13")),
Subsignal("wait", Pins("T14")),
Subsignal("cen", Pins("L18")),
Subsignal("ub", Pins("J13")),
Subsignal("lb", Pins("J15")),
Subsignal("cre", Pins("J14")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
# RMII Ethernet
("eth_clocks", 0,
Subsignal("ref_clk", Pins("D5")),
IOStandard("LVCMOS33"),
),
("aud_pwm", 0,
Subsignal("pwm_out", Pins("A11")),
Subsignal("enable", Pins("D12")),
IOStandard("LVCMOS33"),
),
("eth", 0,
Subsignal("rst_n", Pins("B3")),
Subsignal("rx_data", Pins("C11 D10")),
Subsignal("crs_dv", Pins("D9")),
Subsignal("tx_en", Pins("B9")),
Subsignal("tx_data", Pins("A10 A8")),
Subsignal("mdc", Pins("C9")),
Subsignal("mdio", Pins("A9")),
Subsignal("rx_er", Pins("C10")),
Subsignal("int_n", Pins("B8")),
IOStandard("LVCMOS33")
),
# VGA
("vga", 0,
Subsignal("hsync_n", Pins("B11")),
Subsignal("vsync_n", Pins("B12")),
Subsignal("r", Pins("A4 C5 B4 A3")),
Subsignal("g", Pins("A6 B6 A5 C6")),
Subsignal("b", Pins("D7 C7 B7 D8")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("pmoda", "B13 F14 D17 E17 G13 C17 D18 E18"),
("pmodb", "G14 P15 V11 V15 K16 R16 T9 U11"),
("pmodc", "K2 E7 J3 J4 K1 E6 J2 G6"),
("pmodd", "H4 H1 G1 G3 H2 G4 G2 F3"),
("pmodxdac", "A13 A15 B16 B18 A14 A16 B17 A18"),
]
# PMODS --------------------------------------------------------------------------------------------
def sdcard_pmod_io(pmod):
return [
# SDCard PMOD:
# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
("spisdcard", 0,
Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLUP True")),
Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLUP True")),
Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLUP True")),
Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLUP True")),
Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("cd", Pins(f"{pmod}:6")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
]
_sdcard_pmod_io = sdcard_pmod_io("pmodd") # SDCARD PMOD on JD.
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("eth_clocks:ref_clk", loose=True), 1e9/50e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((8365, 8458), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-CSG324-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7a100t-CSG324-1', _io, _connectors,\n toolchain=toolchain)\n", (8388, 8458), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((8591, 8650), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a100t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a100t.bit')\n", (8598, 8650), False, 'from litex.build.openocd import OpenOCD\n'), ((8697, 8739), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (8723, 8739), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# License: BSD
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import versa_ecp5
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.build.tools import write_to_file
from litex.soc.cores.clock import *
from litex.soc.cores.gpio import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.soc.integration import export
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.cores.spi import SPIMaster
from litescope import LiteScopeAnalyzer
from litedram.modules import MT41K64M16
from litedram.phy import ECP5DDRPHY
from litedram.frontend.dma import LiteDRAMDMAReader
from litedram.frontend.dma import LiteDRAMDMAWriter
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from liteeth.mac import LiteEthMAC
from memtest import MemtestCore
from dac7563 import DAC7563Core
from ad7984 import AD7984Core
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_init = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain()
self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True)
# # #
self.stop = Signal()
# Clk / Rst
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
platform.add_period_constraint(clk100, 1e9/100e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq)
pll.create_clkout(self.cd_init, 25e6)
self.specials += [
Instance("ECLKSYNCB",
i_ECLKI = self.cd_sys2x_i.clk,
i_STOP = self.stop,
o_ECLKO = self.cd_sys2x.clk),
Instance("CLKDIVF",
p_DIV = "2.0",
i_ALIGNWD = 0,
i_CLKI = self.cd_sys2x.clk,
i_RST = self.cd_sys2x.rst,
o_CDIVX = self.cd_sys.clk),
AsyncResetSynchronizer(self.cd_init, ~por_done | ~pll.locked | ~rst_n),
AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
]
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", integrated_rom_size=0x8000, **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain)
# SoCSDRAM ---------------------------------------------------------------------------------
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=integrated_rom_size,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# https://github.com/enjoy-digital/litex/issues/234
# https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/gpio.py
# /repos/litex/litex-boards/litex_boards/official/platforms/versa_ecp5.py
self.add_csr("gpio_leds")
self.submodules.gpio_leds = GPIOOut(Cat([platform.request("user_led", i) for i in range(8)]))
# add spi master, from ~/repos/litex/litex/litex/soc/cores
self.add_csr("spi_test")
spi_test = SPIMaster(platform.request("spi_test",1), 8, sys_clk_freq, int(sys_clk_freq/5))
self.submodules.spi_test = spi_test
self.add_csr("dac_test")
dac_test = DAC7563Core(platform.request("dac_test",1))
self.submodules.dac_test = dac_test
# https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers litescope bridge
# added io to platform, serial_wb
self.submodules.bridge = UARTWishboneBridge(platform.request("serial_wb",1), sys_clk_freq, baudrate=115200)
self.add_wb_master(self.bridge.wishbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
print("creating DDR3 SDRAM")
self.submodules.ddrphy = ECP5DDRPHY(
platform.request("ddram"),
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_constant("ECP5DDRPHY", None)
self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
sdram_module = MT41K64M16(sys_clk_freq, "1:2")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)
self.add_csr("memory_test")
memory_test = MemtestCore(self.sdram.crossbar.get_port())
self.submodules.memory_test = memory_test
self.add_csr("adc_test")
adc_test = AD7984Core(self.sdram.crossbar.get_port(), platform.request("adc_test",1))
self.submodules.adc_test = adc_test
# litescope, track spi
self.add_csr("analyzer")
analyzer_signals = [
dac_test.dac.dac_load,
dac_test._load.fields.load,
dac_test.dac.load,
dac_test.dac.dac_cs,
dac_test.dac.dac_sck,
dac_test.dac.dac_sdi,
dac_test.dac.dac_ready,
dac_test.dac.state,
]
analyzer_depth = 256 # samples
analyzer_clock_domain = "sys"
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
analyzer_depth,
clock_domain=analyzer_clock_domain)
# EthernetSoC --------------------------------------------------------------------------------------
class EthernetSoC(BaseSoC):
mem_map = {
"ethmac": 0xb0000000,
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, toolchain="diamond", **kwargs):
BaseSoC.__init__(self, toolchain=toolchain, integrated_rom_size=0x10000, **kwargs)
self.submodules.ethphy = LiteEthPHYRGMII(
self.platform.request("eth_clocks"),
self.platform.request("eth"))
self.add_csr("ethphy")
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
self.add_csr("ethmac")
self.add_interrupt("ethmac")
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis",
help='gateware toolchain to use, trellis (default)')
builder_args(parser)
soc_sdram_args(parser)
trellis_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder_kargs = {}
if args.toolchain == "trellis":
builder_kargs == trellis_argdict(args)
vns = builder.build(**builder_kargs)
csr_csv = export.get_csr_csv(soc.csr_regions, soc.constants)
write_to_file("test/csr.csv", csr_csv)
soc.analyzer.export_csv(vns, "test/analyzer.csv") # Export the current analyzer configuration
if __name__ == "__main__":
main()
| [
"litex.build.lattice.trellis.trellis_argdict",
"litex.soc.integration.export.get_csr_csv",
"litex.build.tools.write_to_file",
"litex.build.lattice.trellis.trellis_args"
] | [((7679, 7741), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Versa ECP5"""'}), "(description='LiteX SoC on Versa ECP5')\n", (7702, 7741), False, 'import argparse\n'), ((7944, 7964), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (7956, 7964), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((8636, 8686), 'litex.soc.integration.export.get_csr_csv', 'export.get_csr_csv', (['soc.csr_regions', 'soc.constants'], {}), '(soc.csr_regions, soc.constants)\n', (8654, 8686), False, 'from litex.soc.integration import export\n'), ((8691, 8729), 'litex.build.tools.write_to_file', 'write_to_file', (['"""test/csr.csv"""', 'csr_csv'], {}), "('test/csr.csv', csr_csv)\n", (8704, 8729), False, 'from litex.build.tools import write_to_file\n'), ((3135, 3175), 'litex_boards.platforms.versa_ecp5.Platform', 'versa_ecp5.Platform', ([], {'toolchain': 'toolchain'}), '(toolchain=toolchain)\n', (3154, 3175), False, 'from litex_boards.platforms import versa_ecp5\n'), ((7050, 7143), 'liteeth.mac.LiteEthMAC', 'LiteEthMAC', ([], {'phy': 'self.ethphy', 'dw': '(32)', 'interface': '"""wishbone"""', 'endianness': 'self.cpu.endianness'}), "(phy=self.ethphy, dw=32, interface='wishbone', endianness=self.\n cpu.endianness)\n", (7060, 7143), False, 'from liteeth.mac import LiteEthMAC\n'), ((2714, 2784), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_init', '(~por_done | ~pll.locked | ~rst_n)'], {}), '(self.cd_init, ~por_done | ~pll.locked | ~rst_n)\n', (2736, 2784), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2798, 2867), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~por_done | ~pll.locked | ~rst_n)'], {}), '(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)\n', (2820, 2867), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((5162, 5193), 'litedram.modules.MT41K64M16', 'MT41K64M16', (['sys_clk_freq', '"""1:2"""'], {}), "(sys_clk_freq, '1:2')\n", (5172, 5193), False, 'from litedram.modules import MT41K64M16\n'), ((6274, 6366), 'litescope.LiteScopeAnalyzer', 'LiteScopeAnalyzer', (['analyzer_signals', 'analyzer_depth'], {'clock_domain': 'analyzer_clock_domain'}), '(analyzer_signals, analyzer_depth, clock_domain=\n analyzer_clock_domain)\n', (6291, 6366), False, 'from litescope import LiteScopeAnalyzer\n'), ((8548, 8569), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (8563, 8569), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import ecp5_evn
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.dma import WishboneDMAWriter
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSRField
from litex.soc.interconnect import wishbone
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, x5_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
# # #
# clk / rst
clk = clk12 = platform.request("clk12")
rst_n = platform.request("rst_n")
if x5_clk_freq is not None:
clk = clk50 = platform.request("ext_clk50")
self.comb += platform.request("ext_clk50_en").eq(1)
platform.add_period_constraint(clk50, 1e9/x5_clk_freq)
# pll
self.submodules.pll = pll = ECP5PLL()
self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk, x5_clk_freq or 12e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
class Wishbone_DMA_Burst(Module, AutoCSR):
def __init__(self):
self.wishbone = wishbone.Interface()
self._start = CSRStorage(fields=[CSRField("start_burst", size=1, offset=0, pulse=True)])
self._ready = CSRStatus(8)
self._burst_size = CSRStorage(16)
self._base = CSRStorage(32)
self._offset = CSRStorage(32)
words_count = Signal(16)
pass_count = Signal(5)
self.wb_dma = wb_dma = WishboneDMAWriter(self.wishbone, endianness="big")
self.submodules += wb_dma
self.comb += [
self.wb_dma.sink.address.eq((self._base.storage >> 2) + (self._offset.storage>>2) + words_count),
self.wb_dma.sink.data.eq(pass_count),
]
fsm = FSM(reset_state="WAIT-FOR-TRIGGER")
self.submodules += fsm
fsm.act("WAIT-FOR-TRIGGER",
self._ready.status.eq(1),
NextValue(words_count, 0),
If(self._start.fields.start_burst,
NextState("WRITE-DATA"),
)
)
fsm.act("WRITE-DATA",
self.wb_dma.sink.valid.eq(1),
If(self.wb_dma.sink.ready,
NextValue(words_count, words_count+1),
If(words_count == (self._burst_size.storage-1),
NextState("WAIT-FOR-TRIGGER"),
NextValue(pass_count, pass_count+1)
)
)
)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {
"adc_sram" : 0x30000000,
}
mem_map.update(SoCCore.mem_map)
def __init__(self, sys_clk_freq=int(50e6), x5_clk_freq=None, toolchain="trellis", **kwargs):
platform = ecp5_evn.Platform(toolchain=toolchain)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on ECP5 Evaluation Board",
ident_version = True,
integrated_main_ram_size=0x8000,
**kwargs)
# CRG --------------------------------------------------------------------------------------
crg = _CRG(platform, sys_clk_freq, x5_clk_freq)
self.submodules.crg = crg
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(8)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Wishbone DMA Burst Testing
# block of SRAM of WB dma testing
self.add_ram("adc_sram", self.mem_map["adc_sram"], 8*4*4096)
self.submodules.dma_burst = Wishbone_DMA_Burst()
self.add_csr("dma_burst")
self.add_wb_master(self.dma_burst.wishbone)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)")
parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency")
args = parser.parse_args()
soc = BaseSoC(toolchain=args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
x5_clk_freq = args.x5_clk_freq,
**soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.cores.dma.WishboneDMAWriter",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.csr.CSRField"
] | [((4525, 4598), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on ECP5 Evaluation Board"""'}), "(description='LiteX SoC on ECP5 Evaluation Board')\n", (4548, 4598), False, 'import argparse\n'), ((1401, 1444), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~rst_n)'], {}), '(self.cd_sys, ~rst_n)\n', (1423, 1444), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((1537, 1557), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (1555, 1557), False, 'from litex.soc.interconnect import wishbone\n'), ((1678, 1690), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(8)'], {}), '(8)\n', (1687, 1690), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSRField\n'), ((1718, 1732), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(16)'], {}), '(16)\n', (1728, 1732), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSRField\n'), ((1754, 1768), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(32)'], {}), '(32)\n', (1764, 1768), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSRField\n'), ((1792, 1806), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(32)'], {}), '(32)\n', (1802, 1806), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSRField\n'), ((1913, 1963), 'litex.soc.cores.dma.WishboneDMAWriter', 'WishboneDMAWriter', (['self.wishbone'], {'endianness': '"""big"""'}), "(self.wishbone, endianness='big')\n", (1930, 1963), False, 'from litex.soc.cores.dma import WishboneDMAWriter\n'), ((3247, 3285), 'litex_boards.platforms.ecp5_evn.Platform', 'ecp5_evn.Platform', ([], {'toolchain': 'toolchain'}), '(toolchain=toolchain)\n', (3264, 3285), False, 'from litex_boards.platforms import ecp5_evn\n'), ((5545, 5604), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.svf')"], {}), "(builder.gateware_dir, soc.build_name + '.svf')\n", (5557, 5604), False, 'import os\n'), ((1600, 1653), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""start_burst"""'], {'size': '(1)', 'offset': '(0)', 'pulse': '(True)'}), "('start_burst', size=1, offset=0, pulse=True)\n", (1608, 1653), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSRField\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import argparse
import sys
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
# IOs ----------------------------------------------------------------------------------------------
_io = [("clk25", 0, Pins("P6"), IOStandard("LVCMOS33"))]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-6BG256C", _io, **kwargs)
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
# # #
# Clk / Rst
clk25 = platform.request("clk25")
platform.add_period_constraint(clk25, 1e9/25e6)
# Power on reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# PLL
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
# IOStreamer ---------------------------------------------------------------------------------------
class IOStreamer(Module):
"""Stream an identifier string over UART"""
def __init__(self, identifier, pad, sys_clk_freq, baudrate):
from litex.soc.cores.uart import RS232PHYTX
assert len(identifier) <= 4
for i in range(4-len(identifier)):
identifier += " "
# UART
pads = Record([("tx", 1)])
self.comb += pad.eq(pads.tx)
phy = RS232PHYTX(pads, int((baudrate/sys_clk_freq)*2**32))
self.submodules += phy
# Memory
mem = Memory(8, 4, init=[ord(identifier[i]) for i in range(4)])
port = mem.get_port()
self.specials += mem, port
self.comb += phy.sink.valid.eq(1)
self.comb += phy.sink.data.eq(port.dat_r)
self.sync += If(phy.sink.ready, port.adr.eq(port.adr + 1))
# IOsStreamSoC -------------------------------------------------------------------------------------
class IOsStreamSoC(SoCMini):
def __init__(self, platform):
sys_clk_freq = int(25e6)
SoCMini.__init__(self, platform, sys_clk_freq)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Get IOs from JSON database ---------------------------------------------------------------
import json
json_file = open("iodb.json")
json_data = json.load(json_file)
json_file.close()
ios = list(json_data["packages"]["CABGA256"].keys())
# Exclude some IOs -------------------------------------------------------------------------
excludes = []
excludes += ["P6"]
for exclude in excludes:
ios.remove(exclude)
# Create platform IOs ----------------------------------------------------------------------
for io in ios:
platform.add_extension([(io, 0, Pins(io), IOStandard("LVCMOS33"), Misc("DRIVE=4"))])
# Stream IOs' identifiers to IOs -----------------------------------------------------------
for io in ios:
io_streamer = IOStreamer(io, platform.request(io), sys_clk_freq, baudrate=9600)
self.submodules += io_streamer
# Load ---------------------------------------------------------------------------------------------
def load():
import os
f = open("openocd.cfg", "w")
f.write(
"""
interface ftdi
ftdi_vid_pid 0x0403 0x6011
ftdi_channel 0
ftdi_layout_init 0x0098 0x008b
reset_config none
adapter_khz 25000
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
f.close()
os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf build/gateware/ios_stream.svf; exit\"")
exit()
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser()
parser.add_argument("--build", action="store_true", help="build bitstream")
parser.add_argument("--load", action="store_true", help="load bitstream")
args = parser.parse_args()
if args.load:
load()
platform = Platform(toolchain="trellis")
soc = IOsStreamSoC(platform)
builder = Builder(soc, output_dir="build")
builder.build(build_name="ios_stream", run=args.build)
if __name__ == "__main__":
main()
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"litex.build.lattice.LatticePlatform.__init__"
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#
# This file is part of LiteX.
#
# Copyright (c) 2019-2022 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.cdc import AsyncResetSynchronizer, MultiReg
from litex.soc.interconnect import stream
# JTAG TAP FSM -------------------------------------------------------------------------------------
class JTAGTAPFSM(Module):
def __init__(self, tms):
self.submodules.fsm = fsm = FSM(reset_state="TEST_LOGIC_RESET")
def JTAGTAPFSMState(name, transitions={}):
logic = []
# Transitions logic.
nextstates = {}
nextstates[0] = NextState(transitions.get(0, name))
nextstates[1] = NextState(transitions.get(1, name))
logic.append(Case(tms, nextstates))
# Ongoing logic.
ongoing = Signal()
setattr(self, name, ongoing)
logic.append(ongoing.eq(1))
# Add logic to state.
fsm.act(name, *logic)
# Test-Logic-Reset.
# -----------------
JTAGTAPFSMState(
name = "TEST_LOGIC_RESET",
transitions = {
0 : "RUN_TEST_IDLE",
}
)
# Run-Test/Idle.
# --------------
JTAGTAPFSMState(
name = "RUN_TEST_IDLE",
transitions = {
1 : "SELECT_DR_SCAN",
}
)
# DR-Scan.
# --------
JTAGTAPFSMState(
name = "SELECT_DR_SCAN",
transitions = {
0 : "CAPTURE_DR",
1 : "SELECT_IR_SCAN",
}
)
JTAGTAPFSMState(
name = "CAPTURE_DR",
transitions = {
0 : "SHIFT_DR",
1 : "EXIT1_DR",
}
)
JTAGTAPFSMState(
name = "SHIFT_DR",
transitions = {
1 : "EXIT1_DR",
}
)
JTAGTAPFSMState(
name = "EXIT1_DR",
transitions = {
0 : "PAUSE_DR",
1 : "UPDATE_DR",
}
)
JTAGTAPFSMState(
name = "PAUSE_DR",
transitions = {
1 : "EXIT2_DR",
}
)
JTAGTAPFSMState(
name = "EXIT2_DR",
transitions = {
0 : "SHIFT_DR",
1 : "UPDATE_DR",
}
)
JTAGTAPFSMState(
name = "UPDATE_DR",
transitions = {
0 : "RUN_TEST_IDLE",
1 : "SELECT_DR_SCAN",
}
)
# IR-Scan.
# --------
JTAGTAPFSMState(
name = "SELECT_IR_SCAN",
transitions = {
0 : "CAPTURE_IR",
1 : "TEST_LOGIC_RESET",
}
)
JTAGTAPFSMState(
name = "CAPTURE_IR",
transitions = {
0 : "SHIFT_IR",
1 : "EXIT1_IR",
}
)
JTAGTAPFSMState(
name = "SHIFT_IR",
transitions = {
1 : "EXIT1_IR",
}
)
JTAGTAPFSMState(
name = "EXIT1_IR",
transitions = {
0 : "PAUSE_IR",
1 : "UPDATE_IR",
}
)
JTAGTAPFSMState(
name = "PAUSE_IR",
transitions = {
1 : "EXIT2_IR",
}
)
JTAGTAPFSMState(
name = "EXIT2_IR",
transitions = {
0 : "SHIFT_IR",
1 : "UPDATE_IR",
}
)
JTAGTAPFSMState(
name = "UPDATE_IR",
transitions = {
0 : "RUN_TEST_IDLE",
1 : "SELECT_DR_SCAN",
}
)
# Altera JTAG --------------------------------------------------------------------------------------
class AlteraJTAG(Module):
def __init__(self, primitive, pads):
# Common with Xilinx.
self.reset = reset = Signal() # Provided by our own TAP FSM.
self.capture = capture = Signal() # Provided by our own TAP FSM.
self.shift = shift = Signal()
self.update = update = Signal()
# Unique to Altera.
self.runtest = runtest = Signal()
self.drck = drck = Signal()
self.sel = sel = Signal()
self.tck = tck = Signal()
self.tms = tms = Signal()
self.tdi = tdi = Signal()
self.tdo = tdo = Signal()
# Magic reserved signals that have to be routed to the top module.
self.altera_reserved_tck = rtck = Signal()
self.altera_reserved_tms = rtms = Signal()
self.altera_reserved_tdi = rtdi = Signal()
self.altera_reserved_tdo = rtdo = Signal()
# Inputs.
self.tdouser = tdouser = Signal()
# Outputs.
self.tmsutap = tmsutap = Signal()
self.tckutap = tckutap = Signal()
self.tdiutap = tdiutap = Signal()
# # #
# Create falling-edge JTAG clock domain for TAP FSM.
self.clock_domains.cd_jtag_inv = cd_jtag_inv = ClockDomain("jtag_inv")
self.comb += ClockSignal("jtag_inv").eq(~ClockSignal("jtag"))
self.comb += ResetSignal("jtag_inv").eq(ResetSignal("jtag"))
# Connect the TAP state signals that LiteX expects but the HW IP doesn't provide.
self.submodules.tap_fsm = ClockDomainsRenamer("jtag")(JTAGTAPFSM(tms))
self.sync.jtag_inv += reset.eq(self.tap_fsm.TEST_LOGIC_RESET)
self.sync.jtag_inv += capture.eq(self.tap_fsm.CAPTURE_DR)
self.specials += Instance(primitive,
# HW TAP FSM states.
o_shiftuser = shift,
o_updateuser = update,
o_runidleuser = runtest,
o_clkdruser = drck,
o_usr1user = sel,
# JTAG TAP IO.
i_tdouser = tdouser,
o_tmsutap = tmsutap,
o_tckutap = tckutap,
o_tdiutap = tdiutap,
# Reserved pins.
i_tms = rtms,
i_tck = rtck,
i_tdi = rtdi,
o_tdo = rtdo,
)
# connect magical reserved signals to top level pads
self.comb += [
rtms.eq(pads["altera_reserved_tms"]),
rtck.eq(pads["altera_reserved_tck"]),
rtdi.eq(pads["altera_reserved_tdi"]),
pads["altera_reserved_tdo"].eq(rtdo),
]
# Connect TAP IO.
self.comb += [
tck.eq(tckutap),
tms.eq(tmsutap),
tdi.eq(tdiutap),
]
self.sync.jtag_inv += tdouser.eq(tdo)
@staticmethod
def get_primitive(device):
# TODO: Add support for all devices.
prim_dict = {
# Primitive Name Ðevice (startswith)
"arriaii_jtag" : [],
"arriaiigz_jtag" : [],
"arriav_jtag" : [],
"arriavgz_jtag" : [],
"cyclone_jtag" : [],
"cyclone10lp_jtag" : ["10cl"],
"cycloneii_jtag" : [],
"cycloneiii_jtag" : [],
"cycloneiiils_jtag" : [],
"cycloneiv_jtag" : [],
"cycloneive_jtag" : ["ep4c"],
"cyclonev_jtag" : ["5c"],
"fiftyfivenm_jtag" : ["10m"],
"maxii_jtag" : [],
"maxv_jtag" : [],
"stratix_jtag" : [],
"stratixgx_jtag" : [],
"stratixii_jtag" : [],
"stratixiigx_jtag" : [],
"stratixiii_jtag" : [],
"stratixiv_jtag" : [],
"stratixv_jtag" : [],
"twentynm_jtagblock" : [],
"twentynm_jtag" : [],
"twentynm_hps_interface_jtag" : [],
}
for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs:
if device.lower().startswith(prim_dev):
return prim
return None
# Xilinx JTAG --------------------------------------------------------------------------------------
class XilinxJTAG(Module):
def __init__(self, primitive, chain=1):
self.reset = Signal()
self.capture = Signal()
self.shift = Signal()
self.update = Signal()
self.tck = Signal()
self.tms = Signal()
self.tdi = Signal()
self.tdo = Signal()
# # #
self.specials += Instance(primitive,
p_JTAG_CHAIN = chain,
o_RESET = self.reset,
o_CAPTURE = self.capture,
o_SHIFT = self.shift,
o_UPDATE = self.update,
o_TCK = self.tck,
o_TMS = self.tms,
o_TDI = self.tdi,
i_TDO = self.tdo,
)
@staticmethod
def get_primitive(device):
# TODO: Add support for all devices.
prim_dict = {
# Primitive Name Ðevice (startswith)
"BSCAN_SPARTAN6" : ["xc6"],
"BSCANE2" : ["xc7", "xcku", "xcvu", "xczu"],
}
for prim, prim_devs in prim_dict.items():
for prim_dev in prim_devs:
if device.lower().startswith(prim_dev):
return prim
return None
# ECP5 JTAG ----------------------------------------------------------------------------------------
class ECP5JTAG(Module):
def __init__(self, tck_delay_luts=8):
self.reset = Signal()
self.capture = Signal()
self.shift = Signal()
self.update = Signal()
self.tck = Signal()
self.tdi = Signal()
self.tdo = Signal()
# # #
rst_n = Signal()
tck = Signal()
jce1 = Signal()
jce1_d = Signal()
self.sync.jtag += jce1_d.eq(jce1)
self.comb += self.capture.eq(jce1 & ~jce1_d) # First cycle jce1 is high we're in Capture-DR.
self.comb += self.reset.eq(~rst_n)
self.specials += Instance("JTAGG",
o_JRSTN = rst_n,
o_JSHIFT = self.shift,
o_JUPDATE = self.update,
o_JTCK = tck,
o_JTDI = self.tdi, # JTDI = FF(posedge TCK, TDI)
o_JCE1 = jce1, # (FSM==Capture-DR || Shift-DR) & (IR==0x32)
i_JTDO1 = self.tdo, # FF(negedge TCK, JTDO1) if (IR==0x32 && FSM==Shift-DR)
)
# TDI/TCK are synchronous on JTAGG output (TDI being registered with TCK). Introduce a delay
# on TCK with multiple LUT4s to allow its use as the JTAG Clk.
for i in range(tck_delay_luts):
new_tck = Signal()
self.specials += Instance("LUT4",
attr = {"keep"},
p_INIT = 2,
i_A = tck,
i_B = 0,
i_C = 0,
i_D = 0,
o_Z = new_tck
)
tck = new_tck
self.comb += self.tck.eq(tck)
# JTAG PHY -----------------------------------------------------------------------------------------
class JTAGPHY(Module):
def __init__(self, jtag=None, device=None, data_width=8, clock_domain="sys", chain=1, platform=None):
"""JTAG PHY
Provides a simple JTAG to LiteX stream module to easily stream data to/from the FPGA
over JTAG.
Wire format: data_width + 2 bits, LSB first.
Host to Target:
- TX ready : bit 0
- RX data: : bit 1 to data_width
- RX valid : bit data_width + 1
Target to Host:
- RX ready : bit 0
- TX data : bit 1 to data_width
- TX valid : bit data_width + 1
"""
self.sink = sink = stream.Endpoint([("data", data_width)])
self.source = source = stream.Endpoint([("data", data_width)])
# # #
valid = Signal()
data = Signal(data_width)
count = Signal(max=data_width)
# JTAG TAP ---------------------------------------------------------------------------------
if jtag is None:
# Xilinx.
if XilinxJTAG.get_primitive(device) is not None:
jtag = XilinxJTAG(primitive=XilinxJTAG.get_primitive(device), chain=chain)
# Lattice.
elif device[:5] == "LFE5U":
jtag = ECP5JTAG()
# Altera/Intel.
elif AlteraJTAG.get_primitive(device) is not None:
platform.add_reserved_jtag_decls()
jtag = AlteraJTAG(
primitive = AlteraJTAG.get_primitive(device),
pads = platform.get_reserved_jtag_pads()
)
else:
print(device)
raise NotImplementedError
self.submodules.jtag = jtag
# JTAG clock domain ------------------------------------------------------------------------
self.clock_domains.cd_jtag = ClockDomain()
self.comb += ClockSignal("jtag").eq(jtag.tck)
self.specials += AsyncResetSynchronizer(self.cd_jtag, ResetSignal(clock_domain))
# JTAG clock domain crossing ---------------------------------------------------------------
if clock_domain != "jtag":
tx_cdc = stream.AsyncFIFO([("data", data_width)], 4)
tx_cdc = ClockDomainsRenamer({"write": clock_domain, "read": "jtag"})(tx_cdc)
rx_cdc = stream.AsyncFIFO([("data", data_width)], 4)
rx_cdc = ClockDomainsRenamer({"write": "jtag", "read": clock_domain})(rx_cdc)
self.submodules.tx_cdc = tx_cdc
self.submodules.rx_cdc = rx_cdc
self.comb += [
sink.connect(tx_cdc.sink),
rx_cdc.source.connect(source)
]
sink, source = tx_cdc.source, rx_cdc.sink
# JTAG Xfer FSM ----------------------------------------------------------------------------
fsm = FSM(reset_state="XFER-READY")
fsm = ClockDomainsRenamer("jtag")(fsm)
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.comb += fsm.reset.eq(jtag.reset | jtag.capture)
fsm.act("XFER-READY",
jtag.tdo.eq(source.ready),
If(jtag.shift,
sink.ready.eq(jtag.tdi),
NextValue(valid, sink.valid),
NextValue(data, sink.data),
NextValue(count, 0),
NextState("XFER-DATA")
)
)
fsm.act("XFER-DATA",
jtag.tdo.eq(data),
If(jtag.shift,
NextValue(count, count + 1),
NextValue(data, Cat(data[1:], jtag.tdi)),
If(count == (data_width - 1),
NextState("XFER-VALID")
)
)
)
fsm.act("XFER-VALID",
jtag.tdo.eq(valid),
If(jtag.shift,
source.valid.eq(jtag.tdi),
NextState("XFER-READY")
)
)
self.comb += source.data.eq(data)
| [
"litex.soc.interconnect.stream.AsyncFIFO",
"litex.soc.interconnect.stream.Endpoint"
] | [((12313, 12352), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (12328, 12352), False, 'from litex.soc.interconnect import stream\n'), ((12384, 12423), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (12399, 12423), False, 'from litex.soc.interconnect import stream\n'), ((13848, 13891), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', data_width)]", '(4)'], {}), "([('data', data_width)], 4)\n", (13864, 13891), False, 'from litex.soc.interconnect import stream\n'), ((14003, 14046), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', data_width)]", '(4)'], {}), "([('data', data_width)], 4)\n", (14019, 14046), False, 'from litex.soc.interconnect import stream\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import fomu_pvt
from litex.soc.cores.ram import Up5kSPRAM
from litex.soc.cores.clock import iCE40PLL
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
kB = 1024
mB = 1024*kB
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
assert sys_clk_freq == 12e6
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_usb_12 = ClockDomain()
self.clock_domains.cd_usb_48 = ClockDomain()
# # #
# Clk/Rst
clk48 = platform.request("clk48")
platform.add_period_constraint(clk48, 1e9/48e6)
# Power On Reset
por_count = Signal(16, reset=2**16-1)
por_done = Signal()
self.comb += self.cd_por.clk.eq(ClockSignal())
self.comb += por_done.eq(por_count == 0)
self.sync.por += If(~por_done, por_count.eq(por_count - 1))
# USB PLL
self.submodules.pll = pll = iCE40PLL()
#self.comb += pll.reset.eq(self.rst) # FIXME: Add proper iCE40PLL reset support and add back | self.rst.
pll.clko_freq_range = ( 12e6, 275e9) # FIXME: improve iCE40PLL to avoid lowering clko_freq_min.
pll.register_clkin(clk48, 48e6)
pll.create_clkout(self.cd_usb_12, 12e6, with_reset=False)
self.comb += self.cd_usb_48.clk.eq(clk48)
self.specials += AsyncResetSynchronizer(self.cd_usb_12, ~por_done | ~pll.locked)
self.specials += AsyncResetSynchronizer(self.cd_usb_48, ~por_done | ~pll.locked)
# Sys Clk
self.comb += self.cd_sys.clk.eq(self.cd_usb_12.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, spi_flash_module="AT25SF161", sys_clk_freq=int(12e6),
with_led_chaser=True, **kwargs):
kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM
platform = fomu_pvt.Platform()
# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
kwargs["integrated_sram_size"] = 0
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# Serial -----------------------------------------------------------------------------------
# FIXME: do proper install of ValentyUSB.
os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri")
sys.path.append("valentyusb")
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Fomu",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB SPRAM (used as 64kB SRAM / 64kB RAM) -----------------------------------------------
self.submodules.spram = Up5kSPRAM(size=128*kB)
self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128*kB))
self.bus.add_region("sram", SoCRegion(
origin = self.bus.regions["psram"].origin + 0*kB,
size = 64*kB,
linker = True)
)
if not self.integrated_main_ram_size:
self.bus.add_region("main_ram", SoCRegion(
origin = self.bus.regions["psram"].origin + 64*kB,
size = 64*kB,
linker = True)
)
# SPI Flash --------------------------------------------------------------------------------
from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV
from litespi.opcodes import SpiNorFlashOpCodes as Codes
# lambdas for lazy module instantiation.
spi_flash_modules = {
"AT25SF161": lambda: AT25SF161( Codes.READ_1_1_4),
"GD25Q16C": lambda: GD25Q16C( Codes.READ_1_1_1),
"MX25R1635F": lambda: MX25R1635F(Codes.READ_1_1_4),
"W25Q128JV": lambda: W25Q128JV( Codes.READ_1_1_4),
}
self.add_spi_flash(mode="4x", module=spi_flash_modules[spi_flash_module](), with_master=False)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 32*kB,
linker = True)
)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led_n"),
sys_clk_freq = sys_clk_freq)
# Flash --------------------------------------------------------------------------------------------
def flash(build_dir, build_name, bios_flash_offset):
from litex.build.dfu import DFUProg
prog = DFUProg(vid="1209", pid="5bf0")
bitstream = open(f"{build_dir}/gateware/{build_name}.bin", "rb")
bios = open(f"{build_dir}/software/bios/bios.bin", "rb")
image = open(f"{build_dir}/image.bin", "wb")
# Copy bitstream at 0.
assert bios_flash_offset >= 128*kB
for i in range(0, bios_flash_offset):
b = bitstream.read(1)
if not b:
image.write(0xff.to_bytes(1, "big"))
else:
image.write(b)
# Copy bios at bios_flash_offset.
for i in range(0, 32*kB):
b = bios.read(1)
if not b:
image.write(0xff.to_bytes(1, "big"))
else:
image.write(b)
bitstream.close()
bios.close()
image.close()
prog.load_bitstream(f"{build_dir}/image.bin")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Fomu")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency.")
parser.add_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.")
parser.add_argument("--flash", action="store_true", help="Flash Bitstream.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
dfu_flash_offset = 0x40000
soc = BaseSoC(
bios_flash_offset = dfu_flash_offset + int(args.bios_flash_offset, 0),
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.flash:
flash(builder.output_dir, soc.build_name, int(args.bios_flash_offset, 0))
if __name__ == "__main__":
main()
| [
"litex.soc.integration.soc.SoCRegion",
"litex.soc.cores.ram.Up5kSPRAM",
"litex.build.dfu.DFUProg",
"litex.soc.cores.clock.iCE40PLL"
] | [((5901, 5932), 'litex.build.dfu.DFUProg', 'DFUProg', ([], {'vid': '"""1209"""', 'pid': '"""5bf0"""'}), "(vid='1209', pid='5bf0')\n", (5908, 5932), False, 'from litex.build.dfu import DFUProg\n'), ((6804, 6860), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Fomu"""'}), "(description='LiteX SoC on Fomu')\n", (6827, 6860), False, 'import argparse\n'), ((1592, 1602), 'litex.soc.cores.clock.iCE40PLL', 'iCE40PLL', ([], {}), '()\n', (1600, 1602), False, 'from litex.soc.cores.clock import iCE40PLL\n'), ((2002, 2065), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_usb_12', '(~por_done | ~pll.locked)'], {}), '(self.cd_usb_12, ~por_done | ~pll.locked)\n', (2024, 2065), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2091, 2154), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_usb_48', '(~por_done | ~pll.locked)'], {}), '(self.cd_usb_48, ~por_done | ~pll.locked)\n', (2113, 2154), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2259, 2319), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '(~por_done | ~pll.locked)'], {}), '(self.cd_sys, ~por_done | ~pll.locked)\n', (2281, 2319), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2740, 2759), 'litex_boards.platforms.fomu_pvt.Platform', 'fomu_pvt.Platform', ([], {}), '()\n', (2757, 2759), False, 'from litex_boards.platforms import fomu_pvt\n'), ((3226, 3304), 'os.system', 'os.system', (['"""git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri"""'], {}), "('git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri')\n", (3235, 3304), False, 'import os\n'), ((3313, 3342), 'sys.path.append', 'sys.path.append', (['"""valentyusb"""'], {}), "('valentyusb')\n", (3328, 3342), False, 'import sys\n'), ((3902, 3926), 'litex.soc.cores.ram.Up5kSPRAM', 'Up5kSPRAM', ([], {'size': '(128 * kB)'}), '(size=128 * kB)\n', (3911, 3926), False, 'from litex.soc.cores.ram import Up5kSPRAM\n'), ((3977, 4001), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'size': '(128 * kB)'}), '(size=128 * kB)\n', (3986, 4001), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((4037, 4127), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': "(self.bus.regions['psram'].origin + 0 * kB)", 'size': '(64 * kB)', 'linker': '(True)'}), "(origin=self.bus.regions['psram'].origin + 0 * kB, size=64 * kB,\n linker=True)\n", (4046, 4127), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((5263, 5356), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': "(self.mem_map['spiflash'] + bios_flash_offset)", 'size': '(32 * kB)', 'linker': '(True)'}), "(origin=self.mem_map['spiflash'] + bios_flash_offset, size=32 * kB,\n linker=True)\n", (5272, 5356), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((4277, 4368), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': "(self.bus.regions['psram'].origin + 64 * kB)", 'size': '(64 * kB)', 'linker': '(True)'}), "(origin=self.bus.regions['psram'].origin + 64 * kB, size=64 * kB,\n linker=True)\n", (4286, 4368), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((4791, 4818), 'litespi.modules.AT25SF161', 'AT25SF161', (['Codes.READ_1_1_4'], {}), '(Codes.READ_1_1_4)\n', (4800, 4818), False, 'from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV\n'), ((4855, 4881), 'litespi.modules.GD25Q16C', 'GD25Q16C', (['Codes.READ_1_1_1'], {}), '(Codes.READ_1_1_1)\n', (4863, 4881), False, 'from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV\n'), ((4919, 4947), 'litespi.modules.MX25R1635F', 'MX25R1635F', (['Codes.READ_1_1_4'], {}), '(Codes.READ_1_1_4)\n', (4929, 4947), False, 'from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV\n'), ((4983, 5010), 'litespi.modules.W25Q128JV', 'W25Q128JV', (['Codes.READ_1_1_4'], {}), '(Codes.READ_1_1_4)\n', (4992, 5010), False, 'from litespi.modules import AT25SF161, GD25Q16C, MX25R1635F, W25Q128JV\n')] |
# This file is Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("K17"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J17"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("L14"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("L15"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("L16"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("K16"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("M15"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("M16"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("B21"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("A21"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("E22"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("D22"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("E21"), IOStandard("LVCMOS33")),
("user_sw", 5, Pins("D21"), IOStandard("LVCMOS33")),
("user_sw", 6, Pins("G21"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("G22"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("P20"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("P19"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("P17"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("N17"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("H4"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("M2"), IOStandard("LVCMOS33")),
("serial", 0, # Can be used when FT2232H's Channel A configured to ASYNC Serial (UART) mode
Subsignal("tx", Pins("Y21")),
Subsignal("rx", Pins("Y22")),
IOStandard("LVCMOS33")
),
("usb_fifo", 0, # Can be used when FT2232H's Channel A configured to ASYNC FIFO 245 mode
Subsignal("data", Pins("Y22 Y21 AB22 AA21 AB21 AA20 AB20 AA18")),
Subsignal("rxf_n", Pins("W21")),
Subsignal("txe_n", Pins("V22")),
Subsignal("rd_n", Pins("AA19")),
Subsignal("wr_n", Pins("W22")),
Subsignal("siwua", Pins("U21")),
Subsignal("oe_n", Pins("T21")),
Misc("SLEW=FAST"),
Drive(8),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("clk", Pins("L12")),
Subsignal("dq", Pins("P22", "R22", "P21", "R21")),
IOStandard("LVCMOS33")
),
("spiflash", 0,
Subsignal("cs_n", Pins("T19")),
Subsignal("clk", Pins("L12")),
Subsignal("mosi", Pins("P22")),
Subsignal("miso", Pins("R22")),
Subsignal("wp", Pins("P21")),
Subsignal("hold", Pins("R21")),
IOStandard("LVCMOS33"),
),
("ddram", 0,
Subsignal("a", Pins(
"U6 T5 Y6 T6 V2 T4 Y2 R2",
"Y1 R4 W5 W1 AA6 U2"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("W6 U5 R6"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("V5"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T1"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("Y7 AA1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"Y8 AB6 W9 AA8 AB7 V7 AB8 W7",
"V4 AB2 AA5 AB3 AB5 W4 AB1 AA4"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("V9 Y3"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("V8 AA3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U3"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V3"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("U1"), IOStandard("SSTL15")),
Subsignal("odt", Pins("W2"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("U7"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("eeprom", 0,
Subsignal("scl", Pins("N5")),
Subsignal("sda", Pins("P6")),
IOStandard("LVCMOS33")
),
("eth_clocks", 0,
Subsignal("tx", Pins("U20")),
Subsignal("rx", Pins("W19")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("R14"), IOStandard("LVCMOS33")),
Subsignal("int_n", Pins("V19")),
Subsignal("mdio", Pins("P16")),
Subsignal("mdc", Pins("R19")),
Subsignal("rx_ctl", Pins("Y19")),
Subsignal("rx_data", Pins("AB18 W20 W17 V20")),
Subsignal("tx_ctl", Pins("T20")),
Subsignal("tx_data", Pins("V18 U18 V17 U17")),
IOStandard("LVCMOS33")
),
("hdmi_in", 0,
Subsignal("clk_p", Pins("K4"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("J4"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("K1"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("J1"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("M1"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("L1"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("P2"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("N2"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("J2"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("H2"), IOStandard("LVCMOS33")),
Subsignal("hpd_en", Pins("G2"), IOStandard("LVCMOS33")),
Subsignal("cec", Pins("K2"), IOStandard("LVCMOS33")), # FIXME
# Subsignal("txen", Pins("R3"), IOStandard("LVCMOS33")), # FIXME
),
("hdmi_out", 0,
Subsignal("clk_p", Pins("L3"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("K3"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("B1"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("A1"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("E1"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("D1"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("G1"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("F1"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("D2"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("C2"), IOStandard("LVCMOS33")),
Subsignal("cec", Pins("E2"), IOStandard("LVCMOS33")), # FIXME
Subsignal("hdp", Pins("B2"), IOStandard("LVCMOS33")), # FIXME
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("P12", "J20 J21 K21 K22 H20 G20 J19 H19",
"J22 H22 K18 K19 L19 L20 M21 N22",
"N20 M20 M18 L18 N18 N19 H17 H18",
"G17 G18 G15 G16 J15 H15 K13 K14",
"M13 K14 M13 L13 J14 H14 H13 G13"),
("P13", "F19 F20 E19 D19 D20 C20 C22 B22",
"F18 E18 C18 C19 D17 C17 B20 A20",
"B17 B18 A18 A19 E16 D16 B15 B16",
"A15 A16 C14 C15 A13 A14 C13 B13",
"D14 D15 E13 E14 F13 F14 F16 E17")
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a50tfgg484-1", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a50t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((7349, 7439), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a50tfgg484-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a50tfgg484-1', _io, _connectors,\n toolchain='vivado')\n", (7372, 7439), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((7893, 7951), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a50t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a50t.bit')\n", (7900, 7951), False, 'from litex.build.openocd import OpenOCD\n'), ((7998, 8040), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (8024, 8040), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk27", 0, Pins("54")),
("clk27", 0, Pins("54")),
# Leds
("user_led", 0, Pins("7"),
Misc("CURRENT_STRENGTH_NEW 4MA")),
# Serial
("serial", 0,
Subsignal("tx", Pins("46")),
Subsignal("rx", Pins("31")),
),
# VGA
("vga", 0,
Subsignal("hsync_n", Pins("119")),
Subsignal("vsync_n", Pins("136")),
Subsignal("r", Pins("135 137 141 142 143 144")),
Subsignal("g", Pins("106 110 111 112 113 114")),
Subsignal("b", Pins("115 120 121 125 132 133")),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
),
# Audio
("audio", 0,
Subsignal("l", Pins("65")),
Subsignal("r", Pins("80")),
Misc("CURRENT_STRENGTH_NEW 4MA"),
),
# SPI
("spi", 0,
Subsignal("do", Pins("105")),
Subsignal("di", Pins("88")),
Subsignal("sck", Pins("126")),
Subsignal("ss2", Pins("127")),
Subsignal("ss3", Pins("91")),
Subsignal("ss4", Pins("90")),
),
# SDR SDRAM
("sdram_clock", 0, Pins("43"),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("49 44 42 39 4 6 8 10 11 28 50 30 32")),
Subsignal("dq", Pins("83 79 77 76 72 71 69 68 86 87 98 99 100 101 103 104"),
Misc("FAST_INPUT_REGISTER ON"), Misc("FAST_OUTPUT_ENABLE_REGISTER ON")),
Subsignal("ba", Pins("58 51")),
Subsignal("dm", Pins("67 85")), # DQML, DQMH
Subsignal("ras_n", Pins("60")),
Subsignal("cas_n", Pins("64")),
Subsignal("we_n", Pins("66")),
Subsignal("cs_n", Pins("59")),
Subsignal("cke", Pins("33")),
Misc("FAST_OUTPUT_REGISTER ON"),
Misc("CURRENT_STRENGTH_NEW \"MAXIMUM CURRENT\""),
),
# Others
("conf_data0", 0, Pins("13")),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk27"
default_clk_period = 1e9/27e6
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP3C25E144C8", _io, toolchain="quartus")
self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone III\"")
self.add_platform_command("set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144")
self.add_platform_command("set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED")
self.add_platform_command("set_global_assignment -name USE_CONFIGURATION_DEVICE OFF")
self.add_platform_command("set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME \"PASSIVE SERIAL\"")
self.add_platform_command("set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP \"AS INPUT TRI-STATED\"")
self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name STRATIX_DEVICE_IO_STANDARD \"3.3-V LVTTL\"")
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk27", 0, loose=True), 1e9/27e6)
self.add_period_constraint(self.lookup_request("clk27", 1, loose=True), 1e9/27e6)
| [
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__",
"litex.build.altera.AlteraPlatform.do_finalize"
] | [((2510, 2581), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP3C25E144C8"""', '_io'], {'toolchain': '"""quartus"""'}), "(self, 'EP3C25E144C8', _io, toolchain='quartus')\n", (2533, 2581), False, 'from litex.build.altera import AlteraPlatform\n'), ((3979, 3991), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (3989, 3991), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((4038, 4080), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4064, 4080), False, 'from litex.build.altera import AlteraPlatform\n')] |
#!/usr/bin/env python3
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("user_led", 0, Pins("H17"), IOStandard("LVCMOS33")),
("user_sw", 0, Pins("J15"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("N17"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C12"), IOStandard("LVCMOS33")),
("user_rgb_led_r", 0, Pins("N16"), IOStandard("LVCMOS33")),
("user_rgb_led_g", 0, Pins("R11"), IOStandard("LVCMOS33")),
("user_rgb_led_b", 0, Pins("G14"), IOStandard("LVCMOS33")),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e6/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a100t-csg324-1", _io, toolchain="vivado")
# Design -------------------------------------------------------------------------------------------
# Create our platform (fpga interface)
platform = Platform()
# Create our module (fpga description)
class Blink(Module):
def __init__(self, blink_freq, sys_clk_freq, led):
counter = Signal(32)
# synchronous assignments
self.sync += [
counter.eq(counter + 1),
If(counter == int((sys_clk_freq/blink_freq)/2 - 1),
counter.eq(0),
led.eq(~led)
)
]
# combinatorial assignements
self.comb += []
class RGBBlink(Module):
def __init__(self, platform):
# submodules
blink_r = Blink(1, 100e6, platform.request("user_rgb_led_r"))
blink_g = Blink(2, 100e6, platform.request("user_rgb_led_g"))
blink_b = Blink(4, 100e6, platform.request("user_rgb_led_b"))
self.submodules += blink_r, blink_g, blink_b
module = RGBBlink(platform)
# Build --------------------------------------------------------------------------------------------
platform.build(module)
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((970, 1045), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a100t-csg324-1"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a100t-csg324-1', _io, toolchain='vivado')\n", (993, 1045), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2016-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.interconnect import stream
from litedram.common import *
# LiteDRAMNativePortCDC ----------------------------------------------------------------------------
class LiteDRAMNativePortCDC(Module):
def __init__(self, port_from, port_to,
cmd_depth = 4,
wdata_depth = 16,
rdata_depth = 16):
assert port_from.address_width == port_to.address_width
assert port_from.data_width == port_to.data_width
assert port_from.mode == port_to.mode
address_width = port_from.address_width
data_width = port_from.data_width
mode = port_from.mode
# # #
cmd_cdc = stream.ClockDomainCrossing(
layout = [("we", 1), ("addr", address_width)],
cd_from = port_from.clock_domain,
cd_to = port_to.clock_domain,
depth = cmd_depth)
self.submodules += cmd_cdc
self.submodules += stream.Pipeline(port_from.cmd, cmd_cdc, port_to.cmd)
if mode in ["write", "both"]:
wdata_cdc = stream.ClockDomainCrossing(
layout = [("data", data_width), ("we", data_width//8)],
cd_from = port_from.clock_domain,
cd_to = port_to.clock_domain,
depth = wdata_depth)
self.submodules += wdata_cdc
self.submodules += stream.Pipeline(port_from.wdata, wdata_cdc, port_to.wdata)
if mode in ["read", "both"]:
rdata_cdc = stream.ClockDomainCrossing(
layout = [("data", data_width)],
cd_from = port_to.clock_domain,
cd_to = port_from.clock_domain,
depth = rdata_depth)
self.submodules += rdata_cdc
self.submodules += stream.Pipeline(port_to.rdata, rdata_cdc, port_from.rdata)
# LiteDRAMNativePortDownConverter ------------------------------------------------------------------
class LiteDRAMNativePortDownConverter(Module):
"""LiteDRAM port DownConverter
This module reduces user port data width to fit controller data width.
With N = port_from.data_width/port_to.data_width:
- Address is adapted (multiplied by N + internal increments)
- A write from the user is splitted and generates N writes to the
controller.
- A read from the user generates N reads to the controller and returned
datas are regrouped in a single data presented to the user.
"""
def __init__(self, port_from, port_to, reverse=False):
assert port_from.clock_domain == port_to.clock_domain
assert port_from.data_width > port_to.data_width
assert port_from.mode == port_to.mode
if port_from.data_width % port_to.data_width:
raise ValueError("Ratio must be an int")
# # #
ratio = port_from.data_width//port_to.data_width
mode = port_from.mode
count = Signal(max=ratio)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
NextValue(count, 0),
If(port_from.cmd.valid,
NextState("CONVERT")
)
)
fsm.act("CONVERT",
port_to.cmd.valid.eq(1),
port_to.cmd.we.eq(port_from.cmd.we),
port_to.cmd.addr.eq(port_from.cmd.addr*ratio + count),
If(port_to.cmd.ready,
NextValue(count, count + 1),
If(count == (ratio - 1),
port_from.cmd.ready.eq(1),
NextState("IDLE")
)
)
)
if mode in ["write", "both"]:
wdata_converter = stream.StrideConverter(
description_from = port_from.wdata.description,
description_to = port_to.wdata.description,
reverse = reverse)
self.submodules += wdata_converter
self.submodules += stream.Pipeline(port_from.wdata, wdata_converter, port_to.wdata)
if mode in ["read", "both"]:
rdata_converter = stream.StrideConverter(
description_from = port_to.rdata.description,
description_to = port_from.rdata.description,
reverse = reverse)
self.submodules += rdata_converter
self.submodules += stream.Pipeline(
port_to.rdata, rdata_converter, port_from.rdata)
# LiteDRAMNativePortUpConverter --------------------------------------------------------------------
class LiteDRAMNativePortUpConverter(Module):
"""LiteDRAM port UpConverter
This module increase user port data width to fit controller data width.
With N = port_to.data_width/port_from.data_width:
- Address is adapted (divided by N)
- N read from user are regrouped in a single one to the controller
(when possible, ie when consecutive and bursting)
- N writes from user are regrouped in a single one to the controller
(when possible, ie when consecutive and bursting)
Incomplete writes/reads (i.e. with n < N) are handled automatically in the
middle of a burst, but last command has to use cmd.last=1 if the last burst
is not complete (not all N addresses have been used).
"""
def __init__(self, port_from, port_to, reverse=False):
assert port_from.clock_domain == port_to.clock_domain
assert port_from.data_width < port_to.data_width
assert port_from.mode == port_to.mode
if port_to.data_width % port_from.data_width:
raise ValueError("Ratio must be an int")
# # #
ratio = port_to.data_width//port_from.data_width
mode = port_from.mode
# Command ----------------------------------------------------------------------------------
# Defines cmd type and the chunks that have been requested for the current port_to command.
sel = Signal(ratio)
cmd_buffer = stream.SyncFIFO([("sel", ratio), ("we", 1)], 0)
self.submodules += cmd_buffer
# Store last received command.
cmd_addr = Signal.like(port_from.cmd.addr)
cmd_we = Signal()
cmd_last = Signal()
# Indicates that we need to proceed to the next port_to command.
next_cmd = Signal()
addr_changed = Signal()
# Signals that indicate that write/read convertion has finished.
wdata_finished = Signal()
rdata_finished = Signal()
# Used to prevent reading old memory value if previous command has written the same address.
read_lock = Signal()
read_unlocked = Signal()
rw_collision = Signal()
# Different order depending on read/write:
# - read: new -> cmd -> fill -> commit -> new
# - write: new -> fill -> commit -> cmd -> new
# For writes we have to send the command at the end to prevent situations when, during
# a burst, LiteDRAM expects data (wdata_ready=1) but write converter is still converting.
self.submodules.fsm = fsm = FSM()
fsm.act("NEW",
port_from.cmd.ready.eq(port_from.cmd.valid & ~read_lock),
If(port_from.cmd.ready,
NextValue(cmd_addr, port_from.cmd.addr),
NextValue(cmd_we, port_from.cmd.we),
NextValue(cmd_last, port_from.cmd.last),
NextValue(sel, 1 << port_from.cmd.addr[:log2_int(ratio)]),
If(port_from.cmd.we,
NextState("FILL"),
).Else(
NextState("CMD"),
)
)
)
fsm.act("CMD",
port_to.cmd.valid.eq(1),
port_to.cmd.we.eq(cmd_we),
port_to.cmd.addr.eq(cmd_addr[log2_int(ratio):]),
If(port_to.cmd.ready,
If(cmd_we,
NextState("NEW")
).Else(
NextState("FILL")
)
)
)
fsm.act("FILL",
If(next_cmd,
NextState("COMMIT")
).Else( # Acknowledge incomming commands, while filling `sel`.
port_from.cmd.ready.eq(port_from.cmd.valid),
NextValue(cmd_last, port_from.cmd.last),
NextValue(sel, sel | 1 << port_from.cmd.addr[:log2_int(ratio)]),
)
)
fsm.act("COMMIT",
cmd_buffer.sink.valid.eq(1),
cmd_buffer.sink.sel.eq(sel),
cmd_buffer.sink.we.eq(cmd_we),
If(cmd_buffer.sink.ready,
If(cmd_we,
NextState("CMD")
).Else(
NextState("NEW")
)
)
)
self.comb += [
cmd_buffer.source.ready.eq(wdata_finished | rdata_finished),
addr_changed.eq(cmd_addr[log2_int(ratio):] != port_from.cmd.addr[log2_int(ratio):]),
# Collision happens on write to read transition when address does not change.
rw_collision.eq(cmd_we & (port_from.cmd.valid & ~port_from.cmd.we) & ~addr_changed),
# Go to the next command if one of the following happens:
# - port_to address changes.
# - cmd type changes.
# - we received all the `ratio` commands.
# - this is the last command in a sequence.
# - master requests a flush (even after the command has been sent).
next_cmd.eq(addr_changed | (cmd_we != port_from.cmd.we) | (sel == 2**ratio - 1)
| cmd_last | port_from.flush),
]
self.sync += [
# Block sending read command if we have just written to that address
If(wdata_finished,
read_lock.eq(0),
read_unlocked.eq(1),
).Elif(rw_collision & ~port_to.cmd.valid & ~read_unlocked,
read_lock.eq(1)
),
If(port_from.cmd.valid & port_from.cmd.ready,
read_unlocked.eq(0)
)
]
# Read Datapath ----------------------------------------------------------------------------
if mode in ["read", "both"]:
# Queue received data not to loose it when it comes too fast.
rdata_fifo = stream.SyncFIFO(port_to.rdata.description, ratio - 1)
rdata_converter = stream.StrideConverter(
description_from = port_to.rdata.description,
description_to = port_from.rdata.description,
reverse = reverse)
self.submodules += rdata_fifo, rdata_converter
# Shift register with a bitmask of current chunk.
rdata_chunk = Signal(ratio, reset=1)
rdata_chunk_valid = Signal()
self.sync += \
If(rdata_converter.source.valid &
rdata_converter.source.ready,
rdata_chunk.eq(Cat(rdata_chunk[ratio-1], rdata_chunk[:ratio-1]))
)
self.comb += [
# port_to -> rdata_fifo -> rdata_converter -> port_from
port_to.rdata.connect(rdata_fifo.sink),
rdata_fifo.source.connect(rdata_converter.sink),
rdata_chunk_valid.eq((cmd_buffer.source.sel & rdata_chunk) != 0),
If(cmd_buffer.source.valid & ~cmd_buffer.source.we,
# If that chunk is valid we send it to the user port and wait for ready.
If(rdata_chunk_valid,
port_from.rdata.valid.eq(rdata_converter.source.valid),
port_from.rdata.data.eq(rdata_converter.source.data),
rdata_converter.source.ready.eq(port_from.rdata.ready)
).Else( # If this chunk was not requested in `sel`, ignore it.
rdata_converter.source.ready.eq(1)
),
rdata_finished.eq(rdata_converter.source.valid & rdata_converter.source.ready
& rdata_chunk[ratio - 1])
),
]
# Write Datapath ---------------------------------------------------------------------------
if mode in ["write", "both"]:
# Queue write data not to miss it when the lower chunks haven't been reqested.
wdata_fifo = stream.SyncFIFO(port_from.wdata.description, ratio - 1)
wdata_buffer = stream.SyncFIFO(port_to.wdata.description, 1)
wdata_converter = stream.StrideConverter(
description_from = port_from.wdata.description,
description_to = port_to.wdata.description,
reverse = reverse)
self.submodules += wdata_converter, wdata_fifo, wdata_buffer
# Shift register with a bitmask of current chunk.
wdata_chunk = Signal(ratio, reset=1)
wdata_chunk_valid = Signal()
self.sync += \
If(wdata_converter.sink.valid & wdata_converter.sink.ready,
wdata_chunk.eq(Cat(wdata_chunk[ratio-1], wdata_chunk[:ratio-1]))
)
# Replicate `sel` bits to match the width of port_to.wdata.we.
wdata_sel = Signal.like(port_to.wdata.we)
if reverse:
wdata_sel_parts = [
Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
for i in reversed(range(ratio))
]
else:
wdata_sel_parts = [
Replicate(cmd_buffer.source.sel[i], port_to.wdata.we.nbits // sel.nbits)
for i in range(ratio)
]
self.sync += \
If(cmd_buffer.source.valid & cmd_buffer.source.we & wdata_chunk[ratio - 1],
wdata_sel.eq(Cat(wdata_sel_parts))
)
self.comb += [
# port_from -> wdata_fifo -> wdata_converter
port_from.wdata.connect(wdata_fifo.sink),
wdata_buffer.source.connect(port_to.wdata),
wdata_chunk_valid.eq((cmd_buffer.source.sel & wdata_chunk) != 0),
If(cmd_buffer.source.valid & cmd_buffer.source.we,
# When the current chunk is valid, read it from wdata_fifo.
If(wdata_chunk_valid,
wdata_converter.sink.valid.eq(wdata_fifo.source.valid),
wdata_converter.sink.data.eq(wdata_fifo.source.data),
wdata_converter.sink.we.eq(wdata_fifo.source.we),
wdata_fifo.source.ready.eq(wdata_converter.sink.ready),
).Else( # If chunk is not valid, send any data and do not advance fifo.
wdata_converter.sink.valid.eq(1),
),
),
wdata_buffer.sink.valid.eq(wdata_converter.source.valid),
wdata_buffer.sink.data.eq(wdata_converter.source.data),
wdata_buffer.sink.we.eq(wdata_converter.source.we & wdata_sel),
wdata_converter.source.ready.eq(wdata_buffer.sink.ready),
wdata_finished.eq(wdata_converter.sink.valid & wdata_converter.sink.ready
& wdata_chunk[ratio-1]),
]
# LiteDRAMNativePortConverter ----------------------------------------------------------------------
class LiteDRAMNativePortConverter(Module):
def __init__(self, port_from, port_to, reverse=False):
assert port_from.clock_domain == port_to.clock_domain
assert port_from.mode == port_to.mode
# # #
ratio = port_from.data_width/port_to.data_width
if ratio > 1:
# DownConverter
self.submodules.converter = LiteDRAMNativePortDownConverter(port_from, port_to, reverse)
elif ratio < 1:
# UpConverter
self.submodules.converter = LiteDRAMNativePortUpConverter(port_from, port_to, reverse)
else:
# Identity
self.comb += port_from.connect(port_to)
| [
"litex.soc.interconnect.stream.ClockDomainCrossing",
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream.StrideConverter",
"litex.soc.interconnect.stream.SyncFIFO"
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from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import AutoCSR
from migen import *
from litex.soc.interconnect import wishbone
class HardSPIWrapper(Module):
def __init__(self, instance):
assert instance in [0, 1]
# CSn
self.mcsnoe = Signal(4)
self.mcsno = Signal(4)
self.scsn = Signal()
# SCK
self.scko = Signal()
self.scki = Signal()
self.sckoe = Signal()
# MISO
self.mi = Signal()
self.so = Signal()
self.soe = Signal()
# MOSI
self.mo = Signal()
self.si = Signal()
self.moe = Signal()
# System Bus
self.sb_addr = Signal(4)
self.sb_di = Signal(8)
self.sb_do = Signal(8)
self.sb_rw = Signal()
self.sb_stb = Signal()
self.sb_ack = Signal()
self.specials += Instance(
"SB_SPI",
i_SBCLKI=ClockSignal(),
i_SBRWI=self.sb_rw,
i_SBSTBI=self.sb_stb,
i_SBADRI0=self.sb_addr[0],
i_SBADRI1=self.sb_addr[1],
i_SBADRI2=self.sb_addr[2],
i_SBADRI3=self.sb_addr[3],
i_SBADRI4=0,
i_SBADRI5=instance,
i_SBADRI6=0,
i_SBADRI7=0,
i_SBDATI0=self.sb_di[0],
i_SBDATI1=self.sb_di[1],
i_SBDATI2=self.sb_di[2],
i_SBDATI3=self.sb_di[3],
i_SBDATI4=self.sb_di[4],
i_SBDATI5=self.sb_di[5],
i_SBDATI6=self.sb_di[6],
i_SBDATI7=self.sb_di[7],
o_SBDATO0=self.sb_do[0],
o_SBDATO1=self.sb_do[1],
o_SBDATO2=self.sb_do[2],
o_SBDATO3=self.sb_do[3],
o_SBDATO4=self.sb_do[4],
o_SBDATO5=self.sb_do[5],
o_SBDATO6=self.sb_do[6],
o_SBDATO7=self.sb_do[7],
o_SBACKO=self.sb_ack,
i_MI=self.mi,
o_SO=self.so,
o_SOE=self.soe,
i_SI=self.si,
o_MO=self.mo,
o_MOE=self.moe,
i_SCKI=self.scki,
o_SCKO=self.scko,
o_SCKOE=self.sckoe,
i_SCSNI=self.scsn,
o_MCSNO0=self.mcsno[0],
o_MCSNO1=self.mcsno[1],
o_MCSNO2=self.mcsno[2],
o_MCSNO3=self.mcsno[3],
o_MCSNOE0=self.mcsnoe[0],
o_MCSNOE1=self.mcsnoe[1],
o_MCSNOE2=self.mcsnoe[2],
o_MCSNOE3=self.mcsnoe[3],
p_BUS_ADDR74=["0b0000", "0b0010"][instance],
)
class HardSPISlavePeripheral(Module):
def __init__(self, spi_pads, instance=0):
assert instance in [0, 1]
self.bus = bus = wishbone.Interface()
self.submodules.spi = spi = HardSPIWrapper(instance)
self.specials += Instance(
"SB_IO",
io_PACKAGE_PIN=spi_pads.cs_n,
i_OUTPUT_ENABLE=0,
o_D_IN_0=spi.scsn,
p_PIN_TYPE=0b101001,
p_PULLUP=1,
)
self.specials += Instance(
"SB_IO",
io_PACKAGE_PIN=spi_pads.miso,
i_OUTPUT_ENABLE=spi.soe,
i_D_OUT_0=spi.so,
p_PIN_TYPE=0b101001,
)
self.comb += [
spi.scki.eq(spi_pads.clk),
spi.si.eq(spi_pads.mosi),
]
self.comb += [
spi.sb_addr.eq(bus.adr[0:4]),
spi.sb_di.eq(bus.dat_w[0:8]),
spi.sb_rw.eq(bus.we),
spi.sb_stb.eq(bus.cyc),
If(bus.cyc, bus.dat_r.eq(spi.sb_do)),
bus.ack.eq(spi.sb_ack),
]
class HardSPISlave(Module):
def __init__(self, spi_pads, instance=0):
self.submodules.spi = spi = HardSPIWrapper(instance)
self.start = Signal()
self.done = Signal()
self.byte = Signal()
self.mosi = Signal(8)
self.miso = Signal(8)
self.dbg_status = Signal()
self.specials += Instance(
"SB_IO",
io_PACKAGE_PIN=spi_pads.cs_n,
i_OUTPUT_ENABLE=0,
o_D_IN_0=spi.scsn,
p_PIN_TYPE=0b101001,
p_PULLUP=1,
)
self.specials += Instance(
"SB_IO",
io_PACKAGE_PIN=spi_pads.miso,
i_OUTPUT_ENABLE=spi.soe,
i_D_OUT_0=spi.so,
p_PIN_TYPE=0b101001,
)
self.comb += [
spi.scki.eq(spi_pads.clk),
spi.si.eq(spi_pads.mosi),
]
sr_busy = Signal()
self.submodules.fsm = fsm = FSM(reset_state="RESET")
fsm.act("RESET",
spi.sb_stb.eq(1),
spi.sb_rw.eq(1),
spi.sb_addr.eq(0b1001), # SPICR1
spi.sb_di.eq(0b10000000), # Enable SPI
If(spi.sb_ack, NextState("IDLE"))
)
fsm.act("IDLE",
NextValue(self.byte, 0),
NextState("READ_STATUS")
)
fsm.act("READ_STATUS",
spi.sb_stb.eq(1),
spi.sb_rw.eq(0),
spi.sb_addr.eq(0b1100), # SPISR
self.dbg_status.eq(1),
If(spi.sb_ack,
NextValue(sr_busy, spi.sb_do[6]),
If(spi.sb_do[4],
NextState("UPDATE_TX_START")
).Elif(spi.sb_do[3],
NextState("UPDATE_RX_START")
).Else(
NextState("IDLE")
)
)
)
fsm.act("UPDATE_TX_START", NextState("UPDATE_TX"))
fsm.act("UPDATE_TX",
spi.sb_stb.eq(1),
spi.sb_rw.eq(1),
spi.sb_addr.eq(0b1101), # SPITXDR
spi.sb_di.eq(self.miso),
If(spi.sb_ack, NextState("IDLE"))
)
fsm.act("UPDATE_RX_START", NextState("UPDATE_RX"))
fsm.act("UPDATE_RX",
spi.sb_stb.eq(1),
spi.sb_rw.eq(0),
spi.sb_addr.eq(0b1110), # SPIRXDR
If(spi.sb_ack,
NextValue(self.mosi, spi.sb_do),
NextValue(self.byte, 1),
NextState("IDLE")
)
)
sr_busy_d = Signal()
self.sync += sr_busy_d.eq(sr_busy)
self.comb += [
self.start.eq(sr_busy & ~sr_busy_d),
self.done.eq(~sr_busy),
] | [
"litex.soc.interconnect.wishbone.Interface"
] | [((2723, 2743), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2741, 2743), False, 'from litex.soc.interconnect import wishbone\n')] |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from migen.genlib.cdc import MultiReg, PulseSynchronizer
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect import stream
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO
def framer_params():
return [
("x_start", 16),
("y_start", 16),
("x_stop", 16),
("y_stop", 16),
]
class Framer(Module, AutoCSR):
def __init__(self):
self.sink = sink = Endpoint([("data", 32)])
self.params = params = Endpoint(framer_params())
self.hsync = hsync = Signal()
self.vsync = vsync = Signal()
# VGA output
self.red = red = Signal(8)
self.green = green = Signal(8)
self.blue = blue = Signal(8)
self.data_valid = data_valid = Signal()
# parameters
pixel_counter = Signal(14)
line_counter = Signal(14)
h_det = EdgeDetect(mode="fall", input_cd="video", output_cd="video")
v_det = EdgeDetect(mode="fall", input_cd="video", output_cd="video")
self.submodules += h_det, v_det
self.comb += [
h_det.i.eq(hsync),
v_det.i.eq(vsync),
]
self.comb += [
If((line_counter >= params.y_start) & (line_counter < params.y_stop),
If((pixel_counter >= params.x_start) & (pixel_counter < params.x_stop),
sink.ready.eq(1)
)
)
]
self.sync.video += [
# Default values
red.eq(0),
green.eq(0),
blue.eq(0),
data_valid.eq(0),
# Show pixels
If((line_counter >= params.y_start) & (line_counter < params.y_stop),
If((pixel_counter >= params.x_start) & (pixel_counter < params.x_stop),
data_valid.eq(1),
If(sink.valid,
red.eq(sink.data[0:8]),
green.eq(sink.data[8:16]),
blue.eq(sink.data[16:24])
).Else(
red.eq(0xFF),
green.eq(0x77),
blue.eq(0xFF)
)
)
),
# Horizontal timing for one line
pixel_counter.eq(pixel_counter + 1),
If(h_det.o,
pixel_counter.eq(0),
line_counter.eq(line_counter + 1),
),
If(v_det.o,
line_counter.eq(0),
)
]
class FrameExtraction(Module, AutoCSR):
def __init__(self, fifo_depth):
# in pix clock domain
self.valid_i = Signal()
self.vsync = Signal()
self.de = Signal()
self.data = Signal(16)
# in sys clock domain
word_layout = [("sof", 1), ("pixels", 16)]
self.frame = stream.Endpoint(word_layout)
self.busy = Signal()
self._overflow = CSR()
# # #
# start of frame detection
vsync = self.vsync
vsync_r = Signal()
self.new_frame = new_frame = Signal()
self.comb += new_frame.eq(vsync & ~vsync_r)
self.sync.pix += vsync_r.eq(vsync)
# FIFO
fifo = stream.AsyncFIFO(word_layout, fifo_depth)
fifo = ClockDomainsRenamer({"write": "pix", "read": "sys"})(fifo)
self.submodules += fifo
self.fifo = fifo
self.comb += [
fifo.sink.pixels.eq(self.data),
fifo.sink.valid.eq(self.de)
]
self.sync.pix += \
If(new_frame,
fifo.sink.sof.eq(1)
).Elif(self.de,
fifo.sink.sof.eq(0)
)
self.comb += [
fifo.source.connect(self.frame),
self.busy.eq(0)
]
# overflow detection
pix_overflow = Signal()
pix_overflow_reset = Signal()
self.sync.pix += [
If(fifo.sink.valid & ~fifo.sink.ready,
pix_overflow.eq(1)
).Elif(pix_overflow_reset,
pix_overflow.eq(0)
)
]
sys_overflow = Signal()
self.specials += MultiReg(pix_overflow, sys_overflow)
self.submodules.overflow_reset = PulseSynchronizer("sys", "pix")
self.submodules.overflow_reset_ack = PulseSynchronizer("pix", "sys")
self.comb += [
pix_overflow_reset.eq(self.overflow_reset.o),
self.overflow_reset_ack.i.eq(pix_overflow_reset)
]
overflow_mask = Signal()
self.comb += [
self._overflow.w.eq(sys_overflow & ~overflow_mask),
self.overflow_reset.i.eq(self._overflow.re)
]
self.sync += \
If(self._overflow.re,
overflow_mask.eq(1)
).Elif(self.overflow_reset_ack.o,
overflow_mask.eq(0)
)
| [
"litex.soc.interconnect.stream.AsyncFIFO",
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.stream.Endpoint"
] | [((659, 683), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 32)]"], {}), "([('data', 32)])\n", (667, 683), False, 'from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO\n'), ((1116, 1176), 'rtl.edge_detect.EdgeDetect', 'EdgeDetect', ([], {'mode': '"""fall"""', 'input_cd': '"""video"""', 'output_cd': '"""video"""'}), "(mode='fall', input_cd='video', output_cd='video')\n", (1126, 1176), False, 'from rtl.edge_detect import EdgeDetect\n'), ((1193, 1253), 'rtl.edge_detect.EdgeDetect', 'EdgeDetect', ([], {'mode': '"""fall"""', 'input_cd': '"""video"""', 'output_cd': '"""video"""'}), "(mode='fall', input_cd='video', output_cd='video')\n", (1203, 1253), False, 'from rtl.edge_detect import EdgeDetect\n'), ((3081, 3109), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['word_layout'], {}), '(word_layout)\n', (3096, 3109), False, 'from litex.soc.interconnect import stream\n'), ((3165, 3170), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (3168, 3170), False, 'from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage\n'), ((3448, 3489), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (['word_layout', 'fifo_depth'], {}), '(word_layout, fifo_depth)\n', (3464, 3489), False, 'from litex.soc.interconnect import stream\n'), ((4381, 4417), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pix_overflow', 'sys_overflow'], {}), '(pix_overflow, sys_overflow)\n', (4389, 4417), False, 'from migen.genlib.cdc import MultiReg, PulseSynchronizer\n'), ((4459, 4490), 'migen.genlib.cdc.PulseSynchronizer', 'PulseSynchronizer', (['"""sys"""', '"""pix"""'], {}), "('sys', 'pix')\n", (4476, 4490), False, 'from migen.genlib.cdc import MultiReg, PulseSynchronizer\n'), ((4536, 4567), 'migen.genlib.cdc.PulseSynchronizer', 'PulseSynchronizer', (['"""pix"""', '"""sys"""'], {}), "('pix', 'sys')\n", (4553, 4567), False, 'from migen.genlib.cdc import MultiReg, PulseSynchronizer\n')] |
#
# This file is part of LiteX-on-proFPGA-Systems.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk300", 0,
Subsignal("n", Pins("CA40"), IOStandard("LVDS")),
Subsignal("p", Pins("CA39"), IOStandard("LVDS")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("TA1", { # FIXME: use real connector name, fake ones used since no access to documentation.
"io0" : "E40",
"io1" : "AU10",
"io2" : "AU11",
"io3" : "AJ1",
"io4" : "AK3",
"io5" : "AL1",
"io6" : "AM3",
"io7" : "AN1",
"io8" : "AP3",
"io9" : "AR1",
"io10" : "AT3",
"io11" : "AJ2",
"io12" : "AK4",
"io13" : "AL2",
"io14" : "AM4",
"io15" : "AN2",
"io16" : "AP4",
"io17" : "AR2",
"io18" : "AT4",
"io19" : "AL6",
"io20" : "AM8",
"io21" : "AN6",
"io22" : "AP8",
"io23" : "AR6",
"io24" : "AT8",
"io25" : "AU6",
"io26" : "AV8",
"io27" : "AL7",
"io28" : "AM9",
"io29" : "AN7",
"io30" : "AP9",
"io31" : "AR7",
"io32" : "AT9",
"io33" : "AU7",
"io34" : "AV9",
}),
("TA2", {}), # FIXME: TBD
("TA3", {}), # FIXME: TBD
("TA4", {}), # FIXME: TBD
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk300"
default_clk_period = 1e9/300e6
def __init__(self):
XilinxPlatform.__init__(self, "xcvu19p-fsva3824-2-e", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# For passively cooled boards, overheating is a significant risk if airflow isn't sufficient
self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]")
# Reduce programming time
self.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]")
# TA1 pins Internal Vref
self.add_platform_command("set_property INTERNAL_VREF 0.90 [get_iobanks 69]")
self.add_platform_command("set_property INTERNAL_VREF 0.90 [get_iobanks 70]")
self.add_platform_command("set_property INTERNAL_VREF 0.90 [get_iobanks 71]")
self.add_period_constraint(self.lookup_request("clk300", 0, loose=True), 1e9/300e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((1909, 2004), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xcvu19p-fsva3824-2-e"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xcvu19p-fsva3824-2-e', _io, _connectors,\n toolchain='vivado')\n", (1932, 2004), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((2050, 2068), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (2066, 2068), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((2115, 2157), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2141, 2157), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteSPI
#
# Copyright (c) 2020-2021 Antmicro <www.antmicro.com>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.misc import WaitTimer
from litespi.common import *
from litespi.clkgen import LiteSPIClkGen
from litex.soc.interconnect import stream
from litex.soc.interconnect.csr import *
from litex.build.io import SDROutput, SDRInput, SDRTristate
from litex.soc.integration.doc import AutoDoc
# LiteSPI PHY Core ---------------------------------------------------------------------------------
class LiteSPISDRPHYCore(Module, AutoCSR, AutoDoc):
"""LiteSPI PHY instantiator
The ``LiteSPIPHYCore`` class provides a generic PHY that can be connected to the ``LiteSPICore``.
It supports single/dual/quad/octal output reads from the flash chips.
The following diagram shows how each clock configuration option relates to outputs and input sampling in DDR mode:
.. wavedrom:: ../../doc/ddr-timing-diagram.json
Parameters
----------
pads : Object
SPI pads description.
flash : SpiNorFlashModule
SpiNorFlashModule configuration object.
device : str
Device type for use by the ``LiteSPIClkGen``.
default_divisor : int
Default frequency divisor for clkgen.
Attributes
----------
source : Endpoint(spi_phy2core_layout), out
Data stream.
sink : Endpoint(spi_core2phy_layout), in
Control stream.
cs : Signal(), in
Flash CS signal.
clk_divisor : CSRStorage
Register which holds a clock divisor value applied to clkgen.
"""
def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay):
self.source = source = stream.Endpoint(spi_phy2core_layout)
self.sink = sink = stream.Endpoint(spi_core2phy_layout)
self.cs = Signal()
self._spi_clk_divisor = spi_clk_divisor = Signal(8)
self._default_divisor = default_divisor
self.clk_divisor = clk_divisor = CSRStorage(8, reset=self._default_divisor)
# # #
# Resynchronize CSR Clk Divisor to LiteSPI Clk Domain.
self.submodules += ResyncReg(clk_divisor.storage, spi_clk_divisor, clock_domain)
# Determine SPI Bus width and DQs.
# if hasattr(pads, "mosi"):
# bus_width = 1
# else:
# bus_width = len(pads.dq)
# assert bus_width in [1, 2, 4, 8]
bus_width = 1
# bus_width = 4
# Check if number of pads matches configured mode.
# assert flash.check_bus_width(bus_width)
self.addr_bits = addr_bits = flash.addr_bits
self.cmd_width = cmd_width = flash.cmd_width
self.addr_width = addr_width = flash.addr_width
self.data_width = data_width = flash.bus_width
self.ddr = ddr = flash.ddr
self.command = command = flash.read_opcode.code
# Clock Generator.
self.submodules.clkgen = clkgen = LiteSPIClkGen(pads, device, with_ddr=ddr)
self.comb += [
clkgen.div.eq(spi_clk_divisor),
clkgen.sample_cnt.eq(1),
clkgen.update_cnt.eq(1),
]
# CS control.
cs_timer = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
cs_enable = Signal()
self.submodules += cs_timer
self.comb += cs_timer.wait.eq(self.cs)
self.comb += cs_enable.eq(cs_timer.done)
self.comb += pads.cs_n.eq(~cs_enable)
# I/Os.
data_bits = 32
cmd_bits = 8
# if hasattr(pads, "mosi"):
if bus_width == 1:
dq_o = Signal()
dq_i = Signal(2)
dq_oe = Signal() # Unused.
self.specials += SDROutput(
i = ~dq_oe,
o = pads.io0_oeb
)
self.comb += pads.io1_oeb.eq(1)
self.specials += SDROutput(
i = dq_o,
o = pads.io0_do
)
self.specials += SDRInput(
i = pads.io1_di,
o = dq_i[1]
)
self.comb += pads.io1_do.eq(0)
self.comb += pads.io2_do.eq(0)
self.comb += pads.io3_do.eq(0)
self.comb += pads.io2_oeb.eq(1)
self.comb += pads.io3_oeb.eq(1)
else:
dq_o = Signal(bus_width)
dq_i = Signal(bus_width)
dq_oe = Signal(bus_width)
for i in range(bus_width):
self.specials += SDROutput(
i=dq_oe[i],
o=getattr(pads,"io"+str(i)+"_oeb")
)
self.specials += SDROutput(
i=dq_o[i],
o=getattr(pads,"io"+str(i)+"_do")
)
self.specials += SDRInput(
i=getattr(pads,"io"+str(i)+"_di"),
o=dq_i[i]
)
# self.specials += SDRTristate(
# io = pads.dq_io[i],
# o = dq_o[i],
# oe = dq_oe[i],
# i = dq_i[i],
# )
# Data Shift Registers.
sr_cnt = Signal(8, reset_less=True)
sr_out_load = Signal()
sr_out_shift = Signal()
sr_out = Signal(len(sink.data), reset_less=True)
sr_in_shift = Signal()
sr_in = Signal(len(sink.data), reset_less=True)
# Data Out Generation/Load/Shift.
self.comb += [
dq_oe.eq(sink.mask),
Case(sink.width, {
1 : dq_o.eq(sr_out[-1:]),
2 : dq_o.eq(sr_out[-2:]),
4 : dq_o.eq(sr_out[-4:]),
8 : dq_o.eq(sr_out[-8:]),
})
]
self.sync += If(sr_out_load,
sr_out.eq(sink.data << (len(sink.data) - sink.len))
)
self.sync += If(sr_out_shift,
Case(sink.width, {
1 : sr_out.eq(Cat(Signal(1), sr_out)),
2 : sr_out.eq(Cat(Signal(2), sr_out)),
4 : sr_out.eq(Cat(Signal(4), sr_out)),
8 : sr_out.eq(Cat(Signal(8), sr_out)),
})
)
# Data In Shift.
self.sync += If(sr_in_shift,
Case(sink.width, {
1 : sr_in.eq(Cat(dq_i[1], sr_in)),
2 : sr_in.eq(Cat(dq_i[:2], sr_in)),
4 : sr_in.eq(Cat(dq_i[:4], sr_in)),
8 : sr_in.eq(Cat(dq_i[:8], sr_in)),
})
)
# FSM.
self.submodules.fsm = fsm = FSM(reset_state="WAIT-CMD-DATA")
fsm.act("WAIT-CMD-DATA",
# Wait for CS and a CMD from the Core.
If(cs_enable & sink.valid,
# Load Shift Register Count/Data Out.
NextValue(sr_cnt, sink.len - sink.width),
sr_out_load.eq(1),
# Start XFER.
NextState("XFER"),
),
)
fsm.act("XFER",
# Generate Clk.
self.clkgen.en.eq(1),
# Data In Shift.
If(clkgen.posedge_reg2, sr_in_shift.eq(1)),
# Data Out Shift.
If(clkgen.negedge, sr_out_shift.eq(1)),
# Shift Register Count Update/Check.
If(self.clkgen.negedge,
NextValue(sr_cnt, sr_cnt - sink.width),
# End XFer.
If(sr_cnt == 0,
NextState("XFER-END"),
),
),
)
fsm.act("XFER-END",
# Last data already captured in XFER when divisor > 0 so only capture for divisor == 0.
If((spi_clk_divisor > 0) | clkgen.posedge_reg2,
# Accept CMD.
sink.ready.eq(1),
# Capture last data (only for spi_clk_divisor == 0).
sr_in_shift.eq(spi_clk_divisor == 0),
# Send Status/Data to Core.
NextState("SEND-STATUS-DATA"),
)
)
self.comb += source.data.eq(sr_in)
fsm.act("SEND-STATUS-DATA",
# Send Data In to Core and return to WAIT when accepted.
source.valid.eq(1),
source.last.eq(1),
If(source.ready,
NextState("WAIT-CMD-DATA"),
)
)
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.build.io.SDROutput",
"litex.build.io.SDRInput"
] | [((1784, 1820), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_phy2core_layout'], {}), '(spi_phy2core_layout)\n', (1799, 1820), False, 'from litex.soc.interconnect import stream\n'), ((1862, 1898), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['spi_core2phy_layout'], {}), '(spi_core2phy_layout)\n', (1877, 1898), False, 'from litex.soc.interconnect import stream\n'), ((3068, 3109), 'litespi.clkgen.LiteSPIClkGen', 'LiteSPIClkGen', (['pads', 'device'], {'with_ddr': 'ddr'}), '(pads, device, with_ddr=ddr)\n', (3081, 3109), False, 'from litespi.clkgen import LiteSPIClkGen\n'), ((3304, 3327), 'migen.genlib.misc.WaitTimer', 'WaitTimer', (['(cs_delay + 1)'], {}), '(cs_delay + 1)\n', (3313, 3327), False, 'from migen.genlib.misc import WaitTimer\n'), ((3828, 3863), 'litex.build.io.SDROutput', 'SDROutput', ([], {'i': '(~dq_oe)', 'o': 'pads.io0_oeb'}), '(i=~dq_oe, o=pads.io0_oeb)\n', (3837, 3863), False, 'from litex.build.io import SDROutput, SDRInput, SDRTristate\n'), ((3987, 4019), 'litex.build.io.SDROutput', 'SDROutput', ([], {'i': 'dq_o', 'o': 'pads.io0_do'}), '(i=dq_o, o=pads.io0_do)\n', (3996, 4019), False, 'from litex.build.io import SDROutput, SDRInput, SDRTristate\n'), ((4099, 4133), 'litex.build.io.SDRInput', 'SDRInput', ([], {'i': 'pads.io1_di', 'o': 'dq_i[1]'}), '(i=pads.io1_di, o=dq_i[1])\n', (4107, 4133), False, 'from litex.build.io import SDROutput, SDRInput, SDRTristate\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2020-2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import argparse
from migen import *
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.soc.integration.common import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.integration.soc import *
from litex.soc.cores.bitbang import *
from litex.soc.cores.cpu import CPUS
from litedram.gen import LiteDRAMCoreControl
from litedram.modules import EM6GA16L
from litedram.core.controller import ControllerSettings
from litedram.phy.rpc.simphy import SimulationPHY
# Platform -----------------------------------------------------------------------------------------
_io = [
# clocks added later
("sys_rst", 0, Pins(1)),
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
# RPC pads
("rpcdram", 0,
Subsignal("clk_p", Pins(1)),
Subsignal("clk_n", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("dqs_p", Pins(1)),
Subsignal("dqs_n", Pins(1)),
Subsignal("stb", Pins(1)),
Subsignal("db", Pins(16)),
),
]
class Platform(SimPlatform):
def __init__(self):
print('_io', end=' = '); __import__('pprint').pprint(_io)
SimPlatform.__init__(self, "SIM", _io)
# DFI PHY model settings ---------------------------------------------------------------------------
sdram_module_nphases = {
"SDR": 1,
"DDR": 2,
"LPDDR": 2,
"DDR2": 2,
"DDR3": 4,
"RPC": 4,
"DDR4": 4,
}
def get_sdram_phy_settings(memtype, data_width, clk_freq):
nphases = sdram_module_nphases[memtype]
assert memtype == "DDR3"
# Settings from s7ddrphy
tck = 2/(2*nphases*clk_freq)
cmd_latency = 0
cl, cwl = get_cl_cw(memtype, tck)
cl_sys_latency = get_sys_latency(nphases, cl)
cwl = cwl + cmd_latency
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdcmdphase, rdphase = get_sys_phases(nphases, cl_sys_latency, cl)
wrcmdphase, wrphase = get_sys_phases(nphases, cwl_sys_latency, cwl)
read_latency = 2 + cl_sys_latency + 2 + 3
write_latency = cwl_sys_latency
sdram_phy_settings = {
"nphases": nphases,
"rdphase": rdphase,
"wrphase": wrphase,
"rdcmdphase": rdcmdphase,
"wrcmdphase": wrcmdphase,
"cl": cl,
"cwl": cwl,
"read_latency": read_latency,
"write_latency": write_latency,
}
return PhySettings(
phytype = "SDRAMPHYModel",
memtype = memtype,
databits = data_width,
dfi_databits = data_width if memtype == "SDR" else 2*data_width,
**sdram_phy_settings,
)
# Clocks -------------------------------------------------------------------------------------------
class Clocks(dict):
# FORMAT: {name: {"freq_hz": _, "phase_deg": _}, ...}
def names(self):
return list(self.keys())
def add_io(self, io):
for name in self.names():
print((name + "_clk", 0, Pins(1)))
io.append((name + "_clk", 0, Pins(1)))
def add_clockers(self, sim_config):
for name, desc in self.items():
sim_config.add_clocker(name + "_clk", **desc)
class _CRG(Module):
def __init__(self, platform, domains=None):
if domains is None:
domains = ["sys"]
# request() before clreating domains to avoid signal renaming problem
domains = {name: platform.request(name + "_clk") for name in domains}
self.clock_domains.cd_por = ClockDomain(reset_less=True)
for name in domains.keys():
setattr(self.clock_domains, "cd_" + name, ClockDomain(name=name))
int_rst = Signal(reset=1)
self.sync.por += int_rst.eq(0)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
for name, clk in domains.items():
cd = getattr(self, "cd_" + name)
self.comb += cd.clk.eq(clk)
self.comb += cd.rst.eq(int_rst)
# Simulation SoC -----------------------------------------------------------------------------------
class SimSoC(SoCCore):
def __init__(self, clocks, trace_reset=1, auto_precharge=False, with_refresh=True, **kwargs):
platform = Platform()
sys_clk_freq = clocks["sys"]["freq_hz"]
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "LiteX Simulation",
ident_version = True,
cpu_variant = "lite",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, clocks.names())
# Debugging --------------------------------------------------------------------------------
platform.add_debug(self, reset=trace_reset)
# RPC DRAM ---------------------------------------------------------------------------------
sdram_module = EM6GA16L(sys_clk_freq, "1:4")
pads = platform.request("rpcdram")
self.submodules.ddrphy = SimulationPHY(pads, sys_clk_freq=sys_clk_freq, generate_read_data=True)
self.add_csr("ddrphy")
controller_settings = ControllerSettings()
controller_settings.auto_precharge = auto_precharge
controller_settings.with_refresh = with_refresh
self.add_sdram("sdram",
phy = self.ddrphy,
module = sdram_module,
origin = self.mem_map["main_ram"],
size = kwargs.get("max_sdram_size", 0x40000000),
l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False,
controller_settings = controller_settings
)
# Reduce memtest size for simulation speedup
self.add_constant("MEMTEST_DATA_SIZE", 8*1024)
self.add_constant("MEMTEST_ADDR_SIZE", 8*1024)
self.add_constant("CONFIG_SIM_DISABLE_BIOS_PROMPT")
# self.add_constant("CONFIG_DISABLE_DELAYS")
self.submodules.ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
self.sync += If(self.ddrctrl.init_done.storage, Finish())
# Print info
def dump(obj):
print()
print(" " + obj.__class__.__name__)
print(" " + "-" * len(obj.__class__.__name__))
d = obj if isinstance(obj, dict) else vars(obj)
for var, val in d.items():
if var == "self":
continue
print(" {}: {}".format(var, val))
print("=" * 80)
dump(clocks)
dump(self.ddrphy.settings)
dump(sdram_module.geom_settings)
dump(sdram_module.timing_settings)
print()
print("=" * 80)
# Build --------------------------------------------------------------------------------------------
def generate_gtkw_savefile(builder, vns, trace_fst):
from litex.build.sim import gtkwave as gtkw
dumpfile = os.path.join(builder.gateware_dir, "sim.{}".format("fst" if trace_fst else "vcd"))
savefile = os.path.join(builder.gateware_dir, "sim.gtkw")
soc = builder.soc
rdphase = soc.sdram.controller.settings.phy.rdphase
wrphase = soc.sdram.controller.settings.phy.wrphase
with gtkw.GTKWSave(vns, savefile=savefile, dumpfile=dumpfile) as save:
save.clocks()
save.add(soc.bus.slaves["main_ram"], mappers=[gtkw.wishbone_sorter(), gtkw.wishbone_colorer()])
save.fsm_states(soc)
# all dfi signals
save.add(soc.ddrphy.dfi, mappers=[gtkw.dfi_sorter(), gtkw.dfi_in_phase_colorer()])
# each phase in separate group
with save.gtkw.group("dfi phaseX", closed=True):
for i, phase in enumerate(soc.ddrphy.dfi.phases):
save.add(phase, group_name="dfi p{}".format(i), mappers=[
gtkw.dfi_sorter(phases=False),
gtkw.dfi_in_phase_colorer(),
])
# only dfi command signals
save.add(soc.ddrphy.dfi, group_name="dfi commands", mappers=[
gtkw.regex_filter(gtkw.suffixes2re(["cas_n", "ras_n", "we_n"])),
gtkw.dfi_sorter(),
gtkw.dfi_per_phase_colorer(),
])
# only dfi data signals
save.add(soc.ddrphy.dfi, group_name="dfi wrdata", mappers=[
gtkw.regex_filter(["wrdata$", f"p{wrphase}.*wrdata_en$"]),
gtkw.dfi_sorter(),
gtkw.dfi_per_phase_colorer(),
])
save.add(soc.ddrphy.dfi, group_name="dfi wrdata_mask", mappers=[
gtkw.regex_filter(gtkw.suffixes2re(["wrdata_mask"])),
gtkw.dfi_sorter(),
gtkw.dfi_per_phase_colorer(),
])
save.add(soc.ddrphy.dfi, group_name="dfi rddata", mappers=[
gtkw.regex_filter(gtkw.suffixes2re(["rddata", f"p{rdphase}.*rddata_valid"])),
gtkw.dfi_sorter(),
gtkw.dfi_per_phase_colorer(),
])
# dram pads
save.group([s for s in vars(soc.ddrphy.pads).values() if isinstance(s, Signal)],
group_name = "pads",
mappers = [
gtkw.regex_filter(gtkw.suffixes2re(["dqs_n", "clk_n"]), negate=True),
gtkw.regex_sorter(["clk", "cs", "stb", "db", "dqs"]),
gtkw.regex_colorer({
"yellow": gtkw.suffixes2re(["cs"]),
"orange": gtkw.suffixes2re(["db", "dqs"]),
"red": gtkw.suffixes2re(["stb"]),
}),
],
)
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start", default=0, help="Cycle to start tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end tracing")
parser.add_argument("--trace-reset", default=1, help="Tracing state at start")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
parser.add_argument("--sys-clk-freq", default="100e6", help="Core clock frequency")
parser.add_argument("--auto-precharge", action="store_true", help="Use DRAM auto precharge")
parser.add_argument("--no-refresh", action="store_true", help="Disable DRAM refresher")
parser.add_argument("--gtkw-savefile", action="store_true", help="Generate GTKWSave savefile")
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(float(args.sys_clk_freq))
clocks = Clocks({
"sys": dict(freq_hz=sys_clk_freq),
"sys2x": dict(freq_hz=2*sys_clk_freq),
"sys4x": dict(freq_hz=4*sys_clk_freq),
"sys4x_90": dict(freq_hz=4*sys_clk_freq, phase_deg=90),
"sys4x_180": dict(freq_hz=4*sys_clk_freq, phase_deg=180),
"sys4x_90_ddr": dict(freq_hz=2*4*sys_clk_freq, phase_deg=2*90),
"sys4x_180_ddr": dict(freq_hz=2*4*sys_clk_freq, phase_deg=(2*180)%360),
})
clocks.add_io(_io)
sim_config = SimConfig()
clocks.add_clockers(sim_config)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu.endianness)
args.with_sdram = True
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(
clocks = clocks,
trace_reset = args.trace_reset,
auto_precharge = args.auto_precharge,
with_refresh = not args.no_refresh,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
l2_size = args.l2_size,
**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
opt_level = args.opt_level,
trace = args.trace,
trace_fst = args.trace_fst,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end))
if args.gtkw_savefile:
generate_gtkw_savefile(builder, vns, trace_fst=args.trace_fst)
builder.build(build=False, threads=args.threads, sim_config=sim_config,
opt_level = args.opt_level,
trace = args.trace,
trace_fst = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end)
)
if __name__ == "__main__":
main()
| [
"litex.build.sim.gtkwave.dfi_in_phase_colorer",
"litex.build.sim.gtkwave.wishbone_sorter",
"litex.build.sim.gtkwave.wishbone_colorer",
"litex.build.sim.gtkwave.dfi_sorter",
"litex.build.sim.gtkwave.dfi_per_phase_colorer",
"litex.build.sim.config.SimConfig",
"litex.build.sim.gtkwave.GTKWSave",
"litex.b... | [((10250, 10317), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Generic LiteX SoC Simulation"""'}), "(description='Generic LiteX SoC Simulation')\n", (10273, 10317), False, 'import argparse\n'), ((12433, 12444), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {}), '()\n', (12442, 12444), False, 'from litex.build.sim.config import SimConfig\n'), ((1623, 1661), 'litex.build.sim.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""SIM"""', '_io'], {}), "(self, 'SIM', _io)\n", (1643, 1661), False, 'from litex.build.sim import SimPlatform\n'), ((5528, 5557), 'litedram.modules.EM6GA16L', 'EM6GA16L', (['sys_clk_freq', '"""1:4"""'], {}), "(sys_clk_freq, '1:4')\n", (5536, 5557), False, 'from litedram.modules import EM6GA16L\n'), ((5634, 5705), 'litedram.phy.rpc.simphy.SimulationPHY', 'SimulationPHY', (['pads'], {'sys_clk_freq': 'sys_clk_freq', 'generate_read_data': '(True)'}), '(pads, sys_clk_freq=sys_clk_freq, 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import gtkwave as gtkw\n')] |
#!/usr/bin/env python3
import time
import numpy as np
from litex import RemoteClient
wb = RemoteClient()
wb.open()
# # #
x = np.linspace(0,2 * np.pi, 1000)
sine = (2**15 * np.sin(x)) + 2**15
sine = sine.astype('int').tolist()
print("artistic sine output...")
i = 0
while(1):
i = (i + 1) % 1000
wb.regs.dac_dacval.write(sine[i])
#time.sleep(0.001)
# # #
wb.close()
| [
"litex.RemoteClient"
] | [((93, 107), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (105, 107), False, 'from litex import RemoteClient\n'), ((130, 161), 'numpy.linspace', 'np.linspace', (['(0)', '(2 * np.pi)', '(1000)'], {}), '(0, 2 * np.pi, 1000)\n', (141, 161), True, 'import numpy as np\n'), ((177, 186), 'numpy.sin', 'np.sin', (['x'], {}), '(x)\n', (183, 186), True, 'import numpy as np\n')] |
#
# This file is part of LiteX-Boards.
# FPGA Board Info : https://shop.trenz-electronic.de/en/TE0725-03-35-2C-FPGA-Module-with-Xilinx-Artix-7-XC7A35T-2CSG324C-2-x-50-Pin-with-2.54-mm-pitch
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("P17"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("T8"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M16"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("L18")),
Subsignal("rx", Pins("M18")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("E9")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("E9")),
Subsignal("dq", Pins("K17 K18 L14 M14")),
IOStandard("LVCMOS33")
),
# HyperRAM
("hyperram", 0,
Subsignal("dq", Pins("E17 B17 F18 F16 G17 D18 B18 A16"), IOStandard("SSTL18_II")),
Subsignal("rwds", Pins("E18"), IOStandard("SSTL18_II")),
Subsignal("cs_n", Pins("D17"), IOStandard("SSTL18_II")),
Subsignal("rst_n", Pins("J17"), IOStandard("SSTL18_II")),
Subsignal("clk_p", Pins("A13"), IOStandard("DIFF_SSTL18_II")),
Subsignal("clk_n", Pins("A14"), IOStandard("DIFF_SSTL18_II")),
Misc("SLEW=FAST"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("j1", "C6 C5 B7 B6 A6 A5 D8 C7",
"E6 E5 E7 D7 C4 B4 A4 A3",
"B1 A1 B3 B2 D5 D4 E3 D3",
"F4 F3 E2 D2 H2 G2 C2 C1",
"H1 G1 F1 E1 G6 F6 J3 J2",
"K2 K1"),
("j2", "L1 M1 N2 N1 M3 M2 U1 V1",
"U4 U3 U2 V2 V5 V4 R3 T3",
"T5 T4 N5 P5 P4 P3 P2 R2",
"M4 N4 R1 T1 M6 N6 R6 R5",
"V7 V6 U9 V9 U7 U6 R7 T6",
"R8"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35tcsg324-2", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16"
" -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property CFGBVS VCCO [current_design]")
self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a35t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
# "set_property SEVERITY {{Warning}} [get_drc_checks UCIO-1]"]
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2645, 2735), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35tcsg324-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a35tcsg324-2', _io, _connectors,\n toolchain='vivado')\n", (2668, 2735), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((3255, 3313), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a35t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a35t.bit')\n", (3262, 3313), False, 'from litex.build.openocd import OpenOCD\n'), ((3360, 3402), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3386, 3402), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys", "nextpnr-ice40"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
# Disable pylint's E1101, which breaks completely on migen
#pylint:disable=E1101
#from migen import *
from migen import Module, Signal, Instance, ClockDomain, If
from migen.fhdl.specials import TSTriple
from migen.fhdl.decorators import ClockDomainsRenamer
from litex.build.lattice.platform import LatticePlatform
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.cpu import CPUNone
from litex.soc.integration.builder import Builder
from litex.soc.interconnect import wishbone
from litex.soc.cores import spi_flash
from valentyusb.usbcore import io as usbio
from valentyusb.usbcore.cpu import epmem, unififo, epfifo, dummyusb, eptri
from valentyusb.usbcore.endpoint import EndpointType
import litex.soc.doc as lxsocdoc
import spibone
import argparse
import os
import subprocess
from rtl.version import Version
from rtl.romgen import RandomFirmwareROM, FirmwareROMHex
from rtl.messible import Messible
class BaseSoC(SoCCore, AutoDoc):
"""Fomu Bootloader and Base SoC
Fomu is an FPGA that fits in your USB port. This reference manual
documents the basic SoC that runs the bootloader, and that can be
reused to run your own RISC-V programs.
This reference manual only describes a particular version of the SoC.
The register sets described here are guaranteed to be available
with a given ``major version``, but are not guaranteed to be available on
any other version. Naturally, you are free to create your own SoC
that does not provide these hardware blocks. To see what the version of the
bitstream you're running, check the ``VERSION`` registers.
"""
csr_map = {
"ctrl": 0, # provided by default (optional)
"crg": 1, # user
"uart_phy": 2, # provided by default (optional)
"uart": 3, # provided by default (optional)
"identifier_mem": 4, # provided by default (optional)
"timer0": 5, # provided by default (optional)
"cpu_or_bridge": 8,
"usb": 9,
"picorvspi": 10,
"touch": 11,
"reboot": 12,
"rgb": 13,
"version": 14,
"lxspi": 15,
"messible": 16,
"button": 17,
}
SoCCore.mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0xa0000000)
"spiflash": 0x20000000, # (default shadow @0xa0000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"csr": 0xe0000000, # (default shadow @0xe0000000)
"vexriscv_debug": 0xf00f0000,
}
interrupt_map = {
"timer0": 2,
"usb": 3,
}
interrupt_map.update(SoCCore.interrupt_map)
def __init__(self, platform, boot_source="rand",
debug=None, bios_file=None,
use_dsp=False, placer="heap", output_dir="build",
pnr_seed=0,
**kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
if hasattr(platform, "get_integrated_sram_size"):
self.integrated_sram_size = platform.get_integrated_sram_size()
self.output_dir = output_dir
clk_freq = int(12e6)
platform.add_crg(self)
SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=self.integrated_sram_size, with_uart=False, csr_data_width=32, **kwargs)
usb_debug = False
if debug is not None:
if debug == "uart":
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
elif debug == "usb":
usb_debug = True
elif debug == "spi":
import spibone
# Add SPI Wishbone bridge
debug_device = [
("spidebug", 0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)
]
platform.add_extension(debug_device)
spi_pads = platform.request("spidebug")
self.submodules.spibone = ClockDomainsRenamer("usb_12")(spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
platform.add_cpu_variant(self, debug=True)
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
platform.add_cpu_variant(self)
if hasattr(platform, "add_sram"):
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = platform.add_sram(self)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# Add a Messible for device->host communications
self.submodules.messible = Messible()
if boot_source == "rand":
kwargs['cpu_reset_address'] = 0
bios_size = 0x2000
self.submodules.random_rom = RandomFirmwareROM(bios_size)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.random_rom.bus, bios_size)
elif boot_source == "bios":
kwargs['cpu_reset_address'] = 0
if bios_file is None:
self.integrated_rom_size = bios_size = 0x4000
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
bios_size = 0x4000
self.submodules.firmware_rom = FirmwareROMHex(bios_size, bios_file)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.firmware_rom.bus, bios_size)
elif boot_source == "spi":
kwargs['cpu_reset_address'] = 0
self.integrated_rom_size = bios_size = 0x2000
gateware_size = 0x1a000
self.flash_boot_address = self.mem_map["spiflash"] + gateware_size
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
raise ValueError("unrecognized boot_source: {}".format(boot_source))
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=platform.spi_dummy, endianness="little")
self.lxspi.add_clk_primitive(platform.device)
self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=platform.spi_size)
# Add USB pads, as well as the appropriate USB controller. If no CPU is
# present, use the DummyUsb controller.
usb_pads = platform.request_usb()
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=usb_debug)
else:
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_debug)
if usb_debug:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# For the EVT board, ensure the pulldown pin is tristated as an input
if hasattr(usb_pads, "pulldown"):
pulldown = TSTriple()
self.specials += pulldown.get_tristate(usb_pads.pulldown)
self.comb += pulldown.oe.eq(0)
# Add GPIO pads for the touch buttons
if hasattr(platform, "add_touch"):
platform.add_touch(self)
if hasattr(platform, "add_button"):
platform.add_button(self)
bootloader_size = 512*1024
self.add_constant("FLASH_MAX_ADDR", value=platform.spi_size - bootloader_size)
# Allow the user to reboot the FPGA. Additionally, connect the CPU
# RESET line to a register that can be modified, to allow for
# us to debug programs even during reset.
platform.add_reboot(self)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.cpu_params.update(
i_externalResetVector=self.reboot.addr.storage,
)
platform.add_rgb(self)
self.submodules.version = Version(platform.revision, platform.hw_platform, self, pnr_seed, models=[
("0x45", "E", "Fomu EVT"),
("0x44", "D", "Fomu DVT"),
("0x50", "P", "Fomu PVT (production)"),
("0x48", "H", "Fomu Hacker"),
("0x11", "1", "OrangeCrab r0.1"),
("0x12", "2", "OrangeCrab r0.2"),
("0x63", "c", "OrangeCart"),
("0x3f", "?", "Unknown model"),
])
if hasattr(platform, "build_templates"):
platform.build_templates(use_dsp, pnr_seed, placer)
git_version_subprocess = subprocess.Popen("git describe --tags", shell=True, stdout=subprocess.PIPE)
git_version = git_version_subprocess.stdout.read().decode("utf-8").strip()
for (name,value) in platform.get_config(git_version):
self.add_constant("CONFIG_" + name, value)
def main():
parser = argparse.ArgumentParser(
description="Build Fomu Main Gateware")
parser.add_argument(
"--boot-source", choices=["spi", "rand", "bios"], default="bios",
help="where to have the CPU obtain its executable code from"
)
parser.add_argument(
"--document-only", default=False, action="store_true",
help="Don't build gateware or software, only build documentation"
)
parser.add_argument(
"--platform", choices=["fomu", "orangecrab", "orangecart"], required=True,
help="build foboot for a particular hardware"
)
parser.add_argument(
"--bios", help="use specified file as a BIOS, rather than building one"
)
parser.add_argument(
"--with-debug", help="enable debug support", choices=["usb", "uart", "spi", None]
)
parser.add_argument(
"--with-dsp", help="use dsp inference in yosys (not all yosys builds have -dsp)", action="store_true"
)
parser.add_argument(
"--no-cpu", help="disable cpu generation for debugging purposes", action="store_true"
)
parser.add_argument(
"--placer", choices=["sa", "heap"], default="heap", help="which placer to use in nextpnr"
)
parser.add_argument(
"--seed", default=0, help="seed to use in nextpnr"
)
parser.add_argument(
"--export-random-rom-file", help="Generate a random ROM file and save it to a file"
)
parser.add_argument(
"--skip-gateware", help="Skip generating gateware", default=False
)
args, _ = parser.parse_known_args()
# Select platform based arguments
if args.platform == "orangecrab":
from rtl.platform.orangecrab import Platform, add_platform_args
elif args.platform == "orangecart":
from rtl.platform.orangecart import Platform, add_platform_args
elif args.platform == "fomu":
from rtl.platform.fomu import Platform, add_platform_args
# Add any platform independent args
add_platform_args(parser)
args = parser.parse_args()
# load our platform file
if args.platform == "orangecrab":
platform = Platform(revision=args.revision, device=args.device)
elif args.platform == "orangecart":
platform = Platform(device=args.device)
elif args.platform == "fomu":
platform = Platform(revision=args.revision)
output_dir = 'build'
#if args.export_random_rom_file is not None:
rom_rand = os.path.join(output_dir, "gateware", "rand_rom.hex")
os.system(f"ecpbram --generate {rom_rand} --seed {0} --width {32} --depth {int(0x4000/4)}")
compile_software = False
if (args.boot_source == "bios" or args.boot_source == "spi") and args.bios is None:
compile_software = True
compile_gateware = True
if args.skip_gateware:
compile_gateware = False
cpu_type = "vexriscv"
cpu_variant = "minimal"
if args.with_debug:
cpu_variant = cpu_variant + "+debug"
if args.no_cpu:
cpu_type = None
cpu_variant = None
if args.document_only:
compile_gateware = False
compile_software = False
os.environ["LITEX"] = "1" # Give our Makefile something to look for
soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant,
debug=args.with_debug, boot_source=args.boot_source,
bios_file=args.bios,
use_dsp=args.with_dsp, placer=args.placer,
pnr_seed=int(args.seed),
output_dir=output_dir)
builder = Builder(soc, output_dir=output_dir, csr_csv="build/csr.csv", csr_svd="build/soc.svd",
compile_software=compile_software, compile_gateware=compile_gateware)
if compile_software:
builder.software_packages = [
("bios", os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "sw")))
]
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc, "build/documentation/", project_name="Fomu Bootloader", author="<NAME>")
if not args.document_only:
platform.finalise(output_dir)
if __name__ == "__main__":
main()
def export_random_rom_file(filename):
size = 0x2000
def xorshift32(x):
x = x ^ (x << 13) & 0xffffffff
x = x ^ (x >> 17) & 0xffffffff
x = x ^ (x << 5) & 0xffffffff
return x & 0xffffffff
def get_rand(x):
out = 0
for i in range(32):
x = xorshift32(x)
if (x & 1) == 1:
out = out | (1 << i)
return out & 0xffffffff
seed = 1
with open(filename, "w", newline="\n") as output:
for _ in range(int(size / 4)):
seed = get_rand(seed)
print("{:08x}".format(seed), file=output)
return 0
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"litex.soc.integration.builder.Builder",
"litex.build.generic_platform.Pins",
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.soc.cores.spi_flash.SpiFlashDualQuad",
"litex.soc.interconnect.wishbone.SRAM"
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"('dbg:3')\n", (4858, 4867), False, 'from litex.build.generic_platform import Pins, Subsignal\n')] |
from itertools import product
from sys import stdout
import json
import ctypes
from litex.tools.litex_client import RemoteClient
from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
analyzer = LiteScopeAnalyzerDriver(wb.regs, "analyzer", debug=True, config_csv="test/analyzer.csv")
analyzer.configure_subsampler(1) ## increase this to "skip" cycles, e.g. subsample
analyzer.configure_group(0)
# trigger conditions will depend upon each other in sequence
analyzer.add_rising_edge_trigger("puf_reset")
analyzer.run(offset=8, length=512) ### CHANGE THIS TO MATCH DEPTH offset=32 by default
for i, j in product(range(2), repeat=2):
wb.regs.teropuf_reset.write(1) # enable reset
wb.regs.teropuf_cell0_select.write(i)
wb.regs.teropuf_cell1_select.write(j)
wb.regs.teropuf_reset.write(0) # disable reset
print(f'Comparator from set {i} and {j}:')
for _ in range(10):
print(wb.regs.teropuf_bit_value.read())
print(ctypes.c_int32(wb.regs.teropuf_bit_value.read()).value)
analyzer.wait_done()
analyzer.upload()
analyzer.save("test/dump.vcd")
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((207, 243), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (219, 243), False, 'from litex.tools.litex_client import RemoteClient\n'), ((266, 359), 'litescope.software.driver.analyzer.LiteScopeAnalyzerDriver', 'LiteScopeAnalyzerDriver', (['wb.regs', '"""analyzer"""'], {'debug': '(True)', 'config_csv': '"""test/analyzer.csv"""'}), "(wb.regs, 'analyzer', debug=True, config_csv=\n 'test/analyzer.csv')\n", (289, 359), False, 'from litescope.software.driver.analyzer import LiteScopeAnalyzerDriver\n')] |
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