code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------... | [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((3780, 3894), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-UV4LQ144C6/I5"""', '_io', '_connectors'], {'toolchain': 'toolchain', 'devicename': '"""GW1N-4"""'}), "(self, 'GW1N-UV4LQ144C6/I5', _io, _connectors,\n toolchain=toolchain, devicename='GW1N-4')\n", (3802,... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2017-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ---------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((18029, 18124), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xcku040-ffva1156-2-e"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xcku040-ffva1156-2-e', _io, _connectors,\n toolchain='vivado')\n", (18052, 18124), False, 'from litex.build.xilinx import ... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Board diagram/pinout:
# https://user-images.githubusercontent.com/1450143/133655492-532d5e9a-0635-4889-85c9-68683d06cae0.png
# http://dl.sipeed.com/TANG/Nano/HDK/Tang-NANO-2704(Schematic).pdf
from ... | [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((1481, 1592), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-LV1QN48C6/I5"""', '_io', '_connectors'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1N-1"""'}), "(self, 'GW1N-LV1QN48C6/I5', _io, _connectors,\n toolchain='gowin', devicename='GW1N-1')\n", (1503, 1... |
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 msloniewski <<EMAIL>>
# Copyright (c) 2019 vytautasb <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import subprocess
import sys
import math
from shutil import which
from migen.fhdl.structure import _Fragmen... | [
"litex.build.tools.get_litex_git_revision",
"litex.build.generic_platform.Pins",
"litex.build.tools.write_to_file"
] | [((6393, 6459), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(True)'}), '(script_file, script_contents, force_unix=True)\n', (6412, 6459), False, 'from litex.build import tools\n'), ((6627, 6647), 'shutil.which', 'which', (['"""quartus_map"""'], {}), "('... |
#!/usr/bin/env python3
import time
from statistics import mean
from litex import RemoteClient
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
# # #
# Read frequency meter
fmeter_values = []
print("Reading frequency...")
for i in range(100):
fmeter_value = wb.regs.fmeter_value.read()
print(fmeter_value)... | [
"litex.RemoteClient"
] | [((102, 138), 'litex.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (114, 138), False, 'from litex import RemoteClient\n'), ((364, 379), 'time.sleep', 'time.sleep', (['(1.0)'], {}), '(1.0)\n', (374, 379), False, 'import time\n'), ((398, 417), 'statistics.mean', 'me... |
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from bft import Bft
from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface
from litex.soc.interconnect.stream import (ClockDomainCrossing, Converter,
Endpoint)
from migen import *
from pld_ax... | [
"litex.soc.interconnect.axi.AXILiteInterface"
] | [((5719, 5794), 'litex.soc.interconnect.axi.AXILiteInterface', 'AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(5)', 'clock_domain': 'clock_domain'}), '(data_width=32, address_width=5, clock_domain=clock_domain)\n', (5735, 5794), False, 'from litex.soc.interconnect.axi import AXILiteInterface, AXIStre... |
from litex.tools.litex_client import RemoteClient
wb = RemoteClient("192.168.1.50", 1234, csr_data_width=8)
wb.open()
regs = wb.regs
# # #
print("temperature: %f°C" %(regs.xadc_temperature.read()*503.975/4096 - 273.15))
print("vccint: %fV" %(regs.xadc_vccint.read()/4096*3))
print("vccaux: %fV" %(regs.xadc_vccaux.rea... | [
"litex.tools.litex_client.RemoteClient"
] | [((56, 108), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', (['"""192.168.1.50"""', '(1234)'], {'csr_data_width': '(8)'}), "('192.168.1.50', 1234, csr_data_width=8)\n", (68, 108), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import csv
import logging
import argparse
from operator import and_
from functools import reduce
from itertools import zip_longest
from migen import *
from migen.genlib.misc import WaitTimer
from litex.build.sim.config import S... | [
"litex.tools.litex_sim.SimSoC.__init__",
"litex.build.sim.config.SimConfig"
] | [((7932, 8004), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteDRAM Benchmark SoC Simulation"""'}), "(description='LiteDRAM Benchmark SoC Simulation')\n", (7955, 8004), False, 'import argparse\n'), ((9954, 9973), 'logging.getLogger', 'logging.getLogger', ([], {}), '()\n', (9971, 9973... |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
rom_base = 0x00000000
dump_size = 0x8000
words_per_packet = 128
wb = RemoteClient()
wb.open()
# # #
print("dumping cpu rom to dump.bin...")
dump = []
for n in range(dump_size//(words_per_packet*4)):
dump += wb.read(rom_base + n*words_per_p... | [
"litex.tools.litex_client.RemoteClient"
] | [((144, 158), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (156, 158), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020-21 gatecat <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSy... | [
"litex.soc.interconnect.wishbone.SRAM",
"litex.build.lattice.oxide.oxide_args",
"litex.soc.cores.ram.NXLRAM",
"litex.soc.cores.freqmeter.FreqMeter",
"litex.soc.cores.gpio.GPIOIn",
"litex.build.lattice.oxide.oxide_argdict"
] | [((7015, 7089), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Crosslink-NX VIP Board"""'}), "(description='LiteX SoC on Crosslink-NX VIP Board')\n", (7038, 7089), False, 'import argparse\n'), ((7766, 7784), 'litex.build.lattice.oxide.oxide_args', 'oxide_args', (['parser'], ... |
#
# This file is part of LiteX.
#
# Copyright (c) 2016-2017 <NAME> <<EMAIL>>
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
IBM's 8b/10b Encoding
This scheme is used by a large number of protocols including Display Port, PCI
Express, Gigabit Ethernet, SATA and USB 3.
The encod... | [
"litex.soc.interconnect.stream.PipelinedActor.__init__",
"litex.soc.interconnect.stream.Endpoint"
] | [((10573, 10624), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('d', nwords * 8), ('k', nwords)]"], {}), "([('d', nwords * 8), ('k', nwords)])\n", (10588, 10624), False, 'from litex.soc.interconnect import stream\n'), ((10654, 10694), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.cs... | [
"litex.build.sim.SimPlatform.__init__",
"litex.build.generic_platform.Pins"
] | [((908, 928), 'litedram.phy.utils.Serializer', 'Serializer', ([], {}), '(**kwargs)\n', (918, 928), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((1174, 1196), 'litedram.phy.utils.Deserializer', 'Deserializer', ([], {}), '(**kwargs)\n', (1186, 1196), False, 'from litedram.phy.utils import S... |
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((3739, 3789), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE22F17C6"""', '_io'], {}), "(self, 'EP4CE22F17C6', _io)\n", (3762, 3789), False, 'from litex.build.altera import AlteraPlatform\n'), ((3839, 3851), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ---------------------------------------------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((2536, 2586), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE15F23C8"""', '_io'], {}), "(self, 'EP4CE15F23C8', _io)\n", (2559, 2586), False, 'from litex.build.altera import AlteraPlatform\n'), ((2636, 2648), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs -------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((4685, 4759), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', 'device', 'io', 'connectors'], {'toolchain': 'toolchain'}), '(self, device, io, connectors, toolchain=toolchain)\n', (4708, 4759), False, 'from litex.build.altera import AlteraPlatform\n'), ((5037, 5049), 'litex.build.alt... |
from migen import Module, Signal, Instance, ClockDomain, If
from litex.build.lattice.platform import LatticePlatform
from litex.soc.cores import up5kspram, spi_flash
from litex_boards.targets.fomu import _CRG
import litex.soc.doc as lxsocdoc
import spibone
from ..romgen import RandomFirmwareROM, FirmwareROM
from .... | [
"litex.soc.cores.up5kspram.Up5kSPRAM",
"litex.build.lattice.platform.LatticePlatform.__init__"
] | [((3049, 3059), 'litex_boards.targets.fomu._CRG', '_CRG', (['self'], {}), '(self)\n', (3053, 3059), False, 'from litex_boards.targets.fomu import _CRG\n'), ((3371, 3407), 'litex.soc.cores.up5kspram.Up5kSPRAM', 'up5kspram.Up5kSPRAM', ([], {'size': 'spram_size'}), '(size=spram_size)\n', (3390, 3407), False, 'from litex.s... |
# Support for the Digilent Atlys (http://digilentinc.com/atlys/) - The board used for HDMI2USB prototyping.
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, iMPACT
# There appear to be 4 x LTC2481C on the U1-SCL / U1-SDA lines connected to the Cypress
class DynamicLVCMOS(obje... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.iMPACT",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((37550, 37618), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx45-csg324-3"""', '_io', '_connectors'], {}), "(self, 'xc6slx45-csg324-3', _io, _connectors)\n", (37573, 37618), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38798, 38840), 'litex.build.... |
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.openocd import OpenOCD
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("H5"), IOSt... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.VivadoProgrammer"
] | [((4558, 4633), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-csg324-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a35t-csg324-1', _io, toolchain=toolchain)\n", (4581, 4633), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'),... |
#!/usr/bin/env python3
import time
import random
from operator import or_
from functools import reduce
from utils import memfill, memcheck
################################################################################
class DRAMAddressConverter:
def __init__(self, colbits=10, rowbits=14, bankbits=3,
... | [
"litex.RemoteClient"
] | [((7959, 7978), 'random.Random', 'random.Random', (['seed'], {}), '(seed)\n', (7972, 7978), False, 'import random\n'), ((8102, 8127), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (8125, 8127), False, 'import argparse\n'), ((10386, 10400), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n'... |
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("sys_clk", 0, Pi... | [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader"
] | [((1044, 1147), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-LV1QN48C6/I5"""', '_io', '[]'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1N-1"""'}), "(self, 'GW1N-LV1QN48C6/I5', _io, [], toolchain=\n 'gowin', devicename='GW1N-1')\n", (1066, 1147), False, 'fro... |
#!/usr/bin/env python3
"""
This script is used to test the minimal DDR litex design.
It performs the calibration step by sending commands and data through an UART bridge
to the DDR controller.
It makes use of the litex RemoteClient.
This script is able to calculate which are the correct bitslip and delay values of t... | [
"litex.RemoteClient"
] | [((7584, 7660), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Script to test correct DDR behaviour."""'}), "(description='Script to test correct DDR behaviour.')\n", (7607, 7660), False, 'import argparse\n'), ((7896, 7921), 'litex.RemoteClient', 'RemoteClient', ([], {'debug': '(False)'}... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream:
# ./siglent_ds1104xe.py --with-etherbone --uart-nam... | [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((7595, 7657), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on SDS1104X-E"""'}), "(description='LiteX SoC on SDS1104X-E')\n", (7618, 7657), False, 'import argparse\n'), ((8533, 8558), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(par... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Direct Memory Access (DMA) reader and writer modules."""
from migen import *
from litex.gen.common import reverse_bytes
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import ... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.gen.common.reverse_bytes"
] | [((1300, 1358), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', bus.adr_width, ('last', 1))]"], {}), "([('address', bus.adr_width, ('last', 1))])\n", (1315, 1358), False, 'from litex.soc.interconnect import stream\n'), ((1390, 1433), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoin... |
#!/usr/bin/env python3
"""
Copyright (c) 2019-2020 Antmicro <www.antmicro.com>
Zephyr DTS & config overlay generator for LiteX SoC.
This script parses LiteX 'csr.csv' file and generates DTS and config
files overlay for Zephyr.
"""
import argparse
from litex.configuration import Configuration
configuration = None
... | [
"litex.configuration.Configuration"
] | [((4444, 4469), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (4467, 4469), False, 'import argparse\n'), ((4954, 4983), 'litex.configuration.Configuration', 'Configuration', (['args.conf_file'], {}), '(args.conf_file)\n', (4967, 4983), False, 'from litex.configuration import Configuration\n')] |
# This file is Copyright (c) 2021 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk24", 0, Pins("C1"), IOStandard("LVCMOS18"... | [
"litex.build.lattice.LatticePlatform.__init__"
] | [((3691, 3795), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8MG285C"""', '_io', '_connectors'], {'toolchain': '"""trellis"""'}), "(self, 'LFE5U-25F-8MG285C', _io, _connectors,\n toolchain='trellis', **kwargs)\n", (3715, 3795), False, 'from litex.build.lattice i... |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 Dolu1990 <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.build.io import SDRTristate
# USB OHCI -------... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.build.io.SDRTristate",
"litex.get_data_mod"
] | [((662, 695), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (680, 695), False, 'from litex.soc.interconnect import wishbone\n'), ((729, 774), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': 'dma_data_width'}),... |
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
from migen import *
from migen.genlib.cdc import MultiReg
from liteeth.common import convert_ip, eth_udp_user_description
from litedram.frontend.dma import LiteDRAMDMAWriter
from litex.gen.common import reverse_bytes
from litex.soc.interco... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((564, 575), 'utils.FastLatch', 'FastLatch', ([], {}), '()\n', (573, 575), False, 'from utils import FastLatch\n'), ((1462, 1510), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('address', 32)]"], {}), "([('data', 32), ('address', 32)])\n", (1477, 1510), False, 'from litex.soc.intercon... |
#!/usr/bin/env python3
import argparse
from migen import *
from litex.boards.platforms import arty
from litex.soc.cores import *
from litex.soc.integration import soc_core
from litex.soc.interconnect.csr import *
from litex.soc.cores import gpio
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.inte... | [
"litex.build.generic_platform.Misc",
"litex.build.generic_platform.IOStandard",
"litex.soc.integration.soc_core.SoCCore",
"litex.boards.platforms.arty.Platform",
"litex.build.generic_platform.Pins",
"litex.soc.cores.gpio.GPIOOut"
] | [((2883, 2898), 'litex.boards.platforms.arty.Platform', 'arty.Platform', ([], {}), '()\n', (2896, 2898), False, 'from litex.boards.platforms import arty\n'), ((2962, 3087), 'litex.soc.integration.soc_core.SoCCore', 'soc_core.SoCCore', (['platform', 'sys_clk_freq'], {'cpu_variant': '"""lite+debug"""', 'integrated_rom_si... |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys", "nextpnr-ice40"]
# Import lxbuildenv ... | [
"litex.soc.integration.builder.Builder",
"litex.build.generic_platform.Pins",
"litex.soc.cores.up5kspram.Up5kSPRAM",
"litex.soc.integration.soc_core.SoCCore.__init__",
"litex.build.lattice.platform.LatticePlatform.__init__",
"litex.soc.cores.spi_flash.SpiFlashDualQuad",
"litex.soc.interconnect.wishbone.... | [((14327, 14390), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Build Fomu Main Gateware"""'}), "(description='Build Fomu Main Gateware')\n", (14350, 14390), False, 'import argparse\n'), ((17701, 17835), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'output_dir': 'outpu... |
#!/usr/bin/env python3
import argparse
from migen import *
from litex.gen.fhdl.utils import get_signals
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict
... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.build.sim.config.SimConfig",
"litex.gen.fhdl.utils.get_signals",
"litex.soc.interconnect.avalon.AvalonMM2Wishbone",
"litex.build.sim.verilator.verilator_build_args",
"litex.build.sim.SimPlatform.__init__",
"litex.build.sim.verilator.verilator_build_arg... | [((4725, 4788), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteEth Bench Simulation"""'}), "(description='LiteEth Bench Simulation')\n", (4748, 4788), False, 'import argparse\n'), ((5072, 5100), 'litex.build.sim.verilator.verilator_build_args', 'verilator_build_args', (['parser'], {}... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.emif import EMIF
class EMIFPads:
def __init__(self):
self.cs_n = Signal(reset=1)
... | [
"litex.soc.interconnect.wishbone.SRAM",
"litex.soc.cores.emif.EMIF"
] | [((2785, 2795), 'litex.soc.cores.emif.EMIF', 'EMIF', (['pads'], {}), '(pads)\n', (2789, 2795), False, 'from litex.soc.cores.emif import EMIF\n'), ((2858, 2889), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(16)'], {'bus': 'emif.bus'}), '(16, bus=emif.bus)\n', (2871, 2889), False, 'from litex.soc.intercon... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ---------------------... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((10824, 10917), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k160t-fbg676-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7k160t-fbg676-1', _io, _connectors,\n toolchain=toolchain)\n", (10847, 10917), False, 'from litex.build.xilinx import XilinxPl... |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import unittest
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.stream import EndpointDescription, Endpoint
from litex.soc.interconnect.csr import *
def data_stream_description(dw):
payload_layout = [(... | [
"litex.soc.interconnect.stream.EndpointDescription",
"litex.soc.interconnect.wishbone.Interface"
] | [((344, 379), 'litex.soc.interconnect.stream.EndpointDescription', 'EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (363, 379), False, 'from litex.soc.interconnect.stream import EndpointDescription, Endpoint\n'), ((11120, 11135), 'unittest.main', 'unittest.main', ([], {}), '()\n', (11133, 11135), ... |
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.csr import *
from migen import *
class StartWriter(Module, AutoCSR):
def __init__(self, signal):
self.signal = signal
self._start = CSRStorage(1, reset=0)
self.comb += signal.eq(self._start.storage)
d... | [
"litex.build.generic_platform.Pins"
] | [((426, 433), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (430, 433), False, 'from litex.build.generic_platform import Pins, Subsignal\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import copy
import random
import unittest
from collections import namedtuple
from migen import *
from litex.soc.interconnect import stream
from litedram.common import *
from litedram.phy imp... | [
"litex.gen.sim.run_simulation"
] | [((3708, 3856), 'litedram.phy.dfi.Interface', 'dfi.Interface', ([], {'addressbits': 'abits', 'bankbits': 'babits', 'nranks': 'settings.phy.nranks', 'databits': 'settings.phy.dfi_databits', 'nphases': 'settings.phy.nphases'}), '(addressbits=abits, bankbits=babits, nranks=settings.phy.\n nranks, databits=settings.phy.... |
from migen import *
from litex.soc.interconnect.stream import SyncFIFO
class FIFOSyncMacro(Module, Record):
"""FIFOSyncMacro
Provides an equivalent of Xilinx' FIFO_SYNC_MACRO which is a unimacro dedicated for 7 series
FPGAs and Zynq-7000 SoC.
Detailed informations can be found in official documentat... | [
"litex.soc.interconnect.stream.SyncFIFO"
] | [((3611, 3655), 'litex.soc.interconnect.stream.SyncFIFO', 'SyncFIFO', (["[('data', data_width)]", 'fifo_depth'], {}), "([('data', data_width)], fifo_depth)\n", (3619, 3655), False, 'from litex.soc.interconnect.stream import SyncFIFO\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Board diagram/pinout:
# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-specifications.jpg
# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-GW1NSR-4C-FPGA-board-... | [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((2907, 3025), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1NSR-LV4CQN48PC7/I6"""', '_io', '_connectors'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1NSR-4C"""'}), "(self, 'GW1NSR-LV4CQN48PC7/I6', _io, _connectors,\n toolchain='gowin', devicename='GW1NSR-4C'... |
#!/usr/bin/env python3
import argparse
from migen import *
from litex.build.generic_platform import IOStandard, Subsignal, Pins
from litex_boards.platforms import colorlight_5a_75b
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.s... | [
"litex.build.lattice.trellis.trellis_args",
"litex.build.lattice.trellis.trellis_argdict"
] | [((1490, 1568), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC with PLL on Colorlight 5A-75B"""'}), "(description='LiteX SoC with PLL on Colorlight 5A-75B')\n", (1513, 1568), False, 'import argparse\n'), ((1963, 1983), 'litex.build.lattice.trellis.trellis_args', 'trellis_args',... |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from migen.genlib.cdc import MultiReg
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.s... | [
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream_sim.Packet",
"litex.soc.interconnect.stream_sim.PacketStreamer",
"litex.soc.interconnect.stream_sim.PacketLogger",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.stream.Endpoint"
] | [((526, 550), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 32)]"], {}), "([('data', 32)])\n", (534, 550), False, 'from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO\n'), ((582, 606), 'litex.soc.interconnect.stream.Endpoint', 'Endpoint', (["[('data', 32)]"], {}), "([... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal
from litex.build.xilinx import XilinxPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs -----------------------------------------------------------------------------... | [
"litex.build.generic_platform.IOStandard",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.generic_platform.Pins",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((381, 392), 'litex.build.generic_platform.Pins', 'Pins', (['"""H16"""'], {}), "('H16')\n", (385, 392), False, 'from litex.build.generic_platform import Pins, IOStandard, Subsignal\n'), ((394, 416), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (404, 416), False, ... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
#
# http://trenz.org/max1000-info
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((3176, 3249), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""10M08SAU169C8G"""', '_io'], {'toolchain': 'toolchain'}), "(self, '10M08SAU169C8G', _io, toolchain=toolchain)\n", (3199, 3249), False, 'from litex.build.altera import AlteraPlatform\n'), ((3596, 3608), 'litex.build.alt... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
# IOs ------------------------------------------------------------------
_io = [
("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
("serial", 0,
... | [
"litex.build.altera.AlteraPlatform.__init__"
] | [((1310, 1360), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""5CSEMA5F31C6"""', '_io'], {}), "(self, '5CSEMA5F31C6', _io)\n", (1333, 1360), False, 'from litex.build.altera import AlteraPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# iCEBreaker Bitsy FPGA:
# - 1BitSquared Store: https://1bitsquared.com/collections/fpga/products/icebreaker-bitsy
# - Design files: https://github.com/icebreaker... | [
"litex.build.dfu.DFUProg",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((4289, 4380), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', 'io', 'connectors'], {'toolchain': 'toolchain'}), "(self, 'ice40-up5k-sg48', io, connectors, toolchain\n =toolchain)\n", (4313, 4380), False, 'from litex.build.lattice import LatticePlatform... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.cdc import AsyncResetSynchronizer
from litex.soc.interconnect import stream
# Altera Atlant... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((490, 520), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (505, 520), False, 'from litex.soc.interconnect import stream\n'), ((552, 582), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (567, 582), ... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import math
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.cdc import MultiReg
from litex.soc.interconnect import stream
# Layout/Helpers -----------------------------... | [
"litex.soc.interconnect.stream.EndpointDescription"
] | [((448, 490), 'litex.soc.interconnect.stream.EndpointDescription', 'stream.EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (474, 490), False, 'from litex.soc.interconnect import stream\n'), ((3462, 3506), 'migen.fhdl.specials.Tristate', 'Tristate', (['pads.data', 'data_w', 'data_oe', 'data_r'], {}... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use:
# The current support is sufficient to run LiteX BIOS on Cortex-A53 core #0:
# ./alinx_axu2cga.py --build --load
# LiteX BIOS can then be executed on hardware usin... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc.SoCRegion",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((6709, 6774), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Alinx AXU2CGA"""'}), "(description='LiteX SoC on Alinx AXU2CGA')\n", (6732, 6774), False, 'import argparse\n'), ((7187, 7212), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}),... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.resetsync import AsyncResetSynchroni... | [
"litex.soc.interconnect.axi.AXIInterface"
] | [((3364, 3411), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_ps7', '(~ps7_rst_n)'], {}), '(self.cd_ps7, ~ps7_rst_n)\n', (3386, 3411), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((9968, 10030), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterfa... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
# IOs -------------------------------------... | [
"litex.build.lattice.programmer.OpenOCDJTAGProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((3999, 4095), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', "(device + '-45F-8MG285C')", '_io'], {'toolchain': 'toolchain'}), "(self, device + '-45F-8MG285C', _io, toolchain=\n toolchain, **kwargs)\n", (4023, 4095), False, 'from litex.build.lattice import LatticePlatform\n')... |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020-2022 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.targets.digilent_arty import BaseSoC
from litex.bui... | [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc.SoCRegion",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((11099, 11158), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Arty A7"""'}), "(description='LiteX SoC on Arty A7')\n", (11122, 11158), False, 'import argparse\n'), ((12480, 12505), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(par... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
LiteX standalone SoC generator.
This generator reduces the scope of LiteX to CPU/Peripherals selection/integration and to the creation
of SoC with MMAP/Streaming DMA interfaces t... | [
"litex.soc.interconnect.axi.AXILiteInterface",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.soc.SoCRegion",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((3866, 3934), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX standalone SoC generator"""'}), "(description='LiteX standalone SoC generator')\n", (3888, 3934), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((3346, 3402), 'litex.s... |
#
# This file is part of LiteHelloWorld.
#
from migen import *
from litex.soc.interconnect import stream
from litehelloworld.common import *
from litex.soc.interconnect import wishbone
class DummyLitexModel(Module):
def __init__(self, inputs, outputs):
#Create inputs and outputs for the core
sel... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.stream.Endpoint"
] | [((329, 367), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['dummy_phy_data_layout'], {}), '(dummy_phy_data_layout)\n', (344, 367), False, 'from litex.soc.interconnect import stream\n'), ((390, 428), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['dummy_phy_data_layout'], {}), '(dummy_p... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ---------------------------------------------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((8402, 8455), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""10CL016YU256C8G"""', '_io'], {}), "(self, '10CL016YU256C8G', _io)\n", (8425, 8455), False, 'from litex.build.altera import AlteraPlatform\n'), ((8505, 8552), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', (... |
# This file is Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 Dolu1990 <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# ... | [
"litex.build.tools.deprecated_warning",
"litex.soc.cores.cpu.lm32.LM32",
"litex.soc.cores.timer.Timer",
"litex.soc.cores.cpu.picorv32.PicoRV32",
"litex.soc.cores.uart.UARTStub",
"litex.soc.interconnect.csr_bus.Interface",
"litex.soc.interconnect.csr_bus.CSRBankArray",
"litex.soc.cores.identifier.Ident... | [((1862, 1888), 'os.path.splitext', 'os.path.splitext', (['filename'], {}), '(filename)\n', (1878, 1888), False, 'import os\n'), ((2447, 2471), 'math.ceil', 'math.ceil', (['(data_size / 4)'], {}), '(data_size / 4)\n', (2456, 2471), False, 'import math\n'), ((7271, 7312), 'litex.soc.cores.cpu.check_format_cpu_variant', ... |
#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from litex.build.generic_platform import GenericPlatform
from litex.build.gowin import common, gowin
# GowinPlatform -----------------------------------... | [
"litex.build.generic_platform.GenericPlatform.get_verilog",
"litex.build.generic_platform.GenericPlatform.__init__",
"litex.build.gowin.gowin.GowinToolchain"
] | [((528, 583), 'litex.build.generic_platform.GenericPlatform.__init__', 'GenericPlatform.__init__', (['self', 'device', '*args'], {}), '(self, device, *args, **kwargs)\n', (552, 583), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((1247, 1369), 'litex.build.generic_platform.GenericPlatform.get_ve... |
#
# This file is part of LiteX.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.cores.cpu import CPU
from litex.soc.interconnect import axi
class ZynqMP(CPU):
variants = ["standard"]
family = "aarch64"
name ... | [
"litex.soc.interconnect.axi.AXIInterface"
] | [((2070, 2140), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': 'data_width', 'address_width': '(32)', 'id_width': '(16)'}), '(data_width=data_width, address_width=32, id_width=16)\n', (2086, 2140), False, 'from litex.soc.interconnect import axi\n')] |
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
class SPRAM(Module):
"""
ICE40 UltraPlus family-specific Wishbone interface to the Single Port RAM
(SPRAM) primitives. Because SPRAM is much more coarse grained than Block
... | [
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.wishbone.Interface"
] | [((1097, 1122), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', (['width'], {}), '(width)\n', (1115, 1122), False, 'from litex.soc.interconnect import wishbone\n'), ((4219, 4232), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {}), '(8)\n', (4229, 4232), False, 'from litex.soc.inter... |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by a... | [
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((1555, 1613), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Digilent Arty args."""'}), "(description='Digilent Arty args.')\n", (1578, 1613), False, 'import argparse\n'), ((3126, 3164), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado.vivado_build_argdict', (['self.args'], {}... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import UJProg
# IOs -----------------------------------------------... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.UJProg",
"litex.build.lattice.LatticePlatform.__init__"
] | [((8936, 9028), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', "(device + '-6BG381C')", '_io'], {'toolchain': 'toolchain'}), "(self, device + '-6BG381C', _io, toolchain=\n toolchain, **kwargs)\n", (8960, 9028), False, 'from litex.build.lattice import LatticePlatform\n'), ((9073... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
import importlib
from migen import *
from litex.build.io import CRG
from litex.soc.integration.soc_core im... | [
"litex.soc.integration.soc.SoCRegion"
] | [((2424, 2442), 'litex_boards.platforms.tec0117.Platform', 'tec0117.Platform', ([], {}), '()\n', (2440, 2442), False, 'from litex_boards.platforms import tec0117\n'), ((2841, 2898), 'spiflash.serialflash.SerialFlashManager.get_flash_device', 'SerialFlashManager.get_flash_device', (['"""ftdi://ftdi:2232/2"""'], {}), "('... |
from litex.soc.integration.soc_core import mem_decoder
from liteeth.phy.model import LiteEthPHYModel
from liteeth.core.mac import LiteEthMAC
from targets.utils import csr_map_update
from targets.sim.base import BaseSoC
class NetSoC(BaseSoC):
# FIXME: The sim seems to require ethphy at 18 and ethmac at 19!?
# csr... | [
"litex.soc.integration.soc_core.mem_decoder"
] | [((930, 969), 'targets.sim.base.BaseSoC.__init__', 'BaseSoC.__init__', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (946, 969), False, 'from targets.sim.base import BaseSoC\n'), ((1083, 1176), 'liteeth.core.mac.LiteEthMAC', 'LiteEthMAC', ([], {'phy': 'self.ethphy', 'dw': '(32)', 'interface': '"""wishbone"""', ... |
# This file is Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
("afedat0", 0, Pins("AE25"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 1, Pins("AE26"), IOStandard("DIFF_SSTL18_II")),
... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((14602, 14677), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg676-3"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg676-3', _io, toolchain='vivado')\n", (14625, 14677), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), (... |
#!/usr/bin/env python3
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
import os
import argparse
from migen import *
from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
from litex_boards.targets import colorlight_5a_75x
from litex.build.generic_platform import Pins... | [
"litex.build.generic_platform.Pins",
"litex.build.lattice.trellis.trellis_args",
"litex.soc.integration.soc_core.soc_core_args",
"litex.soc.integration.builder.builder_args",
"litex.soc.integration.soc_core.soc_core_argdict",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.integration.builder.builde... | [((7892, 7961), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Colorlight 5A-75X"""'}), "(description='LiteX SoC on Colorlight 5A-75X')\n", (7915, 7961), False, 'import argparse\n'), ((8874, 8894), 'litex.soc.integration.builder.builder_args', 'builder_args', (['parser'], {}... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import re
from migen import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.inte... | [
"litex.build.sim.SimPlatform.__init__",
"litex.build.generic_platform.Pins"
] | [((919, 939), 'litedram.phy.utils.Serializer', 'Serializer', ([], {}), '(**kwargs)\n', (929, 939), False, 'from litedram.phy.utils import Serializer, Deserializer, edge\n'), ((1185, 1207), 'litedram.phy.utils.Deserializer', 'Deserializer', ([], {}), '(**kwargs)\n', (1197, 1207), False, 'from litedram.phy.utils import S... |
#
# This file is part of LiteX.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
import shutil
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.microsemi impo... | [
"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file"
] | [((1615, 1663), 'litex.build.tools.write_to_file', 'tools.write_to_file', (["(build_name + '_io.pdc')", 'pdc'], {}), "(build_name + '_io.pdc', pdc)\n", (1634, 1663), False, 'from litex.build import tools\n'), ((1876, 1924), 'litex.build.tools.write_to_file', 'tools.write_to_file', (["(build_name + '_fp.pdc')", 'pdc'], ... |
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# License: BSD
"""Direct Memory Access (DMA) reader and writer modules."""
from migen import *
... | [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((1415, 1465), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', port.address_width)]"], {}), "([('address', port.address_width)])\n", (1430, 1465), False, 'from litex.soc.interconnect import stream\n'), ((1497, 1541), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data',... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import filecmp
import unittest
from litex.build.tools import write_to_file
from litedram.init import get_sdram_phy_c_header, get_sdram_phy_py_header
def compare_with_reference(content, filen... | [
"litex.boards.targets.kcu105.BaseSoC",
"litex.build.tools.write_to_file"
] | [((330, 362), 'litex.build.tools.write_to_file', 'write_to_file', (['filename', 'content'], {}), '(filename, content)\n', (343, 362), False, 'from litex.build.tools import write_to_file\n'), ((442, 461), 'os.remove', 'os.remove', (['filename'], {}), '(filename)\n', (451, 461), False, 'import os\n'), ((393, 436), 'os.pa... |
#!/usr/bin/env python3
from litex import RemoteClient
import time
wb = RemoteClient()
wb.open()
# --------------------------------------------------------------------
wb.regs.writer_start.write(0)
wb.regs.writer_reset.write(1)
time.sleep(10000 / 1e6)
wb.regs.writer_reset.write(0)
wb.write(0x20000000, 0xffffffff) #... | [
"litex.RemoteClient"
] | [((73, 87), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (85, 87), False, 'from litex import RemoteClient\n'), ((231, 260), 'time.sleep', 'time.sleep', (['(10000 / 1000000.0)'], {}), '(10000 / 1000000.0)\n', (241, 260), False, 'import time\n'), ((2253, 2282), 'time.sleep', 'time.sleep', (['(10000 / 1000000.0... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((7513, 7605), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg676-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg676-2', _io, _connectors,\n toolchain='vivado')\n", (7536, 7605), False, 'from litex.build.xilinx import XilinxPlat... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2017-2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from litex.build.generic_programmer import GenericProgrammer
from litex.build import tools
# LatticeProgrammer ------------------------------------... | [
"litex.build.lattice.bit_to_svf.bit_to_svf",
"litex.build.tools.write_to_file",
"litex.build.generic_programmer.GenericProgrammer.__init__"
] | [((710, 752), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['xcf_file', 'xcf_content'], {}), '(xcf_file, xcf_content)\n', (729, 752), False, 'from litex.build import tools\n'), ((1039, 1093), 'litex.build.generic_programmer.GenericProgrammer.__init__', 'GenericProgrammer.__init__', (['self', 'flash_proxy_... |
from migen import Module, TSTriple, Cat
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
from litex.soc.integration.doc import ModuleDoc
from litex.build.generic_platform import Pins, Subsignal
class TouchPads(Module, AutoCSR):
touch_device = [
("touch_pads", 0,
Subsignal("... | [
"litex.soc.integration.doc.ModuleDoc",
"litex.build.generic_platform.Pins",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus"
] | [((568, 1040), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""Fomu Touchpads\n\n Fomu has four single-ended exposed pads on its side. These pads are designed\n to be connected to some captouch block, or driven in a resistive touch mode\n in order to get simple touchpad support.\n\n ... |
from migen import *
from litex.soc.interconnect.csr import AutoCSR, CSRStorage
class LEDCtrl(Module, AutoCSR):
def __init__(self, num, reset_value):
self._set = CSRStorage(num * 4, reset_value)
self.inputs = leds = Array(Record([('r', 1), ('g', 1), ('b', 1)]) for i in range(num))
self.out... | [
"litex.soc.interconnect.csr.CSRStorage"
] | [((175, 207), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(num * 4)', 'reset_value'], {}), '(num * 4, reset_value)\n', (185, 207), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs -----------------------------------------------------... | [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3786, 3848), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', 'device', '_io'], {'toolchain': '"""vivado"""'}), "(self, device, _io, toolchain='vivado')\n", (3809, 3848), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((4219, 4277), 'litex.build.openocd.OpenOCD', 'OpenOC... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.cores.icap import ICAP, ICAPBitstream
class TestICAP(unittest.TestCase):
def test_icap_command_reload(self):
def generator(dut):
... | [
"litex.soc.cores.icap.ICAPBitstream",
"litex.soc.cores.icap.ICAP"
] | [((587, 624), 'litex.soc.cores.icap.ICAP', 'ICAP', ([], {'with_csr': '(False)', 'simulation': '(True)'}), '(with_csr=False, simulation=True)\n', (591, 624), False, 'from litex.soc.cores.icap import ICAP, ICAPBitstream\n'), ((795, 825), 'litex.soc.cores.icap.ICAPBitstream', 'ICAPBitstream', ([], {'simulation': '(True)'}... |
#!/usr/bin/env python3
from os import path
from itertools import cycle, islice, chain, count
from migen import *
from litex.soc.cores.uart import UARTWishboneBridge, UARTBone
from litex.soc.integration.builder import Builder
from litex.build.generic_platform import Subsignal, IOStandard, Pins
from litex_boards.tar... | [
"litex.soc.integration.builder.Builder"
] | [((3952, 4014), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'csr_csv': '"""test/csr.csv"""', 'csr_json': '"""test/csr.json"""'}), "(soc, csr_csv='test/csr.csv', csr_json='test/csr.json')\n", (3959, 4014), False, 'from litex.soc.integration.builder import Builder\n'), ((567, 580), 'itertools.cycle', '... |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
wb = RemoteClient()
wb.open()
print("\nPWM")
#wb.write(0x82002800, 0xff)
#wb.write(0x82002810, 0xff)
#wb.write(0x8200280C, 0x40)
print("Enable 0x{:08X}".format(wb.read(0x82002800)))
print("Divider 0x{:08X}".format(wb.read(0x82002804) << 8 | w... | [
"litex.tools.litex_client.RemoteClient"
] | [((79, 93), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (91, 93), False, 'from litex.tools.litex_client import RemoteClient\n')] |
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import AutoCSR
from litex.soc.interconnect import wishbone
from migen import *
from migen.genlib.cdc import Mu... | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.doc.ModuleDoc"
] | [((3498, 3527), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""SPI slave driver"""'], {}), "('SPI slave driver')\n", (3507, 3527), False, 'from litex.soc.integration.doc import AutoDoc, ModuleDoc\n'), ((3559, 3579), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (3577, 3... |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
import socket
from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
from litex.t... | [
"litex.tools.remote.etherbone.EtherbonePacket",
"litex.tools.remote.etherbone.EtherboneRecord",
"litex.tools.remote.csr_builder.CSRBuilder.__init__",
"litex.tools.remote.etherbone.EtherboneWrites"
] | [((4883, 5003), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX Client utility."""', 'formatter_class': 'argparse.ArgumentDefaultsHelpFormatter'}), "(description='LiteX Client utility.',\n formatter_class=argparse.ArgumentDefaultsHelpFormatter)\n", (4906, 5003), False, 'import ar... |
from enum import IntEnum, unique
from functools import reduce
from operator import or_, and_
from migen import *
from migen.genlib.coding import Decoder as OneHotDecoder
from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from ... | [
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.csr.CSRField"
] | [((13070, 13075), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (13073, 13075), False, 'from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR\n'), ((15266, 15287), 'migen.genlib.coding.Decoder', 'OneHotDecoder', (['nranks'], {}), '(nranks)\n', (15279, 15287), True, 'from mige... |
#
# This file is part of LiteX.
#
# Copyright (c) 2018-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import logging
import math
from migen import Record
from litex.soc.integration.soc import colorer
logging.basicConfig(level=logging.INFO)
# Logging --------------------------------------------------... | [
"litex.soc.integration.soc.colorer"
] | [((219, 258), 'logging.basicConfig', 'logging.basicConfig', ([], {'level': 'logging.INFO'}), '(level=logging.INFO)\n', (238, 258), False, 'import logging\n'), ((557, 573), 'litex.soc.integration.soc.colorer', 'colorer', (['"""ClkIn"""'], {}), "('ClkIn')\n", (564, 573), False, 'from litex.soc.integration.soc import colo... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Modified for custom ecp5 board, <NAME>, 2021
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import OpenOCDJTAGProgram... | [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.OpenOCDJTAGProgrammer",
"litex.build.lattice.LatticePlatform.request",
"litex.build.lattice.LatticePlatform.__init__"
] | [((3222, 3325), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8BG256"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'LFE5U-25F-8BG256', _io, _connectors,\n toolchain=toolchain, **kwargs)\n", (3246, 3325), False, 'from litex.build.lattice import ... |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2020-2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from math import ceil
from operator import and_
from migen import *
from migen.genlib.misc import WaitTimer
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
fr... | [
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus"
] | [((2358, 2370), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {}), '()\n', (2368, 2370), False, 'from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage\n'), ((2407, 2432), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(databits // 8)'], {}), '(databits // 8)\n', (2417, 2432... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
fro... | [
"litex.build.generic_platform.Misc",
"litex.build.generic_platform.IOStandard",
"litex.build.generic_platform.Pins",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((501, 512), 'litex.build.generic_platform.Pins', 'Pins', (['"""N14"""'], {}), "('N14')\n", (505, 512), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((514, 536), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (524, 536), F... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Colorlight i5 PCB and IOs have been documented by @wuxx
# https://github.com/wuxx/Colorlight-FPGA-Projects
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlat... | [
"litex.build.lattice.programmer.EcpDapProgrammer",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((5132, 5223), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', 'device', 'io'], {'connectors': 'connectors', 'toolchain': 'toolchain'}), '(self, device, io, connectors=connectors, toolchain\n =toolchain)\n', (5156, 5223), False, 'from litex.build.lattice import LatticePlatform\... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs -------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4702, 4781), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu7ev-ffvc1156-2-i"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xczu7ev-ffvc1156-2-i', _io, toolchain=toolchain)\n", (4725, 4781), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), (... |
from migen import *
from litex.soc.interconnect import stream
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter
class PatternMemory(Module):
def __init__(self,... | [
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.stream.Endpoint"
] | [((1696, 1701), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (1699, 1701), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR\n'), ((1815, 1882), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', ([], {'description': '"""Indicates that the transfer is not ongoing"""'}), ... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs -------------... | [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((4472, 4542), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE6E22C8"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'EP4CE6E22C8', _io, toolchain=toolchain)\n", (4495, 4542), False, 'from litex.build.altera import AlteraPlatform\n'), ((5480, 5492), 'litex.build.altera.pr... |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
"""
LitePCIE standalone core generator
LitePCIe aims to be directly used as a python package when the SoC is created using LiteX. However,
for some use cases it could be interesting to generate a standalone verilog file of the c... | [
"litex.soc.integration.export.get_csr_header",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.dna.DNA",
"litex.soc.cores.xadc.XADC",
"litex.build.xilinx.XilinxPlatform",
"litex.soc.integration.export.get_mem_header",
"litex.soc.cores.icap.ICAP",
"litex.soc.integration.export.get_soc_hea... | [((12352, 12425), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LitePCIe standalone core generator"""'}), "(description='LitePCIe standalone core generator')\n", (12375, 12425), False, 'import argparse\n'), ((6386, 6455), 'litepcie.core.LitePCIeEndpoint', 'LitePCIeEndpoint', (['self.pci... |
from litex.build.sim import SimPlatform
from litex.build.generic_platform import Pins, Subsignal
class SimPins(Pins):
def __init__(self, n=1):
Pins.__init__(self, "s "*n)
_io = [
("sys_clk", 0, SimPins(1)),
("sys_rst", 0, SimPins(1)),
("serial", 0,
Subsignal("source_valid", SimPins()... | [
"litex.build.generic_platform.Pins.__init__",
"litex.build.sim.SimPlatform.__init__"
] | [((157, 186), 'litex.build.generic_platform.Pins.__init__', 'Pins.__init__', (['self', "('s ' * n)"], {}), "(self, 's ' * n)\n", (170, 186), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((728, 766), 'litex.build.sim.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""SIM"""', '_io'], {... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs --------------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((6738, 6829), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020-clg400-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7z020-clg400-1', _io, _connectors,\n toolchain='vivado')\n", (6761, 6829), False, 'from litex.build.xilinx import XilinxPlatfo... |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
# clock
("clk25", 0, Pins("M9"), IOStandard("LVCMOS33")),
# led
("user_led", 0, Pins("F7"), IOStandard("LVCMOS33")),
# button
("user_btn", 0, Pins("P4"), IOStandard("LVCMOS33")),
# serial
... | [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2081, 2136), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx16-2-ftg256"""', '_io'], {}), "(self, 'xc6slx16-2-ftg256', _io)\n", (2104, 2136), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex_boards.platforms impor... | [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc.SoCRegion",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((4410, 4485), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on Spartan Edge Accelerator"""'}), "(description='LiteX SoC on Spartan Edge Accelerator')\n", (4432, 4485), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((5166, 5... |
import os
import sys
import argparse
import shutil
import pathlib
from litex.soc.integration.builder import Builder
import platform
import trigger
def main():
parser = argparse.ArgumentParser(description="")
parser.add_argument("--load", action="store_true", help="Load bitstream")
args = parser.parse_... | [
"litex.soc.integration.builder.Builder"
] | [((176, 215), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '""""""'}), "(description='')\n", (199, 215), False, 'import argparse\n'), ((338, 356), 'platform.BaseSoC', 'platform.BaseSoC', ([], {}), '()\n', (354, 356), False, 'import platform\n'), ((589, 616), 'trigger.ClockDivider', 'trigge... |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
import unittest
from migen import *
from litex.soc.cores.spi import SPIMaster, SPISlave
class TestSPI(unittest.TestCase):
def test_spi_master_syntax(self):
spi_master = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq... | [
"litex.soc.cores.spi.SPIMaster",
"litex.soc.cores.spi.SPISlave"
] | [((252, 342), 'litex.soc.cores.spi.SPIMaster', 'SPIMaster', ([], {'pads': 'None', 'data_width': '(32)', 'sys_clk_freq': '(100000000.0)', 'spi_clk_freq': '(5000000.0)'}), '(pads=None, data_width=32, sys_clk_freq=100000000.0, spi_clk_freq=\n 5000000.0)\n', (261, 342), False, 'from litex.soc.cores.spi import SPIMaster,... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs -------------------------------------------------------------------------------------... | [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2625, 2704), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu9eg-ffvb1156-2-i"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xczu9eg-ffvb1156-2-i', _io, toolchain=toolchain)\n", (2648, 2704), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), (... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from math import log2
from migen import *
from migen.genlib.roundrobin import *
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from... | [
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.stream.EndpointDescription",
"litex.soc.interconnect.stream.Endpoint"
] | [((5260, 5293), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['sink_description'], {}), '(sink_description)\n', (5275, 5293), False, 'from litex.soc.interconnect import stream\n'), ((5325, 5360), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['source_description'], {}), '(source_descrip... |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import math
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.cdc import MultiReg
from litex.soc.interconnect import stream
from litex.build.io import SDRTristate
# Layo... | [
"litex.soc.interconnect.stream.EndpointDescription"
] | [((488, 530), 'litex.soc.interconnect.stream.EndpointDescription', 'stream.EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (514, 530), False, 'from litex.soc.interconnect import stream\n'), ((2273, 2331), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['read_fifo_almost_full', 'read_fifo_almost_full_us... |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.efinix.platform import EfinixPlatform
from litex.build.efinix import EfinixProgrammer
# IOs -----------------------------------------------... | [
"litex.build.efinix.platform.EfinixPlatform.__init__",
"litex.build.efinix.platform.EfinixPlatform.do_finalize",
"litex.build.efinix.EfinixProgrammer"
] | [((4185, 4297), 'litex.build.efinix.platform.EfinixPlatform.__init__', 'EfinixPlatform.__init__', (['self', '"""Ti60F225C3"""', '_io', '_connectors'], {'iobank_info': 'iobank_info', 'toolchain': 'toolchain'}), "(self, 'Ti60F225C3', _io, _connectors, iobank_info=\n iobank_info, toolchain=toolchain)\n", (4208, 4297), ... |
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
from migen.genlib.cdc import MultiReg
def io_pins():
return Record([("i", 1),("o", 1),("oe", 1)])
class IOPin(Module):
def __init__(self, pad):
... | [
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus"
] | [((613, 638), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['self._ts.i', '_in'], {}), '(self._ts.i, _in)\n', (621, 638), False, 'from migen.genlib.cdc import MultiReg\n'), ((1362, 1489), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['nbits'], {'description': '"""GPIO Tristate(s) Control.\n Write ``1`` e... |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from enum import IntEnum
from migen import *
from migen.genlib.cdc import PulseSynchronizer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
# Constants -----------... | [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((10939, 10983), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', 32)]", 'fifo_depth'], {}), "([('data', 32)], fifo_depth)\n", (10955, 10983), False, 'from litex.soc.interconnect import stream\n')] |
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
from migen import *
from litex.soc.interconnect import csr, stream
class MemStreamReader(Module):
def __init__(self, rport):
self.sink = sink = stream.Endpoint([
('address', rport.adr.nbits),
])
sel... | [
"litex.soc.interconnect.stream.Endpoint"
] | [((238, 285), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', rport.adr.nbits)]"], {}), "([('address', rport.adr.nbits)])\n", (253, 285), False, 'from litex.soc.interconnect import csr, stream\n'), ((340, 386), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', rport.... |
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