code stringlengths 144 85.5k | apis list | extract_api stringlengths 121 59.8k |
|---|---|---|
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk12", 0, Pins("4"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("23"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("26"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("27"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("28"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("29"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("30"), IOStandard("LVCMOS33")),
# RGB led, active-low
("rgb_led", 0,
Subsignal("r", Pins("112")),
Subsignal("g", Pins("114")),
Subsignal("b", Pins("113")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("106")),
Subsignal("g", Pins("111")),
Subsignal("b", Pins("110")),
IOStandard("LVCMOS33"),
),
("rgb_led", 2,
Subsignal("r", Pins("101")),
Subsignal("g", Pins("104")),
Subsignal("b", Pins("102")),
IOStandard("LVCMOS33"),
),
("rgb_led", 3,
Subsignal("r", Pins("98")),
Subsignal("g", Pins("100")),
Subsignal("b", Pins("99")),
IOStandard("LVCMOS33"),
),
# Switches
("user_sw", 0, Pins("75"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("76"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("78"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("79"), IOStandard("LVCMOS33")),
("user_sw", 4, Pins("80"), IOStandard("LVCMOS33")),
("user_sw", 5, Pins("81"), IOStandard("LVCMOS33")),
("user_sw", 6, Pins("82"), IOStandard("LVCMOS33")),
("user_sw", 7, Pins("83"), IOStandard("LVCMOS33")),
# Buttons.
("user_btn", 0, Pins("58"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("59"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("60"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("61"), IOStandard("LVCMOS33")),
("user_btn", 4, Pins("62"), IOStandard("LVCMOS33")),
("user_btn", 5, Pins("63"), IOStandard("LVCMOS33")),
("user_btn", 6, Pins("64"), IOStandard("LVCMOS33")),
("user_btn", 7, Pins("65"), IOStandard("LVCMOS33")),
# Serial.
# FT232H has only one interface -> use (arbitrary) two pins from J2 to
# connect an external USB<->serial adapter
("serial", 0,
Subsignal("tx", Pins("116")), # J2.17
Subsignal("rx", Pins("115")), # J2.18
IOStandard("LVCMOS33")
),
# Seven Segment
("seven_seg_dig", 0, Pins("137"), IOStandard("LVCMOS33")),
("seven_seg_dig", 1, Pins("140"), IOStandard("LVCMOS33")),
("seven_seg_dig", 2, Pins("141"), IOStandard("LVCMOS33")),
("seven_seg_dig", 3, Pins("7"), IOStandard("LVCMOS33")),
("seven_seg", 0, Pins("138 142 9 11 12 139 8 10"), IOStandard("LVCMOS33")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
["J1", "- 38 39 40 41 42 43 44 66 67 68 69 70 71 72 96 95 94 93 -"],
["J2", "- 136 135 134 133 132 131 130 129 128 123 122 121 120 119 118 117 116 115 -"],
]
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self, toolchain="gowin"):
GowinPlatform.__init__(self, "GW1N-UV4LQ144C6/I5", _io, _connectors, toolchain=toolchain, devicename="GW1N-4")
self.toolchain.options["use_mspi_as_gpio"] = 1
def create_programmer(self):
return OpenFPGALoader("runber")
def do_finalize(self, fragment):
GowinPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
| [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((3780, 3894), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-UV4LQ144C6/I5"""', '_io', '_connectors'], {'toolchain': 'toolchain', 'devicename': '"""GW1N-4"""'}), "(self, 'GW1N-UV4LQ144C6/I5', _io, _connectors,\n toolchain=toolchain, devicename='GW1N-4')\n", (3802, 3894), False, 'from litex.build.gowin.platform import GowinPlatform\n'), ((3995, 4019), 'litex.build.openfpgaloader.OpenFPGALoader', 'OpenFPGALoader', (['"""runber"""'], {}), "('runber')\n", (4009, 4019), False, 'from litex.build.openfpgaloader import OpenFPGALoader\n'), ((4066, 4107), 'litex.build.gowin.platform.GowinPlatform.do_finalize', 'GowinPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4091, 4107), False, 'from litex.build.gowin.platform import GowinPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2017-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0,
Subsignal("p", Pins("G10"), IOStandard("LVDS")),
Subsignal("n", Pins("F10"), IOStandard("LVDS"))
),
("clk300", 0,
Subsignal("p", Pins("AK17"), IOStandard("DIFF_SSTL12")),
Subsignal("n", Pins("AK16"), IOStandard("DIFF_SSTL12"))
),
("cpu_reset", 0, Pins("AN8"), IOStandard("LVCMOS18")),
# Leds
("user_led", 0, Pins("AP8"), IOStandard("LVCMOS18")),
("user_led", 1, Pins("H23"), IOStandard("LVCMOS18")),
("user_led", 2, Pins("P20"), IOStandard("LVCMOS18")),
("user_led", 3, Pins("P21"), IOStandard("LVCMOS18")),
("user_led", 4, Pins("N22"), IOStandard("LVCMOS18")),
("user_led", 5, Pins("M22"), IOStandard("LVCMOS18")),
("user_led", 6, Pins("R23"), IOStandard("LVCMOS18")),
("user_led", 7, Pins("P23"), IOStandard("LVCMOS18")),
# Buttons
("user_btn_c", 0, Pins("AE10"), IOStandard("LVCMOS18")),
("user_btn_n", 0, Pins("AD10"), IOStandard("LVCMOS18")),
("user_btn_s", 0, Pins("AF8"), IOStandard("LVCMOS18")),
("user_btn_w", 0, Pins("AF9"), IOStandard("LVCMOS18")),
("user_btn_e", 0, Pins("AE8"), IOStandard("LVCMOS18")),
# Switches
("user_dip_btn", 0, Pins("AN16"), IOStandard("LVCMOS12")),
("user_dip_btn", 1, Pins("AN19"), IOStandard("LVCMOS12")),
("user_dip_btn", 2, Pins("AP18"), IOStandard("LVCMOS12")),
("user_dip_btn", 3, Pins("AN14"), IOStandard("LVCMOS12")),
# SMA
("user_sma_clock", 0,
Subsignal("p", Pins("D23"), IOStandard("LVDS")),
Subsignal("n", Pins("C23"), IOStandard("LVDS"))
),
("user_sma_clock_p", 0, Pins("D23"), IOStandard("LVCMOS18")),
("user_sma_clock_n", 0, Pins("C23"), IOStandard("LVCMOS18")),
("user_sma_gpio", 0,
Subsignal("p", Pins("H27"), IOStandard("LVDS")),
Subsignal("n", Pins("G27"), IOStandard("LVDS"))
),
("user_sma_gpio_p", 0, Pins("H27"), IOStandard("LVCMOS18")),
("user_sma_gpio_n", 0, Pins("G27"), IOStandard("LVCMOS18")),
# I2C
("i2c", 0,
Subsignal("scl", Pins("J24")),
Subsignal("sda", Pins("J25")),
IOStandard("LVCMOS18")
),
# Serial
("serial", 0,
Subsignal("cts", Pins("L23")),
Subsignal("rts", Pins("K27")),
Subsignal("tx", Pins("K26")),
Subsignal("rx", Pins("G25")),
IOStandard("LVCMOS18")
),
# SPIFlash
("spiflash", 0, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("U7")),
Subsignal("dq", Pins("AC7 AB7 AA7 Y7")),
IOStandard("LVCMOS18")
),
("spiflash", 1, # clock needs to be accessed through primitive
Subsignal("cs_n", Pins("G26")),
Subsignal("dq", Pins("M20 L20 R21 R22")),
IOStandard("LVCMOS18")
),
# SDCard
("spisdcard", 0,
Subsignal("clk", Pins("AL10")),
Subsignal("cs_n", Pins("AH8")),
Subsignal("mosi", Pins("AD9"), Misc("PULLUP")),
Subsignal("miso", Pins("AP9"), Misc("PULLUP")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS18")
),
("sdcard", 0,
Subsignal("clk", Pins("AL10")),
Subsignal("cmd", Pins("AD9"), Misc("PULLUP True")),
Subsignal("data", Pins("AP9 AN9 AH9 AH8"), Misc("PULLUP True")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS18")
),
# Rotary Encoder
("rotary", 0,
Subsignal("a", Pins("Y21")),
Subsignal("b", Pins("AD26")),
Subsignal("push", Pins("AF28")),
IOStandard("LVCMOS18")
),
# HDMI
("hdmi", 0,
Subsignal("d", Pins(
"AK11 AP11 AP13 AN13 AN11 AM11 AN12 AM12",
"AL12 AK12 AL13 AK13 AD11 AH12 AG12 AJ11",
"AG10 AK8")),
Subsignal("de", Pins("AE11")),
Subsignal("clk", Pins("AF13")),
Subsignal("vsync", Pins("AH13")),
Subsignal("hsync", Pins("AE13")),
Subsignal("spdif", Pins("AE12")),
Subsignal("spdif_out", Pins("AF12")),
IOStandard("LVCMOS18")
),
# DDR4 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"AE17 AH17 AE18 AJ15 AG16 AL17 AK18 AG17",
"AF18 AH19 AF15 AD19 AJ14 AG19"),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AF17 AL15"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("AG15"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AF14"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AG14"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AD16"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AL19"), IOStandard("SSTL12_DCI")),
Subsignal("act_n", Pins("AH14"), IOStandard("SSTL12_DCI")),
#Subsignal("ten", Pins("AH16"), IOStandard("SSTL12_DCI")),
#Subsignal("alert_n", Pins("AJ16"), IOStandard("SSTL12_DCI")),
#Subsignal("par", Pins("AD18"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AD21 AE25 AJ21 AM21 AH26 AN26 AJ29 AL32"),
IOStandard("POD12_DCI")),
Subsignal("dq", Pins(
"AE23 AG20 AF22 AF20 AE22 AD20 AG22 AE20",
"AJ24 AG24 AJ23 AF23 AH23 AF24 AH22 AG25",
"AL22 AL25 AM20 AK23 AK22 AL24 AL20 AL23",
"AM24 AN23 AN24 AP23 AP25 AN22 AP24 AM22",
"AH28 AK26 AK28 AM27 AJ28 AH27 AK27 AM26",
"AL30 AP29 AM30 AN28 AL29 AP28 AM29 AN27",
"AH31 AH32 AJ34 AK31 AJ31 AJ30 AH34 AK32",
"AN33 AP33 AM34 AP31 AM32 AN31 AL34 AN32"),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("AG21 AH24 AJ20 AP20 AL27 AN29 AH33 AN34"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("AH21 AJ25 AK20 AP21 AL28 AP30 AJ33 AP34"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("AE16"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("clk_n", Pins("AE15"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("cke", Pins("AD15"), IOStandard("SSTL12_DCI")),
Subsignal("odt", Pins("AJ18"), IOStandard("SSTL12_DCI")),
Subsignal("reset_n", Pins("AL18"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2")),
Subsignal("rx_n", Pins("AB1")),
Subsignal("tx_p", Pins("AC4")),
Subsignal("tx_n", Pins("AC3"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2")),
Subsignal("rx_n", Pins("AB1 AD1")),
Subsignal("tx_p", Pins("AC4 AE4")),
Subsignal("tx_n", Pins("AC3 AE3"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2")),
Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1")),
Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6")),
Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5"))
),
("pcie_x8", 0,
Subsignal("rst_n", Pins("K22"), IOStandard("LVCMOS18")),
Subsignal("clk_p", Pins("AB6")),
Subsignal("clk_n", Pins("AB5")),
Subsignal("rx_p", Pins("AB2 AD2 AF2 AH2 AJ4 AK2 AM2 AP2")),
Subsignal("rx_n", Pins("AB1 AD1 AF1 AH1 AJ3 AK1 AM1 AP1")),
Subsignal("tx_p", Pins("AC4 AE4 AG4 AH6 AK6 AL4 AM6 AN4")),
Subsignal("tx_n", Pins("AC3 AE3 AG3 AH5 AK5 AL3 AM5 AN3"))
),
# SGMII Clk
("sgmii_clock", 0,
Subsignal("p", Pins("P26"), IOStandard("LVDS_25")),
Subsignal("n", Pins("N26"), IOStandard("LVDS_25"))
),
# SI570
("si570_refclk", 0,
Subsignal("p", Pins("P6")),
Subsignal("n", Pins("P5"))
),
# SMA
("user_sma_mgt_refclk", 0,
Subsignal("p", Pins("V6")),
Subsignal("n", Pins("V5"))
),
("user_sma_mgt_tx", 0,
Subsignal("p", Pins("R4")),
Subsignal("n", Pins("R3"))
),
("user_sma_mgt_rx", 0,
Subsignal("p", Pins("P2")),
Subsignal("n", Pins("P1"))
),
# SFP
("sfp", 0,
Subsignal("txp", Pins("U4")),
Subsignal("txn", Pins("U3")),
Subsignal("rxp", Pins("T2")),
Subsignal("rxn", Pins("T1"))
),
("sfp_tx", 0,
Subsignal("p", Pins("U4")),
Subsignal("n", Pins("U3")),
),
("sfp_rx", 0,
Subsignal("p", Pins("T2")),
Subsignal("n", Pins("T1")),
),
("sfp_tx_disable_n", 0, Pins("AL8"), IOStandard("LVCMOS18")),
("sfp", 1,
Subsignal("txp", Pins("W4")),
Subsignal("txn", Pins("W3")),
Subsignal("rxp", Pins("V2")),
Subsignal("rxn", Pins("V1"))
),
("sfp_tx", 1,
Subsignal("p", Pins("W4")),
Subsignal("n", Pins("W3")),
),
("sfp_rx", 1,
Subsignal("p", Pins("V2")),
Subsignal("n", Pins("V1")),
),
("sfp_tx_disable_n", 1, Pins("D28"), IOStandard("LVCMOS18")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"DP0_C2M_P" : "F6",
"DP0_C2M_N" : "F5",
"DP0_M2C_P" : "E4",
"DP0_M2C_N" : "E3",
"DP1_C2M_P" : "D6",
"DP1_C2M_N" : "D5",
"DP1_M2C_P" : "D2",
"DP1_M2C_N" : "D1",
"DP2_C2M_P" : "C4",
"DP2_C2M_N" : "C3",
"DP2_M2C_P" : "B2",
"DP2_M2C_N" : "B1",
"DP3_C2M_P" : "B6",
"DP3_C2M_N" : "B5",
"DP3_M2C_P" : "A4",
"DP3_M2C_N" : "A3",
"DP4_C2M_P" : "N4",
"DP4_C2M_N" : "N3",
"DP4_M2C_P" : "M2",
"DP4_M2C_N" : "M1",
"DP5_C2M_P" : "J4",
"DP5_C2M_N" : "J3",
"DP5_M2C_P" : "H2",
"DP5_M2C_N" : "H1",
"DP6_C2M_P" : "L4",
"DP6_C2M_N" : "L3",
"DP6_M2C_P" : "K2",
"DP6_M2C_N" : "K1",
"DP7_C2M_P" : "G4",
"DP7_C2M_N" : "G3",
"DP7_M2C_P" : "F2",
"DP7_M2C_N" : "F1",
"LA06_P" : "D13",
"LA06_N" : "C13",
"LA10_P" : "L8",
"LA10_N" : "K8",
"LA14_P" : "B10",
"LA14_N" : "A10",
"LA18_CC_P" : "E22",
"LA18_CC_N" : "E23",
"LA27_P" : "H21",
"LA27_N" : "G21",
"HA01_CC_P" : "E16",
"HA01_CC_N" : "D16",
"HA05_P" : "J15",
"HA05_N" : "J14",
"HA09_P" : "F18",
"HA09_N" : "F17",
"HA13_P" : "B14",
"HA13_N" : "A14",
"HA16_P" : "A19",
"HA16_N" : "A18",
"HA20_P" : "C19",
"HA20_N" : "B19",
"CLK1_M2C_P" : "E25",
"CLK1_M2C_N" : "D25",
"LA00_CC_P" : "H11",
"LA00_CC_N" : "G11",
"LA03_P" : "A13",
"LA03_N" : "A12",
"LA08_P" : "J8",
"LA08_N" : "H8",
"LA12_P" : "E10",
"LA12_N" : "D10",
"LA16_P" : "B9",
"LA16_N" : "A9",
"LA20_P" : "B24",
"LA20_N" : "A24",
"LA22_P" : "G24",
"LA22_N" : "F25",
"LA25_P" : "D20",
"LA25_N" : "D21",
"LA29_P" : "B20",
"LA29_N" : "A20",
"LA31_P" : "B25",
"LA31_N" : "A25",
"LA33_P" : "A27",
"LA33_N" : "A28",
"HA03_P" : "G15",
"HA03_N" : "G14",
"HA07_P" : "L19",
"HA07_N" : "L18",
"HA11_P" : "J19",
"HA11_N" : "J18",
"HA14_P" : "F15",
"HA14_N" : "F14",
"HA18_P" : "B17",
"HA18_N" : "B16",
"HA22_P" : "C18",
"HA22_N" : "C17",
"GBTCLK1_M2C_P" : "H6",
"GBTCLK1_M2C_N" : "H5",
"GBTCLK0_M2C_P" : "K6",
"GBTCLK0_M2C_N" : "K5",
"LA01_CC_P" : "G9",
"LA01_CC_N" : "F9",
"LA05_P" : "L13",
"LA05_N" : "K13",
"LA09_P" : "J9",
"LA09_N" : "H9",
"LA13_P" : "D9",
"LA13_N" : "C9",
"LA17_CC_P" : "D24",
"LA17_CC_N" : "C24",
"LA23_P" : "G22",
"LA23_N" : "F22",
"LA26_P" : "G20",
"LA26_N" : "F20",
"PG_M2C" : "L27",
"HA00_CC_P" : "G17",
"HA00_CC_N" : "G16",
"HA04_P" : "G19",
"HA04_N" : "F19",
"HA08_P" : "K18",
"HA08_N" : "K17",
"HA12_P" : "K16",
"HA12_N" : "J16",
"HA15_P" : "D14",
"HA15_N" : "C14",
"HA19_P" : "D19",
"HA19_N" : "D18",
"PRSNT_M2C_B" : "H24",
"CLK0_M2C_P" : "H12",
"CLK0_M2C_N" : "G12",
"LA02_P" : "K10",
"LA02_N" : "J10",
"LA04_P" : "L12",
"LA04_N" : "K12",
"LA07_P" : "F8",
"LA07_N" : "E8",
"LA11_P" : "K11",
"LA11_N" : "J11",
"LA15_P" : "D8",
"LA15_N" : "C8",
"LA19_P" : "C21",
"LA19_N" : "C22",
"LA21_P" : "F23",
"LA21_N" : "F24",
"LA24_P" : "E20",
"LA24_N" : "E21",
"LA28_P" : "B21",
"LA28_N" : "B22",
"LA30_P" : "C26",
"LA30_N" : "B26",
"LA32_P" : "E26",
"LA32_N" : "D26",
"HA02_P" : "H19",
"HA02_N" : "H18",
"HA06_P" : "L15",
"HA06_N" : "K15",
"HA10_P" : "H17",
"HA10_N" : "H16",
"HA17_CC_P" : "E18",
"HA17_CC_N" : "E17",
"HA21_P" : "E15",
"HA21_N" : "D15",
"HA23_P" : "B15",
"HA23_N" : "A15",
}
),
("LPC", {
"GBTCLK0_M2C_P" : "AA24",
"GBTCLK0_M2C_N" : "AA25",
"LA01_CC_P" : "W25",
"LA01_CC_N" : "Y25",
"LA05_P" : "V27",
"LA05_N" : "V28",
"LA09_P" : "V26",
"LA09_N" : "W26",
"LA13_P" : "AA20",
"LA13_N" : "AB20",
"LA17_CC_P" : "AA32",
"LA17_CC_N" : "AB32",
"LA23_P" : "AD30",
"LA23_N" : "AD31",
"LA26_P" : "AF33",
"LA26_N" : "AG34",
"CLK0_M2C_P" : "AA24",
"CLK0_M2C_N" : "AA25",
"LA02_P" : "AA22",
"LA02_N" : "AB22",
"LA04_P" : "U26",
"LA04_N" : "U27",
"LA07_P" : "V22",
"LA07_N" : "V23",
"LA11_P" : "V21",
"LA11_N" : "W21",
"LA15_P" : "AB25",
"LA15_N" : "AB26",
"LA19_P" : "AA29",
"LA19_N" : "AB29",
"LA21_P" : "AC33",
"LA21_N" : "AD33",
"LA24_P" : "AE32",
"LA24_N" : "AF32",
"LA28_P" : "V31",
"LA28_N" : "W31",
"LA30_P" : "Y31",
"LA30_N" : "Y32",
"LA32_P" : "W30",
"LA32_N" : "Y30",
"LA06_P" : "V29",
"LA06_N" : "W29",
"LA10_P" : "T22",
"LA10_N" : "T23",
"LA14_P" : "U21",
"LA14_N" : "U22",
"LA18_CC_P" : "AB30",
"LA18_CC_N" : "AB31",
"LA27_P" : "AG31",
"LA27_N" : "AG32",
"CLK1_M2C_P" : "AC31",
"CLK1_M2C_N" : "AC32",
"LA00_CC_P" : "W23",
"LA00_CC_N" : "W24",
"LA03_P" : "W28",
"LA03_N" : "Y28",
"LA08_P" : "U24",
"LA08_N" : "U25",
"LA12_P" : "AC22",
"LA12_N" : "AC23",
"LA16_P" : "AB21",
"LA16_N" : "AC21",
"LA20_P" : "AA34",
"LA20_N" : "AB34",
"LA22_P" : "AC34",
"LA22_N" : "AD34",
"LA25_P" : "AE33",
"LA25_N" : "AF34",
"LA29_P" : "U34",
"LA29_N" : "V34",
"LA31_P" : "V33",
"LA31_N" : "W34",
"LA33_P" : "W33",
"LA33_N" : "Y33",
}
),
("pmod0", "AK25 AN21 AH18 AM19 AE26 AF25 AE21 AM17"),
("pmod1", "AL14 AM14 AP16 AP15 AM16 AM15 AN18 AN17"),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-2-e", _io, _connectors, toolchain="vivado")
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 44]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 45]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 46]")
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((18029, 18124), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xcku040-ffva1156-2-e"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xcku040-ffva1156-2-e', _io, _connectors,\n toolchain='vivado')\n", (18052, 18124), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((18170, 18188), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (18186, 18188), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((18235, 18277), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (18261, 18277), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Board diagram/pinout:
# https://user-images.githubusercontent.com/1450143/133655492-532d5e9a-0635-4889-85c9-68683d06cae0.png
# http://dl.sipeed.com/TANG/Nano/HDK/Tang-NANO-2704(Schematic).pdf
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk24", 0, Pins("35"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("16"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("17"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("18"), IOStandard("LVCMOS33")),
# Buttons.
("user_btn", 0, Pins("15"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("14"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("8")),
Subsignal("rx", Pins("9")),
IOStandard("LVCMOS33")
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):
default_clk_name = "clk24"
default_clk_period = 1e9/24e6
def __init__(self):
GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, _connectors, toolchain="gowin", devicename="GW1N-1")
self.toolchain.options["use_done_as_gpio"] = 1
def create_programmer(self):
return OpenFPGALoader("tangnano")
def do_finalize(self, fragment):
GowinPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
| [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((1481, 1592), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-LV1QN48C6/I5"""', '_io', '_connectors'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1N-1"""'}), "(self, 'GW1N-LV1QN48C6/I5', _io, _connectors,\n toolchain='gowin', devicename='GW1N-1')\n", (1503, 1592), False, 'from litex.build.gowin.platform import GowinPlatform\n'), ((1693, 1719), 'litex.build.openfpgaloader.OpenFPGALoader', 'OpenFPGALoader', (['"""tangnano"""'], {}), "('tangnano')\n", (1707, 1719), False, 'from litex.build.openfpgaloader import OpenFPGALoader\n'), ((1766, 1807), 'litex.build.gowin.platform.GowinPlatform.do_finalize', 'GowinPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1791, 1807), False, 'from litex.build.gowin.platform import GowinPlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 msloniewski <<EMAIL>>
# Copyright (c) 2019 vytautasb <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import subprocess
import sys
import math
from shutil import which
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import Pins, IOStandard, Misc
from litex.build import tools
# IO/Placement Constraints (.qsf) ------------------------------------------------------------------
def _format_constraint(c, signame, fmt_r):
# IO location constraints
if isinstance(c, Pins):
tpl = "set_location_assignment -comment \"{name}\" -to {signame} Pin_{pin}"
return tpl.format(signame=signame, name=fmt_r, pin=c.identifiers[0])
# IO standard constraints
elif isinstance(c, IOStandard):
tpl = "set_instance_assignment -name io_standard -comment \"{name}\" \"{std}\" -to {signame}"
return tpl.format(signame=signame, name=fmt_r, std=c.name)
# Others constraints
elif isinstance(c, Misc):
if not isinstance(c.misc, str) and len(c.misc) == 2:
tpl = "set_instance_assignment -comment \"{name}\" -name {misc[0]} \"{misc[1]}\" -to {signame}"
return tpl.format(signame=signame, name=fmt_r, misc=c.misc)
else:
tpl = "set_instance_assignment -comment \"{name}\" -name {misc} -to {signame}"
return tpl.format(signame=signame, name=fmt_r, misc=c.misc)
def _format_qsf_constraint(signame, pin, others, resname):
fmt_r = "{}:{}".format(*resname[:2])
if resname[2] is not None:
fmt_r += "." + resname[2]
fmt_c = [_format_constraint(c, signame, fmt_r) for c in ([Pins(pin)] + others)]
return '\n'.join(fmt_c)
def _build_qsf_constraints(named_sc, named_pc):
qsf = []
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
qsf.append(_format_qsf_constraint("{}[{}]".format(sig, i), p, others, resname))
else:
qsf.append(_format_qsf_constraint(sig, pins[0], others, resname))
if named_pc:
qsf.append("\n\n".join(named_pc))
return "\n".join(qsf)
# Timing Constraints (.sdc) ------------------------------------------------------------------------
def _build_sdc(clocks, false_paths, vns, named_sc, build_name, additional_sdc_commands):
sdc = []
# Clock constraints
for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
is_port = False
for sig, pins, others, resname in named_sc:
if sig == vns.get_name(clk):
is_port = True
if is_port:
tpl = "create_clock -name {clk} -period {period} [get_ports {{{clk}}}]"
sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
else:
tpl = "create_clock -name {clk} -period {period} [get_nets {{{clk}}}]"
sdc.append(tpl.format(clk=vns.get_name(clk), period=str(period)))
# False path constraints
for from_, to in sorted(false_paths, key=lambda x: (x[0].duid, x[1].duid)):
tpl = "set_false_path -from [get_clocks {{{from_}}}] -to [get_clocks {{{to}}}]"
sdc.append(tpl.format(from_=vns.get_name(from_), to=vns.get_name(to)))
# Add additional commands
sdc += additional_sdc_commands
# Generate .sdc
tools.write_to_file("{}.sdc".format(build_name), "\n".join(sdc))
# Project (.qsf) -----------------------------------------------------------------------------------
def _build_qsf(device, ips, sources, vincpaths, named_sc, named_pc, build_name, additional_qsf_commands):
qsf = []
# Set device
qsf.append("set_global_assignment -name DEVICE {}".format(device))
# Add sources
for filename, language, library in sources:
if language == "verilog": language = "systemverilog" # Enforce use of SystemVerilog
tpl = "set_global_assignment -name {lang}_FILE {path} -library {lib}"
# Do not add None type files
if language is not None:
qsf.append(tpl.format(lang=language.upper(), path=filename.replace("\\", "/"), lib=library))
# Check if the file is a header. Those should not be explicitly added to qsf,
# but rather included in include search_path
else:
if filename.endswith(".svh") or filename.endswith(".vh"):
fpath = os.path.dirname(filename)
if fpath not in vincpaths:
vincpaths.append(fpath)
# Add ips
for filename in ips:
tpl = "set_global_assignment -name QSYS_FILE {filename}"
qsf.append(tpl.replace(filename=filename.replace("\\", "/")))
# Add include paths
for path in vincpaths:
qsf.append("set_global_assignment -name SEARCH_PATH {}".format(path.replace("\\", "/")))
# Set top level
qsf.append("set_global_assignment -name top_level_entity " + build_name)
# Add io, placement constraints
qsf.append(_build_qsf_constraints(named_sc, named_pc))
# Set timing constraints
qsf.append("set_global_assignment -name SDC_FILE {}.sdc".format(build_name))
# Add additional commands
qsf += additional_qsf_commands
# Generate .qsf
tools.write_to_file("{}.qsf".format(build_name), "\n".join(qsf))
# Script -------------------------------------------------------------------------------------------
def _build_script(build_name, create_rbf):
if sys.platform in ["win32", "cygwin"]:
script_contents = "REM Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
script_file = "build_" + build_name + ".bat"
else:
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
script_file = "build_" + build_name + ".sh"
script_contents += """
quartus_map --read_settings_files=on --write_settings_files=off {build_name} -c {build_name}
quartus_fit --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_asm --read_settings_files=off --write_settings_files=off {build_name} -c {build_name}
quartus_sta {build_name} -c {build_name}"""
if create_rbf:
script_contents += """
if [ -f "{build_name}.sof" ]
then
quartus_cpf -c {build_name}.sof {build_name}.rbf
fi
"""
script_contents = script_contents.format(build_name=build_name)
tools.write_to_file(script_file, script_contents, force_unix=True)
return script_file
def _run_script(script):
if sys.platform in ["win32", "cygwin"]:
shell = ["cmd", "/c"]
else:
shell = ["bash"]
if which("quartus_map") is None:
msg = "Unable to find Quartus toolchain, please:\n"
msg += "- Add Quartus toolchain to your $PATH."
raise OSError(msg)
if subprocess.call(shell + [script]) != 0:
raise OSError("Error occured during Quartus's script execution.")
# AlteraQuartusToolchain ---------------------------------------------------------------------------
class AlteraQuartusToolchain:
attr_translate = {}
def __init__(self):
self.clocks = dict()
self.false_paths = set()
self.additional_sdc_commands = []
self.additional_qsf_commands = []
def build(self, platform, fragment,
build_dir = "build",
build_name = "top",
run = True,
**kwargs):
# Create build directory
cwd = os.getcwd()
os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir)
# Finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# Generate verilog
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
platform.add_source(v_file)
# Generate design timing constraints file (.sdc)
_build_sdc(
clocks = self.clocks,
false_paths = self.false_paths,
vns = v_output.ns,
named_sc = named_sc,
build_name = build_name,
additional_sdc_commands = self.additional_sdc_commands)
# Generate design project and location constraints file (.qsf)
_build_qsf(
device = platform.device,
ips = platform.ips,
sources = platform.sources,
vincpaths = platform.verilog_include_paths,
named_sc = named_sc,
named_pc = named_pc,
build_name = build_name,
additional_qsf_commands = self.additional_qsf_commands)
# Generate build script
script = _build_script(build_name, platform.create_rbf)
# Run
if run:
_run_script(script)
os.chdir(cwd)
return v_output.ns
def add_period_constraint(self, platform, clk, period):
clk.attr.add("keep")
period = math.floor(period*1e3)/1e3 # round to lowest picosecond
if clk in self.clocks:
if period != self.clocks[clk]:
raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
.format(self.clocks[clk], period))
self.clocks[clk] = period
def add_false_path_constraint(self, platform, from_, to):
from_.attr.add("keep")
to.attr.add("keep")
if (to, from_) not in self.false_paths:
self.false_paths.add((from_, to))
| [
"litex.build.tools.get_litex_git_revision",
"litex.build.generic_platform.Pins",
"litex.build.tools.write_to_file"
] | [((6393, 6459), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(True)'}), '(script_file, script_contents, force_unix=True)\n', (6412, 6459), False, 'from litex.build import tools\n'), ((6627, 6647), 'shutil.which', 'which', (['"""quartus_map"""'], {}), "('quartus_map')\n", (6632, 6647), False, 'from shutil import which\n'), ((6808, 6841), 'subprocess.call', 'subprocess.call', (['(shell + [script])'], {}), '(shell + [script])\n', (6823, 6841), False, 'import subprocess\n'), ((7460, 7471), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (7469, 7471), False, 'import os\n'), ((7480, 7517), 'os.makedirs', 'os.makedirs', (['build_dir'], {'exist_ok': '(True)'}), '(build_dir, exist_ok=True)\n', (7491, 7517), False, 'import os\n'), ((7526, 7545), 'os.chdir', 'os.chdir', (['build_dir'], {}), '(build_dir)\n', (7534, 7545), False, 'import os\n'), ((9088, 9101), 'os.chdir', 'os.chdir', (['cwd'], {}), '(cwd)\n', (9096, 9101), False, 'import os\n'), ((5584, 5614), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (5612, 5614), False, 'from litex.build import tools\n'), ((5741, 5771), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (5769, 5771), False, 'from litex.build import tools\n'), ((9237, 9264), 'math.floor', 'math.floor', (['(period * 1000.0)'], {}), '(period * 1000.0)\n', (9247, 9264), False, 'import math\n'), ((4431, 4456), 'os.path.dirname', 'os.path.dirname', (['filename'], {}), '(filename)\n', (4446, 4456), False, 'import os\n'), ((1721, 1730), 'litex.build.generic_platform.Pins', 'Pins', (['pin'], {}), '(pin)\n', (1725, 1730), False, 'from litex.build.generic_platform import Pins, IOStandard, Misc\n')] |
#!/usr/bin/env python3
import time
from statistics import mean
from litex import RemoteClient
wb = RemoteClient(csr_csv="test/csr.csv")
wb.open()
# # #
# Read frequency meter
fmeter_values = []
print("Reading frequency...")
for i in range(100):
fmeter_value = wb.regs.fmeter_value.read()
print(fmeter_value)
fmeter_values.append(fmeter_value)
time.sleep(1.0)
print(f'average: {mean(fmeter_values)}')
| [
"litex.RemoteClient"
] | [((102, 138), 'litex.RemoteClient', 'RemoteClient', ([], {'csr_csv': '"""test/csr.csv"""'}), "(csr_csv='test/csr.csv')\n", (114, 138), False, 'from litex import RemoteClient\n'), ((364, 379), 'time.sleep', 'time.sleep', (['(1.0)'], {}), '(1.0)\n', (374, 379), False, 'import time\n'), ((398, 417), 'statistics.mean', 'mean', (['fmeter_values'], {}), '(fmeter_values)\n', (402, 417), False, 'from statistics import mean\n')] |
from axil_cdc import AxilCDC
from axilite2bft import AxiLite2Bft
from bft import Bft
from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface
from litex.soc.interconnect.stream import (ClockDomainCrossing, Converter,
Endpoint)
from migen import *
from pld_axi import *
class Leaf(Module):
def __init__(self, clk, rst, start, platform):
self.platform = platform
self.clk = clk
self.reset = rst
self.start = start
self.resend = 0
self.din_leaf_bft2interface_1 = Signal(49, name="din_leaf_bft2interface_1")
self.dout_leaf_interface2bft_1 = Signal(49, name="dout_leaf_interface2bft_1")
self.din_leaf_bft2interface_2 = Signal(49, name="din_leaf_bft2interface_2")
self.dout_leaf_interface2bft_2 = Signal(49, name="dout_leaf_interface2bft_2")
def connect_input(self, din, dout):
self.comb += self.din_leaf_bft2interface_1.eq(din)
self.comb += dout.eq(self.dout_leaf_interface2bft_1)
def connect_output(self, din, dout):
self.comb += self.din_leaf_bft2interface_2.eq(din)
self.comb += dout.eq(self.dout_leaf_interface2bft_2)
class Leaf2(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_2",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class Leaf3(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_3",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class Leaf4(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_4",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class Leaf5(Leaf):
def __init__(self, clk, rst, start, platform):
super().__init__(clk, rst, start, platform)
self.specials += Instance(
"leaf_5",
i_clk=self.clk,
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
i_start=self.start,
i_resend=self.resend,
i_reset=self.reset,
)
class InterfaceWrapperLeafOnly(Module):
def __init__(self, clk, rst, platform, clock_domain="bft"):
self.source = PldAXIStreamInterface(data_width=32)
self.sink = PldAXIStreamInterface(data_width=32)
self.clk = clk
self.rst = rst
self.resend = Signal(1, name="resend")
self.din_leaf_bft2interface_1 = Signal(49, name="din_leaf_bft2interface_1")
self.dout_leaf_interface2bft_1 = Signal(49, name="dout_leaf_interface2bft_1")
self.din_leaf_bft2interface_2 = Signal(49, name="din_leaf_bft2interface_2")
self.dout_leaf_interface2bft_2 = Signal(49, name="dout_leaf_interface2bft_2")
self.platform = platform
source_sigs = self.source.get_signals()
sink_sigs = self.sink.get_signals()
self.specials += Instance(
"InterfaceWrapperLeafOnly",
i_clk=self.clk,
i_reset=self.rst,
i_resend=self.resend,
# bft interface
i_din_leaf_bft2interface_1=self.din_leaf_bft2interface_1,
o_dout_leaf_interface2bft_1=self.dout_leaf_interface2bft_1,
i_din_leaf_bft2interface_2=self.din_leaf_bft2interface_2,
o_dout_leaf_interface2bft_2=self.dout_leaf_interface2bft_2,
# stream interface
i_Input_1_V_V=sink_sigs["tpayload"].data,
i_Input_1_V_V_ap_vld=sink_sigs["tvalid"],
o_Input_1_V_V_ap_ack=sink_sigs["tready"],
o_Output_1_V_V=source_sigs["tpayload"].data,
o_Output_1_V_V_ap_vld=source_sigs["tvalid"],
i_Output_1_V_V_ap_ack=source_sigs["tready"],
)
def connect_input(self, stream):
assert isinstance(stream, Endpoint)
assert stream.payload.data.nbits == 32
self.comb += stream.connect(self.sink)
def connect_output(self, stream):
assert isinstance(stream, Endpoint)
assert stream.payload.data.nbits == 32
self.comb += self.source.connect(stream)
class RenderingLeafOnly(Module):
def __init__(self, clk, rst, platform, start=1, clock_domain="bft"):
self.axil = AXILiteInterface(
data_width=32, address_width=5, clock_domain=clock_domain
)
self.clk = clk
self.rst = rst
self.start = start
self.platform = platform
self.clock_domain = clock_domain
self.submodules.interface_wrapper = (
interface_wrapper
) = InterfaceWrapperLeafOnly(clk, rst, platform)
self.submodules.leaf_2 = leaf_2 = Leaf2(clk, rst, start, platform)
self.submodules.leaf_3 = leaf_3 = Leaf3(clk, rst, start, platform)
self.submodules.leaf_4 = leaf_4 = Leaf4(clk, rst, start, platform)
self.submodules.leaf_5 = leaf_5 = Leaf5(clk, rst, start, platform)
data_1 = Signal(49)
data_2 = Signal(49)
data_3 = Signal(49)
data_4 = Signal(49)
data_5 = Signal(49)
data_6 = Signal(49)
data_7 = Signal(49)
data_8 = Signal(49)
data_9 = Signal(49)
data_a = Signal(49)
# interface_wrapper
self.comb += data_1.eq(interface_wrapper.dout_leaf_interface2bft_1)
self.comb += interface_wrapper.din_leaf_bft2interface_1.eq(data_3)
self.comb += data_2.eq(interface_wrapper.dout_leaf_interface2bft_2)
self.comb += interface_wrapper.din_leaf_bft2interface_2.eq(data_4)
# self.comb += interface_wrapper.din_leaf_bft2interface_2.eq(interface_wrapper.dout_leaf_interface2bft_1)
# self.comb += interface_wrapper.din_leaf_bft2interface_1.eq(interface_wrapper.dout_leaf_interface2bft_2)
self.comb += interface_wrapper.resend.eq(0)
# leaves
leaf_2.connect_input(data_1, data_3)
leaf_2.connect_output(data_5, data_6)
leaf_3.connect_input(data_6, data_5)
leaf_3.connect_output(data_7, data_8)
leaf_4.connect_input(data_8, data_7)
leaf_4.connect_output(data_9, data_a)
leaf_5.connect_input(data_a, data_9)
leaf_5.connect_output(data_2, data_4)
self.platform.add_source_dir("rtl/leaf_interface/")
self.platform.add_source_dir("rtl/rendering_leaf_only/")
self.platform.add_source("rtl/SynFIFO.v")
def connect_input(self, stream, clock_domain="sys"):
assert isinstance(stream, Endpoint)
input_stream = stream
# if clock_domain != self.clock_domain:
# from IPython import embed; embed()
# self.submodules.input_cross_domain_converter = input_cross_domain_converter = \
# ClockDomainCrossing(input_stream.description, cd_from=clock_domain, cd_to=self.clock_domain, depth=8)
# mm2s_axis_bft = AXIStreamInterface(32)
# self.comb += input_stream.connect(input_cross_domain_converter.sink)
# self.comb += input_cross_domain_converter.source.connect(mm2s_axis_bft)
# input_stream = mm2s_axis_bft
self.interface_wrapper.connect_input(input_stream)
def connect_output(self, stream, clock_domain="sys"):
assert isinstance(stream, Endpoint)
output_stream = stream
# if clock_domain != self.clock_domain:
# from IPython import embed; embed()
# self.submodules.output_cross_domain_converter = output_cross_domain_converter = \
# ClockDomainCrossing(output_stream.description, cd_from=self.clock_domain, cd_to=clock_domain, depth=8)
# s2mm_axis_bft = AXIStreamInterface(32)
# self.comb += output_cross_domain_converter.source.connect(output_stream)
# self.comb += s2mm_axis_bft.connect(output_cross_domain_converter.sink)
# output_stream = s2mm_axis_bft
self.interface_wrapper.connect_output(output_stream)
| [
"litex.soc.interconnect.axi.AXILiteInterface"
] | [((5719, 5794), 'litex.soc.interconnect.axi.AXILiteInterface', 'AXILiteInterface', ([], {'data_width': '(32)', 'address_width': '(5)', 'clock_domain': 'clock_domain'}), '(data_width=32, address_width=5, clock_domain=clock_domain)\n', (5735, 5794), False, 'from litex.soc.interconnect.axi import AXILiteInterface, AXIStreamInterface\n')] |
from litex.tools.litex_client import RemoteClient
wb = RemoteClient("192.168.1.50", 1234, csr_data_width=8)
wb.open()
regs = wb.regs
# # #
print("temperature: %f°C" %(regs.xadc_temperature.read()*503.975/4096 - 273.15))
print("vccint: %fV" %(regs.xadc_vccint.read()/4096*3))
print("vccaux: %fV" %(regs.xadc_vccaux.read()/4096*3))
print("vccbram: %fV" %(regs.xadc_vccbram.read()/4096*3))
# # #
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((56, 108), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', (['"""192.168.1.50"""', '(1234)'], {'csr_data_width': '(8)'}), "('192.168.1.50', 1234, csr_data_width=8)\n", (68, 108), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import csv
import logging
import argparse
from operator import and_
from functools import reduce
from itertools import zip_longest
from migen import *
from migen.genlib.misc import WaitTimer
from litex.build.sim.config import SimConfig
from litex.soc.interconnect.csr import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litex.tools.litex_sim import SimSoC
from litedram.frontend.bist import _LiteDRAMBISTGenerator, _LiteDRAMBISTChecker, \
_LiteDRAMPatternGenerator, _LiteDRAMPatternChecker
# LiteDRAM Benchmark SoC ---------------------------------------------------------------------------
class LiteDRAMBenchmarkSoC(SimSoC):
def __init__(self,
sdram_module = "MT48LC16M16",
sdram_data_width = 32,
bist_base = 0x0000000,
bist_end = 0x0100000,
bist_length = 1024,
bist_random = False,
bist_alternating = False,
num_generators = 1,
num_checkers = 1,
pattern_init = None,
**kwargs):
# SimSoC -----------------------------------------------------------------------------------
SimSoC.__init__(self,
with_sdram = True,
sdram_module = sdram_module,
sdram_data_width = sdram_data_width,
**kwargs
)
# BIST Generator / Checker -----------------------------------------------------------------
# make sure that we perform at least one access
bist_length = max(bist_length, self.sdram.controller.interface.data_width // 8)
custom_pattern_mode = pattern_init is not None
if custom_pattern_mode:
make_generator = lambda: _LiteDRAMPatternGenerator(self.sdram.crossbar.get_port(), init=pattern_init)
make_checker = lambda: _LiteDRAMPatternChecker(self.sdram.crossbar.get_port(), init=pattern_init)
else:
make_generator = lambda: _LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
make_checker = lambda: _LiteDRAMBISTChecker(self.sdram.crossbar.get_port())
generators = [make_generator() for _ in range(num_generators)]
checkers = [make_checker() for _ in range(num_checkers)]
self.submodules += generators + checkers
if custom_pattern_mode:
def bist_config(module):
return []
if not bist_alternating:
address_set = set()
for addr, _ in pattern_init:
assert addr not in address_set, \
'Duplicate address 0x%08x in pattern_init, write will overwrite previous value!' % addr
address_set.add(addr)
else:
def bist_config(module):
return [
module.base.eq(bist_base),
module.end.eq(bist_end),
module.length.eq(bist_length),
module.random_addr.eq(bist_random),
]
assert not (bist_random and not bist_alternating), \
'Write to random address may overwrite previously written data before reading!'
# check address correctness
assert bist_end > bist_base
assert bist_end <= 2**(len(generators[0].end)) - 1, 'End address outside of range'
bist_addr_range = bist_end - bist_base
assert bist_addr_range > 0 and bist_addr_range & (bist_addr_range - 1) == 0, \
'Length of the address range must be a power of 2'
def combined_read(modules, signal, operator):
sig = Signal()
self.comb += sig.eq(reduce(operator, (getattr(m, signal) for m in modules)))
return sig
def combined_write(modules, signal):
sig = Signal()
self.comb += [getattr(m, signal).eq(sig) for m in modules]
return sig
# Sequencer --------------------------------------------------------------------------------
class LiteDRAMCoreControl(Module, AutoCSR):
def __init__(self):
self.init_done = CSRStorage()
self.init_error = CSRStorage()
self.submodules.ddrctrl = ddrctrl = LiteDRAMCoreControl()
self.add_csr("ddrctrl")
display = Signal()
finish = Signal()
self.submodules.fsm = fsm = FSM(reset_state="WAIT-INIT")
fsm.act("WAIT-INIT",
If(self.ddrctrl.init_done.storage, # Written by CPU when initialization is done
NextState("BIST-GENERATOR")
)
)
if bist_alternating:
# force generators to wait for checkers and vice versa
# connect them in pairs, with each unpaired connected to the first of the others
bist_connections = []
for generator, checker in zip_longest(generators, checkers):
g = generator or generators[0]
c = checker or checkers[0]
bist_connections += g.run.eq(c.ready), c.run.eq(g.ready)
fsm.act("BIST-GENERATOR",
combined_write(generators + checkers, 'start').eq(1),
*bist_connections,
*map(bist_config, generators + checkers),
If(combined_read(checkers, 'done', and_),
NextState("DISPLAY")
)
)
else:
fsm.act("BIST-GENERATOR",
combined_write(generators, 'start').eq(1),
combined_write(generators, 'run').eq(1),
*map(bist_config, generators),
If(combined_read(generators, 'done', and_),
NextState("BIST-CHECKER")
)
)
fsm.act("BIST-CHECKER",
combined_write(checkers, 'start').eq(1),
combined_write(checkers, 'run').eq(1),
*map(bist_config, checkers),
If(combined_read(checkers, 'done', and_),
NextState("DISPLAY")
)
)
fsm.act("DISPLAY",
display.eq(1),
NextState("FINISH")
)
fsm.act("FINISH",
finish.eq(1)
)
# Simulation Results -----------------------------------------------------------------------
def max_signal(signals):
signals = iter(signals)
s = next(signals)
out = Signal(len(s))
self.comb += out.eq(s)
for curr in signals:
prev = out
out = Signal(max(len(prev), len(curr)))
self.comb += If(prev > curr, out.eq(prev)).Else(out.eq(curr))
return out
generator_ticks = max_signal((g.ticks for g in generators))
checker_errors = max_signal((c.errors for c in checkers))
checker_ticks = max_signal((c.ticks for c in checkers))
self.sync += [
If(display,
Display("BIST-GENERATOR ticks: %08d", generator_ticks),
Display("BIST-CHECKER errors: %08d", checker_errors),
Display("BIST-CHECKER ticks: %08d", checker_ticks),
)
]
# Simulation End ---------------------------------------------------------------------------
end_timer = WaitTimer(2**16)
self.submodules += end_timer
self.comb += end_timer.wait.eq(finish)
self.sync += If(end_timer.done, Finish())
# Build --------------------------------------------------------------------------------------------
def load_access_pattern(filename):
with open(filename, newline='') as f:
reader = csv.reader(f)
pattern_init = [(int(addr, 0), int(data, 0)) for addr, data in reader]
return pattern_init
def main():
parser = argparse.ArgumentParser(description="LiteDRAM Benchmark SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O0", help="Compilation optimization level")
parser.add_argument("--bist-base", default="0x00000000", help="Base address of the test (default=0)")
parser.add_argument("--bist-length", default="1024", help="Length of the test (default=1024)")
parser.add_argument("--bist-random", action="store_true", help="Use random data during the test")
parser.add_argument("--bist-alternating", action="store_true", help="Perform alternating writes/reads (WRWRWR... instead of WWW...RRR...)")
parser.add_argument("--num-generators", default=1, help="Number of BIST generators")
parser.add_argument("--num-checkers", default=1, help="Number of BIST checkers")
parser.add_argument("--access-pattern", help="Load access pattern (address, data) from CSV (ignores --bist-*)")
parser.add_argument("--log-level", default="info", help="Set logging verbosity",
choices=['critical', 'error', 'warning', 'info', 'debug'])
args = parser.parse_args()
root_logger = logging.getLogger()
root_logger.setLevel(getattr(logging, args.log_level.upper()))
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
# Configuration --------------------------------------------------------------------------------
soc_kwargs["with_uart"] = False
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
soc_kwargs["bist_base"] = int(args.bist_base, 0)
soc_kwargs["bist_length"] = int(args.bist_length, 0)
soc_kwargs["bist_random"] = args.bist_random
soc_kwargs["bist_alternating"] = args.bist_alternating
soc_kwargs["num_generators"] = int(args.num_generators)
soc_kwargs["num_checkers"] = int(args.num_checkers)
if args.access_pattern:
soc_kwargs["pattern_init"] = load_access_pattern(args.access_pattern)
# SoC ------------------------------------------------------------------------------------------
soc = LiteDRAMBenchmarkSoC(**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(
threads = args.threads,
sim_config = sim_config,
opt_level = args.opt_level,
trace = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end)
)
if __name__ == "__main__":
main()
| [
"litex.tools.litex_sim.SimSoC.__init__",
"litex.build.sim.config.SimConfig"
] | [((7932, 8004), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteDRAM Benchmark SoC Simulation"""'}), "(description='LiteDRAM Benchmark SoC Simulation')\n", (7955, 8004), False, 'import argparse\n'), ((9954, 9973), 'logging.getLogger', 'logging.getLogger', ([], {}), '()\n', (9971, 9973), False, 'import logging\n'), ((10148, 10180), 'litex.build.sim.config.SimConfig', 'SimConfig', ([], {'default_clk': '"""sys_clk"""'}), "(default_clk='sys_clk')\n", (10157, 10180), False, 'from litex.build.sim.config import SimConfig\n'), ((1276, 1390), 'litex.tools.litex_sim.SimSoC.__init__', 'SimSoC.__init__', (['self'], {'with_sdram': '(True)', 'sdram_module': 'sdram_module', 'sdram_data_width': 'sdram_data_width'}), '(self, with_sdram=True, sdram_module=sdram_module,\n sdram_data_width=sdram_data_width, **kwargs)\n', (1291, 1390), False, 'from litex.tools.litex_sim import SimSoC\n'), ((7440, 7458), 'migen.genlib.misc.WaitTimer', 'WaitTimer', (['(2 ** 16)'], {}), '(2 ** 16)\n', (7449, 7458), False, 'from migen.genlib.misc import WaitTimer\n'), ((7788, 7801), 'csv.reader', 'csv.reader', (['f'], {}), '(f)\n', (7798, 7801), False, 'import csv\n'), ((4976, 5009), 'itertools.zip_longest', 'zip_longest', (['generators', 'checkers'], {}), '(generators, checkers)\n', (4987, 5009), False, 'from itertools import zip_longest\n')] |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
rom_base = 0x00000000
dump_size = 0x8000
words_per_packet = 128
wb = RemoteClient()
wb.open()
# # #
print("dumping cpu rom to dump.bin...")
dump = []
for n in range(dump_size//(words_per_packet*4)):
dump += wb.read(rom_base + n*words_per_packet*4, words_per_packet)
f = open("dump.bin", "wb")
for v in dump:
f.write(v.to_bytes(4, byteorder="big"))
f.close()
# # #
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((144, 158), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (156, 158), False, 'from litex.tools.litex_client import RemoteClient\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020-21 gatecat <<EMAIL>>
#
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex_boards.platforms import crosslink_nx_vip
from litex_boards.platforms import crosslink_nx_vip
from litehyperbus.core.hyperbus import HyperRAM
from litex.soc.cores.ram import NXLRAM
from litex.soc.cores.spi_flash import SpiFlash
from litex.build.io import CRG
from litex.build.generic_platform import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.freqmeter import FreqMeter
from litex.soc.cores.gpio import GPIOIn
from litex.build.lattice.oxide import oxide_args, oxide_argdict
from dphy_wrapper import DPHY_CSIRX_CIL
from mipi_csi import *
kB = 1024
mB = 1024*kB
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain()
# TODO: replace with PLL
# Clocking
self.submodules.sys_clk = sys_osc = NXOSCA()
sys_osc.create_hf_clk(self.cd_sys, sys_clk_freq)
platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
# use cam_reset here because it's also hardwired to the reset of the cameras
rst_n = platform.request("cam_reset")
# Power On Reset
por_cycles = 4096
por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0) | self.rst)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x40000000,
"main_ram": 0x50000000,
"csr": 0xf0000000,
}
def __init__(self, sys_clk_freq=int(75e6), hyperram="none", toolchain="radiant", **kwargs):
platform = crosslink_nx_vip.Platform(toolchain=toolchain)
platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}")
# Disable Integrated SRAM since we want to instantiate LRAM specifically for it
kwargs["integrated_sram_size"] = 0
# SoCCore -----------------------------------------_----------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Crosslink-NX VIP Input Board",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# 128KB LRAM (used as SRAM) ------------------------------------------------------------
size = 128*kB
self.submodules.spram = NXLRAM(32, size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
# Use HyperRAM generic PHY as main ram -----------------------------------------------------
size = 8*1024*kB
hr_pads = platform.request("hyperram", 0)
self.submodules.hyperram = HyperRAM(hr_pads)
self.register_mem("main_ram", self.mem_map["main_ram"], self.hyperram.bus, size)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
refclk = platform.request("clk27_0")
cam_mclk = platform.request("camera_mclk", 0)
self.comb += cam_mclk.eq(refclk)
self.submodules.i2c = I2CMaster(platform.request("i2c", 0))
self.add_csr("i2c")
self.submodules.dphy = DPHY_CSIRX_CIL(
pads = platform.request("camera", 0),
num_lanes = 4,
clk_mode = "ENABLED",
deskew = "DISABLED",
gearing = 8,
loc = "TDPHY_CORE2",
)
self.comb += [
self.dphy.sync_clk.eq(ClockSignal()),
self.dphy.sync_rst.eq(ResetSignal()),
self.dphy.pd_dphy.eq(0),
self.dphy.hs_rx_en.eq(1),
]
self.submodules.clk_byte_freq = FreqMeter(period=sys_clk_freq, clk=self.dphy.clk_byte)
self.add_csr("clk_byte_freq")
self.submodules.hs_rx_data = GPIOIn(pads=self.dphy.hs_rx_data)
self.add_csr("hs_rx_data")
self.submodules.hs_rx_sync = GPIOIn(pads=self.dphy.hs_rx_sync)
self.add_csr("hs_rx_sync")
self.clock_domains.cd_mipi = ClockDomain()
self.comb += self.cd_mipi.clk.eq(self.dphy.clk_byte)
dphy_header = Signal(32)
for i in range(0, 4):
prev_sync = Signal()
self.sync.mipi += prev_sync.eq(self.dphy.hs_rx_sync[i])
self.sync.mipi += If(prev_sync, dphy_header[(8*i):(8*(i+1))].eq(self.dphy.hs_rx_data[(8*i):(8*(i+1))]))
self.submodules.dphy_header = GPIOIn(pads=dphy_header)
self.add_csr("dphy_header")
wa = WordAligner(lane_width=8, num_lanes=4, depth=3)
swapped_data = Cat(self.dphy.hs_rx_data[24:32], self.dphy.hs_rx_data[8:16], self.dphy.hs_rx_data[16:24], self.dphy.hs_rx_data[0:8])
self.sync.mipi += [
wa.data_in.eq(swapped_data),
wa.sync_in.eq(self.dphy.hs_rx_sync)
]
self.submodules.wa = wa
packet_cap = PacketCapture(data=wa.data_out, data_sync=wa.sync_out, depth=128)
self.submodules.packet_cap = packet_cap
packet_io = wishbone.SRAM(self.packet_cap.mem, read_only=True)
self.submodules.packet_io = packet_io
self.register_mem("packet_io", 0xb0000000, packet_io.bus, size=0x4000)
image_cap = ImageCapture(data=wa.data_out, data_sync=wa.sync_out, subsample_x=10, subsample_y=32, out_width=60, out_height=33)
self.submodules.image_cap = image_cap
image_io = wishbone.SRAM(self.image_cap.mem, read_only=True)
self.submodules.image_io = image_io
self.register_mem("image_io", 0xb0010000, image_io.bus, size=0x4000)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--toolchain", default="radiant", help="FPGA toolchain: radiant (default) or prjoxide")
parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)")
parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1")
parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash")
builder_args(parser)
oxide_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
hyperram = args.with_hyperram,
toolchain = args.toolchain,
cpu_type = "picorv32",
cpu_variant = "minimal",
integrated_rom_size = 32768,
)
builder = Builder(soc, **builder_argdict(args))
builder_kargs = oxide_argdict(args) if args.toolchain == "oxide" else {}
builder.build(**builder_kargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.prog_target)
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.wishbone.SRAM",
"litex.build.lattice.oxide.oxide_args",
"litex.soc.cores.ram.NXLRAM",
"litex.soc.cores.freqmeter.FreqMeter",
"litex.soc.cores.gpio.GPIOIn",
"litex.build.lattice.oxide.oxide_argdict"
] | [((7015, 7089), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Crosslink-NX VIP Board"""'}), "(description='LiteX SoC on Crosslink-NX VIP Board')\n", (7038, 7089), False, 'import argparse\n'), ((7766, 7784), 'litex.build.lattice.oxide.oxide_args', 'oxide_args', (['parser'], {}), '(parser)\n', (7776, 7784), False, 'from litex.build.lattice.oxide import oxide_args, oxide_argdict\n'), ((2100, 2143), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_por', '(~rst_n)'], {}), '(self.cd_por, ~rst_n)\n', (2122, 2143), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2169, 2235), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_sys', '((por_counter != 0) | self.rst)'], {}), '(self.cd_sys, (por_counter != 0) | self.rst)\n', (2191, 2235), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((2669, 2715), 'litex_boards.platforms.crosslink_nx_vip.Platform', 'crosslink_nx_vip.Platform', ([], {'toolchain': 'toolchain'}), '(toolchain=toolchain)\n', (2694, 2715), False, 'from litex_boards.platforms import crosslink_nx_vip\n'), ((3535, 3551), 'litex.soc.cores.ram.NXLRAM', 'NXLRAM', (['(32)', 'size'], {}), '(32, size)\n', (3541, 3551), False, 'from litex.soc.cores.ram import NXLRAM\n'), ((3841, 3858), 'litehyperbus.core.hyperbus.HyperRAM', 'HyperRAM', (['hr_pads'], {}), '(hr_pads)\n', (3849, 3858), False, 'from litehyperbus.core.hyperbus import HyperRAM\n'), ((5025, 5079), 'litex.soc.cores.freqmeter.FreqMeter', 'FreqMeter', ([], {'period': 'sys_clk_freq', 'clk': 'self.dphy.clk_byte'}), '(period=sys_clk_freq, clk=self.dphy.clk_byte)\n', (5034, 5079), False, 'from litex.soc.cores.freqmeter import FreqMeter\n'), ((5155, 5188), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', ([], {'pads': 'self.dphy.hs_rx_data'}), '(pads=self.dphy.hs_rx_data)\n', (5161, 5188), False, 'from litex.soc.cores.gpio import GPIOIn\n'), ((5261, 5294), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', ([], {'pads': 'self.dphy.hs_rx_sync'}), '(pads=self.dphy.hs_rx_sync)\n', (5267, 5294), False, 'from litex.soc.cores.gpio import GPIOIn\n'), ((5761, 5785), 'litex.soc.cores.gpio.GPIOIn', 'GPIOIn', ([], {'pads': 'dphy_header'}), '(pads=dphy_header)\n', (5767, 5785), False, 'from litex.soc.cores.gpio import GPIOIn\n'), ((6339, 6389), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['self.packet_cap.mem'], {'read_only': '(True)'}), '(self.packet_cap.mem, read_only=True)\n', (6352, 6389), False, 'from litex.soc.interconnect import wishbone\n'), ((6716, 6765), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['self.image_cap.mem'], {'read_only': '(True)'}), '(self.image_cap.mem, read_only=True)\n', (6729, 6765), False, 'from litex.soc.interconnect import wishbone\n'), ((8156, 8175), 'litex.build.lattice.oxide.oxide_argdict', 'oxide_argdict', (['args'], {}), '(args)\n', (8169, 8175), False, 'from litex.build.lattice.oxide import oxide_args, oxide_argdict\n'), ((8375, 8434), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (8387, 8434), False, 'import os\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2016-2017 <NAME> <<EMAIL>>
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
IBM's 8b/10b Encoding
This scheme is used by a large number of protocols including Display Port, PCI
Express, Gigabit Ethernet, SATA and USB 3.
The encoding is built by combining an 5b/6b and 3b/4b encoding schemes and
guarantees both DC balance and enough bit transitions to recover the clock
signal.
Note: This encoding is *not* used by DVI/HDMI (that uses a *different* 8b/10b
scheme called TMDS).
"""
from functools import reduce
from operator import add
from migen import *
from litex.soc.interconnect import stream
# Helpers ------------------------------------------------------------------------------------------
def K(x, y):
return (y << 5) | x
def disparity(word, nbits):
n0 = 0
n1 = 0
for i in range(nbits):
if word & (1 << i):
n1 += 1
else:
n0 += 1
return n1 - n0
def reverse_table_flip(inputs, flips, nbits):
outputs = [None]*2**nbits
for i, (word, flip) in enumerate(zip(inputs, flips)):
if outputs[word] is not None:
raise ValueError
outputs[word] = i
if flip:
word_n = ~word & (2**nbits-1)
if outputs[word_n] is not None:
raise ValueError
outputs[word_n] = i
for i in range(len(outputs)):
if outputs[i] is None:
outputs[i] = 0
return outputs
def reverse_table(inputs, nbits):
outputs = [None]*2**nbits
for i, word in enumerate(inputs):
if outputs[word] is not None:
raise ValueError
outputs[word] = i
for i in range(len(outputs)):
if outputs[i] is None:
outputs[i] = 0
return outputs
# 5b6b ---------------------------------------------------------------------------------------------
table_5b6b = [
0b011000,
0b100010,
0b010010,
0b110001,
0b001010,
0b101001,
0b011001,
0b000111,
0b000110,
0b100101,
0b010101,
0b110100,
0b001101,
0b101100,
0b011100,
0b101000,
0b100100,
0b100011,
0b010011,
0b110010,
0b001011,
0b101010,
0b011010,
0b000101,
0b001100,
0b100110,
0b010110,
0b001001,
0b001110,
0b010001,
0b100001,
0b010100,
]
table_5b6b_unbalanced = [bool(disparity(c, 6)) for c in table_5b6b]
table_5b6b_flip = list(table_5b6b_unbalanced)
table_5b6b_flip[7] = True
table_6b5b = reverse_table_flip(table_5b6b, table_5b6b_flip, 6)
table_6b5b[0b001111] = 0b11100 # K.28
table_6b5b[0b110000] = 0b11100 # K.28
# 3b4b ---------------------------------------------------------------------------------------------
table_3b4b = [
0b0100,
0b1001,
0b0101,
0b0011,
0b0010,
0b1010,
0b0110,
0b0001, # Primary D.x.7
]
table_3b4b_unbalanced = [bool(disparity(c, 4)) for c in table_3b4b]
table_3b4b_flip = list(table_3b4b_unbalanced)
table_3b4b_flip[3] = True
table_4b3b = reverse_table_flip(table_3b4b, table_3b4b_flip, 4)
# Alternative D.x.7
table_4b3b[0b0111] = 0b0111
table_4b3b[0b1000] = 0b0111
table_4b3b_kn = reverse_table(table_3b4b, 4)
table_4b3b_kp = reverse_table([~x & 0b1111 for x in table_3b4b], 4)
# Primary D.x.7 is not used
table_4b3b_kn[0b0001] = 0b000
table_4b3b_kn[0b1000] = 0b111
table_4b3b_kp[0b1110] = 0b000
table_4b3b_kp[0b0111] = 0b111
# Single Encoder -----------------------------------------------------------------------------------
@CEInserter()
class SingleEncoder(Module):
def __init__(self, lsb_first=False):
self.d = Signal(8)
self.k = Signal()
self.disp_in = Signal()
self.output = Signal(10)
self.disp_out = Signal()
# # #
# Stage 1: 5b/6b and 3b/4b encoding.
code5b = self.d[:5]
code6b = Signal(6, reset_less=True)
code6b_unbalanced = Signal(reset_less=True)
code6b_flip = Signal()
self.sync += [
If(self.k & (code5b == 28),
code6b.eq(0b110000),
code6b_unbalanced.eq(1),
code6b_flip.eq(1)
).Else(
code6b.eq(Array(table_5b6b)[code5b]),
code6b_unbalanced.eq(Array(table_5b6b_unbalanced)[code5b]),
code6b_flip.eq(Array(table_5b6b_flip)[code5b])
)
]
code3b = self.d[5:]
code4b = Signal(4, reset_less=True)
code4b_unbalanced = Signal(reset_less=True)
code4b_flip = Signal()
self.sync += [
code4b.eq(Array(table_3b4b)[code3b]),
code4b_unbalanced.eq(Array(table_3b4b_unbalanced)[code3b]),
If(self.k,
code4b_flip.eq(1)
).Else(
code4b_flip.eq(Array(table_3b4b_flip)[code3b])
)
]
alt7_rd0 = Signal(reset_less=True) # If disparity is -1, use alternative D.x.7.
alt7_rd1 = Signal(reset_less=True) # If disparity is +1, use alternative D.x.7.
self.sync += [
alt7_rd0.eq(0),
alt7_rd1.eq(0),
If(code3b == 7,
If((code5b == 17) | (code5b == 18) | (code5b == 20),
alt7_rd0.eq(1)),
If((code5b == 11) | (code5b == 13) | (code5b == 14),
alt7_rd1.eq(1)),
If(self.k,
alt7_rd0.eq(1),
alt7_rd1.eq(1)
)
)
]
# Stage 2 (combinatorial): disparity control.
output_6b = Signal(6)
disp_inter = Signal()
self.comb += [
disp_inter.eq(self.disp_in ^ code6b_unbalanced),
If(~self.disp_in & code6b_flip,
output_6b.eq(~code6b)
).Else(
output_6b.eq(code6b)
)
]
output_4b = Signal(4)
self.comb += [
If(~disp_inter & alt7_rd0,
self.disp_out.eq(~disp_inter),
output_4b.eq(0b0111)
).Elif(disp_inter & alt7_rd1,
self.disp_out.eq(~disp_inter),
output_4b.eq(0b1000)
).Else(
self.disp_out.eq(disp_inter ^ code4b_unbalanced),
If(~disp_inter & code4b_flip,
output_4b.eq(~code4b)
).Else(
output_4b.eq(code4b)
)
)
]
output_msb_first = Signal(10)
self.comb += output_msb_first.eq(Cat(output_4b, output_6b))
if lsb_first:
for i in range(10):
self.comb += self.output[i].eq(output_msb_first[9-i])
else:
self.comb += self.output.eq(output_msb_first)
# Encoder ------------------------------------------------------------------------------------------
class Encoder(Module):
def __init__(self, nwords=1, lsb_first=False):
self.ce = Signal(reset=1)
self.d = [Signal(8) for _ in range(nwords)]
self.k = [Signal() for _ in range(nwords)]
self.output = [Signal(10, reset_less=True) for _ in range(nwords)]
self.disparity = [Signal() for _ in range(nwords)]
# # #
encoders = [SingleEncoder(lsb_first) for _ in range(nwords)]
self.comb += [encoder.ce.eq(self.ce) for encoder in encoders]
self.submodules += encoders
self.sync += If(self.ce, encoders[0].disp_in.eq(encoders[-1].disp_out))
for e1, e2 in zip(encoders, encoders[1:]):
self.comb += e2.disp_in.eq(e1.disp_out)
for d, k, output, disparity, encoder in zip(self.d, self.k, self.output, self.disparity, encoders):
self.comb += [
encoder.d.eq(d),
encoder.k.eq(k)
]
output.reset_less = True
self.sync += If(self.ce,
output.eq(encoder.output),
disparity.eq(encoder.disp_out)
)
# Decoder ------------------------------------------------------------------------------------------
class Decoder(Module):
def __init__(self, lsb_first=False):
self.ce = Signal(reset=1)
self.input = Signal(10)
self.d = Signal(8)
self.k = Signal()
self.invalid = Signal()
# # #
input_msb_first = Signal(10)
if lsb_first:
for i in range(10):
self.comb += input_msb_first[i].eq(self.input[9-i])
else:
self.comb += input_msb_first.eq(self.input)
code6b = input_msb_first[4:]
code5b = Signal(5)
code4b = input_msb_first[:4]
code3b = Signal(3, reset_less=True)
mem_6b5b = Memory(5, len(table_6b5b), init=table_6b5b)
port_6b5b = mem_6b5b.get_port(has_re=True)
self.specials += mem_6b5b, port_6b5b
self.comb += port_6b5b.adr.eq(code6b)
self.comb += port_6b5b.re.eq(self.ce)
self.sync += If(self.ce,
self.k.eq(0),
If(code6b == 0b001111,
self.k.eq(1),
code3b.eq(Array(table_4b3b_kn)[code4b])
).Elif(code6b == 0b110000,
self.k.eq(1),
code3b.eq(Array(table_4b3b_kp)[code4b])
).Else(
If((code4b == 0b0111) | (code4b == 0b1000), # D.x.A7/K.x.7
If((code6b != 0b100011) &
(code6b != 0b010011) &
(code6b != 0b001011) &
(code6b != 0b110100) &
(code6b != 0b101100) &
(code6b != 0b011100), self.k.eq(1))
),
code3b.eq(Array(table_4b3b)[code4b])
),
)
self.comb += code5b.eq(port_6b5b.dat_r)
self.comb += self.d.eq(Cat(code5b, code3b))
# Basic invalid symbols detection: check that we have 4,5 or 6 ones in the symbol. This does
# not report all invalid symbols but still allow detecting issues with the link.
ones = Signal(4, reset_less=True)
self.sync += If(self.ce, ones.eq(reduce(add, [self.input[i] for i in range(10)])))
self.comb += self.invalid.eq((ones != 4) & (ones != 5) & (ones != 6))
# Stream Encoder -----------------------------------------------------------------------------------
class StreamEncoder(stream.PipelinedActor):
def __init__(self, nwords=1):
self.sink = sink = stream.Endpoint([("d", nwords*8), ("k", nwords)])
self.source = source = stream.Endpoint([("data", nwords*10)])
stream.PipelinedActor.__init__(self, latency=2)
# # #
# Encoders
encoder = Encoder(nwords, True)
self.submodules += encoder
# Control
self.comb += encoder.ce.eq(self.pipe_ce)
# Datapath
for i in range(nwords):
self.comb += [
encoder.k[i].eq(sink.k[i]),
encoder.d[i].eq(sink.d[8*i:8*(i+1)]),
source.data[10*i:10*(i+1)].eq(encoder.output[i])
]
# Stream Encoder -----------------------------------------------------------------------------------
class StreamDecoder(stream.PipelinedActor):
def __init__(self, nwords=1):
self.sink = sink = stream.Endpoint([("data", nwords*10)])
self.source = source = stream.Endpoint([("d", nwords*8), ("k", nwords)])
stream.PipelinedActor.__init__(self, latency=1)
# # #
# Decoders
decoders = [Decoder(True) for _ in range(nwords)]
self.submodules += decoders
# Control
self.comb += [decoders[i].ce.eq(self.pipe_ce) for i in range(nwords)]
# Datapath
for i in range(nwords):
self.comb += [
decoders[i].input.eq(sink.data[10*i:10*(i+1)]),
source.k[i].eq(decoders[i].k),
source.d[8*i:8*(i+1)].eq(decoders[i].d)
] | [
"litex.soc.interconnect.stream.PipelinedActor.__init__",
"litex.soc.interconnect.stream.Endpoint"
] | [((10573, 10624), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('d', nwords * 8), ('k', nwords)]"], {}), "([('d', nwords * 8), ('k', nwords)])\n", (10588, 10624), False, 'from litex.soc.interconnect import stream\n'), ((10654, 10694), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', nwords * 10)]"], {}), "([('data', nwords * 10)])\n", (10669, 10694), False, 'from litex.soc.interconnect import stream\n'), ((10701, 10748), 'litex.soc.interconnect.stream.PipelinedActor.__init__', 'stream.PipelinedActor.__init__', (['self'], {'latency': '(2)'}), '(self, latency=2)\n', (10731, 10748), False, 'from litex.soc.interconnect import stream\n'), ((11395, 11435), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', nwords * 10)]"], {}), "([('data', nwords * 10)])\n", (11410, 11435), False, 'from litex.soc.interconnect import stream\n'), ((11465, 11516), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('d', nwords * 8), ('k', nwords)]"], {}), "([('d', nwords * 8), ('k', nwords)])\n", (11480, 11516), False, 'from litex.soc.interconnect import stream\n'), ((11523, 11570), 'litex.soc.interconnect.stream.PipelinedActor.__init__', 'stream.PipelinedActor.__init__', (['self'], {'latency': '(1)'}), '(self, latency=1)\n', (11553, 11570), False, 'from litex.soc.interconnect import stream\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.csr import CSRStorage, AutoCSR
from litedram.common import Settings, tXXDController
from litedram.phy.utils import Serializer, Deserializer, edge
# PHY ----------------------------------------------------------------------------------------------
class SimSerDesMixin:
"""Helper class for easier (de-)serialization to simulation pads."""
def ser(self, *, i, o, clkdiv, clk, name="", **kwargs):
assert len(o) == 1
kwargs = dict(i=i, i_dw=len(i), o=o, o_dw=1, clk=clk, clkdiv=clkdiv,
name=f"ser_{name}".strip("_"), **kwargs)
self.submodules += Serializer(**kwargs)
def des(self, *, i, o, clkdiv, clk, name="", **kwargs):
assert len(i) == 1
kwargs = dict(i=i, i_dw=1, o=o, o_dw=len(o), clk=clk, clkdiv=clkdiv,
name=f"des_{name}".strip("_"), **kwargs)
self.submodules += Deserializer(**kwargs)
# Platform -----------------------------------------------------------------------------------------
class SimPad(Settings):
def __init__(self, name, width, io=False):
self.set_attributes(locals())
class SimulationPads(Module):
"""Pads for simulation purpose
Tristate pads are simulated as separate input/output pins (name_i, name_o) and
an output-enable pin (name_oe). Output pins are to be driven byt the PHY and
input pins are to be driven by the DRAM simulator. An additional pin without
a suffix is created and this module will include logic to set this pin to the
actual value depending on the output-enable signal.
"""
def layout(self, **kwargs):
raise NotImplementedError("Simulation pads layout as a list of SimPad objects")
def __init__(self, **kwargs):
for pad in self.layout(**kwargs):
if pad.io:
o, i, oe = (f"{pad.name}_{suffix}" for suffix in ["o", "i", "oe"])
setattr(self, pad.name, Signal(pad.width))
setattr(self, o, Signal(pad.width, name=o))
setattr(self, i, Signal(pad.width, name=i))
setattr(self, oe, Signal(name=oe))
self.comb += If(getattr(self, oe),
getattr(self, pad.name).eq(getattr(self, o))
).Else(
getattr(self, pad.name).eq(getattr(self, i))
)
else:
setattr(self, pad.name, Signal(pad.width, name=pad.name))
class Clocks(dict):
"""Helper for definiting simulation clocks
Dictionary format is `{name: {"freq_hz": _, "phase_deg": _}, ...}`.
"""
def names(self):
return list(self.keys())
def add_io(self, io):
for name in self.names():
io.append((name + "_clk", 0, Pins(1)))
def add_clockers(self, sim_config):
for name, desc in self.items():
sim_config.add_clocker(name + "_clk", **desc)
class CRG(Module):
"""Clock & Reset Generator for Verilator-based simulation"""
def __init__(self, platform, clock_domains=None):
if clock_domains is None:
clock_domains = ["sys"]
elif isinstance(clock_domains, Clocks):
clock_domains = list(clock_domains.names())
# request() before creating clock_domains to avoid signal renaming problem
clock_domains = {name: platform.request(name + "_clk") for name in clock_domains}
self.clock_domains.cd_por = ClockDomain(reset_less=True)
for name in clock_domains.keys():
setattr(self.clock_domains, "cd_" + name, ClockDomain(name=name))
int_rst = Signal(reset=1)
self.sync.por += int_rst.eq(0)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
for name, clk in clock_domains.items():
cd = getattr(self, "cd_" + name)
self.comb += cd.clk.eq(clk)
self.comb += cd.rst.eq(int_rst)
class Platform(SimPlatform):
def __init__(self, io, clocks: Clocks):
common_io = [
("sys_rst", 0, Pins(1)),
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
]
clocks.add_io(common_io)
SimPlatform.__init__(self, "SIM", common_io + io)
# Logging ------------------------------------------------------------------------------------------
class SimLogger(Module, AutoCSR):
"""Logger for use in simulation
This module allows for easier message logging when running simulation designs.
The logger can be used from `comb` context so it the methods can be directly
used inside `FSM` code. It also provides logging levels that can be used to
filter messages, either by specifying the default `log_level` or in runtime
by driving to the `level` signal or using a corresponding CSR.
"""
# Allows to use Display inside FSM and to filter log messages by level (statically or dynamically)
DEBUG = 0
INFO = 1
WARN = 2
ERROR = 3
NONE = 4
def __init__(self, log_level=INFO, clk_freq=None):
self.ops = []
self.level = Signal(reset=log_level, max=self.NONE)
self.time_ps = None
if clk_freq is not None:
self.time_ps = Signal(64)
cnt = Signal(64)
self.sync += cnt.eq(cnt + 1)
self.comb += self.time_ps.eq(cnt * int(1e12/clk_freq))
def debug(self, fmt, *args, **kwargs):
return self.log("[DEBUG] " + fmt, *args, level=self.DEBUG, **kwargs)
def info(self, fmt, *args, **kwargs):
return self.log("[INFO] " + fmt, *args, level=self.INFO, **kwargs)
def warn(self, fmt, *args, **kwargs):
return self.log("[WARN] " + fmt, *args, level=self.WARN, **kwargs)
def error(self, fmt, *args, **kwargs):
return self.log("[ERROR] " + fmt, *args, level=self.ERROR, **kwargs)
def log(self, fmt, *args, level=DEBUG, once=True):
cond = Signal()
if once: # make the condition be triggered only on rising edge
condition = edge(self, cond)
else:
condition = cond
self.ops.append((level, condition, fmt, args))
return cond.eq(1)
def add_csrs(self):
self._level = CSRStorage(len(self.level), reset=self.level.reset.value)
self.comb += self.level.eq(self._level.storage)
def do_finalize(self):
for level, cond, fmt, args in self.ops:
if self.time_ps is not None:
fmt = f"[%16d ps] {fmt}"
args = (self.time_ps, *args)
self.sync += If((level >= self.level) & cond, Display(fmt, *args))
def log_level_getter(log_level):
"""Parse logging level description
Log level can be presented in a simple form (e.g. `--log-level=DEBUG`) to specify
the same level for all modules, or can set different levels for different modules
e.g. `--log-level=all=INFO,data=DEBUG`.
"""
def get_level(name):
return getattr(SimLogger, name.upper())
if "=" not in log_level: # simple log_level, e.g. "INFO"
return lambda _: get_level(log_level)
# parse log_level in the per-module form, e.g. "--log-level=all=INFO,data=DEBUG"
per_module = dict(part.split("=") for part in log_level.strip().split(","))
return lambda module: get_level(per_module.get(module, per_module.get("all", None)))
# Simulator ----------------------------------------------------------------------------------------
class PulseTiming(Module):
"""Timing monitor with pulse input/output
This module works like `tXXDController` with the following differences:
* countdown triggered by a low to high pulse on `trigger`
* `ready` is initially low, only after a trigger it can become high
* provides `ready_p` which is high only for 1 cycle when `ready` becomes high
"""
def __init__(self, t):
self.trigger = Signal()
self.ready = Signal()
self.ready_p = Signal()
ready_d = Signal()
triggered = Signal()
tctrl = tXXDController(t)
self.submodules += tctrl
self.sync += If(self.trigger, triggered.eq(1)),
self.comb += [
self.ready.eq(triggered & tctrl.ready),
self.ready_p.eq(edge(self, self.ready)),
tctrl.valid.eq(edge(self, self.trigger)),
]
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"litex.build.sim.SimPlatform.__init__",
"litex.build.generic_platform.Pins"
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# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk50", 0, Pins("R8"), IOStandard("3.3-V LVTTL")),
("user_led", 0, Pins("A15"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("A13"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("B13"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("A11"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("D1"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("F3"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("B1"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("L3"), IOStandard("3.3-V LVTTL")),
("key", 0, Pins("J15"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("E1"), IOStandard("3.3-V LVTTL")),
("sw", 0, Pins("M1"), IOStandard("3.3-V LVTTL")),
("sw", 1, Pins("T8"), IOStandard("3.3-V LVTTL")),
("sw", 2, Pins("B9"), IOStandard("3.3-V LVTTL")),
("sw", 3, Pins("M15"), IOStandard("3.3-V LVTTL")),
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
# GND on JP1 Pin 12.
Subsignal("tx", Pins("B5"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("B4"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
("sdram_clock", 0, Pins("R4"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"P2 N5 N6 M8 P8 T7 N8 T6",
"R1 P1 N2 N1 L4")),
Subsignal("ba", Pins("M7 M6")),
Subsignal("cs_n", Pins("P6")),
Subsignal("cke", Pins("L7")),
Subsignal("ras_n", Pins("L2")),
Subsignal("cas_n", Pins("L1")),
Subsignal("we_n", Pins("C2")),
Subsignal("dq", Pins(
"G2 G1 L8 K5 K2 J2 J1 R7",
"T4 T2 T3 R3 R5 P3 N3 K1")),
Subsignal("dm", Pins("R6 T5")),
IOStandard("3.3-V LVTTL")
),
("epcs", 0,
Subsignal("data0", Pins("H2")),
Subsignal("dclk", Pins("H1")),
Subsignal("ncs0", Pins("D2")),
Subsignal("asd0", Pins("C1")),
IOStandard("3.3-V LVTTL")
),
("i2c", 0,
Subsignal("sclk", Pins("F2")),
Subsignal("sdat", Pins("F1")),
IOStandard("3.3-V LVTTL")
),
("g_sensor", 0,
Subsignal("cs_n", Pins("G5")),
Subsignal("int", Pins("M2")),
IOStandard("3.3-V LVTTL")
),
("adc", 0,
Subsignal("cs_n", Pins("A10")),
Subsignal("saddr", Pins("B10")),
Subsignal("sclk", Pins("B14")),
Subsignal("sdat", Pins("A9")),
IOStandard("3.3-V LVTTL")
),
("gpio_0", 0, Pins(
"D3 C3 A2 A3 B3 B4 A4 B5",
"A5 D5 B6 A6 B7 D6 A7 C6",
"C8 E6 E7 D8 E8 F8 F9 E9",
"C9 D9 E11 E10 C11 B11 A12 D11",
"D12 B12"),
IOStandard("3.3-V LVTTL")
),
("gpio_1", 0, Pins(
"F13 T15 T14 T13 R13 T12 R12 T11",
"T10 R11 P11 R10 N12 P9 N9 N11",
"L16 K16 R16 L15 P15 P16 R14 N16",
"N15 P14 L14 N14 M10 L13 J16 K15",
"J13 J14"),
IOStandard("3.3-V LVTTL")
),
("gpio_2", 0, Pins(
"A14 B16 C14 C16 C15 D16 D15 D14",
"F15 F16 F14 G16 G15"),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((3739, 3789), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE22F17C6"""', '_io'], {}), "(self, 'EP4CE22F17C6', _io)\n", (3762, 3789), False, 'from litex.build.altera import AlteraPlatform\n'), ((3839, 3851), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (3849, 3851), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((3898, 3940), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3924, 3940), False, 'from litex.build.altera import AlteraPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
# Button
("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
# Serial
("serial", 0,
# Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232)
Subsignal("tx", Pins("AA13"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10)
Subsignal("rx", Pins("AA14"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8)
),
# SDR SDRAM
("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"V2 V1 U2 U1 V3 V4 Y2 AA1",
"Y3 V5 W1 Y4 V6")),
Subsignal("ba", Pins("Y1 W2")),
Subsignal("cs_n", Pins("AA3")),
Subsignal("cke", Pins("W6")),
Subsignal("ras_n", Pins("AB3")),
Subsignal("cas_n", Pins("AA4")),
Subsignal("we_n", Pins("AB4")),
Subsignal("dq", Pins(
"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
Subsignal("dm", Pins("AA5 W7")),
IOStandard("3.3-V LVTTL")
),
# GPIOs
#ignore for now
#("gpio_0", 0, Pins(
# "D3 C3 A2 A3 B3 B4 A4 B5",
# "A5 D5 B6 A6 B7 D6 A7 C6",
# "C8 E6 E7 D8 E8 F8 F9 E9",
# "C9 D9 E11 E10 C11 B11 A12 D11",
# "D12 B12"),
# IOStandard("3.3-V LVTTL")
#),
#("gpio_1", 0, Pins(
# "F13 T15 T14 T13 R13 T12 R12 T11",
# "T10 R11 P11 R10 N12 P9 N9 N11",
# "L16 K16 R16 L15 P15 P16 R14 N16",
# "N15 P14 L14 N14 M10 L13 J16 K15",
# "J13 J14"),
# IOStandard("3.3-V LVTTL")
#),
#("gpio_2", 0, Pins(
# "A14 B16 C14 C16 C15 D16 D15 D14",
# "F15 F16 F14 G16 G15"),
# IOStandard("3.3-V LVTTL")
#),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "EP4CE15F23C8", _io)
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")),
# Button
("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")),
# SPIFlash (W25Q64)
("spiflash", 0,
# clk
Subsignal("cs_n", Pins("E2")),
Subsignal("clk", Pins("K2")),
Subsignal("mosi", Pins("D1")),
Subsignal("miso", Pins("E2")),
IOStandard("3.3-V LVTTL"),
),
# SDR SDRAM
("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"V2 V1 U2 U1 V3 V4 Y2 AA1",
"Y3 V5 W1 Y4 V6")),
Subsignal("ba", Pins("Y1 W2")),
Subsignal("cs_n", Pins("AA3")),
Subsignal("cke", Pins("W6")),
Subsignal("ras_n", Pins("AB3")),
Subsignal("cas_n", Pins("AA4")),
Subsignal("we_n", Pins("AB4")),
Subsignal("dq", Pins(
"AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5",
"Y7 W8 Y8 V9 V10 Y10 W10 V11")),
Subsignal("dm", Pins("AA5 W7")),
IOStandard("3.3-V LVTTL")
),
]
# The connectors are named after the daughterboard, not the core board
# because on the different core boards the names vary, but on the
# daughterboard they stay the same, which we need to connect the
# daughterboard peripherals to the core board.
# On this board J2 is U7 and J3 is U8
_connectors = [
("J2", {
# odd row even row
7: "R1", 8: "R2",
9: "P1", 10: "P2",
11: "N1", 12: "N2",
13: "M1", 14: "M2",
15: "J1", 16: "J2",
17: "H1", 18: "H2",
19: "F1", 20: "F2",
21: "E1", 22: "D2",
23: "C1", 24: "C2",
25: "B1", 26: "B2",
27: "B3", 28: "A3",
29: "B4", 30: "A4",
31: "C4", 32: "C3",
33: "B5", 34: "A5",
35: "B6", 36: "A6",
37: "B7", 38: "A7",
39: "B8", 40: "A8",
41: "B9", 42: "A9",
43: "B10", 44: "A10",
45: "B13", 46: "A13",
47: "B14", 48: "A14",
49: "B15", 50: "A15",
51: "B16", 52: "A16",
53: "B17", 54: "A17",
55: "B18", 56: "A18",
57: "B19", 58: "A19",
59: "B20", 60: "A20",
}),
("J3", {
# odd row even row
7: "AA13", 8: "AB13",
9: "AA14", 10: "AB14",
11: "AA15", 12: "AB15",
13: "AA16", 14: "AB16",
15: "AA17", 16: "AB17",
17: "AA18", 18: "AB18",
19: "AA19", 20: "AB19",
21: "AA20", 22: "AB20",
23: "Y22", 24: "Y21",
25: "W22", 26: "W21",
27: "V22", 28: "V21",
29: "U22", 30: "U21",
31: "R22", 32: "R21",
33: "P22", 34: "P21",
35: "N22", 36: "N21",
37: "M22", 38: "M21",
39: "L22", 40: "L21",
41: "K22", 42: "K21",
43: "J22", 44: "J21",
45: "H22", 46: "H21",
47: "F22", 48: "F21",
49: "E22", 50: "E21",
51: "D22", 52: "D21",
53: "C22", 54: "C21",
55: "B22", 56: "B21",
57: "N20", 58: "N19",
59: "M20", 60: "M19",
})
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
core_resources = [
("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL"))
),
]
def __init__(self, variant="ep4ce15", toolchain="quartus", with_daughterboard=False):
device = {
"ep4ce15": "EP4CE15F23C8",
"ep4ce55": "EP4CE55F23C8"
}[variant]
io = _io
connectors = _connectors
if with_daughterboard:
from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard
daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL"))
io += daughterboard.io
connectors += daughterboard.connectors
else:
io += self.core_resources
AlteraPlatform.__init__(self, device, io, connectors, toolchain=toolchain)
if with_daughterboard:
# an ethernet pin takes K22, so make it available
self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
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"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
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from migen import Module, Signal, Instance, ClockDomain, If
from litex.build.lattice.platform import LatticePlatform
from litex.soc.cores import up5kspram, spi_flash
from litex_boards.targets.fomu import _CRG
import litex.soc.doc as lxsocdoc
import spibone
from ..romgen import RandomFirmwareROM, FirmwareROM
from ..fomutouch import TouchPads
from ..sbwarmboot import SBWarmBoot
from rtl.sbled import SBLED
import argparse
import os
def add_platform_args(parser):
parser.add_argument(
"--revision", choices=["evt", "dvt", "pvt", "hacker"], required=True,
help="build foboot for a particular hardware revision"
)
class Platform(LatticePlatform):
def __init__(self, revision=None, toolchain="icestorm"):
self.revision = revision
self.hw_platform = "fomu"
if revision == "evt":
from litex_boards.platforms.fomu_evt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm")
self.spi_size = 16 * 1024 * 1024
self.spi_dummy = 6
elif revision == "dvt":
from litex_boards.platforms.fomu_pvt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 6
elif revision == "pvt":
from litex_boards.platforms.fomu_pvt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 6
elif revision == "hacker":
from litex_boards.platforms.fomu_hacker import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 4
else:
raise ValueError("Unrecognized revision: {}. Known values: evt, dvt, pvt, hacker".format(revision))
self.warmboot_offsets = [
160,
160,
157696,
262144,
262144 + 32768,
]
def get_config(self, git_version):
return [
("USB_VENDOR_ID", 0x1209), # pid.codes
("USB_PRODUCT_ID", 0x5bf0), # Assigned to Fomu project
("USB_DEVICE_VER", 0x0101), # Bootloader version
("USB_MANUFACTURER_NAME", "Foosn"),
] + {
"evt": [("USB_PRODUCT_NAME", "Fomu EVT running DFU Bootloader {}".format(git_version))],
"dvt": [("USB_PRODUCT_NAME", "Fomu DVT running DFU Bootloader {}".format(git_version))],
"pvt": [("USB_PRODUCT_NAME", "Fomu PVT running DFU Bootloader {}".format(git_version))],
"hacker":[("USB_PRODUCT_NAME", "Fomu Hacker running DFU Bootloader {}".format(git_version))],
}[self.revision]
def add_crg(self, soc):
soc.submodules.crg = _CRG(self)
def add_cpu_variant(self, soc, debug=False):
if debug:
soc.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
else:
soc.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
def add_sram(self, soc):
spram_size = 128*1024
soc.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
return spram_size
def add_reboot(self, soc):
soc.submodules.reboot = SBWarmBoot(soc, self.warmboot_offsets)
def add_touch(self, soc):
self.add_extension(TouchPads.touch_device)
soc.submodules.touch = TouchPads(self.request("touch_pads"))
def add_rgb(self, soc):
soc.submodules.rgb = SBLED(self.revision, self.request("rgb_led"))
def create_programmer(self):
raise ValueError("programming is not supported")
def build_templates(self, use_dsp, pnr_seed, placer):
# Override default LiteX's yosys/build templates
assert hasattr(self.toolchain, "yosys_template")
assert hasattr(self.toolchain, "build_template")
self.toolchain.yosys_template = [
"{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ice40 -json {build_name}.json -top {build_name}",
]
self.toolchain.build_template = [
"yosys -q -l {build_name}.rpt {build_name}.ys",
"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt \
--pre-pack {build_name}_pre_pack.py --{architecture} --package {package}",
"icepack {build_name}.txt {build_name}.bin"
]
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
self.toolchain.yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
self.toolchain.yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
self.toolchain.build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
self.toolchain.build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
self.toolchain.build_template[1] += " --placer {}".format(placer)
def finialise(self, output_dir):
make_multiboot_header(os.path.join(output_dir, "gateware", "multiboot-header.bin"),
self.warmboot_offsets)
with open(os.path.join(output_dir, 'gateware', 'multiboot-header.bin'), 'rb') as multiboot_header_file:
multiboot_header = multiboot_header_file.read()
with open(os.path.join(output_dir, 'gateware', 'top.bin'), 'rb') as top_file:
top = top_file.read()
with open(os.path.join(output_dir, 'gateware', 'top-multiboot.bin'), 'wb') as top_multiboot_file:
top_multiboot_file.write(multiboot_header)
top_multiboot_file.write(top)
print(
"""Foboot build complete. Output files:
{}/gateware/top.bin Bitstream file. Load this onto the FPGA for testing.
{}/gateware/top-multiboot.bin Multiboot-enabled bitstream file. Flash this onto FPGA ROM.
{}/gateware/top.v Source Verilog file. Useful for debugging issues.
{}/software/include/generated/ Directory with header files for API access.
{}/software/bios/bios.elf ELF file for debugging bios.
""".format(output_dir, output_dir, output_dir, output_dir, output_dir))
def make_multiboot_header(filename, boot_offsets=[160]):
"""
ICE40 allows you to program the SB_WARMBOOT state machine by adding the following
values to the bitstream, before any given image:
[7e aa 99 7e] Sync Header
[92 00 k0] Boot mode (k = 1 for cold boot, 0 for warmboot)
[44 03 o1 o2 o3] Boot address
[82 00 00] Bank offset
[01 08] Reboot
[...] Padding (up to 32 bytes)
Note that in ICE40, the second nybble indicates the number of remaining bytes
(with the exception of the sync header).
The above construct is repeated five times:
INITIAL_BOOT The image loaded at first boot
BOOT_S00 The first image for SB_WARMBOOT
BOOT_S01 The second image for SB_WARMBOOT
BOOT_S10 The third image for SB_WARMBOOT
BOOT_S11 The fourth image for SB_WARMBOOT
"""
while len(boot_offsets) < 5:
boot_offsets.append(boot_offsets[0])
with open(filename, 'wb') as output:
for offset in boot_offsets:
# Sync Header
output.write(bytes([0x7e, 0xaa, 0x99, 0x7e]))
# Boot mode
output.write(bytes([0x92, 0x00, 0x00]))
# Boot address
output.write(bytes([0x44, 0x03,
(offset >> 16) & 0xff,
(offset >> 8) & 0xff,
(offset >> 0) & 0xff]))
# Bank offset
output.write(bytes([0x82, 0x00, 0x00]))
# Reboot command
output.write(bytes([0x01, 0x08]))
for x in range(17, 32):
output.write(bytes([0]))
| [
"litex.soc.cores.up5kspram.Up5kSPRAM",
"litex.build.lattice.platform.LatticePlatform.__init__"
] | [((3049, 3059), 'litex_boards.targets.fomu._CRG', '_CRG', (['self'], {}), '(self)\n', (3053, 3059), False, 'from litex_boards.targets.fomu import _CRG\n'), ((3371, 3407), 'litex.soc.cores.up5kspram.Up5kSPRAM', 'up5kspram.Up5kSPRAM', ([], {'size': 'spram_size'}), '(size=spram_size)\n', (3390, 3407), False, 'from litex.soc.cores import up5kspram, spi_flash\n'), ((923, 1016), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-sg48', _io, _connectors,\n toolchain='icestorm')\n", (947, 1016), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((5756, 5816), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""multiboot-header.bin"""'], {}), "(output_dir, 'gateware', 'multiboot-header.bin')\n", (5768, 5816), False, 'import os\n'), ((1206, 1300), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-uwg30"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-uwg30', _io, _connectors,\n toolchain='icestorm')\n", (1230, 1300), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((5892, 5952), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""multiboot-header.bin"""'], {}), "(output_dir, 'gateware', 'multiboot-header.bin')\n", (5904, 5952), False, 'import os\n'), ((1489, 1583), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-uwg30"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-uwg30', _io, _connectors,\n toolchain='icestorm')\n", (1513, 1583), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((6068, 6115), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""top.bin"""'], {}), "(output_dir, 'gateware', 'top.bin')\n", (6080, 6115), False, 'import os\n'), ((1778, 1872), 'litex.build.lattice.platform.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-uwg30"""', '_io', '_connectors'], {'toolchain': '"""icestorm"""'}), "(self, 'ice40-up5k-uwg30', _io, _connectors,\n toolchain='icestorm')\n", (1802, 1872), False, 'from litex.build.lattice.platform import LatticePlatform\n'), ((6200, 6257), 'os.path.join', 'os.path.join', (['output_dir', '"""gateware"""', '"""top-multiboot.bin"""'], {}), "(output_dir, 'gateware', 'top-multiboot.bin')\n", (6212, 6257), False, 'import os\n')] |
# Support for the Digilent Atlys (http://digilentinc.com/atlys/) - The board used for HDMI2USB prototyping.
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, iMPACT
# There appear to be 4 x LTC2481C on the U1-SCL / U1-SDA lines connected to the Cypress
class DynamicLVCMOS(object):
"""Object to allow configuration of IOBs connected to dynamic voltage level.
This is used because VCCB2 supply for Bank 2 can be connected to either the
VCC2V5 or VCC3V3 rail depending on JP12, however there is no way to
autodetect this.
"""
def __init__(self, name):
self.name = name
self.level = None
def set(self, value):
self.level = {
"VCC2V5": "LVCMOS25",
"VCC3V3": "LVCMOS33",
}[value]
def __str__(self):
assert self.level, "%s object accessed before voltage level set!" % self.name
return self.level
def __add__(self, o):
return str(self) + o
def __radd__(self, o):
return o + str(self)
# VCC Bank 0 == 3V3
LVCMOS_BANK0 = "LVCMOS33"
# VCC Bank 1 == 3V3
LVCMOS_BANK1 = "LVCMOS33"
# VCC Bank 2 == 3V3 or 2V5
LVCMOS_BANK2 = DynamicLVCMOS("LVCMOS_BANK2")
# VCC Bank 3 == 1V8
LVCMOS_BANK3 = "LVCMOS18"
# VCC Aux == 3V3
_io = [
# NET "clk" LOC = "L15"; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
# SG8002JF - 100MHz - CMOS Crystal Oscillator
("clk100", 0, Pins("L15"), IOStandard(LVCMOS_BANK1)),
# M0/RESET button
# VCCB2 --[10K]--+--[1k]-- M0/Reset
# |
# GND -[ BTN ]-+--[390]- BTNRST
# NET "btn<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
("cpu_reset", 0, Pins("T15"), IOStandard(LVCMOS_BANK2)),
## onBoard USB controller - FIXME
# CY7C68013A-56
# EEPROM config 24AA128 -- A0,A1,A2 = 1,0,0 -- JP9 connects / disconnects SDA
# NET "EppAstb" LOC = "B9"; # Bank = 0, Pin name = IO_L35P_GCLK17, Sch name = U1-FLAGA
# NET "EppDstb" LOC = "A9"; # Bank = 0, Pin name = IO_L35N_GCLK16, Sch name = U1-FLAGB
# NET "UsbFlag" LOC = "C15"; # Bank = 0, Pin name = IO_L64P_SCP5, Sch name = U1-FLAGC
# NET "EppWait" LOC = "F13"; # Bank = 0, Pin name = IO_L63P_SCP7, Sch name = U1-SLRD
# NET "EppDB<0>" LOC = "A2"; # Bank = 0, Pin name = IO_L2N, Sch name = U1-FD0
# NET "EppDB<1>" LOC = "D6"; # Bank = 0, Pin name = IO_L3P, Sch name = U1-FD1
# NET "EppDB<2>" LOC = "C6"; # Bank = 0, Pin name = IO_L3N, Sch name = U1-FD2
# NET "EppDB<3>" LOC = "B3"; # Bank = 0, Pin name = IO_L4P, Sch name = U1-FD3
# NET "EppDB<4>" LOC = "A3"; # Bank = 0, Pin name = IO_L4N, Sch name = U1-FD4
# NET "EppDB<5>" LOC = "B4"; # Bank = 0, Pin name = IO_L5P, Sch name = U1-FD5
# NET "EppDB<6>" LOC = "A4"; # Bank = 0, Pin name = IO_L5N, Sch name = U1-FD6
# NET "EppDB<7>" LOC = "C5"; # Bank = 0, Pin name = IO_L6P, Sch name = U1-FD7
# HDMI2USB configuration....
("fx2", 0,
Subsignal("ifclk", Pins("C10")),
Subsignal("data", Pins("A2 D6 C6 B3 A3 B4 A4 C5")),
Subsignal("addr", Pins("A14 B14"), Misc("DRIVE=12")),
Subsignal("flaga", Pins("B9"), Misc("DRIVE=12")),
Subsignal("flagb", Pins("A9"), Misc("DRIVE=12")),
Subsignal("flagc", Pins("C15"), Misc("DRIVE=12")),
Subsignal("rd_n", Pins("F13"), Misc("DRIVE=12")),
Subsignal("wr_n", Pins("E13")),
Subsignal("oe_n", Pins("A15"), Misc("DRIVE=12")),
Subsignal("cs_n", Pins("B2")),
Subsignal("pktend_n", Pins("C4"), Misc("DRIVE=12")),
IOStandard(LVCMOS_BANK0)
),
## onBoard Quad-SPI Flash
# 16Mbyte x4 SPI Flash for configuration & data storage. An FPGA
# configuration file requires less than 12Mbits, leaving 116Mbits
# available for user data.
# Numonyx -- N25Q12-F8 or N25Q12-SF
# DQ0 - SDI, DQ1 - SDO, DQ2 -> ^WP/DQ2 (pulled high), DQ3 -> ^HOLD/DQ3 (pulled high)
("spiflash4x", 0,
# NET "FlashCS" LOC = "V3"; # Bank = 2, Pin name = IO_L65N_CSO_B_2, Sch name = CS
Subsignal("cs_n", Pins("V3")),
# NET "FlashCLK" LOC = "R15"; # Bank = 2, Pin name = IO_L1P_CCLK_2, Sch name = SCK
Subsignal("clk", Pins("R15")),
# NET "FlashMemDq<0>" LOC = "T13"; # Bank = 2, Pin name = IO_L3N_MOSI_CSI_B_MISO0_2, Sch name = SDI
# NET "FlashMemDq<1>" LOC = "R13"; # Bank = 2, Pin name = IO_L3P_D0_DIN_MISO_MISO1_2, Sch name = DQ1
# NET "FlashMemDq<2>" LOC = "T14"; # Bank = 2, Pin name = IO_L12P_D1_MISO2_2, Sch name = DQ2
# NET "FlashMemDq<3>" LOC = "V14"; # Bank = 2, Pin name = IO_L12N_D2_MISO3_2, Sch name = DQ3
Subsignal("dq", Pins("T13", "R13", "T14", "V14")),
IOStandard(LVCMOS_BANK2), Misc("SLEW=FAST")
),
## onBoard Leds
# NET "Led<0>" LOC = "U18"; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0
# NET "Led<1>" LOC = "M14"; # Bank = 1, Pin name = IO_L53P, Sch name = LD1
# NET "Led<2>" LOC = "N14"; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2
# NET "Led<3>" LOC = "L14"; # Bank = 1, Pin name = IO_L61P, Sch name = LD3
# NET "Led<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4
# NET "Led<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
# NET "Led<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
# NET "Led<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
("user_led", 0, Pins("U18"), IOStandard(LVCMOS_BANK1)),
("user_led", 1, Pins("M14"), IOStandard(LVCMOS_BANK1)),
("user_led", 2, Pins("N14"), IOStandard(LVCMOS_BANK1)),
("user_led", 3, Pins("L14"), IOStandard(LVCMOS_BANK1)),
("user_led", 4, Pins("M13"), IOStandard(LVCMOS_BANK1)),
("user_led", 5, Pins("D4"), IOStandard(LVCMOS_BANK0)),
("user_led", 6, Pins("P16"), IOStandard(LVCMOS_BANK1)),
("user_led", 7, Pins("N12"), IOStandard(LVCMOS_BANK2)),
## onBoard PUSH BUTTONS - FIXME
# Mapping "up" to north
# VCC1V8 - pulled down to GND via 10k
# NET "btn<1>" LOC = "N4"; # Bank = 3, Pin name = IO_L1P, Sch name = BTNU
("user_btn", 0, Pins("N4"), IOStandard(LVCMOS_BANK3)), # North button
# NET "btn<2>" LOC = "P4"; # Bank = 3, Pin name = IO_L2P, Sch name = BTNL
("user_btn", 1, Pins("P4"), IOStandard(LVCMOS_BANK3)), # East button
# NET "btn<3>" LOC = "P3"; # Bank = 3, Pin name = IO_L2N, Sch name = BTND
("user_btn", 2, Pins("P3"), IOStandard(LVCMOS_BANK3)), # South button
# NET "btn<4>" LOC = "F6"; # Bank = 3, Pin name = IO_L55P_M3A13, Sch name = BTNR
("user_btn", 3, Pins("F6"), IOStandard(LVCMOS_BANK3)), # West button
# NET "btn<5>" LOC = "F5"; # Bank = 3, Pin name = IO_L55N_M3A14, Sch name = BTNC
("user_btn", 4, Pins("F5"), IOStandard(LVCMOS_BANK3)), # Center button
## onBoard SWITCHES - FIXME
# SW(0,1,2,3) - VCC3V3 / GND
# SW(4,5,6) - VCCB2 / GND
# SW(7) - VCC1V8 / GND
# NET "sw<0>" LOC = "A10"; # Bank = 0, Pin name = IO_L37N_GCLK12, Sch name = SW0
# NET "sw<1>" LOC = "D14"; # Bank = 0, Pin name = IO_L65P_SCP3, Sch name = SW1
# NET "sw<2>" LOC = "C14"; # Bank = 0, Pin name = IO_L65N_SCP2, Sch name = SW2
# NET "sw<3>" LOC = "P15"; # Bank = 1, Pin name = IO_L74P_AWAKE_1, Sch name = SW3
# NET "sw<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4
# NET "sw<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
# NET "sw<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
# NET "sw<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
("user_sw", 0, Pins("A10"), IOStandard(LVCMOS_BANK0)),
("user_sw", 1, Pins("D14"), IOStandard(LVCMOS_BANK0)),
("user_sw", 2, Pins("C14"), IOStandard(LVCMOS_BANK0)),
("user_sw", 3, Pins("P15"), IOStandard(LVCMOS_BANK1)),
("user_sw", 4, Pins("P12"), IOStandard(LVCMOS_BANK2)),
("user_sw", 5, Pins("R5"), IOStandard(LVCMOS_BANK2)),
("user_sw", 6, Pins("T5"), IOStandard(LVCMOS_BANK2)),
("user_sw", 7, Pins("E4"), IOStandard(LVCMOS_BANK3)),
## TEMAC Ethernet MAC - FIXME
# 10/100/1000 Ethernet PHY
# 88E111-B2-RCJ1-C000 - Marvell Alaska Tri-mode PHY (the 88E1111)
# paired with a Halo HFJ11-1G01E RJ-45 connector
# Runs from 1.2V power supply
("eth_clocks", 0,
# NET "phytxclk" LOC = "K16"; # Bank = 1, Pin name = IO_L41N_GCLK8_M1CASN, Sch name = E-TXCLK
Subsignal("tx", Pins("K16")),
# NET "phygtxclk" LOC = "L12"; # Bank = 1, Pin name = IO_L40P_GCLK11_M1A5, Sch name = E-GTXCLK
Subsignal("gtx", Pins("L12")),
# NET "phyrxclk" LOC = "K15"; # Bank = 1, Pin name = IO_L41P_GCLK9_IRDY1_M1RASN, Sch name = E-RXCLK
Subsignal("rx", Pins("K15")),
IOStandard(LVCMOS_BANK1)
),
("eth", 0,
# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET
Subsignal("rst_n", Pins("G13")),
# NET "phyint" LOC = "L16"; # Bank = 1, Pin name = IO_L42N_GCLK6_TRDY1_M1LDM, Sch name = E-INT
Subsignal("int_n", Pins("L16")),
# NET "phymdi" LOC = "N17"; # Bank = 1, Pin name = IO_L48P_HDC_M1DQ8, Sch name = E-MDIO
Subsignal("mdio", Pins("N17")),
# NET "phymdc" LOC = "F16"; # Bank = 1, Pin name = IO_L1N_A24_VREF, Sch name = E-MDC
Subsignal("mdc", Pins("F16")),
# NET "phyrxdv" LOC = "F17"; # Bank = 1, Pin name = IO_L35P_A11_M1A7, Sch name = E-RXDV
Subsignal("rx_dv", Pins("F17")),
# NET "phyrxer" LOC = "F18"; # Bank = 1, Pin name = IO_L35N_A10_M1A2, Sch name = E-RXER
Subsignal("rx_er", Pins("F18")),
# NET "phyRXD<0>" LOC = "G16"; # Bank = 1, Pin name = IO_L38P_A5_M1CLK, Sch name = E-RXD0
# NET "phyRXD<1>" LOC = "H14"; # Bank = 1, Pin name = IO_L36N_A8_M1BA1, Sch name = E-RXD1
# NET "phyRXD<2>" LOC = "E16"; # Bank = 1, Pin name = IO_L33P_A15_M1A10, Sch name = E-RXD2
# NET "phyRXD<3>" LOC = "F15"; # Bank = 1, Pin name = IO_L1P_A25, Sch name = E-RXD3
# NET "phyRXD<4>" LOC = "F14"; # Bank = 1, Pin name = IO_L30P_A21_M1RESET, Sch name = E-RXD4
# NET "phyRXD<5>" LOC = "E18"; # Bank = 1, Pin name = IO_L33N_A14_M1A4, Sch name = E-RXD5
# NET "phyRXD<6>" LOC = "D18"; # Bank = 1, Pin name = IO_L31N_A18_M1A12, Sch name = E-RXD6
# NET "phyRXD<7>" LOC = "D17"; # Bank = 1, Pin name = IO_L31P_A19_M1CKE, Sch name = E-RXD7
Subsignal("rx_data", Pins("G16 H14 E16 F15 F14 E18 D18 D17")),
# NET "phytxen" LOC = "H15"; # Bank = 1, Pin name = IO_L37P_A7_M1A0, Sch name = E-TXEN
Subsignal("tx_en", Pins("H15")),
# NET "phytxer" LOC = "G18"; # Bank = 1, Pin name = IO_L38N_A4_M1CLKN, Sch name = E-TXER
Subsignal("tx_er", Pins("G18")),
# NET "phyTXD<0>" LOC = "H16"; # Bank = 1, Pin name = IO_L37N_A6_M1A1, Sch name = E-TXD0
# NET "phyTXD<1>" LOC = "H13"; # Bank = 1, Pin name = IO_L36P_A9_M1BA0, Sch name = E-TXD1
# NET "phyTXD<2>" LOC = "K14"; # Bank = 1, Pin name = IO_L39N_M1ODT, Sch name = E-TXD2
# NET "phyTXD<3>" LOC = "K13"; # Bank = 1, Pin name = IO_L34N_A12_M1BA2, Sch name = E-TXD3
# NET "phyTXD<4>" LOC = "J13"; # Bank = 1, Pin name = IO_L39P_M1A3, Sch name = E-TXD4
# NET "phyTXD<5>" LOC = "G14"; # Bank = 1, Pin name = IO_L30N_A20_M1A11, Sch name = E-TXD5
# NET "phyTXD<6>" LOC = "H12"; # Bank = 1, Pin name = IO_L32P_A17_M1A8, Sch name = E-TXD6
# NET "phyTXD<7>" LOC = "K12"; # Bank = 1, Pin name = IO_L34P_A13_M1WE, Sch name = E-TXD7
Subsignal("tx_data", Pins("H16 H13 K14 K13 J13 G14 H12 K12")),
# C17 - from Atlys reference manual, not listed in UCF file?
Subsignal("col", Pins("C17")),
# C18 - from Atlys reference manual, not listed in UCF file?
Subsignal("crs", Pins("C18")),
IOStandard(LVCMOS_BANK1)
),
## DDR2
# 128Mbyte DDR2 16-bit wide data @ 800MHz
# Older boards - MT47H64M16HR-25E - DDR2 - 2.5ns @ CL = 5 (DDR2-800)
# Newer boards - MIRA P3R1GE3EGF G8E DDR2 -
#
# The interface supports SSTL18 signaling. Address and control signals
# are terminated through 47-ohm resistors to a 0.9V VTT, and data
# signals use the On-Die-Termination (ODT) feature of the DDR2 chip.
#
# When generating a MIG core for the MIRA part, selecting the
# “EDE1116AXXX-8E” device will result in the correct timing parameters
# being set. When generating a component for the Micron part, it can be
# selected by name within the wizard. The part loaded on your Atlys can
# be determined by examining the print on the DDR2 component (IC13).
#
# NET "DDR2CLK0" LOC = "G3"; # Bank = 3, Pin name = IO_L46P_M3CLK, Sch name = DDR-CK_P
# NET "DDR2CLK1" LOC = "G1"; # Bank = 3, Pin name = IO_L46N_M3CLKN, Sch name = DDR-CK_N
("ddram_clock", 0,
Subsignal("p", Pins("G3")),
Subsignal("n", Pins("G1")),
IOStandard("DIFF_SSTL18_II"), Misc("IN_TERM=NONE")
),
("ddram", 0,
# NET "DDR2CKE" LOC = "H7"; # Bank = 3, Pin name = IO_L53P_M3CKE, Sch name = DDR-CKE
Subsignal("cke", Pins("H7"), IOStandard("SSTL18_II")),
# NET "DDR2RASN" LOC = "L5"; # Bank = 3, Pin name = IO_L43P_GCLK23_M3RASN, Sch name = DDR-RAS
Subsignal("ras_n", Pins("L5"), IOStandard("SSTL18_II")),
# NET "DDR2CASN" LOC = "K5"; # Bank = 3, Pin name = IO_L43N_GCLK22_IRDY2_M3CASN, Sch name = DDR-CAS
Subsignal("cas_n", Pins("K5"), IOStandard("SSTL18_II")),
# NET "DDR2WEN" LOC = "E3"; # Bank = 3, Pin name = IO_L50P_M3WE, Sch name = DDR-WE
Subsignal("we_n", Pins("E3"), IOStandard("SSTL18_II")),
# NET "DDR2BA0" LOC = "F2"; # Bank = 3, Pin name = IO_L48P_M3BA0, Sch name = DDR-BA0
# NET "DDR2BA1" LOC = "F1"; # Bank = 3, Pin name = IO_L48N_M3BA1, Sch name = DDR-BA1
# NET "DDR2BA2" LOC = "E1"; # Bank = 3, Pin name = IO_L50N_M3BA2, Sch name = DDR-BA2
Subsignal("ba", Pins("F2 F1 E1"), IOStandard("SSTL18_II")),
# NET "DDR2A0" LOC = "J7"; # Bank = 3, Pin name = IO_L47P_M3A0, Sch name = DDR-A0
# NET "DDR2A1" LOC = "J6"; # Bank = 3, Pin name = IO_L47N_M3A1, Sch name = DDR-A1
# NET "DDR2A2" LOC = "H5"; # Bank = 3, Pin name = IO_L49N_M3A2, Sch name = DDR-A2
# NET "DDR2A3" LOC = "L7"; # Bank = 3, Pin name = IO_L45P_M3A3, Sch name = DDR-A3
# NET "DDR2A4" LOC = "F3"; # Bank = 3, Pin name = IO_L51N_M3A4, Sch name = DDR-A4
# NET "DDR2A5" LOC = "H4"; # Bank = 3, Pin name = IO_L44P_GCLK21_M3A5, Sch name = DDR-A5
# NET "DDR2A6" LOC = "H3"; # Bank = 3, Pin name = IO_L44N_GCLK20_M3A6, Sch name = DDR-A6
# NET "DDR2A7" LOC = "H6"; # Bank = 3, Pin name = IO_L49P_M3A7, Sch name = DDR-A7
# NET "DDR2A8" LOC = "D2"; # Bank = 3, Pin name = IO_L52P_M3A8, Sch name = DDR-A8
# NET "DDR2A9" LOC = "D1"; # Bank = 3, Pin name = IO_L52N_M3A9, Sch name = DDR-A9
# NET "DDR2A10" LOC = "F4"; # Bank = 3, Pin name = IO_L51P_M3A10, Sch name = DDR-A10
# NET "DDR2A11" LOC = "D3"; # Bank = 3, Pin name = IO_L54N_M3A11, Sch name = DDR-A11
# NET "DDR2A12" LOC = "G6"; # Bank = 3, Pin name = IO_L53N_M3A12, Sch name = DDR-A12
Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6"), IOStandard("SSTL18_II")),
# NET "DDR2DQ0" LOC = "L2"; # Bank = 3, Pin name = IO_L37P_M3DQ0, Sch name = DDR-DQ0
# NET "DDR2DQ1" LOC = "L1"; # Bank = 3, Pin name = IO_L37N_M3DQ1, Sch name = DDR-DQ1
# NET "DDR2DQ2" LOC = "K2"; # Bank = 3, Pin name = IO_L38P_M3DQ2, Sch name = DDR-DQ2
# NET "DDR2DQ3" LOC = "K1"; # Bank = 3, Pin name = IO_L38N_M3DQ3, Sch name = DDR-DQ3
# NET "DDR2DQ4" LOC = "H2"; # Bank = 3, Pin name = IO_L41P_GCLK27_M3DQ4, Sch name = DDR-DQ4
# NET "DDR2DQ5" LOC = "H1"; # Bank = 3, Pin name = IO_L41N_GCLK26_M3DQ5, Sch name = DDR-DQ5
# NET "DDR2DQ6" LOC = "J3"; # Bank = 3, Pin name = IO_L40P_M3DQ6, Sch name = DDR-DQ6
# NET "DDR2DQ7" LOC = "J1"; # Bank = 3, Pin name = IO_L40N_M3DQ7, Sch name = DDR-DQ7
# NET "DDR2DQ8" LOC = "M3"; # Bank = 3, Pin name = IO_L36P_M3DQ8, Sch name = DDR-DQ8
# NET "DDR2DQ9" LOC = "M1"; # Bank = 3, Pin name = IO_L36N_M3DQ9, Sch name = DDR-DQ9
# NET "DDR2DQ10" LOC = "N2"; # Bank = 3, Pin name = IO_L35P_M3DQ10, Sch name = DDR-DQ10
# NET "DDR2DQ11" LOC = "N1"; # Bank = 3, Pin name = IO_L35N_M3DQ11, Sch name = DDR-DQ11
# NET "DDR2DQ12" LOC = "T2"; # Bank = 3, Pin name = IO_L33P_M3DQ12, Sch name = DDR-DQ12
# NET "DDR2DQ13" LOC = "T1"; # Bank = 3, Pin name = IO_L33N_M3DQ13, Sch name = DDR-DQ13
# NET "DDR2DQ14" LOC = "U2"; # Bank = 3, Pin name = IO_L32P_M3DQ14, Sch name = DDR-DQ14
# NET "DDR2DQ15" LOC = "U1"; # Bank = 3, Pin name = IO_L32N_M3DQ15, Sch name = DDR-DQ15
Subsignal("dq", Pins(
"L2 L1 K2 K1 H2 H1 J3 J1",
"M3 M1 N2 N1 T2 T1 U2 U1"), IOStandard("SSTL18_II")),
# U == Upper, L == Lower
# NET "DDR2UDQS" LOC="P2"; # Bank = 3, Pin name = IO_L34P_M3UDQS, Sch name = DDR-UDQS_P
# NET "DDR2UDQSN" LOC="P1"; # Bank = 3, Pin name = IO_L34N_M3UDQSN, Sch name = DDR-UDQS_N
# NET "DDR2LDQS" LOC="L4"; # Bank = 3, Pin name = IO_L39P_M3LDQS, Sch name = DDR-LDQS_P
# NET "DDR2LDQSN" LOC="L3"; # Bank = 3, Pin name = IO_L39N_M3LDQSN, Sch name = DDR-LDQS_N
Subsignal("dqs", Pins("P2 L4"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dqs_n", Pins("P1 L3"), IOStandard("DIFF_SSTL18_II")),
# NET "DDR2UDM" LOC="K4"; # Bank = 3, Pin name = IO_L42P_GCLK25_TRDY2_M3UDM, Sch name = DDR-UDM
# NET "DDR2LDM" LOC="K3"; # Bank = 3, Pin name = IO_L42N_GCLK24_M3LDM, Sch name = DDR-LDM
Subsignal("dm", Pins("K4 K3"), IOStandard("SSTL18_II")),
# NET "DDR2ODT" LOC="K6"; # Bank = 3, Pin name = IO_L45N_M3ODT, Sch name = DDR-ODT
Subsignal("odt", Pins("K6"), IOStandard("SSTL18_II"))
),
## onboard HDMI OUT
# Type A connector, marked as J2 on the board, next to the power connector.
# Buffered / protected with TMDS141RHAR
# NET "HDMIOUTCLKP" LOC = "B6"; # Bank = 0, Pin name = IO_L8P, Sch name = TMDS-TX-CLK_P
# NET "HDMIOUTCLKN" LOC = "A6"; # Bank = 0, Pin name = IO_L8N_VREF, Sch name = TMDS-TX-CLK_N
# NET "HDMIOUTD0P" LOC = "D8"; # Bank = 0, Pin name = IO_L11P, Sch name = TMDS-TX-0_P
# NET "HDMIOUTD0N" LOC = "C8"; # Bank = 0, Pin name = IO_L11N, Sch name = TMDS-TX-0_N
# NET "HDMIOUTD1P" LOC = "C7"; # Bank = 0, Pin name = IO_L10P, Sch name = TMDS-TX-1_P
# NET "HDMIOUTD1N" LOC = "A7"; # Bank = 0, Pin name = IO_L10N, Sch name = TMDS-TX-1_N
# NET "HDMIOUTD2P" LOC = "B8"; # Bank = 0, Pin name = IO_L33P, Sch name = TMDS-TX-2_P
# NET "HDMIOUTD2N" LOC = "A8"; # Bank = 0, Pin name = IO_L33N, Sch name = TMDS-TX-2_N
# NET "HDMIOUTSCL" LOC = "D9"; # Bank = 0, Pin name = IO_L34P_GCLK19, Sch name = TMDS-TX-SCL
# NET "HDMIOUTSDA" LOC = "C9"; # Bank = 0, Pin name = IO_L34N_GCLK18, Sch name = TMDS-TX-SDA
("hdmi_out", 0,
Subsignal("clk_p", Pins("B6"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("A6"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("D8"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("C8"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("C7"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("A7"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("B8"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("A8"), IOStandard("TMDS_33")),
# Disconnect JP6 and JP7 for FPGA SCL/SDA control, otherwise
# this is connected to J3's SCL/SDA pins.
Subsignal("scl", Pins("D9"), IOStandard("I2C")),
Subsignal("sda", Pins("C9"), IOStandard("I2C")),
),
## onboard HDMI IN1 (PMODA)
# Type A connector, marked as J1, on side with USB connectors.
# Buffered / protected with TMDS141RHAR
# JP4 connects / disconnects 5V to HDMI pin 18, for input to work make
# sure it is connected.
# NET "HDMIIN1CLKP" LOC = "D11"; # Bank = 0, Pin name = IO_L36P_GCLK15, Sch name = TMDS-RXB-CLK_P
# NET "HDMIIN1CLKN" LOC = "C11"; # Bank = 0, Pin name = IO_L36N_GCLK14, Sch name = TMDS-RXB-CLK_N
# NET "HDMIIN1D0P" LOC = "G9"; # Bank = 0, Pin name = IO_L38P, Sch name = TMDS-RXB-0_P
# NET "HDMIIN1D0N" LOC = "F9"; # Bank = 0, Pin name = IO_L38N_VREF, Sch name = TMDS-RXB-0_N
# NET "HDMIIN1D1P" LOC = "B11"; # Bank = 0, Pin name = IO_L39P, Sch name = TMDS-RXB-1_P
# NET "HDMIIN1D1N" LOC = "A11"; # Bank = 0, Pin name = O_L39N, Sch name = TMDS-RXB-1_N
# NET "HDMIIN1D2P" LOC = "B12"; # Bank = 0, Pin name = IO_L41P, Sch name = TMDS-RXB-2_P
# NET "HDMIIN1D2N" LOC = "A12"; # Bank = 0, Pin name = IO_L41N, Sch name = TMDS-RXB-2_N
# NET "HDMIIN1SCL" LOC = "C13"; # Bank = 0, Pin name = IO_L50P, Sch name = PMOD-SCL
# NET "HDMIIN1SDA" LOC = "A13"; # Bank = 0, Pin name = IO_L50N, Sch name = PMOD-SDA
("hdmi_in", 0,
Subsignal("clk_p", Pins("D11")),
Subsignal("clk_n", Pins("C11")),
Subsignal("data0_p", Pins("G9")),
Subsignal("data0_n", Pins("F9")),
Subsignal("data1_p", Pins("B11")),
Subsignal("data1_n", Pins("A11")),
Subsignal("data2_p", Pins("B12")),
Subsignal("data2_n", Pins("A12")),
# Make sure JP2 is connected. Shared with J1.
Subsignal("scl", Pins("C13"), IOStandard(LVCMOS_BANK0)),
Subsignal("sda", Pins("A13"), IOStandard(LVCMOS_BANK0)),
#Subsignal("hpd_notif", Pins("G22"), IOStandard("LVCMOS33")),
#Subsignal("hpd_en", Pins("G17"), IOStandard("LVCMOS33"))
),
## onboard HDMI IN2
# Type A connector, marked as J3, between audio connectors and Ethernet
# RJ45 connector.
# Buffered / protected with a TMDS141RHAR
# JP8 connects / disconnects 5V to HDMI pin 18, for input to work make
# sure it is connected.
# NET "HDMIIN2CLKP" LOC = "H17"; # Bank = 1, Pin name = IO_L43P_GCLK5_M1DQ4, Sch name = TMDS-RX-CLK_P
# NET "HDMIIN2CLKN" LOC = "H18"; # Bank = 1, Pin name = IO_L43N_GCLK4_M1DQ5, Sch name = TMDS-RX-CLK_N
# NET "HDMIIN2D0P" LOC = "K17"; # Bank = 1, Pin name = IO_L45P_A1_M1LDQS, Sch name = TMDS-RX-0_P
# NET "HDMIIN2D0N" LOC = "K18"; # Bank = 1, Pin name = IO_L45N_A0_M1LDQSN, Sch name = TMDS-RX-0_N
# NET "HDMIIN2D1P" LOC = "L17"; # Bank = 1, Pin name = IO_L46P_FCS_B_M1DQ2, Sch name = TMDS-RX-1_P
# NET "HDMIIN2D1N" LOC = "L18"; # Bank = 1, Pin name = IO_L46N_FOE_B_M1DQ3, Sch name = TMDS-RX-1_N
# NET "HDMIIN2D2P" LOC = "J16"; # Bank = 1, Pin name = IO_L44P_A3_M1DQ6, Sch name = TMDS-RX-2_P
# NET "HDMIIN2D2N" LOC = "J18"; # Bank = 1, Pin name = IO_L44N_A2_M1DQ7, Sch name = TMDS-RX-2_N
# NET "HDMIIN2SCL" LOC = "M16"; # Bank = 1, Pin name = IO_L47P_FWE_B_M1DQ0, Sch name = TMDS-RX-SCL
# NET "HDMIIN2SDA" LOC = "M18"; # Bank = 1, Pin name = IO_L47N_LDC_M1DQ1, Sch name = TMDS-RX-SDA
("hdmi_in", 1,
Subsignal("clk_p", Pins("H17")),
Subsignal("clk_n", Pins("H18")),
Subsignal("data0_p", Pins("K17")),
Subsignal("data0_n", Pins("K18")),
Subsignal("data1_p", Pins("L17")),
Subsignal("data1_n", Pins("L18")),
Subsignal("data2_p", Pins("J16")),
Subsignal("data2_n", Pins("J18")),
# Disconnect JP6 and JP7 for FPGA SCL/SDA control, otherwise
# this is connected to J2's SCL/SDA pins.
Subsignal("scl", Pins("M16"), IOStandard(LVCMOS_BANK1)),
Subsignal("sda", Pins("M18"), IOStandard(LVCMOS_BANK1)),
#Subsignal("hpd_notif", Pins("G16"), IOStandard("LVCMOS33")),
#Subsignal("hpd_en", Pins("B20"), IOStandard("LVCMOS33"))
),
## onboard USB Host Controller - FIXME
# PIC32MX440F256H-40I/MR
# USB-HID port (for mouse/keyboard)
# PS/2 Keyboard - K_CLK - P17
# PS/2 Keyboard - K_DAT - N15
# PS/2 Mouse - M_CLK - N18
# PS/2 Mouse - M_DAT - P18
# FPGA Serial programming - DIN - R13
# FPGA Serial programming - CLK - R15
# NET "USBCLK" LOC = "P17"; # Bank = 1, Pin name = IO_L49P_M1DQ10, Sch name = PIC32-SCK1
# NET "USBSDI" LOC = "N15"; # Bank = 1, Pin name = IO_L50P_M1UDQS, Sch name = PIC32-SDI1
# NET "USBSS" LOC = "P18"; # Bank = 1, Pin name = IO_L49N_M1DQ11, Sch name = PIC32-SS1
# NET "USBSDO" LOC = "N18"; # Bank = 1, Pin name = IO_L48N_M1DQ9, Sch name = PIC32-SDO1
## Audio - FIXME
# National Semiconductor - LM4550VH
# AC-97 Codec with line-in, line-out, mic, & headphone
# Audio
# NET "BITCLK" LOC = "L13"; # Bank = 1, Pin name = IO_L40N_GCLK10_M1A6, Sch name = AUD-BIT-CLK
# NET "AUDSYNC" LOC = "U17"; # Bank = 1, Pin name = IO_L52P_M1DQ14, Sch name = AUD-SYNC
# NET "AUDRST" LOC = "T17"; # Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = AUD-RESET
# NET "AUDSDI" LOC = "T18"; # Bank = 1, Pin name = IO_L51N_M1DQ13, Sch name = AUD-SDI
# NET "AUDSDO" LOC = "N16"; # Bank = 1, Pin name = IO_L50N_M1UDQSN, Sch name = AUD-SDO
## USB UART Connector
# USB Micro B port marked as UART between HDMI connector and USB A connector.
# XR21V1410IL16 - Vizzini USB Serial - https://github.com/shenki/exar-uart-driver
# NET "UartRx" LOC = "A16"; # Bank = 0, Pin name = IO_L66N_SCP0, Sch name = USBB-RXD
# NET "UartTx" LOC = "B16"; # Bank = 0, Pin name = IO_L66P_SCP1, Sch name = USBB-TXD
("serial", 0,
Subsignal("rx", Pins("A16"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("B16"), IOStandard("LVCMOS33")),
),
# ("fpga_cfg",
# Subsignal("din", Pins("T14")),
# Subsignal("cclk", Pins("R14")),
# Subsignal("init_b", Pins("T12")),
# Subsignal("prog_b", Pins("A2")),
# Subsignal("done", Pins("T15")),
# ),
# ("jtag",
# Subsignal("tms", Pins("B2")),
# Subsignal("tdo", Pins("B16")),
# Subsignal("tdi", Pins("B1")),
# Subsignal("tck", Pins("A15")),
# ),
]
# This Micro-D HDMI connector only works when VCCB2 is set to 3V3.
_io_vccb2_3v3 = [
## PMOD Connector
# Micro-D connector, marked as JB, on the same side as switches + LEDs
# but on the underside of the board below MOD connector. Works as
# either output or input because it isn't buffered. Also often referred
# to as "JA".
# JP12 connects VCC to 3.3V or 2.5V, make sure 3.3V is selected.
# JP3 connects / disconnects 5V to HDMI pin 19.
# * To use as output, remove the jumper.
# * To use as input, make sure it is connected.
# NET "JB<5>" LOC = "T9"; # Bank = 2, Pin name = IO_L32P_GCLK29, Sch name = JA-CLK_P
# NET "JB<4>" LOC = "V9"; # Bank = 2, Pin name = IO_L32N_GCLK28, Sch name = JA-CLK_N
# NET "JB<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, Sch name = JA-D0_P
# NET "JB<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, Sch name = JA-D0_N
# NET "JB<7>" LOC = "T4"; # Bank = 2, Pin name = IO_L63P, Sch name = JA-D1_P
# NET "JB<6>" LOC = "V4"; # Bank = 2, Pin name = IO_L63N, Sch name = JA-D1_N
# NET "JB<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, Sch name = JA-D2_P
# NET "JB<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, Sch name = JA-D2_N
("hdmi_out", 1,
Subsignal("clk_p", Pins("T9"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("V9"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("R3"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("T3"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("T4"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("V4"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("N5"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("P6"), IOStandard("TMDS_33")),
# Make sure JP2 is connected. Shared with JA.
#Subsignal("scl", Pins("C13"), IOStandard("LVCMOS33")),
#Subsignal("sda", Pins("A13"), IOStandard("LVCMOS33")),
),
]
_io_vccb2_2v5 = []
_connectors = [
## onboard VHDCI - FIXME
# Can either run at 2.5V or 3.3V dependent on JP12 connector.
# Channel 1 connects to P signals, Channel 2 to N signals
# NET "VHDCIIO1<0>" LOC = "U16"; # Bank = 2, Pin name = IO_L2P_CMPCLK, Sch name = EXP-IO1_P
# NET "VHDCIIO1<1>" LOC = "U15"; # Bank = 2, Pin name = *IO_L5P, Sch name = EXP-IO2_P
# NET "VHDCIIO1<2>" LOC = "U13"; # Bank = 2, Pin name = IO_L14P_D11, Sch name = EXP-IO3_P
# NET "VHDCIIO1<3>" LOC = "M11"; # Bank = 2, Pin name = *IO_L15P, Sch name = EXP-IO4_P
# NET "VHDCIIO1<4>" LOC = "R11"; # Bank = 2, Pin name = IO_L16P, Sch name = EXP-IO5_P
# NET "VHDCIIO1<5>" LOC = "T12"; # Bank = 2, Pin name = *IO_L19P, Sch name = EXP-IO6_P
# NET "VHDCIIO1<6>" LOC = "N10"; # Bank = 2, Pin name = *IO_L20P, Sch name = EXP-IO7_P
# NET "VHDCIIO1<7>" LOC = "M10"; # Bank = 2, Pin name = *IO_L22P, Sch name = EXP-IO8_P
# NET "VHDCIIO1<8>" LOC = "U11"; # Bank = 2, Pin name = IO_L23P, Sch name = EXP-IO9_P
# NET "VHDCIIO1<9>" LOC = "R10"; # Bank = 2, Pin name = IO_L29P_GCLK3, Sch name = EXP-IO10_P
# NET "VHDCIIO1<10>" LOC = "U10"; # Bank = 2, Pin name = IO_L30P_GCLK1_D13, Sch name = EXP-IO11_P
# NET "VHDCIIO1<11>" LOC = "R8"; # Bank = 2, Pin name = IO_L31P_GCLK31_D14, Sch name = EXP-IO12_P
# NET "VHDCIIO1<12>" LOC = "M8"; # Bank = 2, Pin name = *IO_L40P, Sch name = EXP-IO13_P
# NET "VHDCIIO1<13>" LOC = "U8"; # Bank = 2, Pin name = IO_L41P, Sch name = EXP-IO14_P
# NET "VHDCIIO1<14>" LOC = "U7"; # Bank = 2, Pin name = IO_L43P, Sch name = EXP-IO15_P
# NET "VHDCIIO1<15>" LOC = "N7"; # Bank = 2, Pin name = *IO_L44P, Sch name = EXP-IO16_P
# NET "VHDCIIO1<16>" LOC = "T6"; # Bank = 2, Pin name = IO_L45P, Sch name = EXP-IO17_P
# NET "VHDCIIO1<17>" LOC = "R7"; # Bank = 2, Pin name = IO_L46P, Sch name = EXP-IO18_P
# NET "VHDCIIO1<18>" LOC = "N6"; # Bank = 2, Pin name = *IO_L47P, Sch name = EXP-IO19_P
# NET "VHDCIIO1<19>" LOC = "U5"; # Bank = 2, Pin name = IO_49P_D3, Sch name = EXP-IO20_P
# --
# NET "VHDCIIO2<0>" LOC = "V16"; # Bank = 2, Pin name = IO_L2N_CMPMOSI, Sch name = EXP-IO1_N
# NET "VHDCIIO2<1>" LOC = "V15"; # Bank = 2, Pin name = *IO_L5N, Sch name = EXP-IO2_N
# NET "VHDCIIO2<2>" LOC = "V13"; # Bank = 2, Pin name = IO_L14N_D12, Sch name = EXP-IO3_N
# NET "VHDCIIO2<3>" LOC = "N11"; # Bank = 2, Pin name = *IO_L15N, Sch name = EXP-IO4_N
# NET "VHDCIIO2<4>" LOC = "T11"; # Bank = 2, Pin name = IO_L16N_VREF, Sch name = EXP-IO5_N
# NET "VHDCIIO2<5>" LOC = "V12"; # Bank = 2, Pin name = *IO_L19N, Sch name = EXP-IO6_N
# NET "VHDCIIO2<6>" LOC = "P11"; # Bank = 2, Pin name = *IO_L20N, Sch name = EXP-IO7_N
# NET "VHDCIIO2<7>" LOC = "N9"; # Bank = 2, Pin name = *IO_L22N, Sch name = EXP-IO8_N
# NET "VHDCIIO2<8>" LOC = "V11"; # Bank = 2, Pin name = IO_L23N, Sch name = EXP-IO9_N
# NET "VHDCIIO2<9>" LOC = "T10"; # Bank = 2, Pin name = IO_L29N_GCLK2, Sch name = EXP-IO10_N
# NET "VHDCIIO2<10>" LOC = "V10"; # Bank = 2, Pin name = IO_L30N_GCLK0_USERCCLK, Sch name = EXP-IO11_N
# NET "VHDCIIO2<11>" LOC = "T8"; # Bank = 2, Pin name = IO_L31N_GCLK30_D15, Sch name = EXP-IO12_N
# NET "VHDCIIO2<12>" LOC = "N8"; # Bank = 2, Pin name = *IO_L40N, Sch name = EXP-IO13_N
# NET "VHDCIIO2<13>" LOC = "V8"; # Bank = 2, Pin name = IO_L41N_VREF, Sch name = EXP-IO14_N
# NET "VHDCIIO2<14>" LOC = "V7"; # Bank = 2, Pin name = IO_L43N, Sch name = EXP-IO15_N
# NET "VHDCIIO2<15>" LOC = "P8"; # Bank = 2, Pin name = *IO_L44N, Sch name = EXP-IO16_N
# NET "VHDCIIO2<16>" LOC = "V6"; # Bank = 2, Pin name = IO_L45N, Sch name = EXP-IO17_N
# NET "VHDCIIO2<17>" LOC = "T7"; # Bank = 2, Pin name = IO_L46N, Sch name = EXP-IO18_N
# NET "VHDCIIO2<18>" LOC = "P7"; # Bank = 2, Pin name = *IO_L47N, Sch name = EXP-IO19_N
# NET "VHDCIIO2<19>" LOC = "V5"; # Bank = 2, Pin name = IO_49N_D4, Sch name = EXP-IO20_N
("VHDCI",
{
"EXP-IO1_P": "U16",
"EXP-IO2_P": "U15",
"EXP-IO3_P": "U13",
"EXP-IO4_P": "M11",
"EXP-IO5_P": "R11",
"EXP-IO6_P": "T12",
"EXP-IO7_P": "N10",
"EXP-IO8_P": "M10",
"EXP-IO9_P": "U11",
"EXP-IO10_P": "R10",
"EXP-IO11_P": "U10",
"EXP-IO12_P": "R8",
"EXP-IO13_P": "M8",
"EXP-IO14_P": "U8",
"EXP-IO15_P": "U7",
"EXP-IO16_P": "N7",
"EXP-IO17_P": "T6",
"EXP-IO18_P": "R7",
"EXP-IO19_P": "N6",
"EXP-IO20_P": "U5",
"EXP-IO1_N": "V16",
"EXP-IO2_N": "V15",
"EXP-IO3_N": "V13",
"EXP-IO4_N": "N11",
"EXP-IO5_N": "T11",
"EXP-IO6_N": "V12",
"EXP-IO7_N": "P11",
"EXP-IO8_N": "N9",
"EXP-IO9_N": "V11",
"EXP-IO10_N": "T10",
"EXP-IO11_N": "V10",
"EXP-IO12_N": "T8",
"EXP-IO13_N": "N8",
"EXP-IO14_N": "V8",
"EXP-IO15_N": "V7",
"EXP-IO16_N": "P8",
"EXP-IO17_N": "V6",
"EXP-IO18_N": "T7",
"EXP-IO19_N": "P7",
"EXP-IO20_N": "V5",
}
),
]
_hdmi_infos = {
"HDMI_IN0_MNEMONIC": "J1",
"HDMI_IN0_DESCRIPTION" : (
" Type A connector, marked as J1, on side with USB connectors.\\r\\n"
" To use J1, make sure:\\r\\n"
" * JP4 has a jumper (it connects / disconnects 5V to HDMI pin 18).\\r\\n"
" * JP2 (marked only as SDA/SCL - not to be confused with JP6 and JP6)\\r\\n"
" has *two* jumpers (horizontally).\\r\\n"
" * JP5 has a jumper (it enables the HDMI input buffer).\\r\\n"
),
"HDMI_IN1_MNEMONIC": "J3",
"HDMI_IN1_DESCRIPTION" : (
" Type A connector, marked as J3, between audio connectors and\\r\\n"
" Ethernet RJ45 connector.\\r\\n"
" To use J3, make sure:\\r\\n"
" * JP8 has a jumper (it connects / disconnects 5V to HDMI pin 18)\\r\\n"
" * JP6 and JP7 do *not* have any jumpers (it connect J3's and J2's\\r\\n"
" EDID lines together).\\r\\n"
),
"HDMI_OUT0_MNEMONIC": "J2",
"HDMI_OUT0_DESCRIPTION" : (
" Type A connector, marked as J2, next to the power connector.\\r\\n"
" To use J2, make sure:\\r\\n"
" * JP8 has a jumper (it connects / disconnects 5V to HDMI pin 18)\\r\\n"
" * JP6 and JP7 do *not* have any jumpers (it connect J3's and J2's\\r\\n"
" EDID lines together).\\r\\n"
),
"HDMI_OUT1_MNEMONIC": "JB",
"HDMI_OUT1_DESCRIPTION" : (
" Micro-D connector, marked as JB, on the same side as switches\\r\\n"
" + LEDs but on the underside of the board below MOD connector.\\r\\n"
" Works as either output or input because it isn't buffered.\\r\\n"
" Also often referred to as 'JA'.\\r\\n"
)
}
class Platform(XilinxPlatform):
name = "atlys"
default_clk_name = "clk100"
default_clk_period = 10.0
hdmi_infos = _hdmi_infos
# https://reference.digilentinc.com/atlys:atlys:refmanual#flash_memory
# The Atlys has a XC6SLX45 which bitstream takes up ~12Mbit (1484472 bytes)
# 0x200000 offset (16Mbit) gives plenty of space
gateware_size = 0x200000
# Micron N25Q128 (ID 0x0018ba20)
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_model = "n25q128"
spiflash_read_dummy_bits = 10
spiflash_clock_div = 4
spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
def __init__(self, programmer="openocd", vccb2_voltage="VCC3V3"):
# Some IO configurations only work at certain vccb2 voltages.
if vccb2_voltage == "VCC3V3":
_io.extend(_io_vccb2_3v3)
elif vccb2_voltage == "VCC2V5":
_io.extend(_io_vccb2_2v5)
else:
raise SystemError("Unknown vccb2_voltage=%r" % vccb2_voltage)
# Resolve the LVCMOS_BANK2 voltage level before anything uses the _io
# definition.
LVCMOS_BANK2.set(vccb2_voltage)
# XC6SLX45-2CSG324C
XilinxPlatform.__init__(self, "xc6slx45-csg324-3", _io, _connectors)
self.programmer = programmer
# FPGA AUX is connected to the 3.3V supply on the Atlys
self.add_platform_command("""CONFIG VCCAUX="3.3";""")
def create_programmer(self):
# Preferred programmer - Needs ixo-usb-jtag and latest openocd.
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
if self.programmer == "openocd":
return OpenOCD(config="board/digilent_atlys.cfg", flash_proxy_basename=proxy)
# Alternative programmers - not regularly tested.
elif self.programmer == "xc3sprog":
return XC3SProg("jtaghs1_fast", "bscan_spi_digilent_atlys.bit")
elif self.programmer == "impact":
return iMPACT()
elif self.programmer == "adept":
return Adept("Atlys", 0)
elif self.programmer == "fpgalink":
from mibuild.fpgalink_programmer import FPGALink
return FPGALink("1443:0007")
elif self.programmer == "urjtag":
return UrJTAG(cable="USBBlaster", pld="spartan-6")
else:
raise ValueError("{} programmer is not supported".format(self.programmer))
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
# The oscillator clock sources.
try:
self.add_period_constraint(self.lookup_request("clk100"), 10.0)
except ConstraintError:
pass
# HDMI input clock pins.
for i in range(2):
try:
self.add_period_constraint(self.lookup_request("hdmi_in", i).clk_p, 12)
except ConstraintError:
pass
# Ethernet input clock pins.
try:
self.add_period_constraint(self.lookup_request("eth_clocks").rx, 40.0)
except ConstraintError:
pass
# USB input clock pins.
try:
self.add_period_constraint(self.lookup_request("fx2").ifclk, 10)
except ConstraintError:
pass
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.iMPACT",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((37550, 37618), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx45-csg324-3"""', '_io', '_connectors'], {}), "(self, 'xc6slx45-csg324-3', _io, _connectors)\n", (37573, 37618), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38798, 38840), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (38824, 38840), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38313, 38321), 'litex.build.xilinx.iMPACT', 'iMPACT', ([], {}), '()\n', (38319, 38321), False, 'from litex.build.xilinx import XilinxPlatform, iMPACT\n'), ((38524, 38545), 'mibuild.fpgalink_programmer.FPGALink', 'FPGALink', (['"""1443:0007"""'], {}), "('1443:0007')\n", (38532, 38545), False, 'from mibuild.fpgalink_programmer import FPGALink\n')] |
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.openocd import OpenOCD
from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer
_io = [
("user_led", 0, Pins("H5"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("J5"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T9"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("T10"), IOStandard("LVCMOS33")),
("rgb_leds", 0,
Subsignal("r", Pins("G6 G3 J3 K1")),
Subsignal("g", Pins("F6 J4 J2 H6")),
Subsignal("b", Pins("E1 G4 H4 K2")),
IOStandard("LVCMOS33")
),
("user_sw", 0, Pins("A8"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("C11"), IOStandard("LVCMOS33")),
("user_sw", 2, Pins("C10"), IOStandard("LVCMOS33")),
("user_sw", 3, Pins("A10"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("D9"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("C9"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("B9"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("B8"), IOStandard("LVCMOS33")),
("clk100", 0, Pins("E3"), IOStandard("LVCMOS33")),
("cpu_reset", 0, Pins("C2"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("D10")),
Subsignal("rx", Pins("A9")),
IOStandard("LVCMOS33")),
("spiflash_4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
("spiflash_1x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("L13")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),
Subsignal("hold", Pins("M14")),
IOStandard("LVCMOS33")
),
("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),
("ddram", 0,
Subsignal("a", Pins(
"R2 M6 N4 T1 N6 R7 V6 U7",
"R8 V7 R6 U6 T6 T8"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("R1 P4 P2"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P3"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("M4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("P5"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("U8"), IOStandard("SSTL15")),
Subsignal("dm", Pins("L1 U1"), IOStandard("SSTL15")),
Subsignal("dq", Pins(
"K5 L3 K3 L6 M3 M1 L4 M2",
"V4 T5 U4 V5 V1 T3 U3 R3"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_40")),
Subsignal("dqs_p", Pins("N2 U2"), IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("N1 V2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("U9"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("V9"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("N5"), IOStandard("SSTL15")),
Subsignal("odt", Pins("R5"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("K6"), IOStandard("SSTL15")),
Misc("SLEW=FAST"),
),
("eth_clocks", 0,
Subsignal("tx", Pins("H16")),
Subsignal("rx", Pins("F15")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("C16")),
Subsignal("mdio", Pins("K13")),
Subsignal("mdc", Pins("F16")),
Subsignal("rx_dv", Pins("G16")),
Subsignal("rx_er", Pins("C17")),
Subsignal("rx_data", Pins("D18 E17 E18 G17")),
Subsignal("tx_en", Pins("H15")),
Subsignal("tx_data", Pins("H14 J14 J13 H17")),
Subsignal("col", Pins("D17")),
Subsignal("crs", Pins("G14")),
IOStandard("LVCMOS33")
),
]
class Platform(XilinxPlatform):
name = "arty"
default_clk_name = "clk100"
default_clk_period = 10.0
# From https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
# 17536096 bits == 2192012 == 0x21728c -- Therefore 0x220000
gateware_size = 0x220000
# Micron N25Q128A13ESF40 (ID 0x0018ba20)
# FIXME: Create a "spi flash module" object in the same way we have SDRAM
# module objects.
spiflash_model = "n25q128a13"
spiflash_read_dummy_bits = 10
spiflash_clock_div = 2
spiflash_total_size = int((128/8)*1024*1024) # 128Mbit
spiflash_page_size = 256
spiflash_sector_size = 0x10000
def __init__(self, toolchain="vivado", programmer="openocd"):
XilinxPlatform.__init__(self, "xc7a35t-csg324-1", _io,
toolchain=toolchain)
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
if self.programmer == "openocd":
proxy="bscan_spi_{}.bit".format(self.device.split('-')[0])
return OpenOCD(config="board/digilent_arty.cfg", flash_proxy_basename=proxy)
elif self.programmer == "xc3sprog":
return XC3SProg("nexys4")
elif self.programmer == "vivado":
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
else:
raise ValueError("{} programmer is not supported"
.format(self.programmer))
| [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XC3SProg",
"litex.build.xilinx.VivadoProgrammer"
] | [((4558, 4633), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35t-csg324-1"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xc7a35t-csg324-1', _io, toolchain=toolchain)\n", (4581, 4633), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((5276, 5345), 'litex.build.openocd.OpenOCD', 'OpenOCD', ([], {'config': '"""board/digilent_arty.cfg"""', 'flash_proxy_basename': 'proxy'}), "(config='board/digilent_arty.cfg', flash_proxy_basename=proxy)\n", (5283, 5345), False, 'from litex.build.openocd import OpenOCD\n'), ((5409, 5427), 'litex.build.xilinx.XC3SProg', 'XC3SProg', (['"""nexys4"""'], {}), "('nexys4')\n", (5417, 5427), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n'), ((5489, 5545), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""n25q128-3.3v-spi-x1_x2_x4"""'}), "(flash_part='n25q128-3.3v-spi-x1_x2_x4')\n", (5505, 5545), False, 'from litex.build.xilinx import XilinxPlatform, XC3SProg, VivadoProgrammer\n')] |
#!/usr/bin/env python3
import time
import random
from operator import or_
from functools import reduce
from utils import memfill, memcheck
################################################################################
class DRAMAddressConverter:
def __init__(self, colbits=10, rowbits=14, bankbits=3,
address_mapping='ROW_BANK_COL', address_align=3):
# FIXME: generate these from BaseSoC
# soc.sdram.controller.settings
self.colbits = colbits
self.rowbits = rowbits
self.bankbits = bankbits
self.address_mapping = address_mapping
self.address_align = address_align
assert self.address_mapping == 'ROW_BANK_COL'
def _encode(self, bank, row, col):
assert bank < 2**self.bankbits
assert col < 2**self.colbits
assert row < 2**self.rowbits
def masked(value, width, offset):
masked = value & (2**width - 1)
assert masked == value, "Value larger than value bit-width"
return masked << offset
return reduce(or_, [
masked(row, self.rowbits, self.bankbits + self.colbits),
masked(bank, self.bankbits, self.colbits),
masked(col, self.colbits, 0),
])
def encode_bus(self, *, bank, row, col, base=0x40000000, bus_align=2):
assert bus_align <= self.address_align
address = self._encode(bank, row, col)
return base + (address << (self.address_align - bus_align))
def encode_dma(self, *, bank, row, col):
address = self._encode(bank, row, col)
return address >> self.address_align
def _decode(self, address):
def extract(value, width, offset):
mask = 2**width - 1
return (value & (mask << offset)) >> offset
row = extract(address, self.rowbits, self.bankbits + self.colbits)
bank = extract(address, self.bankbits, self.colbits)
col = extract(address, self.colbits, 0)
return bank, row, col
def decode_bus(self, address, base=0x40000000, bus_align=2):
address -= base
address >>= self.address_align - bus_align
return self._decode(address)
def decode_dma(self, address):
return self._decode(address << self.address_align)
################################################################################
class RowHammer:
def __init__(self, wb, *, nrows, rowbits, colbits, column, bank,
rows_start=0, no_refresh=False, verbose=False, plot=False):
for name, val in locals().items():
setattr(self, name, val)
self.converter = DRAMAddressConverter(colbits=colbits, rowbits=rowbits)
self.addresses_per_row = self._addresses_per_row()
@property
def rows(self):
return list(range(self.rows_start, self.nrows))
def _addresses_per_row(self):
addresses = {}
for row in self.rows:
addresses[row] = [self.converter.encode_bus(bank=self.bank, col=col, row=row)
for col in range(2**self.colbits)]
return addresses
def attack(self, row1, row2, read_count, progress_header=''):
# Make sure that the row hammer module is in reset state
self.wb.regs.rowhammer_enabled.write(0)
self.wb.regs.rowhammer_count.read() # clears the value
# Configure the row hammer attacker
addresses = [self.converter.encode_dma(bank=self.bank, col=self.column, row=r)
for r in [row1, row2]]
self.wb.regs.rowhammer_address1.write(addresses[0])
self.wb.regs.rowhammer_address2.write(addresses[1])
self.wb.regs.rowhammer_enabled.write(1)
row_strw = len(str(2**self.rowbits - 1))
def progress(count):
s = ' {}'.format(progress_header + ' ' if progress_header else '')
s += 'Rows = ({:{n}d},{:{n}d}), Count = {:5.2f}M / {:5.2f}M'.format(
row1, row2, count/1e6, read_count/1e6, n=row_strw)
print(s, end=' \r')
while True:
count = self.wb.regs.rowhammer_count.read()
progress(count)
if count >= read_count:
break
self.wb.regs.rowhammer_enabled.write(0)
progress(self.wb.regs.rowhammer_count.read()) # also clears the value
print()
def row_access_iterator(self, burst=16):
for row, addresses in self.addresses_per_row.items():
n = (max(addresses) - min(addresses)) // 4
base_addr = addresses[0]
yield row, n, base_addr
def check_errors(self, row_patterns, row_progress=16):
row_errors = {}
for row, n, base in self.row_access_iterator():
row_errors[row] = memcheck(wb, n, pattern=row_patterns[row], base=base, burst=255)
if row % row_progress == 0:
print('.', end='', flush=True)
return row_errors
def errors_count(self, row_errors):
return sum(1 if len(e) > 0 else 0 for e in row_errors.values())
def display_errors(self, row_errors):
for row in row_errors:
if len(row_errors[row]) > 0:
print("row_errors for row={:{n}}: {}".format(
row, len(row_errors[row]), n=len(str(2**self.rowbits-1))))
if self.verbose:
for i, word in row_errors[row]:
base_addr = min(self.addresses_per_row[row])
addr = base_addr + 4*i
bank, _row, col = self.converter.decode_bus(addr)
print("Error: 0x{:08x}: 0x{:08x} (row={}, col={})".format(
addr, word, _row, col))
if self.plot:
from matplotlib import pyplot as plt
row_err_counts = [len(row_errors.get(row, [])) for row in self.rows]
plt.bar(self.rows, row_err_counts, width=1)
plt.grid(True)
plt.xlabel('Row')
plt.ylabel('Errors')
plt.show()
def run(self, row_pairs, pattern_generator, read_count, row_progress=16, verify_initial=False):
print('\nPreparing ...')
row_patterns = pattern_generator(self.rows)
print('\nFilling memory with data ...')
for row, n, base in self.row_access_iterator():
memfill(wb, n, pattern=row_patterns[row], base=base, burst=255)
if row % row_progress == 0:
print('.', end='', flush=True)
if verify_initial:
print('\nVerifying written memory ...')
errors = self.check_errors(row_patterns, row_progress=row_progress)
if self.errors_count(errors) == 0:
print('OK')
else:
print()
self.display_errors(errors)
return
if self.no_refresh:
print('\nDisabling refresh ...')
wb.regs.controller_settings_refresh.write(0)
print('\nRunning row hammer attacks ...')
for i, (row1, row2) in enumerate(row_pairs):
s = 'Iter {:{n}} / {:{n}}'.format(i, len(row_pairs), n=len(str(len(row_pairs))))
self.attack(row1, row2, read_count=read_count, progress_header=s)
if self.no_refresh:
print('\nReenabling refresh ...')
wb.regs.controller_settings_refresh.write(1)
print('\nVerifying attacked memory ...')
errors = self.check_errors(row_patterns, row_progress=row_progress)
if self.errors_count(errors) == 0:
print('OK')
else:
print()
self.display_errors(errors)
return
################################################################################
def patterns_const(rows, value):
return {row: value for row in rows}
def patterns_alternating_per_row(rows):
return {row: 0xffffffff if row % 2 == 0 else 0x00000000 for row in rows}
def patterns_random_per_row(rows, seed=42):
rng = random.Random(seed)
return {row: rng.randint(0, 2**32 - 1) for row in rows}
if __name__ == "__main__":
import argparse
parser = argparse.ArgumentParser()
parser.add_argument('--nrows', type=int, default=0, help='Number of rows to consider')
parser.add_argument('--bank', type=int, default=0, help='Bank number')
parser.add_argument('--column', type=int, default=512, help='Column to read from')
parser.add_argument('--colbits', type=int, default=10, help='Number of column bits') # FIXME: take from our design
parser.add_argument('--rowbits', type=int, default=14, help='Number of row bits') # FIXME: take from our design
parser.add_argument('--start-row', type=int, default=0, help='Starting row (range = (start, start+nrows))')
parser.add_argument('--read_count', type=float, default=10e6, help='How many reads to perform for single address pair')
parser.add_argument('--hammer-only', nargs=2, type=int, help='Run only the row hammer attack')
parser.add_argument('--no-refresh', action='store_true', help='Disable refresh commands during the attacks')
parser.add_argument('--pattern', default='01_per_row',
choices=['all_0', 'all_1', '01_in_row', '01_per_row', 'rand_per_row'],
help='Pattern written to DRAM before running attacks')
parser.add_argument('--row-pairs', choices=['sequential', 'const', 'random'], default='sequential',
help='How the rows for subsequent attacks are selected')
parser.add_argument('--const-rows-pair', type=int, nargs=2, required=False, help='When using --row-pairs constant')
parser.add_argument('--plot', action='store_true', help='Plot errors distribution') # requiers matplotlib and pyqt5 packages
parser.add_argument('-v', '--verbose', action='store_true', help='Be more verbose')
parser.add_argument("--srv", action="store_true", help='Start LiteX server')
parser.add_argument("--experiment-no", type=int, default=0, help='Run preconfigured experiment #no')
args = parser.parse_args()
if args.experiment_no == 1:
args.nrows = 512
args.read_count = 15e6
args.pattern = '01_in_row'
args.row_pairs = 'const'
args.const_rows_pair = 88, 99
args.no_refresh = True
if args.srv:
from wrapper import litex_srv
litex_srv()
from litex import RemoteClient
wb = RemoteClient()
wb.open()
row_hammer = RowHammer(wb,
nrows = args.nrows,
rowbits = args.rowbits,
colbits = args.colbits,
column = args.column,
bank = args.bank,
rows_start = args.start_row,
verbose = args.verbose,
plot = args.plot,
no_refresh = args.no_refresh,
)
if args.hammer_only:
row_hammer.attack(*args.hammer_only, read_count=args.read_count)
else:
rng = random.Random(42)
def rand_row():
return rng.randint(args.start_row, args.start_row + args.nrows)
assert not (args.row_pairs == 'const' and not args.const_rows_pair), 'Specify --const-rows-pair'
row_pairs = {
'sequential': [(0 + args.start_row, i + args.start_row) for i in range(args.nrows)],
'const': [tuple(args.const_rows_pair)],
'random': [(rand_row(), rand_row()) for i in range(args.nrows)],
}[args.row_pairs]
pattern = {
'all_0': lambda rows: patterns_const(rows, 0x00000000),
'all_ones': lambda rows: patterns_const(rows, 0xffffffff),
'01_in_row': lambda rows: patterns_const(rows, 0xaaaaaaaa),
'01_per_row': patterns_alternating_per_row,
'rand_per_row': patterns_random_per_row,
}[args.pattern]
row_hammer.run(row_pairs=row_pairs, read_count=args.read_count, pattern_generator=pattern)
wb.close()
| [
"litex.RemoteClient"
] | [((7959, 7978), 'random.Random', 'random.Random', (['seed'], {}), '(seed)\n', (7972, 7978), False, 'import random\n'), ((8102, 8127), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (8125, 8127), False, 'import argparse\n'), ((10386, 10400), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (10398, 10400), False, 'from litex import RemoteClient\n'), ((10328, 10339), 'wrapper.litex_srv', 'litex_srv', ([], {}), '()\n', (10337, 10339), False, 'from wrapper import litex_srv\n'), ((10887, 10904), 'random.Random', 'random.Random', (['(42)'], {}), '(42)\n', (10900, 10904), False, 'import random\n'), ((4757, 4821), 'utils.memcheck', 'memcheck', (['wb', 'n'], {'pattern': 'row_patterns[row]', 'base': 'base', 'burst': '(255)'}), '(wb, n, pattern=row_patterns[row], base=base, burst=255)\n', (4765, 4821), False, 'from utils import memfill, memcheck\n'), ((5851, 5894), 'matplotlib.pyplot.bar', 'plt.bar', (['self.rows', 'row_err_counts'], {'width': '(1)'}), '(self.rows, row_err_counts, width=1)\n', (5858, 5894), True, 'from matplotlib import pyplot as plt\n'), ((5907, 5921), 'matplotlib.pyplot.grid', 'plt.grid', (['(True)'], {}), '(True)\n', (5915, 5921), True, 'from matplotlib import pyplot as plt\n'), ((5934, 5951), 'matplotlib.pyplot.xlabel', 'plt.xlabel', (['"""Row"""'], {}), "('Row')\n", (5944, 5951), True, 'from matplotlib import pyplot as plt\n'), ((5964, 5984), 'matplotlib.pyplot.ylabel', 'plt.ylabel', (['"""Errors"""'], {}), "('Errors')\n", (5974, 5984), True, 'from matplotlib import pyplot as plt\n'), ((5997, 6007), 'matplotlib.pyplot.show', 'plt.show', ([], {}), '()\n', (6005, 6007), True, 'from matplotlib import pyplot as plt\n'), ((6311, 6374), 'utils.memfill', 'memfill', (['wb', 'n'], {'pattern': 'row_patterns[row]', 'base': 'base', 'burst': '(255)'}), '(wb, n, pattern=row_patterns[row], base=base, burst=255)\n', (6318, 6374), False, 'from utils import memfill, memcheck\n')] |
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("sys_clk", 0, Pins("35"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("16"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("17"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("18"), IOStandard("LVCMOS33")),
# Buttons.
("user_btn", 0, Pins("15"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("14"), IOStandard("LVCMOS33")),
# Ring DI
("do", 0, Pins("23"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("8")),
Subsignal("rx", Pins("9")),
IOStandard("LVCMOS33")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):
def __init__(self):
GowinPlatform.__init__(self, "GW1N-LV1QN48C6/I5", _io, [], toolchain="gowin", devicename="GW1N-1")
self.toolchain.options["use_done_as_gpio"] = 1
self.toolchain.options["use_reconfign_as_gpio"] = 1
def create_programmer(self):
return OpenFPGALoader("tangnano")
| [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader"
] | [((1044, 1147), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1N-LV1QN48C6/I5"""', '_io', '[]'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1N-1"""'}), "(self, 'GW1N-LV1QN48C6/I5', _io, [], toolchain=\n 'gowin', devicename='GW1N-1')\n", (1066, 1147), False, 'from litex.build.gowin.platform import GowinPlatform\n'), ((1307, 1333), 'litex.build.openfpgaloader.OpenFPGALoader', 'OpenFPGALoader', (['"""tangnano"""'], {}), "('tangnano')\n", (1321, 1333), False, 'from litex.build.openfpgaloader import OpenFPGALoader\n')] |
#!/usr/bin/env python3
"""
This script is used to test the minimal DDR litex design.
It performs the calibration step by sending commands and data through an UART bridge
to the DDR controller.
It makes use of the litex RemoteClient.
This script is able to calculate which are the correct bitslip and delay values of the
IOSERDESes.
If the DDR design is correctly working, depending on the system frequency, an output similar
to the following is desplayed as output of this script:
Minimal Arty DDR3 Design for tests with Project X-Ray 2020-02-03 11:30:24
Release reset
Bring CKE high
Load Mode Register 2, CWL=5
Load Mode Register 3
Load Mode Register 1
Load Mode Register 0, CL=6, BL=8
ZQ Calibration
bitslip 0: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|31|
bitslip 1: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
bitslip 2: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
bitslip 3: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
bitslip 4: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
bitslip 5: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
bitslip 6: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
bitslip 7: |..|..|..|..|..|..|..|..|..|.............|..|..|..|..|..|..|..|..|..|..|..|..|..|..|..|
NOTE: if the system frequency is lower than 50 MHz, the DDR won't correctly function
"""
import sys
import argparse
from litex import RemoteClient
from sdram_init import dfii_control_sel, init_sequence
def identify_fpga(wb):
""" Gets the FPGA identifier and prints it on terminal."""
fpga_id = ""
for i in range(256):
c = chr(wb.read(wb.bases.identifier_mem + 4 * i) & 0xff)
fpga_id += c
if c == "\0":
break
print(fpga_id)
def seed_to_data(seed, random=True):
if random:
return (1664525 * seed + 1013904223) & 0xffffffff
else:
return seed
def write_pattern(wb, length):
for i in range(length):
wb.write(wb.mems.main_ram.base + 4 * i, seed_to_data(i))
def check_pattern(wb, length, debug=False):
errors = 0
for i in range(length):
error = 0
if wb.read(wb.mems.main_ram.base + 4 * i) != seed_to_data(i):
error = 1
if debug:
print(
"{}: 0x{:08x}, 0x{:08x} KO".format(
i, wb.read(wb.mems.main_ram.base + 4 * i),
seed_to_data(i)
)
)
else:
if debug:
print(
"{}: 0x{:08x}, 0x{:08x} OK".format(
i, wb.read(wb.mems.main_ram.base + 4 * i),
seed_to_data(i)
)
)
errors += error
return errors
def find_bitslips_delays(wb):
""" Finds bitslip and delay values that can be used with the implemented DDR design."""
nbitslips = 8
ndelays = 32
nmodules = 2
nwords = 16
final_bitslip = None
final_delay = None
for bitslip in range(nbitslips):
print("bitslip {:d}: |".format(bitslip), end="")
for delay in range(ndelays):
for module in range(nmodules):
wb.regs.ddrphy_dly_sel.write(1 << module)
wb.regs.ddrphy_rdly_dq_rst.write(1)
wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
for i in range(bitslip):
wb.regs.ddrphy_rdly_dq_bitslip.write(1)
for i in range(delay):
wb.regs.ddrphy_rdly_dq_inc.write(1)
write_pattern(wb, nwords)
errors = check_pattern(wb, nwords)
if errors:
print("..|", end="")
else:
print("{:02d}|".format(delay), end="")
final_bitslip = bitslip if final_bitslip is None else final_bitslip
final_delay = delay if final_delay is None else final_delay
sys.stdout.flush()
print("")
assert final_bitslip is not None and final_delay is not None, "bitslip/delay values not found"
return final_bitslip, final_delay
def set_bitslip_delay(wb, bitslip, delay):
""" Sets bitslip and delay values."""
nmodules = 2
for module in range(nmodules):
wb.regs.ddrphy_dly_sel.write(1 << module)
wb.regs.ddrphy_rdly_dq_rst.write(1)
wb.regs.ddrphy_rdly_dq_bitslip_rst.write(1)
for i in range(bitslip):
wb.regs.ddrphy_rdly_dq_bitslip.write(1)
for i in range(delay):
wb.regs.ddrphy_rdly_dq_inc.write(1)
def read_word_offset(read_only=False):
word = None
if not read_only:
print("\n==================================================\n")
print(
"Set a byte long word to write to memory (e.g. 0xdeadbeef): ",
end=""
)
word = int(input(), 16) & 0xffffffff
print("\n==================================================\n")
print("Set offset from base memory address: ", end="")
offset = int(input())
print("\n==================================================\n")
print("Set number of words to read or write: ", end="")
length = int(input())
return word, offset, length
def write_user_pattern(wb, offset, length, pattern):
"""
Writes to memory words set by user.
inputs:
- offset -> offset from base RAM address
- length -> number of words to be written starting
from offset
- pattern -> word to be written at offset
"""
for i in range(length):
wb.write(wb.mems.main_ram.base + 4 * (offset + i), pattern)
def read_user_pattern(wb, offset, length, pattern=None):
"""
Reads from memory at address set by user.
inputs:
- offset -> offset from base RAM address
- length -> number of lines to be read
- pattern -> pattern to be checked against read value
"""
for i in range(length):
read_value = wb.read(wb.mems.main_ram.base + 4 * (offset + i))
if pattern is None:
print("0x{:08x}".format(read_value))
else:
if read_value == pattern:
outcome = "CORRECT"
else:
outcome = "INCORRECT"
print(
"{} --> 0x{:08x}, 0x{:08x}".format(
outcome, read_value, pattern
)
)
def start_command_interface(wb):
cmd_list = """
Commands list:
0 --> Write memory
1 --> Read memory
2 --> Write/Read memory
3 --> Print commands list
4 --> Exit
"""
print(cmd_list)
while True:
print("\nWaiting for command: ", end="")
cmd = int(input())
if cmd == 0:
word, offset, length = read_word_offset()
write_user_pattern(wb, offset, length, word)
elif cmd == 1:
word, offset, length = read_word_offset(True)
read_user_pattern(wb, offset, length)
elif cmd == 2:
word, offset, length = read_word_offset()
write_user_pattern(wb, offset, length, word)
read_user_pattern(wb, offset, length, word)
elif cmd == 3:
print(cmd_list)
elif cmd == 4:
break
else:
print("Command not recognized, try again...")
def main():
parser = argparse.ArgumentParser(
description="Script to test correct DDR behaviour."
)
parser.add_argument(
'--bitslip', default=None, help="Defines a bitslip value."
)
parser.add_argument('--delay', default=None, help="Defines a delay value.")
args = parser.parse_args()
wb = RemoteClient(debug=False)
wb.open()
# software control
wb.regs.sdram_dfii_control.write(0)
# sdram initialization
for i, (comment, a, ba, cmd, delay) in enumerate(init_sequence):
print(comment)
wb.regs.sdram_dfii_pi0_address.write(a)
wb.regs.sdram_dfii_pi0_baddress.write(ba)
if i < 2:
wb.regs.sdram_dfii_control.write(cmd)
else:
wb.regs.sdram_dfii_pi0_command.write(cmd)
wb.regs.sdram_dfii_pi0_command_issue.write(1)
# hardware control
wb.regs.sdram_dfii_control.write(dfii_control_sel)
if args.bitslip is None or args.delay is None:
bitslip, delay = find_bitslips_delays(wb)
else:
bitslip = int(args.bitslip)
delay = int(args.delay)
set_bitslip_delay(wb, bitslip, delay)
start_command_interface(wb)
wb.close()
if __name__ == "__main__":
main()
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"litex.RemoteClient"
] | [((7584, 7660), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Script to test correct DDR behaviour."""'}), "(description='Script to test correct DDR behaviour.')\n", (7607, 7660), False, 'import argparse\n'), ((7896, 7921), 'litex.RemoteClient', 'RemoteClient', ([], {'debug': '(False)'}), '(debug=False)\n', (7908, 7921), False, 'from litex import RemoteClient\n'), ((4173, 4191), 'sys.stdout.flush', 'sys.stdout.flush', ([], {}), '()\n', (4189, 4191), False, 'import sys\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use ----------------------------------------------------------------------------------------
# Build/Load bitstream:
# ./siglent_ds1104xe.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load
#
# Test Ethernet:
# ping 192.168.1.50
#
# Test Console:
# litex_server --udp
# litex_term crossover
# --------------------------------------------------------------------------------------------------
import os
import argparse
from migen import *
from litex_boards.platforms import sds1104xe
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.video import VideoVGAPHY
from litedram.common import PHYPadsReducer
from litedram.modules import MT41K64M16
from litedram.phy import s7ddrphy
from liteeth.phy.mii import LiteEthPHYMII
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_ethernet=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()
self.clock_domains.cd_dvi = ClockDomain()
# # #
# Clk / Rst
clk25 = ClockSignal("eth_tx") if with_ethernet else platform.request("eth_clocks").rx
# PLL
self.submodules.pll = pll = S7PLL(speedgrade=-1)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
pll.create_clkout(self.cd_idelay, 200e6)
pll.create_clkout(self.cd_dvi, 33.3e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6), with_etherbone=True, eth_ip="192.168.1.50", with_video_terminal=False, with_video_framebuffer=False, **kwargs):
platform = sds1104xe.Platform()
# SoCCore ----------------------------------------------------------------------------------
if kwargs.get("uart_name", "serial") == "serial":
kwargs["uart_name"] = "crossover" # Defaults to Crossover UART.
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Siglent SDS1104X-E",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_etherbone)
# DDR3 SDRAM -------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
pads = PHYPadsReducer(platform.request("ddram"), [0, 1]), # FIXME: Reduce to 16-bit for use with NaxRiscv.
memtype = "DDR3",
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_sdram("sdram",
phy = self.ddrphy,
module = MT41K64M16(sys_clk_freq, "1:4"),
l2_cache_size = kwargs.get("l2_size", 8192)
)
# Etherbone --------------------------------------------------------------------------------
if with_etherbone:
# FIXME: Simplify LiteEth Hybrid MAC integration.
from liteeth.common import convert_ip
from liteeth.mac import LiteEthMAC
from liteeth.core.arp import LiteEthARP
from liteeth.core.ip import LiteEthIP
from liteeth.core.udp import LiteEthUDP
from liteeth.core.icmp import LiteEthICMP
from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone
# Ethernet PHY
self.submodules.ethphy = LiteEthPHYMII(
clock_pads = self.platform.request("eth_clocks"),
pads = self.platform.request("eth"))
etherbone_ip_address = convert_ip("192.168.1.51")
etherbone_mac_address = 0x10e2d5000001
# Ethernet MAC
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=8,
interface = "hybrid",
endianness = self.cpu.endianness,
hw_mac = etherbone_mac_address)
# Software Interface.
self.add_memory_region("ethmac", getattr(self.mem_map, "ethmac", None), 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# Hardware Interface.
self.submodules.arp = LiteEthARP(self.ethmac, etherbone_mac_address, etherbone_ip_address, sys_clk_freq, dw=8)
self.submodules.ip = LiteEthIP(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.arp.table, dw=8)
self.submodules.icmp = LiteEthICMP(self.ip, etherbone_ip_address, dw=8)
self.submodules.udp = LiteEthUDP(self.ip, etherbone_ip_address, dw=8)
self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface.
# Etherbone
self.submodules.etherbone = LiteEthEtherbone(self.udp, 1234, mode="master")
self.add_wb_master(self.etherbone.wishbone.bus)
# Timing constraints
eth_rx_clk = self.ethphy.crg.cd_eth_rx.clk
eth_tx_clk = self.ethphy.crg.cd_eth_tx.clk
self.platform.add_period_constraint(eth_rx_clk, 1e9/self.ethphy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/self.ethphy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
# Video ------------------------------------------------------------------------------------
video_timings = ("800x480@60Hz", {
"pix_clk" : 33.3e6,
"h_active" : 800,
"h_blanking" : 256,
"h_sync_offset" : 210,
"h_sync_width" : 1,
"v_active" : 480,
"v_blanking" : 45,
"v_sync_offset" : 22,
"v_sync_width" : 1,
})
if with_video_terminal or with_video_framebuffer:
self.submodules.videophy = VideoVGAPHY(platform.request("lcd"), clock_domain="dvi")
if with_video_terminal:
self.add_video_terminal(phy=self.videophy, timings=video_timings, clock_domain="dvi")
if with_video_framebuffer:
self.add_video_framebuffer(phy=self.videophy, timings=video_timings, clock_domain="dvi")
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on SDS1104X-E")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
with_video_terminal = args.with_video_terminal,
with_video_framebuffer = args.with_video_framebuffer,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"), device=1)
if __name__ == "__main__":
main()
| [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((7595, 7657), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on SDS1104X-E"""'}), "(description='LiteX SoC on SDS1104X-E')\n", (7618, 7657), False, 'import argparse\n'), ((8533, 8558), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (8550, 8558), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((2642, 2662), 'litex_boards.platforms.sds1104xe.Platform', 'sds1104xe.Platform', ([], {}), '()\n', (2660, 2662), False, 'from litex_boards.platforms import sds1104xe\n'), ((4762, 4788), 'liteeth.common.convert_ip', 'convert_ip', (['"""192.168.1.51"""'], {}), "('192.168.1.51')\n", (4772, 4788), False, 'from liteeth.common import convert_ip\n'), ((4905, 5025), 'liteeth.mac.LiteEthMAC', 'LiteEthMAC', ([], {'phy': 'self.ethphy', 'dw': '(8)', 'interface': '"""hybrid"""', 'endianness': 'self.cpu.endianness', 'hw_mac': 'etherbone_mac_address'}), "(phy=self.ethphy, dw=8, interface='hybrid', endianness=self.cpu.\n endianness, hw_mac=etherbone_mac_address)\n", (4915, 5025), False, 'from liteeth.mac import LiteEthMAC\n'), ((5474, 5566), 'liteeth.core.arp.LiteEthARP', 'LiteEthARP', (['self.ethmac', 'etherbone_mac_address', 'etherbone_ip_address', 'sys_clk_freq'], {'dw': '(8)'}), '(self.ethmac, etherbone_mac_address, etherbone_ip_address,\n sys_clk_freq, dw=8)\n', (5484, 5566), False, 'from liteeth.core.arp import LiteEthARP\n'), ((5598, 5692), 'liteeth.core.ip.LiteEthIP', 'LiteEthIP', (['self.ethmac', 'etherbone_mac_address', 'etherbone_ip_address', 'self.arp.table'], {'dw': '(8)'}), '(self.ethmac, etherbone_mac_address, etherbone_ip_address, self.\n arp.table, dw=8)\n', (5607, 5692), False, 'from liteeth.core.ip import LiteEthIP\n'), ((5723, 5771), 'liteeth.core.icmp.LiteEthICMP', 'LiteEthICMP', (['self.ip', 'etherbone_ip_address'], {'dw': '(8)'}), '(self.ip, etherbone_ip_address, dw=8)\n', (5734, 5771), False, 'from liteeth.core.icmp import LiteEthICMP\n'), ((5807, 5854), 'liteeth.core.udp.LiteEthUDP', 'LiteEthUDP', (['self.ip', 'etherbone_ip_address'], {'dw': '(8)'}), '(self.ip, etherbone_ip_address, dw=8)\n', (5817, 5854), False, 'from liteeth.core.udp import LiteEthUDP\n'), ((6035, 6082), 'liteeth.frontend.etherbone.LiteEthEtherbone', 'LiteEthEtherbone', (['self.udp', '(1234)'], {'mode': '"""master"""'}), "(self.udp, 1234, mode='master')\n", (6051, 6082), False, 'from liteeth.frontend.etherbone import LiteEthEtherbone\n'), ((8983, 9009), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (9003, 9009), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((9122, 9181), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (9134, 9181), False, 'import os\n'), ((3796, 3827), 'litedram.modules.MT41K64M16', 'MT41K64M16', (['sys_clk_freq', '"""1:4"""'], {}), "(sys_clk_freq, '1:4')\n", (3806, 3827), False, 'from litedram.modules import MT41K64M16\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2020-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""Direct Memory Access (DMA) reader and writer modules."""
from migen import *
from litex.gen.common import reverse_bytes
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
from litex.soc.interconnect import wishbone
# Helpers ------------------------------------------------------------------------------------------
def format_bytes(s, endianness):
return {"big": s, "little": reverse_bytes(s)}[endianness]
# WishboneDMAReader --------------------------------------------------------------------------------
class WishboneDMAReader(Module, AutoCSR):
"""Read data from Wishbone MMAP memory.
For every address written to the sink, one word will be produced on the source.
Parameters
----------
bus : bus
Wishbone bus of the SoC to read from.
Attributes
----------
sink : Record("address")
Sink for MMAP addresses to be read.
source : Record("data")
Source for MMAP word results from reading.
"""
def __init__(self, bus, endianness="little", with_csr=False):
assert isinstance(bus, wishbone.Interface)
self.bus = bus
self.sink = sink = stream.Endpoint([("address", bus.adr_width, ("last", 1))])
self.source = source = stream.Endpoint([("data", bus.data_width)])
# # #
data = Signal(bus.data_width)
self.submodules.fsm = fsm = FSM(reset_state="BUS-READ")
fsm.act("BUS-READ",
bus.stb.eq(sink.valid),
bus.cyc.eq(sink.valid),
bus.we.eq(0),
bus.sel.eq(2**(bus.data_width//8)-1),
bus.adr.eq(sink.address),
If(bus.stb & bus.ack,
NextValue(data, format_bytes(bus.dat_r, endianness)),
NextState("SOURCE-WRITE")
)
)
fsm.act("SOURCE-WRITE",
source.valid.eq(1),
source.last.eq(sink.last),
source.data.eq(data),
If(source.ready,
sink.ready.eq(1),
NextState("BUS-READ")
)
)
if with_csr:
self.add_csr()
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
self._base = CSRStorage(64, reset=default_base)
self._length = CSRStorage(32, reset=default_length)
self._enable = CSRStorage(reset=default_enable)
self._done = CSRStatus()
self._loop = CSRStorage(reset=default_loop)
self._offset = CSRStatus(32)
# # #
shift = log2_int(self.bus.data_width//8)
base = Signal(self.bus.adr_width)
offset = Signal(self.bus.adr_width)
length = Signal(self.bus.adr_width)
self.comb += base.eq(self._base.storage[shift:])
self.comb += length.eq(self._length.storage[shift:])
self.comb += self._offset.status.eq(offset)
fsm = FSM(reset_state="IDLE")
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE",
NextValue(offset, 0),
NextState("RUN"),
)
fsm.act("RUN",
self.sink.valid.eq(1),
self.sink.last.eq(offset == (length - 1)),
self.sink.address.eq(base + offset),
If(self.sink.ready,
NextValue(offset, offset + 1),
If(self.sink.last,
If(self._loop.storage,
NextValue(offset, 0)
).Else(
NextState("DONE")
)
)
)
)
fsm.act("DONE", self._done.status.eq(1))
# WishboneDMAWriter --------------------------------------------------------------------------------
class WishboneDMAWriter(Module, AutoCSR):
"""Write data to Wishbone MMAP memory.
Parameters
----------
bus : bus
Wishbone bus of the SoC to read from.
Attributes
----------
sink : Record("address", "data")
Sink for MMAP addresses/datas to be written.
"""
def __init__(self, bus, endianness="little", with_csr=False):
assert isinstance(bus, wishbone.Interface)
self.bus = bus
self.sink = sink = stream.Endpoint([("address", bus.adr_width), ("data", bus.data_width)])
# # #
data = Signal(bus.data_width)
self.comb += [
bus.stb.eq(sink.valid),
bus.cyc.eq(sink.valid),
bus.we.eq(1),
bus.sel.eq(2**(bus.data_width//8)-1),
bus.adr.eq(sink.address),
bus.dat_w.eq(format_bytes(sink.data, endianness)),
sink.ready.eq(bus.ack),
]
if with_csr:
self.add_csr()
def add_csr(self, default_base=0, default_length=0, default_enable=0, default_loop=0):
self._sink = self.sink
self.sink = stream.Endpoint([("data", self.bus.data_width)])
self._base = CSRStorage(64, reset=default_base)
self._length = CSRStorage(32, reset=default_length)
self._enable = CSRStorage(reset=default_enable)
self._done = CSRStatus()
self._loop = CSRStorage(reset=default_loop)
self._offset = CSRStatus(32)
# # #
shift = log2_int(self.bus.data_width//8)
base = Signal(self.bus.adr_width)
offset = Signal(self.bus.adr_width)
length = Signal(self.bus.adr_width)
self.comb += base.eq(self._base.storage[shift:])
self.comb += length.eq(self._length.storage[shift:])
self.comb += self._offset.status.eq(offset)
fsm = FSM(reset_state="IDLE")
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.comb += fsm.reset.eq(~self._enable.storage)
fsm.act("IDLE",
self.sink.ready.eq(1),
NextValue(offset, 0),
NextState("RUN"),
)
fsm.act("RUN",
self._sink.valid.eq(self.sink.valid),
self._sink.last.eq(offset == (length - 1)),
self._sink.address.eq(base + offset),
self._sink.data.eq(self.sink.data),
self.sink.ready.eq(self._sink.ready),
If(self.sink.valid & self.sink.ready,
NextValue(offset, offset + 1),
If(self._sink.last,
If(self._loop.storage,
NextValue(offset, 0)
).Else(
NextState("DONE")
)
)
)
)
fsm.act("DONE", self._done.status.eq(1))
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.gen.common.reverse_bytes"
] | [((1300, 1358), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', bus.adr_width, ('last', 1))]"], {}), "([('address', bus.adr_width, ('last', 1))])\n", (1315, 1358), False, 'from litex.soc.interconnect import stream\n'), ((1390, 1433), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', bus.data_width)]"], {}), "([('data', bus.data_width)])\n", (1405, 1433), False, 'from litex.soc.interconnect import stream\n'), ((4399, 4470), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', bus.adr_width), ('data', bus.data_width)]"], {}), "([('address', bus.adr_width), ('data', bus.data_width)])\n", (4414, 4470), False, 'from litex.soc.interconnect import stream\n'), ((5037, 5085), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', self.bus.data_width)]"], {}), "([('data', self.bus.data_width)])\n", (5052, 5085), False, 'from litex.soc.interconnect import stream\n'), ((539, 555), 'litex.gen.common.reverse_bytes', 'reverse_bytes', (['s'], {}), '(s)\n', (552, 555), False, 'from litex.gen.common import reverse_bytes\n')] |
#!/usr/bin/env python3
"""
Copyright (c) 2019-2020 Antmicro <www.antmicro.com>
Zephyr DTS & config overlay generator for LiteX SoC.
This script parses LiteX 'csr.csv' file and generates DTS and config
files overlay for Zephyr.
"""
import argparse
from litex.configuration import Configuration
configuration = None
def disabled_handler(name):
return """
&{} {{
status = "disabled";
}};
""".format(name)
def ram_handler(region, **kw):
result = """
&ram0 {{
reg = <0x{address} {size}>;
}};
""".format(address=hex(region['address'])[2:], size=hex(region['size']))
return result
def ethmac_handler(peripheral, **kw):
buf = kw['buffer']()
result = """
&{} {{
""".format(kw['reference'])
result += """
reg = <{} {} {} {}>;
""".format(hex(peripheral['address']),
hex(kw['size']),
hex(buf['address']),
hex(buf['size']))
if 'constants' in peripheral:
if 'interrupt' in peripheral['constants']:
irq_no = int(peripheral['constants']['interrupt'], 0)
result += """
interrupts = <{} 0>;
""".format(hex(irq_no))
result += """
};
"""
return result
def i2c_handler(peripheral, **kw):
result = """
&{} {{
reg = <{} {} {} {}>;
}};
""".format(kw['reference'],
hex(peripheral['address']),
hex(kw['size']),
hex(peripheral['address'] + kw['size']),
hex(kw['size']))
return result
def peripheral_handler(peripheral, **kw):
result = """
&{} {{
""".format(kw['reference'])
result += """
reg = <{} {}>;
""".format(hex(peripheral['address']),
hex(kw['size']))
if 'constants' in peripheral:
if 'interrupt' in peripheral['constants']:
irq_no = int(peripheral['constants']['interrupt'], 0)
result += """
interrupts = <{} 0>;
""".format(hex(irq_no))
result += """
};
"""
return result
peripheral_handlers = {
'uart': {
'handler': peripheral_handler,
'reference': 'uart0',
'size': 0x18,
'config_entry': 'UART_LITEUART'
},
'timer0': {
'handler': peripheral_handler,
'reference': 'timer0',
'size': 0x40,
'config_entry': 'LITEX_TIMER'
},
'ethmac': {
'handler': ethmac_handler,
'reference': 'eth0',
'size': 0x6c,
'buffer': lambda: configuration.mem_regions['ethmac'],
'config_entry': 'ETH_LITEETH'
},
'i2c0' : {
'handler': i2c_handler,
'reference': 'i2c0',
'size': 0x4,
'config_entry': 'I2C_LITEX'
}
}
mem_region_handler = {
'main_ram': {
'handler': ram_handler,
}
}
def generate_dts():
result = ""
for name, peripheral in configuration.peripherals.items():
if name not in peripheral_handlers:
print('Skipping unsupported peripheral `{}` at {}'
.format(name, hex(peripheral['address'])))
continue
h = peripheral_handlers[name]
result += h['handler'](peripheral, **h)
# disable all known, but not present devices
for name, handler in peripheral_handlers.items():
if name in configuration.peripherals.keys():
# this has already been generated
continue
result += disabled_handler(handler['reference'])
print(configuration.mem_regions)
for name, mem_region in configuration.mem_regions.items():
if name not in mem_region_handler:
print('Skipping unsupported mem_region `{}` at {}'
.format(name, hex(mem_region['address'])))
continue
h = mem_region_handler[name]
result += h['handler'](mem_region, **h)
return result
def generate_config():
result = ""
for name, handler in peripheral_handlers.items():
if name not in configuration.peripherals.keys():
result += "-DCONFIG_{}=n ".format(handler['config_entry'])
return result
def print_or_save(filepath, lines):
""" Prints given string on standard output or to the file.
Args:
filepath (string): path to the file lines should be written to
or '-' to write to a standard output
lines (string): content to be printed/written
"""
if filepath == '-':
print(lines)
else:
with open(filepath, 'w') as f:
f.write(lines)
def parse_args():
parser = argparse.ArgumentParser()
parser.add_argument('conf_file',
help='CSV configuration generated by LiteX')
parser.add_argument('--dts', action='store', required=True,
help='Output DTS overlay file')
parser.add_argument('--config', action='store', required=True,
help='Output config overlay file')
args = parser.parse_args()
return args
def main():
global configuration
args = parse_args()
configuration = Configuration(args.conf_file)
print_or_save(args.dts, generate_dts())
print_or_save(args.config, generate_config())
if __name__ == '__main__':
main()
| [
"litex.configuration.Configuration"
] | [((4444, 4469), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {}), '()\n', (4467, 4469), False, 'import argparse\n'), ((4954, 4983), 'litex.configuration.Configuration', 'Configuration', (['args.conf_file'], {}), '(args.conf_file)\n', (4967, 4983), False, 'from litex.configuration import Configuration\n')] |
# This file is Copyright (c) 2021 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk24", 0, Pins("C1"), IOStandard("LVCMOS18")),
("rst_n", 0, Pins("V17"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("N4"), IOStandard("LVCMOS18")),
("hyper_ram", 0,
Subsignal("rst_n", Pins("D2"), IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("clk_p", Pins("G1"), IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("clk_n", Pins("F2"), IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("cs_n", Pins("F3"), IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("dq", Pins("J2 J1 G4 K1 K4 L1 K3 M1"), IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("rwds", Pins("H1"), IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
),
("boson", 0,
Subsignal("data", Pins("B17 A13 A9 B11 B2 A2 A3 B4 \
B1 A8 A7 B9 B8 B6 D1 A6"),IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("clk", Pins("A11"),IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("vsync", Pins("B10"),IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("hsync", Pins("A17"),IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("valid", Pins("B18"),IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
Subsignal("rx", Pins("B7"),IOStandard("LVCMOS18"),Misc("PULLMODE=UP"),Misc("SLEWRATE=SLOW")),
Subsignal("tx", Pins("A4"),IOStandard("LVCMOS18"),Misc("PULLMODE=UP"),Misc("SLEWRATE=SLOW")),
Subsignal("reset", Pins("C2"),IOStandard("LVCMOS18"),Misc("SLEWRATE=SLOW")),
Subsignal("ext_sync", Pins("A16"),IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST")),
),
("io", 0,
Subsignal("out", Pins("M2 M3"),IOStandard("LVCMOS18"),Misc("PULLMODE=UP")),
Subsignal("oe", Pins("N3 N2"),IOStandard("LVCMOS18"),Misc("PULLMODE=UP")),
),
("sdmmc", 0,
Subsignal("clk", Pins("J18"),IOStandard("LVCMOS33"),Misc("SLEWRATE=FAST")),
Subsignal("cmd", Pins("H18"),IOStandard("LVCMOS33"),Misc("PULLMODE=UP"),Misc("SLEWRATE=FAST")),
Subsignal("data", Pins("K18 L18 F18 G18"),IOStandard("LVCMOS33"),Misc("PULLMODE=UP"),Misc("SLEWRATE=FAST")),
Subsignal("cd", Pins("F17"),IOStandard("LVCMOS33"),Misc("PULLMODE=UP")),
),
# ("spiflash", 0,
# Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")),
# #Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")), # Note: CLK is bound using USRMCLK block
# Subsignal("miso", Pins("T18"), IOStandard("LVCMOS33")),
# Subsignal("mosi", Pins("U18"), IOStandard("LVCMOS33")),
# Subsignal("wp", Pins("R18"), IOStandard("LVCMOS33")),
# Subsignal("hold", Pins("N18"), IOStandard("LVCMOS33")),
# ),
("spiflash4x", 0,
Subsignal("cs_n", Pins("U17"), IOStandard("LVCMOS33")),
#Subsignal("clk", Pins("U16"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("U18 T18 R18 N18"),Misc("PULLMODE=UP"), IOStandard("LVCMOS33")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-8MG285C", _io, _connectors, toolchain='trellis', **kwargs)
self.name = 'boson_sd'
| [
"litex.build.lattice.LatticePlatform.__init__"
] | [((3691, 3795), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8MG285C"""', '_io', '_connectors'], {'toolchain': '"""trellis"""'}), "(self, 'LFE5U-25F-8MG285C', _io, _connectors,\n toolchain='trellis', **kwargs)\n", (3715, 3795), False, 'from litex.build.lattice import LatticePlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2021 Dolu1990 <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.build.io import SDRTristate
# USB OHCI -----------------------------------------------------------------------------------------
class USBOHCI(Module):
def __init__(self, platform, pads, usb_clk_freq=48e6, dma_data_width=32):
self.pads = pads
self.usb_clk_freq = usb_clk_freq
self.dma_data_width = dma_data_width
self.wb_ctrl = wb_ctrl = wishbone.Interface(data_width=32)
self.wb_dma = wb_dma = wishbone.Interface(data_width=dma_data_width)
self.interrupt = Signal()
# # #
usb_ios = Record([
("dp_i", 1), ("dp_o", 1), ("dp_oe", 1),
("dm_i", 1), ("dm_o", 1), ("dm_oe", 1),
])
self.specials += Instance(self.get_netlist_name(),
# Clk / Rst.
i_phy_clk = ClockSignal("usb"),
i_phy_reset = ResetSignal("usb"),
i_ctrl_clk = ClockSignal("sys"),
i_ctrl_reset = ResetSignal("sys"),
# Wishbone Control.
i_io_ctrl_CYC = wb_ctrl.cyc,
i_io_ctrl_STB = wb_ctrl.stb,
o_io_ctrl_ACK = wb_ctrl.ack,
i_io_ctrl_WE = wb_ctrl.we,
i_io_ctrl_ADR = wb_ctrl.adr,
o_io_ctrl_DAT_MISO = wb_ctrl.dat_r,
i_io_ctrl_DAT_MOSI = wb_ctrl.dat_w,
i_io_ctrl_SEL = wb_ctrl.sel,
# Wishbone DMA.
o_io_dma_CYC = wb_dma.cyc,
o_io_dma_STB = wb_dma.stb,
i_io_dma_ACK = wb_dma.ack,
o_io_dma_WE = wb_dma.we,
o_io_dma_ADR = wb_dma.adr,
i_io_dma_DAT_MISO = wb_dma.dat_r,
o_io_dma_DAT_MOSI = wb_dma.dat_w,
o_io_dma_SEL = wb_dma.sel,
i_io_dma_ERR = wb_dma.err,
o_io_dma_CTI = wb_dma.cti,
o_io_dma_BTE = wb_dma.bte,
# Interrupt.
o_io_interrupt = self.interrupt,
# USB
i_io_usb_0_dp_read = usb_ios.dp_i,
o_io_usb_0_dp_write = usb_ios.dp_o,
o_io_usb_0_dp_writeEnable = usb_ios.dp_oe,
i_io_usb_0_dm_read = usb_ios.dm_i,
o_io_usb_0_dm_write = usb_ios.dm_o,
o_io_usb_0_dm_writeEnable = usb_ios.dm_oe,
)
self.specials += SDRTristate(
io = pads.dp,
o = usb_ios.dp_o,
oe = usb_ios.dp_oe,
i = usb_ios.dp_i,
)
self.specials += SDRTristate(
io = pads.dm,
o = usb_ios.dm_o,
oe = usb_ios.dm_oe,
i = usb_ios.dm_i,
)
self.add_sources(platform)
def get_netlist_name(self):
return "UsbOhciWishbone" \
f"_Dw{self.dma_data_width}" \
f"_Pc{len(self.pads.dp)}" \
f"_Pf{self.usb_clk_freq}"
def add_sources(self, platform):
vdir = get_data_mod("misc", "usb_ohci").data_location
netlist_name = self.get_netlist_name()
print(f"USB OHCI netlist : {netlist_name}")
if not os.path.exists(os.path.join(vdir, netlist_name + ".v")):
self.generate_netlist()
platform.add_source(os.path.join(vdir, netlist_name + ".v"), "verilog")
def generate_netlist(self):
print(f"Generating USB OHCI netlist")
vdir = get_data_mod("misc", "usb_ohci").data_location
gen_args = []
gen_args.append(f"--port-count={len(self.pads.dp)}")
gen_args.append(f"--phy-frequency={self.usb_clk_freq}")
gen_args.append(f"--dma-width={self.dma_data_width}")
gen_args.append(f"--netlist-name={self.get_netlist_name()}")
gen_args.append(f"--netlist-directory={vdir}")
cmd = 'cd {path} && sbt "lib/runMain spinal.lib.com.usb.ohci.UsbOhciWishbone {args}"'.format(
path=os.path.join(vdir, "ext", "SpinalHDL"), args=" ".join(gen_args))
print("!!! " + cmd)
if os.system(cmd) != 0:
raise OSError('Failed to run sbt')
| [
"litex.soc.interconnect.wishbone.Interface",
"litex.build.io.SDRTristate",
"litex.get_data_mod"
] | [((662, 695), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (680, 695), False, 'from litex.soc.interconnect import wishbone\n'), ((729, 774), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': 'dma_data_width'}), '(data_width=dma_data_width)\n', (747, 774), False, 'from litex.soc.interconnect import wishbone\n'), ((2616, 2689), 'litex.build.io.SDRTristate', 'SDRTristate', ([], {'io': 'pads.dp', 'o': 'usb_ios.dp_o', 'oe': 'usb_ios.dp_oe', 'i': 'usb_ios.dp_i'}), '(io=pads.dp, o=usb_ios.dp_o, oe=usb_ios.dp_oe, i=usb_ios.dp_i)\n', (2627, 2689), False, 'from litex.build.io import SDRTristate\n'), ((2784, 2857), 'litex.build.io.SDRTristate', 'SDRTristate', ([], {'io': 'pads.dm', 'o': 'usb_ios.dm_o', 'oe': 'usb_ios.dm_oe', 'i': 'usb_ios.dm_i'}), '(io=pads.dm, o=usb_ios.dm_o, oe=usb_ios.dm_oe, i=usb_ios.dm_i)\n', (2795, 2857), False, 'from litex.build.io import SDRTristate\n'), ((3197, 3229), 'litex.get_data_mod', 'get_data_mod', (['"""misc"""', '"""usb_ohci"""'], {}), "('misc', 'usb_ohci')\n", (3209, 3229), False, 'from litex import get_data_mod\n'), ((3481, 3520), 'os.path.join', 'os.path.join', (['vdir', "(netlist_name + '.v')"], {}), "(vdir, netlist_name + '.v')\n", (3493, 3520), False, 'import os\n'), ((3628, 3660), 'litex.get_data_mod', 'get_data_mod', (['"""misc"""', '"""usb_ohci"""'], {}), "('misc', 'usb_ohci')\n", (3640, 3660), False, 'from litex import get_data_mod\n'), ((4234, 4248), 'os.system', 'os.system', (['cmd'], {}), '(cmd)\n', (4243, 4248), False, 'import os\n'), ((3374, 3413), 'os.path.join', 'os.path.join', (['vdir', "(netlist_name + '.v')"], {}), "(vdir, netlist_name + '.v')\n", (3386, 3413), False, 'import os\n'), ((4128, 4166), 'os.path.join', 'os.path.join', (['vdir', '"""ext"""', '"""SpinalHDL"""'], {}), "(vdir, 'ext', 'SpinalHDL')\n", (4140, 4166), False, 'import os\n')] |
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
from migen import *
from migen.genlib.cdc import MultiReg
from liteeth.common import convert_ip, eth_udp_user_description
from litedram.frontend.dma import LiteDRAMDMAWriter
from litex.gen.common import reverse_bytes
from litex.soc.interconnect import csr, stream
from utils import FastLatch
class Conv32to64(Module):
def __init__(self, source, sink, reverse=False):
partial = Signal(32)
bit = Signal()
rbit = Signal()
self.submodules._reset = FastLatch()
if reverse:
conv = reverse_bytes
else:
conv = lambda x: x
self.comb += [
rbit.eq(bit & ~self._reset.out),
sink.valid.eq(source.valid & rbit),
sink.data[:32].eq(conv(partial)),
sink.data[32:].eq(conv(source.data)),
source.ready.eq(sink.ready | ~rbit),
]
self.sync += If(source.valid,
If(~rbit,
partial.eq(source.data),
bit.eq(1),
If(self._reset.out, self._reset.reset.send()),
).Elif(sink.ready,
bit.eq(0),
),
)
def reset(self):
return self._reset.set.send()
class ProtocolHandler(Module):
def __init__(self, source, sink):
state = Signal(2)
STREAM = 1
SKIP = 2
address = Signal(18)
sink32 = stream.Endpoint([("data", 32), ("address", 32)])
self.submodules.conv = Conv32to64(sink32, sink, reverse=True)
self.comb += [
sink.address.eq(sink32.address[1:19]),
]
self.comb += [
sink32.valid.eq((state == STREAM) & source.valid),
sink32.data.eq(source.data),
sink32.address.eq(address),
source.ready.eq((state != STREAM) | sink32.ready),
]
self.sync += If(source.valid,
If(state == 0,
address.eq(source.data[0:18]),
state.eq(STREAM),
self.conv.reset(),
).Elif(state==SKIP,
If(source.end,
state.eq(0),
),
).Elif(sink32.ready,
address.eq(address + 1),
If(source.end,
state.eq(0),
),
),
)
class UdpDramWriter(Module, csr.AutoCSR):
def __init__(self, sdram, udp, port_num):
# UDP port -> (eth_rx) FIFO (sys) -> UpConverter -> DMA writer
udp_port = udp.crossbar.get_port(port_num, dw=32)
# FIFO
renamer = ClockDomainsRenamer({'write': 'eth_rx', 'read': 'sys'})
fifo_layout = [("data", 32), ("end", 1)]
self.submodules.fifo = fifo = renamer(stream.AsyncFIFO(fifo_layout, 512, buffered=True))
self.connect_udp_to_fifo(udp_port.source, fifo, port_num)
# Converter
dma_layout = [("data", 64), ("address", 32)]
converter = stream.Endpoint(dma_layout)
self.submodules.handler = ProtocolHandler(fifo.source, converter)
# DMA writer
sdram_port = sdram.crossbar.get_port(mode='write', data_width=64)
self.submodules.dma = LiteDRAMDMAWriter(sdram_port, fifo_depth=1, fifo_buffered=False)
self.comb += converter.connect(self.dma.sink)
def connect_udp_to_fifo(self, udp, fifo, port_num):
valid = Signal()
self.comb += [
valid.eq(udp.dst_port == port_num),
fifo.sink.valid.eq(udp.valid & valid),
fifo.sink.data.eq(udp.data),
fifo.sink.end.eq(udp.last),
udp.ready.eq(fifo.sink.ready),
]
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((564, 575), 'utils.FastLatch', 'FastLatch', ([], {}), '()\n', (573, 575), False, 'from utils import FastLatch\n'), ((1462, 1510), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 32), ('address', 32)]"], {}), "([('data', 32), ('address', 32)])\n", (1477, 1510), False, 'from litex.soc.interconnect import csr, stream\n'), ((3000, 3027), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['dma_layout'], {}), '(dma_layout)\n', (3015, 3027), False, 'from litex.soc.interconnect import csr, stream\n'), ((3228, 3292), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'LiteDRAMDMAWriter', (['sdram_port'], {'fifo_depth': '(1)', 'fifo_buffered': '(False)'}), '(sdram_port, fifo_depth=1, fifo_buffered=False)\n', (3245, 3292), False, 'from litedram.frontend.dma import LiteDRAMDMAWriter\n'), ((2789, 2838), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (['fifo_layout', '(512)'], {'buffered': '(True)'}), '(fifo_layout, 512, buffered=True)\n', (2805, 2838), False, 'from litex.soc.interconnect import csr, stream\n')] |
#!/usr/bin/env python3
import argparse
from migen import *
from litex.boards.platforms import arty
from litex.soc.cores import *
from litex.soc.integration import soc_core
from litex.soc.interconnect.csr import *
from litex.soc.cores import gpio
from litex.soc.cores.uart import UARTWishboneBridge
from litex.soc.integration.builder import *
from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal
from migen.genlib.cdc import MultiReg
_pmods = [
("pmoda", 0,
Subsignal("p0", Pins("pmoda:0")),
Subsignal("p1", Pins("pmoda:1")),
Subsignal("p2", Pins("pmoda:2")),
Subsignal("p3", Pins("pmoda:3")),
Subsignal("p4", Pins("pmoda:4")),
Subsignal("p5", Pins("pmoda:5")),
Subsignal("p6", Pins("pmoda:6")),
Subsignal("p7", Pins("pmoda:7")),
IOStandard("LVCMOS33")
),
("pmodb", 0,
Subsignal("p0", Pins("pmodb:0")),
Subsignal("p1", Pins("pmodb:1")),
Subsignal("p2", Pins("pmodb:2")),
Subsignal("p3", Pins("pmodb:3")),
Subsignal("p4", Pins("pmodb:4")),
Subsignal("p5", Pins("pmodb:5")),
Subsignal("p6", Pins("pmodb:6")),
Subsignal("p7", Pins("pmodb:7")),
IOStandard("LVCMOS33")
),
("pmodc", 0,
Subsignal("p0", Pins("pmodc:0")),
Subsignal("p1", Pins("pmodc:1")),
Subsignal("p2", Pins("pmodc:2")),
Subsignal("p3", Pins("pmodc:3")),
Subsignal("p4", Pins("pmodc:4")),
Subsignal("p5", Pins("pmodc:5")),
Subsignal("p6", Pins("pmodc:6")),
Subsignal("p7", Pins("pmodc:7")),
IOStandard("LVCMOS33")
),
("pmodd", 0,
Subsignal("p0", Pins("pmodd:0")),
Subsignal("p1", Pins("pmodd:1")),
Subsignal("p2", Pins("pmodd:2")),
Subsignal("p3", Pins("pmodd:3")),
Subsignal("p4", Pins("pmodd:4")),
Subsignal("p5", Pins("pmodd:5")),
Subsignal("p6", Pins("pmodd:6")),
Subsignal("p7", Pins("pmodd:7")),
IOStandard("LVCMOS33")
),
]
_serial2 = [
("serial2", 0,
Subsignal("rx", Pins("N15")),
Subsignal("tx", Pins("M16"), Misc("PULLUP")),
IOStandard("LVCMOS33")
),
]
class GPIOBidirectional(Module, AutoCSR):
def __init__(self, soc, pad_name):
pins_pad = soc.platform.request(pad_name)
pins_t = TSTriple(len(pins_pad))
self.specials += pins_t.get_tristate(Cat(pins_pad.p0, pins_pad.p1, pins_pad.p2, pins_pad.p3, pins_pad.p4, pins_pad.p5, pins_pad.p6, pins_pad.p7))
self._pins_in = CSRStatus(len(pins_pad))
self._pins_out = CSRStorage(len(pins_pad))
self._pins_oe = CSRStorage(len(pins_pad))
self.specials += MultiReg(pins_t.i, self._pins_in.status)
self.comb += pins_t.o.eq(self._pins_out.storage)
self.comb += pins_t.oe.eq(self._pins_oe.storage)
# Build --------------------------------------------------------------------------------------------
def main():
platform = arty.Platform()
sys_clk_freq = 1/platform.default_clk_period*1e9
soc = soc_core.SoCCore(platform,
sys_clk_freq,
cpu_variant="lite+debug",
integrated_rom_size=0x8000,
integrated_sram_size=0x8000)
# rgb led
led_pad = platform.request("rgb_led", 0)
soc.submodules.leds = gpio.GPIOOut(led_pad.r)
soc.add_csr("leds")
# pmods
platform.add_extension(_pmods)
soc.submodules.pmoda = GPIOBidirectional(soc, "pmoda")
soc.submodules.pmodb = GPIOBidirectional(soc, "pmodb")
soc.submodules.pmodc = GPIOBidirectional(soc, "pmodc")
soc.submodules.pmodd = GPIOBidirectional(soc, "pmodd")
soc.add_csr("pmoda")
soc.add_csr("pmodb")
soc.add_csr("pmodc")
soc.add_csr("pmodd")
# debug
# https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers#litescope-bridge
platform.add_extension(_serial2)
soc.submodules.uartbridge = UARTWishboneBridge(platform.request("serial2"), int(sys_clk_freq), baudrate=115200)
soc.add_wb_master(soc.uartbridge.wishbone)
soc.register_mem("vexriscv_debug", 0xf00f0000, soc.cpu.debug_bus, 0x10)
builder = Builder(soc, csr_csv="csr.csv")
# for package in builder.software_packages:
# if package[0] == "bios":
# builder.software_packages.remove(package)
# break
# builder.add_software_package("bios", src_dir="../../../../sw")
builder.build()
if __name__ == "__main__":
main()
| [
"litex.build.generic_platform.Misc",
"litex.build.generic_platform.IOStandard",
"litex.soc.integration.soc_core.SoCCore",
"litex.boards.platforms.arty.Platform",
"litex.build.generic_platform.Pins",
"litex.soc.cores.gpio.GPIOOut"
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{}), "('PULLUP')\n", (2041, 2051), False, 'from litex.build.generic_platform import Pins, IOStandard, Misc, Subsignal\n')] |
#!/usr/bin/env python3
# This variable defines all the external programs that this module
# relies on. lxbuildenv reads this variable in order to ensure
# the build will finish without exiting due to missing third-party
# programs.
LX_DEPENDENCIES = ["riscv", "icestorm", "yosys", "nextpnr-ice40"]
# Import lxbuildenv to integrate the deps/ directory
import lxbuildenv
# Disable pylint's E1101, which breaks completely on migen
#pylint:disable=E1101
#from migen import *
from migen import Module, Signal, Instance, ClockDomain, If
from migen.fhdl.specials import TSTriple
from migen.fhdl.decorators import ClockDomainsRenamer
from litex.build.lattice.platform import LatticePlatform
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.integration.soc_core import SoCCore
from litex.soc.cores.cpu import CPUNone
from litex.soc.integration.builder import Builder
from litex.soc.interconnect import wishbone
from litex.soc.cores import up5kspram, spi_flash
from litex_boards.partner.targets.fomu import _CRG
from valentyusb.usbcore import io as usbio
from valentyusb.usbcore.cpu import epmem, unififo, epfifo, dummyusb, eptri
from valentyusb.usbcore.endpoint import EndpointType
import lxsocdoc
import spibone
import argparse
import os
from rtl.version import Version
from rtl.romgen import RandomFirmwareROM, FirmwareROM
from rtl.fomutouch import TouchPads
from rtl.sbled import SBLED
from rtl.sbwarmboot import SBWarmBoot
from rtl.messible import Messible
class Platform(LatticePlatform):
def __init__(self, revision=None, toolchain="icestorm"):
self.revision = revision
if revision == "evt":
from litex_boards.partner.platforms.fomu_evt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm")
self.spi_size = 16 * 1024 * 1024
self.spi_dummy = 6
elif revision == "dvt":
from litex_boards.partner.platforms.fomu_pvt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 6
elif revision == "pvt":
from litex_boards.partner.platforms.fomu_pvt import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 6
elif revision == "hacker":
from litex_boards.partner.platforms.fomu_hacker import _io, _connectors
LatticePlatform.__init__(self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
self.spi_size = 2 * 1024 * 1024
self.spi_dummy = 4
else:
raise ValueError("Unrecognized revision: {}. Known values: evt, dvt, pvt, hacker".format(revision))
def create_programmer(self):
raise ValueError("programming is not supported")
class BaseSoC(SoCCore, AutoDoc):
"""Fomu Bootloader and Base SoC
Fomu is an FPGA that fits in your USB port. This reference manual
documents the basic SoC that runs the bootloader, and that can be
reused to run your own RISC-V programs.
This reference manual only describes a particular version of the SoC.
The register sets described here are guaranteed to be available
with a given ``major version``, but are not guaranteed to be available on
any other version. Naturally, you are free to create your own SoC
that does not provide these hardware blocks. To see what the version of the
bitstream you're running, check the ``VERSION`` registers.
"""
SoCCore.csr_map = {
"ctrl": 0, # provided by default (optional)
"crg": 1, # user
"uart_phy": 2, # provided by default (optional)
"uart": 3, # provided by default (optional)
"identifier_mem": 4, # provided by default (optional)
"timer0": 5, # provided by default (optional)
"cpu_or_bridge": 8,
"usb": 9,
"picorvspi": 10,
"touch": 11,
"reboot": 12,
"rgb": 13,
"version": 14,
"lxspi": 15,
"messible": 16,
}
SoCCore.mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0xa0000000)
"spiflash": 0x20000000, # (default shadow @0xa0000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
"csr": 0xe0000000, # (default shadow @0xe0000000)
}
interrupt_map = {
"timer0": 2,
"usb": 3,
}
interrupt_map.update(SoCCore.interrupt_map)
def __init__(self, platform, boot_source="rand",
debug=None, bios_file=None,
use_dsp=False, placer="heap", output_dir="build",
pnr_seed=0,
warmboot_offsets=None,
**kwargs):
# Disable integrated RAM as we'll add it later
self.integrated_sram_size = 0
self.output_dir = output_dir
clk_freq = int(12e6)
self.submodules.crg = _CRG(platform)
SoCCore.__init__(self, platform, clk_freq, integrated_sram_size=0, with_uart=False, **kwargs)
usb_debug = False
if debug is not None:
if debug == "uart":
from litex.soc.cores.uart import UARTWishboneBridge
self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
self.add_wb_master(self.uart_bridge.wishbone)
elif debug == "usb":
usb_debug = True
elif debug == "spi":
import spibone
# Add SPI Wishbone bridge
debug_device = [
("spidebug", 0,
Subsignal("mosi", Pins("dbg:0")),
Subsignal("miso", Pins("dbg:1")),
Subsignal("clk", Pins("dbg:2")),
Subsignal("cs_n", Pins("dbg:3")),
)
]
platform.add_extension(debug_device)
spi_pads = platform.request("spidebug")
self.submodules.spibone = ClockDomainsRenamer("usb_12")(spibone.SpiWishboneBridge(spi_pads, wires=4))
self.add_wb_master(self.spibone.wishbone)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu_Debug.v")
os.path.join(output_dir, "gateware")
self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
else:
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.use_external_variant("rtl/VexRiscv_Fomu.v")
# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
# free up scarce block RAM.
spram_size = 128*1024
self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
# Add a Messible for device->host communications
self.submodules.messible = Messible()
if boot_source == "rand":
kwargs['cpu_reset_address'] = 0
bios_size = 0x2000
self.submodules.random_rom = RandomFirmwareROM(bios_size)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.random_rom.bus, bios_size)
elif boot_source == "bios":
kwargs['cpu_reset_address'] = 0
if bios_file is None:
self.integrated_rom_size = bios_size = 0x2000
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
bios_size = 0x2000
self.submodules.firmware_rom = FirmwareROM(bios_size, bios_file)
self.add_constant("ROM_DISABLE", 1)
self.register_rom(self.firmware_rom.bus, bios_size)
elif boot_source == "spi":
kwargs['cpu_reset_address'] = 0
self.integrated_rom_size = bios_size = 0x2000
gateware_size = 0x1a000
self.flash_boot_address = self.mem_map["spiflash"] + gateware_size
self.submodules.rom = wishbone.SRAM(bios_size, read_only=True, init=[])
self.register_rom(self.rom.bus, bios_size)
else:
raise ValueError("unrecognized boot_source: {}".format(boot_source))
# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
# for doing writes.
spi_pads = platform.request("spiflash4x")
self.submodules.lxspi = spi_flash.SpiFlashDualQuad(spi_pads, dummy=platform.spi_dummy, endianness="little")
self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=platform.spi_size)
# Add USB pads, as well as the appropriate USB controller. If no CPU is
# present, use the DummyUsb controller.
usb_pads = platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.submodules.usb = eptri.TriEndpointInterface(usb_iobuf, debug=usb_debug)
else:
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=usb_debug)
if usb_debug:
self.add_wb_master(self.usb.debug_bridge.wishbone)
# For the EVT board, ensure the pulldown pin is tristated as an input
if hasattr(usb_pads, "pulldown"):
pulldown = TSTriple()
self.specials += pulldown.get_tristate(usb_pads.pulldown)
self.comb += pulldown.oe.eq(0)
# Add GPIO pads for the touch buttons
platform.add_extension(TouchPads.touch_device)
self.submodules.touch = TouchPads(platform.request("touch_pads"))
# Allow the user to reboot the ICE40. Additionally, connect the CPU
# RESET line to a register that can be modified, to allow for
# us to debug programs even during reset.
self.submodules.reboot = SBWarmBoot(self, warmboot_offsets)
if hasattr(self, "cpu") and not isinstance(self.cpu, CPUNone):
self.cpu.cpu_params.update(
i_externalResetVector=self.reboot.addr.storage,
)
self.submodules.rgb = SBLED(platform.revision, platform.request("rgb_led"))
self.submodules.version = Version(platform.revision, self, pnr_seed, models=[
("0x45", "E", "Fomu EVT"),
("0x44", "D", "Fomu DVT"),
("0x50", "P", "Fomu PVT (production)"),
("0x48", "H", "Fomu Hacker"),
("0x3f", "?", "Unknown model"),
])
# Add "-relut -dffe_min_ce_use 4" to the synth_ice40 command.
# The "-reult" adds an additional LUT pass to pack more stuff in,
# and the "-dffe_min_ce_use 4" flag prevents Yosys from generating a
# Clock Enable signal for a LUT that has fewer than 4 flip-flops.
# This increases density, and lets us use the FPGA more efficiently.
platform.toolchain.nextpnr_yosys_template[2] += " -relut -abc2 -dffe_min_ce_use 4 -relut"
if use_dsp:
platform.toolchain.nextpnr_yosys_template[2] += " -dsp"
# Disable final deep-sleep power down so firmware words are loaded
# onto softcore's address bus.
platform.toolchain.build_template[3] = "icepack -s {build_name}.txt {build_name}.bin"
platform.toolchain.nextpnr_build_template[2] = "icepack -s {build_name}.txt {build_name}.bin"
# Allow us to set the nextpnr seed
platform.toolchain.nextpnr_build_template[1] += " --seed " + str(pnr_seed)
if placer is not None:
platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer)
def copy_memory_file(self, src):
import os
from shutil import copyfile
if not os.path.exists(self.output_dir):
os.mkdir(self.output_dir)
if not os.path.exists(os.path.join(self.output_dir, "gateware")):
os.mkdir(os.path.join(self.output_dir, "gateware"))
copyfile(os.path.join("rtl", src), os.path.join(self.output_dir, "gateware", src))
def make_multiboot_header(filename, boot_offsets=[160]):
"""
ICE40 allows you to program the SB_WARMBOOT state machine by adding the following
values to the bitstream, before any given image:
[7e aa 99 7e] Sync Header
[92 00 k0] Boot mode (k = 1 for cold boot, 0 for warmboot)
[44 03 o1 o2 o3] Boot address
[82 00 00] Bank offset
[01 08] Reboot
[...] Padding (up to 32 bytes)
Note that in ICE40, the second nybble indicates the number of remaining bytes
(with the exception of the sync header).
The above construct is repeated five times:
INITIAL_BOOT The image loaded at first boot
BOOT_S00 The first image for SB_WARMBOOT
BOOT_S01 The second image for SB_WARMBOOT
BOOT_S10 The third image for SB_WARMBOOT
BOOT_S11 The fourth image for SB_WARMBOOT
"""
while len(boot_offsets) < 5:
boot_offsets.append(boot_offsets[0])
with open(filename, 'wb') as output:
for offset in boot_offsets:
# Sync Header
output.write(bytes([0x7e, 0xaa, 0x99, 0x7e]))
# Boot mode
output.write(bytes([0x92, 0x00, 0x00]))
# Boot address
output.write(bytes([0x44, 0x03,
(offset >> 16) & 0xff,
(offset >> 8) & 0xff,
(offset >> 0) & 0xff]))
# Bank offset
output.write(bytes([0x82, 0x00, 0x00]))
# Reboot command
output.write(bytes([0x01, 0x08]))
for x in range(17, 32):
output.write(bytes([0]))
def main():
parser = argparse.ArgumentParser(
description="Build Fomu Main Gateware")
parser.add_argument(
"--boot-source", choices=["spi", "rand", "bios"], default="bios",
help="where to have the CPU obtain its executable code from"
)
parser.add_argument(
"--document-only", default=False, action="store_true",
help="Don't build gateware or software, only build documentation"
)
parser.add_argument(
"--revision", choices=["evt", "dvt", "pvt", "hacker"], required=True,
help="build foboot for a particular hardware revision"
)
parser.add_argument(
"--bios", help="use specified file as a BIOS, rather than building one"
)
parser.add_argument(
"--with-debug", help="enable debug support", choices=["usb", "uart", "spi", None]
)
parser.add_argument(
"--with-dsp", help="use dsp inference in yosys (not all yosys builds have -dsp)", action="store_true"
)
parser.add_argument(
"--no-cpu", help="disable cpu generation for debugging purposes", action="store_true"
)
parser.add_argument(
"--placer", choices=["sa", "heap"], default="heap", help="which placer to use in nextpnr"
)
parser.add_argument(
"--seed", default=0, help="seed to use in nextpnr"
)
parser.add_argument(
"--export-random-rom-file", help="Generate a random ROM file and save it to a file"
)
args = parser.parse_args()
output_dir = 'build'
if args.export_random_rom_file is not None:
size = 0x2000
def xorshift32(x):
x = x ^ (x << 13) & 0xffffffff
x = x ^ (x >> 17) & 0xffffffff
x = x ^ (x << 5) & 0xffffffff
return x & 0xffffffff
def get_rand(x):
out = 0
for i in range(32):
x = xorshift32(x)
if (x & 1) == 1:
out = out | (1 << i)
return out & 0xffffffff
seed = 1
with open(args.export_random_rom_file, "w", newline="\n") as output:
for d in range(int(size / 4)):
seed = get_rand(seed)
print("{:08x}".format(seed), file=output)
return 0
compile_software = False
if (args.boot_source == "bios" or args.boot_source == "spi") and args.bios is None:
compile_software = True
cpu_type = "vexriscv"
cpu_variant = "min"
if args.with_debug:
cpu_variant = cpu_variant + "+debug"
if args.no_cpu:
cpu_type = None
cpu_variant = None
compile_gateware = True
if args.document_only:
compile_gateware = False
compile_software = False
warmboot_offsets = [
160,
160,
157696,
262144,
262144 + 32768,
]
os.environ["LITEX"] = "1" # Give our Makefile something to look for
platform = Platform(revision=args.revision)
soc = BaseSoC(platform, cpu_type=cpu_type, cpu_variant=cpu_variant,
debug=args.with_debug, boot_source=args.boot_source,
bios_file=args.bios,
use_dsp=args.with_dsp, placer=args.placer,
pnr_seed=int(args.seed),
output_dir=output_dir,
warmboot_offsets=warmboot_offsets[1:])
builder = Builder(soc, output_dir=output_dir, csr_csv="build/csr.csv",
compile_software=compile_software, compile_gateware=compile_gateware)
if compile_software:
builder.software_packages = [
("bios", os.path.abspath(os.path.join(os.path.dirname(__file__), "..", "sw")))
]
vns = builder.build()
soc.do_exit(vns)
lxsocdoc.generate_docs(soc, "build/documentation/", project_name="Fomu Bootloader", author="<NAME>")
lxsocdoc.generate_svd(soc, "build/software", vendor="Foosn", name="Fomu")
if not args.document_only:
make_multiboot_header(os.path.join(output_dir, "gateware", "multiboot-header.bin"),
warmboot_offsets)
with open(os.path.join(output_dir, 'gateware', 'multiboot-header.bin'), 'rb') as multiboot_header_file:
multiboot_header = multiboot_header_file.read()
with open(os.path.join(output_dir, 'gateware', 'top.bin'), 'rb') as top_file:
top = top_file.read()
with open(os.path.join(output_dir, 'gateware', 'top-multiboot.bin'), 'wb') as top_multiboot_file:
top_multiboot_file.write(multiboot_header)
top_multiboot_file.write(top)
print(
"""Foboot build complete. Output files:
{}/gateware/top.bin Bitstream file. Load this onto the FPGA for testing.
{}/gateware/top-multiboot.bin Multiboot-enabled bitstream file. Flash this onto FPGA ROM.
{}/gateware/top.v Source Verilog file. Useful for debugging issues.
{}/software/include/generated/ Directory with header files for API access.
{}/software/bios/bios.elf ELF file for debugging bios.
""".format(output_dir, output_dir, output_dir, output_dir, output_dir))
if __name__ == "__main__":
main()
| [
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"litex.build.lattice.platform.LatticePlatform.__init__",
"litex.soc.cores.spi_flash.SpiFlashDualQuad",
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#!/usr/bin/env python3
import argparse
from migen import *
from litex.gen.fhdl.utils import get_signals
from litex.build.generic_platform import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.sim.verilator import verilator_build_args, verilator_build_argdict
from litex.soc.interconnect import avalon
from litex.soc.interconnect import wishbone
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from liteeth.phy.model import LiteEthPHYModel
from litescope import LiteScopeAnalyzer
from pcie_mitm.ip.gpio import AvalonMMGPIO
# IOs ----------------------------------------------------------------------------------------------
_io = [
("sys_clk", 0, Pins(1)),
("sys_rst", 0, Pins(1)),
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
("eth_clocks", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
),
("eth", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
# Leds.
("user_led", 0, Pins(1)),
("user_led", 1, Pins(1)),
("user_led", 2, Pins(1)),
("user_led", 3, Pins(1)),
("user_led", 4, Pins(1)),
("user_led", 5, Pins(1)),
("user_led", 6, Pins(1)),
("user_led", 7, Pins(1)),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(SimPlatform):
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
# Bench SoC ----------------------------------------------------------------------------------------
class SimSoC(SoCCore):
def __init__(self, sys_clk_freq = None, trace=False, **kwargs):
platform = Platform()
sys_clk_freq = int(sys_clk_freq)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq,
ident = "Avalon-MM GPIO WB bridge test simulation",
**kwargs)
self.add_constant("CONFIG_DISABLE_DELAYS", 1)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(platform.request("sys_clk"))
# Trace ------------------------------------------------------------------------------------
self.platform.add_debug(self, reset=0)
# Etherbone --------------------------------------------------------------------------------
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.add_etherbone(phy=self.ethphy, ip_address = "192.168.42.50", buffer_depth=16*4096-1)
# Leds -------------------------------------------------------------------------------------
led_pads = platform.request_all("user_led")
if False:
self.submodules.leds = LedChaser(
pads = led_pads,
sys_clk_freq = sys_clk_freq)
else:
self.submodules.led_gpio = AvalonMMGPIO(self.platform)
for src, sink in zip(self.led_gpio.out_port, led_pads):
self.comb += sink.eq(src)
self.led_gpio_wb = wishbone.Interface(adr_width=2)
self.add_memory_region("gpio", 0x9000_0000, length=4*4, type="io")
self.add_wb_slave(0x9000_0000, self.led_gpio_wb)
self.submodules.led_gpio_avmm2wb = avalon.AvalonMM2Wishbone(self.led_gpio.avmm, self.led_gpio_wb)
if True:
analyzer_signals = set([
*get_signals(led_pads),
*get_signals(self.led_gpio),
*get_signals(self.led_gpio_wb),
*get_signals(self.led_gpio_avmm2wb),
])
analyzer_signals_denylist = set([
])
analyzer_signals -= analyzer_signals_denylist
analyzer_signals = list(analyzer_signals)
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 64*1,
register = True,
clock_domain = "sys",
samplerate = sys_clk_freq,
csr_csv = "analyzer.csv")
# Main ---------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteEth Bench Simulation")
parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency (default: 200MHz)")
parser.add_argument("--debug-soc-gen", action="store_true", help="Don't run simulation")
builder_args(parser)
soc_core_args(parser)
verilator_build_args(parser)
args = parser.parse_args()
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=args.sys_clk_freq)
sim_config.add_module("serial2console", "serial")
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.42.100"})
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
verilator_build_kwargs = verilator_build_argdict(args)
soc_kwargs['sys_clk_freq'] = int(args.sys_clk_freq)
soc_kwargs['uart_name'] = 'sim'
# soc_kwargs['cpu_type'] = 'None'
soc_kwargs['cpu_type'] = 'femtorv' # slow
soc_kwargs['cpu_variant'] = 'quark'
builder_kwargs['csr_csv'] = 'csr.csv'
soc = SimSoC(
trace=args.trace,
trace_reset_on=int(float(args.trace_start)) > 0 or int(float(args.trace_end)) > 0,
**soc_kwargs)
if not args.debug_soc_gen:
builder = Builder(soc, **builder_kwargs)
for i in range(2):
build = (i == 0)
run = (i == 1)
builder.build(
build=build,
run=run,
sim_config=sim_config,
**verilator_build_kwargs,
)
if __name__ == "__main__":
main()
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#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.cores.emif import EMIF
class EMIFPads:
def __init__(self):
self.cs_n = Signal(reset=1)
self.we_n = Signal(reset=1)
self.oe_n = Signal(reset=1)
self.wait_n = Signal(reset=1)
self.ba = Signal(2)
self.addr = Signal(22)
self.dqm_n = Signal(2)
self.data = Record([("oe", 1), ("o", 16), ("i", 16)])
def emif_write(pads, addr, data, release_cs=True):
for i in range(2):
yield pads.cs_n.eq(0)
yield pads.we_n.eq(1)
yield pads.oe_n.eq(1)
yield pads.ba.eq(1<<i)
yield pads.addr.eq(addr)
yield pads.data.i.eq((data >> 16*i) & 0xffff)
yield
yield pads.we_n.eq(0)
for i in range(8):
yield
yield pads.we_n.eq(1)
yield
yield pads.cs_n.eq(release_cs)
yield
def emif_read(pads, addr, release_cs=True, release_oe=True):
data = 0
for i in range(2):
yield pads.cs_n.eq(0)
yield pads.we_n.eq(1)
yield pads.oe_n.eq(release_oe)
yield pads.ba.eq(1<<i)
yield pads.addr.eq(addr)
yield
yield pads.oe_n.eq(0)
for i in range(8):
yield
data >>= 16
data |= (yield pads.data.o) << 16
yield pads.oe_n.eq(release_oe)
yield
yield pads.cs_n.eq(release_cs)
yield
return data
class TestEMIF(unittest.TestCase):
def test_emif(self):
pads = EMIFPads()
def generator(dut):
# Test writes/reads with cs release between accesses
yield from emif_write(pads, 0, 0xdeadbeef, True)
yield from emif_write(pads, 1, 0x12345678, True)
yield from emif_write(pads, 2, 0x5aa55aa5, True)
self.assertEqual((yield from emif_read(pads, 0, True)), 0xdeadbeef)
self.assertEqual((yield from emif_read(pads, 1, True)), 0x12345678)
self.assertEqual((yield from emif_read(pads, 2, True)), 0x5aa55aa5)
# Test writes/reads without cs release between accesses
yield from emif_write(pads, 0, 0xdeadbeef, False)
yield from emif_write(pads, 1, 0x12345678, False)
yield from emif_write(pads, 2, 0x5aa55aa5, False)
self.assertEqual((yield from emif_read(pads, 0, False)), 0xdeadbeef)
self.assertEqual((yield from emif_read(pads, 1, False)), 0x12345678)
self.assertEqual((yield from emif_read(pads, 2, False)), 0x5aa55aa5)
class DUT(Module):
def __init__(self, pads):
emif = EMIF(pads)
self.submodules += emif
mem = wishbone.SRAM(16, bus=emif.bus)
self.submodules += mem
dut = DUT(pads)
run_simulation(dut, [generator(dut)])
| [
"litex.soc.interconnect.wishbone.SRAM",
"litex.soc.cores.emif.EMIF"
] | [((2785, 2795), 'litex.soc.cores.emif.EMIF', 'EMIF', (['pads'], {}), '(pads)\n', (2789, 2795), False, 'from litex.soc.cores.emif import EMIF\n'), ((2858, 2889), 'litex.soc.interconnect.wishbone.SRAM', 'wishbone.SRAM', (['(16)'], {'bus': 'emif.bus'}), '(16, bus=emif.bus)\n', (2871, 2889), False, 'from litex.soc.interconnect import wishbone\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk100", 0, Pins("F22"), IOStandard("LVCMOS33")),
("clk150", 0,
Subsignal("p", Pins("G24"), IOStandard("TMDS_33")),
Subsignal("n", Pins("F24"), IOStandard("TMDS_33"))
),
("cpu_reset", 0, Pins("C26"), IOStandard("LVCMOS33"), Misc("PULLDOWN=True")), # Active high, pulldown needed.
# Leds (activive-low)
("rgb_led", 0,
Subsignal("r", Pins("J26")),
Subsignal("g", Pins("H26")),
Subsignal("b", Pins("G26")),
IOStandard("LVCMOS33"),
),
# FAN
("fan", 0, Pins("J25"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("H22")),
Subsignal("rx", Pins("K22")),
Subsignal("rts", Pins("L22")),
Subsignal("cts", Pins("L23")),
Subsignal("cbus0", Pins("K23")),
IOStandard("LVCMOS33")
),
# XADC
("xadc", 0,
Subsignal("adc_p", Pins("C16 A18 B17")),
Subsignal("adc_n", Pins("B16 A19 A17")),
Subsignal("v_p", Pins("N12")),
Subsignal("v_n", Pins("P11")),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"AF7 AE7 AC7 AB7 AA7 AC8 AC9 AA9",
"AD8 V9 Y11 Y7 W10 Y8 Y10 W9"),
IOStandard("SSTL135")),
Subsignal("ba", Pins("AA8 AD9 AB9"), IOStandard("SSTL135")),
Subsignal("ras_n", Pins("AC13"), IOStandard("SSTL135")),
Subsignal("cas_n", Pins("AC12"), IOStandard("SSTL135")),
Subsignal("we_n", Pins("AA13"), IOStandard("SSTL135")),
Subsignal("cs_n", Pins("AB12"), IOStandard("SSTL135")),
Subsignal("dm", Pins(
"W16 AD18 AE15 AB15 AD1 AC3 Y3 V6"),
IOStandard("SSTL135")),
Subsignal("dq", Pins(
"V19 V16 Y17 V14 V17 V18 W14 W15",
"AB17 AB19 AC18 AC19 AA19 AA20 AC17 AD19",
"AD16 AD15 AF20 AE17 AF17 AF19 AF14 AF15",
"AB16 AA15 AA14 AC14 AA18 AA17 AD14 AB14",
"AE3 AE6 AE2 AF3 AD4 AE5 AE1 AF2",
"AB6 Y6 AB4 AC4 AC6 AD6 Y5 AA4",
"AB2 AC2 V1 W1 V2 AA3 Y1 Y2",
"V4 V3 U2 U1 U7 W3 U6 U5"),
IOStandard("SSTL135_T_DCI")),
Subsignal("dqs_p", Pins("W18 AD20 AE18 Y15 AF5 AA5 AB1 W6"),
IOStandard("DIFF_SSTL135")),
Subsignal("dqs_n", Pins("W19 AE20 AF18 Y16 AF4 AB5 AC1 W5"),
IOStandard("DIFF_SSTL135")),
Subsignal("clk_p", Pins("V11"), IOStandard("DIFF_SSTL135")),
Subsignal("clk_n", Pins("W11"), IOStandard("DIFF_SSTL135")),
Subsignal("cke", Pins("AA10"), IOStandard("SSTL135")),
Subsignal("odt", Pins("AD13"), IOStandard("SSTL135")),
Subsignal("reset_n", Pins("AA2"), IOStandard("SSTL135")),
Misc("SLEW=FAST"),
),
# SPIFlash
("spiflash", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
Subsignal("mosi", Pins("B24")),
Subsignal("miso", Pins("A25")),
Subsignal("wp", Pins("B22")),
Subsignal("hold", Pins("A22")),
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
Subsignal("cs_n", Pins("C23")),
Subsignal("dq", Pins("B24", "A25", "B22", "A22")),
IOStandard("LVCMOS33")
),
# SDCard
("sdcard", 0,
Subsignal("cmd", Pins("H24")),
Subsignal("clk", Pins("G22")),
Subsignal("dat", Pins("F25 E25 J23 H23")),
IOStandard("LVCMOS33")
),
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4")),
Subsignal("rx_n", Pins("J3")),
Subsignal("tx_p", Pins("H2")),
Subsignal("tx_n", Pins("H1"))
),
("pcie_x2", 0,
Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4 L4")),
Subsignal("rx_n", Pins("J3 L3")),
Subsignal("tx_p", Pins("H2 K2")),
Subsignal("tx_n", Pins("H1 K1"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("E21"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")),
Subsignal("clk_p", Pins("K6")),
Subsignal("clk_n", Pins("K5")),
Subsignal("rx_p", Pins("J4 L4 N4 R4")),
Subsignal("rx_n", Pins("J3 L3 N3 R3")),
Subsignal("tx_p", Pins("H2 K2 M2 P2")),
Subsignal("tx_n", Pins("H1 K1 M1 P1"))
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
# FMC GTP Section
"DP0_M2C_P" : "G4",
"DP0_M2C_N" : "G3",
"DP1_M2C_P" : "E4",
"DP1_M2C_N" : "E3",
"DP2_M2C_P" : "C4",
"DP2_M2C_N" : "C3",
"DP3_M2C_P" : "B6",
"DP3_M2C_N" : "B5",
"GBTCLK0_M2C_P" : "F6",
"GBTCLK0_M2C_N" : "F5",
"GBTCLK1_M2C_P" : "D6",
"GBTCLK1_M2C_N" : "D5",
"DP0_C2M_P" : "F2",
"DP0_C2M_N" : "F1",
"DP1_C2M_P" : "D2",
"DP1_C2M_N" : "D1",
"DP2_C2M_P" : "B2",
"DP2_C2M_N" : "B1",
"DP3_C2M_P" : "A4",
"DP3_C2M_N" : "A3",
# FMC LA Bank GPIOs
"LA00_P" : "AA23",
"LA00_N" : "AB24",
"LA01_P" : "Y23",
"LA01_N" : "AA24",
"LA02_P" : "AD26",
"LA02_N" : "AE26",
"LA03_P" : "AA25",
"LA03_N" : "AB25",
"LA04_P" : "AD25",
"LA04_N" : "AE25",
"LA05_P" : "W25",
"LA05_N" : "W26",
"LA06_P" : "Y25",
"LA06_N" : "Y26",
"LA07_P" : "V23",
"LA07_N" : "V24",
"LA08_P" : "U26",
"LA08_N" : "V26",
"LA09_P" : "W20",
"LA09_N" : "Y21",
"LA10_P" : "V21",
"LA10_N" : "W21",
"LA11_P" : "L19",
"LA11_N" : "L20",
"LA12_P" : "M17",
"LA12_N" : "L18",
"LA13_P" : "K20",
"LA13_N" : "J20",
"LA14_P" : "J18",
"LA14_N" : "J19",
"LA15_P" : "U17",
"LA15_N" : "T17",
"LA16_P" : "T18",
"LA16_N" : "T19",
"LA17_P" : "E18",
"LA17_N" : "D18",
"LA18_P" : "F17",
"LA18_N" : "E17",
"LA19_P" : "H16",
"LA19_N" : "G16",
"LA20_P" : "K16",
"LA20_N" : "K17",
"LA21_P" : "D19",
"LA21_N" : "D20",
"LA22_P" : "C19",
"LA22_N" : "B19",
"LA23_P" : "C17",
"LA23_N" : "C18",
"LA24_P" : "D15",
"LA24_N" : "D16",
"LA25_P" : "F19",
"LA25_N" : "E20",
"LA26_P" : "J15",
"LA26_N" : "J16",
"LA27_P" : "G15",
"LA27_N" : "F15",
"LA28_P" : "G17",
"LA28_N" : "F18",
"LA29_P" : "E15",
"LA29_N" : "E16",
"LA30_P" : "H17",
"LA30_N" : "H18",
"LA31_P" : "G19",
"LA31_N" : "F20",
"LA32_P" : "H19",
"LA32_N" : "G20",
"LA33_P" : "L17",
"LA33_N" : "K18",
# FMC HA Bank GPIOs
"HA00_P" : "P23",
"HA00_N" : "N23",
"HA01_P" : "N21",
"HA01_N" : "N22",
"HA02_P" : "AB22",
"HA02_N" : "AC22",
"HA03_P" : "AD23",
"HA03_N" : "AD24",
"HA04_P" : "N19",
"HA04_N" : "M20",
"HA05_P" : "R18",
"HA05_N" : "P18",
"HA06_P" : "P16",
"HA06_N" : "N17",
"HA07_P" : "R16",
"HA07_N" : "R17",
"HA08_P" : "U19",
"HA08_N" : "U20",
"HA09_P" : "N18",
"HA09_N" : "M19",
"HA10_P" : "T20",
"HA10_N" : "R20",
"HA11_P" : "P19",
"HA11_N" : "P20",
"HA12_P" : "T24",
"HA12_N" : "T25",
"HA13_P" : "U24",
"HA13_N" : "U25",
"HA14_P" : "R26",
"HA14_N" : "P26",
"HA15_P" : "P24",
"HA15_N" : "N24",
"HA16_P" : "R25",
"HA16_N" : "P25",
"HA17_P" : "M21",
"HA17_N" : "M22",
"HA18_P" : "N26",
"HA18_N" : "M26",
"HA19_P" : "K25",
"HA19_N" : "K26",
"HA20_P" : "M25",
"HA20_N" : "L25",
"HA21_P" : "M24",
"HA21_N" : "L24",
"HA22_P" : "T22",
"HA22_N" : "T23",
"HA23_P" : "U22",
"HA23_N" : "V22",
# FMC HB Bank GPIOs
"HB00_P" : "E10",
"HB00_N" : "D10",
"HB01_P" : "F14",
"HB01_N" : "F13",
"HB02_P" : "H14",
"HB02_N" : "G14",
"HB03_P" : "J13",
"HB03_N" : "H13",
"HB04_P" : "B14",
"HB04_N" : "A14",
"HB05_P" : "B15",
"HB05_N" : "A15",
"HB06_P" : "C12",
"HB06_N" : "C11",
"HB07_P" : "G10",
"HB07_N" : "G9",
"HB08_P" : "E13",
"HB08_N" : "E12",
"HB09_P" : "D14",
"HB09_N" : "D13",
"HB10_P" : "C9",
"HB10_N" : "B9",
"HB11_P" : "A13",
"HB11_N" : "A12",
"HB12_P" : "B10",
"HB12_N" : "A10",
"HB13_P" : "B12",
"HB13_N" : "B11",
"HB14_P" : "F9",
"HB14_N" : "F8",
"HB15_P" : "E11",
"HB15_N" : "D11",
"HB16_P" : "D9",
"HB16_N" : "D8",
"HB17_P" : "G11",
"HB17_N" : "F10",
"HB18_P" : "G12",
"HB18_N" : "F12",
"HB19_P" : "A9",
"HB19_N" : "A8",
"HB20_P" : "J11",
"HB20_N" : "J10",
"HB21_P" : "H9",
"HB21_N" : "H8",
# FMC Clock and Misc signals
"CLK0_M2C_P" : "Y22",
"CLK0_M2C_N" : "AA22",
"CLK1_M2C_P" : "AC23",
"CLK1_M2C_N" : "AC24",
"CLK2_BIDIR_P" : "R22",
"CLK2_BIDIR_N" : "R23",
"CLK3_BIDIR_P" : "R21",
"CLK3_BIDIR_N" : "P21",
"CLK_DIR" : "D23",
"PG_C2M" : "D26",
"PG_M2C" : "E26",
"FMC_SCL" : "C21",
"FMC_SDA" : "B21",
"FMC_PRSNT" : "B26",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xc7k160t-fbg676-1", _io, _connectors, toolchain=toolchain)
self.add_platform_command("""
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
""")
self.toolchain.bitstream_commands = [
"set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]",
"set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]",
"set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
self.add_period_constraint(self.lookup_request("clk150", loose=True), 1e9/150e6)
| [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((10824, 10917), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7k160t-fbg676-1"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'xc7k160t-fbg676-1', _io, _connectors,\n toolchain=toolchain)\n", (10847, 10917), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((11580, 11638), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft232.cfg"""', '"""bscan_spi_xc7k160t.bit"""'], {}), "('openocd_xc7_ft232.cfg', 'bscan_spi_xc7k160t.bit')\n", (11587, 11638), False, 'from litex.build.openocd import OpenOCD\n'), ((11685, 11727), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (11711, 11727), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
import unittest
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.stream import EndpointDescription, Endpoint
from litex.soc.interconnect.csr import *
def data_stream_description(dw):
payload_layout = [("data", dw)]
return EndpointDescription(payload_layout)
class dummySource(Module):
def __init__(self):
self.source = source = Endpoint(data_stream_description(32))
counter = Signal(32)
self.clr = Signal()
frame = Signal(32)
v_ctr = Signal(32)
h_ctr = Signal(32)
r = Signal(8)
g = Signal(8)
b = Signal(8)
self.comb += [
source.valid.eq(1),
source.data.eq(Cat(r,g,b,Signal(8))),
]
self.sync += [
If(source.ready,
h_ctr.eq(h_ctr + 1),
If(h_ctr >= 800-1,
h_ctr.eq(0),
v_ctr.eq(v_ctr + 1),
If(v_ctr >= 600-1,
v_ctr.eq(0),
frame.eq(frame + 1)
)
)
),
If(self.clr,
v_ctr.eq(0),
h_ctr.eq(0)
)
]
speed = 1
frame_tri = (Mux(frame[8], ~frame[:8], frame[:8]))
frame_tri2 = (Mux(frame[9], ~frame[1:9], frame[1:9]))
X = Mux(v_ctr[6], h_ctr + frame[speed:], h_ctr - frame[speed:])
Y = v_ctr
self.sync += [
r.eq(frame_tri[1:]),
g.eq(v_ctr * Mux(X & Y, 255, 0)),
b.eq(~(frame_tri2 + (X ^ Y)) * 255)
]
class dummySink(Module):
def __init__(self):
self.sink = sink = Endpoint(data_stream_description(32))
self.comb += [
sink.ready.eq(1)
]
@ResetInserter()
class StreamWriter(Module, AutoCSR):
def __init__(self):
self.bus = bus = wishbone.Interface()
self.source = source = Endpoint(data_stream_description(32))
self._sinks = []
tx_cnt = Signal(32)
last_address = Signal()
busy = Signal()
done = Signal()
evt_done = Signal()
active = Signal()
burst_end = Signal()
burst_cnt = Signal(32)
adr = Signal(32)
self.transfer_size = CSRStorage(32)
self.burst_size = CSRStorage(32, reset=256)
self.start_address = CSRStorage(32)
self.done = CSRStatus()
self.enable = CSR()
self._reset = CSR()
self.start = Signal()
self.short = Signal()
self.external_sync = CSRStorage()
self.sink_csr = CSRStorage(4, name="sink_mux")
self.enabled = enabled = Signal()
overflow = Signal()
underflow = Signal()
self.comb += [
overflow.eq(source.ready & ~source.valid),
underflow.eq(~source.ready & source.valid),
self.done.status.eq(done)
]
self.comb += [
bus.sel.eq(0xF),
bus.we.eq(0),
bus.cyc.eq(active),
bus.stb.eq(active),
bus.adr.eq(adr[:-2] + tx_cnt),
source.data.eq(bus.dat_r),
source.valid.eq(bus.ack & active),
If(~active,
bus.cti.eq(0b000) # CLASSIC_CYCLE
).Elif(burst_end,
bus.cti.eq(0b111), # END-OF-BURST
).Else(
bus.cti.eq(0b010), # LINEAR_BURST
),
]
self.comb += [
burst_end.eq(last_address | (burst_cnt == self.burst_size.storage - 1)),
last_address.eq(tx_cnt >= self.transfer_size.storage - 1),
]
self.sync += [
If(bus.ack & active,
If(last_address,
tx_cnt.eq(0)
).Else(
tx_cnt.eq(tx_cnt + 1)
)
),
# Burst Counter
If(~active,
burst_cnt.eq(0)
).Else(
If(bus.ack & active,
burst_cnt.eq(burst_cnt + 1)
)
),
If(self.enable.re,
enabled.eq(self.enable.r[0])
),
If(evt_done,
done.eq(1),
)
]
# Main FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(busy & source.ready,
NextState("ACTIVE"),
),
If((self.start & enabled & self.external_sync.storage) | (~self.external_sync.storage & self.enable.re),
NextValue(busy,1),
NextValue(adr, self.start_address.storage),
)
)
fsm.act("ACTIVE",
If(~source.ready,
NextState("IDLE")
),
If(burst_end & bus.ack & active,
NextState("IDLE"),
If(last_address,
evt_done.eq(1),
NextValue(busy,0),
)
),
)
self.comb += active.eq(fsm.ongoing("ACTIVE") & source.ready)
def do_finalize(self):
self.comb += self.reset.eq(self._reset.re)
def add_sink(self, sink, sink_name, ext_start=Signal()):
self._sinks += [(sink, sink_name, ext_start)]
#s,name = self._sinks[i]
self.comb += [
If(self.sink_csr.storage == (len(self._sinks) - 1),
self.source.connect(sink),
self.start.eq(ext_start)
)
]
@ResetInserter()
class StreamReader(Module, AutoCSR):
def __init__(self):
self.bus = bus = wishbone.Interface()
self.sink = sink = Endpoint(data_stream_description(32))
self._sources = []
tx_cnt = Signal(32)
last_address = Signal()
busy = Signal()
done = Signal()
self.evt_done = evt_done = Signal()
active = Signal()
burst_end = Signal()
burst_cnt = Signal(32)
adr = Signal(32)
self.transfer_size = CSRStorage(32)
self.burst_size = CSRStorage(32, reset=256)
self.start_address = CSRStorage(32)
self.done = CSRStatus()
self.enable = CSR()
self._reset = CSR()
self.start = Signal()
self.external_sync = CSRStorage()
self.source_csr = CSRStorage(4, name="source_mux")
self.enabled = enabled = Signal()
overflow = Signal()
underflow = Signal()
self.comb += [
overflow.eq(sink.ready & ~sink.valid),
underflow.eq(~sink.ready & sink.valid),
self.done.status.eq(done)
]
self.comb += [
bus.sel.eq(0xF),
bus.we.eq(active),
bus.cyc.eq(active),
bus.stb.eq(active),
bus.adr.eq(adr[:-2] + tx_cnt),
bus.dat_w.eq(sink.data),
sink.ready.eq(bus.ack & active),
If(~active,
bus.cti.eq(0b000) # CLASSIC_CYCLE
).Elif(burst_end,
bus.cti.eq(0b111), # END-OF-BURST
).Else(
bus.cti.eq(0b010), # LINEAR_BURST
)
]
self.comb += [
#If(self._burst_size.storage == 1,
# burst_end.eq(1),
#).Else(
burst_end.eq(last_address | (burst_cnt == self.burst_size.storage - 1)),
last_address.eq(tx_cnt == self.transfer_size.storage - 1),
#)
]
self.sync += [
If(bus.ack & active,
If(last_address,
tx_cnt.eq(0)
).Else(
tx_cnt.eq(tx_cnt + 1)
)
),
# Burst Counter
If(~active,
burst_cnt.eq(0)
).Else(
If(bus.ack & active,
burst_cnt.eq(burst_cnt + 1)
)
),
If(self.enable.re,
enabled.eq(self.enable.r[0])
),
If(evt_done,
done.eq(1),
),
]
# Main FSM
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(busy & sink.valid,
NextState("ACTIVE"),
),
If((self.start & enabled & self.external_sync.storage) | (~self.external_sync.storage & self.enable.re),
NextValue(busy,1),
NextValue(adr, self.start_address.storage),
)
)
fsm.act("ACTIVE",
If(~sink.valid,
NextState("IDLE")
),
If(burst_end & bus.ack & active,
NextState("IDLE"),
If(last_address,
NextValue(busy,0),
evt_done.eq(1),
)
),
)
self.comb += active.eq(fsm.ongoing("ACTIVE") & sink.valid)
def do_finalize(self):
self.comb += [
self.reset.eq(self._reset.re),
]
def add_source(self, source, source_name, ext_start=Signal()):
self._sources += [(source, source_name, ext_start)]
#s,name = self._sinks[i]
self.comb += [
If(self.source_csr.storage == (len(self._sources) - 1),
#self.sink.connect(source),
source.connect(self.sink),
self.start.eq(ext_start)
)
]
# -=-=-=-= tests -=-=-=-=
def write_stream(stream, dat):
yield stream.data.eq(dat)
yield stream.valid.eq(1)
yield
yield stream.data.eq(0)
yield stream.valid.eq(0)
class TestWriter(unittest.TestCase):
def test_dma_write(self):
def write(dut):
dut = dut.reader
yield from dut.start_address.write(0x0)
yield from dut.transfer_size.write(4)
yield from dut.burst_size.write(2)
yield from dut.enable.write(1)
yield
for _ in range(64):
yield
yield
def logger(dut):
yield dut.reader.sink.valid.eq(1)
for j in range(2):
while (yield dut.reader.bus.cyc == 0):
yield
for _ in range(4):
yield
for i in range(2):
yield dut.reader.bus.ack.eq(1)
yield dut.reader.sink.valid.eq(~((j == 1) & (i == 0)))
yield
#yield
yield dut.reader.bus.ack.eq(0)
yield
class test(Module):
def __init__(self):
self.submodules.reader = StreamReader()
self.submodules.dummySource = ds = dummySource()
#self.comb += ds.source.connect(self.reader.sink)
dut = test()
run_simulation(dut, [write(dut), logger(dut)], vcd_name='write.vcd')
if __name__ == '__main__':
unittest.main() | [
"litex.soc.interconnect.stream.EndpointDescription",
"litex.soc.interconnect.wishbone.Interface"
] | [((344, 379), 'litex.soc.interconnect.stream.EndpointDescription', 'EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (363, 379), False, 'from litex.soc.interconnect.stream import EndpointDescription, Endpoint\n'), ((11120, 11135), 'unittest.main', 'unittest.main', ([], {}), '()\n', (11133, 11135), False, 'import unittest\n'), ((1993, 2013), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2011, 2013), False, 'from litex.soc.interconnect import wishbone\n'), ((5752, 5772), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (5770, 5772), False, 'from litex.soc.interconnect import wishbone\n')] |
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.csr import *
from migen import *
class StartWriter(Module, AutoCSR):
def __init__(self, signal):
self.signal = signal
self._start = CSRStorage(1, reset=0)
self.comb += signal.eq(self._start.storage)
def get_ios(self, bus_name="start"):
subsignals = []
subsignals.append(Subsignal("signal", Pins(1)))
return [(bus_name, 0) + tuple(subsignals)]
def connect_to_pads(self, pads):
r = []
r.append(pads.signal.eq(self.signal))
return r
| [
"litex.build.generic_platform.Pins"
] | [((426, 433), 'litex.build.generic_platform.Pins', 'Pins', (['(1)'], {}), '(1)\n', (430, 433), False, 'from litex.build.generic_platform import Pins, Subsignal\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import copy
import random
import unittest
from collections import namedtuple
from migen import *
from litex.soc.interconnect import stream
from litedram.common import *
from litedram.phy import dfi
from litedram.core.multiplexer import Multiplexer
# load after "* imports" to avoid using Migen version of vcd.py
from litex.gen.sim import run_simulation
from test.common import timeout_generator, CmdRequestRWDriver
def dfi_cmd_to_char(cas_n, ras_n, we_n):
return {
(1, 1, 1): "_",
(0, 1, 0): "w",
(0, 1, 1): "r",
(1, 0, 1): "a",
(1, 0, 0): "p",
(0, 0, 1): "f",
}[(cas_n, ras_n, we_n)]
class BankMachineStub:
def __init__(self, babits, abits):
self.cmd = stream.Endpoint(cmd_request_rw_layout(a=abits, ba=babits))
self.refresh_req = Signal()
self.refresh_gnt = Signal()
class RefresherStub:
def __init__(self, babits, abits):
self.cmd = stream.Endpoint(cmd_request_rw_layout(a=abits, ba=babits))
class MultiplexerDUT(Module):
# Define default settings that can be overwritten in specific tests use only these settings
# that we actually need for Multiplexer.
default_controller_settings = dict(
read_time = 32,
write_time = 16,
with_bandwidth = False,
)
default_phy_settings = dict(
nphases = 2,
rdphase = 0,
wrphase = 1,
rdcmdphase = 1,
wrcmdphase = 0,
read_latency = 5,
cwl = 3,
# Indirectly
nranks = 1,
databits = 16,
dfi_databits = 2*16,
memtype = "DDR2",
)
default_geom_settings = dict(
bankbits = 3,
rowbits = 13,
colbits = 10,
)
default_timing_settings = dict(
tWTR = 2,
tFAW = None,
tCCD = 1,
tRRD = None,
)
def __init__(self,
controller_settings = None,
phy_settings = None,
geom_settings = None,
timing_settings = None):
# Update settings if provided
def updated(settings, update):
copy = settings.copy()
copy.update(update or {})
return copy
controller_settings = updated(self.default_controller_settings, controller_settings)
phy_settings = updated(self.default_phy_settings, phy_settings)
geom_settings = updated(self.default_geom_settings, geom_settings)
timing_settings = updated(self.default_timing_settings, timing_settings)
# Use simpler settigns to include only Multiplexer-specific members
class SimpleSettings(Settings):
def __init__(self, **kwargs):
self.set_attributes(kwargs)
settings = SimpleSettings(**controller_settings)
settings.phy = SimpleSettings(**phy_settings)
settings.geom = SimpleSettings(**geom_settings)
settings.timing = SimpleSettings(**timing_settings)
settings.geom.addressbits = max(settings.geom.rowbits, settings.geom.colbits)
self.settings = settings
# Create interfaces and stubs required to instantiate Multiplexer
abits = settings.geom.addressbits
babits = settings.geom.bankbits
nbanks = 2**babits
nranks = settings.phy.nranks
self.bank_machines = [BankMachineStub(abits=abits, babits=babits)
for _ in range(nbanks*nranks)]
self.refresher = RefresherStub(abits=abits, babits=babits)
self.dfi = dfi.Interface(
addressbits = abits,
bankbits = babits,
nranks = settings.phy.nranks,
databits = settings.phy.dfi_databits,
nphases = settings.phy.nphases)
address_align = log2_int(burst_lengths[settings.phy.memtype])
self.interface = LiteDRAMInterface(address_align=address_align, settings=settings)
# Add Multiplexer
self.submodules.multiplexer = Multiplexer(settings, self.bank_machines, self.refresher,
self.dfi, self.interface)
# Add helpers for driving bank machines/refresher
self.bm_drivers = [CmdRequestRWDriver(bm.cmd, i) for i, bm in enumerate(self.bank_machines)]
self.refresh_driver = CmdRequestRWDriver(self.refresher.cmd, i=1)
def fsm_state(self):
# Return name of current state of Multiplexer's FSM
return self.multiplexer.fsm.decoding[(yield self.multiplexer.fsm.state)]
class TestMultiplexer(unittest.TestCase):
def test_init(self):
# Verify that instantiation of Multiplexer in MultiplexerDUT is correct. This will fail if
# Multiplexer starts using any new setting from controller.settings.
MultiplexerDUT()
def test_fsm_start_at_read(self):
# FSM should start at READ state (assumed in some other tests).
def main_generator(dut):
self.assertEqual((yield from dut.fsm_state()), "READ")
dut = MultiplexerDUT()
run_simulation(dut, main_generator(dut))
def test_fsm_read_to_write_latency(self):
# Verify the timing of READ to WRITE transition.
def main_generator(dut):
rtw = dut.settings.phy.read_latency
expected = "r" + (rtw - 1) * ">" + "w"
states = ""
# Set write_available=1
yield from dut.bm_drivers[0].write()
yield
for _ in range(len(expected)):
state = (yield from dut.fsm_state())
# Use ">" for all other states, as FSM.delayed_enter uses anonymous states instead
# of staying in RTW
states += {
"READ": "r",
"WRITE": "w",
}.get(state, ">")
yield
self.assertEqual(states, expected)
dut = MultiplexerDUT()
run_simulation(dut, main_generator(dut))
def test_fsm_write_to_read_latency(self):
# Verify the timing of WRITE to READ transition.
def main_generator(dut):
write_latency = math.ceil(dut.settings.phy.cwl / dut.settings.phy.nphases)
wtr = dut.settings.timing.tWTR + write_latency + dut.settings.timing.tCCD or 0
expected = "w" + (wtr - 1) * ">" + "r"
states = ""
# Simulate until we are in WRITE
yield from dut.bm_drivers[0].write()
while (yield from dut.fsm_state()) != "WRITE":
yield
# Set read_available=1
yield from dut.bm_drivers[0].read()
yield
for _ in range(len(expected)):
state = (yield from dut.fsm_state())
states += {
"READ": "r",
"WRITE": "w",
}.get(state, ">")
yield
self.assertEqual(states, expected)
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_steer_read_correct_phases(self):
# Check that correct phases are being used during READ.
def main_generator(dut):
yield from dut.bm_drivers[2].read()
yield from dut.bm_drivers[3].activate()
while not (yield dut.bank_machines[2].cmd.ready):
yield
yield
# fsm starts in READ
for phase in range(dut.settings.phy.nphases):
if phase == dut.settings.phy.rdphase:
self.assertEqual((yield dut.dfi.phases[phase].bank), 2)
elif phase == dut.settings.phy.rdcmdphase:
self.assertEqual((yield dut.dfi.phases[phase].bank), 3)
else:
self.assertEqual((yield dut.dfi.phases[phase].bank), 0)
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_steer_write_correct_phases(self):
# Check that correct phases are being used during WRITE.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
yield from dut.bm_drivers[3].activate()
while not (yield dut.bank_machines[2].cmd.ready):
yield
yield
# fsm starts in READ
for phase in range(dut.settings.phy.nphases):
if phase == dut.settings.phy.wrphase:
self.assertEqual((yield dut.dfi.phases[phase].bank), 2)
elif phase == dut.settings.phy.wrcmdphase:
self.assertEqual((yield dut.dfi.phases[phase].bank), 3)
else:
self.assertEqual((yield dut.dfi.phases[phase].bank), 0)
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_single_phase_cmd_req(self):
# Verify that, for a single phase, commands are sent sequentially.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
yield from dut.bm_drivers[3].activate()
ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
# Activate should appear first
while not ((yield ready[2]) or (yield ready[3])):
yield
yield from dut.bm_drivers[3].nop()
yield
self.assertEqual((yield dut.dfi.phases[0].bank), 3)
# Then write
while not (yield ready[2]):
yield
yield from dut.bm_drivers[2].nop()
yield
self.assertEqual((yield dut.dfi.phases[0].bank), 2)
dut = MultiplexerDUT(phy_settings=dict(nphases=1))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_ras_trrd(self):
# Verify tRRD.
def main_generator(dut):
yield from dut.bm_drivers[2].activate()
yield from dut.bm_drivers[3].activate()
ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
# Wait for activate
while not ((yield ready[2]) or (yield ready[3])):
yield
# Invalidate command that was ready
if (yield ready[2]):
yield from dut.bm_drivers[2].nop()
else:
yield from dut.bm_drivers[3].nop()
yield
# Wait for the second activate; start from 1 for the previous cycle
ras_time = 1
while not ((yield ready[2]) or (yield ready[3])):
ras_time += 1
yield
self.assertEqual(ras_time, 6)
dut = MultiplexerDUT(timing_settings=dict(tRRD=6))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_cas_tccd(self):
# Verify tCCD.
def main_generator(dut):
yield from dut.bm_drivers[2].read()
yield from dut.bm_drivers[3].read()
ready = {2: dut.bank_machines[2].cmd.ready, 3: dut.bank_machines[3].cmd.ready}
# Wait for activate
while not ((yield ready[2]) or (yield ready[3])):
yield
# Invalidate command that was ready
if (yield ready[2]):
yield from dut.bm_drivers[2].nop()
else:
yield from dut.bm_drivers[3].nop()
yield
# Wait for the second activate; start from 1 for the previous cycle
cas_time = 1
while not ((yield ready[2]) or (yield ready[3])):
cas_time += 1
yield
self.assertEqual(cas_time, 3)
dut = MultiplexerDUT(timing_settings=dict(tCCD=3))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_fsm_anti_starvation(self):
# Check that anti-starvation works according to controller settings.
def main_generator(dut):
yield from dut.bm_drivers[2].read()
yield from dut.bm_drivers[3].write()
# Go to WRITE
# anti starvation does not work for 1st read, as read_time_en already starts as 1
# READ -> RTW -> WRITE
while (yield from dut.fsm_state()) != "WRITE":
yield
# wait for write anti starvation
for _ in range(dut.settings.write_time):
self.assertEqual((yield from dut.fsm_state()), "WRITE")
yield
self.assertEqual((yield from dut.fsm_state()), "WTR")
# WRITE -> WTR -> READ
while (yield from dut.fsm_state()) != "READ":
yield
# Wait for read anti starvation
for _ in range(dut.settings.read_time):
self.assertEqual((yield from dut.fsm_state()), "READ")
yield
self.assertEqual((yield from dut.fsm_state()), "RTW")
dut = MultiplexerDUT()
generators = [
main_generator(dut),
timeout_generator(100),
]
run_simulation(dut, generators)
def test_write_datapath(self):
# Verify that data is transmitted from native interface to DFI.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
# 16bits * 2 (DDR) * 1 (phases)
yield dut.interface.wdata.eq(0xbaadf00d)
yield dut.interface.wdata_we.eq(0xf)
while not (yield dut.bank_machines[2].cmd.ready):
yield
yield
self.assertEqual((yield dut.dfi.phases[0].wrdata), 0xbaadf00d)
self.assertEqual((yield dut.dfi.phases[0].wrdata_en), 1)
self.assertEqual((yield dut.dfi.phases[0].address), 2)
self.assertEqual((yield dut.dfi.phases[0].bank), 2)
dut = MultiplexerDUT(phy_settings=dict(nphases=1))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_read_datapath(self):
# Verify that data is transmitted from DFI to native interface.
def main_generator(dut):
yield from dut.bm_drivers[2].write()
# 16bits * 2 (DDR) * 1 (phases)
yield dut.dfi.phases[0].rddata.eq(0xbaadf00d)
yield dut.dfi.phases[0].rddata_en.eq(1)
yield
while not (yield dut.bank_machines[2].cmd.ready):
yield
yield
self.assertEqual((yield dut.interface.rdata), 0xbaadf00d)
self.assertEqual((yield dut.interface.wdata_we), 0)
self.assertEqual((yield dut.dfi.phases[0].address), 2)
self.assertEqual((yield dut.dfi.phases[0].bank), 2)
dut = MultiplexerDUT(phy_settings=dict(nphases=1))
generators = [
main_generator(dut),
timeout_generator(50),
]
run_simulation(dut, generators)
def test_refresh_requires_gnt(self):
# After refresher command request, multiplexer waits for permission from all bank machines.
def main_generator(dut):
def assert_dfi_cmd(cas, ras, we):
p = dut.dfi.phases[0]
cas_n, ras_n, we_n = (yield p.cas_n), (yield p.ras_n), (yield p.we_n)
self.assertEqual((cas_n, ras_n, we_n), (1 - cas, 1 - ras, 1 - we))
for bm in dut.bank_machines:
self.assertEqual((yield bm.refresh_req), 0)
yield from dut.refresh_driver.refresh()
yield
# Bank machines get the request
for bm in dut.bank_machines:
self.assertEqual((yield bm.refresh_req), 1)
# No command yet
yield from assert_dfi_cmd(cas=0, ras=0, we=0)
# Grant permission for refresh
prng = random.Random(42)
delays = [prng.randrange(100) for _ in dut.bank_machines]
for t in range(max(delays) + 1):
# Grant permission
for delay, bm in zip(delays, dut.bank_machines):
if delay == t:
yield bm.refresh_gnt.eq(1)
yield
# Make sure thare is no command yet
yield from assert_dfi_cmd(cas=0, ras=0, we=0)
yield
yield
# Refresh command
yield from assert_dfi_cmd(cas=1, ras=1, we=0)
dut = MultiplexerDUT()
run_simulation(dut, main_generator(dut))
def test_requests_from_multiple_bankmachines(self):
# Check complex communication scenario with requests from multiple bank machines
# The communication is greatly simplified - data path is completely ignored, no responses
# from PHY are simulated. Each bank machine performs a sequence of requests, bank machines
# are ordered randomly and the DFI command data is checked to verify if all the commands
# have been sent if correct per-bank order.
# Tequests sequence on given bank machines
bm_sequences = {
0: "awwwwwwp",
1: "arrrrrrp",
2: "arwrwrwp",
3: "arrrwwwp",
4: "awparpawp",
5: "awwparrrrp",
}
# convert to lists to use .pop()
bm_sequences = {bm_num: list(seq) for bm_num, seq in bm_sequences.items()}
def main_generator(bank_machines, drivers):
# work on a copy
bm_seq = copy.deepcopy(bm_sequences)
def non_empty():
return list(filter(lambda n: len(bm_seq[n]) > 0, bm_seq.keys()))
# Artificially perform the work of LiteDRAMCrossbar by always picking only one request
prng = random.Random(42)
while len(non_empty()) > 0:
# Pick random bank machine
bm_num = prng.choice(non_empty())
# Set given request
request_char = bm_seq[bm_num].pop(0)
yield from drivers[bm_num].request(request_char)
yield
# Wait for ready
while not (yield bank_machines[bm_num].cmd.ready):
yield
# Disable it
yield from drivers[bm_num].nop()
for _ in range(16):
yield
# Gather data on DFI
DFISnapshot = namedtuple("DFICapture",
["cmd", "bank", "address", "wrdata_en", "rddata_en"])
dfi_snapshots = []
@passive
def dfi_monitor(dfi):
while True:
# Capture current state of DFI lines
phases = []
for i, p in enumerate(dfi.phases):
# Transform cas/ras/we to command name
cas_n, ras_n, we_n = (yield p.cas_n), (yield p.ras_n), (yield p.we_n)
captured = {"cmd": dfi_cmd_to_char(cas_n, ras_n, we_n)}
# Capture rest of fields
for field in DFISnapshot._fields:
if field != "cmd":
captured[field] = (yield getattr(p, field))
phases.append(DFISnapshot(**captured))
dfi_snapshots.append(phases)
yield
dut = MultiplexerDUT()
generators = [
main_generator(dut.bank_machines, dut.bm_drivers),
dfi_monitor(dut.dfi),
timeout_generator(200),
]
run_simulation(dut, generators)
# Check captured DFI data with the description
for snap in dfi_snapshots:
for i, phase_snap in enumerate(snap):
if phase_snap.cmd == "_":
continue
# Distinguish bank machines by the bank number
bank = phase_snap.bank
# Find next command for the given bank
cmd = bm_sequences[bank].pop(0)
# Check if the captured data is correct
self.assertEqual(phase_snap.cmd, cmd)
if cmd in ["w", "r"]:
# Addresses are artificially forced to bank numbers in drivers
self.assertEqual(phase_snap.address, bank)
if cmd == "w":
self.assertEqual(phase_snap.wrdata_en, 1)
if cmd == "r":
self.assertEqual(phase_snap.rddata_en, 1)
| [
"litex.gen.sim.run_simulation"
] | [((3708, 3856), 'litedram.phy.dfi.Interface', 'dfi.Interface', ([], {'addressbits': 'abits', 'bankbits': 'babits', 'nranks': 'settings.phy.nranks', 'databits': 'settings.phy.dfi_databits', 'nphases': 'settings.phy.nphases'}), '(addressbits=abits, bankbits=babits, nranks=settings.phy.\n nranks, databits=settings.phy.dfi_databits, nphases=settings.phy.nphases)\n', (3721, 3856), False, 'from litedram.phy import dfi\n'), ((4164, 4252), 'litedram.core.multiplexer.Multiplexer', 'Multiplexer', (['settings', 'self.bank_machines', 'self.refresher', 'self.dfi', 'self.interface'], {}), '(settings, self.bank_machines, self.refresher, self.dfi, self.\n interface)\n', (4175, 4252), False, 'from litedram.core.multiplexer import Multiplexer\n'), ((4450, 4493), 'test.common.CmdRequestRWDriver', 'CmdRequestRWDriver', (['self.refresher.cmd'], {'i': '(1)'}), '(self.refresher.cmd, i=1)\n', (4468, 4493), False, 'from test.common import timeout_generator, CmdRequestRWDriver\n'), ((7207, 7238), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 'generators'], {}), '(dut, generators)\n', (7221, 7238), False, 'from litex.gen.sim import run_simulation\n'), ((8189, 8220), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 'generators'], {}), '(dut, generators)\n', (8203, 8220), False, 'from litex.gen.sim import run_simulation\n'), ((9167, 9198), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 'generators'], {}), '(dut, generators)\n', (9181, 9198), False, 'from litex.gen.sim import run_simulation\n'), ((10184, 10215), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 'generators'], {}), '(dut, generators)\n', (10198, 10215), False, 'from litex.gen.sim import run_simulation\n'), ((11265, 11296), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 'generators'], {}), '(dut, generators)\n', (11279, 11296), False, 'from litex.gen.sim import run_simulation\n'), ((12338, 12369), 'litex.gen.sim.run_simulation', 'run_simulation', (['dut', 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CmdRequestRWDriver\n'), ((15434, 15455), 'test.common.timeout_generator', 'timeout_generator', (['(50)'], {}), '(50)\n', (15451, 15455), False, 'from test.common import timeout_generator, CmdRequestRWDriver\n'), ((16404, 16421), 'random.Random', 'random.Random', (['(42)'], {}), '(42)\n', (16417, 16421), False, 'import random\n'), ((18037, 18064), 'copy.deepcopy', 'copy.deepcopy', (['bm_sequences'], {}), '(bm_sequences)\n', (18050, 18064), False, 'import copy\n'), ((18295, 18312), 'random.Random', 'random.Random', (['(42)'], {}), '(42)\n', (18308, 18312), False, 'import random\n'), ((20010, 20032), 'test.common.timeout_generator', 'timeout_generator', (['(200)'], {}), '(200)\n', (20027, 20032), False, 'from test.common import timeout_generator, CmdRequestRWDriver\n')] |
from migen import *
from litex.soc.interconnect.stream import SyncFIFO
class FIFOSyncMacro(Module, Record):
"""FIFOSyncMacro
Provides an equivalent of Xilinx' FIFO_SYNC_MACRO which is a unimacro dedicated for 7 series
FPGAs and Zynq-7000 SoC.
Detailed informations can be found in official documentation:
https://docs.xilinx.com/r/2021.2-English/ug953-vivado-7series-libraries/FIFO_SYNC_MACRO
"""
def __init__(self, fifo_size="18Kb", data_width=32, almost_empty_offset=0, almost_full_offset=0, do_reg=0, toolchain="vivado"):
assert data_width <= 72
assert fifo_size in ["18Kb", "36Kb"]
if do_reg and toolchain != "vivado":
raise NotImplementedError("FIFOSyncMacro: DO_REG==1 is supported only for Vivado toolchain")
fifo_sync_macro_layout = [
("rd_d", data_width),
("almostfull", 1),
("almostempty", 1),
("full", 1),
("empty", 1),
("rdcount", 13),
("rderr", 1),
("wrerr", 1),
("wrcount", 13),
("rden", 1),
("wr_d", data_width),
("wren", 1),
("reset", 1)
]
Record.__init__(self, fifo_sync_macro_layout)
if toolchain == "vivado":
self.specials += Instance("FIFO_SYNC_MACRO",
p_DEVICE = "7SERIES",
p_FIFO_SIZE = fifo_size,
p_DATA_WIDTH = data_width,
p_ALMOST_EMPTY_OFFSET = almost_empty_offset,
p_ALMOST_FULL_OFFSET = almost_full_offset,
p_DO_REG = do_reg,
i_CLK = ClockSignal(),
i_RST = self.reset,
o_ALMOSTFULL = self.almostfull,
o_ALMOSTEMPTY = self.almostempty,
o_FULL = self.full,
o_EMPTY = self.empty,
i_WREN = self.wren,
i_DI = self.wr_d,
i_RDEN = self.rden,
o_DO = self.rd_d,
o_RDCOUNT = self.rdcount,
o_RDERR = self.rderr,
o_WRCOUNT = self.wrcount,
o_WRERR = self.wrerr,
)
else:
level = Signal(14)
# FIFO size is adjusted to only match configurations supported by FIFO_SYNC_MACRO
if fifo_size == "18Kb":
fifo_size = 16
elif fifo_size == "36Kb":
fifo_size = 32
else:
raise ValueError("FIFOSyncMacro can only be configured to 18Kb or 36Kb of memory")
if data_width in range(1, 5):
macro_data_width = 4
elif data_width in range(5, 10):
macro_data_width = 8
elif data_width in range(10, 19):
macro_data_width = 16
elif data_width in range(19, 37):
macro_data_width = 32
elif data_width in range(37, 73):
if fifo_size == 36:
macro_data_width = 64
else:
raise ValueError("FIFOSyncMacro accepts data width up to 72 bits only for 36Kb FIFO size.")
else:
raise ValueError("FIFOSyncMacro only accepts data width up to 72 bits.")
self.fifo_depth = fifo_depth = (int)(fifo_size * 1024 / macro_data_width)
self.submodules.fifo = fifo = ResetInserter()(SyncFIFO([("data", data_width)], fifo_depth))
self.comb += [
fifo.reset.eq(self.reset),
level.eq(fifo.level),
# connect port signals to internal fifo
# sink
fifo.sink.data.eq(self.wr_d),
fifo.sink.valid.eq(self.wren),
# source
self.rd_d.eq(fifo.source.data),
fifo.source.ready.eq(self.rden),
self.wrerr.eq(~fifo.sink.ready & self.wren),
self.rderr.eq(fifo.source.ready & self.rden),
If(level == 0,
self.empty.eq(1)
).Else(
self.empty.eq(0)
),
If(level == fifo_depth,
self.full.eq(1)
).Else(
self.full.eq(0)
),
]
self.sync += [
# reset only these two since other signals are dependent on fifo state
If(self.reset,
self.rdcount.eq(0),
self.wrcount.eq(0),
),
# wrcount and rdcount are counters of respectively written and read words
If(fifo.sink.ready & fifo.sink.valid,
If(self.wrcount == (fifo_depth - 1),
self.wrcount.eq(0)
).Else(
self.wrcount.eq(self.wrcount + 1),
)
),
If(fifo.source.ready & fifo.source.valid,
If(self.rdcount == (fifo_depth - 1),
self.rdcount.eq(0)
).Else(
self.rdcount.eq(self.rdcount + 1),
)
),
# assert almostempty when fifo level is lower than almost_empty_offset
If((level <= almost_empty_offset),
self.almostempty.eq(1)
).Else(
self.almostempty.eq(0)
),
# assert almostfull when fifo level is higher than almost_full_offset
If((level >= (fifo_depth - almost_full_offset)),
self.almostfull.eq(1)
).Else(
self.almostfull.eq(0)
),
]
| [
"litex.soc.interconnect.stream.SyncFIFO"
] | [((3611, 3655), 'litex.soc.interconnect.stream.SyncFIFO', 'SyncFIFO', (["[('data', data_width)]", 'fifo_depth'], {}), "([('data', data_width)], fifo_depth)\n", (3619, 3655), False, 'from litex.soc.interconnect.stream import SyncFIFO\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Board diagram/pinout:
# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-specifications.jpg
# http://www.fabienm.eu/flf/wp-content/uploads/2021/08/Tang-Nano-4K-GW1NSR-4C-FPGA-board-pinout-diagram.jpg
from migen import *
from litex.build.generic_platform import *
from litex.build.gowin.platform import GowinPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk27", 0, Pins("45"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("10"), IOStandard("LVCMOS33")),
# Buttons.
("user_btn", 0, Pins("14"), IOStandard("LVCMOS18")),
("user_btn", 1, Pins("15"), IOStandard("LVCMOS18")),
# Serial (FIXME: For tests, change or remove.)
("serial", 0,
Subsignal("rx", Pins("44")), # CAM_SCL
Subsignal("tx", Pins("46")), # CAM_SDA
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("2"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("1"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("47"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("48"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("8"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("9"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("2")),
Subsignal("clk", Pins("1")),
Subsignal("dq", Pins("48 47 8 9")),
IOStandard("LVCMOS33")
),
# HyperRAM (embedded in SIP, requires specific IO naming).
("O_hpram_ck", 0, Pins(1)),
("O_hpram_ck_n", 0, Pins(1)),
("O_hpram_cs_n", 0, Pins(1)),
("O_hpram_reset_n", 0, Pins(1)),
("IO_hpram_dq", 0, Pins(8)),
("IO_hpram_rwds", 0, Pins(1)),
# HDMI.
("hdmi", 0,
Subsignal("clk_p", Pins("28")),
Subsignal("clk_n", Pins("27")),
Subsignal("data0_p", Pins("30")),
Subsignal("data0_n", Pins("29")),
Subsignal("data1_p", Pins("32")),
Subsignal("data1_n", Pins("31")),
Subsignal("data2_p", Pins("35")),
Subsignal("data2_n", Pins("34")),
Misc("PULL_MODE=NONE"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
["P6", "30 29 28 27 23 22 21 20 19 18 17 13 16 9 8 33 2 - - - - 15"],
["P7", "31 32 34 35 10 39 40 41 42 43 47 48 1 46 44 - - 6 3 4 7 14"],
]
# Platform -----------------------------------------------------------------------------------------
class Platform(GowinPlatform):
default_clk_name = "clk27"
default_clk_period = 1e9/27e6
def __init__(self):
GowinPlatform.__init__(self, "GW1NSR-LV4CQN48PC7/I6", _io, _connectors, toolchain="gowin", devicename="GW1NSR-4C")
self.toolchain.options["use_mode_as_gpio"] = 1
self.toolchain.options["use_mspi_as_gpio"] = 1
self.toolchain.options["use_done_as_gpio"] = 1
def create_programmer(self):
return OpenFPGALoader("tangnano4k")
def do_finalize(self, fragment):
GowinPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk27", loose=True), 1e9/27e6)
| [
"litex.build.gowin.platform.GowinPlatform.__init__",
"litex.build.openfpgaloader.OpenFPGALoader",
"litex.build.gowin.platform.GowinPlatform.do_finalize"
] | [((2907, 3025), 'litex.build.gowin.platform.GowinPlatform.__init__', 'GowinPlatform.__init__', (['self', '"""GW1NSR-LV4CQN48PC7/I6"""', '_io', '_connectors'], {'toolchain': '"""gowin"""', 'devicename': '"""GW1NSR-4C"""'}), "(self, 'GW1NSR-LV4CQN48PC7/I6', _io, _connectors,\n toolchain='gowin', devicename='GW1NSR-4C')\n", (2929, 3025), False, 'from litex.build.gowin.platform import GowinPlatform\n'), ((3236, 3264), 'litex.build.openfpgaloader.OpenFPGALoader', 'OpenFPGALoader', (['"""tangnano4k"""'], {}), "('tangnano4k')\n", (3250, 3264), False, 'from litex.build.openfpgaloader import OpenFPGALoader\n'), ((3311, 3352), 'litex.build.gowin.platform.GowinPlatform.do_finalize', 'GowinPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3336, 3352), False, 'from litex.build.gowin.platform import GowinPlatform\n')] |
#!/usr/bin/env python3
import argparse
from migen import *
from litex.build.generic_platform import IOStandard, Subsignal, Pins
from litex_boards.platforms import colorlight_5a_75b
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
clk25 = platform.request("clk25")
platform.add_period_constraint(clk25, 1e9/25e6)
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
class BaseSoC(SoCCore):
def __init__(self, revision, cpu, freq):
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = freq
# SoC with CPU
SoCCore.__init__(
self,
platform,
cpu_type = cpu,
clk_freq = sys_clk_freq,
ident = "LiteX SoC with PLL on Colorlight 5A-75B",
ident_version = True,
integrated_rom_size = 0x8000,
integrated_main_ram_size = 0x4000,
uart_name = "serial"
)
# Clock Reset Generation and PLL
self.submodules.crg = _CRG(platform, sys_clk_freq)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC with PLL on Colorlight 5A-75B")
parser.add_argument("--revision", action="store", default="7.0", help="Colorlight 5A-75B board revision (6.1 / 7.0)")
parser.add_argument("--cpu", action="store", default="vexriscv", help="SoC CPU (vexriscv / picorv32)")
parser.add_argument("--freq", action="store", type=int, default=50e6, help="System clock frequency (Hz)")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
args = parser.parse_args()
soc = BaseSoC(
revision = args.revision,
cpu = args.cpu,
freq = args.freq
)
builder = Builder(soc, **builder_argdict(args))
builder.build(**trellis_argdict(args), run=True)
if __name__ == "__main__": main()
| [
"litex.build.lattice.trellis.trellis_args",
"litex.build.lattice.trellis.trellis_argdict"
] | [((1490, 1568), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC with PLL on Colorlight 5A-75B"""'}), "(description='LiteX SoC with PLL on Colorlight 5A-75B')\n", (1513, 1568), False, 'import argparse\n'), ((1963, 1983), 'litex.build.lattice.trellis.trellis_args', 'trellis_args', (['parser'], {}), '(parser)\n', (1975, 1983), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n'), ((831, 867), 'litex_boards.platforms.colorlight_5a_75b.Platform', 'colorlight_5a_75b.Platform', (['revision'], {}), '(revision)\n', (857, 867), False, 'from litex_boards.platforms import colorlight_5a_75b\n'), ((2210, 2231), 'litex.build.lattice.trellis.trellis_argdict', 'trellis_argdict', (['args'], {}), '(args)\n', (2225, 2231), False, 'from litex.build.lattice.trellis import trellis_args, trellis_argdict\n')] |
# This file is Copyright (c) 2020 <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.stream import Endpoint
from migen.genlib.cdc import MultiReg
from rtl.edge_detect import EdgeDetect
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litex.soc.interconnect.stream import Endpoint, EndpointDescription, AsyncFIFO
from litex.soc.interconnect.stream import *
@ResetInserter()
class StreamPrepend(Module, AutoCSR):
def __init__(self):
self.sink = sink = Endpoint([("data", 32)])
self.source = source = Endpoint([("data", 32)])
self.length = CSRStorage(8)
delay_count = Signal(8)
_valid = Signal()
self.sync += _valid.eq(sink.valid)
self.submodules.fsm = fsm = FSM(reset_state='PASS')
fsm.act('PASS',
sink.connect(source),
If(~sink.valid,
If(self.length.storage > 0,
NextState('DELAY'),
NextValue(delay_count, self.length.storage)
)
)
)
fsm.act('DELAY',
sink.connect(source, omit=['first','ready']),
If(delay_count == 0,
NextState('PASS'),
).Elif(sink.valid & source.ready,
NextValue(delay_count, delay_count - 1),
),
)
@ResetInserter()
class StreamAppend(Module, AutoCSR):
def __init__(self):
self.sink = sink = Endpoint([("data", 32)])
self.source = source = Endpoint([("data", 32)])
self.length = CSRStorage(8)
delay_count = Signal(8)
_valid = Signal()
self.sync += _valid.eq(sink.valid)
self.submodules.fsm = fsm = FSM(reset_state='PASS')
fsm.act('PASS',
sink.connect(source,omit=['last','ready']),
If(sink.last,
If(self.length.storage > 0,
NextState('DELAY'),
NextValue(delay_count, self.length.storage)
).Else(
source.last.eq(1),
)
).Else(
sink.ready.eq(source.ready)
)
)
fsm.act('DELAY',
sink.connect(source, omit=['last','ready']),
If(delay_count == 0,
sink.ready.eq(source.ready),
source.last.eq(1),
NextState('PASS'),
).Elif(sink.valid & source.ready,
NextValue(delay_count, delay_count - 1),
),
)
## Unit tests
import unittest
from litex.soc.interconnect.stream_sim import PacketStreamer, PacketLogger, Packet, Randomizer
from litex.soc.interconnect.stream import Pipeline
class TestStream(unittest.TestCase):
def testPrepend(self):
data = [i for i in range(2,10)]
length = 5
def generator(dut):
d = Packet(data)
yield from dut.prepend.length.write(length-1)
yield from dut.streamer.send_blocking(d)
def checker(dut):
yield from dut.logger.receive()
assert(dut.logger.packet == ([data[0]]*(length) + data))
class DUT(Module):
def __init__(self):
self.submodules.prepend = StreamPrepend()
self.submodules.streamer = PacketStreamer([("data", 32)])
self.submodules.logger = PacketLogger([("data", 32)])
self.submodules.pipeline = Pipeline(
self.streamer,
self.prepend,
self.logger
)
dut = DUT()
generators = {
"sys" : [generator(dut),
checker(dut),
dut.streamer.generator(),
dut.logger.generator(),
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name='test.vcd')
def testAppend(self):
data = [i for i in range(32,38)]
length = 3
def generator(dut):
d = Packet(data)
yield from dut.append.length.write(length-1)
yield from dut.streamer.send_blocking(d)
def checker(dut):
yield from dut.logger.receive()
assert(dut.logger.packet == (data + [data[-1]]*(length)))
class DUT(Module):
def __init__(self):
self.submodules.append = StreamAppend()
self.submodules.streamer = PacketStreamer([("data", 32)])
self.submodules.logger = PacketLogger([("data", 32)])
self.submodules.pipeline = Pipeline(
self.streamer,
self.append,
self.logger
)
dut = DUT()
generators = {
"sys" : [generator(dut),
checker(dut),
dut.streamer.generator(),
dut.logger.generator(),
]
}
clocks = {"sys": 10}
run_simulation(dut, generators, clocks, vcd_name='test.vcd')
| [
"litex.soc.interconnect.stream.Pipeline",
"litex.soc.interconnect.stream_sim.Packet",
"litex.soc.interconnect.stream_sim.PacketStreamer",
"litex.soc.interconnect.stream_sim.PacketLogger",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.stream.Endpoint"
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# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import Pins, IOStandard, Subsignal
from litex.build.xilinx import XilinxPlatform
from litex.build.openfpgaloader import OpenFPGALoader
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0, Pins("H16"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
("rgb_led", 0,
Subsignal("r", Pins("N15")),
Subsignal("g", Pins("G17")),
Subsignal("b", Pins("L15")),
IOStandard("LVCMOS33"),
),
("rgb_led", 1,
Subsignal("r", Pins("M15")),
Subsignal("g", Pins("L14")),
Subsignal("b", Pins("G14")),
IOStandard("LVCMOS33"),
),
# Switches
("user_sw", 0, Pins("M20"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("M19"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("D19"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("D20"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")),
# Serial (ust to make CI pass)
# Unfortunately the only USB UART is hard-wired to the ARM CPU
("serial", 0,
Subsignal("tx", Pins("Y18")),
Subsignal("rx", Pins("Y19")),
IOStandard("LVCMOS33"),
),
# SPI
("spi", 0,
Subsignal("clk", Pins("H15")),
Subsignal("cs_n", Pins("F16")),
Subsignal("mosi", Pins("T12")),
Subsignal("miso", Pins("W15")),
IOStandard("LVCMOS33"),
),
# I2C
("i2c", 0,
Subsignal("scl", Pins("P16")),
Subsignal("sda", Pins("P15")),
IOStandard("LVCMOS33"),
),
# Audio
("audio", 0,
Subsignal("pwm", Pins("R18")), # FIXME
Subsignal("sd", Pins("T17")), # FIXME
IOStandard("LVCMOS33"),
),
# HDMI In
("hdmi_in", 0,
Subsignal("clk_p", Pins("H17"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")),
Subsignal("hpd_en", Pins("T19"), IOStandard("LVCMOS33")),
Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")),
),
# HDMI Out
("hdmi_out", 0,
Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")),
Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")),
Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")),
Subsignal("hdp", Pins("R19"), IOStandard("LVCMOS33")),
),
# PS7
("ps7_clk", 0, Pins(1)),
("ps7_porb", 0, Pins(1)),
("ps7_srstb", 0, Pins(1)),
("ps7_mio", 0, Pins(54)),
("ps7_ddram", 0,
Subsignal("addr", Pins(15)),
Subsignal("ba", Pins(3)),
Subsignal("cas_n", Pins(1)),
Subsignal("ck_n", Pins(1)),
Subsignal("ck_p", Pins(1)),
Subsignal("cke", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("dm", Pins(4)),
Subsignal("dq", Pins(32)),
Subsignal("dqs_n", Pins(4)),
Subsignal("dqs_p", Pins(4)),
Subsignal("odt", Pins(1)),
Subsignal("ras_n", Pins(1)),
Subsignal("reset_n", Pins(1)),
Subsignal("we_n", Pins(1)),
Subsignal("vrn", Pins(1)),
Subsignal("vrp", Pins(1)),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
# access a pin with `pmoda:N`, where N is:
# N: 0 1 2 3 4 5 6 7
# Pin: 1 2 3 4 7 8 9 10
# Bank 13
("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"),
("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"),
("ck_io", {
"ck_ioa" : "Y13",
# Outer Digital Header
"ck_io0" : "T14",
"ck_io1" : "U12",
"ck_io2" : "U13",
"ck_io3" : "V13",
"ck_io4" : "V15",
"ck_io5" : "T15",
"ck_io6" : "R16",
"ck_io7" : "U17",
"ck_io8" : "V17",
"ck_io9" : "V18",
"ck_io10" : "T16",
"ck_io11" : "R17",
"ck_io12" : "P18",
"ck_io13" : "N17",
# Inner Digital Header
# Only for Arty Z7 20
"ck_io26" : "U5",
"ck_io27" : "V5",
"ck_io28" : "V6",
"ck_io29" : "U7",
"ck_io30" : "V7",
"ck_io31" : "U8",
"ck_io32" : "V8",
"ck_io33" : "V10",
"ck_io34" : "W10",
"ck_io35" : "W6",
"ck_io36" : "Y6",
"ck_io37" : "Y7",
"ck_io38" : "W8",
"ck_io39" : "Y8",
"ck_io40" : "W9",
"ck_io41" : "Y9",
# Outer Analog Header as Digital IO
# Only for Arty Z7 20
"ck_a0" : "Y11",
"ck_a1" : "Y12",
"ck_a2" : "W11",
"ck_a3" : "V11",
"ck_a4" : "T5",
"ck_a5" : "U10",
# Inner Analog Header as Digital IO
"ck_a6" : "F19",
"ck_a7" : "F20",
"ck_a8" : "C20",
"ck_a9" : "B20",
"ck_a10" : "B19",
"ck_a11" : "A20",
}),
("XADC", {
# Outer Analog Header
"vaux1_p" : "E17",
"vaux1_n" : "B18",
"vaux9_p" : "E18",
"vaux9_n" : "E19",
"vaux6_p" : "K14",
"vaux6_n" : "J14",
"vaux15_p" : "K16",
"vaux15_n" : "J16",
"vaux5_p" : "J20",
"vaux5_n" : "H20",
"vaux13_p" : "G19",
"vaux13_n" : "G20",
# Inner Analog Header
"vaux12_p" : "F19",
"vaux12_n" : "F20",
"vaux0_p" : "C20",
"vaux0_n" : "B20",
"vaux8_p" : "B19",
"vaux8_n" : "A19",
})
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self, variant="z7-20", toolchain="vivado"):
device = {
"z7-10": "xc7z010clg400-1",
"z7-20": "xc7z020clg400-1"
}[variant]
self.board = {
"z7-10": "arty_z7_10",
"z7-20": "arty_z7_20"
}[variant]
XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
def create_programmer(self):
return OpenFPGALoader(self.board)
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e6/125e6)
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"litex.build.generic_platform.Pins",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
#
# http://trenz.org/max1000-info
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk12", 0, Pins("H6"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("A8"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("A9"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("A11"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("A10"), IOStandard("3.3-V LVTTL")),
("user_led", 4, Pins("B10"), IOStandard("3.3-V LVTTL")),
("user_led", 5, Pins("C9"), IOStandard("3.3-V LVTTL")),
("user_led", 6, Pins("C10"), IOStandard("3.3-V LVTTL")),
("user_led", 7, Pins("D8"), IOStandard("3.3-V LVTTL")),
# Buttons
("user_btn", 0, Pins("E6"), IOStandard("3.3-V LVTTL")),
("user_btn", 1, Pins("E7"), IOStandard("3.3-V LVTTL")), # nConfig.
# Serial
("serial", 0,
Subsignal("tx", Pins("B4"), IOStandard("3.3-V LVTTL")),
Subsignal("rx", Pins("A4"), IOStandard("3.3-V LVTTL"))
),
# SPI Flash
("spiflash4x", 0,
Subsignal("cs_n", Pins("B3")),
Subsignal("clk", Pins("A3")),
Subsignal("dq", Pins("A2", "B2", "B9", "C4")),
IOStandard("3.3-V LVTTL")
),
("spiflash", 0,
Subsignal("cs_n", Pins("B3")),
Subsignal("clk", Pins("A3")),
Subsignal("mosi", Pins("A2")),
Subsignal("miso", Pins("B2")),
Subsignal("wp", Pins("B9")),
Subsignal("hold", Pins("C4")),
IOStandard("3.3-V LVTTL"),
),
# SDRAM
("sdram_clock", 0, Pins("M9"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"K6 M5 N5 J8 N10 M11 N9 L10",
"M13 N8 N4 M10")),
Subsignal("ba", Pins("N6 K8")),
Subsignal("cs_n", Pins("M4")),
Subsignal("cke", Pins("M8")),
Subsignal("ras_n", Pins("M7")),
Subsignal("cas_n", Pins("N7")),
Subsignal("we_n", Pins("K7")),
Subsignal("dq", Pins(
"D11 G10 F10 F9 E10 D9 G9 F8",
"F13 E12 E13 D12 C12 B12 B13 A12")),
Subsignal("dm", Pins("E9 F12")),
IOStandard("3.3-V LVTTL")
),
# all IO not connected to peripherals mapped to MFIO
# <- LEDS -> <- PMOD -> <- D0..D14, D11R, D12R -> <- AIN0..AIN7 -> JE [C O I S i1 i2]sw
("bbio", 0, Pins("A8 A9 A11 A10 B10 C9 C10 D8 M3 L3 M2 M1 N3 N2 K2 K1 H8 K10 H5 H4 J1 J2 L12 J12 J13 K11 K12 J10 H10 H13 G12 B11 G13 E1 C2 C1 D1 E3 F1 E4 B1 E5 J6 J7 K5 L5 J5 L4 E6"),
IOStandard("3.3-V LVTTL")),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "10M08SAU169C8G", _io, toolchain=toolchain)
self.add_platform_command("set_global_assignment -name FAMILY \"MAX 10\"")
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF")
self.add_platform_command("set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE \"SINGLE IMAGE WITH ERAM\"")
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
# Generate PLL clock in STA
self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
# Calculates clock uncertainties
self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
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"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((3176, 3249), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""10M08SAU169C8G"""', '_io'], {'toolchain': 'toolchain'}), "(self, '10M08SAU169C8G', _io, toolchain=toolchain)\n", (3199, 3249), False, 'from litex.build.altera import AlteraPlatform\n'), ((3596, 3608), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (3606, 3608), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((3655, 3697), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3681, 3697), False, 'from litex.build.altera import AlteraPlatform\n')] |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
# IOs ------------------------------------------------------------------
_io = [
("clk50", 0, Pins("AF14"), IOStandard("3.3-V LVTTL")),
("serial", 0,
Subsignal("tx", Pins("AC18"), IOStandard("3.3-V LVTTL")), # JP1 GPIO[0]
Subsignal("rx", Pins("Y17"), IOStandard("3.3-V LVTTL")) # JP1 GPIO[1]
),
("sdram_clock", 0, Pins("AH12"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins("AK14 AH14 AG15 AE14 AB15 AC14 AD14 AF15 AH15 AG13 AG12 AH13 AJ14")),
Subsignal("ba", Pins("AF13 AJ12")),
Subsignal("cs_n", Pins("AG11")),
Subsignal("cke", Pins("AK13")),
Subsignal("ras_n", Pins("AE13")),
Subsignal("cas_n", Pins("AF11")),
Subsignal("we_n", Pins("AA13")),
Subsignal("dq", Pins("AK6 AJ7 AK7 AK8 AK9 AG10 AK11 AJ11 AH10 AJ10 AJ9 AH9 AH8 AH7 AJ6 AJ5")),
Subsignal("dm", Pins("AB13 AK12")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
AlteraPlatform.__init__(self, "5CSEMA5F31C6", _io)
| [
"litex.build.altera.AlteraPlatform.__init__"
] | [((1310, 1360), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""5CSEMA5F31C6"""', '_io'], {}), "(self, '5CSEMA5F31C6', _io)\n", (1333, 1360), False, 'from litex.build.altera import AlteraPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# iCEBreaker Bitsy FPGA:
# - 1BitSquared Store: https://1bitsquared.com/collections/fpga/products/icebreaker-bitsy
# - Design files: https://github.com/icebreaker-fpga/icebreaker
from litex.build.dfu import DFUProg
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
# IOs ----------------------------------------------------------------------------------------------
_io_v0 = [
# Clk / Rst
("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
# Leds
("user_led_n", 0, Pins("11"), IOStandard("LVCMOS33")),
("user_led_n", 1, Pins("37"), IOStandard("LVCMOS33")),
("user_ledr_n", 0, Pins("11"), IOStandard("LVCMOS33")), # Color-specific alias
("user_ledg_n", 0, Pins("37"), IOStandard("LVCMOS33")), # Color-specific alias
# Button
("user_btn_n", 0, Pins("10"), IOStandard("LVCMOS33")),
# USB
("usb", 0,
Subsignal("d_p", Pins("43")),
Subsignal("d_n", Pins("42")),
Subsignal("pullup", Pins("38")),
IOStandard("LVCMOS33")
),
# Serial
("serial", 0,
Subsignal("rx", Pins("18")),
Subsignal("tx", Pins("19"), Misc("PULLUP")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("12"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("13"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("14 17 12 13"), IOStandard("LVCMOS33")),
),
]
_io_v1 = [
# Clk / Rst
("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
# Leds
("user_led_n", 0, Pins("25"), IOStandard("LVCMOS33")),
("user_led_n", 1, Pins( "6"), IOStandard("LVCMOS33")),
("user_ledr_n", 0, Pins("25"), IOStandard("LVCMOS33")), # Color-specific alias
("user_ledg_n", 0, Pins( "6"), IOStandard("LVCMOS33")), # Color-specific alias
# Button
("user_btn_n", 0, Pins( "2"), IOStandard("LVCMOS33")),
# USB
("usb", 0,
Subsignal("d_p", Pins("42")),
Subsignal("d_n", Pins("38")),
Subsignal("pullup", Pins("37")),
IOStandard("LVCMOS33")
),
# Serial
("serial", 0,
Subsignal("rx", Pins("47")),
Subsignal("tx", Pins("44"), Misc("PULLUP")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("17"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("14"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("18"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("19"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("16"), IOStandard("LVCMOS33")),
Subsignal("clk", Pins("15"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("14 17 18 19"), IOStandard("LVCMOS33")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors_v0 = [
]
_connectors_v1 = [
("PIN", "47 44 48 45 4 3 9 10 11 12 21 13 20 25 23 27 26 28 31 32 34 36 43 46"),
("PMOD1", "47 48 4 9 44 45 3 10"),
("PMOD2", "43 32 26 28 36 31 27 34"),
("PMOD3", "23 12 13 11 25 21 20 46")
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6
def __init__(self, revision="v1", toolchain="icestorm"):
assert revision in ["v0", "v1"]
io, connectors = {
"v0": (_io_v0, _connectors_v0),
"v1": (_io_v1, _connectors_v1),
}[revision]
LatticePlatform.__init__(self, "ice40-up5k-sg48", io, connectors, toolchain=toolchain)
def create_programmer(self):
return DFUProg(vid="1d50", pid="6146")
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk12", loose=True), 1e9/12e6)
| [
"litex.build.dfu.DFUProg",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((4289, 4380), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""ice40-up5k-sg48"""', 'io', 'connectors'], {'toolchain': 'toolchain'}), "(self, 'ice40-up5k-sg48', io, connectors, toolchain\n =toolchain)\n", (4313, 4380), False, 'from litex.build.lattice import LatticePlatform\n'), ((4425, 4456), 'litex.build.dfu.DFUProg', 'DFUProg', ([], {'vid': '"""1d50"""', 'pid': '"""6146"""'}), "(vid='1d50', pid='6146')\n", (4432, 4456), False, 'from litex.build.dfu import DFUProg\n'), ((4503, 4546), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4530, 4546), False, 'from litex.build.lattice import LatticePlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# Copyright (c) 2017 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from migen.genlib.cdc import AsyncResetSynchronizer
from litex.soc.interconnect import stream
# Altera Atlantic JTAG -----------------------------------------------------------------------------
class JTAGAtlantic(Module):
def __init__(self):
self.sink = sink = stream.Endpoint([("data", 8)])
self.source = source = stream.Endpoint([("data", 8)])
# # #
self.specials += Instance("alt_jtag_atlantic",
# Parameters
p_LOG2_RXFIFO_DEPTH = "5", # FIXME: expose?
p_LOG2_TXFIFO_DEPTH = "5", # FIXME: expose?
p_SLD_AUTO_INSTANCE_INDEX = "YES",
# Clk/Rst
i_clk = ClockSignal("sys"),
i_rst_n = ~ResetSignal("sys"),
# TX
i_r_dat = sink.data,
i_r_val = sink.valid,
o_r_ena = sink.ready,
# RX
o_t_dat = source.data,
i_t_dav = source.ready,
o_t_ena = source.valid,
)
# Xilinx JTAG --------------------------------------------------------------------------------------
class XilinxJTAG(Module):
def __init__(self, primitive, chain=1):
self.reset = Signal()
self.capture = Signal()
self.shift = Signal()
self.update = Signal()
self.tck = Signal()
self.tms = Signal()
self.tdi = Signal()
self.tdo = Signal()
# # #
self.specials += Instance(primitive,
p_JTAG_CHAIN = chain,
o_RESET = self.reset,
o_CAPTURE = self.capture,
o_SHIFT = self.shift,
o_UPDATE = self.update,
o_TCK = self.tck,
o_TMS = self.tms,
o_TDI = self.tdi,
i_TDO = self.tdo,
)
class S6JTAG(XilinxJTAG):
def __init__(self, *args, **kwargs):
XilinxJTAG.__init__(self, primitive="BSCAN_SPARTAN6", *args, **kwargs)
class S7JTAG(XilinxJTAG):
def __init__(self, *args, **kwargs):
XilinxJTAG.__init__(self, primitive="BSCANE2", *args, **kwargs)
class USJTAG(XilinxJTAG):
def __init__(self, *args, **kwargs):
XilinxJTAG.__init__(self, primitive="BSCANE2", *args, **kwargs)
# JTAG PHY -----------------------------------------------------------------------------------------
class JTAGPHY(Module):
def __init__(self, jtag=None, device=None, data_width=8, clock_domain="sys", chain=1):
"""JTAG PHY
Provides a simple JTAG to LiteX stream module to easily stream data to/from the FPGA
over JTAG.
Wire format: data_width + 2 bits, LSB first.
Host to Target:
- TX ready : bit 0
- RX data: : bit 1 to data_width
- RX valid : bit data_width + 1
Target to Host:
- RX ready : bit 0
- TX data : bit 1 to data_width
- TX valid : bit data_width + 1
"""
self.sink = sink = stream.Endpoint([("data", data_width)])
self.source = source = stream.Endpoint([("data", data_width)])
# # #
valid = Signal()
data = Signal(data_width)
count = Signal(max=data_width)
# JTAG TAP ---------------------------------------------------------------------------------
if jtag is None:
if device[:3] == "xc6":
jtag = S6JTAG(chain=chain)
elif device[:3] == "xc7":
jtag = S7JTAG(chain=chain)
elif device[:4] in ["xcku", "xcvu"]:
jtag = USJTAG(chain=chain)
else:
raise NotImplementedError
self.submodules.jtag = jtag
# JTAG clock domain ------------------------------------------------------------------------
self.clock_domains.cd_jtag = ClockDomain()
self.comb += ClockSignal("jtag").eq(jtag.tck)
self.specials += AsyncResetSynchronizer(self.cd_jtag, ResetSignal(clock_domain))
# JTAG clock domain crossing ---------------------------------------------------------------
if clock_domain != "jtag":
tx_cdc = stream.AsyncFIFO([("data", data_width)], 4)
tx_cdc = ClockDomainsRenamer({"write": clock_domain, "read": "jtag"})(tx_cdc)
rx_cdc = stream.AsyncFIFO([("data", data_width)], 4)
rx_cdc = ClockDomainsRenamer({"write": "jtag", "read": clock_domain})(rx_cdc)
self.submodules.tx_cdc = tx_cdc
self.submodules.rx_cdc = rx_cdc
self.comb += [
sink.connect(tx_cdc.sink),
rx_cdc.source.connect(source)
]
sink, source = tx_cdc.source, rx_cdc.sink
# JTAG Xfer FSM ----------------------------------------------------------------------------
fsm = FSM(reset_state="XFER-READY")
fsm = ClockDomainsRenamer("jtag")(fsm)
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.comb += fsm.reset.eq(jtag.reset | jtag.capture)
fsm.act("XFER-READY",
jtag.tdo.eq(source.ready),
If(jtag.shift,
sink.ready.eq(jtag.tdi),
NextValue(valid, sink.valid),
NextValue(data, sink.data),
NextValue(count, 0),
NextState("XFER-DATA")
)
)
fsm.act("XFER-DATA",
jtag.tdo.eq(data),
If(jtag.shift,
NextValue(count, count + 1),
NextValue(data, Cat(data[1:], jtag.tdi)),
If(count == (data_width - 1),
NextState("XFER-VALID")
)
)
)
fsm.act("XFER-VALID",
jtag.tdo.eq(valid),
If(jtag.shift,
source.valid.eq(jtag.tdi),
NextState("XFER-READY")
)
)
self.comb += source.data.eq(data)
| [
"litex.soc.interconnect.stream.Endpoint",
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((490, 520), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (505, 520), False, 'from litex.soc.interconnect import stream\n'), ((552, 582), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', 8)]"], {}), "([('data', 8)])\n", (567, 582), False, 'from litex.soc.interconnect import stream\n'), ((3154, 3193), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (3169, 3193), False, 'from litex.soc.interconnect import stream\n'), ((3225, 3264), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', data_width)]"], {}), "([('data', data_width)])\n", (3240, 3264), False, 'from litex.soc.interconnect import stream\n'), ((4313, 4356), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', data_width)]", '(4)'], {}), "([('data', data_width)], 4)\n", (4329, 4356), False, 'from litex.soc.interconnect import stream\n'), ((4468, 4511), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', data_width)]", '(4)'], {}), "([('data', data_width)], 4)\n", (4484, 4511), False, 'from litex.soc.interconnect import stream\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import math
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.cdc import MultiReg
from litex.soc.interconnect import stream
# Layout/Helpers -----------------------------------------------------------------------------------
def phy_description(dw):
payload_layout = [("data", dw)]
return stream.EndpointDescription(payload_layout)
def anti_starvation(module, timeout):
en = Signal()
max_time = Signal()
if timeout:
t = timeout - 1
time = Signal(max=t+1)
module.comb += max_time.eq(time == 0)
module.sync += If(~en,
time.eq(t)
).Elif(~max_time,
time.eq(time - 1)
)
else:
module.comb += max_time.eq(0)
return en, max_time
# FT245 Synchronous FIFO Mode ----------------------------------------------------------------------
class FT245PHYSynchronous(Module):
def __init__(self, pads, clk_freq,
fifo_depth = 8,
read_time = 128,
write_time = 128):
dw = len(pads.data)
# read fifo (FTDI --> SoC)
read_fifo = stream.AsyncFIFO(phy_description(dw), fifo_depth)
read_fifo = ClockDomainsRenamer({"write": "usb", "read": "sys"})(read_fifo)
read_buffer = stream.SyncFIFO(phy_description(dw), 4)
read_buffer = ClockDomainsRenamer("usb")(read_buffer)
self.comb += read_buffer.source.connect(read_fifo.sink)
self.submodules += read_fifo, read_buffer
# write fifo (SoC --> FTDI)
write_fifo = stream.AsyncFIFO(phy_description(dw), fifo_depth)
write_fifo = ClockDomainsRenamer({"write": "sys", "read": "usb"})(write_fifo)
self.submodules += write_fifo
# sink / source interfaces
self.sink = write_fifo.sink
self.source = read_fifo.source
# read / write arbitration
wants_write = Signal()
wants_read = Signal()
txe_n = Signal()
rxf_n = Signal()
self.comb += [
txe_n.eq(pads.txe_n),
rxf_n.eq(pads.rxf_n),
wants_write.eq(~txe_n & write_fifo.source.valid),
wants_read.eq(~rxf_n & read_fifo.sink.ready),
]
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
data_w_accepted = Signal(reset=1)
fsm = FSM(reset_state="READ")
self.submodules += ClockDomainsRenamer("usb")(fsm)
fsm.act("READ",
read_time_en.eq(1),
If(wants_write,
If(~wants_read | max_read_time,
NextState("RTW")
)
)
)
fsm.act("RTW",
NextState("WRITE")
)
fsm.act("WRITE",
write_time_en.eq(1),
If(wants_read,
If(~wants_write | max_write_time,
NextState("WTR")
)
),
write_fifo.source.ready.eq(wants_write & data_w_accepted)
)
fsm.act("WTR",
NextState("READ")
)
# databus tristate
data_w = Signal(dw)
data_r = Signal(dw)
data_oe = Signal()
self.specials += Tristate(pads.data, data_w, data_oe, data_r)
# read / write actions
pads.oe_n.reset = 1
pads.rd_n.reset = 1
pads.wr_n.reset = 1
self.sync.usb += [
If(fsm.ongoing("READ"),
data_oe.eq(0),
pads.oe_n.eq(0),
pads.rd_n.eq(~wants_read),
pads.wr_n.eq(1)
).Elif(fsm.ongoing("WRITE"),
data_oe.eq(1),
pads.oe_n.eq(1),
pads.rd_n.eq(1),
pads.wr_n.eq(~wants_write),
data_w_accepted.eq(~txe_n)
).Else(
data_oe.eq(1),
pads.oe_n.eq(~fsm.ongoing("WTR")),
pads.rd_n.eq(1),
pads.wr_n.eq(1)
),
read_buffer.sink.valid.eq(~pads.rd_n & ~rxf_n),
read_buffer.sink.data.eq(data_r),
If(~txe_n & data_w_accepted,
data_w.eq(write_fifo.source.data)
)
]
# FT245 Asynchronous FIFO Mode ---------------------------------------------------------------------
class FT245PHYAsynchronous(Module):
def __init__(self, pads, clk_freq,
fifo_depth = 8,
read_time = 128,
write_time = 128):
dw = len(pads.data)
self.clk_freq = clk_freq
# timings
tRD = self.ns(30) # RD# active pulse width (t4)
tRDDataSetup = self.ns(14) # RD# to DATA (t3)
tWRDataSetup = self.ns(5) # DATA to WR# active setup time (t8)
tWR = self.ns(30) # WR# active pulse width (t10)
tMultiReg = 2
# read fifo (FTDI --> SoC)
read_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
# write fifo (SoC --> FTDI)
write_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
self.submodules += read_fifo, write_fifo
# sink / source interfaces
self.sink = write_fifo.sink
self.source = read_fifo.source
# read / write arbitration
wants_write = Signal()
wants_read = Signal()
txe_n = Signal()
rxf_n = Signal()
self.specials += [
MultiReg(pads.txe_n, txe_n),
MultiReg(pads.rxf_n, rxf_n)
]
self.comb += [
wants_write.eq(~txe_n & write_fifo.source.valid),
wants_read.eq(~rxf_n & read_fifo.sink.ready),
]
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
fsm = FSM(reset_state="READ")
self.submodules += fsm
read_done = Signal()
write_done = Signal()
commuting = Signal()
fsm.act("READ",
read_time_en.eq(1),
If(wants_write & read_done,
If(~wants_read | max_read_time,
commuting.eq(1),
NextState("RTW")
)
)
)
fsm.act("RTW",
NextState("WRITE")
)
fsm.act("WRITE",
write_time_en.eq(1),
If(wants_read & write_done,
If(~wants_write | max_write_time,
commuting.eq(1),
NextState("WTR")
)
)
)
fsm.act("WTR",
NextState("READ")
)
# databus tristate
data_w = Signal(dw)
data_r_async = Signal(dw)
data_r = Signal(dw)
data_oe = Signal()
self.specials += [
Tristate(pads.data, data_w, data_oe, data_r_async),
MultiReg(data_r_async, data_r)
]
# read actions
pads.rd_n.reset = 1
read_fsm = FSM(reset_state="IDLE")
self.submodules += read_fsm
read_counter = Signal(8)
read_fsm.act("IDLE",
read_done.eq(1),
NextValue(read_counter, 0),
If(fsm.ongoing("READ") & wants_read,
If(~commuting,
NextState("PULSE_RD_N")
)
)
)
read_fsm.act("PULSE_RD_N",
pads.rd_n.eq(0),
NextValue(read_counter, read_counter + 1),
If(read_counter == max(tRD-1, tRDDataSetup + tMultiReg -1),
NextState("ACQUIRE_DATA")
)
)
read_fsm.act("ACQUIRE_DATA",
read_fifo.sink.valid.eq(1),
read_fifo.sink.data.eq(data_r),
NextState("WAIT_RXF_N")
)
read_fsm.act("WAIT_RXF_N",
If(rxf_n,
NextState("IDLE")
)
)
# write actions
pads.wr_n.reset = 1
write_fsm = FSM(reset_state="IDLE")
self.submodules += write_fsm
write_counter = Signal(8)
write_fsm.act("IDLE",
write_done.eq(1),
NextValue(write_counter, 0),
If(fsm.ongoing("WRITE") & wants_write,
If(~commuting,
NextState("SET_DATA")
)
)
)
write_fsm.act("SET_DATA",
data_oe.eq(1),
data_w.eq(write_fifo.source.data),
NextValue(write_counter, write_counter + 1),
If(write_counter == (tWRDataSetup-1),
NextValue(write_counter, 0),
NextState("PULSE_WR_N")
)
)
write_fsm.act("PULSE_WR_N",
data_oe.eq(1),
data_w.eq(write_fifo.source.data),
pads.wr_n.eq(0),
NextValue(write_counter, write_counter + 1),
If(write_counter == (tWR-1),
NextState("WAIT_TXE_N")
)
)
write_fsm.act("WAIT_TXE_N",
If(txe_n,
write_fifo.source.ready.eq(1),
NextState("IDLE")
)
)
def ns(self, t, margin=True):
clk_period_ns = 1e9/self.clk_freq
if margin:
t += clk_period_ns/2
return math.ceil(t/clk_period_ns)
# FT245 FIFO Mode PHY (Automatic Asynchronous/Synchronous selection) -------------------------------
def FT245PHY(pads, *args, **kwargs):
# autodetect PHY
if hasattr(pads, "clkout"):
return FT245PHYSynchronous(pads, *args, **kwargs)
else:
return FT245PHYAsynchronous(pads, *args, **kwargs)
| [
"litex.soc.interconnect.stream.EndpointDescription"
] | [((448, 490), 'litex.soc.interconnect.stream.EndpointDescription', 'stream.EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (474, 490), False, 'from litex.soc.interconnect import stream\n'), ((3462, 3506), 'migen.fhdl.specials.Tristate', 'Tristate', (['pads.data', 'data_w', 'data_oe', 'data_r'], {}), '(pads.data, data_w, data_oe, data_r)\n', (3470, 3506), False, 'from migen.fhdl.specials import Tristate\n'), ((9500, 9528), 'math.ceil', 'math.ceil', (['(t / clk_period_ns)'], {}), '(t / clk_period_ns)\n', (9509, 9528), False, 'import math\n'), ((5666, 5693), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pads.txe_n', 'txe_n'], {}), '(pads.txe_n, txe_n)\n', (5674, 5693), False, 'from migen.genlib.cdc import MultiReg\n'), ((5707, 5734), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pads.rxf_n', 'rxf_n'], {}), '(pads.rxf_n, rxf_n)\n', (5715, 5734), False, 'from migen.genlib.cdc import MultiReg\n'), ((7059, 7109), 'migen.fhdl.specials.Tristate', 'Tristate', (['pads.data', 'data_w', 'data_oe', 'data_r_async'], {}), '(pads.data, data_w, data_oe, data_r_async)\n', (7067, 7109), False, 'from migen.fhdl.specials import Tristate\n'), ((7123, 7153), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['data_r_async', 'data_r'], {}), '(data_r_async, data_r)\n', (7131, 7153), False, 'from migen.genlib.cdc import MultiReg\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Build/Use:
# The current support is sufficient to run LiteX BIOS on Cortex-A53 core #0:
# ./alinx_axu2cga.py --build --load
# LiteX BIOS can then be executed on hardware using JTAG with the following xsct script from:
# https://github.com/trabucayre/litex-template/
# make -f Makefile.axu2cga load will build everything and run xsct in the end.
#
# Relies on https://github.com/lucaceresoli/zynqmp-pmufw-builder to create a generic PMU firmware;
# first build will take a while because it includes a cross-toolchain.
import os
import argparse
from migen import *
from litex_boards.platforms import alinx_axu2cga
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.build.tools import write_to_file
from litex.soc.interconnect import axi
from litex.soc.interconnect import wishbone
from litex.soc.cores.clock import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, use_psu_clk=False):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
# # #
if use_psu_clk:
self.comb += [
ClockSignal("sys").eq(ClockSignal("ps")),
ResetSignal("sys").eq(ResetSignal("ps") | self.rst),
]
else:
# Clk
clk25 = platform.request("clk25")
# PLL
self.submodules.pll = pll = USMMCM(speedgrade=-1)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(clk25, 25e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
# Ignore sys_clk to pll.clkin path created by SoC's rst.
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(25e6), with_led_chaser=True, **kwargs):
platform = alinx_axu2cga.Platform()
if kwargs.get("cpu_type", None) == "zynqmp":
kwargs['integrated_sram_size'] = 0
kwargs['with_uart'] = False
self.mem_map = {
'csr': 0x8000_0000, # Zynq GP0 default
}
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Alinx AXU2CGA",
**kwargs)
# ZynqMP Integration ---------------------------------------------------------------------
if kwargs.get("cpu_type", None) == "zynqmp":
self.cpu.config.update(platform.psu_config)
# Connect AXI HPM0 LPD to the SoC
wb_lpd = wishbone.Interface()
self.submodules += axi.AXI2Wishbone(
axi = self.cpu.add_axi_gp_master(2, 32),
wishbone = wb_lpd,
base_address = self.mem_map['csr'])
self.add_wb_master(wb_lpd)
self.bus.add_region("sram", SoCRegion(
origin=self.cpu.mem_map["sram"],
size=1 * 1024 * 1024 * 1024) # DDR
)
self.bus.add_region("rom", SoCRegion(
origin=self.cpu.mem_map["rom"],
size=512 * 1024 * 1024 // 8,
linker=True)
)
self.constants['CONFIG_CLOCK_FREQUENCY'] = 1199880127
use_psu_clk = True
else:
use_psu_clk = False
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, use_psu_clk)
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
def finalize(self, *args, **kwargs):
super(BaseSoC, self).finalize(*args, **kwargs)
if self.cpu_type != "zynqmp":
return
libxil_path = os.path.join(self.builder.software_dir, 'libxil')
os.makedirs(os.path.realpath(libxil_path), exist_ok=True)
lib = os.path.join(libxil_path, 'embeddedsw')
if not os.path.exists(lib):
os.system("git clone --depth 1 https://github.com/Xilinx/embeddedsw {}".format(lib))
os.makedirs(os.path.realpath(self.builder.include_dir), exist_ok=True)
for header in [
'XilinxProcessorIPLib/drivers/uartps/src/xuartps_hw.h',
'lib/bsp/standalone/src/common/xil_types.h',
'lib/bsp/standalone/src/common/xil_assert.h',
'lib/bsp/standalone/src/common/xil_io.h',
'lib/bsp/standalone/src/common/xil_printf.h',
'lib/bsp/standalone/src/common/xstatus.h',
'lib/bsp/standalone/src/common/xdebug.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xpseudo_asm.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xreg_cortexa53.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_cache.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/xil_errata.h',
'lib/bsp/standalone/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h',
'lib/bsp/standalone/src/arm/common/xil_exception.h',
'lib/bsp/standalone/src/arm/common/gcc/xpseudo_asm_gcc.h',
]:
shutil.copy(os.path.join(lib, header), self.builder.include_dir)
write_to_file(os.path.join(self.builder.include_dir, 'bspconfig.h'), """
#ifndef BSPCONFIG_H
#define BSPCONFIG_H
#define EL3 1
#define EL1_NONSECURE 0
#endif
""")
write_to_file(os.path.join(self.builder.include_dir, 'xparameters.h'), '''
#ifndef XPARAMETERS_H
#define XPARAMETERS_H
#include "xparameters_ps.h"
#define STDIN_BASEADDRESS 0xFF010000
#define STDOUT_BASEADDRESS 0xFF010000
#define XPAR_PSU_DDR_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PSU_DDR_0_S_AXI_HIGHADDR 0x7FFFFFFF
#define XPAR_PSU_DDR_1_S_AXI_BASEADDR 0x800000000
#define XPAR_PSU_DDR_1_S_AXI_HIGHADDR 0x87FFFFFFF
#define XPAR_CPU_CORTEXA53_0_TIMESTAMP_CLK_FREQ 99999005
#endif
''')
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Alinx AXU2CGA")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream.")
parser.add_argument("--cable", default="ft232", help="JTAG interface.")
parser.add_argument("--sys-clk-freq", default=25e6, help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
parser.set_defaults(cpu_type="zynqmp")
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq=int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
if args.cpu_type == "zynqmp":
soc.builder = builder
builder.add_software_package('libxil')
builder.add_software_library('libxil')
builder.build(**vivado_build_argdict(args), run=args.build)
if args.load:
prog = soc.platform.create_programmer(args.cable)
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if __name__ == "__main__":
main()
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#
# This file is part of LiteX.
#
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.interconnect import wishbone
from litex.soc.interconnect import axi
from litex.soc.cores.cpu import CPU
# Zynq 7000 ----------------------------------------------------------------------------------------
class Zynq7000(CPU):
variants = ["standard"]
family = "arm"
name = "zynq7000"
human_name = "Zynq7000"
data_width = 32
endianness = "little"
reset_address = 0x00000000
gcc_triple = "arm-xilinx-eabi"
linker_output_format = "elf32-littlearm"
nop = "nop"
io_regions = {0x00000000: 0x100000000} # Origin, Length.
# Memory Mapping.
@property
def mem_map(self):
return {"csr": 0x00000000}
def __init__(self, platform, variant):
platform.ps7_cfg = {}
self.platform = platform
self.reset = Signal()
self.periph_buses = [] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
self.axi_gp_masters = [] # General Purpose AXI Masters.
self.axi_gp_slaves = [] # General Purpose AXI Slaves.
self.axi_hp_slaves = [] # High Performance AXI Slaves.
# # #
# PS7 Clocking.
self.clock_domains.cd_ps7 = ClockDomain()
# PS7 (Minimal) ----------------------------------------------------------------------------
self.ps7_name = None
self.ps7_tcl = []
ps7_rst_n = Signal()
ps7_ddram_pads = platform.request("ps7_ddram")
self.cpu_params = dict(
# Clk / Rst.
io_PS_CLK = platform.request("ps7_clk"),
io_PS_PORB = platform.request("ps7_porb"),
io_PS_SRSTB = platform.request("ps7_srstb"),
# MIO.
io_MIO = platform.request("ps7_mio"),
# DDRAM.
io_DDR_Addr = ps7_ddram_pads.addr,
io_DDR_BankAddr = ps7_ddram_pads.ba,
io_DDR_CAS_n = ps7_ddram_pads.cas_n,
io_DDR_Clk_n = ps7_ddram_pads.ck_n,
io_DDR_Clk = ps7_ddram_pads.ck_p,
io_DDR_CKE = ps7_ddram_pads.cke,
io_DDR_CS_n = ps7_ddram_pads.cs_n,
io_DDR_DM = ps7_ddram_pads.dm,
io_DDR_DQ = ps7_ddram_pads.dq,
io_DDR_DQS_n = ps7_ddram_pads.dqs_n,
io_DDR_DQS = ps7_ddram_pads.dqs_p,
io_DDR_ODT = ps7_ddram_pads.odt,
io_DDR_RAS_n = ps7_ddram_pads.ras_n,
io_DDR_DRSTB = ps7_ddram_pads.reset_n,
io_DDR_WEB = ps7_ddram_pads.we_n,
io_DDR_VRN = ps7_ddram_pads.vrn,
io_DDR_VRP = ps7_ddram_pads.vrp,
# USB0.
i_USB0_VBUS_PWRFAULT = 0,
# Fabric Clk / Rst.
o_FCLK_CLK0 = ClockSignal("ps7"),
o_FCLK_RESET0_N = ps7_rst_n
)
self.specials += AsyncResetSynchronizer(self.cd_ps7, ~ps7_rst_n)
# Enet0 mdio -------------------------------------------------------------------------------
ps7_enet0_mdio_pads = platform.request("ps7_enet0_mdio", loose=True)
if ps7_enet0_mdio_pads is not None:
self.cpu_params.update(
o_ENET0_MDIO_MDC = ps7_enet0_mdio_pads.mdc,
i_ENET0_MDIO_I = ps7_enet0_mdio_pads.i,
o_ENET0_MDIO_O = ps7_enet0_mdio_pads.o,
o_ENET0_MDIO_T = ps7_enet0_mdio_pads.t
)
# Enet0 ------------------------------------------------------------------------------------
ps7_enet0_pads = platform.request("ps7_enet0", loose=True)
if ps7_enet0_pads is not None:
self.cpu_params.update(
o_ENET0_GMII_TX_EN = ps7_enet0_pads.tx_en,
o_ENET0_GMII_TX_ER = ps7_enet0_pads.tx_er,
o_ENET0_GMII_TXD = ps7_enet0_pads.txd,
i_ENET0_GMII_COL = ps7_enet0_pads.col,
i_ENET0_GMII_CRS = ps7_enet0_pads.crs,
i_ENET0_GMII_RX_CLK = ps7_enet0_pads.rx_clk,
i_ENET0_GMII_RX_DV = ps7_enet0_pads.rx_dv,
i_ENET0_GMII_RX_ER = ps7_enet0_pads.rx_er,
i_ENET0_GMII_TX_CLK = ps7_enet0_pads.tx_clk,
i_ENET0_GMII_RXD = ps7_enet0_pads.rxd
)
# SDIO0 ------------------------------------------------------------------------------------
ps7_sdio0_pads = platform.request("ps7_sdio0", loose=True)
if ps7_sdio0_pads is not None:
self.cpu_params.update(
o_SDIO0_CLK = ps7_sdio0_pads.clk,
i_SDIO0_CLK_FB = ps7_sdio0_pads.clk_fb,
o_SDIO0_CMD_O = ps7_sdio0_pads.cmd_o,
i_SDIO0_CMD_I = ps7_sdio0_pads.cmd_i,
o_SDIO0_CMD_T = ps7_sdio0_pads.cmd_t,
o_SDIO0_DATA_O = ps7_sdio0_pads.data_o,
i_SDIO0_DATA_I = ps7_sdio0_pads.data_i,
o_SDIO0_DATA_T = ps7_sdio0_pads.data_t,
o_SDIO0_LED = ps7_sdio0_pads.led,
o_SDIO0_BUSPOW = ps7_sdio0_pads.buspow,
o_SDIO0_BUSVOLT = ps7_sdio0_pads.busvolt,
)
# SDIO0_CD ---------------------------------------------------------------------------------
ps7_sdio0_cd_pads = platform.request("ps7_sdio0_cd", loose=True)
if ps7_sdio0_cd_pads is not None:
self.cpu_params.update(i_SDIO0_CDN = ps7_sdio0_cd_pads.cdn)
# SDIO0_WP ---------------------------------------------------------------------------------
ps7_sdio0_wp_pads = platform.request("ps7_sdio0_wp", loose=True)
if ps7_sdio0_wp_pads is not None:
self.cpu_params.update(i_SDIO0_WP = ps7_sdio0_wp_pads.wp)
# TODO compare this possibly redundant homebrew zynq config thingy against upstream litex functionality
def gen_ps7_ip(self, preset='ZedBoard'):
'''
To customize Zynq PS configuration, add key value pairs to
self.platform.ps7_cfg. Use vivado gui to find valid settings:
* open project: `build/gateware/*.xpr`
* open `ps7_cfg` in the project manager
* customize Peripheral I/O Pins / Fabric clocks / etc, OK
* Generate Output Products: Skip
* File, Project, Open Journal File
* Copy the lines starting with `set_proerty`, strip the `CONFIG.`
from the key and add them to ps7_cfg dict
TODO better integration with the litex build process
'''
print('gen_ps7_ip()', self.platform.ps7_cfg)
cmds = self.platform.toolchain.pre_synthesis_commands
preset = '{{' + preset + '}}'
cmds += [
'create_ip -name processing_system7 -vendor xilinx.com -library ip -version 5.5 -module_name ps7_cfg',
f'set_property -dict [list CONFIG.preset {preset}] [get_ips ps7_cfg]',
]
for k, v in self.platform.ps7_cfg.items():
v = '{{' + v + '}}'
cmds.append(f'set_property CONFIG.{k} {v} [get_ips ps7_cfg]')
cmds += [
'upgrade_ip [get_ips ps7_cfg]',
'generate_target all [get_ips ps7_cfg]',
'set_msg_config -id {{Vivado 12-5447}} -new_severity {{Info}}',
'synth_ip [get_ips ps7_cfg]'
]
def set_ps7_xci(self, xci):
# Add .xci as Vivado IP and set ps7_name from .xci filename.
self.ps7_xci = xci
self.ps7_name = os.path.splitext(os.path.basename(xci))[0]
self.platform.add_ip(xci)
def add_ps7_config(self, config):
# Check that PS7 has been set.
if self.ps7_name is None:
raise Exception("Please set PS7 with set_ps7 method first.")
# Config must be provided as a config, value dict.
assert isinstance(config, dict)
# Add configs to PS7.
self.ps7_tcl.append("set_property -dict [list \\")
for config, value in config.items():
self.ps7_tcl.append("CONFIG.{} {} \\".format(config, '{{' + value + '}}'))
self.ps7_tcl.append(f"] [get_ips {self.ps7_name}]")
def set_ps7(self, name=None, xci=None, preset=None, config=None):
# Check that PS7 has not already been set.
if self.ps7_name is not None:
raise Exception(f"PS7 has already been set to {self.ps7_name}.")
self.ps7_name = preset if name is None else name
# User should provide an .xci file, preset_name or config dict but not all at once.
if (xci is not None) and (preset is not None):
raise Exception("PS7 .xci and preset specified, please only provide one.")
# User provides an .xci file...
if xci is not None:
self.set_ps7_xci(xci)
# User provides a preset or/and config
else:
self.ps7_tcl.append(f"set ps7 [create_ip -vendor xilinx.com -name processing_system7 -module_name {self.ps7_name}]")
if preset is not None:
assert isinstance(preset, str)
self.ps7_tcl.append("set_property -dict [list CONFIG.preset {}] [get_ips {}]".format("{{" + preset + "}}", self.ps7_name))
if config is not None:
self.add_ps7_config(config)
# AXI General Purpose Master -------------------------------------------------------------------
def add_axi_gp_master(self):
assert len(self.axi_gp_masters) < 2
n = len(self.axi_gp_masters)
axi_gpn = axi.AXIInterface(data_width=32, address_width=32, id_width=12)
self.axi_gp_masters.append(axi_gpn)
self.cpu_params.update({
# AXI GP clk.
f"i_M_AXI_GP{n}_ACLK" : ClockSignal("ps7"),
# AXI GP aw.
f"o_M_AXI_GP{n}_AWVALID" : axi_gpn.aw.valid,
f"i_M_AXI_GP{n}_AWREADY" : axi_gpn.aw.ready,
f"o_M_AXI_GP{n}_AWADDR" : axi_gpn.aw.addr,
f"o_M_AXI_GP{n}_AWBURST" : axi_gpn.aw.burst,
f"o_M_AXI_GP{n}_AWLEN" : axi_gpn.aw.len[:4],
f"o_M_AXI_GP{n}_AWSIZE" : axi_gpn.aw.size[:3],
f"o_M_AXI_GP{n}_AWID" : axi_gpn.aw.id,
f"o_M_AXI_GP{n}_AWLOCK" : axi_gpn.aw.lock,
f"o_M_AXI_GP{n}_AWPROT" : axi_gpn.aw.prot,
f"o_M_AXI_GP{n}_AWCACHE" : axi_gpn.aw.cache,
f"o_M_AXI_GP{n}_AWQOS" : axi_gpn.aw.qos,
# AXI GP w.
f"o_M_AXI_GP{n}_WVALID" : axi_gpn.w.valid,
f"o_M_AXI_GP{n}_WLAST" : axi_gpn.w.last,
f"i_M_AXI_GP{n}_WREADY" : axi_gpn.w.ready,
f"o_M_AXI_GP{n}_WID" : axi_gpn.w.id,
f"o_M_AXI_GP{n}_WDATA" : axi_gpn.w.data,
f"o_M_AXI_GP{n}_WSTRB" : axi_gpn.w.strb,
# AXI GP b.
f"i_M_AXI_GP{n}_BVALID" : axi_gpn.b.valid,
f"o_M_AXI_GP{n}_BREADY" : axi_gpn.b.ready,
f"i_M_AXI_GP{n}_BID" : axi_gpn.b.id,
f"i_M_AXI_GP{n}_BRESP" : axi_gpn.b.resp,
# AXI GP ar.
f"o_M_AXI_GP{n}_ARVALID" : axi_gpn.ar.valid,
f"i_M_AXI_GP{n}_ARREADY" : axi_gpn.ar.ready,
f"o_M_AXI_GP{n}_ARADDR" : axi_gpn.ar.addr,
f"o_M_AXI_GP{n}_ARBURST" : axi_gpn.ar.burst,
f"o_M_AXI_GP{n}_ARLEN" : axi_gpn.ar.len[:4],
f"o_M_AXI_GP{n}_ARID" : axi_gpn.ar.id,
f"o_M_AXI_GP{n}_ARLOCK" : axi_gpn.ar.lock,
f"o_M_AXI_GP{n}_ARSIZE" : axi_gpn.ar.size[:3],
f"o_M_AXI_GP{n}_ARPROT" : axi_gpn.ar.prot,
f"o_M_AXI_GP{n}_ARCACHE" : axi_gpn.ar.cache,
f"o_M_AXI_GP{n}_ARQOS" : axi_gpn.ar.qos,
# AXI GP r.
f"i_M_AXI_GP{n}_RVALID" : axi_gpn.r.valid,
f"o_M_AXI_GP{n}_RREADY" : axi_gpn.r.ready,
f"i_M_AXI_GP{n}_RLAST" : axi_gpn.r.last,
f"i_M_AXI_GP{n}_RID" : axi_gpn.r.id,
f"i_M_AXI_GP{n}_RRESP" : axi_gpn.r.resp,
f"i_M_AXI_GP{n}_RDATA" : axi_gpn.r.data,
})
return axi_gpn
# AXI General Purpose Slave --------------------------------------------------------------------
def add_axi_gp_slave(self):
raise NotImplementedError
# AXI High Performance Slave -------------------------------------------------------------------
def add_axi_hp_slave(self):
assert len(self.axi_hp_slaves) < 4
n = len(self.axi_hp_slaves)
axi_hpn = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
self.axi_hp_slaves.append(axi_hpn)
self.cpu_params.update({
# AXI HP0 clk.
f"i_S_AXI_HP{n}_ACLK" : ClockSignal("ps7"),
# AXI HP0 aw.
f"i_S_AXI_HP{n}_AWVALID" : axi_hpn.aw.valid,
f"o_S_AXI_HP{n}_AWREADY" : axi_hpn.aw.ready,
f"i_S_AXI_HP{n}_AWADDR" : axi_hpn.aw.addr,
f"i_S_AXI_HP{n}_AWBURST" : axi_hpn.aw.burst,
f"i_S_AXI_HP{n}_AWLEN" : axi_hpn.aw.len,
f"i_S_AXI_HP{n}_AWSIZE" : axi_hpn.aw.size,
f"i_S_AXI_HP{n}_AWID" : axi_hpn.aw.id,
f"i_S_AXI_HP{n}_AWLOCK" : axi_hpn.aw.lock,
f"i_S_AXI_HP{n}_AWPROT" : axi_hpn.aw.prot,
f"i_S_AXI_HP{n}_AWCACHE" : axi_hpn.aw.cache,
f"i_S_AXI_HP{n}_AWQOS" : axi_hpn.aw.qos,
# AXI HP0 w.
f"i_S_AXI_HP{n}_WVALID" : axi_hpn.w.valid,
f"i_S_AXI_HP{n}_WLAST" : axi_hpn.w.last,
f"o_S_AXI_HP{n}_WREADY" : axi_hpn.w.ready,
f"i_S_AXI_HP{n}_WID" : axi_hpn.w.id,
f"i_S_AXI_HP{n}_WDATA" : axi_hpn.w.data,
f"i_S_AXI_HP{n}_WSTRB" : axi_hpn.w.strb,
# AXI HP0 b.
f"o_S_AXI_HP{n}_BVALID" : axi_hpn.b.valid,
f"i_S_AXI_HP{n}_BREADY" : axi_hpn.b.ready,
f"o_S_AXI_HP{n}_BID" : axi_hpn.b.id,
f"o_S_AXI_HP{n}_BRESP" : axi_hpn.b.resp,
# AXI HP0 ar.
f"i_S_AXI_HP{n}_ARVALID" : axi_hpn.ar.valid,
f"o_S_AXI_HP{n}_ARREADY" : axi_hpn.ar.ready,
f"i_S_AXI_HP{n}_ARADDR" : axi_hpn.ar.addr,
f"i_S_AXI_HP{n}_ARBURST" : axi_hpn.ar.burst,
f"i_S_AXI_HP{n}_ARLEN" : axi_hpn.ar.len,
f"i_S_AXI_HP{n}_ARID" : axi_hpn.ar.id,
f"i_S_AXI_HP{n}_ARLOCK" : axi_hpn.ar.lock,
f"i_S_AXI_HP{n}_ARSIZE" : axi_hpn.ar.size,
f"i_S_AXI_HP{n}_ARPROT" : axi_hpn.ar.prot,
f"i_S_AXI_HP{n}_ARCACHE" : axi_hpn.ar.cache,
f"i_S_AXI_HP{n}_ARQOS" : axi_hpn.ar.qos,
# AXI HP0 r.
f"o_S_AXI_HP{n}_RVALID" : axi_hpn.r.valid,
f"i_S_AXI_HP{n}_RREADY" : axi_hpn.r.ready,
f"o_S_AXI_HP{n}_RLAST" : axi_hpn.r.last,
f"o_S_AXI_HP{n}_RID" : axi_hpn.r.id,
f"o_S_AXI_HP{n}_RRESP" : axi_hpn.r.resp,
f"o_S_AXI_HP{n}_RDATA" : axi_hpn.r.data,
})
return axi_hpn
def add_emio_spi(self, spi_pads, n=0):
'''
Connect a PS SPI interfaces to some IO pads.
n selects which one (0 or 1).
'''
self.platform.ps7_cfg[f'CONFIG.PCW_SPI{n}_PERIPHERAL_ENABLE'] = '1'
p = spi_pads
for s, v in zip(["SCLK", "MOSI", "SS"], [p.clk, p.mosi, p.cs_n]):
self.cpu_params["o_SPI{}_{}_O".format(n, s)] = v
try:
miso = p.miso
except AttributeError:
print("add_emio_spi(): MISO pin hard-wired to 0")
miso = 0
self.cpu_params["i_SPI{}_MISO_I".format(n)] = miso
# ----------------
# unused PS pins
# ----------------
for s, v in zip(["SCLK", "MOSI", "SS"], [0, 0, 1]):
self.cpu_params["i_SPI{}_{}_I".format(n, s)] = v
# o_SPI0_SS1_O=
# o_SPI0_SS2_O=
# o_SPI0_SCLK_T=
# o_SPI0_MOSI_T=
# o_SPI0_SS_T=
def add_emio_gpio(self, target_pads=None, N=32):
'''
Connect a PS GPIO interfaces to some IO pads.
N selects width of GPIO port.
'''
self.platform.ps7_cfg.update(
PCW_GPIO_EMIO_GPIO_ENABLE='1',
PCW_GPIO_EMIO_GPIO_IO=str(N)
)
GPIO_O = Signal(N)
GPIO_T = Signal(N)
GPIO_I = Signal(N)
self.cpu_params.update(
o_GPIO_O=GPIO_O,
o_GPIO_T=GPIO_T,
i_GPIO_I=GPIO_I
)
if target_pads:
self.specials += Tristate(target_pads, GPIO_O, ~GPIO_T, GPIO_I)
def add_emio_i2c(self, target_pads, n=0):
'''
Connect a PS I2C interfaces to some IO pads.
n selects which one (0 or 1).
'''
self.platform.ps7_cfg[f'PCW_I2C{n}_PERIPHERAL_ENABLE'] = '1'
for l in ('SDA', 'SCL'):
_I = Signal()
_O = Signal()
_T = Signal()
self.cpu_params["i_I2C{}_{}_I".format(n, l)] = _I
self.cpu_params["o_I2C{}_{}_O".format(n, l)] = _O
self.cpu_params["o_I2C{}_{}_T".format(n, l)] = _T
p = getattr(target_pads, l.lower())
self.specials += Tristate(p, _O, ~_T, _I)
# @staticmethod
# def add_sources(platform):
# platform.add_ip(os.path.join("ip", self.ps7))
def do_finalize(self):
if self.ps7_name is None:
raise Exception("PS7 must be set with set_ps7 or set_ps7_xci methods.")
if len(self.ps7_tcl):
self.ps7_tcl += [
f"upgrade_ip [get_ips {self.ps7_name}]",
f"generate_target all [get_ips {self.ps7_name}]",
f"synth_ip [get_ips {self.ps7_name}]"
]
self.platform.toolchain.pre_synthesis_commands += self.ps7_tcl
self.specials += Instance(self.ps7_name, **self.cpu_params)
| [
"litex.soc.interconnect.axi.AXIInterface"
] | [((3364, 3411), 'migen.genlib.resetsync.AsyncResetSynchronizer', 'AsyncResetSynchronizer', (['self.cd_ps7', '(~ps7_rst_n)'], {}), '(self.cd_ps7, ~ps7_rst_n)\n', (3386, 3411), False, 'from migen.genlib.resetsync import AsyncResetSynchronizer\n'), ((9968, 10030), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': '(32)', 'address_width': '(32)', 'id_width': '(12)'}), '(data_width=32, address_width=32, id_width=12)\n', (9984, 10030), False, 'from litex.soc.interconnect import axi\n'), ((12889, 12950), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': '(64)', 'address_width': '(32)', 'id_width': '(6)'}), '(data_width=64, address_width=32, id_width=6)\n', (12905, 12950), False, 'from litex.soc.interconnect import axi\n'), ((16867, 16913), 'migen.fhdl.specials.Tristate', 'Tristate', (['target_pads', 'GPIO_O', '(~GPIO_T)', 'GPIO_I'], {}), '(target_pads, GPIO_O, ~GPIO_T, GPIO_I)\n', (16875, 16913), False, 'from migen.fhdl.specials import Tristate\n'), ((17519, 17543), 'migen.fhdl.specials.Tristate', 'Tristate', (['p', '_O', '(~_T)', '_I'], {}), '(p, _O, ~_T, _I)\n', (17527, 17543), False, 'from migen.fhdl.specials import Tristate\n'), ((7979, 8000), 'os.path.basename', 'os.path.basename', (['xci'], {}), '(xci)\n', (7995, 8000), False, 'import os\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk.
("clk40", 0, Pins("A9"), IOStandard("LVCMOS33")),
# Leds.
("led_g_n", 0, Pins("R16"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
("led_g_n", 1, Pins("M18"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO4.
("led_g_n", 2, Pins("T17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO6.
("led_r_n", 0, Pins("V17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")),
("led_r_n", 1, Pins("R18"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO5.
("led_r_n", 2, Pins("R17"), IOStandard("LVCMOS33"), Misc("OPENDRAIN=ON")), # Shared with FPGA_GPIO7.
# Revision.
("revision", 0,
Subsignal("hardware", Pins("D4 M2 N4 J3")),
Subsignal("bom", Pins("N1 M1 N2")),
IOStandard("LVCMOS25")
),
# GPIO.
("gpio", 0, Pins("N15 N18 N16 N17 M18 R18 T17 R17"), IOStandard("LVCMOS33")),
("egpio", 0, Pins("A10 A8"), IOStandard("LVCMOS33")),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("U17")),
Subsignal("clk", Pins("U16")),
Subsignal("miso", Pins("U18")),
Subsignal("mosi", Pins("T18")),
IOStandard("LVCMOS33"),
),
# I2C.
("i2c", 0,
Subsignal("scl", Pins("C10"), Misc("OPENDRAIN=ON")),
Subsignal("sda", Pins("B9"), Misc("OPENDRAIN=ON")),
IOStandard("LVCMOS33"),
),
# SPI.
("spi", 0,
# SPI.
Subsignal("clk", Pins("M3")),
Subsignal("lms_cs_n", Pins("N3")),
Subsignal("dac_cs_n", Pins("L4")),
Subsignal("mosi", Pins("L3")),
Subsignal("miso", Pins("K3")),
IOStandard("LVCMOS25"),
),
# Temperature Sensor.
("lms75_os", 0, Pins("K2"), IOStandard("LVCMOS25")),
# USB-FIFO.
("usb_fifo_clk", 0, Pins("D17"), IOStandard("LVCMOS33")),
("usb_fifo", 0,
Subsignal("rst_n", Pins("M17")),
Subsignal("data", Pins(
"A13 B12 B15 C12 A16 A12 D18 B17",
"F15 D16 D15 C13 H18 B13 J18 A15",
"B18 C18 A17 K18 C15 L18 F18 C16",
"G16 D13 G18 F16 C17 F17 K15 K17")),
Subsignal("be", Pins("L15 J17 K16 H17")),
Subsignal("rxf_n", Pins("H16")),
Subsignal("txe_n", Pins("M16")),
Subsignal("rd_n", Pins("H15")),
Subsignal("wr_n", Pins("J16")),
Subsignal("oe_n", Pins("L16")),
IOStandard("LVCMOS33"),
),
# RF-IC / LMS7002M.
("lms7002m", 0,
# Control.
Subsignal("pwrdwn_n", Pins("C8")),
Subsignal("rxen", Pins("D6")),
Subsignal("txen", Pins("B7")),
# RX-Interface (LMS -> FPGA).
Subsignal("diq1", Pins("J2 L1 K1 K4 G3 F4 J1 H1 G4 F2 G1 H2")),
Subsignal("txnrx1", Pins("F1")),
Subsignal("iqsel1", Pins("F3")),
Subsignal("mclk1", Pins("H4")),
Subsignal("fclk1", Pins("H3")),
# RX-Interface (FPGA -> LMS).
Subsignal("diq2", Pins("A3 C2 A2 B4 C3 B2 D3 B1 A4 C1 C7 A6")),
Subsignal("txnrx2", Pins("B6")),
Subsignal("iqsel2", Pins("C4")),
Subsignal("mclk2", Pins("D2")),
Subsignal("fclk2", Pins("D1")),
# IOStandard/Slew Rate.
IOStandard("LVCMOS25"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk40"
default_clk_period = 1e9/40e6
def __init__(self, device="LFE5U", toolchain="trellis", **kwargs):
assert device in ["LFE5U"]
LatticePlatform.__init__(self, device + "-45F-8MG285C", _io, toolchain=toolchain, **kwargs)
def create_programmer(self):
return OpenOCDJTAGProgrammer("openocd_limesdr_mini_v2.cfg")
def do_finalize(self, fragment):
self.add_period_constraint(self.lookup_request("clk40", loose=True), 1e9/40e6)
| [
"litex.build.lattice.programmer.OpenOCDJTAGProgrammer",
"litex.build.lattice.LatticePlatform.__init__"
] | [((3999, 4095), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', "(device + '-45F-8MG285C')", '_io'], {'toolchain': 'toolchain'}), "(self, device + '-45F-8MG285C', _io, toolchain=\n toolchain, **kwargs)\n", (4023, 4095), False, 'from litex.build.lattice import LatticePlatform\n'), ((4140, 4192), 'litex.build.lattice.programmer.OpenOCDJTAGProgrammer', 'OpenOCDJTAGProgrammer', (['"""openocd_limesdr_mini_v2.cfg"""'], {}), "('openocd_limesdr_mini_v2.cfg')\n", (4161, 4192), False, 'from litex.build.lattice.programmer import OpenOCDJTAGProgrammer\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2020-2022 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
from migen import *
from litex_boards.targets.digilent_arty import BaseSoC
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex.build.generic_platform import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.bitbang import I2CMaster
from litex.soc.cores.ov2640 import OV2640
from litex.soc.interconnect.stream import SyncFIFO
from litevideo.output import VideoOut
from litex.soc.cores.gpu import *
from litex.soc.cores.fastvdma.fastvdma_reader import *
from litex.soc.cores.fastvdma.fastvdma_writer import *
from litex.soc.cores.fastvdma.fastvdma_ov2640 import *
# Platform description for HDMI connector on Expansion Board ---------------------------------------
def hdmi_pmod_io():
return[
("hdmi_out", 0,
Subsignal("clk_p", Pins("T13"), IOStandard("TMDS_33")), # JC9
Subsignal("clk_n", Pins("U13"), IOStandard("TMDS_33")), # JC10
Subsignal("data0_p", Pins("U12"), IOStandard("TMDS_33")), # JC1
Subsignal("data0_n", Pins("V12"), IOStandard("TMDS_33")), # JC2
Subsignal("data1_p", Pins("V10"), IOStandard("TMDS_33")), # JC3
Subsignal("data1_n", Pins("V11"), IOStandard("TMDS_33")), # JC4
Subsignal("data2_p", Pins("U14"), IOStandard("TMDS_33")), # JC7
Subsignal("data2_n", Pins("V14"), IOStandard("TMDS_33")), # JC8
),
]
_hdmi_pmod_io = hdmi_pmod_io()
# Platform description for OV2640 cameras with I2C multiplexer on Expansion Board ------------------
def double_ov2640_pmod_io():
return [
("ov2640", 0,
Subsignal("data", Pins("pmoda:3 pmodb:4 pmodb:1 pmodb:0 pmoda:7 pmoda:6 pmoda:1 pmoda:5"), IOStandard("LVCMOS33")),
Subsignal("pclk", Pins("pmoda:2"), IOStandard("LVCMOS33")),
Subsignal("href", Pins("pmoda:0"), IOStandard("LVCMOS33")),
Subsignal("vsync", Pins("pmoda:4"), IOStandard("LVCMOS33")),
),
("ov2640", 1,
Subsignal("data", Pins("pmodd:5 pmodd:6 pmodd:3 pmodd:2 pmodd:1 pmodd:0 pmodb:3 pmodb:6"), IOStandard("LVCMOS33")),
Subsignal("pclk", Pins("pmodd:4"), IOStandard("LVCMOS33")),
Subsignal("href", Pins("pmodb:2"), IOStandard("LVCMOS33")),
Subsignal("vsync", Pins("pmodb:5"), IOStandard("LVCMOS33")),
),
("i2c_pmod", 0,
Subsignal("scl", Pins("pmodb:7"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("pmodd:7"), IOStandard("LVCMOS33")),
)
]
_double_ov2640_pmod_io = double_ov2640_pmod_io()
# ArtySoC ------------------------------------------------------------------------------------------
class ArtySoC(BaseSoC):
csr_map = {**BaseSoC.csr_map, **{
"i2c_pmod": 0, # addr: 0xf0000000
"fastvdma_ov2640_left": 1, # addr: 0xf0000800
"fastvdma_ov2640_right": 2, # addr: 0xf0001000
"ethmac": 3, # addr: 0xf0001800
"ethphy": 4, # addr: 0xf0002000
"uart": 5, # addr: 0xf0002800
"timer0": 6, # addr: 0xf0003000
"framebuffer": 7, # addr: 0xf0003800
"gpu": 8, # addr: 0xf0004000
"gpu_dma_r1": 9, # addr: 0xf0004800
"gpu_dma_r2": 10, # addr: 0xf0005000
"gpu_dma_w": 11, # addr: 0xf0005800
}}
interrupt_map = {**BaseSoC.interrupt_map, **{
"uart": 0,
"timer0": 1,
"ethmac": 2,
"fastvdma_ov2640_left": 3,
"fastvdma_ov2640_right": 4,
"gpu_dma_r1": 5,
"gpu_dma_r2": 6,
"gpu_dma_w": 7,
}}
mem_map = {**BaseSoC.mem_map, **{
"rom": 0x00000000,
"sram": 0x10000000,
"main_ram": 0x40000000,
"ethmac": 0x80000000,
"fastvdma_ov2640_left": 0x8000a000,
"fastvdma_ov2640_right": 0x8000b000,
"gpu_dma_r1": 0x8000c000,
"gpu_dma_r2": 0x8000d000,
"gpu_dma_w": 0x8000e000,
"csr": 0xf0000000,
}}
def __init__(self, **kwargs):
BaseSoC.__init__(self, **kwargs)
self.clock_domains.cd_clk100 = ClockDomain()
self.crg.pll.create_clkout(self.cd_clk100, 100e6)
# OV2640 Cameras ---------------------------------------------------------------------------
self.platform.add_extension(_double_ov2640_pmod_io)
self.platform.add_extension(_hdmi_pmod_io)
self.submodules.i2c_pmod = I2CMaster(self.platform.request("i2c_pmod"))
# Left camera DMA reader (camera -> memory)
self.submodules.fastvdma_ov2640_left = fastvdma_ov2640_left = FastVDMA_OV2640(self.platform)
self.bus.add_slave("fastvdma_slave_control_1", self.fastvdma_ov2640_left.wb_slave_control, SoCRegion(origin=0x8000a000, size=0x00001000, cached=False))
self.bus.add_master(name="fastvdma_master_writer_1", master=fastvdma_ov2640_left.wb_master_writer)
# Right camera DMA reader (camera -> memory)
self.submodules.fastvdma_ov2640_right = fastvdma_ov2640_right = FastVDMA_OV2640(self.platform)
self.bus.add_slave("fastvdma_slave_control_2", self.fastvdma_ov2640_right.wb_slave_control, SoCRegion(origin=0x8000b000, size=0x00001000, cached=False))
self.bus.add_master(name="fastvdma_master_writer_2", master=fastvdma_ov2640_right.wb_master_writer)
# Left camera signals synchronization
self.submodules.ov2640_left = OV2640(self.platform.request("ov2640", number=0), fastvdma_ov2640_left.io_sync_readerBusy, leds_pads=self.platform.request("rgb_led", number=0))
# Right camera signals synchronization
self.submodules.ov2640_right = OV2640(self.platform.request("ov2640", number=1), fastvdma_ov2640_right.io_sync_readerBusy)
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ov2640_left_pclk_clk]")
self.platform.add_platform_command("set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets ov2640_right_pclk_clk]")
# Connect camera to DMA
self.comb += [
# connection to FIFO
fastvdma_ov2640_left.axi_stream_reader.data.eq(self.ov2640_left.fifo.source.data),
fastvdma_ov2640_left.axi_stream_reader.valid.eq(self.ov2640_left.fifo.source.valid),
self.ov2640_left.fifo.source.ready.eq(fastvdma_ov2640_left.axi_stream_reader.ready),
fastvdma_ov2640_left.io_sync_readerSync.eq(self.ov2640_left.vsync[0] & ~self.ov2640_left.vsync[1]),
fastvdma_ov2640_right.axi_stream_reader.data.eq(self.ov2640_right.fifo.source.data),
fastvdma_ov2640_right.axi_stream_reader.valid.eq(self.ov2640_right.fifo.source.valid),
self.ov2640_right.fifo.source.ready.eq(fastvdma_ov2640_right.axi_stream_reader.ready),
fastvdma_ov2640_right.io_sync_readerSync.eq(self.ov2640_right.vsync[0] & ~self.ov2640_right.vsync[1]),
]
# HDMI -------------------------------------------------------------------------------------
dram_port = self.sdram.crossbar.get_port(
mode = "read",
data_width = 32,
clock_domain = "pix",
reverse = False,
rx_buffer_depth = 32,
cmd_buffer_depth = 32,
priority = 1)
self.clock_domains.cd_hdmi = ClockDomain()
self.specials += Instance("BUFG", i_I=self.crg.cd_sys.clk, o_O=self.cd_hdmi.clk)
self.submodules.framebuffer = framebuffer = ClockDomainsRenamer("hdmi")(VideoOut(
device = self.platform.device,
pads = self.platform.request("hdmi_out"),
dram_port = dram_port,
fifo_depth= 1024))
self.comb += [
self.cd_hdmi.clk.eq(self.crg.cd_sys.clk),
self.cd_hdmi.rst.eq(self.framebuffer.reset.storage | self.crg.cd_sys.rst),
framebuffer.driver.clocking.cd_pix.rst.eq(self.cd_hdmi.rst),
]
clocking = framebuffer.driver.clocking
self.platform.add_period_constraint(clocking.cd_pix.clk, 1e9/31.5e6)
self.platform.add_period_constraint(clocking.cd_pix5x.clk, 1e9/(5*31.5e6))
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
framebuffer.driver.clocking.cd_pix.clk,
framebuffer.driver.clocking.cd_pix5x.clk)
# -| FastVDMA RAM reader 1 |----------------------------------------------------------------
self.submodules.gpu_dma_r1 = FastVDMAReader(self.platform)
# Attach FastVDMA's frontends to Wishbone bus
self.bus.add_slave("gpu_dma_r1_ctrl", self.gpu_dma_r1.wb_ctrl,
SoCRegion(origin=0x8000c000, size=0x1000, cached=False))
self.bus.add_master("gpu_dma_r1", self.gpu_dma_r1.wb_r)
# -| FastVDMA RAM reader 2 |----------------------------------------------------------------
self.submodules.gpu_dma_r2 = FastVDMAReader(self.platform)
# Attach FastVDMA's frontends to Wishbone bus
self.bus.add_slave("gpu_dma_r2_ctrl", self.gpu_dma_r2.wb_ctrl,
SoCRegion(origin=0x8000d000, size=0x1000, cached=False))
self.bus.add_master("gpu_dma_r2", self.gpu_dma_r2.wb_r)
# -| FastVDMA RAM writer |------------------------------------------------------------------
self.submodules.gpu_dma_w = FastVDMAWriter(self.platform)
# Attach FastVDMA's frontends to Wishbone bus
self.bus.add_slave("gpu_dma_w_ctrl", self.gpu_dma_w.wb_ctrl,
SoCRegion(origin=0x8000e000, size=0x1000, cached=False))
self.bus.add_master("gpu_dma_w", self.gpu_dma_w.wb_w)
# Pass both inputs to GPU through FIFO to synchronize signals
self.submodules.input1_fifo = input1_fifo = SyncFIFO([("data", 32)], 512)
self.submodules.input2_fifo = input2_fifo = SyncFIFO([("data", 32)], 512)
self.comb += [
# Inputs from memory (images from cameras)
self.gpu_dma_r1.axi_m.connect(input1_fifo.sink, omit={"user"}),
# Inputs from memory (generated images with text)
self.gpu_dma_r2.axi_m.connect(input2_fifo.sink, omit={"user"}),
]
# -| Alpha blender |------------------------------------------------------------------------
gpu_dmas = [input1_fifo.source, input2_fifo.source, self.gpu_dma_w]
self.submodules.gpu = GPU(gpu_dmas)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--variant", default="a7-35", help="Board variant: a7-35 (default) or a7-100")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
ethopts = parser.add_mutually_exclusive_group()
ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address")
parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting")
parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
assert not (args.with_etherbone and args.eth_dynamic_ip)
soc = ArtySoC(
variant = args.variant,
toolchain = args.toolchain,
sys_clk_freq = int(float(args.sys_clk_freq)),
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
eth_ip = args.eth_ip,
eth_dynamic_ip = args.eth_dynamic_ip,
ident_version = args.no_ident_version,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {}
builder.build(**builder_kwargs, run=args.build)
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
if __name__ == "__main__":
main()
| [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc.SoCRegion",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.soc.interconnect.stream.SyncFIFO"
] | [((11099, 11158), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on Arty A7"""'}), "(description='LiteX SoC on Arty A7')\n", (11122, 11158), False, 'import argparse\n'), ((12480, 12505), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (12497, 12505), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((4567, 4599), 'litex_boards.targets.digilent_arty.BaseSoC.__init__', 'BaseSoC.__init__', (['self'], {}), '(self, **kwargs)\n', (4583, 4599), False, 'from litex_boards.targets.digilent_arty import BaseSoC\n'), ((10332, 10361), 'litex.soc.interconnect.stream.SyncFIFO', 'SyncFIFO', (["[('data', 32)]", '(512)'], {}), "([('data', 32)], 512)\n", (10340, 10361), False, 'from litex.soc.interconnect.stream import SyncFIFO\n'), ((10414, 10443), 'litex.soc.interconnect.stream.SyncFIFO', 'SyncFIFO', (["[('data', 32)]", '(512)'], {}), "([('data', 32)], 512)\n", (10422, 10443), False, 'from litex.soc.interconnect.stream import SyncFIFO\n'), ((13091, 13117), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (13111, 13117), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((5259, 5312), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(2147524608)', 'size': '(4096)', 'cached': '(False)'}), '(origin=2147524608, size=4096, cached=False)\n', (5268, 5312), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((5684, 5737), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(2147528704)', 'size': '(4096)', 'cached': '(False)'}), '(origin=2147528704, size=4096, cached=False)\n', (5693, 5737), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((9205, 9258), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(2147532800)', 'size': '(4096)', 'cached': '(False)'}), '(origin=2147532800, size=4096, cached=False)\n', (9214, 9258), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((9649, 9702), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(2147536896)', 'size': '(4096)', 'cached': '(False)'}), '(origin=2147536896, size=4096, cached=False)\n', (9658, 9702), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((10090, 10143), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(2147540992)', 'size': '(4096)', 'cached': '(False)'}), '(origin=2147540992, size=4096, cached=False)\n', (10099, 10143), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((13303, 13362), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bit')"], {}), "(builder.gateware_dir, soc.build_name + '.bit')\n", (13315, 13362), False, 'import os\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
"""
LiteX standalone SoC generator.
This generator reduces the scope of LiteX to CPU/Peripherals selection/integration and to the creation
of SoC with MMAP/Streaming DMA interfaces that can be reintegrated in external designs (or LiteX SoC).
Think of it as a mini Nios SOPC Builder/ Zynq or Microblaze Subsystem generator that offers you the
possibility to reuse any of CPU supported by LiteX :)
"""
import argparse
from migen import *
from litex.build.generic_platform import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect import axi
# IOs/Interfaces -----------------------------------------------------------------------------------
def get_common_ios():
return [
# Clk/Rst.
("clk", 0, Pins(1)),
("rst", 0, Pins(1)),
]
def get_uart_ios():
return [
# Serial
("uart", 0,
Subsignal("tx", Pins(1)),
Subsignal("rx", Pins(1)),
)
]
# Platform -----------------------------------------------------------------------------------------
class Platform(GenericPlatform):
def build(self, fragment, build_dir, build_name, **kwargs):
os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir)
conv_output = self.get_verilog(fragment, name=build_name)
conv_output.write(f"{build_name}.v")
# LiteX SoC Generator ------------------------------------------------------------------------------
class LiteXSoCGenerator(SoCMini):
def __init__(self, name="litex_soc", sys_clk_freq=int(50e6), **kwargs):
# Platform ---------------------------------------------------------------------------------
platform = Platform(device="", io=get_common_ios())
platform.name = name
platform.add_extension(get_uart_ios())
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(
clk = platform.request("clk"),
rst = platform.request("rst"),
)
# SoC --------------------------------------------------------------------------------------
if kwargs["uart_name"] == "serial":
kwargs["uart_name"] = "uart"
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# MMAP Slave Interface ---------------------------------------------------------------------
s_bus = {
"wishbone" : wishbone.Interface(),
"axi-lite" : axi.AXILiteInterface(),
}[kwargs["bus_standard"]]
self.bus.add_master(name="mmap_s", master=s_bus)
platform.add_extension(s_bus.get_ios("mmap_s"))
wb_pads = platform.request("mmap_s")
self.comb += s_bus.connect_to_pads(wb_pads, mode="slave")
# MMAP Master Interface --------------------------------------------------------------------
# FIXME: Allow Region configuration.
m_bus = {
"wishbone" : wishbone.Interface(),
"axi-lite" : axi.AXILiteInterface(),
}[kwargs["bus_standard"]]
wb_region = SoCRegion(origin=0x2000_0000, size=0x1000_0000, cached=True) # FIXME.
self.bus.add_slave(name="mmap_m", slave=m_bus, region=wb_region)
platform.add_extension(m_bus.get_ios("mmap_m"))
wb_pads = platform.request("mmap_m")
self.comb += m_bus.connect_to_pads(wb_pads, mode="master")
# Build --------------------------------------------------------------------------------------------
def main():
# Arguments.
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX standalone SoC generator")
target_group = parser.add_argument_group(title="Generator options")
target_group.add_argument("--name", default="litex_soc", help="SoC Name.")
target_group.add_argument("--build", action="store_true", help="Build SoC.")
target_group.add_argument("--sys-clk-freq", default=int(50e6), help="System clock frequency.")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
# SoC.
soc = LiteXSoCGenerator(
name = args.name,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
# Build.
builder = Builder(soc, **builder_argdict(args))
builder.build(build_name=args.name, run=args.build)
if __name__ == "__main__":
main()
| [
"litex.soc.interconnect.axi.AXILiteInterface",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.soc.SoCRegion",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((3866, 3934), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX standalone SoC generator"""'}), "(description='LiteX standalone SoC generator')\n", (3888, 3934), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((3346, 3402), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': '(536870912)', 'size': '(268435456)', 'cached': '(True)'}), '(origin=536870912, size=268435456, cached=True)\n', (3355, 3402), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((2700, 2720), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (2718, 2720), False, 'from litex.soc.interconnect import wishbone\n'), ((2747, 2769), 'litex.soc.interconnect.axi.AXILiteInterface', 'axi.AXILiteInterface', ([], {}), '()\n', (2767, 2769), False, 'from litex.soc.interconnect import axi\n'), ((3220, 3240), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (3238, 3240), False, 'from litex.soc.interconnect import wishbone\n'), ((3267, 3289), 'litex.soc.interconnect.axi.AXILiteInterface', 'axi.AXILiteInterface', ([], {}), '()\n', (3287, 3289), False, 'from litex.soc.interconnect import axi\n')] |
#
# This file is part of LiteHelloWorld.
#
from migen import *
from litex.soc.interconnect import stream
from litehelloworld.common import *
from litex.soc.interconnect import wishbone
class DummyLitexModel(Module):
def __init__(self, inputs, outputs):
#Create inputs and outputs for the core
self.sink = stream.Endpoint(dummy_phy_data_layout)
self.source = stream.Endpoint(dummy_phy_data_layout)
#Assign them to inputs and outputs
self.comb += [
self.sink.eq(outputs),
self.source.eq(inputs),
]
#Copy data from inputs to outputs synchronously with sys_clock
self.sync += [
self.sink.eq(self.source),
]
#Create wishbone connexion to gather data from it
self.bus = wishbone.Interface()
#QUESTION/FIXME: IS THERE SOME LIB READY TO USE TO MANAGE READ/WRITE ACCESS TO WISHBONE BASED ON MEMORY MAP AND SO ON?
#Memory section from this doc is outdated? https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers
#EXAMPLE COULD BE TO WRITE TO self.sink WHEN DATA IS COMING/READ FROM THE WISHBONE BUS AND TO WRITE TO WISHBONE BUS WHEN SPECIFIC DATA IS COMING FROM self.source
#TODO HERE: DUMMY EXTERNAL HDL CORE INTEGRATION EXAMPLE CLASS | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.interconnect.stream.Endpoint"
] | [((329, 367), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['dummy_phy_data_layout'], {}), '(dummy_phy_data_layout)\n', (344, 367), False, 'from litex.soc.interconnect import stream\n'), ((390, 428), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['dummy_phy_data_layout'], {}), '(dummy_phy_data_layout)\n', (405, 428), False, 'from litex.soc.interconnect import stream\n'), ((796, 816), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (814, 816), False, 'from litex.soc.interconnect import wishbone\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk48", 0, Pins("E2"), IOStandard("3.3-V LVTTL")),
# SDR SDRAM
("sdram_clock", 0, Pins("B14"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"A12 B12 A15 A14 D14 C14 D11 D12",
"E11 C9 B13 E10 ")),
Subsignal("ba", Pins("A10 B10")),
Subsignal("cs_n", Pins("A11")),
Subsignal("cke", Pins("E9")),
Subsignal("ras_n", Pins("D9")),
Subsignal("cas_n", Pins("B7")),
Subsignal("we_n", Pins("B11")),
Subsignal("dq", Pins(
"A2 B4 B3 A3 A4 A5 B5 A6",
"F8 C8 E7 E8 E6 D8 D6 B6")),
Subsignal("dm", Pins("A7 F9")),
Misc("FAST_OUTPUT_REGISTER ON"),
IOStandard("3.3-V LVTTL")
),
# # SPIFlash (W25Q64)
# ("spiflash", 0,
# # clk
# Subsignal("cs_n", Pins("E2")),
# Subsignal("clk", Pins("K2")),
# Subsignal("mosi", Pins("D1")),
# Subsignal("miso", Pins("E2")),
# IOStandard("3.3-V LVTTL"),
# ),
# Serial
("serial", 0,
Subsignal("tx", Pins("G1"), IOStandard("3.3-V LVTTL")), # Pin D0
Subsignal("rx", Pins("N3"), IOStandard("3.3-V LVTTL")) # Pin D1
),
# # USB FIFO
# ("usb_fifo", 0,
# Subsignal("dq", Pins("AM28 AL28 AM29 AK28 AK32 AM30 AJ32 AL30"), IOStandard("LVCMOS33")),
# Subsignal("txe_n", Pins("AM31"), IOStandard("LVCMOS33")),
# Subsignal("rxf_n", Pins("AJ31"), IOStandard("LVCMOS33")),
# Subsignal("rd_n", Pins("AL32"), IOStandard("LVCMOS33")),
# Subsignal("wr_n", Pins("AG28"), IOStandard("LVCMOS33")),
# Subsignal("siwu_n", Pins("AJ28"), IOStandard("LVCMOS33")),
# ),
# # PCIe
# ("pcie_x1", 0,
# Subsignal("clk_p", Pins("AM14")),
# Subsignal("clk_n", Pins("AM15")),
# Subsignal("rx_p", Pins("AM8 AK12")),
# Subsignal("rx_n", Pins("AM9 AK13")),
# Subsignal("tx_p", Pins("AK9 AM11")),
# Subsignal("tx_n", Pins("AK10 AM12")),
# Subsignal("perst", Pins("D22"), IOStandard("LVCMOS33")),
# Subsignal("wake_n", Pins("A23"), IOStandard("LVCMOS33")),
# ),
# # SPIFlash
# ("spiflash", 0,
# Subsignal("clk", Pins("AM3")),
# Subsignal("cs_n", Pins("AJ3")),
# Subsignal("mosi", Pins("AK2")),
# Subsignal("miso", Pins("AJ2")),
# Subsignal("wp", Pins("AM2")),
# Subsignal("hold", Pins("AL1")),
# IOStandard("LVCMOS33")
# ),
# # HDMI
# ("hdmi", 0,
# Subsignal("tx_d_r", Pins("AS12 AE12 W8 Y8 AD11 AD10 AE11 Y5")),
# Subsignal("tx_d_g", Pins("AF10 Y4 AE9 AB4 AE7 AF6 AF8 AF5")),
# Subsignal("tx_d_b", Pins("AE4 AH2 AH4 AH5 AH6 AG6 AF9 AE8")),
# Subsignal("tx_clk", Pins("AG5")),
# Subsignal("tx_de", Pins("AD19")),
# Subsignal("tx_hs", Pins("T8")),
# Subsignal("tx_vs", Pins("V13")),
# Subsignal("tx_int", Pins("AF11")),
# Misc("FAST_OUTPUT_REGISTER ON"),
# IOStandard("3.3-V LVTTL")
# ),
# # I2C
# ("i2c", 0,
# Subsignal("scl", Pins("U10")),
# Subsignal("sda", Pins("AA4")),
# IOStandard("3.3-V LVTTL")
# ),
'''
# SAM D21 PINS
set_location_assignment PIN_B1 -to bMKR_AREF
set_location_assignment PIN_C2 -to bMKR_A[0]
set_location_assignment PIN_C3 -to bMKR_A[1]
set_location_assignment PIN_C6 -to bMKR_A[2]
set_location_assignment PIN_D1 -to bMKR_A[3]
set_location_assignment PIN_D3 -to bMKR_A[4]
set_location_assignment PIN_F3 -to bMKR_A[5]
set_location_assignment PIN_G2 -to bMKR_A[6]
set_location_assignment PIN_G1 -to bMKR_D[0]
set_location_assignment PIN_N3 -to bMKR_D[1]
set_location_assignment PIN_P3 -to bMKR_D[2]
set_location_assignment PIN_R3 -to bMKR_D[3]
set_location_assignment PIN_T3 -to bMKR_D[4]
set_location_assignment PIN_T2 -to bMKR_D[5]
set_location_assignment PIN_G16 -to bMKR_D[6]
set_location_assignment PIN_G15 -to bMKR_D[7]
set_location_assignment PIN_F16 -to bMKR_D[8]
set_location_assignment PIN_F15 -to bMKR_D[9]
set_location_assignment PIN_C16 -to bMKR_D[10]
set_location_assignment PIN_C15 -to bMKR_D[11]
set_location_assignment PIN_B16 -to bMKR_D[12]
set_location_assignment PIN_C11 -to bMKR_D[13]
set_location_assignment PIN_A13 -to bMKR_D[14]
# Mini PCIe
set_location_assignment PIN_P8 -to bPEX_PIN6
set_location_assignment PIN_L7 -to bPEX_PIN8
set_location_assignment PIN_N8 -to bPEX_PIN10
set_location_assignment PIN_T8 -to iPEX_PIN11
set_location_assignment PIN_M8 -to bPEX_PIN12
set_location_assignment PIN_R8 -to iPEX_PIN13
set_location_assignment PIN_L8 -to bPEX_PIN14
set_location_assignment PIN_M10 -to bPEX_PIN16
set_location_assignment PIN_N12 -to bPEX_PIN20
set_location_assignment PIN_T9 -to iPEX_PIN23
set_location_assignment PIN_R9 -to iPEX_PIN25
set_location_assignment PIN_T13 -to bPEX_PIN28
set_location_assignment PIN_R12 -to bPEX_PIN30
set_location_assignment PIN_A9 -to iPEX_PIN31
set_location_assignment PIN_F13 -to bPEX_PIN32
set_location_assignment PIN_B9 -to iPEX_PIN33
set_location_assignment PIN_R13 -to bPEX_PIN42
set_location_assignment PIN_P14 -to bPEX_PIN44
set_location_assignment PIN_T15 -to bPEX_PIN45
set_location_assignment PIN_R14 -to bPEX_PIN46
set_location_assignment PIN_T14 -to bPEX_PIN47
set_location_assignment PIN_F14 -to bPEX_PIN48
set_location_assignment PIN_D16 -to bPEX_PIN49
set_location_assignment PIN_D15 -to bPEX_PIN51
set_location_assignment PIN_T12 -to bPEX_RST
# HDMI output
set_instance_assignment -name IO_STANDARD LVDS -to oHDMI_TX*
set_instance_assignment -name IO_STANDARD LVDS -to oHDMI_CLK
set_location_assignment PIN_R16 -to oHDMI_TX[0]
set_location_assignment PIN_K15 -to oHDMI_TX[1]
set_location_assignment PIN_J15 -to oHDMI_TX[2]
set_location_assignment PIN_P16 -to oHDMI_TX[0](n)
set_location_assignment PIN_K16 -to oHDMI_TX[1](n)
set_location_assignment PIN_J16 -to oHDMI_TX[2](n)
set_location_assignment PIN_N15 -to oHDMI_CLK
set_location_assignment PIN_N16 -to oHDMI_CLK(n)
set_instance_assignment -name IO_STANDARD "2.5 V" -to bHDMI_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to bHDMI_SDA
set_location_assignment PIN_K5 -to bHDMI_SCL
set_location_assignment PIN_L4 -to bHDMI_SDA
set_location_assignment PIN_M16 -to iHDMI_HPD
# MIPI input
set_instance_assignment -name FAST_INPUT_REGISTER ON -to iMIPI_D*
set_instance_assignment -name IO_STANDARD LVDS -to iMIPI_D*
set_instance_assignment -name IO_STANDARD LVDS -to iMIPI_CLK*
set_location_assignment PIN_L2 -to iMIPI_D[0]
set_location_assignment PIN_J2 -to iMIPI_D[1]
set_location_assignment PIN_L1 -to iMIPI_D[0](n)
set_location_assignment PIN_J1 -to iMIPI_D[1](n)
set_location_assignment PIN_M2 -to iMIPI_CLK
set_location_assignment PIN_M1 -to iMIPI_CLK(n)
set_location_assignment PIN_P2 -to bMIPI_SDA
set_instance_assignment -name IO_STANDARD "2.5 V" -to bMIPI_SDA
set_location_assignment PIN_P1 -to bMIPI_SCL
set_instance_assignment -name IO_STANDARD "2.5 V" -to bMIPI_SCL
set_location_assignment PIN_M7 -to bMIPI_GP[0]
set_location_assignment PIN_P9 -to bMIPI_GP[1]
# misc pins
set_instance_assignment -name IO_STANDARD "2.5 V" -to panel_en
set_location_assignment PIN_L4 -to panel_en
# Flash interface
set_location_assignment PIN_C1 -to oFLASH_MOSI
set_location_assignment PIN_H2 -to iFLASH_MISO
set_location_assignment PIN_H1 -to oFLASH_SCK
set_location_assignment PIN_D2 -to oFLASH_CS
set_location_assignment PIN_R7 -to oFLASH_HOLD
set_location_assignment PIN_T7 -to oFLASH_WP
# interrupt pins
set_location_assignment PIN_N2 -to oSAM_INT
set_location_assignment PIN_L16 -to iSAM_INT
set_instance_assignment -name IO_STANDARD "2.5 V" -to oSAM_INT
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to iSAM_INT
'''
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self):
AlteraPlatform.__init__(self, "10CL016YU256C8G", _io)
def create_programmer(self):
return USBBlaster(cable_name="Arduino MKR Vidor 4000") # [3-2]
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
# Generate PLL clock in STA
self.toolchain.additional_sdc_commands.append("derive_pll_clocks")
# Calculates clock uncertainties
self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty")
| [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((8402, 8455), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""10CL016YU256C8G"""', '_io'], {}), "(self, '10CL016YU256C8G', _io)\n", (8425, 8455), False, 'from litex.build.altera import AlteraPlatform\n'), ((8505, 8552), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {'cable_name': '"""Arduino MKR Vidor 4000"""'}), "(cable_name='Arduino MKR Vidor 4000')\n", (8515, 8552), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((8608, 8650), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (8634, 8650), False, 'from litex.build.altera import AlteraPlatform\n')] |
# This file is Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# This file is Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 Dolu1990 <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018-2017 Tim 'mithro' Ansell <<EMAIL>>
# This file is Copyright (c) 2015 whitequark <<EMAIL>>
# This file is Copyright (c) 2014 <NAME> <<EMAIL>>
# License: BSD
import os
import struct
import inspect
import json
import math
import datetime
import time
from operator import itemgetter
from migen import *
from litex.build.tools import deprecated_warning
from litex.soc.cores import identifier, timer, uart
from litex.soc.cores import cpu
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
__all__ = [
"mem_decoder",
"get_mem_data",
"csr_map_update",
"SoCCore",
"soc_core_args",
"soc_core_argdict",
"SoCMini",
"soc_mini_args",
"soc_mini_argdict",
]
# Helpers ------------------------------------------------------------------------------------------
def version(with_time=True):
if with_time:
return datetime.datetime.fromtimestamp(
time.time()).strftime("%Y-%m-%d %H:%M:%S")
else:
return datetime.datetime.fromtimestamp(
time.time()).strftime("%Y-%m-%d")
def get_mem_data(filename_or_regions, endianness="big", mem_size=None):
# create memory regions
if isinstance(filename_or_regions, dict):
regions = filename_or_regions
else:
filename = filename_or_regions
_, ext = os.path.splitext(filename)
if ext == ".json":
f = open(filename, "r")
regions = json.load(f)
f.close()
else:
regions = {filename: "0x00000000"}
# determine data_size
data_size = 0
for filename, base in regions.items():
data_size = max(int(base, 16) + os.path.getsize(filename), data_size)
assert data_size > 0
if mem_size is not None:
assert data_size < mem_size, (
"file is too big: {}/{} bytes".format(
data_size, mem_size))
# fill data
data = [0]*math.ceil(data_size/4)
for filename, base in regions.items():
with open(filename, "rb") as f:
i = 0
while True:
w = f.read(4)
if not w:
break
if len(w) != 4:
for _ in range(len(w), 4):
w += b'\x00'
if endianness == "little":
data[int(base, 16)//4 + i] = struct.unpack("<I", w)[0]
else:
data[int(base, 16)//4 + i] = struct.unpack(">I", w)[0]
i += 1
return data
def mem_decoder(address, size=0x10000000):
address &= ~0x80000000
size = 2**log2_int(size, False)
assert (address & (size - 1)) == 0
address >>= 2 # bytes to words aligned
size >>= 2 # bytes to words aligned
return lambda a: (a[log2_int(size):-1] == (address >> log2_int(size)))
def csr_map_update(csr_map, csr_peripherals):
csr_map.update(dict((n, v)
for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1)))
# SoCController ------------------------------------------------------------------------------------
class SoCController(Module, AutoCSR):
def __init__(self):
self._reset = CSR()
self._scratch = CSRStorage(32, reset=0x12345678)
self._bus_errors = CSRStatus(32)
# # #
# reset
self.reset = Signal()
self.comb += self.reset.eq(self._reset.re)
# bus errors
self.bus_error = Signal()
bus_errors = Signal(32)
self.sync += \
If(bus_errors != (2**len(bus_errors)-1),
If(self.bus_error,
bus_errors.eq(bus_errors + 1)
)
)
self.comb += self._bus_errors.status.eq(bus_errors)
# SoCCore ------------------------------------------------------------------------------------------
class SoCCore(Module):
# default register/interrupt/memory mappings (can be redefined by user)
csr_map = {}
interrupt_map = {}
mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x01000000, # (default shadow @0x81000000)
"csr": 0x02000000, # (default shadow @0x82000000)
"main_ram": 0x40000000, # (default shadow @0xc0000000)
}
def __init__(self, platform, clk_freq,
# CPU parameters
cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
# MEM MAP parameters
shadow_base=0x80000000,
# ROM parameters
integrated_rom_size=0, integrated_rom_init=[],
# SRAM parameters
integrated_sram_size=4096, integrated_sram_init=[],
# MAIN_RAM parameters
integrated_main_ram_size=0, integrated_main_ram_init=[],
# CSR parameters
csr_data_width=8, csr_alignment=32, csr_address_width=14,
# Identifier parameters
ident="", ident_version=False,
# UART parameters
with_uart=True, uart_name="serial", uart_baudrate=115200, uart_stub=False,
# Timer parameters
with_timer=True,
# Controller parameters
with_ctrl=True,
# Wishbone parameters
wishbone_timeout_cycles=1e6):
self.platform = platform
self.clk_freq = clk_freq
# config dictionary (store all SoC's parameters to be exported to software)
self.config = dict()
# SoC's register/interrupt/memory mappings (default or user defined + dynamically allocateds)
self.soc_csr_map = {}
self.soc_interrupt_map = {}
self.soc_mem_map = self.mem_map
# Regions / Constants lists
self._memory_regions = [] # (name, origin, length)
self._csr_regions = [] # (name, origin, busword, csr_list/Memory)
self._constants = [] # (name, value)
# Wishbone masters/slaves lists
self._wb_masters = []
self._wb_slaves = []
# CSR masters list
self._csr_masters = []
# Parameters managment ---------------------------------------------------------------------
# NOTE: RocketChip reserves the first 256Mbytes for internal use,
# so we must change default mem_map;
# Also, CSRs *must* be 64-bit aligned.
if cpu_type == "rocket":
self.soc_mem_map["rom"] = 0x10000000
self.soc_mem_map["sram"] = 0x11000000
self.soc_mem_map["csr"] = 0x12000000
csr_alignment = 64
if cpu_type == "None":
cpu_type = None
self.cpu_type = cpu_type
self.cpu_variant = cpu.check_format_cpu_variant(cpu_variant)
if integrated_rom_size:
cpu_reset_address = self.soc_mem_map["rom"]
self.cpu_reset_address = cpu_reset_address
self.config["CPU_RESET_ADDR"] = self.cpu_reset_address
self.shadow_base = shadow_base
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size
assert csr_data_width in [8, 32, 64]
assert csr_alignment in [32, 64]
self.csr_data_width = csr_data_width
self.csr_alignment = csr_alignment
self.csr_address_width = csr_address_width
self.with_ctrl = with_ctrl
self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
self.wishbone_timeout_cycles = wishbone_timeout_cycles
# Modules instances ------------------------------------------------------------------------
# Add user's CSRs (needs to be done before the first dynamic allocation)
for _name, _id in self.csr_map.items():
self.add_csr(_name, _id)
# Add SoCController
if with_ctrl:
self.submodules.ctrl = SoCController()
self.add_csr("ctrl", allow_user_defined=True)
# Add CPU
self.config["CPU_TYPE"] = str(cpu_type).upper()
if cpu_type is not None:
if cpu_variant is not None:
self.config["CPU_VARIANT"] = str(cpu_variant.split('+')[0]).upper()
# CPU selection / instance
if cpu_type == "lm32":
self.add_cpu(cpu.lm32.LM32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "mor1kx" or cpu_type == "or1k":
if cpu_type == "or1k":
deprecated_warning("SoCCore's \"cpu-type\" to \"mor1kx\"")
self.add_cpu(cpu.mor1kx.MOR1KX(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "picorv32":
self.add_cpu(cpu.picorv32.PicoRV32(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "vexriscv":
self.add_cpu(cpu.vexriscv.VexRiscv(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "minerva":
self.add_cpu(cpu.minerva.Minerva(platform, self.cpu_reset_address, self.cpu_variant))
elif cpu_type == "rocket":
self.add_cpu(cpu.rocket.RocketRV64(platform, self.cpu_reset_address, self.cpu_variant))
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
# Add CPU CSR (dynamic)
self.add_csr("cpu", allow_user_defined=True)
# Add CPU reserved interrupts
for _name, _id in self.cpu.reserved_interrupts.items():
self.add_interrupt(_name, _id)
# Allow SoCController to reset the CPU
if with_ctrl:
self.comb += self.cpu.reset.eq(self.ctrl.reset)
# Add user's interrupts (needs to be done after CPU reserved interrupts are allocated)
for _name, _id in self.interrupt_map.items():
self.add_interrupt(_name, _id)
# Add integrated ROM
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True, init=integrated_rom_init)
self.register_rom(self.rom.bus, integrated_rom_size)
# Add integrated SRAM
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size, init=integrated_sram_init)
self.register_mem("sram", self.soc_mem_map["sram"], self.sram.bus, integrated_sram_size)
# Add integrated MAIN_RAM (only useful when no external SRAM/SDRAM is available)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size, init=integrated_main_ram_init)
self.register_mem("main_ram", self.soc_mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)
# Add Wishbone to CSR bridge
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(
bus_csr=csr_bus.Interface(csr_data_width, csr_address_width))
self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment
assert 2**(csr_address_width + 2) <= 0x1000000
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 0x1000000)
# Add UART
if with_uart:
if uart_stub:
self.submodules.uart = uart.UARTStub()
else:
if uart_name == "jtag_atlantic":
from litex.soc.cores.jtag import JTAGAtlantic
self.submodules.uart_phy = JTAGAtlantic()
else:
self.submodules.uart_phy = uart.UARTPHY(platform.request(uart_name), clk_freq, uart_baudrate)
self.submodules.uart = ResetInserter()(uart.UART(self.uart_phy))
self.add_csr("uart_phy", allow_user_defined=True)
self.add_csr("uart", allow_user_defined=True)
self.add_interrupt("uart", allow_user_defined=True)
# Add Identifier
if ident:
if ident_version:
ident = ident + " " + version()
self.submodules.identifier = identifier.Identifier(ident)
self.add_csr("identifier_mem", allow_user_defined=True)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
# Add Timer
if with_timer:
self.submodules.timer0 = timer.Timer()
self.add_csr("timer0", allow_user_defined=True)
self.add_interrupt("timer0", allow_user_defined=True)
# Methods --------------------------------------------------------------------------------------
def add_cpu(self, cpu):
if self.finalized:
raise FinalizeError
if hasattr(self, "cpu"):
raise NotImplementedError("More than one CPU is not supported")
self.submodules.cpu = cpu
def add_cpu_or_bridge(self, cpu_or_bridge):
deprecated_warning("SoCCore's \"add_cpu_or_bridge\" call to \"add_cpu\"")
self.add_cpu(cpu_or_bridge)
self.cpu_or_bridge = self.cpu
def add_interrupt(self, interrupt_name, interrupt_id=None, allow_user_defined=False):
# Check that interrupt_name is not already used
if interrupt_name in self.soc_interrupt_map.keys():
if allow_user_defined:
return
else:
raise ValueError("Interrupt conflict, {} name already used".format(interrupt_name))
# Check that interrupt_id is in range
if interrupt_id is not None and interrupt_id >= 32:
raise ValueError("{} Interrupt ID out of range ({}, max=31)".format(
interrupt_name, interrupt_id))
# Interrupt_id not provided: allocate interrupt to the first available id
if interrupt_id is None:
for n in range(32):
if n not in self.soc_interrupt_map.values():
self.soc_interrupt_map.update({interrupt_name: n})
return
raise ValueError("No more space to allocate {} interrupt".format(interrupt_name))
# Interrupt_id provided: check that interrupt_id is not already used and add interrupt
else:
for _name, _id in self.soc_interrupt_map.items():
if interrupt_id == _id:
raise ValueError("Interrupt conflict, {} already used by {} interrupt".format(
interrupt_id, _name))
self.soc_interrupt_map.update({interrupt_name: interrupt_id})
def add_csr(self, csr_name, csr_id=None, allow_user_defined=False):
# Check that csr_name is not already used
if csr_name in self.soc_csr_map.keys():
if allow_user_defined:
return
else:
raise ValueError("CSR conflict, {} name already used".format(csr_name))
# Check that csr_id is in range
if csr_id is not None and csr_id >= 2**self.csr_address_width:
raise ValueError("{} CSR ID out of range ({}, max=31)".format(
csr_name, csr_id))
# csr_id not provided: allocate csr to the first available id
if csr_id is None:
for n in range(2**self.csr_address_width):
if n not in self.soc_csr_map.values():
self.soc_csr_map.update({csr_name: n})
return
raise ValueError("No more space to allocate {} csr".format(csr_name))
# csr_id provided: check that csr_id is not already used and add csr
else:
for _name, _id in self.soc_csr_map.items():
if csr_id == _id:
raise ValueError("CSR conflict, {} already used by {} csr".format(
csr_id, _name))
self.soc_csr_map.update({csr_name: csr_id})
def initialize_rom(self, data):
self.rom.mem.init = data
def add_wb_master(self, wbm):
if self.finalized:
raise FinalizeError
self._wb_masters.append(wbm)
def add_wb_slave(self, address_or_address_decoder, interface, size=None):
if self.finalized:
raise FinalizeError
if size is not None:
address_decoder = mem_decoder(address_or_address_decoder, size)
else:
address_decoder = address_or_address_decoder
self._wb_slaves.append((address_decoder, interface))
def add_csr_master(self, csrm):
# CSR masters are not arbitrated, use this with precaution.
if self.finalized:
raise FinalizeError
self._csr_masters.append(csrm)
def add_memory_region(self, name, origin, length):
def in_this_region(addr):
return addr >= origin and addr < origin + length
for n, o, l in self._memory_regions:
l = 2**log2_int(l, False)
if n == name or in_this_region(o) or in_this_region(o+l-1):
raise ValueError("Memory region conflict between {} and {}".format(n, name))
self._memory_regions.append((name, origin, length))
def register_mem(self, name, address, interface, size=0x10000000):
self.add_wb_slave(address, interface, size)
self.add_memory_region(name, address, size)
def register_rom(self, interface, rom_size=0xa000):
self.add_wb_slave(self.soc_mem_map["rom"], interface, rom_size)
self.add_memory_region("rom", self.cpu_reset_address, rom_size)
def get_memory_regions(self):
return self._memory_regions
def check_csr_range(self, name, addr):
if addr >= 1<<(self.csr_address_width+2):
raise ValueError("{} CSR out of range, increase csr_address_width".format(name))
def check_csr_region(self, name, origin):
for n, o, l, obj in self._csr_regions:
if n == name or o == origin:
raise ValueError("CSR region conflict between {} and {}".format(n, name))
def add_csr_region(self, name, origin, busword, obj):
self.check_csr_region(name, origin)
self._csr_regions.append((name, origin, busword, obj))
def get_csr_regions(self):
return self._csr_regions
def add_constant(self, name, value=None):
self._constants.append((name, value))
def get_constants(self):
r = []
for _name, _id in sorted(self.soc_interrupt_map.items()):
r.append((_name.upper() + "_INTERRUPT", _id))
r += self._constants
return r
def get_csr_dev_address(self, name, memory):
if memory is not None:
name = name + "_" + memory.name_override
try:
return self.soc_csr_map[name]
except KeyError as e:
msg = "Undefined \"{}\" CSR.\n".format(name)
msg += "Avalaible CSRs in {} ({}):\n".format(
self.__class__.__name__, inspect.getfile(self.__class__))
for k in sorted(self.soc_csr_map.keys()):
msg += "- {}\n".format(k)
raise RuntimeError(msg)
except ValueError:
return None
def build(self, *args, **kwargs):
return self.platform.build(self, *args, **kwargs)
# Finalization ---------------------------------------------------------------------------------
def do_finalize(self):
# Verify CPU has required memories
registered_mems = {regions[0] for regions in self._memory_regions}
if self.cpu_type is not None:
for mem in "rom", "sram":
if mem not in registered_mems:
raise FinalizeError("CPU needs \"{}\" to be registered with SoC.register_mem()".format(mem))
# Add the Wishbone Masters/Slaves interconnect
if len(self._wb_masters):
self.submodules.wishbonecon = wishbone.InterconnectShared(self._wb_masters,
self._wb_slaves, register=True, timeout_cycles=self.wishbone_timeout_cycles)
if self.with_ctrl and (self.wishbone_timeout_cycles is not None):
self.comb += self.ctrl.bus_error.eq(self.wishbonecon.timeout.error)
# Collect and create CSRs
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
self.get_csr_dev_address,
data_width=self.csr_data_width,
address_width=self.csr_address_width,
alignment=self.csr_alignment)
# Add CSRs interconnect
self.submodules.csrcon = csr_bus.InterconnectShared(
self._csr_masters, self.csrbankarray.get_buses())
# Check and add CSRs regions
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.check_csr_range(name, 0x800*mapaddr)
self.add_csr_region(name, (self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
self.csr_data_width, csrs)
# Check and add Memory regions
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.check_csr_range(name, 0x800*mapaddr)
self.add_csr_region(name + "_" + memory.name_override,
(self.soc_mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
self.csr_data_width, memory)
# Add CSRs / Config items to constants
for name, constant in self.csrbankarray.constants:
self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))
for name, value in sorted(self.config.items(), key=itemgetter(0)):
self._constants.append(("CONFIG_" + name.upper(), value))
if isinstance(value, str):
self._constants.append(("CONFIG_" + name.upper() + "_" + value, 1))
# Connect interrupts
if hasattr(self, "cpu"):
if hasattr(self.cpu, "interrupt"):
for _name, _id in sorted(self.soc_interrupt_map.items()):
if _name in self.cpu.reserved_interrupts.keys():
continue
if hasattr(self, _name):
module = getattr(self, _name)
assert hasattr(module, 'ev'), "Submodule %s does not have EventManager (xx.ev) module" % _name
self.comb += self.cpu.interrupt[_id].eq(module.ev.irq)
# SoCCore arguments --------------------------------------------------------------------------------
def soc_core_args(parser):
parser.add_argument("--cpu-type", default=None,
help="select CPU: lm32, or1k, picorv32, vexriscv, minerva, rocket")
parser.add_argument("--cpu-variant", default=None,
help="select CPU variant")
parser.add_argument("--integrated-rom-size", default=None, type=int,
help="size/enable the integrated (BIOS) ROM")
parser.add_argument("--integrated-main-ram-size", default=None, type=int,
help="size/enable the integrated main RAM")
parser.add_argument("--uart-stub", default=False, type=bool,
help="enable uart stub")
def soc_core_argdict(args):
r = dict()
for a in [
"cpu_type",
"cpu_variant",
"integrated_rom_size",
"integrated_main_ram_size",
"uart_stub"]:
arg = getattr(args, a)
if arg is not None:
r[a] = arg
return r
# SoCMini ---------------------------------------------------------------------------------------
class SoCMini(SoCCore):
def __init__(self, *args, **kwargs):
if "cpu_type" not in kwargs.keys():
kwargs["cpu_type"] = None
if "integrated_sram_size" not in kwargs.keys():
kwargs["integrated_sram_size"] = 0
if "with_uart" not in kwargs.keys():
kwargs["with_uart"] = False
if "with_timer" not in kwargs.keys():
kwargs["with_timer"] = False
SoCCore.__init__(self, *args, **kwargs)
# SoCMini arguments -----------------------------------------------------------------------------
soc_mini_args = soc_core_args
soc_mini_argdict = soc_core_argdict
| [
"litex.build.tools.deprecated_warning",
"litex.soc.cores.cpu.lm32.LM32",
"litex.soc.cores.timer.Timer",
"litex.soc.cores.cpu.picorv32.PicoRV32",
"litex.soc.cores.uart.UARTStub",
"litex.soc.interconnect.csr_bus.Interface",
"litex.soc.interconnect.csr_bus.CSRBankArray",
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#
# This file is part of LiteX.
#
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2015-2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from litex.build.generic_platform import GenericPlatform
from litex.build.gowin import common, gowin
# GowinPlatform -----------------------------------------------------------------------------------
class GowinPlatform(GenericPlatform):
bitstream_ext = ".fs"
def __init__(self, device, *args, toolchain="gowin", devicename=None, **kwargs):
GenericPlatform.__init__(self, device, *args, **kwargs)
if not devicename:
idx = device.find('-')
likely_name = f"{device[:idx]}-{device[idx+3]}"
raise ValueError(f"devicename not provided, maybe {likely_name}?")
self.devicename = devicename
if toolchain == "gowin":
self.toolchain = gowin.GowinToolchain()
elif toolchain == "apicula":
raise ValueError("Apicula toolchain needs more work")
else:
raise ValueError("Unknown toolchain")
def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.gowin_special_overrides)
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so,
attr_translate=self.toolchain.attr_translate,
**kwargs)
def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs)
| [
"litex.build.generic_platform.GenericPlatform.get_verilog",
"litex.build.generic_platform.GenericPlatform.__init__",
"litex.build.gowin.gowin.GowinToolchain"
] | [((528, 583), 'litex.build.generic_platform.GenericPlatform.__init__', 'GenericPlatform.__init__', (['self', 'device', '*args'], {}), '(self, device, *args, **kwargs)\n', (552, 583), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((1247, 1369), 'litex.build.generic_platform.GenericPlatform.get_verilog', 'GenericPlatform.get_verilog', (['self', '*args'], {'special_overrides': 'so', 'attr_translate': 'self.toolchain.attr_translate'}), '(self, *args, special_overrides=so,\n attr_translate=self.toolchain.attr_translate, **kwargs)\n', (1274, 1369), False, 'from litex.build.generic_platform import GenericPlatform\n'), ((884, 906), 'litex.build.gowin.gowin.GowinToolchain', 'gowin.GowinToolchain', ([], {}), '()\n', (904, 906), False, 'from litex.build.gowin import common, gowin\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.soc.cores.cpu import CPU
from litex.soc.interconnect import axi
class ZynqMP(CPU):
variants = ["standard"]
family = "aarch64"
name = "zynqmp"
human_name = "Zynq Ultrascale+ MPSoC"
data_width = 64
endianness = "little"
reset_address = 0xc000_0000
gcc_triple = "aarch64-none-elf"
gcc_flags = ""
linker_output_format = "elf64-littleaarch64"
nop = "nop"
io_regions = { # Origin, Length.
0x8000_0000: 0x4000_0000,
0xe000_0000: 0xff_2000_0000 # TODO: there are more details here
}
@property
def mem_map(self):
return {
"sram": 0x0000_0000, # DDR low in fact
"rom": 0xc000_0000, # Quad SPI memory
}
def __init__(self, platform, variant, *args, **kwargs):
super().__init__(*args, **kwargs)
self.platform = platform
self.reset = Signal()
self.periph_buses = [] # Peripheral buses (Connected to main SoC's bus).
self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
self.axi_gp_masters = [None] * 3 # General Purpose AXI Masters.
self.clock_domains.cd_ps = ClockDomain()
self.ps_name = "ps"
self.ps_tcl = []
self.config = {'PSU__FPGA_PL0_ENABLE': 1} # enable pl_clk0
rst_n = Signal()
self.cpu_params = dict(
o_pl_clk0=ClockSignal("ps"),
o_pl_resetn0=rst_n
)
self.comb += ResetSignal("ps").eq(~rst_n)
self.ps_tcl.append(f"set ps [create_ip -vendor xilinx.com -name zynq_ultra_ps_e -module_name {self.ps_name}]")
def add_axi_gp_master(self, n=0, data_width=32):
assert n < 3 and self.axi_gp_masters[n] is None
assert data_width in [32, 64, 128]
axi_gpn = axi.AXIInterface(data_width=data_width, address_width=32, id_width=16)
self.config[f'PSU__USE__M_AXI_GP{n}'] = 1
self.config[f'PSU__MAXIGP{n}__DATA_WIDTH'] = data_width
self.axi_gp_masters.append(axi_gpn)
xpd = {0 : "fpd", 1 : "fpd", 2 : "lpd"}[n]
self.cpu_params[f"i_maxihpm0_{xpd}_aclk"] = ClockSignal("ps")
layout = axi_gpn.layout_flat()
dir_map = {DIR_M_TO_S: 'o', DIR_S_TO_M: 'i'}
for group, signal, direction in layout:
sig_name = group + signal
if sig_name in ['bfirst', 'blast', 'rfirst', 'arfirst', 'arlast', 'awfirst', 'awlast', 'wfirst', 'wid']:
continue
direction = dir_map[direction]
self.cpu_params[f'{direction}_maxigp{n}_{group}{signal}'] = getattr(getattr(axi_gpn, group), signal)
return axi_gpn
def do_finalize(self):
if len(self.ps_tcl):
self.ps_tcl.append("set_property -dict [list \\")
for config, value in self.config.items():
self.ps_tcl.append("CONFIG.{} {} \\".format(config, '{{' + str(value) + '}}'))
self.ps_tcl.append(f"] [get_ips {self.ps_name}]")
self.ps_tcl += [
f"generate_target all [get_ips {self.ps_name}]",
f"synth_ip [get_ips {self.ps_name}]"
]
self.platform.toolchain.pre_synthesis_commands += self.ps_tcl
self.specials += Instance(self.ps_name, **self.cpu_params)
| [
"litex.soc.interconnect.axi.AXIInterface"
] | [((2070, 2140), 'litex.soc.interconnect.axi.AXIInterface', 'axi.AXIInterface', ([], {'data_width': 'data_width', 'address_width': '(32)', 'id_width': '(16)'}), '(data_width=data_width, address_width=32, id_width=16)\n', (2086, 2140), False, 'from litex.soc.interconnect import axi\n')] |
from migen import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
class SPRAM(Module):
"""
ICE40 UltraPlus family-specific Wishbone interface to the Single Port RAM
(SPRAM) primitives. Because SPRAM is much more coarse grained than Block
RAM resources, this RAM is only minimally configurable at present (64kB or
128kB). Because it is single port, this module is meant to be used as the
CPU's RAM region, leaving block RAM free for other use.
"""
def __init__(self, width=32, size=64*1024):
# Right now, LiteX only supports 32-bit CPUs. To get a 32-bit data bus,
# we must width-cascade 2 16-bit SPRAMs. We've already used 2 out of 4
# SPRAMs for this, so the only other valid config is using all 4 SPRAMs
# by depth-cascading.
if width != 32:
raise ValueError("Width of Up5kSPRAM must be 32 bits")
if size != 64*1024 and size != 128*1024:
raise ValueError("Size of Up5kSPRAM must be 64kB or 128kB.")
self.bus = wishbone.Interface(width)
bytesels = []
for i in range(0, 2):
datain = Signal(16)
dataout = Signal(16)
maskwren = Signal(4)
wren = Signal(1)
# 64k vs 128k-specific routing signals.
datain0 = Signal(16)
dataout0 = Signal(16)
maskwren0 = Signal(4)
if size == 128 * 1024:
datain1 = Signal(16)
dataout1 = Signal(16)
maskwren1 = Signal(4)
# Generic routing common to all depths.
for j in range(16):
self.comb += [self.bus.dat_r[16*i + j].eq(dataout[j])]
self.comb += [
datain.eq(self.bus.dat_w[16*i:16*i+16]),
# MASKWREN is nibble-based, interestingly enough.
maskwren.eq(
Cat(
Replicate(self.bus.sel[2*i], 2),
Replicate(self.bus.sel[2*i + 1], 2),
)
),
wren.eq(self.bus.we & self.bus.stb & self.bus.cyc)
]
# Signals which must be routed differently based on depth.
# 64kB
if size == 64*1024:
self.comb += [
datain0.eq(datain),
dataout.eq(dataout0),
maskwren0.eq(maskwren)
]
# 128kB
else:
self.comb += [
If(self.bus.adr[14],
datain1.eq(datain),
dataout.eq(dataout1),
maskwren1.eq(maskwren)
).Else(
datain0.eq(datain),
dataout.eq(dataout0),
maskwren0.eq(maskwren)
)
]
self.specials.spram = Instance("SB_SPRAM256KA",
i_ADDRESS=self.bus.adr[0:14], i_DATAIN=datain0,
i_MASKWREN=maskwren0,
i_WREN=wren,
i_CHIPSELECT=C(1,1),
i_CLOCK=ClockSignal("sys"),
i_STANDBY=C(0,1),
i_SLEEP=C(0,1),
i_POWEROFF=C(1,1),
o_DATAOUT=dataout0
)
# We need to depth cascade if using 128kB.
if size == 128*1024:
self.specials.spram = Instance("SB_SPRAM256KA",
i_ADDRESS=self.bus.adr[0:14], i_DATAIN=datain1,
i_MASKWREN=maskwren1,
i_WREN=wren,
i_CHIPSELECT=C(1,1),
i_CLOCK=ClockSignal("sys"),
i_STANDBY=C(0,1),
i_SLEEP=C(0,1),
i_POWEROFF=C(1,1),
o_DATAOUT=dataout1
)
self.sync += [
self.bus.ack.eq(0),
If(self.bus.stb & self.bus.cyc & ~self.bus.ack,
self.bus.ack.eq(1)
)
]
class LED(Module, AutoCSR):
def __init__(self, pads):
rgba_pwm = Signal(3)
self.dat = CSRStorage(8)
self.addr = CSRStorage(4)
self.ctrl = CSRStorage(4)
self.specials += Instance("SB_RGBA_DRV",
i_CURREN = self.ctrl.storage[1],
i_RGBLEDEN = self.ctrl.storage[2],
i_RGB0PWM = rgba_pwm[0],
i_RGB1PWM = rgba_pwm[1],
i_RGB2PWM = rgba_pwm[2],
o_RGB0 = pads.rgb0,
o_RGB1 = pads.rgb1,
o_RGB2 = pads.rgb2,
p_CURRENT_MODE = "0b1",
p_RGB0_CURRENT = "0b000011",
p_RGB1_CURRENT = "0b000001",
p_RGB2_CURRENT = "0b000011",
)
self.specials += Instance("SB_LEDDA_IP",
i_LEDDCS = self.dat.re,
i_LEDDCLK = ClockSignal(),
i_LEDDDAT7 = self.dat.storage[7],
i_LEDDDAT6 = self.dat.storage[6],
i_LEDDDAT5 = self.dat.storage[5],
i_LEDDDAT4 = self.dat.storage[4],
i_LEDDDAT3 = self.dat.storage[3],
i_LEDDDAT2 = self.dat.storage[2],
i_LEDDDAT1 = self.dat.storage[1],
i_LEDDDAT0 = self.dat.storage[0],
i_LEDDADDR3 = self.addr.storage[3],
i_LEDDADDR2 = self.addr.storage[2],
i_LEDDADDR1 = self.addr.storage[1],
i_LEDDADDR0 = self.addr.storage[0],
i_LEDDDEN = self.dat.re,
i_LEDDEXE = self.ctrl.storage[0],
# o_LEDDON = led_is_on, # Indicates whether LED is on or not
# i_LEDDRST = ResetSignal(), # This port doesn't actually exist
o_PWMOUT0 = rgba_pwm[0],
o_PWMOUT1 = rgba_pwm[1],
o_PWMOUT2 = rgba_pwm[2],
o_LEDDON = Signal(),
)
class SBWarmBoot(Module, AutoCSR):
def __init__(self, parent):
self.ctrl = CSRStorage(size=8)
self.addr = CSRStorage(size=32)
do_reset = Signal()
self.comb += [
# "Reset Key" is 0xac (0b101011xx)
do_reset.eq(self.ctrl.storage[2] & self.ctrl.storage[3] & ~self.ctrl.storage[4]
& self.ctrl.storage[5] & ~self.ctrl.storage[6] & self.ctrl.storage[7])
]
self.specials += Instance("SB_WARMBOOT",
i_S0 = self.ctrl.storage[0],
i_S1 = self.ctrl.storage[1],
i_BOOT = do_reset,
)
parent.config["BITSTREAM_SYNC_HEADER1"] = 0x7e99aa7e
parent.config["BITSTREAM_SYNC_HEADER2"] = 0x7eaa997e
| [
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.wishbone.Interface"
] | [((1097, 1122), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', (['width'], {}), '(width)\n', (1115, 1122), False, 'from litex.soc.interconnect import wishbone\n'), ((4219, 4232), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {}), '(8)\n', (4229, 4232), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((4253, 4266), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(4)'], {}), '(4)\n', (4263, 4266), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((4287, 4300), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(4)'], {}), '(4)\n', (4297, 4300), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((5978, 5996), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'size': '(8)'}), '(size=8)\n', (5988, 5996), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((6017, 6036), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'size': '(32)'}), '(size=32)\n', (6027, 6036), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n')] |
#!/usr/bin/env python3
# Copyright 2021 The CFU-Playground Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
import argparse
import general
from litex.soc.integration import soc as litex_soc
from litex.soc.integration import builder
from litex.build.xilinx import vivado
from typing import Callable
class DigilentArtySoCWorkflow(general.GeneralSoCWorkflow):
"""Specializes the general workflow for the Digilent Arty."""
def __init__(
self,
args: argparse.Namespace,
soc_constructor: Callable[..., litex_soc.LiteXSoC],
builder_constructor: Callable[..., builder.Builder] = None,
) -> None:
"""Initializes the Arty workflow with an extra --variant argument.
Args:
args: An argparse Namespace that holds SoC and build options.
soc_constructor: The constructor for the LiteXSoC.
builder_constructor: The constructor for the LiteX Builder. If
omitted, litex.soc.integration.builder.Builder will be used.
"""
parser = argparse.ArgumentParser(description='Digilent Arty args.')
parser.add_argument('--variant',
default='a7-35',
help='Arty variant: a7-35 (default) or a7-100')
arty_args = parser.parse_known_args()[0]
args = argparse.Namespace(**vars(arty_args), **vars(args))
#
# If using SymbiFlow, and the user hasn't specified the target freq,
# use 75MHz as default. Currently, using the litex-boards default 100MHz
# with SymbiFlow usually results in a bitstream that does not function
# on the board.
#
# This should be removed when SymbiFlow can reliably
# produce a working bitstream at 100MHz.
#
if args.toolchain == 'symbiflow' and not args.sys_clk_freq:
args.sys_clk_freq = 75000000
print("INFO:Workflow:Setting sys_clk_freq to 75MHz.");
super().__init__(args, soc_constructor, builder_constructor)
def make_soc(self, **kwargs) -> litex_soc.LiteXSoC:
"""Runs make_soc with a l2_size parameter and jtagbone disabled."""
return super().make_soc(l2_size=8 * 1024,
variant=self.args.variant,
with_jtagbone=False,
**kwargs)
def build_soc(self, soc: litex_soc.LiteXSoC, **kwargs) -> builder.Builder:
"""Specializes build_soc to add Vivado args if needed."""
if isinstance(soc.platform.toolchain, vivado.XilinxVivadoToolchain):
kwargs.update(vivado.vivado_build_argdict(self.args))
return super().build_soc(soc, **kwargs)
| [
"litex.build.xilinx.vivado.vivado_build_argdict"
] | [((1555, 1613), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""Digilent Arty args."""'}), "(description='Digilent Arty args.')\n", (1578, 1613), False, 'import argparse\n'), ((3126, 3164), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado.vivado_build_argdict', (['self.args'], {}), '(self.args)\n', (3153, 3164), False, 'from litex.build.xilinx import vivado\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import UJProg
# IOs ----------------------------------------------------------------------------------------------
_io_common = [
# Clk / Rst
("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
("rst", 0, Pins("R1"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("B2"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("C2"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("C1"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D2"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("D1"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("E2"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("E1"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("H3"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),
Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
),
# SDR SDRAM
("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"M20 M19 L20 L19 K20 K19 K18 J20",
"J19 H20 N19 G20 G19")),
Subsignal("dq", Pins(
"J16 L18 M18 N18 P18 T18 T17 U20",
"E19 D20 D19 C20 E18 F18 J18 J17")),
Subsignal("we_n", Pins("T20")),
Subsignal("ras_n", Pins("R20")),
Subsignal("cas_n", Pins("T19")),
Subsignal("cs_n", Pins("P20")),
Subsignal("cke", Pins("F20")),
Subsignal("ba", Pins("P19 N20")),
Subsignal("dm", Pins("U19 E20")),
IOStandard("LVCMOS33"),
Misc("SLEWRATE=FAST"),
),
# GPIOs
("gpio", 0,
Subsignal("p", Pins("B11")),
Subsignal("n", Pins("C11")),
IOStandard("LVCMOS33")
),
("gpio", 1,
Subsignal("p", Pins("A10")),
Subsignal("n", Pins("A11")),
IOStandard("LVCMOS33")
),
("gpio", 2,
Subsignal("p", Pins("A9")),
Subsignal("n", Pins("B10")),
IOStandard("LVCMOS33")
),
("gpio", 3,
Subsignal("p", Pins("B9")),
Subsignal("n", Pins("C10")),
IOStandard("LVCMOS33")
),
# USB
("usb", 0,
Subsignal("d_p", Pins("D15")),
Subsignal("d_n", Pins("E15")),
Subsignal("pullup", Pins("B12 C12")),
IOStandard("LVCMOS33")
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("R2")),
Subsignal("miso", Pins("V2")),
Subsignal("mosi", Pins("W2")),
Subsignal("wp", Pins("Y2")),
Subsignal("hold", Pins("W1")),
IOStandard("LVCMOS33")
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("R2")),
Subsignal("dq", Pins("W2", "V2", "Y2", "W1")),
IOStandard("LVCMOS33")
),
# GPDI
("gpdi", 0,
Subsignal("clk_p", Pins("A17"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
#Subsignal("clk_n", Pins("B18"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data0_p", Pins("A12"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
#Subsignal("data0_n", Pins("A13"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data1_p", Pins("A14"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
#Subsignal("data1_n", Pins("C14"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
Subsignal("data2_p", Pins("A16"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
#Subsignal("data2_n", Pins("B16"), IOStandard("LVCMOS33D"), Misc("DRIVE=4")),
#Subsignal("cec", Pins("A18"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
#Subsignal("scl", Pins("E19"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
#Subsignal("sda", Pins("B19"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP"))
),
# OLED
("oled_spi", 0,
Subsignal("clk", Pins("P4")),
Subsignal("mosi", Pins("P3")),
IOStandard("LVCMOS33"),
),
("oled_ctl", 0,
Subsignal("dc", Pins("P1")),
Subsignal("resn", Pins("P2")),
Subsignal("csn", Pins("N2")),
IOStandard("LVCMOS33"),
),
# Expansion Connectors
("j1", 0,
Subsignal("gn0", Pins("C11")),
Subsignal("gp0", Pins("B11")),
Subsignal("gn1", Pins("A11")),
Subsignal("gp1", Pins("A10")),
Subsignal("gn2", Pins("B10")),
Subsignal("gp2", Pins("A9")),
Subsignal("gn3", Pins("C10")),
Subsignal("gp3", Pins("B9")),
Subsignal("gn4", Pins("A8")),
Subsignal("gp4", Pins("A7")),
Subsignal("gn5", Pins("B8")),
Subsignal("gp5", Pins("C8")),
Subsignal("gn6", Pins("C7")),
Subsignal("gp6", Pins("C6")),
Subsignal("gn7", Pins("B6")),
Subsignal("gp7", Pins("A6")),
Subsignal("gn8", Pins("A5")),
Subsignal("gp8", Pins("A4")),
Subsignal("gn9", Pins("B1")),
Subsignal("gp9", Pins("A2")),
Subsignal("gn10", Pins("B4")),
Subsignal("gp10", Pins("C4")),
Subsignal("gn11", Pins("E3")),
Subsignal("gp11", Pins("F4")),
Subsignal("gn12", Pins("F3")),
Subsignal("gp12", Pins("G3")),
Subsignal("gn13", Pins("G5")),
Subsignal("gp13", Pins("H4")),
IOStandard("LVCMOS33"),
),
("j2", 0,
Subsignal("gn14", Pins("U17")),
Subsignal("gp14", Pins("U18")),
Subsignal("gn15", Pins("P16")),
Subsignal("gp15", Pins("N17")),
Subsignal("gn16", Pins("M17")),
Subsignal("gp16", Pins("N16")),
Subsignal("gn17", Pins("L17")),
Subsignal("gp17", Pins("L16")),
Subsignal("gn18", Pins("H17")),
Subsignal("gp18", Pins("H18")),
Subsignal("gn19", Pins("G18")),
Subsignal("gp19", Pins("F17")),
Subsignal("gn20", Pins("E17")),
Subsignal("gp20", Pins("D18")),
Subsignal("gn21", Pins("D17")),
Subsignal("gp21", Pins("C18")),
Subsignal("gn22", Pins("C15")),
Subsignal("gp22", Pins("B15")),
Subsignal("gn23", Pins("C17")),
Subsignal("gp23", Pins("B17")),
Subsignal("gn24", Pins("D16")),
Subsignal("gp24", Pins("C16")),
Subsignal("gn25", Pins("E14")),
Subsignal("gp25", Pins("D14")),
Subsignal("gn26", Pins("C13")),
Subsignal("gp26", Pins("B13")),
Subsignal("gn27", Pins("E13")),
Subsignal("gp27", Pins("D13")),
IOStandard("LVCMOS33"),
),
("lee_sdcard", 0,
Subsignal("clk", Pins("C16")), # GP24
Subsignal("cmd", Pins("B17"), Misc("PULLMODE=UP")), # GP23
# Subsignal("data", Pins("J3 H1 K1 K2"), Misc("PULLMODE=UP")),
# Subsignal("cd", Pins("N5")),
# Subsignal("wp", Pins("P5")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
# Others
("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
("ext0p", 0, Pins("B11"), IOStandard("LVCMOS33")),
("ext1p", 0, Pins("A10"), IOStandard("LVCMOS33")),
]
_io_1_7 = [
# SDCard
("spisdcard", 0,
Subsignal("clk", Pins("J1")),
Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("clk", Pins("J1")),
Subsignal("cmd", Pins("J3"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
_io_2_0 = [
# SDCard
("spisdcard", 0,
Subsignal("clk", Pins("H2")),
Subsignal("mosi", Pins("J1"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins("K2"), Misc("PULLMODE=UP")),
Subsignal("miso", Pins("J3"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("clk", Pins("H2")),
Subsignal("cmd", Pins("J1"), Misc("PULLMODE=UP")),
Subsignal("data", Pins("J3 H1 K1 K2"), Misc("PULLMODE=UP")),
Subsignal("cd", Pins("N5")),
Subsignal("wp", Pins("P5")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", **kwargs):
assert device in ["LFE5U-12F", "LFE5U-25F", "LFE5U-45F", "LFE5U-85F"]
assert revision in ["1.7", "2.0"]
_io = _io_common + {"1.7": _io_1_7, "2.0": _io_2_0}[revision]
LatticePlatform.__init__(self, device + "-6BG381C", _io, toolchain=toolchain, **kwargs)
def create_programmer(self):
return UJProg()
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
| [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.UJProg",
"litex.build.lattice.LatticePlatform.__init__"
] | [((8936, 9028), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', "(device + '-6BG381C')", '_io'], {'toolchain': 'toolchain'}), "(self, device + '-6BG381C', _io, toolchain=\n toolchain, **kwargs)\n", (8960, 9028), False, 'from litex.build.lattice import LatticePlatform\n'), ((9073, 9081), 'litex.build.lattice.programmer.UJProg', 'UJProg', ([], {}), '()\n', (9079, 9081), False, 'from litex.build.lattice.programmer import UJProg\n'), ((9128, 9171), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (9155, 9171), False, 'from litex.build.lattice import LatticePlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2014-2019 <NAME> <<EMAIL>>
# Copyright (c) 2013-2014 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
import importlib
from migen import *
from litex.build.io import CRG
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
from litex_boards.platforms import tec0117
kB = 1024
mB = 1024*kB
class BaseSoC(SoCCore):
mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs):
platform = tec0117.Platform()
# SoC can have littel a bram, as a treat
kwargs["integrated_sram_size"] = 2048*2
kwargs["integrated_rom_size"] = 0
# Set CPU variant / reset address
kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on TEC0117",
ident_version = True,
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = CRG(
platform.request(platform.default_clk_name),
~platform.request('rst'),
)
# SPI Flash --------------------------------------------------------------------------------
self.add_spi_flash(mode="1x", dummy_cycles=8)
# Add ROM linker region --------------------------------------------------------------------
self.bus.add_region("rom", SoCRegion(
origin = self.mem_map["spiflash"] + bios_flash_offset,
size = 8*mB,
linker = True)
)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq)
self.add_csr("leds")
# Flash --------------------------------------------------------------------------------------------
def flash(offset, path):
from spiflash.serialflash import SerialFlashManager
platform = tec0117.Platform()
flash = platform.request("spiflash", 0)
bus = platform.request("spiflash", 1)
module = Module()
module.comb += [
flash.clk.eq(bus.clk),
flash.cs_n.eq(bus.cs_n),
flash.mosi.eq(bus.mosi),
bus.miso.eq(flash.miso),
]
platform.build(module)
prog = platform.create_programmer()
prog.load_bitstream('build/impl/pnr/project.fs')
dev = SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2")
dev.TIMINGS['chip'] = (4, 60) # chip is too slow
print("Erasing flash...")
dev.erase(0, -1)
with open(path, 'rb') as f:
bios = f.read()
print("Programming flash...")
dev.write(offset, bios)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--bios-flash-offset", default=0x00000, help="BIOS offset in SPI Flash (0x00000 default)")
parser.add_argument("--flash", action="store_true", help="Flash BIOS")
parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)")
builder_args(parser)
soc_core_args(parser)
args = parser.parse_args()
soc= BaseSoC(
bios_flash_offset = args.bios_flash_offset,
sys_clk_freq = int(float(args.sys_clk_freq)),
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)
if args.flash:
flash(
args.bios_flash_offset,
os.path.join(builder.software_dir, "bios", "bios.bin"))
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"),
args.flash)
if __name__ == "__main__":
main()
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"litex.soc.integration.soc.SoCRegion"
] | [((2424, 2442), 'litex_boards.platforms.tec0117.Platform', 'tec0117.Platform', ([], {}), '()\n', (2440, 2442), False, 'from litex_boards.platforms import tec0117\n'), ((2841, 2898), 'spiflash.serialflash.SerialFlashManager.get_flash_device', 'SerialFlashManager.get_flash_device', (['"""ftdi://ftdi:2232/2"""'], {}), "('ftdi://ftdi:2232/2')\n", (2876, 2898), False, 'from spiflash.serialflash import SerialFlashManager\n'), ((3251, 3313), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX SoC on iCEBreaker"""'}), "(description='LiteX SoC on iCEBreaker')\n", (3274, 3313), False, 'import argparse\n'), ((712, 730), 'litex_boards.platforms.tec0117.Platform', 'tec0117.Platform', ([], {}), '()\n', (728, 730), False, 'from litex_boards.platforms import tec0117\n'), ((1808, 1900), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'origin': "(self.mem_map['spiflash'] + bios_flash_offset)", 'size': '(8 * mB)', 'linker': '(True)'}), "(origin=self.mem_map['spiflash'] + bios_flash_offset, size=8 * mB,\n linker=True)\n", (1817, 1900), False, 'from litex.soc.integration.soc import SoCRegion\n'), ((4239, 4293), 'os.path.join', 'os.path.join', (['builder.software_dir', '"""bios"""', '"""bios.bin"""'], {}), "(builder.software_dir, 'bios', 'bios.bin')\n", (4251, 4293), False, 'import os\n'), ((4403, 4466), 'os.path.join', 'os.path.join', (['builder.gateware_dir', '"""impl"""', '"""pnr"""', '"""project.fs"""'], {}), "(builder.gateware_dir, 'impl', 'pnr', 'project.fs')\n", (4415, 4466), False, 'import os\n')] |
from litex.soc.integration.soc_core import mem_decoder
from liteeth.phy.model import LiteEthPHYModel
from liteeth.core.mac import LiteEthMAC
from targets.utils import csr_map_update
from targets.sim.base import BaseSoC
class NetSoC(BaseSoC):
# FIXME: The sim seems to require ethphy at 18 and ethmac at 19!?
# csr_peripherals = (
# "ethphy",
# "ethmac",
# )
# csr_map_update(BaseSoC.csr_map, csr_peripherals)
csr_map = {
"ethphy": 18,
"ethmac": 19,
}
csr_map.update(BaseSoC.csr_map)
mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
mem_map.update(BaseSoC.mem_map)
def __init__(self, *args, **kwargs):
# Need a larger integrated ROM on or1k to fit the BIOS with TFTP support.
if 'integrated_rom_size' not in kwargs and kwargs.get('cpu_type', 'lm32') != 'lm32':
kwargs['integrated_rom_size'] = 0x10000
BaseSoC.__init__(self, *args, **kwargs)
self.submodules.ethphy = LiteEthPHYModel(self.platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.add_interupt("ethmac")
def configure_iprange(self, iprange):
iprange = [int(x) for x in iprange.split(".")]
while len(iprange) < 4:
iprange.append(0)
# Our IP address
self._configure_ip("LOCALIP", iprange[:-1]+[50])
# IP address of tftp host
self._configure_ip("REMOTEIP", iprange[:-1]+[100])
def _configure_ip(self, ip_type, ip):
for i, e in enumerate(ip):
s = ip_type + str(i + 1)
s = s.upper()
self.add_constant(s, e)
SoC = NetSoC
| [
"litex.soc.integration.soc_core.mem_decoder"
] | [((930, 969), 'targets.sim.base.BaseSoC.__init__', 'BaseSoC.__init__', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (946, 969), False, 'from targets.sim.base import BaseSoC\n'), ((1083, 1176), 'liteeth.core.mac.LiteEthMAC', 'LiteEthMAC', ([], {'phy': 'self.ethphy', 'dw': '(32)', 'interface': '"""wishbone"""', 'endianness': 'self.cpu.endianness'}), "(phy=self.ethphy, dw=32, interface='wishbone', endianness=self.\n cpu.endianness)\n", (1093, 1176), False, 'from liteeth.core.mac import LiteEthMAC\n'), ((1198, 1233), 'litex.soc.integration.soc_core.mem_decoder', 'mem_decoder', (["self.mem_map['ethmac']"], {}), "(self.mem_map['ethmac'])\n", (1209, 1233), False, 'from litex.soc.integration.soc_core import mem_decoder\n')] |
# This file is Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# License: BSD
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
_io = [
("afedat0", 0, Pins("AE25"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 1, Pins("AE26"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 2, Pins("AC22"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 3, Pins("AC23"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 4, Pins("AF24"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 5, Pins("AF25"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 6, Pins("AD25"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 7, Pins("AD26"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 8, Pins("AE23"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 9, Pins("AF23"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 10, Pins("AD23"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 11, Pins("AD24"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 12, Pins("AD21"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 13, Pins("AE21"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 14, Pins("AF19"), IOStandard("DIFF_SSTL18_II")),
("afedat0", 15, Pins("AF20"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 0, Pins("AE18"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 1, Pins("AF18"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 2, Pins("Y18"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 3, Pins("AA18"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 4, Pins("AE17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 5, Pins("AF17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 6, Pins("AA17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 7, Pins("AB17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 8, Pins("AC17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 9, Pins("AD17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 10, Pins("Y16"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 11, Pins("Y17"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 12, Pins("AB16"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 13, Pins("AC16"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 14, Pins("Y15"), IOStandard("DIFF_SSTL18_II")),
("afedat1", 15, Pins("AA15"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 0, Pins("U25"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 1, Pins("U26"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 2, Pins("V26"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 3, Pins("W26"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 4, Pins("AB26"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 5, Pins("AC26"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 6, Pins("W25"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 7, Pins("Y26"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 8, Pins("Y25"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 9, Pins("AA25"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 10, Pins("V24"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 11, Pins("W24"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 12, Pins("AA24"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 13, Pins("AB25"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 14, Pins("AA22"), IOStandard("DIFF_SSTL18_II")),
("afedat2", 15, Pins("AA23"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 0, Pins("W20"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 1, Pins("Y20"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 2, Pins("T19"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 3, Pins("U19"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 4, Pins("V19"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 5, Pins("W19"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 6, Pins("V18"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 7, Pins("W18"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 8, Pins("T14"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 9, Pins("T15"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 10, Pins("T17"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 11, Pins("T18"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 12, Pins("U15"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 13, Pins("U16"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 14, Pins("U14"), IOStandard("DIFF_SSTL18_II")),
("afedat3", 15, Pins("V14"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 0, Pins("P15"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 1, Pins("P16"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 2, Pins("N16"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 3, Pins("N17"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 4, Pins("R16"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 5, Pins("R17"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 6, Pins("P18"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 7, Pins("N18"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 8, Pins("K25"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 9, Pins("K26"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 10, Pins("M20"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 11, Pins("L20"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 12, Pins("L24"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 13, Pins("L25"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 14, Pins("M24"), IOStandard("DIFF_SSTL18_II")),
("afedat4", 15, Pins("M25"), IOStandard("DIFF_SSTL18_II")),
("spi_afe", 0,
Subsignal("sclk", Pins("K15"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("J14"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("J16"), IOStandard("LVCMOS33")),
Subsignal("cs_n", 0 ,Pins("K18"), IOStandard("LVCMOS33")),
Subsignal("cs_n", 1 ,Pins("K17"), IOStandard("LVCMOS33")),
Subsignal("cs_n", 2 ,Pins("M15"), IOStandard("LVCMOS33")),
Subsignal("cs_n", 3 ,Pins("H18"), IOStandard("LVCMOS33")),
),
("afe_cfg", 0,
Subsignal("fclkp",Pins("AB21"), IOStandard("DIFF_SSTL18_II")),
Subsignal("fclkm",Pins("AC21"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkp",Pins("AA20"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkm",Pins("AB20"), IOStandard("DIFF_SSTL18_II")),
),
("afe_cfg", 1,
Subsignal("fclkp",Pins("AC19"), IOStandard("DIFF_SSTL18_II")),
Subsignal("fclkm",Pins("AD19"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkp",Pins("AA19"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkm",Pins("AB19"), IOStandard("DIFF_SSTL18_II")),
),
("afe_cfg", 2,
Subsignal("fclkp",Pins("Y22"), IOStandard("DIFF_SSTL18_II")),
Subsignal("fclkm",Pins("Y23"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkp",Pins("U22"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkm",Pins("V22"), IOStandard("DIFF_SSTL18_II")),
),
("afe_cfg", 3,
Subsignal("fclkp",Pins("W21"), IOStandard("DIFF_SSTL18_II")),
Subsignal("fclkm",Pins("Y21"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkp",Pins("U21"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dclkm",Pins("V21"), IOStandard("DIFF_SSTL18_II")),
),
("muxen", 0, Pins("N16"), IOStandard("LVCMOS15")),
("muxen", 1, Pins("N17"), IOStandard("LVCMOS15")),
("muxen", 2, Pins("R16"), IOStandard("LVCMOS15")),
("muxen", 3, Pins("R17"), IOStandard("LVCMOS15")),
("muxen", 4, Pins("N19"), IOStandard("LVCMOS15")),
("muxen", 5, Pins("P23"), IOStandard("LVCMOS15")),
("muxen", 6, Pins("P24"), IOStandard("LVCMOS15")),
("muxen", 7, Pins("R20"), IOStandard("LVCMOS15")),
("muxen", 8, Pins("R21"), IOStandard("LVCMOS15")),
("muxen", 9, Pins("R25"), IOStandard("LVCMOS15")),
("refin_mux", 0, Pins("K25"), IOStandard("LVCMOS15")),
("ss_cfg_dat", 0, Pins("R15"), IOStandard("LVCMOS15")),
("gain_cs", 0, Pins("N26"), IOStandard("LVCMOS15")),
("bias_cs", 0, Pins("M26"), IOStandard("LVCMOS15")),
("offset_cfg", 0,
Subsignal("sclk", Pins("L22"), IOStandard("DIFF_SSTL18_II")),
Subsignal("sdat", Pins("M25"), IOStandard("DIFF_SSTL18_II")),
Subsignal("ld", Pins("M24"), IOStandard("DIFF_SSTL18_II")),
),
("offset", 0, Pins("K26"), IOStandard("LVCMOS15")),
("offset", 1, Pins("M20"), IOStandard("LVCMOS15")),
("offset", 2, Pins("L20"), IOStandard("LVCMOS15")),
("offset", 3, Pins("L24"), IOStandard("LVCMOS15")),
("offset", 4, Pins("L25"), IOStandard("LVCMOS15")),
("trim_cfg", 0,
Subsignal("sclk", Pins("T24"), IOStandard("DIFF_SSTL18_II")),
Subsignal("sdat", Pins("T25"), IOStandard("DIFF_SSTL18_II")),
Subsignal("ld", Pins("R26"), IOStandard("DIFF_SSTL18_II")),
),
("trim", 0, Pins("P26"), IOStandard("LVCMOS15")),
("trim", 1, Pins("T22"), IOStandard("LVCMOS15")),
("trim", 2, Pins("R22"), IOStandard("LVCMOS15")),
("trim", 3, Pins("T23"), IOStandard("LVCMOS15")),
("trim", 4, Pins("R23"), IOStandard("LVCMOS15")),
("sled", 0, Pins("AD5"), IOStandard("LVCMOS15")),
("sled", 1, Pins("AE5"), IOStandard("LVCMOS15")),
("sled", 2, Pins("V9"), IOStandard("LVCMOS15")),
("gpiled", 0, Pins("AF2"), IOStandard("LVCMOS15")),
("lemo", 0,
Subsignal("gpi", Pins("AA4")),
Subsignal("gpo", Pins("AB4")),
IOStandard("LVCMOS33"),
),
("phy", 0,
Subsignal("mdio", Pins("AB2")),
Subsignal("mdc", Pins("AC2")),
IOStandard("LVCMOS33"),
),
("brdy", 0,
Subsignal("brdy0", Pins("AE3")),
Subsignal("brdy1", Pins("AF3")),
IOStandard("LVCMOS33"),
),
("dma", 0,
Subsignal("en", Pins("AC3")),
Subsignal("bsy", Pins("AD3")),
IOStandard("LVCMOS33"),
),
("control", 0,
Subsignal("eth_cs", Pins("AB1")),
Subsignal("cpld_cs", Pins("AC1")),
Subsignal("rd", Pins("Y1")),
Subsignal("wr", Pins("AD1")),
Subsignal("nwait", Pins("AE1")),
Subsignal("cpld_irq", Pins("AE2")),
IOStandard("LVCMOS33"),
),
("stm", 0,
Subsignal("ca", Pins(
"V1 W1 W5 W4 V3 V2 V6 W6 W3 Y3 U7 V7"),
IOStandard("LVCMOS15")),
Subsignal("cd", Pins("AF5 AF4 AC4 AD4 Y7 AA7 Y6 Y5"
"V8 W8 AA5 AB5 Y8 AA8 AB6 AC6"),
IOStandard("LVCMOS15")),
),
("dbg", 0, Pins("D3 C3 F3 E3 C2 B2 A3 A2"
"C1 B1 F2 E2 E1 D1 G2 G1"), IOStandard("LVCMOS15")),
("clk0", 0,
Subsignal("clk_p", Pins("G5"), IOStandard("DIFF_SSTL18_II")),
Subsignal("clk_n", Pins("F5"), IOStandard("DIFF_SSTL18_II")),
),
("clk62_5", 0, Pins("AA4"), IOStandard("LVCMOS15")),
("pll", 0,
Subsignal("pll_sclk", Pins("C18"), IOStandard("SSTL18_II")),
Subsignal("pll_sdat", Pins("D19"), IOStandard("SSTL18_II")),
Subsignal("pll_pdn", Pins("E20"), IOStandard("SSTL18_II")),
Subsignal("pll_status", Pins("D20"), IOStandard("SSTL18_II")),
Subsignal("pll_ld", Pins("E22"), IOStandard("SSTL18_II")),
),
("cdr", 0,
Subsignal("cdr_p", Pins("D4"), IOStandard("DIFF_SSTL18_II")),
Subsignal("cdr_n", Pins("C4"), IOStandard("DIFF_SSTL18_II")),
Subsignal("sfp_scl", Pins("B20"), IOStandard("SSTL18_II")),
Subsignal("sfp_sda", Pins("A20"), IOStandard("SSTL18_II")),
Subsignal("f_sfp_tx_fault", Pins("C21"), IOStandard("SSTL18_II")),
Subsignal("f_sfp_los", Pins("B21"), IOStandard("SSTL18_II")),
Subsignal("f_cdr_lol", Pins("B22"), IOStandard("SSTL18_II")),
Subsignal("f_cdr_los", Pins("A22"), IOStandard("SSTL18_II")),
),
("ddram", 0,
Subsignal("a", Pins(
"T2 R2 U2 U1 P6 P5 T5 R5 U6",
"P8 R7 R6 T8 T7"),
IOStandard("SSTL18_II")),
Subsignal("ba", Pins("K1 J1 L3"), IOStandard("SSTL18_II")),
Subsignal("ras_n", Pins("H2"), IOStandard("SSTL18_II")),
Subsignal("cas_n", Pins("M2"), IOStandard("SSTL18_II")),
Subsignal("we_n", Pins("N3"), IOStandard("SSTL18_II")),
Subsignal("dm", Pins("N1 M1"), IOStandard("SSTL18_II")),
Subsignal("dq", Pins(
"N6 N7 K5 L5 L7 M7 J3 K3"), IOStandard("SSTL18_II"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("M4"), IOStandard("DIFF_SSTL18_II")),
Subsignal("dqs_n", Pins("L4"), IOStandard("DIFF_SSTL18_II")),
Subsignal("clk_p", Pins("R3"), IOStandard("DIFF_SSTL18_II")),
Subsignal("clk_n", Pins("P3"), IOStandard("DIFF_SSTL18_II")),
Subsignal("cke", Pins("L2"), IOStandard("SSTL18_II")),
Subsignal("odt", Pins("H1"), IOStandard("SSTL18_II")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL18_II")),
Misc("SLEW=FAST"),
),
# Verify this!!! This is CPLD Reset
("cpu_reset", 0, Pins("Y2"), IOStandard("LVCMOS15")),
# Verify This!!!
("serial", 0,
Subsignal("tx", Pins("D3")),
Subsignal("rx", Pins("C3")),
IOStandard("LVCMOS33"),
),
("sfp_csr_i2c", 0,
Subsignal("scl", Pins("B20")),
Subsignal("sda", Pins("A20")),
IOStandard("LVCMOS25")),
("sfp_i2c", 0,
Subsignal("tx_f", Pins("E21")),
Subsignal("tx_d", Pins("D21")),
Subsignal("present", Pins("C22")),
Subsignal("rate_s", Pins("C23")),
Subsignal("los", Pins("B25")),
Subsignal("sda", Pins("A25")),
Subsignal("scl", Pins("A23")),
IOStandard("LVCMOS25")
),
("sfp_i2c", 1,
Subsignal("tx_f", Pins("B26")),
Subsignal("tx_d", Pins("C24")),
Subsignal("present", Pins("B24")),
Subsignal("rate_s", Pins("D23")),
Subsignal("los", Pins("D24")),
Subsignal("sda", Pins("C26")),
Subsignal("scl", Pins("A24")),
IOStandard("LVCMOS25")
),
("gtp_tx", 0,
Subsignal("p", Pins("AE7")),
Subsignal("n", Pins("AF7")),
IOStandard("LVCMOS25")
),
("gtp_rx", 0,
Subsignal("p", Pins("AE11")),
Subsignal("n", Pins("AF11")),
IOStandard("LVCMOS25")
),
("gtp_clk", 0,
Subsignal("p", Pins("AA11")),
Subsignal("n", Pins("AB11"))
),
("we",0, Pins("X")),
("rxinit_done",0,Pins("X")),
("link_ready",0, Pins("X")),
("trans_en",0, Pins("X")),
("reset",0, Pins("X")),
("write_clk", 0,
Subsignal("p", Pins("G5"), IOStandard("DIFF_SSTL18_II")),
Subsignal("n", Pins("F5"), IOStandard("DIFF_SSTL18_II")),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk62.5"
default_clk_period = 1e9/62.5e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg676-3", _io, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
def create_programmer(self):
return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4")
# def do_finalize(self, fragment):
# XilinxPlatform.do_finalize(self, fragment)
# try:
# self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
# except ConstraintError:
# pass
def load(self):
from litex.build.xilinx import VivadoProgrammer
prog=VivadoProgrammer()
prog.load_bitstream("build/top.bit")
# class Platform(XilinxPlatform):
# default_clk_name = "clk156"
# default_clk_period = 1e9/156.5e6
# def __init__(self):
# XilinxPlatform.__init__(self, "xc7a200t-fbg676-3", _io, toolchain="vivado")
# self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
# self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
# self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
# self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
# self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
# def create_programmer(self):
# return VivadoProgrammer()
# def do_finalize(self, fragment):
# XilinxPlatform.do_finalize(self, fragment)
# try:
# self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
# except ConstraintError:
# pass
# try:
# self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
# except ConstraintError:
# pass
# try:
# self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
# except ConstraintError:
# pass
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer"
] | [((14602, 14677), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg676-3"""', '_io'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg676-3', _io, toolchain='vivado')\n", (14625, 14677), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((15137, 15193), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {'flash_part': '"""n25q128-3.3v-spi-x1_x2_x4"""'}), "(flash_part='n25q128-3.3v-spi-x1_x2_x4')\n", (15153, 15193), False, 'from litex.build.xilinx import VivadoProgrammer\n'), ((15534, 15552), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (15550, 15552), False, 'from litex.build.xilinx import VivadoProgrammer\n')] |
#!/usr/bin/env python3
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
import os
import argparse
from migen import *
from litex_boards.platforms import colorlight_5a_75b, colorlight_5a_75e
from litex_boards.targets import colorlight_5a_75x
from litex.build.generic_platform import Pins
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from litex.soc.cores.spi_flash import ECP5SPIFlash
from litex.soc.integration.soc_core import (
SoCCore, soc_core_args, soc_core_argdict,
)
from litex.soc.integration.builder import (
Builder, builder_args, builder_argdict,
)
from litex.soc.interconnect import csr
from litex.soc.interconnect.csr import AutoCSR
from litedram.modules import M12L64322A
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litedram.frontend.dma import LiteDRAMDMAReader
from liteeth.common import convert_ip
from liteeth.core import LiteEthUDPIPCore
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from liteeth.phy.model import LiteEthPHYModel
from clockdiv3 import ClockDiv3
from hub75_multi_driver import Hub75MultiDriver
from hub75_controller import Hub75Controller
from row_filler import RowFiller
from mem_stream import MemStreamWriter
from udp_dram_writer import UdpDramWriter
from udp_wishbone_writer import UdpWishboneWriter
class _CRG(colorlight_5a_75x._CRG):
def __init__(self, *args, **kwargs):
super().__init__(*args, **kwargs)
# Add a sys/3 clock.
self.submodules.cd3 = ClockDiv3()
self.clock_domains.cd_sys_div3 = ClockDomain(reset_less=True)
self.comb += [
self.cd_sys_div3.clk.eq(self.cd3.out),
]
class Receiver75(SoCCore):
def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False,
with_etherbone=True, eth_ip="192.168.0.39", eth_phy=0,
use_internal_osc=True, sdram_rate="1:1", **kwargs):
if board == "5a-75b":
platform = colorlight_5a_75b.Platform(revision=revision)
elif board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
# SoCCore with integrated RAM
SoCCore.__init__(self, platform, int(sys_clk_freq),
ident = "Receiver75 on Colorlight " + board,
ident_version = True,
integrated_main_ram_size=0x1000,
**kwargs)
# CRG
self.submodules.crg = _CRG(
platform, sys_clk_freq,
use_internal_osc=use_internal_osc,
with_usb_pll=False,
with_rst=False,
sdram_rate=sdram_rate,
)
# SDRAM - not used directly by the CPU
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
sdram_cls = M12L64322A
self.add_sdram("sdram",
phy = self.sdrphy,
module = sdram_cls(sys_clk_freq, sdram_rate),
l2_cache_size = kwargs.get("l2_size", 1024),
with_soc_interconnect=False,
)
# CSR
class CSRS(Module, AutoCSR):
pass
self.submodules.hub75_soc = CSRS()
self.hub75_soc.mac_address = csr.CSRStorage(6*8, 0x10e2d5000000, name='mac_address')
self.hub75_soc.ip_address = csr.CSRStorage(4*8, convert_ip(eth_ip))
# Etherbone
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads = self.platform.request("eth_clocks", eth_phy),
pads = self.platform.request("eth", eth_phy),
tx_delay = 0e-9)
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
self.add_udp(phy=self.ethphy,
mac_address=self.hub75_soc.mac_address.storage,
ip_address=self.hub75_soc.ip_address.storage)
else:
self.add_etherbone(phy=self.ethphy,
mac_address=self.hub75_soc.mac_address.storage,
ip_address=self.hub75_soc.ip_address.storage)
# Hub75
conns = platform.constraint_manager.connector_manager.connector_table
_, _, _, _, _, _, _, a4, a0, a1, a2, a3, clk, lat, oen, _ = conns['j1']
j1r0, j1g0, j1b0, _, _, _, _, _ = conns['j1'][:8]
def get_rgbs(conn):
pins = conns[conn]
return Pins(*(pins[:3] + pins[4:7]))
platform.add_extension([
('hub75_addr', 0, Pins(a0, a1, a2, a3, a4)),
('hub75_clk', 0, Pins(clk)),
('hub75_lat', 0, Pins(lat)),
('hub75_oen', 0, Pins(oen)),
] + [
(f'hub75_j{i}', 0, get_rgbs(f'j{i}')) for i in range(1, 9)
])
hub75_driver = Hub75MultiDriver(
platform.request('hub75_addr'),
platform.request('hub75_clk'),
platform.request('hub75_lat'),
platform.request('hub75_oen'),
[
platform.request('hub75_j1'),
platform.request('hub75_j2'),
platform.request('hub75_j3'),
platform.request('hub75_j4'),
platform.request('hub75_j5'),
platform.request('hub75_j6'),
platform.request('hub75_j7'),
platform.request('hub75_j8'),
],
cd_read='sys_div3',
with_csr=True,
dbl_buf=True,
)
port = self.sdram.crossbar.get_port(data_width=64)
self.submodules.dma_reader = LiteDRAMDMAReader(port, 8)
self.submodules.writers = [
MemStreamWriter(mem.write)
for mem in hub75_driver.mems
]
row_filler = RowFiller(
self.dma_reader,
[w.sink for w in self.writers],
)
c = self.submodules.hub75_controller = Hub75Controller(
hub75_driver, row_filler,
with_csr=True,
)
if with_ethernet or with_etherbone:
# UDP -> DRAM
self.submodules.mem_streamer = UdpDramWriter(
self.sdram, self.ethcore.udp, 4343,
)
# UDP -> Wishbone
self.submodules.udp_wishbone_writer = UdpWishboneWriter(
self.bus, self.ethcore.udp, 4344,
)
# SPI flash for config
self.submodules.spiflash = ECP5SPIFlash(
pads = platform.request("spiflash"),
sys_clk_freq = sys_clk_freq,
spi_clk_freq = 5e6,
)
self.add_csr("spiflash")
def add_udp(self, name="etherbone", phy=None, phy_cd="eth",
mac_address=0x10e2d5000000,
ip_address="192.168.0.39"):
self.check_if_exists(name)
ethcore = LiteEthUDPIPCore(
phy = phy,
mac_address = mac_address,
ip_address = ip_address,
clk_freq = self.clk_freq,
with_icmp=False)
ethcore = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx",
"sys": phy_cd + "_rx"})(ethcore)
self.submodules.ethcore = ethcore
eth_rx_clk = getattr(phy, "crg", phy).cd_eth_rx.clk
eth_tx_clk = getattr(phy, "crg", phy).cd_eth_tx.clk
if not isinstance(phy, LiteEthPHYModel):
self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
class BiosBuilder(Builder):
def add_software_package(self, name, src_dir=None):
if name == 'bios':
src_dir = os.path.join(os.getcwd(), '../bios')
super().add_software_package(name, src_dir)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
parser.add_argument(
"--build",
action="store_true",
help="Build bitstream",
)
parser.add_argument(
"--board",
default="5a-75b",
help="Board type: 5a-75b (default) or 5a-75e",
)
parser.add_argument(
"--revision",
default="8.0",
help="Board revision",
)
parser.add_argument(
"--sys-clk-freq",
default=64e6,
help="System clock frequency (default: 64MHz)",
)
parser.add_argument(
"--eth-ip",
default="192.168.0.39",
help="Ethernet/Etherbone IP address (overwritten by config)",
)
parser.add_argument(
"--eth-phy",
default=0,
type=int,
help="Ethernet PHY: 0 (default) or 1",
)
parser.add_argument(
"--sdram-rate",
default="1:2",
help="SDRAM Rate: 1:1 Full Rate, 1:2 Half Rate",
)
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
# Override some defaults
parser.set_defaults(
cpu_type='serv',
uart_name='bridge',
)
args = parser.parse_args()
args_dict = soc_core_argdict(args)
soc = Receiver75(board=args.board, revision=args.revision,
sys_clk_freq=int(float(args.sys_clk_freq)),
with_ethernet=True,
with_etherbone=False,
eth_ip=args.eth_ip,
eth_phy=args.eth_phy,
use_internal_osc=True,
sdram_rate=args.sdram_rate,
**soc_core_argdict(args)
)
builder = BiosBuilder(soc, **builder_argdict(args))
if args.build:
builder.build(**trellis_argdict(args), run=args.build)
if __name__ == "__main__":
main()
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"litex.soc.interconnect.csr.CSRStorage",
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#
# This file is part of LiteDRAM.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
import re
from migen import *
from litex.build.sim import SimPlatform
from litex.build.sim.config import SimConfig
from litex.build.generic_platform import Pins, Subsignal
from litex.soc.interconnect.csr import CSRStorage, AutoCSR
from litedram.common import Settings, tXXDController
from litedram.phy.utils import Serializer, Deserializer, edge
# PHY ----------------------------------------------------------------------------------------------
class SimSerDesMixin:
"""Helper class for easier (de-)serialization to simulation pads."""
def ser(self, *, i, o, clkdiv, clk, name="", **kwargs):
assert len(o) == 1
kwargs = dict(i=i, i_dw=len(i), o=o, o_dw=1, clk=clk, clkdiv=clkdiv,
name=f"ser_{name}".strip("_"), **kwargs)
self.submodules += Serializer(**kwargs)
def des(self, *, i, o, clkdiv, clk, name="", **kwargs):
assert len(i) == 1
kwargs = dict(i=i, i_dw=1, o=o, o_dw=len(o), clk=clk, clkdiv=clkdiv,
name=f"des_{name}".strip("_"), **kwargs)
self.submodules += Deserializer(**kwargs)
# Platform -----------------------------------------------------------------------------------------
class SimPad(Settings):
def __init__(self, name, width, io=False):
self.set_attributes(locals())
class SimulationPads(Module):
"""Pads for simulation purpose
Tristate pads are simulated as separate input/output pins (name_i, name_o) and
an output-enable pin (name_oe). Output pins are to be driven byt the PHY and
input pins are to be driven by the DRAM simulator. An additional pin without
a suffix is created and this module will include logic to set this pin to the
actual value depending on the output-enable signal.
"""
def layout(self, **kwargs):
raise NotImplementedError("Simulation pads layout as a list of SimPad objects")
def __init__(self, **kwargs):
for pad in self.layout(**kwargs):
if pad.io:
o, i, oe = (f"{pad.name}_{suffix}" for suffix in ["o", "i", "oe"])
setattr(self, pad.name, Signal(pad.width))
setattr(self, o, Signal(pad.width, name=o))
setattr(self, i, Signal(pad.width, name=i))
setattr(self, oe, Signal(name=oe))
self.comb += If(getattr(self, oe),
getattr(self, pad.name).eq(getattr(self, o))
).Else(
getattr(self, pad.name).eq(getattr(self, i))
)
else:
setattr(self, pad.name, Signal(pad.width, name=pad.name))
class Clocks(dict):
"""Helper for definiting simulation clocks
Dictionary format is `{name: {"freq_hz": _, "phase_deg": _}, ...}`.
"""
def names(self):
return list(self.keys())
def add_io(self, io):
for name in self.names():
io.append((name + "_clk", 0, Pins(1)))
def add_clockers(self, sim_config):
for name, desc in self.items():
sim_config.add_clocker(name + "_clk", **desc)
class CRG(Module):
"""Clock & Reset Generator for Verilator-based simulation"""
def __init__(self, platform, clock_domains=None):
if clock_domains is None:
clock_domains = ["sys"]
elif isinstance(clock_domains, Clocks):
clock_domains = list(clock_domains.names())
# request() before creating clock_domains to avoid signal renaming problem
clock_domains = {name: platform.request(name + "_clk") for name in clock_domains}
self.clock_domains.cd_por = ClockDomain(reset_less=True)
for name in clock_domains.keys():
setattr(self.clock_domains, "cd_" + name, ClockDomain(name=name))
int_rst = Signal(reset=1)
self.sync.por += int_rst.eq(0)
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
for name, clk in clock_domains.items():
cd = getattr(self, "cd_" + name)
self.comb += cd.clk.eq(clk)
self.comb += cd.rst.eq(int_rst)
class Platform(SimPlatform):
def __init__(self, io, clocks: Clocks):
common_io = [
("sys_rst", 0, Pins(1)),
("serial", 0,
Subsignal("source_valid", Pins(1)),
Subsignal("source_ready", Pins(1)),
Subsignal("source_data", Pins(8)),
Subsignal("sink_valid", Pins(1)),
Subsignal("sink_ready", Pins(1)),
Subsignal("sink_data", Pins(8)),
),
]
clocks.add_io(common_io)
SimPlatform.__init__(self, "SIM", common_io + io)
# Logging ------------------------------------------------------------------------------------------
# Named regex group
def ng(name, regex):
return r"(?P<{}>{})".format(name, regex)
class SimLogger(Module, AutoCSR):
"""Logger for use in simulation
This module allows for easier message logging when running simulation designs.
The logger can be used from `comb` context so it the methods can be directly
used inside `FSM` code. It also provides logging levels that can be used to
filter messages, either by specifying the default `log_level` or in runtime
by driving to the `level` signal or using a corresponding CSR.
If `clk_freq` is provided, than the logger will prepend timestamps to the
messages (in picoseconds). This will work as long as the clock domain in which
this module operates is always running with a constant frequency. On the other
hand, if the frequency varies or the clock is sometimes disabled, `clk_freq_cd`
can be specified to select a different clock domain (`clk_freq` must specify
the frequecy of that new clock domain).
"""
# Allows to use Display inside FSM and to filter log messages by level (statically or dynamically)
DEBUG = 0
INFO = 1
WARN = 2
ERROR = 3
NONE = 4
# Regex pattern for parsing logs
LOG_PATTERN = re.compile(r"\[\s*{time} ps] \[{level}]\s*{msg}".format(
time = ng("time", r"[0-9]+"),
level = ng("level", r"DEBUG|INFO|WARN|ERROR"),
msg = ng("msg", ".*"),
))
def __init__(self, log_level=INFO, clk_freq=None, clk_freq_cd=None, with_csrs=False):
self.ops = []
self.level = Signal(reset=log_level, max=self.NONE + 1)
self.time_ps = None
if clk_freq is not None:
self.time_ps = Signal(64)
cnt = Signal(64)
sd_cnt = self.sync if clk_freq_cd is None else getattr(self.sync, clk_freq_cd)
sd_cnt += cnt.eq(cnt + 1)
self.comb += self.time_ps.eq(cnt * int(1e12/clk_freq))
if with_csrs:
self.add_csrs()
def debug(self, fmt, *args, **kwargs):
return self.log("[DEBUG] " + fmt, *args, level=self.DEBUG, **kwargs)
def info(self, fmt, *args, **kwargs):
return self.log("[INFO] " + fmt, *args, level=self.INFO, **kwargs)
def warn(self, fmt, *args, **kwargs):
return self.log("[WARN] " + fmt, *args, level=self.WARN, **kwargs)
def error(self, fmt, *args, **kwargs):
return self.log("[ERROR] " + fmt, *args, level=self.ERROR, **kwargs)
def log(self, fmt, *args, level=DEBUG, once=True):
cond = Signal()
if once: # make the condition be triggered only on rising edge
condition = edge(self, cond)
else:
condition = cond
self.ops.append((level, condition, fmt, args))
return cond.eq(1)
def add_csrs(self):
self._level = CSRStorage(len(self.level), reset=self.level.reset.value)
self.comb += self.level.eq(self._level.storage)
def do_finalize(self):
for level, cond, fmt, args in self.ops:
if self.time_ps is not None:
fmt = f"[%16d ps] {fmt}"
args = (self.time_ps, *args)
self.sync += If((level >= self.level) & cond, Display(fmt, *args))
def log_level_getter(log_level):
"""Parse logging level description
Log level can be presented in a simple form (e.g. `--log-level=DEBUG`) to specify
the same level for all modules, or can set different levels for different modules
e.g. `--log-level=all=INFO,data=DEBUG`.
"""
def get_level(name):
return getattr(SimLogger, name.upper())
if "=" not in log_level: # simple log_level, e.g. "INFO"
return lambda _: get_level(log_level)
# parse log_level in the per-module form, e.g. "--log-level=all=INFO,data=DEBUG"
per_module = dict(part.split("=") for part in log_level.strip().split(","))
return lambda module: get_level(per_module.get(module, per_module.get("all", None)))
# Simulator ----------------------------------------------------------------------------------------
class Timing(Module):
# slight modification of tXXDController
def __init__(self, t):
self.valid = Signal()
self.ready = Signal()
if t is None:
t = 0
if isinstance(t, Signal):
count = Signal.like(t)
else:
count = Signal(max=max(t, 2))
self._t = t
self._count = count
ready = Signal()
ready_reg = Signal()
self.comb += [
self.ready.eq(ready_reg | ready),
ready.eq((t == 0) & self.valid),
]
self.sync += \
If(self.valid,
If(t == 0,
ready_reg.eq(1)
).Else(
count.eq(t - 1),
If(t == 1,
ready_reg.eq(1)
).Else(
ready_reg.eq(0)
)
),
).Elif(~ready,
If(count > 1,
count.eq(count - 1),
),
If(count == 1,
ready_reg.eq(1)
)
)
def progress(self):
full = self._t
current = Signal.like(self._count)
self.comb += current.eq(full - self._count) # down-counting
return (current, full)
class PulseTiming(Module):
"""Timing monitor with pulse input/output
This module works like `tXXDController` with the following differences:
* countdown triggered by a low to high pulse on `trigger`
* `ready` is initially low, only after a trigger it can become high
* provides `ready_p` which is high only for 1 cycle when `ready` becomes high
* supports t values starting from 0, with t=0 `ready_p` will pulse in the same
cycle in which `trigger` is high
"""
def __init__(self, t):
self.trigger = Signal()
self.ready = Signal()
self.ready_p = Signal()
trigger_d = Signal()
triggered = Signal()
self.submodules.timing = timing = Timing(t)
self.sync += [
If(self.trigger, triggered.eq(1)),
trigger_d.eq(self.trigger),
]
self.comb += [
self.ready.eq((triggered & timing.ready) | ((t == 0) & self.trigger)),
self.ready_p.eq(reduce(or_, [
edge(self, self.ready),
(t == 0) & edge(self, self.trigger),
(t == 1) & edge(self, trigger_d),
])),
timing.valid.eq(edge(self, self.trigger)),
]
def progress(self):
return self.timing.progress()
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#
# This file is part of LiteX.
#
# Copyright (c) 2018-2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import sys
import subprocess
import shutil
from migen.fhdl.structure import _Fragment
from litex.build.generic_platform import *
from litex.build import tools
from litex.build.microsemi import common
# Helpers ------------------------------------------------------------------------------------------
def tcl_name(name):
return "{" + name + "}"
# IO Constraints (.pdc) ----------------------------------------------------------------------------
def _format_io_constraint(c):
if isinstance(c, Pins):
return "-pin_name {} ".format(c.identifiers[0])
elif isinstance(c, IOStandard):
return "-io_std {} ".format(c.name)
elif isinstance(c, Misc):
return "-RES_PULL {} ".format(c.misc)
else:
raise NotImplementedError
def _format_io_pdc(signame, pin, others):
fmt_c = [_format_io_constraint(c) for c in ([Pins(pin)] + others)]
r = "set_io "
r += "-port_name {} ".format(tcl_name(signame))
for c in ([Pins(pin)] + others):
r += _format_io_constraint(c)
r += "-fixed true "
r += "\n"
return r
def _build_io_pdc(named_sc, named_pc, build_name, additional_io_constraints):
pdc = ""
for sig, pins, others, resname in named_sc:
if len(pins) > 1:
for i, p in enumerate(pins):
pdc += _format_io_pdc(sig + "[" + str(i) + "]", p, others)
else:
pdc += _format_io_pdc(sig, pins[0], others)
pdc += "\n".join(additional_io_constraints)
tools.write_to_file(build_name + "_io.pdc", pdc)
# Placement Constraints (.pdc) ---------------------------------------------------------------------
def _build_fp_pdc(build_name, additional_fp_constraints):
pdc = "\n".join(additional_fp_constraints)
tools.write_to_file(build_name + "_fp.pdc", pdc)
# Project (.tcl) -----------------------------------------------------------------------------------
def _build_tcl(platform, sources, build_dir, build_name):
tcl = []
# Create project
tcl.append(" ".join([
"new_project",
"-location {./impl}",
"-name {}".format(tcl_name(build_name)),
"-project_description {}",
"-block_mode 0",
"-standalone_peripheral_initialization 0",
"-instantiate_in_smartdesign 1",
"-ondemand_build_dh 0",
"-use_enhanced_constraint_flow 1",
"-hdl {VERILOG}",
"-family {PolarFire}",
"-die {}",
"-package {}",
"-speed {}",
"-die_voltage {}",
"-part_range {}",
"-adv_options {}"
]))
die, package, speed = platform.device.split("-")
tcl.append(" ".join([
"set_device",
"-family {PolarFire}",
"-die {}".format(tcl_name(die)),
"-package {}".format(tcl_name(package)),
"-speed {}".format(tcl_name("-" + speed)),
# FIXME: common to all PolarFire devices?
"-die_voltage {1.0}",
"-part_range {EXT}",
"-adv_options {IO_DEFT_STD:LVCMOS 1.8V}",
"-adv_options {RESTRICTPROBEPINS:1}",
"-adv_options {RESTRICTSPIPINS:0}",
"-adv_options {TEMPR:EXT}",
"-adv_options {UNUSED_MSS_IO_RESISTOR_PULL:None}",
"-adv_options {VCCI_1.2_VOLTR:EXT}",
"-adv_options {VCCI_1.5_VOLTR:EXT}",
"-adv_options {VCCI_1.8_VOLTR:EXT}",
"-adv_options {VCCI_2.5_VOLTR:EXT}",
"-adv_options {VCCI_3.3_VOLTR:EXT}",
"-adv_options {VOLTR:EXT} "
]))
# Add sources
for filename, language, library, *copy in sources:
filename_tcl = "{" + filename + "}"
tcl.append("import_files -hdl_source " + filename_tcl)
# Set top level
tcl.append("set_root -module {}".format(tcl_name(build_name)))
# Copy init files FIXME: support for include path on LiberoSoC?
for file in os.listdir(build_dir):
if file.endswith(".init"):
tcl.append("file copy -- {} impl/synthesis".format(file))
# Import io constraints
tcl.append("import_files -io_pdc {}".format(tcl_name(build_name + "_io.pdc")))
# Import floorplanner constraints
tcl.append("import_files -fp_pdc {}".format(tcl_name(build_name + "_fp.pdc")))
# Import timing constraints
tcl.append("import_files -convert_EDN_to_HDL 0 -sdc {}".format(tcl_name(build_name + ".sdc")))
# Associate constraints with tools
tcl.append(" ".join(["organize_tool_files",
"-tool {SYNTHESIZE}",
"-file impl/constraint/{}.sdc".format(build_name),
"-module {}".format(build_name),
"-input_type {constraint}"
]))
tcl.append(" ".join(["organize_tool_files",
"-tool {PLACEROUTE}",
"-file impl/constraint/io/{}_io.pdc".format(build_name),
"-file impl/constraint/fp/{}_fp.pdc".format(build_name),
"-file impl/constraint/{}.sdc".format(build_name),
"-module {}".format(build_name),
"-input_type {constraint}"
]))
tcl.append(" ".join(["organize_tool_files",
"-tool {VERIFYTIMING}",
"-file impl/constraint/{}.sdc".format(build_name),
"-module {}".format(build_name),
"-input_type {constraint}"
]))
# Build flow
tcl.append("run_tool -name {CONSTRAINT_MANAGEMENT}")
tcl.append("run_tool -name {SYNTHESIZE}")
tcl.append("run_tool -name {PLACEROUTE}")
tcl.append("run_tool -name {GENERATEPROGRAMMINGDATA}")
tcl.append("run_tool -name {GENERATEPROGRAMMINGFILE}")
# Generate tcl
tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
# Timing Constraints (.sdc) ------------------------------------------------------------------------
def _build_timing_sdc(vns, clocks, false_paths, build_name, additional_timing_constraints):
sdc = []
for clk, period in sorted(clocks.items(), key=lambda x: x[0].duid):
sdc.append(
"create_clock -name {clk} -period " + str(period) +
" [get_nets {clk}]".format(clk=vns.get_name(clk)))
for from_, to in sorted(false_paths,
key=lambda x: (x[0].duid, x[1].duid)):
sdc.append(
"set_clock_groups "
"-group [get_clocks -include_generated_clocks -of [get_nets {from_}]] "
"-group [get_clocks -include_generated_clocks -of [get_nets {to}]] "
"-asynchronous".format(from_=from_, to=to))
# generate sdc
sdc += additional_timing_constraints
tools.write_to_file(build_name + ".sdc", "\n".join(sdc))
# Script -------------------------------------------------------------------------------------------
def _build_script(build_name, device):
if sys.platform in ("win32", "cygwin"):
script_ext = ".bat"
script_contents = "@echo off\nREM Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n\n"
copy_stmt = "copy"
fail_stmt = " || exit /b"
else:
script_ext = ".sh"
script_contents = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n"
copy_stmt = "cp"
fail_stmt = " || exit 1"
script_file = "build_" + build_name + script_ext
tools.write_to_file(script_file, script_contents,
force_unix=False)
return script_file
def _run_script(script):
if sys.platform in ["win32", "cygwin"]:
shell = ["cmd", "/c"]
else:
shell = ["bash"]
if subprocess.call(shell + [script]) != 0:
raise OSError("Subprocess failed")
# MicrosemiLiberoSoCPolarfireToolchain -------------------------------------------------------------
class MicrosemiLiberoSoCPolarfireToolchain:
attr_translate = {}
special_overrides = common.microsemi_polarfire_special_overrides
def __init__(self):
self.clocks = dict()
self.false_paths = set()
self.additional_io_constraints = []
self.additional_fp_constraints = []
self.additional_timing_constraints = []
def build(self, platform, fragment,
build_dir = "build",
build_name = "top",
run = False,
**kwargs):
# Create build directory
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)
# Finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)
# Generate verilog
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
top_file = build_name + ".v"
v_output.write(top_file)
platform.add_source(top_file)
# Generate design script file (.tcl)
_build_tcl(platform, platform.sources, build_dir, build_name)
# Generate design io constraints file (.pdc)
_build_io_pdc(named_sc, named_pc, build_name, self.additional_io_constraints)
# Generate design placement constraints file (.pdc)
_build_fp_pdc(build_name, self.additional_fp_constraints)
# Generate design timing constraints file (.sdc)
_build_timing_sdc(v_output.ns, self.clocks, self.false_paths, build_name,
self.additional_timing_constraints)
# Generate build script
script = _build_script(build_name, platform.device)
# Run
if run:
# Delete previous impl
if os.path.exists("impl"):
shutil.rmtree("impl")
_run_script(script)
os.chdir(cwd)
return v_output.ns
def add_period_constraint(self, platform, clk, period):
if clk in self.clocks:
if period != self.clocks[clk]:
raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
.format(self.clocks[clk], period))
self.clocks[clk] = period
def add_false_path_constraint(self, platform, from_, to):
if (to, from_) not in self.false_paths:
self.false_paths.add((from_, to))
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"litex.build.tools.get_litex_git_revision",
"litex.build.tools.write_to_file"
] | [((1615, 1663), 'litex.build.tools.write_to_file', 'tools.write_to_file', (["(build_name + '_io.pdc')", 'pdc'], {}), "(build_name + '_io.pdc', pdc)\n", (1634, 1663), False, 'from litex.build import tools\n'), ((1876, 1924), 'litex.build.tools.write_to_file', 'tools.write_to_file', (["(build_name + '_fp.pdc')", 'pdc'], {}), "(build_name + '_fp.pdc', pdc)\n", (1895, 1924), False, 'from litex.build import tools\n'), ((3928, 3949), 'os.listdir', 'os.listdir', (['build_dir'], {}), '(build_dir)\n', (3938, 3949), False, 'import os\n'), ((7199, 7266), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['script_file', 'script_contents'], {'force_unix': '(False)'}), '(script_file, script_contents, force_unix=False)\n', (7218, 7266), False, 'from litex.build import tools\n'), ((7457, 7490), 'subprocess.call', 'subprocess.call', (['(shell + [script])'], {}), '(shell + [script])\n', (7472, 7490), False, 'import subprocess\n'), ((8233, 8270), 'os.makedirs', 'os.makedirs', (['build_dir'], {'exist_ok': '(True)'}), '(build_dir, exist_ok=True)\n', (8244, 8270), False, 'import os\n'), ((8285, 8296), 'os.getcwd', 'os.getcwd', ([], {}), '()\n', (8294, 8296), False, 'import os\n'), ((8305, 8324), 'os.chdir', 'os.chdir', (['build_dir'], {}), '(build_dir)\n', (8313, 8324), False, 'import os\n'), ((9611, 9624), 'os.chdir', 'os.chdir', (['cwd'], {}), '(cwd)\n', (9619, 9624), False, 'import os\n'), ((9508, 9530), 'os.path.exists', 'os.path.exists', (['"""impl"""'], {}), "('impl')\n", (9522, 9530), False, 'import os\n'), ((6844, 6874), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (6872, 6874), False, 'from litex.build import tools\n'), ((7045, 7075), 'litex.build.tools.get_litex_git_revision', 'tools.get_litex_git_revision', ([], {}), '()\n', (7073, 7075), False, 'from litex.build import tools\n'), ((9548, 9569), 'shutil.rmtree', 'shutil.rmtree', (['"""impl"""'], {}), "('impl')\n", (9561, 9569), False, 'import shutil\n')] |
# This file is Copyright (c) 2015 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016-2019 <NAME> <<EMAIL>>
# This file is Copyright (c) 2018 <NAME> <<EMAIL>>
# This file is Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# License: BSD
"""Direct Memory Access (DMA) reader and writer modules."""
from migen import *
from litex.soc.interconnect import stream
from litedram.common import LiteDRAMNativePort
from litedram.frontend.axi import LiteDRAMAXIPort
# LiteDRAMDMAReader --------------------------------------------------------------------------------
class LiteDRAMDMAReader(Module):
"""Read data from DRAM memory.
For every address written to the sink, one DRAM word will be produced on
the source.
Parameters
----------
port : port
Port on the DRAM memory controller to read from (Native or AXI).
fifo_depth : int
How many request results the output FIFO can contain (and thus how many
read requests can be outstanding at once).
fifo_buffered : bool
Implement FIFO in Block Ram.
Attributes
----------
sink : Record("address")
Sink for DRAM addresses to be read.
source : Record("data")
Source for DRAM word results from reading.
rsv_level: Signal()
FIFO reservation level counter
"""
def __init__(self, port, fifo_depth=16, fifo_buffered=False):
self.sink = sink = stream.Endpoint([("address", port.address_width)])
self.source = source = stream.Endpoint([("data", port.data_width)])
# # #
# Native / AXI selection
is_native = isinstance(port, LiteDRAMNativePort)
is_axi = isinstance(port, LiteDRAMAXIPort)
if is_native:
(cmd, rdata) = port.cmd, port.rdata
elif is_axi:
(cmd, rdata) = port.ar, port.r
else:
raise NotImplementedError
# Request issuance -------------------------------------------------------------------------
request_enable = Signal()
request_issued = Signal()
if is_native:
self.comb += cmd.we.eq(0)
self.comb += [
cmd.addr.eq(sink.address),
cmd.valid.eq(sink.valid & request_enable),
sink.ready.eq(cmd.ready & request_enable),
request_issued.eq(cmd.valid & cmd.ready)
]
# FIFO reservation level counter -----------------------------------------------------------
# incremented when data is planned to be queued
# decremented when data is dequeued
data_dequeued = Signal()
self.rsv_level = rsv_level = Signal(max=fifo_depth+1)
self.sync += [
If(request_issued,
If(~data_dequeued, rsv_level.eq(self.rsv_level + 1))
).Elif(data_dequeued,
rsv_level.eq(rsv_level - 1)
)
]
self.comb += request_enable.eq(rsv_level != fifo_depth)
# FIFO -------------------------------------------------------------------------------------
fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)
self.submodules += fifo
self.comb += [
rdata.connect(fifo.sink, omit={"id", "resp"}),
fifo.source.connect(source),
data_dequeued.eq(source.valid & source.ready)
]
# LiteDRAMDMAWriter --------------------------------------------------------------------------------
class LiteDRAMDMAWriter(Module):
"""Write data to DRAM memory.
Parameters
----------
port : port
Port on the DRAM memory controller to write to (Native or AXI).
fifo_depth : int
How many requests the input FIFO can contain (and thus how many write
requests can be outstanding at once).
fifo_buffered : bool
Implement FIFO in Block Ram.
Attributes
----------
sink : Record("address", "data")
Sink for DRAM addresses and DRAM data word to be written too.
"""
def __init__(self, port, fifo_depth=16, fifo_buffered=False):
assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort))
self.sink = sink = stream.Endpoint([("address", port.address_width),
("data", port.data_width)])
# # #
# Native / AXI selection -------------------------------------------------------------------
is_native = isinstance(port, LiteDRAMNativePort)
is_axi = isinstance(port, LiteDRAMAXIPort)
if is_native:
(cmd, wdata) = port.cmd, port.wdata
elif is_axi:
(cmd, wdata) = port.aw, port.w
else:
raise NotImplementedError
# FIFO -------------------------------------------------------------------------------------
fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered)
self.submodules += fifo
if is_native:
self.comb += cmd.we.eq(1)
self.comb += [
cmd.addr.eq(sink.address),
cmd.valid.eq(fifo.sink.ready & sink.valid),
sink.ready.eq(fifo.sink.ready & cmd.ready),
fifo.sink.valid.eq(sink.valid & cmd.ready),
fifo.sink.data.eq(sink.data)
]
if is_native:
self.comb += wdata.we.eq(2**(port.data_width//8)-1)
if is_axi:
self.comb += wdata.strb.eq(2**(port.data_width//8)-1)
self.comb += [
wdata.valid.eq(fifo.source.valid),
fifo.source.ready.eq(wdata.ready),
wdata.data.eq(fifo.source.data)
]
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"litex.soc.interconnect.stream.SyncFIFO"
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#
# This file is part of LiteDRAM.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import filecmp
import unittest
from litex.build.tools import write_to_file
from litedram.init import get_sdram_phy_c_header, get_sdram_phy_py_header
def compare_with_reference(content, filename):
write_to_file(filename, content)
r = filecmp.cmp(filename, os.path.join("test", "reference", filename))
os.remove(filename)
return r
class TestInit(unittest.TestCase):
def test_sdr(self):
from litex.boards.targets.minispartan6 import BaseSoC
soc = BaseSoC()
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "sdr_init.h"), True)
self.assertEqual(compare_with_reference(py_header, "sdr_init.py"), True)
def test_ddr3(self):
from litex.boards.targets.kc705 import BaseSoC
soc = BaseSoC()
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "ddr3_init.h"), True)
self.assertEqual(compare_with_reference(py_header, "ddr3_init.py"), True)
def test_ddr4(self):
from litex.boards.targets.kcu105 import BaseSoC
soc = BaseSoC(max_sdram_size=0x4000000)
c_header = get_sdram_phy_c_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
py_header = get_sdram_phy_py_header(soc.sdram.controller.settings.phy, soc.sdram.controller.settings.timing)
self.assertEqual(compare_with_reference(c_header, "ddr4_init.h"), True)
self.assertEqual(compare_with_reference(py_header, "ddr4_init.py"), True)
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#!/usr/bin/env python3
from litex import RemoteClient
import time
wb = RemoteClient()
wb.open()
# --------------------------------------------------------------------
wb.regs.writer_start.write(0)
wb.regs.writer_reset.write(1)
time.sleep(10000 / 1e6)
wb.regs.writer_reset.write(0)
wb.write(0x20000000, 0xffffffff) # patttern
wb.write(0x21000000, 0xffffffff) # patttern
wb.write(0x22000000, 0xffffffff) # patttern
wb.write(0x23000000, 0xffffffff) # patttern
wb.write(0x24000000, 0x00000000) # offset
mem_range = 256 * 1024 * 1024 # bytes
mem_mask = (mem_range // 4 // 4) - 1
mem_count = mem_mask
wb.regs.writer_mem_mask.write(mem_mask) # memory range
wb.regs.writer_data_mask.write(0x00000000) # just pattern from address 0x0
wb.regs.writer_count.write(mem_count)
wb.regs.writer_start.write(1)
while True:
if wb.regs.writer_done.read():
break
else:
time.sleep(10000 / 1e6)
wb.regs.writer_start.write(0)
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 4 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 8 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 12 * 4 * 4, 16)]))
# FIXME: random
#off = 67108864 - 100
#wb.write(0x40000000 + off * 4, 0xffffefff)
# --------------------------------------------------------------------
import random
from datetime import datetime
offset = random.Random(datetime.now()).randrange(0x0, 256 * 1024 * 1024 - 32) # FIXME: Check corner case
print('offset: ' + str(offset) + ', expecting: ' + str((offset//16) * 16))
wb.write(0x40000000 + offset, wb.read(0x40000000 + offset) ^ 0x000010000)
# --------------------------------------------------------------------
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 0 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 4 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 8 * 4 * 4, 16)]))
#print('bist: ' + str(["0x{:08x}".format(w) for w in wb.read(0x40000000 + 12 * 4 * 4, 16)]))
wb.regs.reader_start.write(0)
wb.regs.reader_reset.write(1)
time.sleep(10000 / 1e6)
wb.regs.reader_reset.write(0)
# Expected pattern
wb.write(0x30000000, 0xffffffff) # patttern
wb.write(0x31000000, 0xffffffff) # patttern
wb.write(0x32000000, 0xffffffff) # patttern
wb.write(0x33000000, 0xffffffff) # patttern
wb.write(0x34000000, 0x00000000) # offset
wb.regs.reader_mem_mask.write(mem_mask) # memory range
wb.regs.reader_data_mask.write(0x00000000) # pattern range
wb.regs.reader_count.write(mem_count)
wb.regs.reader_start.write(1)
wb.regs.reader_start.write(0)
while True:
if wb.regs.reader_done.read():
break
else:
time.sleep(1000 / 1e6)
# FIXME: assert
# --------------------
ptr = wb.regs.reader_pointer.read()
print('ptr: 0x{:08x}'.format(ptr))
assert(ptr == offset//16)
print('pointer: 0x{:08x} : {:d}'.format(ptr, ptr * 4 * 4))
wb.close()
| [
"litex.RemoteClient"
] | [((73, 87), 'litex.RemoteClient', 'RemoteClient', ([], {}), '()\n', (85, 87), False, 'from litex import RemoteClient\n'), ((231, 260), 'time.sleep', 'time.sleep', (['(10000 / 1000000.0)'], {}), '(10000 / 1000000.0)\n', (241, 260), False, 'import time\n'), ((2253, 2282), 'time.sleep', 'time.sleep', (['(10000 / 1000000.0)'], {}), '(10000 / 1000000.0)\n', (2263, 2282), False, 'import time\n'), ((881, 910), 'time.sleep', 'time.sleep', (['(10000 / 1000000.0)'], {}), '(10000 / 1000000.0)\n', (891, 910), False, 'import time\n'), ((2838, 2866), 'time.sleep', 'time.sleep', (['(1000 / 1000000.0)'], {}), '(1000 / 1000000.0)\n', (2848, 2866), False, 'import time\n'), ((1524, 1538), 'datetime.datetime.now', 'datetime.now', ([], {}), '()\n', (1536, 1538), False, 'from datetime import datetime\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk200", 0,
Subsignal("p", Pins("R3"), IOStandard("DIFF_SSTL15")),
Subsignal("n", Pins("P3"), IOStandard("DIFF_SSTL15"))
),
("clk156", 0,
Subsignal("p", Pins("M21"), IOStandard("LVDS_25")),
Subsignal("n", Pins("M22"), IOStandard("LVDS_25"))
),
("cpu_reset", 0, Pins("U4"), IOStandard("SSTL15")),
# Leds
("user_led", 0, Pins("M26"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("T24"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("T25"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("R26"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("cts", Pins("V19")),
Subsignal("rts", Pins("W19")),
Subsignal("tx", Pins("U19")),
Subsignal("rx", Pins("T19")),
IOStandard("LVCMOS18")
),
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("U22")),
Subsignal("rx", Pins("U21")),
IOStandard("LVCMOS18")
),
("eth", 0,
Subsignal("rx_ctl", Pins("U14")),
Subsignal("rx_data", Pins("U17 V17 V16 V14")),
Subsignal("tx_ctl", Pins("T15")),
Subsignal("tx_data", Pins("U16 U15 T18 T17")),
Subsignal("rst_n", Pins("V18")),
Subsignal("mdc", Pins("W18")),
Subsignal("mdio", Pins("T14")),
Misc("SLEW=FAST"),
Drive(16),
IOStandard("LVCMOS18"),
),
# DDR3 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"M4 J3 J1 L4 K5 M7 K1 M6",
"H1 K3 N7 L5 L7 N6 L3 K2"),
IOStandard("SSTL15")),
Subsignal("ba", Pins("N1 M1 H2"), IOStandard("SSTL15")),
Subsignal("ras_n", Pins("P1"), IOStandard("SSTL15")),
Subsignal("cas_n", Pins("T4"), IOStandard("SSTL15")),
Subsignal("we_n", Pins("R1"), IOStandard("SSTL15")),
Subsignal("cs_n", Pins("T3"), IOStandard("SSTL15")),
Subsignal("dm", Pins("AC6 AC4 AA3 U7 G1 F3 G5 H9"),
IOStandard("SSTL15")),
Subsignal("dq", Pins(
"AB6 AA8 Y8 AB5 AA5 Y5 Y6 Y7",
"AF4 AF5 AF3 AE3 AD3 AC3 AB4 AA4",
"AC2 AB2 AF2 AE2 Y1 Y2 AC1 AB1",
"Y3 W3 W6 V6 W4 W5 W1 V1",
"G2 D1 E1 E2 F2 A2 A3 C2",
"C3 D3 A4 B4 C4 D4 D5 E5",
"F4 G4 K6 K7 K8 L8 J5 J6",
"G6 H6 F7 F8 G8 H8 D6 E6"),
IOStandard("SSTL15"),
Misc("IN_TERM=UNTUNED_SPLIT_50")),
Subsignal("dqs_p", Pins("V8 AD5 AD1 V3 C1 B5 J4 H7"),
IOStandard("DIFF_SSTL15")),
Subsignal("dqs_n", Pins("W8 AE5 AE1 V2 B1 A5 H4 G7"),
IOStandard("DIFF_SSTL15")),
Subsignal("clk_p", Pins("M2"), IOStandard("DIFF_SSTL15")),
Subsignal("clk_n", Pins("L2"), IOStandard("DIFF_SSTL15")),
Subsignal("cke", Pins("P4"), IOStandard("SSTL15")),
Subsignal("odt", Pins("R2"), IOStandard("SSTL15")),
Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15")),
Misc("SLEW=FAST"),
),
# PCIe
("pcie_x1", 0,
Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("F11")),
Subsignal("clk_n", Pins("E11")),
Subsignal("rx_p", Pins("D12")),
Subsignal("rx_n", Pins("C12")),
Subsignal("tx_p", Pins("D10")),
Subsignal("tx_n", Pins("C10"))
),
("pcie_x4", 0,
Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")),
Subsignal("clk_p", Pins("F11")),
Subsignal("clk_n", Pins("E11")),
Subsignal("rx_p", Pins("D12 B13 D14 B11")),
Subsignal("rx_n", Pins("C12 A13 C14 A11")),
Subsignal("tx_p", Pins("D10 B9 D8 B7")),
Subsignal("tx_n", Pins("C10 A9 C8 A7"))
),
# GTP RefClk
("gtp_refclk", 0,
Subsignal("p", Pins("AA13")),
Subsignal("n", Pins("AB13"))
),
# SFP
("sfp", 0,
Subsignal("txp", Pins("AC10")),
Subsignal("txn", Pins("AD10")),
Subsignal("rxp", Pins("AC12")),
Subsignal("rxn", Pins("AD12")),
),
("sfp_mgt_clk_sel0", 0, Pins("B26"), IOStandard("LVCMOS25")),
("sfp_mgt_clk_sel1", 0, Pins("C24"), IOStandard("LVCMOS25")),
("sfp_tx_disable_n", 0, Pins("R18"), IOStandard("LVCMOS33")),
("sfp_rx_los", 0, Pins("R23"), IOStandard("LVCMOS33")),
# Others
("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("HPC", {
"CLK0_M2C_N" : "C19",
"CLK0_M2C_P" : "D19",
"CLK1_M2C_N" : "H22",
"CLK1_M2C_P" : "H21",
"LA00_CC_N" : "C18",
"LA00_CC_P" : "D18",
"LA01_CC_N" : "E18",
"LA01_CC_P" : "E17",
"LA02_N" : "H15",
"LA02_P" : "H14",
"LA03_N" : "F17",
"LA03_P" : "G17",
"LA04_N" : "F19",
"LA04_P" : "F18",
"LA05_N" : "F15",
"LA05_P" : "G15",
"LA06_N" : "F20",
"LA06_P" : "G19",
"LA07_N" : "G16",
"LA07_P" : "H16",
"LA08_N" : "B17",
"LA08_P" : "C17",
"LA09_N" : "D16",
"LA09_P" : "E16",
"LA10_N" : "A18",
"LA10_P" : "A17",
"LA11_N" : "A19",
"LA11_P" : "B19",
"LA12_N" : "D20",
"LA12_P" : "E20",
"LA13_N" : "A20",
"LA13_P" : "B20",
"LA14_N" : "B21",
"LA14_P" : "C21",
"LA15_N" : "A22",
"LA15_P" : "B22",
"LA16_N" : "D21",
"LA16_P" : "E21",
"LA17_CC_N" : "J21",
"LA17_CC_P" : "K21",
"LA18_CC_N" : "G21",
"LA18_CC_P" : "G20",
"LA19_N" : "L14",
"LA19_P" : "M14",
"LA20_N" : "M17",
"LA20_P" : "M16",
"LA21_N" : "H19",
"LA21_P" : "J19",
"LA22_N" : "L18",
"LA22_P" : "L17",
"LA23_N" : "J20",
"LA23_P" : "K20",
"LA24_N" : "H18",
"LA24_P" : "J18",
"LA25_N" : "F22",
"LA25_P" : "G22",
"LA26_N" : "H24",
"LA26_P" : "J24",
"LA27_N" : "E23",
"LA27_P" : "F23",
"LA28_N" : "K23",
"LA28_P" : "K22",
"LA29_N" : "F24",
"LA29_P" : "G24",
"LA30_N" : "D25",
"LA30_P" : "E25",
"LA31_N" : "D26",
"LA31_P" : "E26",
"LA32_N" : "G26",
"LA32_P" : "H26",
"LA33_N" : "F25",
"LA33_P" : "G25",
"PRSNT_M2C_L" : "N16",
"PWR_GOOD_FLASH_RST_B": "P15"}
),
("XADC", {
"GPIO0" : "H17",
"GPIO1" : "E22",
"GPIO2" : "K18",
"GPIO3" : "L19",
"VAUX0_N" : "J16",
"VAUX0_P" : "K15",
"VAUX8_N" : "J15",
"VAUX8_P" : "J14",
}
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk156"
default_clk_period = 1e9/156.5e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a200t-fbg676-2", _io, _connectors, toolchain="vivado")
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 33]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]")
self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]")
def create_programmer(self):
return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk200", loose=True), 1e9/200e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:tx", loose=True), 1e9/125e6)
| [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((7513, 7605), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a200t-fbg676-2"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a200t-fbg676-2', _io, _connectors,\n toolchain='vivado')\n", (7536, 7605), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((8189, 8248), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft2232.cfg"""', '"""bscan_spi_xc7a200t.bit"""'], {}), "('openocd_xc7_ft2232.cfg', 'bscan_spi_xc7a200t.bit')\n", (8196, 8248), False, 'from litex.build.openocd import OpenOCD\n'), ((8295, 8337), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (8321, 8337), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2017-2018 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
from litex.build.generic_programmer import GenericProgrammer
from litex.build import tools
# LatticeProgrammer --------------------------------------------------------------------------------
class LatticeProgrammer(GenericProgrammer):
needs_bitreverse = False
def __init__(self, xcf_template):
self.xcf_template = xcf_template
def load_bitstream(self, bitstream_file):
xcf_file = bitstream_file.replace(".bit", ".xcf")
xcf_content = self.xcf_template.format(bitstream_file=bitstream_file)
tools.write_to_file(xcf_file, xcf_content)
self.call(["pgrcmd", "-infile", xcf_file], check=False)
# OpenOCDJTAGProgrammer --------------------------------------------------------------------------------
class OpenOCDJTAGProgrammer(GenericProgrammer):
def __init__(self, config, flash_proxy_basename=None):
GenericProgrammer.__init__(self, flash_proxy_basename)
self.config = config
def load_bitstream(self, bitstream_file):
config = self.find_config()
assert bitstream_file.endswith(".bit") or bitstream_file.endswith(".svf")
if bitstream_file.endswith(".bit"):
from litex.build.lattice.bit_to_svf import bit_to_svf
bit = bitstream_file
svf = bit.replace(".bit", ".svf")
bit_to_svf(bit=bit, svf=svf)
else:
svf = bitstream_file
self.call(["openocd", "-f", config, "-c", "transport select jtag; init; svf quiet progress \"{}\"; exit".format(svf)])
def flash(self, address, data, verify=True):
config = self.find_config()
flash_proxy = self.find_flash_proxy()
script = "; ".join([
"transport select jtag",
"target create ecp5.spi0.proxy testee -chain-position ecp5.tap",
"flash bank spi0 jtagspi 0 0 0 0 ecp5.spi0.proxy 0x32",
"init",
"svf quiet progress \"{}\"".format(flash_proxy),
"reset halt",
"flash probe spi0",
"flash write_image erase \"{0}\" 0x{1:x}".format(data, address),
"flash verify_bank spi0 \"{0}\" 0x{1:x}" if verify else "".format(data, address),
"exit"
])
self.call(["openocd", "-f", config, "-c", script])
# IceStormProgrammer -------------------------------------------------------------------------------
class IceStormProgrammer(GenericProgrammer):
needs_bitreverse = False
def flash(self, address, bitstream_file):
self.call(["iceprog", "-o", str(address), bitstream_file])
def load_bitstream(self, bitstream_file):
self.call(["iceprog", "-S", bitstream_file])
# IceSugarProgrammer -------------------------------------------------------------------------------
class IceSugarProgrammer(GenericProgrammer):
needs_bitreverse = False
def flash(self, address, bitstream_file):
self.call(["icesprog", "-o", str(address), bitstream_file])
def load_bitstream(self, bitstream_file):
self.call(["icesprog", bitstream_file])
# IceBurnProgrammer --------------------------------------------------------------------------------
class IceBurnProgrammer(GenericProgrammer):
def __init__(self, iceburn_path):
GenericProgrammer.__init__(self)
self.iceburn = iceburn_path
needs_bitreverse = False
def load_bitstream(self, bitstream_file):
self.call([self.iceburn, "-evw", bitstream_file])
# TinyFpgaBProgrammer ------------------------------------------------------------------------------
class TinyFpgaBProgrammer(GenericProgrammer):
needs_bitreverse = False
# The default flash address you probably want is 0x30000; the image at
# address 0 is for the bootloader.
def flash(self, address, bitstream_file):
self.call(["tinyfpgab", "-a", str(address), "-p",
bitstream_file])
# Force user image to boot if a user reset tinyfpga, the bootloader
# is active, and the user image need not be reprogrammed.
def boot(self):
self.call(["tinyfpgab", "-b"])
# TinyProgProgrammer -------------------------------------------------------------------------------
# Different bootloader protocol requires different application. In the basic
# case, command-line arguments are the same. Note that this programmer can
# also be used with TinyFPGA B2 if you have updated its bootloader.
class TinyProgProgrammer(GenericProgrammer):
needs_bitreverse = False
# You probably want to pass address="None" for this programmer
# unless you know what you're doing.
def flash(self, address, bitstream_file, user_data=False):
if address is None:
if not user_data:
# tinyprog looks at spi flash metadata to figure out where to
# program your bitstream.
self.call(["tinyprog", "-p", bitstream_file])
else:
# Ditto with user data.
self.call(["tinyprog", "-u", bitstream_file])
else:
# Provide override so user can program wherever they wish.
self.call(["tinyprog", "-a", str(address), "-p",
bitstream_file])
# Force user image to boot if a user reset tinyfpga, the bootloader
# is active, and the user image need not be reprogrammed.
def boot(self):
self.call(["tinyprog", "-b"])
# MyStormProgrammer --------------------------------------------------------------------------------
class MyStormProgrammer(GenericProgrammer):
def __init__(self, serial_port):
self.serial_port = serial_port
def load_bitstream(self, bitstream_file):
import serial
with serial.Serial(self.serial_port) as port:
with open(bitstream_file, "rb") as f:
port.write(f.read())
# UJProg -------------------------------------------------------------------------------------------
class UJProg(GenericProgrammer):
needs_bitreverse = False
def load_bitstream(self, bitstream_file):
self.call(["ujprog", bitstream_file])
# EcpDapProgrammer -------------------------------------------------------------------------------
class EcpDapProgrammer(GenericProgrammer):
"""ECPDAP allows you to program ECP5 FPGAs and attached SPI flash using CMSIS-DAP probes in JTAG mode.
You can get `ecpdap` here: https://github.com/adamgreig/ecpdap
"""
needs_bitreverse = False
def __init__(self, frequency=8_000_000):
self.frequency_khz = frequency // 1000
def flash(self, address, bitstream_file):
self.call(["ecpdap",
"flash", "write",
"--freq", str(self.frequency_khz),
"--offset", str(address),
bitstream_file
])
def load_bitstream(self, bitstream_file):
self.call(["ecpdap",
"program",
"--freq", str(self.frequency_khz),
bitstream_file
])
# EcpprogProgrammer -------------------------------------------------------------------------------
class EcpprogProgrammer(GenericProgrammer):
"""ecpprog allows you to program ECP5 FPGAs and attached SPI flash using FTDI based JTAG probes
You can get `ecpprog` here: https://github.com/gregdavill/ecpprog
"""
needs_bitreverse = False
def flash(self, address, bitstream_file):
self.call(["ecpprog", "-o", str(address), bitstream_file])
def load_bitstream(self, bitstream_file):
self.call(["ecpprog", "-S", bitstream_file])
| [
"litex.build.lattice.bit_to_svf.bit_to_svf",
"litex.build.tools.write_to_file",
"litex.build.generic_programmer.GenericProgrammer.__init__"
] | [((710, 752), 'litex.build.tools.write_to_file', 'tools.write_to_file', (['xcf_file', 'xcf_content'], {}), '(xcf_file, xcf_content)\n', (729, 752), False, 'from litex.build import tools\n'), ((1039, 1093), 'litex.build.generic_programmer.GenericProgrammer.__init__', 'GenericProgrammer.__init__', (['self', 'flash_proxy_basename'], {}), '(self, flash_proxy_basename)\n', (1065, 1093), False, 'from litex.build.generic_programmer import GenericProgrammer\n'), ((3412, 3444), 'litex.build.generic_programmer.GenericProgrammer.__init__', 'GenericProgrammer.__init__', (['self'], {}), '(self)\n', (3438, 3444), False, 'from litex.build.generic_programmer import GenericProgrammer\n'), ((1491, 1519), 'litex.build.lattice.bit_to_svf.bit_to_svf', 'bit_to_svf', ([], {'bit': 'bit', 'svf': 'svf'}), '(bit=bit, svf=svf)\n', (1501, 1519), False, 'from litex.build.lattice.bit_to_svf import bit_to_svf\n'), ((5866, 5897), 'serial.Serial', 'serial.Serial', (['self.serial_port'], {}), '(self.serial_port)\n', (5879, 5897), False, 'import serial\n')] |
from migen import Module, TSTriple, Cat
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
from litex.soc.integration.doc import ModuleDoc
from litex.build.generic_platform import Pins, Subsignal
class TouchPads(Module, AutoCSR):
touch_device = [
("touch_pads", 0,
Subsignal("t1", Pins("touch_pins:0")),
Subsignal("t2", Pins("touch_pins:1")),
Subsignal("t3", Pins("touch_pins:2")),
Subsignal("t4", Pins("touch_pins:3")),
)
]
def __init__(self, pads):
self.intro = ModuleDoc("""Fomu Touchpads
Fomu has four single-ended exposed pads on its side. These pads are designed
to be connected to some captouch block, or driven in a resistive touch mode
in order to get simple touchpad support.
This block simply provides CPU-controlled GPIO support for this block. It has
three registers which control the In, Out, and Output Enable functionality of
each of these pins.
""")
touch1 = TSTriple()
touch2 = TSTriple()
touch3 = TSTriple()
touch4 = TSTriple()
self.specials += touch1.get_tristate(pads.t1)
self.specials += touch2.get_tristate(pads.t2)
self.specials += touch3.get_tristate(pads.t3)
self.specials += touch4.get_tristate(pads.t4)
self.o = CSRStorage(4, description="Output values for pads 1-4")
self.oe = CSRStorage(4, description="Output enable control for pads 1-4")
self.i = CSRStatus(4, description="Input value for pads 1-4")
self.comb += [
touch1.o.eq(self.o.storage[0]),
touch2.o.eq(self.o.storage[1]),
touch3.o.eq(self.o.storage[2]),
touch4.o.eq(self.o.storage[3]),
touch1.oe.eq(self.oe.storage[0]),
touch2.oe.eq(self.oe.storage[1]),
touch3.oe.eq(self.oe.storage[2]),
touch4.oe.eq(self.oe.storage[3]),
self.i.status.eq(Cat(touch1.i, touch2.i, touch3.i, touch4.i))
]
| [
"litex.soc.integration.doc.ModuleDoc",
"litex.build.generic_platform.Pins",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus"
] | [((568, 1040), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""Fomu Touchpads\n\n Fomu has four single-ended exposed pads on its side. These pads are designed\n to be connected to some captouch block, or driven in a resistive touch mode\n in order to get simple touchpad support.\n\n This block simply provides CPU-controlled GPIO support for this block. It has\n three registers which control the In, Out, and Output Enable functionality of\n each of these pins.\n """'], {}), '(\n """Fomu Touchpads\n\n Fomu has four single-ended exposed pads on its side. These pads are designed\n to be connected to some captouch block, or driven in a resistive touch mode\n in order to get simple touchpad support.\n\n This block simply provides CPU-controlled GPIO support for this block. It has\n three registers which control the In, Out, and Output Enable functionality of\n each of these pins.\n """\n )\n', (577, 1040), False, 'from litex.soc.integration.doc import ModuleDoc\n'), ((1048, 1058), 'migen.TSTriple', 'TSTriple', ([], {}), '()\n', (1056, 1058), False, 'from migen import Module, TSTriple, Cat\n'), ((1076, 1086), 'migen.TSTriple', 'TSTriple', ([], {}), '()\n', (1084, 1086), False, 'from migen import Module, TSTriple, Cat\n'), ((1104, 1114), 'migen.TSTriple', 'TSTriple', ([], {}), '()\n', (1112, 1114), False, 'from migen import Module, TSTriple, Cat\n'), ((1132, 1142), 'migen.TSTriple', 'TSTriple', ([], {}), '()\n', (1140, 1142), False, 'from migen import Module, TSTriple, Cat\n'), ((1378, 1433), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(4)'], {'description': '"""Output values for pads 1-4"""'}), "(4, description='Output values for pads 1-4')\n", (1388, 1433), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((1452, 1515), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(4)'], {'description': '"""Output enable control for pads 1-4"""'}), "(4, description='Output enable control for pads 1-4')\n", (1462, 1515), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((1534, 1586), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['(4)'], {'description': '"""Input value for pads 1-4"""'}), "(4, description='Input value for pads 1-4')\n", (1543, 1586), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage\n'), ((325, 345), 'litex.build.generic_platform.Pins', 'Pins', (['"""touch_pins:0"""'], {}), "('touch_pins:0')\n", (329, 345), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((376, 396), 'litex.build.generic_platform.Pins', 'Pins', (['"""touch_pins:1"""'], {}), "('touch_pins:1')\n", (380, 396), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((427, 447), 'litex.build.generic_platform.Pins', 'Pins', (['"""touch_pins:2"""'], {}), "('touch_pins:2')\n", (431, 447), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((478, 498), 'litex.build.generic_platform.Pins', 'Pins', (['"""touch_pins:3"""'], {}), "('touch_pins:3')\n", (482, 498), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((2002, 2045), 'migen.Cat', 'Cat', (['touch1.i', 'touch2.i', 'touch3.i', 'touch4.i'], {}), '(touch1.i, touch2.i, touch3.i, touch4.i)\n', (2005, 2045), False, 'from migen import Module, TSTriple, Cat\n')] |
from migen import *
from litex.soc.interconnect.csr import AutoCSR, CSRStorage
class LEDCtrl(Module, AutoCSR):
def __init__(self, num, reset_value):
self._set = CSRStorage(num * 4, reset_value)
self.inputs = leds = Array(Record([('r', 1), ('g', 1), ('b', 1)]) for i in range(num))
self.outputs = leds = Array(Record([('r', 1), ('g', 1), ('b', 1)]) for i in range(num))
for i in range(num):
self.comb += If(self._set.storage[i*4 + 3],
self.outputs[i].r.eq(self._set.storage[i*4 + 0]),
self.outputs[i].g.eq(self._set.storage[i*4 + 1]),
self.outputs[i].b.eq(self._set.storage[i*4 + 2]),
).Else(
self.outputs[i].eq(self.inputs[i])
)
| [
"litex.soc.interconnect.csr.CSRStorage"
] | [((175, 207), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(num * 4)', 'reset_value'], {}), '(num * 4, reset_value)\n', (185, 207), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
("clk100", 0, Pins("L19"), IOStandard("LVCMOS33")),
("user_led", 0, Pins("F8"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("C8"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("A8"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("D9"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("F9"), IOStandard("LVCMOS33")),
("user_btn", 0, Pins("E8"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("B9"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("C9"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("E9"), IOStandard("LVCMOS33")),
("serial", 0,
Subsignal("tx", Pins("AB18")),
Subsignal("rx", Pins("AA18")),
IOStandard("LVCMOS33")
),
("serial", 1,
Subsignal("tx", Pins("AA20")),
Subsignal("rx", Pins("AB20")),
IOStandard("LVCMOS33")
),
# LPDDR4 (not 1.2V, uses 1.1V or 0.6V depending on J10 jumper)
("lpddr4", 0,
Subsignal("clk_p", Pins("Y3"), IOStandard("DIFF_SSTL12")),
Subsignal("clk_n", Pins("Y2"), IOStandard("DIFF_SSTL12")),
Subsignal("cke", Pins("N4"), IOStandard("SSTL12")),
Subsignal("odt", Pins("N5"), IOStandard("SSTL12")),
Subsignal("reset_n", Pins("P4"), IOStandard("SSTL12")),
Subsignal("cs", Pins("N3"), IOStandard("SSTL12")),
Subsignal("ca", Pins("L3 L5 AA4 AA3 AB3 AB2"), IOStandard("SSTL12")),
Subsignal("dq", Pins(
"L1 K2 K1 K3 R1 P2 P1 N2",
"W2 Y1 AA1 AB1 R2 T1 T3 U1"),
IOStandard("SSTL12_T_DCI")),
Subsignal("dqs_p", Pins("M2 U2"), IOStandard("DIFF_SSTL12")),
Subsignal("dqs_n", Pins("M1 V2"), IOStandard("DIFF_SSTL12")),
Subsignal("dmi", Pins("M3 W1"), IOStandard("SSTL12_T_DCI")),
Misc("SLEW=FAST"),
),
# RGMII Ethernet
("eth_ref_clk", 0, Pins("C12"), IOStandard("LVCMOS33")),
("eth_clocks", 0,
Subsignal("tx", Pins("E17")),
Subsignal("rx", Pins("C17")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("E16"), IOStandard("LVCMOS33")),
Subsignal("mdio", Pins("C14"), IOStandard("LVCMOS33")),
Subsignal("mdc", Pins("B17"), IOStandard("LVCMOS33")),
Subsignal("rx_ctl", Pins("A16"), IOStandard("LVCMOS33")),
Subsignal("rx_data", Pins("B16 A15 B15 A14"), IOStandard("LVCMOS33")),
Subsignal("tx_ctl", Pins("A13"), IOStandard("LVCMOS33")),
Subsignal("tx_data", Pins("B21 B20 A19 A18"), IOStandard("LVCMOS33")),
),
# HyperRAM
("hyperram", 0,
Subsignal("clk", Pins("AB15")), # clk_n AB16
Subsignal("rst_n", Pins("V17")),
Subsignal("dq", Pins("W15 AA15 AA14 W14 Y14 V15 Y16 W17")),
Subsignal("cs_n", Pins("AA16")),
Subsignal("rwds", Pins("Y17")),
IOStandard("LVCMOS33")
),
# SD Card
("sdcard", 0,
Subsignal("data", Pins("D20 D19 C22 D21"), Misc("PULLUP True")),
Subsignal("cmd", Pins("C20"), Misc("PULLUP True")),
Subsignal("clk", Pins("D22")),
Subsignal("cd", Pins("B22")),
Misc("SLEW=FAST"),
IOStandard("LVCMOS33"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk100"
default_clk_period = 1e9/100e6
def __init__(self, device="xc7k70tfbg484-1"):
XilinxPlatform.__init__(self, device, _io, toolchain="vivado")
self.toolchain.bitstream_commands = \
["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = \
["write_cfgmem -force -format bin -interface spix4 -size 16 "
"-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
def create_programmer(self):
return OpenOCD("openocd_xc7_ft4232.cfg", "bscan_spi_xc7k70t.bit")
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6)
| [
"litex.build.openocd.OpenOCD",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((3786, 3848), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', 'device', '_io'], {'toolchain': '"""vivado"""'}), "(self, device, _io, toolchain='vivado')\n", (3809, 3848), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((4219, 4277), 'litex.build.openocd.OpenOCD', 'OpenOCD', (['"""openocd_xc7_ft4232.cfg"""', '"""bscan_spi_xc7k70t.bit"""'], {}), "('openocd_xc7_ft4232.cfg', 'bscan_spi_xc7k70t.bit')\n", (4226, 4277), False, 'from litex.build.openocd import OpenOCD\n'), ((4324, 4366), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4350, 4366), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import unittest
from migen import *
from litex.soc.cores.icap import ICAP, ICAPBitstream
class TestICAP(unittest.TestCase):
def test_icap_command_reload(self):
def generator(dut):
yield dut.addr.eq(0x4)
yield dut.data.eq(0xf)
for i in range(16):
yield
yield dut.send.eq(1)
yield
yield dut.send.eq(0)
for i in range(256):
yield
dut = ICAP(with_csr=False, simulation=True)
clocks = {"sys": 10, "icap":20}
run_simulation(dut, generator(dut), clocks, vcd_name="icap.vcd")
def test_icap_bitstream_syntax(self):
dut = ICAPBitstream(simulation=True)
| [
"litex.soc.cores.icap.ICAPBitstream",
"litex.soc.cores.icap.ICAP"
] | [((587, 624), 'litex.soc.cores.icap.ICAP', 'ICAP', ([], {'with_csr': '(False)', 'simulation': '(True)'}), '(with_csr=False, simulation=True)\n', (591, 624), False, 'from litex.soc.cores.icap import ICAP, ICAPBitstream\n'), ((795, 825), 'litex.soc.cores.icap.ICAPBitstream', 'ICAPBitstream', ([], {'simulation': '(True)'}), '(simulation=True)\n', (808, 825), False, 'from litex.soc.cores.icap import ICAP, ICAPBitstream\n')] |
#!/usr/bin/env python3
from os import path
from itertools import cycle, islice, chain, count
from migen import *
from litex.soc.cores.uart import UARTWishboneBridge, UARTBone
from litex.soc.integration.builder import Builder
from litex.build.generic_platform import Subsignal, IOStandard, Pins
from litex_boards.targets.gsd_orangecrab import BaseSoC
from litescope import LiteScopeIO, LiteScopeAnalyzer
from litepuf import RingOscillator
from litepuf.oscillator import MetastableOscillator
from litepuf.random import RandomLFSR
def slicer():
slice_iter = cycle("ABCD")
for i in count(0):
for _ in range(4):
yield (i, next(slice_iter))
def ro_placer(num_chains, chain_length, x_start=4, y_start=11):
for chain in range(num_chains):
placement = [f"X{x_start+column}/Y{y_start+chain}/SLICE{slice_id}" for column, slice_id in islice(slicer(), chain_length)]
print(placement)
yield placement
class LiteScopeSoC(BaseSoC):
csr_map = {
"io": 16,
"analyzer": 17
}
csr_map.update(BaseSoC.csr_map)
def __init__(self):
sys_clk_freq = int(48e6)
BaseSoC.__init__(self, sys_clk_freq=sys_clk_freq, toolchain="trellis",
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False
)
# bridge
from valentyusb.usbcore.cpu import epfifo, dummyusb
from valentyusb.usbcore import io as usbio
usb_pads = self.platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
self.submodules.usb = dummyusb.DummyUsb(usb_iobuf, debug=True, vid=0x1209, pid=0x5af0)
self.add_wb_master(self.usb.debug_bridge.wishbone)
self.platform.add_source_dir(path.join(path.dirname(__file__), 'verilog/lattice_ecp5'))
self.platform.add_source(path.join(path.dirname(__file__), 'verilog/lfsr.v'))
self.platform.add_source(path.join(path.dirname(__file__), 'verilog/random.v'))
metastable = Signal(name_override="metastable")
metastable.attr.add(("keep", 1))
rand_out = Signal(8, name_override="lfsr_weak")
chain_out = Signal(name_override="chain_out")#, attr=set(["keep", ("noglobal", "1")]))
chain_out.attr.add(("keep", 1))
chain_out.attr.add(("noglobal", 1))
self.submodules.ro = RingOscillator(
[
"X20/Y20/SLICEA",
"X20/Y20/SLICEB",
"X20/Y20/SLICEC",
"X20/Y20/SLICED",
])
# Litescope IO
self.submodules.io = LiteScopeIO(8)
for i in range(7):#8
try:
self.comb += self.platform.request("user_led", i).eq(self.io.output[i])
except:
pass
# Litescope Analyzer
analyzer_groups = {}
self.specials += [
Instance("randomized_lfsr_weak",
i_clk=self.crg.cd_sys.clk,
i_rst=~self.platform.lookup_request("rst_n"),
o_out=rand_out,
o_metastable=metastable
),
]
oscillators = [RingOscillator(placement) for placement in ro_placer(4, 7, x_start=4, y_start=4)]
self.submodules.trng = trng = RandomLFSR(oscillators)
analyzer_groups[0] = [
rand_out,
metastable
]
analyzer_groups[1] = [
trng.word_ready,
trng.reset,
trng.word_o,
trng.metastable,
trng.oscillators_o,
trng.counter_rng,
trng.trng,
]
analyzer_signals = [
trng.metastable,
]
# analyzer
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth=2**16,
clock_domain="sys",
csr_csv="test/analyzer.csv")
soc = LiteScopeSoC()
builder = Builder(soc, csr_csv="test/csr.csv", csr_json="test/csr.json")
vns = builder.build(nowidelut=True, ignoreloops=True)
#
# Create csr and analyzer files
#
soc.finalize()
soc.do_exit(vns)
| [
"litex.soc.integration.builder.Builder"
] | [((3952, 4014), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'csr_csv': '"""test/csr.csv"""', 'csr_json': '"""test/csr.json"""'}), "(soc, csr_csv='test/csr.csv', csr_json='test/csr.json')\n", (3959, 4014), False, 'from litex.soc.integration.builder import Builder\n'), ((567, 580), 'itertools.cycle', 'cycle', (['"""ABCD"""'], {}), "('ABCD')\n", (572, 580), False, 'from itertools import cycle, islice, chain, count\n'), ((594, 602), 'itertools.count', 'count', (['(0)'], {}), '(0)\n', (599, 602), False, 'from itertools import cycle, islice, chain, count\n'), ((1154, 1297), 'litex_boards.targets.gsd_orangecrab.BaseSoC.__init__', 'BaseSoC.__init__', (['self'], {'sys_clk_freq': 'sys_clk_freq', 'toolchain': '"""trellis"""', 'cpu_type': 'None', 'csr_data_width': '(32)', 'with_uart': '(False)', 'with_timer': '(False)'}), "(self, sys_clk_freq=sys_clk_freq, toolchain='trellis',\n cpu_type=None, csr_data_width=32, with_uart=False, with_timer=False)\n", (1170, 1297), False, 'from litex_boards.targets.gsd_orangecrab import BaseSoC\n'), ((1548, 1604), 'valentyusb.usbcore.io.IoBuf', 'usbio.IoBuf', (['usb_pads.d_p', 'usb_pads.d_n', 'usb_pads.pullup'], {}), '(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)\n', (1559, 1604), True, 'from valentyusb.usbcore import io as usbio\n'), ((1635, 1696), 'valentyusb.usbcore.cpu.dummyusb.DummyUsb', 'dummyusb.DummyUsb', (['usb_iobuf'], {'debug': '(True)', 'vid': '(4617)', 'pid': '(23280)'}), '(usb_iobuf, debug=True, vid=4617, pid=23280)\n', (1652, 1696), False, 'from valentyusb.usbcore.cpu import epfifo, dummyusb\n'), ((2394, 2486), 'litepuf.RingOscillator', 'RingOscillator', (["['X20/Y20/SLICEA', 'X20/Y20/SLICEB', 'X20/Y20/SLICEC', 'X20/Y20/SLICED']"], {}), "(['X20/Y20/SLICEA', 'X20/Y20/SLICEB', 'X20/Y20/SLICEC',\n 'X20/Y20/SLICED'])\n", (2408, 2486), False, 'from litepuf import RingOscillator\n'), ((2628, 2642), 'litescope.LiteScopeIO', 'LiteScopeIO', (['(8)'], {}), '(8)\n', (2639, 2642), False, 'from litescope import LiteScopeIO, LiteScopeAnalyzer\n'), ((3316, 3339), 'litepuf.random.RandomLFSR', 'RandomLFSR', (['oscillators'], {}), '(oscillators)\n', (3326, 3339), False, 'from litepuf.random import RandomLFSR\n'), ((3785, 3888), 'litescope.LiteScopeAnalyzer', 'LiteScopeAnalyzer', (['analyzer_signals'], {'depth': '(2 ** 16)', 'clock_domain': '"""sys"""', 'csr_csv': '"""test/analyzer.csv"""'}), "(analyzer_signals, depth=2 ** 16, clock_domain='sys',\n csr_csv='test/analyzer.csv')\n", (3802, 3888), False, 'from litescope import LiteScopeIO, LiteScopeAnalyzer\n'), ((3196, 3221), 'litepuf.RingOscillator', 'RingOscillator', (['placement'], {}), '(placement)\n', (3210, 3221), False, 'from litepuf import RingOscillator\n'), ((1807, 1829), 'os.path.dirname', 'path.dirname', (['__file__'], {}), '(__file__)\n', (1819, 1829), False, 'from os import path\n'), ((1899, 1921), 'os.path.dirname', 'path.dirname', (['__file__'], {}), '(__file__)\n', (1911, 1921), False, 'from os import path\n'), ((1985, 2007), 'os.path.dirname', 'path.dirname', (['__file__'], {}), '(__file__)\n', (1997, 2007), False, 'from os import path\n')] |
#!/usr/bin/env python3
from litex.tools.litex_client import RemoteClient
wb = RemoteClient()
wb.open()
print("\nPWM")
#wb.write(0x82002800, 0xff)
#wb.write(0x82002810, 0xff)
#wb.write(0x8200280C, 0x40)
print("Enable 0x{:08X}".format(wb.read(0x82002800)))
print("Divider 0x{:08X}".format(wb.read(0x82002804) << 8 | wb.read(0x82002808)))
print("Period 0x{:08X}".format(wb.read(0x82002810)))
print("Width 0x{:08X}".format(wb.read(0x8200280C)))
print("Count 0x{:08X}".format(wb.read(0x82002814)))
print("Enable 0x{:08X}".format(wb.read(0x82003000)))
print("Divider 0x{:08X}".format(wb.read(0x82003004) << 8 | wb.read(0x82002808)))
print("Period 0x{:08X}".format(wb.read(0x82003010)))
print("Width 0x{:08X}".format(wb.read(0x8200300C)))
print("Count 0x{:08X}".format(wb.read(0x82003014)))
wb.close()
| [
"litex.tools.litex_client.RemoteClient"
] | [((79, 93), 'litex.tools.litex_client.RemoteClient', 'RemoteClient', ([], {}), '()\n', (91, 93), False, 'from litex.tools.litex_client import RemoteClient\n')] |
# Copyright (c) 2019-2020 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litex.soc.interconnect.csr import AutoCSR
from litex.soc.interconnect import wishbone
from migen import *
from migen.genlib.cdc import MultiReg
from hard_spi import HardSPISlave
# SPI Slave ----------------------------------------------------------------------------------------
# This module is a modified version of `litex.soc.cores.spi.SPISlave`
class SPISlave(Module):
"""4-wire SPI Slave
Provides a simple and minimal hardware SPI Slave with CPOL=0, CPHA=0 and build time configurable
data_width.
"""
pads_layout = [("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)]
def __init__(self, pads):
if pads is None:
pads = Record(self.pads_layout)
if not hasattr(pads, "cs_n"):
pads.cs_n = Signal()
self.pads = pads
self.start = Signal()
self.byte = Signal()
self.length = Signal(3)
self.done = Signal()
self.irq = Signal()
self.mosi = Signal(8)
self.miso = Signal(8)
self.cs = Signal()
# # #
clk = Signal()
cs = Signal()
mosi = Signal()
miso = Signal()
# IOs <--> Internal (input resynchronization) ----------------------------------------------
self.specials += [
MultiReg(pads.clk, clk),
MultiReg(~pads.cs_n, cs),
MultiReg(pads.mosi, mosi),
]
self.comb += pads.miso.eq(miso)
# Clock detection --------------------------------------------------------------------------
clk_d = Signal()
clk_rise = Signal()
clk_fall = Signal()
self.sync += clk_d.eq(clk)
self.comb += clk_rise.eq(clk & ~clk_d)
self.comb += clk_fall.eq(~clk & clk_d)
# Control FSM ------------------------------------------------------------------------------
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(cs,
self.start.eq(1),
NextValue(self.length, 0),
NextState("XFER")
).Else(
self.done.eq(1)
)
)
fsm.act("XFER",
If(~cs,
self.irq.eq(1),
NextState("IDLE")
),
NextValue(self.length, self.length + clk_fall)
)
byte = Signal()
self.comb += byte.eq(clk_fall & (self.length == 7))
self.sync += self.byte.eq(byte)
# Master In Slave Out (MISO) generation (generated on spi_clk falling edge) ----------------
miso_data = Signal(8)
self.sync += \
If(self.start | self.byte,
miso_data.eq(self.miso)
).Elif(cs & clk_fall,
miso_data.eq(Cat(Signal(), miso_data[:-1]))
)
self.comb += miso.eq(miso_data[-1])
# Master Out Slave In (MOSI) capture (captured on spi_clk rising edge) ---------------------
mosi_data = Signal(8)
self.sync += [
If(cs & clk_rise,
mosi_data.eq(Cat(mosi, mosi_data[:-1]))
),
If(byte, self.mosi.eq(mosi_data))
]
class SPIBridge(Module, AutoCSR, AutoDoc):
def __init__(self, spi_pads):
# Documentation
self.intro = ModuleDoc("SPI slave driver")
self.wishbone = bus = wishbone.Interface()
self.submodules.spi = spi = HardSPISlave(spi_pads)
spi_counter = Signal(4)
spi_dword_mosi = Signal(32)
spi_dword_miso = Signal(32)
self.sync += \
If(spi.start,
spi_counter.eq(0),
).Elif(spi.byte,
spi_counter.eq(spi_counter + 1),
spi_dword_mosi.eq(Cat(spi_dword_mosi[8:], spi.mosi)),
spi_dword_miso.eq(Cat(spi_dword_miso[8:], Signal(8))),
)
address = Signal(16)
address_hi = Signal(16)
command = Signal(8)
self.comb += spi.miso.eq(spi_dword_miso[:8])
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(spi.start, NextState("COMMAND"))
)
fsm.act("COMMAND",
If(spi.done,
NextState("IDLE")
).Else(
If(spi_counter == 1,
NextValue(command, spi_dword_mosi[-8:]),
),
If(spi_counter == 3,
NextValue(address, spi_dword_mosi[-16:]),
If(command == 0x03, NextState("READ"))
),
If((spi_counter == 7) and command == 0x02,
#NextValue(data, spi_dword_mosi),
NextState("WRITE"),
)
),
)
fsm.act("READ",
bus.cyc.eq(1),
bus.stb.eq(1),
bus.we.eq(0),
bus.adr.eq(Cat(address, address_hi)),
bus.sel.eq(2 ** len(bus.sel) - 1),
If(bus.ack,
NextValue(spi_dword_miso, bus.dat_r),
NextState("IDLE")
)
)
fsm.act("WRITE",
bus.cyc.eq(1),
bus.stb.eq(1),
bus.we.eq(1),
bus.adr.eq(Cat(address, address_hi)),
bus.dat_w.eq(spi_dword_mosi),
bus.sel.eq(2 ** len(bus.sel) - 1),
If(bus.ack,
NextState("IDLE")
)
) | [
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.integration.doc.ModuleDoc"
] | [((3498, 3527), 'litex.soc.integration.doc.ModuleDoc', 'ModuleDoc', (['"""SPI slave driver"""'], {}), "('SPI slave driver')\n", (3507, 3527), False, 'from litex.soc.integration.doc import AutoDoc, ModuleDoc\n'), ((3559, 3579), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {}), '()\n', (3577, 3579), False, 'from litex.soc.interconnect import wishbone\n'), ((3616, 3638), 'hard_spi.HardSPISlave', 'HardSPISlave', (['spi_pads'], {}), '(spi_pads)\n', (3628, 3638), False, 'from hard_spi import HardSPISlave\n'), ((1502, 1525), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pads.clk', 'clk'], {}), '(pads.clk, clk)\n', (1510, 1525), False, 'from migen.genlib.cdc import MultiReg\n'), ((1539, 1563), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['(~pads.cs_n)', 'cs'], {}), '(~pads.cs_n, cs)\n', (1547, 1563), False, 'from migen.genlib.cdc import MultiReg\n'), ((1577, 1602), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pads.mosi', 'mosi'], {}), '(pads.mosi, mosi)\n', (1585, 1602), False, 'from migen.genlib.cdc import MultiReg\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2020 <NAME> <<EMAIL>>
# Copyright (c) 2016 Tim 'mithro' Ansell <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import os
import argparse
import socket
from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord
from litex.tools.remote.etherbone import EtherboneReads, EtherboneWrites
from litex.tools.remote.etherbone import EtherboneIPC
from litex.tools.remote.csr_builder import CSRBuilder
# Remote Client ------------------------------------------------------------------------------------
class RemoteClient(EtherboneIPC, CSRBuilder):
def __init__(self, host="localhost", port=1234, base_address=0, csr_csv=None, csr_data_width=None, debug=False):
# If csr_csv set to None and local csr.csv file exists, use it.
if csr_csv is None and os.path.exists("csr.csv"):
csr_csv = "csr.csv"
# If valid csr_csv file found, build the CSRs.
if csr_csv is not None:
CSRBuilder.__init__(self, self, csr_csv, csr_data_width)
# Else if csr_data_width set to None, force to csr_data_width 32-bit.
elif csr_data_width is None:
csr_data_width = 32
self.host = host
self.port = port
self.debug = debug
self.base_address = base_address if base_address is not None else 0
def open(self):
if hasattr(self, "socket"):
return
self.socket = socket.create_connection((self.host, self.port), 5.0)
self.socket.settimeout(5.0)
def close(self):
if not hasattr(self, "socket"):
return
self.socket.close()
del self.socket
def read(self, addr, length=None, burst="incr"):
length_int = 1 if length is None else length
# Prepare packet
record = EtherboneRecord()
incr = (burst == "incr")
record.reads = EtherboneReads(addrs=[self.base_address + addr + 4*incr*j for j in range(length_int)])
record.rcount = len(record.reads)
# Send packet
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
self.send_packet(self.socket, packet)
# Receive response
packet = EtherbonePacket(self.receive_packet(self.socket))
packet.decode()
datas = packet.records.pop().writes.get_datas()
if self.debug:
for i, data in enumerate(datas):
print("read 0x{:08x} @ 0x{:08x}".format(data, self.base_address + addr + 4*i))
return datas[0] if length is None else datas
def write(self, addr, datas):
datas = datas if isinstance(datas, list) else [datas]
record = EtherboneRecord()
record.writes = EtherboneWrites(base_addr=self.base_address + addr, datas=[d for d in datas])
record.wcount = len(record.writes)
packet = EtherbonePacket()
packet.records = [record]
packet.encode()
self.send_packet(self.socket, packet)
if self.debug:
for i, data in enumerate(datas):
print("write 0x{:08x} @ 0x{:08x}".format(data, self.base_address + addr + 4*i))
# Utils --------------------------------------------------------------------------------------------
def reg2addr(reg):
bus = RemoteClient()
if hasattr(bus.regs, reg):
return getattr(bus.regs, reg).addr
else:
raise ValueError(f"Register {reg} not present, exiting.")
def dump_identifier(port):
bus = RemoteClient(port=port)
bus.open()
# On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
if hasattr(bus.bases, "pcie_phy"):
bus.base_address = -bus.mems.csr.base
fpga_identifier = ""
for i in range(256):
c = chr(bus.read(bus.bases.identifier_mem + 4*i) & 0xff)
fpga_identifier += c
if c == "\0":
break
print(fpga_identifier)
bus.close()
def dump_registers(port, filter=None):
bus = RemoteClient(port=port)
bus.open()
# On PCIe designs, CSR is remapped to 0 to limit BAR0 size.
if hasattr(bus.bases, "pcie_phy"):
bus.base_address = -bus.mems.csr.base
for name, register in bus.regs.__dict__.items():
if (filter is None) or filter in name:
print("0x{:08x} : 0x{:08x} {}".format(register.addr, register.read(), name))
bus.close()
def read_memory(port, addr, length):
bus = RemoteClient(port=port)
bus.open()
for offset in range(length//4):
print(f"0x{addr + 4*offset:08x} : 0x{bus.read(addr + 4*offset):08x}")
bus.close()
def write_memory(port, addr, data):
bus = RemoteClient(port=port)
bus.open()
bus.write(addr, data)
bus.close()
# Run ----------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LiteX Client utility.", formatter_class=argparse.ArgumentDefaultsHelpFormatter)
parser.add_argument("--port", default="1234", help="Host bind port.")
parser.add_argument("--ident", action="store_true", help="Dump SoC identifier.")
parser.add_argument("--regs", action="store_true", help="Dump SoC registers.")
parser.add_argument("--filter", default=None, help="Registers filter (to be used with --regs).")
parser.add_argument("--read", default=None, help="Do a MMAP Read to SoC bus (--read addr/reg).")
parser.add_argument("--write", default=None, nargs=2, help="Do a MMAP Write to SoC bus (--write addr/reg data).")
parser.add_argument("--length", default="4", help="MMAP access length.")
args = parser.parse_args()
port = int(args.port, 0)
if args.ident:
dump_identifier(port=port)
if args.regs:
dump_registers(port=port, filter=args.filter)
if args.read:
if isinstance(args.read, str):
addr = reg2addr(args.read)
else:
addr = int(args.read, 0)
read_memory(port=port, addr=addr, length=int(args.length, 0))
if args.write:
if isinstance(args.write[0], str):
addr = reg2addr(args.write[0])
else:
addr = int(args.write[0], 0)
write_memory(port=port, addr=addr, data=int(args.write[1], 0))
if __name__ == "__main__":
main()
| [
"litex.tools.remote.etherbone.EtherbonePacket",
"litex.tools.remote.etherbone.EtherboneRecord",
"litex.tools.remote.csr_builder.CSRBuilder.__init__",
"litex.tools.remote.etherbone.EtherboneWrites"
] | [((4883, 5003), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LiteX Client utility."""', 'formatter_class': 'argparse.ArgumentDefaultsHelpFormatter'}), "(description='LiteX Client utility.',\n formatter_class=argparse.ArgumentDefaultsHelpFormatter)\n", (4906, 5003), False, 'import argparse\n'), ((1494, 1547), 'socket.create_connection', 'socket.create_connection', (['(self.host, self.port)', '(5.0)'], {}), '((self.host, self.port), 5.0)\n', (1518, 1547), False, 'import socket\n'), ((1866, 1883), 'litex.tools.remote.etherbone.EtherboneRecord', 'EtherboneRecord', ([], {}), '()\n', (1881, 1883), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord\n'), ((2110, 2127), 'litex.tools.remote.etherbone.EtherbonePacket', 'EtherbonePacket', ([], {}), '()\n', (2125, 2127), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord\n'), ((2737, 2754), 'litex.tools.remote.etherbone.EtherboneRecord', 'EtherboneRecord', ([], {}), '()\n', (2752, 2754), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord\n'), ((2779, 2856), 'litex.tools.remote.etherbone.EtherboneWrites', 'EtherboneWrites', ([], {'base_addr': '(self.base_address + addr)', 'datas': '[d for d in datas]'}), '(base_addr=self.base_address + addr, datas=[d for d in datas])\n', (2794, 2856), False, 'from litex.tools.remote.etherbone import EtherboneReads, EtherboneWrites\n'), ((2918, 2935), 'litex.tools.remote.etherbone.EtherbonePacket', 'EtherbonePacket', ([], {}), '()\n', (2933, 2935), False, 'from litex.tools.remote.etherbone import EtherbonePacket, EtherboneRecord\n'), ((858, 883), 'os.path.exists', 'os.path.exists', (['"""csr.csv"""'], {}), "('csr.csv')\n", (872, 883), False, 'import os\n'), ((1016, 1072), 'litex.tools.remote.csr_builder.CSRBuilder.__init__', 'CSRBuilder.__init__', (['self', 'self', 'csr_csv', 'csr_data_width'], {}), '(self, self, csr_csv, csr_data_width)\n', (1035, 1072), False, 'from litex.tools.remote.csr_builder import CSRBuilder\n')] |
from enum import IntEnum, unique
from functools import reduce
from operator import or_, and_
from migen import *
from migen.genlib.coding import Decoder as OneHotDecoder
from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litedram.core.refresher import Refresher
@unique
class OpCode(IntEnum):
NOOP = 0b000
LOOP = 0b111
# (ras, cas, we)
ACT = 0b100
PRE = 0b101
REF = 0b110
ZQC = 0b001
READ = 0b010
@classmethod
def table(cls):
div = '+------+-------+\n'
t = ''
t += div
t += '+ Op + Value +\n'
t += div.replace('-', '=')
for op_code in cls:
t += '+ {:4} | 0b{:03b} +\n'.format(op_code.name, op_code.value)
t += div
t = t.rstrip()
return t
class Decoder(Module):
__doc__ = """
**Instruction decoder**
All instructions are 32-bit. The format of most instructions is the same,
except for the LOOP instruction, which has a constant TIMESLICE of 1.
NOOP with a TIMESLICE of 0 is a special case which is interpreted as
STOP instruction. When this instruction is encountered execution gets
finished imediatelly.
**NOTE:** TIMESLICE is the number of cycles the instruction will take. This
means that instructions other than NOOP that use TIMESLICE=0 are illegal
(although will silently be executed as having TIMESLICE=1).
**NOTE2:** LOOP instruction will *jump* COUNT times, meaning that the "code"
inside the loop will effectively be executed COUNT+1 times.
Op codes:
{op_codes}
Instruction format::
LSB MSB
dfi: OP_CODE | TIMESLICE | ADDRESS
noop: OP_CODE | TIMESLICE_NOOP
loop: OP_CODE | COUNT | JUMP
stop: <NOOP> | 0
Where ADDRESS depends on the DFI command and is one of::
LSB MSB
RANK | BANK | COLUMN
RANK | BANK | ROW
""".format(op_codes=OpCode.table())
# TODO: Load widths from .proto file
INSTRUCTION = 32
OP_CODE = 3
TIMESLICE = 6
ADDRESS = 23
TIMESLICE_NOOP = TIMESLICE + ADDRESS
LOOP_COUNT = 12
LOOP_JUMP = 17
def __init__(self, instruction, *, rankbits, bankbits, rowbits, colbits):
assert len(instruction) == self.INSTRUCTION
assert self.OP_CODE + self.TIMESLICE_NOOP == self.INSTRUCTION
assert self.OP_CODE + self.TIMESLICE + self.ADDRESS == self.INSTRUCTION
assert self.OP_CODE + self.LOOP_COUNT + self.LOOP_JUMP == self.INSTRUCTION
assert rankbits + bankbits + max(rowbits, colbits) <= self.ADDRESS, (rankbits + bankbits + max(rowbits, colbits), self.ADDRESS)
self.op_code = Signal(self.OP_CODE)
# DFI-mappable instructions
self.timeslice = Signal(self.TIMESLICE_NOOP)
self.address = Signal(self.ADDRESS) # TODO: NOOP could resuse it as timeslice
self.cas = Signal()
self.ras = Signal()
self.we = Signal()
self.dfi_bank = Signal(bankbits)
self.dfi_address = Signal(max(rowbits, colbits))
# Loop instruction
self.loop_count = Signal(self.LOOP_COUNT) # max 32K loops
self.loop_jump = Signal(self.LOOP_JUMP) # max jump by 16K instructions
# Stop instruction (NOOP with TIMESLICE=0)
self.stop = Signal()
tail = instruction[self.OP_CODE:]
self.comb += [
self.op_code.eq(instruction[:self.OP_CODE]),
If(self.op_code == OpCode.NOOP,
self.timeslice.eq(tail[:self.TIMESLICE_NOOP]),
).Else(
self.timeslice.eq(tail[:self.TIMESLICE]),
),
self.address.eq(tail[self.TIMESLICE:]),
self.loop_count.eq(tail[:self.LOOP_COUNT]),
self.loop_jump.eq(tail[self.LOOP_COUNT:]),
self.stop.eq((self.op_code == OpCode.NOOP) & (self.timeslice == 0)),
self.cas.eq(self.op_code[1]),
self.ras.eq(self.op_code[2]),
self.we.eq(self.op_code[0]),
self.dfi_bank.eq(self.address[rankbits:rankbits+bankbits]),
self.dfi_address.eq(self.address[rankbits+bankbits:]),
]
if rankbits:
self.dfi_rank = Signal(rankbits)
self.comb += self.dfi_bank.eq(self.address[:rankbits]),
class Encoder:
"""Helper for writing payloads"""
def __init__(self, bankbits, nranks=1):
self.nranks = nranks
self.bankbits = bankbits
class I:
"""Instuction specification without encoding the value yet"""
def __init__(self, op_code, **kwargs):
self.op_code = op_code
for k, v in kwargs.items():
setattr(self, k, v)
if op_code == OpCode.LOOP:
self._parts = [
(Decoder.OP_CODE, op_code),
(Decoder.LOOP_COUNT, kwargs['count']),
(Decoder.LOOP_JUMP, kwargs['jump']),
]
elif op_code == OpCode.NOOP:
self._parts = [
(Decoder.OP_CODE, op_code),
(Decoder.TIMESLICE_NOOP, kwargs['timeslice']),
]
else:
assert kwargs['timeslice'] != 0, 'Timeslice for instructions other than NOOP should be > 0'
no_address = [OpCode.REF] # PRE requires bank address
assert 'address' in kwargs or op_code in no_address, \
'{} instruction requires `address`'.format(op_code.name)
self._parts = [
(Decoder.OP_CODE, op_code),
(Decoder.TIMESLICE, kwargs['timeslice']),
(Decoder.ADDRESS, kwargs.get('address', 0)),
]
def __call__(self, target, **kwargs):
if isinstance(target, OpCode):
return self.encode(target, **kwargs)
elif isinstance(target, self.I):
assert len(kwargs) == 0, 'No kwargs expected for Encoder.I'
return self.encode_spec(target)
elif hasattr(target, '__iter__'):
assert len(kwargs) == 0, 'No kwargs expected for iterable'
return self.encode_payload(target)
raise TypeError('One of the following is expected: OpCode+kwargs, Encoder.I, list[Encoder.I]')
def encode(self, op_code, **kwargs):
return self.encode_spec(self.I(op_code, **kwargs))
def encode_spec(self, spec):
assert isinstance(spec, self.I)
instr = 0
n = 0
for width, val in spec._parts:
mask = 2**width - 1
instr |= (val & mask) << n
n += width
return instr
def encode_payload(self, payload):
return [self.encode_spec(i) for i in payload]
def address(self, *, rank=None, bank=0, row=None, col=None):
assert not (row is not None and col is not None)
if row is not None:
rowcol = row
elif col is not None:
rowcol = col
else:
rowcol = 0
address = bank & (2**self.bankbits - 1)
address |= (rowcol) << self.bankbits
if self.nranks > 1:
address <<= log2_int(self.nranks)
address |= rank
return address
@ResetInserter()
class Scratchpad(Module):
"""
Scratchpad memory filled with data from subsequent READ commands
"""
def __init__(self, mem, dfi):
assert mem.width == len(dfi.p0.rddata) * len(dfi.phases)
self.counter = Signal(max=mem.depth - 1)
self.overflow = Signal()
wr_port = mem.get_port(write_capable=True)
self.specials += wr_port
self.sync += [ # use sync for easier timing as we don't need comb here
wr_port.adr.eq(self.counter),
wr_port.dat_w.eq(Cat(*[p.rddata for p in dfi.phases])),
wr_port.we.eq(reduce(or_, [p.rddata_valid for p in dfi.phases])),
]
self.sync += [
If(wr_port.we,
If(self.counter == mem.depth - 1,
self.overflow.eq(1),
self.counter.eq(0),
).Else(
self.counter.eq(self.counter + 1)
)
)
]
class DFIExecutor(Module):
def __init__(self, dfi, decoder, rank_decoder):
self.phase = Signal(max=len(dfi.phases) - 1)
self.exec = Signal()
nranks = len(dfi.p0.cs_n)
for i, phase in enumerate(dfi.phases):
self.comb += [
# constant signals
phase.cke.eq(Replicate(1, nranks)),
phase.odt.eq(Replicate(1, nranks)), # FIXME: needs to be dynamically driven for multi-rank systems
phase.reset_n.eq(Replicate(1, nranks)),
# send the command on current phase
If((self.phase == i) & self.exec, # selected
phase.cas_n.eq(~decoder.cas),
phase.ras_n.eq(~decoder.ras),
phase.we_n .eq(~decoder.we),
phase.address.eq(decoder.dfi_address),
phase.bank.eq(decoder.dfi_bank),
phase.rddata_en.eq(decoder.op_code == OpCode.READ),
# chip select
If(decoder.op_code == OpCode.NOOP,
phase.cs_n.eq(Replicate(1, nranks)),
).Elif(decoder.op_code == OpCode.REF, # select all ranks on refresh
phase.cs_n.eq(0),
).Else(
phase.cs_n.eq(~rank_decoder.o),
),
).Else( # inactive
phase.cs_n.eq(Replicate(1, nranks)),
phase.cas_n.eq(1),
phase.ras_n.eq(1),
phase.we_n.eq(1),
)
]
class SyncableRefresher(Module):
# Refresher that can be stopped
def __init__(self, *args, **kwargs):
refresher = ResetInserter()(Refresher(*args, **kwargs))
self.submodules += refresher
self.reset = refresher.reset
self.cmd = refresher.cmd
class RefreshCounter(Module):
def __init__(self, dfi_phase, width=32):
self.counter = Signal(width)
self.refresh = Signal()
ref_cmd = dict(cs_n=0, cas_n=0, ras_n=0, we_n=1)
self.comb += self.refresh.eq(reduce(and_,
[getattr(dfi_phase, sig) == val for sig, val in ref_cmd.items()]))
self.sync += If(self.refresh, self.counter.eq(self.counter + 1))
class DFISwitch(Module, AutoCSR):
# Synchronizes disconnection of the MC to last REF/ZQC command sent by MC
# Refresher must provide `ce` signal
def __init__(self, with_refresh, dfii, refresher_reset):
self.wants_dfi = Signal()
self.dfi_ready = Signal()
self.dfi = dfii.ext_dfi
# Refresh is issued always on phase 0. Count refresh commands on DFII
# master (any refresh issued, both by MC and PayloadExecutor)
self.submodules.refresh_counter = RefreshCounter(dfii.master.phases[0])
# If non-zero, we must wait until exactly that refresh count
# Refresh counter is updated 1 cycle after refresh, so add +1 in the test
self.at_refresh = Signal.like(self.refresh_counter.counter, reset=0)
refresh_matches = (self.at_refresh == 0) | (self.at_refresh == self.refresh_counter.counter + 1)
self.submodules.fsm = fsm = FSM()
fsm.act("MEMORY-CONTROLLER",
If(self.wants_dfi,
If(with_refresh,
# FIXME: sometimes ZQCS needs to be sent after refresh, currently it will be missed
If(self.refresh_counter.refresh & refresh_matches,
NextState("PAYLOAD-EXECUTION")
)
).Else(
NextState("PAYLOAD-EXECUTION")
)
)
)
fsm.act("PAYLOAD-EXECUTION",
self.dfi_ready.eq(1),
dfii.ext_dfi_sel.eq(1),
If(~self.wants_dfi,
# Reset Refresher so that it starts counting tREFI from 0
refresher_reset.eq(1),
NextState("MEMORY-CONTROLLER")
)
)
def add_csrs(self):
self._refresh_count = CSRStatus(len(self.refresh_counter.counter), description=
"Count of all refresh commands issued (both by Memory Controller and Payload Executor)."
" Value is latched from internal counter on mode trasition: MC -> PE or by writing to"
" the `refresh_update` CSR."
)
self._at_refresh = CSRStorage(len(self.at_refresh), reset=0, description=
"If set to a value different than 0 the mode transition MC -> PE will be peformed only"
" when the value of this register matches the current refresh commands count."
)
self._refresh_update = CSR()
self._refresh_update.description = "Force an update of the `refresh_count` CSR."
self.comb += self.at_refresh.eq(self._at_refresh.storage)
# detect mode transition
pe_ongoing = self.fsm.ongoing("PAYLOAD-EXECUTION")
mc_ongoing = self.fsm.ongoing("MEMORY-CONTROLLER")
mc_ongoing_d = Signal()
self.sync += mc_ongoing_d.eq(mc_ongoing)
mc_to_pe = mc_ongoing_d & pe_ongoing
self.sync += If(mc_to_pe | self._refresh_update.re,
self._refresh_count.status.eq(self.refresh_counter.counter),
)
class PayloadExecutor(Module, AutoCSR, AutoDoc):
def __init__(self, mem_payload, mem_scratchpad, dfi_switch, *,
nranks, bankbits, rowbits, colbits, rdphase):
self.description = ModuleDoc("""
Executes the DRAM payload from memory
{}
""".format(Decoder.__doc__))
self.start = Signal()
self.executing = Signal()
self.ready = Signal()
self.program_counter = Signal(max=mem_payload.depth - 1)
self.loop_counter = Signal(Decoder.LOOP_COUNT)
self.idle_counter = Signal(Decoder.TIMESLICE_NOOP)
# Scratchpad
self.submodules.scratchpad = Scratchpad(mem_scratchpad, dfi_switch.dfi)
# Fetcher
# uses synchronious port, instruction is ready 1 cycle after fetch_address is asserted
assert mem_payload.width == Decoder.INSTRUCTION, \
'Wrong payload memory word width: {} vs {}'.format(mem_payload.width, Decoder.INSTRUCTION)
instruction = Signal(Decoder.INSTRUCTION)
fetch_address = Signal.like(self.program_counter)
payload_port = mem_payload.get_port(write_capable=False)
self.specials += payload_port
self.comb += [
payload_port.adr.eq(fetch_address),
instruction.eq(payload_port.dat_r),
]
# Decoder
rankbits = log2_int(nranks)
self.submodules.decoder = decoder = Decoder(
instruction, rankbits=rankbits, bankbits=bankbits, rowbits=rowbits, colbits=colbits)
self.submodules.rank_decoder = OneHotDecoder(nranks)
if rankbits:
self.comb += self.rank_decoder.i.eq(self.decoder.dfi_rank)
# Executor
self.submodules.dfi_executor = DFIExecutor(dfi_switch.dfi, self.decoder, self.rank_decoder)
self.submodules.fsm = FSM()
self.fsm.act("READY",
self.ready.eq(1),
If(self.start,
NextState("WAIT-DFI"),
)
)
self.fsm.act("WAIT-DFI",
self.scratchpad.reset.eq(1),
fetch_address.eq(0),
dfi_switch.wants_dfi.eq(1),
If(dfi_switch.dfi_ready,
NextValue(self.program_counter, 0),
NextState("RUN")
)
)
self.fsm.act("RUN",
self.executing.eq(1),
dfi_switch.wants_dfi.eq(1),
# Terminate after executing the whole program or when STOP instruction is encountered
If((self.program_counter == mem_payload.depth - 1) | decoder.stop,
NextState("READY")
),
# Execute instruction
If(decoder.op_code == OpCode.LOOP,
# If a loop instruction with count=0 is found it will be a NOOP
If(self.loop_counter != decoder.loop_count,
# Continue the loop
fetch_address.eq(self.program_counter - decoder.loop_jump),
NextValue(self.program_counter, fetch_address),
NextValue(self.loop_counter, self.loop_counter + 1),
).Else(
# Finish the loop
# Set loop_counter to 0 so that next loop instruction will start properly
fetch_address.eq(self.program_counter + 1),
NextValue(self.program_counter, fetch_address),
NextValue(self.loop_counter, 0),
),
).Else(
# DFI instruction
# Timeslice=0 should be illegal but we still consider it as =1
If((decoder.timeslice == 0) | (decoder.timeslice == 1),
fetch_address.eq(self.program_counter + 1),
NextValue(self.program_counter, fetch_address),
).Else(
# Wait in idle loop after sending the command
NextValue(self.idle_counter, decoder.timeslice - 2),
NextState("IDLE"),
),
# Send DFI command
self.dfi_executor.exec.eq(1),
If(decoder.cas & ~decoder.ras & ~decoder.we, # READ command
self.dfi_executor.phase.eq(rdphase),
).Else(
self.dfi_executor.phase.eq(0),
)
),
)
self.fsm.act("IDLE",
self.executing.eq(1),
dfi_switch.wants_dfi.eq(1),
If(self.idle_counter == 0,
fetch_address.eq(self.program_counter + 1),
NextValue(self.program_counter, fetch_address),
NextState("RUN"),
).Else(
NextValue(self.idle_counter, self.idle_counter - 1),
)
)
def add_csrs(self):
self._start = CSR()
# CSR does not take a description parameter so we must set it manually
self._start.description = "Writing to this register initializes payload execution"
self._status = CSRStatus(fields=[
CSRField("ready", description="Indicates that the executor is not running"),
CSRField("overflow", description="Indicates the scratchpad memory address counter"
" has overflown due to the number of READ commands sent during execution"),
], description="Payload executor status register")
self._read_count = CSRStatus(len(self.scratchpad.counter), description="Number of data"
" from READ commands that is stored in the scratchpad memory")
self.comb += [
self.start.eq(self._start.re),
self._status.fields.ready.eq(self.ready),
self._status.fields.overflow.eq(self.scratchpad.overflow),
self._read_count.status.eq(self.scratchpad.counter),
]
| [
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.csr.CSRField"
] | [((13070, 13075), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (13073, 13075), False, 'from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR\n'), ((15266, 15287), 'migen.genlib.coding.Decoder', 'OneHotDecoder', (['nranks'], {}), '(nranks)\n', (15279, 15287), True, 'from migen.genlib.coding import Decoder as OneHotDecoder\n'), ((18501, 18506), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (18504, 18506), False, 'from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR\n'), ((10136, 10162), 'litedram.core.refresher.Refresher', 'Refresher', (['*args'], {}), '(*args, **kwargs)\n', (10145, 10162), False, 'from litedram.core.refresher import Refresher\n'), ((8017, 8066), 'functools.reduce', 'reduce', (['or_', '[p.rddata_valid for p in dfi.phases]'], {}), '(or_, [p.rddata_valid for p in dfi.phases])\n', (8023, 8066), False, 'from functools import reduce\n'), ((18731, 18806), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""ready"""'], {'description': '"""Indicates that the executor is not running"""'}), "('ready', description='Indicates that the executor is not running')\n", (18739, 18806), False, 'from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR\n'), ((18820, 18984), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""overflow"""'], {'description': '"""Indicates the scratchpad memory address counter has overflown due to the number of READ commands sent during execution"""'}), "('overflow', description=\n 'Indicates the scratchpad memory address counter has overflown due to the number of READ commands sent during execution'\n )\n", (18828, 18984), False, 'from litex.soc.interconnect.csr import CSR, CSRStatus, CSRStorage, CSRField, AutoCSR\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2018-2020 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import logging
import math
from migen import Record
from litex.soc.integration.soc import colorer
logging.basicConfig(level=logging.INFO)
# Logging ------------------------------------------------------------------------------------------
def register_clkin_log(logger, clkin, freq):
logger.info("Registering {} {} of {}.".format(
colorer("Differential") if isinstance(clkin, Record) else colorer("Single Ended"),
colorer("ClkIn"),
colorer("{:3.2f}MHz".format(freq/1e6))
))
def create_clkout_log(logger, name, freq, margin, nclkouts):
logger.info("Creating {} of {} {}.".format(
colorer("ClkOut{} {}".format(nclkouts, name)),
colorer("{:3.2f}MHz".format(freq/1e6)),
"(+-{:3.2f}ppm)".format(margin*1e6),
))
def compute_config_log(logger, config):
log = "Config:\n"
length = 0
for name in config.keys():
if len(name) > length: length = len(name)
for name, value in config.items():
if "freq" in name or "vco" in name:
value = "{:3.2f}MHz".format(value/1e6)
if "phase" in name:
value = "{:3.2f}°".format(value)
log += "{}{}: {}\n".format(name, " "*(length-len(name)), value)
log = log[:-1]
logger.info(log)
# Helpers ------------------------------------------------------------------------------------------
def period_ns(freq):
return 1e9/freq
def clkdiv_range(start, stop, step=1):
start = float(start)
stop = float(stop)
step = float(step)
current = start
while current < stop:
yield int(current) if math.floor(current) == current else current
current += step
| [
"litex.soc.integration.soc.colorer"
] | [((219, 258), 'logging.basicConfig', 'logging.basicConfig', ([], {'level': 'logging.INFO'}), '(level=logging.INFO)\n', (238, 258), False, 'import logging\n'), ((557, 573), 'litex.soc.integration.soc.colorer', 'colorer', (['"""ClkIn"""'], {}), "('ClkIn')\n", (564, 573), False, 'from litex.soc.integration.soc import colorer\n'), ((466, 489), 'litex.soc.integration.soc.colorer', 'colorer', (['"""Differential"""'], {}), "('Differential')\n", (473, 489), False, 'from litex.soc.integration.soc import colorer\n'), ((524, 547), 'litex.soc.integration.soc.colorer', 'colorer', (['"""Single Ended"""'], {}), "('Single Ended')\n", (531, 547), False, 'from litex.soc.integration.soc import colorer\n'), ((1714, 1733), 'math.floor', 'math.floor', (['current'], {}), '(current)\n', (1724, 1733), False, 'import math\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# Modified for custom ecp5 board, <NAME>, 2021
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import OpenOCDJTAGProgrammer
import os
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk48", 0, Pins("L16"), IOStandard("LVCMOS33")),
("rst_n", 0, Pins("M16"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("A3"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("A4"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("rx", Pins("A2"), IOStandard("LVCMOS33")),
Subsignal("tx", Pins("B3"), IOStandard("LVCMOS33")),
),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("N8"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("T8"), IOStandard("LVCMOS33")),
Subsignal("miso", Pins("T7"), IOStandard("LVCMOS33")),
Subsignal("wp", Pins("M7"), IOStandard("LVCMOS33")),
Subsignal("hold", Pins("N7"), IOStandard("LVCMOS33")),
),
("spiflash4x", 0,
Subsignal("cs_n", Pins("N8"), IOStandard("LVCMOS33")),
Subsignal("dq", Pins("T8 T7 M7 N7"), IOStandard("LVCMOS33")),
),
("hyperram", 0,
Subsignal("clk_p", Pins("N5")),
Subsignal("clk_n", Pins("N6")),
Subsignal("rst_n", Pins("N3")),
Subsignal("dq", Pins("P4 R3 P5 T4 P6 R5 M5 M6")),
Subsignal("cs_n", Pins("R4")),
Subsignal("rwds", Pins("P3")),
IOStandard("LVCMOS18")
),
("usb_aux", 0,
Subsignal("d_p", Pins("M11")),
Subsignal("d_n", Pins("N11")),
Subsignal("pullup", Pins("P12")),
IOStandard("LVCMOS33")
),
("adc", 0,
Subsignal("cs_n", Pins("A15"), IOStandard("LVCMOS33")),
Subsignal("sck", Pins("A14"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("A13"), IOStandard("LVCMOS33")),
),
("dac", 0,
Subsignal("clr_n", Pins("B11"), IOStandard("LVCMOS33")),
Subsignal("sync_n", Pins("B10"), IOStandard("LVCMOS33")),
Subsignal("sclk", Pins("A10"), IOStandard("LVCMOS33")),
Subsignal("mosi", Pins("A12"), IOStandard("LVCMOS33")),
Subsignal("vout_en", Pins("A11"), IOStandard("LVCMOS33")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("PMOD1",
"None", # (no pin 0)
"K1", # 1
"J3", # 2
"F2", # 3
"E3", # 4
"None", # 5 GND
"None", # 6 VCCIO0
"K2", # 7
"K3", # 8
"E1", # 9
"F3", # 10
"None", # 11 GND
"None", # 12 VCCIO0
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk48"
default_clk_period = 1e9/48e6
def __init__(self, toolchain="trellis", **kwargs):
LatticePlatform.__init__(self, "LFE5U-25F-8BG256", _io, _connectors, toolchain=toolchain, **kwargs)
def request(self, *args, **kwargs):
return LatticePlatform.request(self, *args, **kwargs)
def create_programmer(self):
return OpenOCDJTAGProgrammer("openocd_evn_ecp5.cfg")
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk48", loose=True), 1e9/48e6)
| [
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.programmer.OpenOCDJTAGProgrammer",
"litex.build.lattice.LatticePlatform.request",
"litex.build.lattice.LatticePlatform.__init__"
] | [((3222, 3325), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', '"""LFE5U-25F-8BG256"""', '_io', '_connectors'], {'toolchain': 'toolchain'}), "(self, 'LFE5U-25F-8BG256', _io, _connectors,\n toolchain=toolchain, **kwargs)\n", (3246, 3325), False, 'from litex.build.lattice import LatticePlatform\n'), ((3378, 3424), 'litex.build.lattice.LatticePlatform.request', 'LatticePlatform.request', (['self', '*args'], {}), '(self, *args, **kwargs)\n', (3401, 3424), False, 'from litex.build.lattice import LatticePlatform\n'), ((3474, 3519), 'litex.build.lattice.programmer.OpenOCDJTAGProgrammer', 'OpenOCDJTAGProgrammer', (['"""openocd_evn_ecp5.cfg"""'], {}), "('openocd_evn_ecp5.cfg')\n", (3495, 3519), False, 'from litex.build.lattice.programmer import OpenOCDJTAGProgrammer\n'), ((3566, 3609), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (3593, 3609), False, 'from litex.build.lattice import LatticePlatform\n')] |
#
# This file is part of LiteDRAM.
#
# Copyright (c) 2020-2021 Antmicro <www.antmicro.com>
# SPDX-License-Identifier: BSD-2-Clause
from math import ceil
from operator import and_
from migen import *
from migen.genlib.misc import WaitTimer
from litex.soc.interconnect.csr import AutoCSR, CSR, CSRStatus, CSRStorage
from litedram.common import *
from litedram.phy.utils import chunks, bitpattern
from litedram.phy.dfi import Interface as DFIInterface
from litedram.phy.rpc.commands import DFIAdapter
class ShiftRegister(Module):
def __init__(self, n, i=None):
if i is None:
i = Signal()
assert len(i) == 1
self.i = i
self.sr = sr = Signal(n)
last = Signal.like(sr)
self.comb += sr.eq(Cat(i, last))
self.sync += last.eq(sr)
def __getitem__(self, key):
return self.sr[key]
class RPCPads:
_layout = [
("clk_p", 1),
("clk_n", 1),
("cs_n", 1),
("dqs_p", 1), # may be 2 (hardware option; 2-bit DQS strobes DB by bytes: [0:7], [8:15])
("dqs_n", 1), # may be 2
("stb", 1),
("db", 16),
]
def __init__(self, pads):
self.map(pads)
for pad, width in self._layout:
assert len(getattr(self, pad)) >= width, \
"Pad {} has width {} < {}".format(pad, len(getattr(self, pad)), width)
# reimplement if a specific mapping is needed
def map(self, pads):
for pad, _ in self._layout:
setattr(self, pad, getattr(pads, pad))
class BasePHY(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq, write_ser_latency, read_des_latency, phytype):
# TODO: pads groups for multiple chips
# pads = PHYPadsCombiner(pads)
if not isinstance(pads, RPCPads):
pads = RPCPads(pads)
self.pads = pads
self.memtype = memtype = "RPC"
self.nranks = nranks = 1
self.databits = databits = 16
self.addressbits = addressbits = 12
self.bankbits = bankbits = 2
self.nphases = nphases = 4
self.tck = tck = 1 / (nphases*sys_clk_freq)
# CSRs -------------------------------------------------------------------------------------
bitslip_cycles = 1
self._rst = CSRStorage()
self._dly_sel = CSRStorage(databits//8)
self._rdly_dq_bitslip_rst = CSR()
self._rdly_dq_bitslip = CSR()
self._reset_done = CSRStatus()
self._init_done = CSRStatus()
self._reset_fsm = CSR()
self._burst_stop = CSRStorage(reset=1)
# PHY settings -----------------------------------------------------------------------------
def get_cl(tck):
# FIXME: for testing it's easier to use CL=8; read/write will be on phase 3; max sys_clk_freq=100e6
return 8
# tck is for DDR frequency
f_to_cl = OrderedDict()
f_to_cl[533e6] = 3
f_to_cl[800e6] = 8
f_to_cl[1200e6] = 8
f_to_cl[1333e6] = 10
f_to_cl[1600e6] = 11
f_to_cl[1866e6] = 13
for f, cl in f_to_cl.items():
if tck >= 2/f:
return cl
raise ValueError(tck)
# RPC always has AL=1 and both read and write latencies are equal: RL=WL=AL+CL
al = 1
cwl = cl = get_cl(tck) + al
cl_sys_latency = get_sys_latency(nphases, cl)
cwl_sys_latency = get_sys_latency(nphases, cwl)
rdphase = get_sys_phase(nphases, cl_sys_latency, cl)
wrphase = get_sys_phase(nphases, cwl_sys_latency, cwl)
# Read latency
db_cmd_dly = 2 # (need 1 cycle to insert STB preamble + 1 more to always meet tCSS)
cmd_ser_dly = write_ser_latency
read_mux_dly = 1
bitslip_dly = bitslip_cycles
# Time until first data is available on DB
read_db_dly = db_cmd_dly + cmd_ser_dly + cl_sys_latency
# Time until data is deserialized (data present on 1ck signal)
read_db_des_dly = read_db_dly + read_des_latency
# Time until data is set on DFI (+1 because all data is present only on 2nd cycle)
read_dfi_dly = read_mux_dly + bitslip_dly + 1
# Final latency
read_latency = read_db_des_dly + read_dfi_dly
# Write latency for the controller. We must send 1 cycles of data mask before the
# data, and we serialize data over 2 sysclk cycles due to minimal BL=16, so we
# are writing in the 2 cycles following the cycle when we obtain data on DFI.
# Other PHYs can send everything in 1 sysclk. Because of this spcific delay, we
# have to increate tWR in the RPC SDRModule definition to meet tWR requirements.
# +1 cycle needed to insert CS before command
write_latency = cwl_sys_latency + 1
self.settings = PhySettings(
phytype = phytype,
memtype = memtype,
databits = databits,
dfi_databits = 4*databits,
nranks = nranks,
nphases = nphases,
rdphase = rdphase,
wrphase = wrphase,
cl = cl,
cwl = cwl,
read_latency = read_latency,
write_latency = write_latency,
bitslips = bitslip_cycles*2*2*nphases,
)
# DFI Interface ----------------------------------------------------------------------------
# minimal BL=16, which gives 16*16=256 bits; with 4 phases we need 16/4=4 data widths
dfi_params = dict(addressbits=addressbits, bankbits=bankbits, nranks=nranks,
databits=4*databits, nphases=nphases)
# Register DFI history (from newest to oldest), as we need to operate on 3 subsequent cycles
# hist[0] = dfi[N], hist[1] = dfi[N-1], ...
self.dfi = dfi = DFIInterface(**dfi_params)
dfi_hist = [dfi, DFIInterface(**dfi_params), DFIInterface(**dfi_params)]
self.sync += dfi_hist[0].connect(dfi_hist[1], omit={"rddata", "rddata_valid"})
self.sync += dfi_hist[1].connect(dfi_hist[2], omit={"rddata", "rddata_valid"})
# Serialization ----------------------------------------------------------------------------
# We have the following signals that have to be serialized:
# - CLK (O) - full-rate clock
# - CS (O) - chip select
# - STB (O) - serial commands, serial preamble
# - DB (IO) - transmits data in/out, data mask, parallel commands
# - DQS (IO) - strobe for commands/data/mask on DB pins
# DQS is edge-aligned to CLK, while DB and STB are center-aligned to CLK (phase = -90).
# Sending a parallel command (on DB pins):
# CLK: ____----____----____----____----____----____
# STB: ----------________________------------------
# DQS: ....................----____----____........
# DB: ..........................PPPPnnnn..........
# The signals prepared by BasePHY will all be phase-aligned. The concrete PHY should shift
# them so that DB/STB/CS are delayed by 90 degrees in relation to CLK/DQS.
# Signal values (de)serialized during 1 sysclk.
# These signals must be populated in specific PHY implementations.
self.clk_1ck_out = clk_1ck_out = Signal(2*nphases)
self.stb_1ck_out = stb_1ck_out = Signal(2*nphases)
self.cs_n_1ck_out = cs_n_1ck_out = Signal(2*nphases)
self.dqs_1ck_out = dqs_1ck_out = Signal(2*nphases)
self.dqs_1ck_in = dqs_1ck_in = Signal(2*nphases)
self.dqs_oe = dqs_oe = Signal()
self.db_1ck_out = db_1ck_out = [Signal(2*nphases) for _ in range(databits)]
self.db_1ck_in = db_1ck_in = [Signal(2*nphases) for _ in range(databits)]
self.db_oe = db_oe = Signal()
# Clocks -----------------------------------------------------------------------------------
self.comb += clk_1ck_out.eq(bitpattern("-_-_-_-_"))
# DB muxing --------------------------------------------------------------------------------
# Commands allowed by FSM
cmd_valid = Signal()
# Muxed cmd/data/mask
db_1ck_data = [Signal(2*nphases) for _ in range(databits)]
db_1ck_mask = [Signal(2*nphases) for _ in range(databits)]
db_1ck_cmd = [Signal(2*nphases) for _ in range(databits)]
dq_data_en = Signal()
dq_mask_en = Signal()
dq_cmd_en = Signal()
dq_read_stb = Signal()
# Output enable when writing cmd/data/mask
# Mask is being send during negative half of sysclk
self.comb += db_oe.eq(cmd_valid & (dq_data_en | dq_mask_en | dq_cmd_en))
# Mux between cmd/data/mask
for i in range(databits):
self.comb += \
If(dq_data_en,
db_1ck_out[i].eq(db_1ck_data[i])
).Elif(dq_mask_en,
db_1ck_out[i].eq(db_1ck_mask[i])
).Else(
db_1ck_out[i].eq(db_1ck_cmd[i])
)
# Parallel commands ------------------------------------------------------------------------
# We need to insert 2 full-clk cycles of STB=0 before any command, to mark the beginning of
# Request Packet. For that reason we use the previous values of DFI commands. To always be
# able to meet tCSS, we have to add a delay of 1 more sysclk.
# list from oldest to newest: dfi[N-1][p0], dfi[N-1][p1], ..., dfi[N][p0], dfi[N][p1], ...
dfi_adapters = []
for phase in dfi_hist[2].phases + dfi_hist[1].phases + dfi_hist[0].phases:
adapter = DFIAdapter(phase)
self.submodules += adapter
dfi_adapters.append(adapter)
self.comb += [
# We always send one WORD, which consists of 32 bytes.
adapter.bc.eq(0),
# Always use fast refresh (equivalent to auto refresh) instead of low-power refresh
# (equivalent to self refresh).
adapter.ref_op.eq(adapter.REF_OP["FST"]),
]
# Serialize commands to DB pins
for i in range(databits):
# A list of differential DB values using previous DFI coomand:
# db_p[p][i], db_n[p][i], db_p[p+1][i], db_n[p+1][i], ...
bits = [db for a in dfi_adapters[:nphases] for db in [a.db_p[i], a.db_n[i]]]
self.comb += db_1ck_cmd[i].eq(Cat(*bits))
# Commands go on the 2nd cycle, so use previous DFI
self.comb += dq_cmd_en.eq(reduce(or_, [a.cmd_valid for a in dfi_adapters[:nphases]]))
# Power Up Reset ---------------------------------------------------------------------------
# During Power Up, after stabilizing clocks, Power Up Reset must be done. It consists of a
# a Parallel Reset followed by two Serial Resets (2x8=16 full-rate cycles = 4 sys cycles).
# We use an FSM to make sure that we pass only the commands from the controller that are
# supported in the current state.
t_reset = 5e-6
t_zqcinit = 1e-6
serial_reset_len = 4
stb_reset_seq = Signal()
serial_reset_count = Signal(max=serial_reset_len + 1)
# prolong the cmd_valid for the cmd latency (length of history)
self.submodules.cmd_valid_sr = ShiftRegister(len(dfi_adapters) // nphases)
self.comb += cmd_valid.eq(reduce(or_, self.cmd_valid_sr))
self.submodules.reset_timer = WaitTimer(ceil(t_reset * sys_clk_freq))
self.submodules.zqcinit_timer = WaitTimer(ceil(t_zqcinit * sys_clk_freq))
self.submodules.reset_fsm = fsm = FSM()
fsm.act("IDLE",
NextValue(serial_reset_count, 0),
NextValue(self._reset_done.status, 0),
self.cmd_valid_sr.i.eq(dfi_adapters[2*nphases+0].is_cmd("RESET")),
If(self.cmd_valid_sr.i,
NextState("RESET_RECEIVED")
),
)
fsm.act("RESET_RECEIVED",
NextState("SERIAL_RESET")
)
fsm.act("SERIAL_RESET",
self.reset_timer.wait.eq(1),
If(serial_reset_count != serial_reset_len,
stb_reset_seq.eq(1),
NextValue(serial_reset_count, serial_reset_count + 1),
),
If(self.reset_timer.done,
NextValue(self._reset_done.status, 1),
NextState("RESET_DONE")
)
)
fsm.act("RESET_DONE",
self.cmd_valid_sr.i.eq(dfi_adapters[2*nphases+0].is_cmd(["PRE", "MRS", "ZQC_INIT"])),
If(dfi_adapters[2*nphases+0].is_cmd("ZQC_INIT"),
NextState("ZQC_INIT")
)
)
fsm.act("ZQC_INIT",
self.zqcinit_timer.wait.eq(1),
If(self.zqcinit_timer.done,
NextState("READY")
)
)
fsm.act("READY",
self._init_done.status.eq(1),
self.cmd_valid_sr.i.eq(1),
If(dfi_adapters[2*nphases+0].is_cmd("UTR") & (dfi_adapters[2*nphases+0].utr_en == 1),
NextState("UTR_MODE")
),
If(self._reset_fsm.re,
NextState("IDLE")
)
)
fsm.act("UTR_MODE",
self._init_done.status.eq(1),
self.cmd_valid_sr.i.eq(reduce(or_, [dfi_adapters[p].is_cmd(["UTR", "RD"])
for p in [2*nphases, 2*nphases+self.settings.rdphase]])),
If(dfi_adapters[2*nphases+0].is_cmd("UTR") & (dfi_adapters[2*nphases+0].utr_en == 0),
NextState("READY")
)
)
# STB --------------------------------------------------------------------------------------
# Currently not sending any serial commands, but the STB pin must be held low for 2 full
# rate cycles before writing a parallel command to activate the DRAM.
stb_bits = []
assert self.settings.rdphase == 3
read_sent = [Signal(), Signal()]
self.comb += read_sent[0].eq(dfi_adapters[3].cmd_valid & (dfi_adapters[3].is_cmd("RD") | dfi_adapters[3].is_cmd("WR")))
self.sync += read_sent[1].eq(read_sent[0])
for p in range(nphases):
# Use cmd from current and prev cycle, depending on which phase the command appears on
preamble = (dfi_adapters[p+2].cmd_valid | dfi_adapters[p+1].cmd_valid) & cmd_valid
# force 000100xxxxxxxxxx after preamble to generate Burst Stop
assert self.settings.rdphase == 3
burst_stop = {
0: [0, 0],
1: [0, 1],
2: [0, 0],
3: [1, 1],
}[(p+1)%4]
read = read_sent[0] if p == 3 else read_sent[1]
burst_stop_zero = [cmd_valid & read & (bs == 0) & self._burst_stop.storage
for bs in burst_stop]
# We only want to use STB to start parallel commands, serial reset or to send NOPs. NOP
# is indicated by the first two bits being high (0b11, and other as "don't care"), so
# we can simply hold STB high all the time and reset is zeros for 8 cycles (1 sysclk).
# stb_bits += 2 * [~(preamble | stb_reset_seq)]
stb_bits += [
~(preamble | stb_reset_seq | burst_stop_zero[0]),
~(preamble | stb_reset_seq | burst_stop_zero[1]),
]
self.comb += stb_1ck_out.eq(Cat(*stb_bits))
# Chip Select ------------------------------------------------------------------------------
# RPC has quite high required time of CS# low before sending a command (tCSS), this means
# that we would need 1 more cmd_latency to support it for all standard frequencies. To meet
# tCSH we hold CS# low 1 cycle after each command (and for writes until the burst ends).
tCSS = 10e-9
tCSH = 5e-9
# CS# is held for 2 sysclks before any command, and 1 sysclk after any command
assert 2 * 1/sys_clk_freq >= tCSS, "tCSS not met for commands on phase 0"
assert 1 * 1/sys_clk_freq >= tCSH, "tCSH not met for commands on phase 3"
cs = Signal()
cs_burst_hold = Signal()
self.submodules.cs_hold = ShiftRegister(2)
# FIXME: currently we hold CS low constantly to avoid problems with signal integrity on our board
# lock CS when DFI sends cs_n=0 only on phase 0 (avoids start condition problems)
cs_lock = Signal()
cs_lock_cond = reduce(and_, [dfi_hist[0].phases[p].cs_n for p in range(1, nphases)])
cs_lock_cond = cs_lock_cond & ~dfi_hist[0].p0.cs_n
self.sync += If(cs_lock_cond, cs_lock.eq(1)).Elif(self._reset_fsm.re, cs_lock.eq(0))
_any_cmd_valid = reduce(or_, (a.cmd_valid for a in dfi_adapters))
self.comb += [
# self.cs_hold.i.eq(cmd_valid & (_any_cmd_valid | cs_burst_hold)),
# cs.eq(reduce(or_, self.cs_hold.sr)),
# cs_n_1ck_out.eq(Replicate(~cs, len(cs_n_1ck_out))),
cs_n_1ck_out.eq(Replicate(~cs_lock, len(cs_n_1ck_out))),
]
# Data IN ----------------------------------------------------------------------------------
# Synchronize the deserializer because we deserialize over 2 cycles.
dq_in_cnt = Signal()
self.sync += If(dq_read_stb, dq_in_cnt.eq(~dq_in_cnt)).Else(dq_in_cnt.eq(0))
# Deserialize read data
# sys_clk: ------------____________------------____________
# sysx4_clk: ---___---___---___---___---___---___---___---___
# DB num: <0><1><2><3><4><5><6><7><8><9><a><b><c><d><e><f>
for i in range(databits):
# BL=16 -> 2ck
n_1ck = 2*nphases
rbits_2ck = Signal(2*n_1ck)
rbits_1ck = Signal(n_1ck)
self.comb += rbits_1ck.eq(db_1ck_in[i])
self.sync += Case(dq_in_cnt, {
0: rbits_2ck[:n_1ck].eq(rbits_1ck),
1: rbits_2ck[n_1ck:].eq(rbits_1ck),
})
bs = BitSlip(len(rbits_2ck), cycles=bitslip_cycles,
rst = self.get_rst(i//8, self._rdly_dq_bitslip_rst.re),
slp = self.get_inc(i//8, self._rdly_dq_bitslip.re),
)
self.submodules += bs
self.comb += bs.i.eq(rbits_2ck)
for p in range(nphases):
self.comb += [
dfi.phases[p].rddata[i+0*databits].eq(bs.o[p*nphases+0]),
dfi.phases[p].rddata[i+1*databits].eq(bs.o[p*nphases+1]),
dfi.phases[p].rddata[i+2*databits].eq(bs.o[p*nphases+2]),
dfi.phases[p].rddata[i+3*databits].eq(bs.o[p*nphases+3]),
]
# Data OUT ---------------------------------------------------------------------------------
# TODO: add 1 to tWR bacause we need 2 cycles to send data from 1 cycle
# Before sending the actual data we have to send 2 32-bit data masks (4 DDR cycles). In the
# mask each 0 bit means "write byte" and 1 means "mask byte". The 1st 32-bits mask the first
# data WORD (32 bytes), and the 2nd 32-bits mask the last data WORD. Because we always send
# 1 WORD of data (BC=0), we don't care about the 2nd mask (can send 1).
#
# Write data
# DFI valid: xxxxxxxxxxxxxxxxxx
# sys_clk: ------____________------------____________------------____________
# sysx4_clk: ---___---___---___---___---___---___---___---___---___---___---___
# DB num: <M><M><M><M><0><1><2><3><4><5><6><7><8><9><a><b><c><d><e><f>
# Synchronize to 2 cycles, reset counting when dq_data_en turns high.
db_cnt = Signal()
self.sync += If(dq_data_en, db_cnt.eq(~db_cnt)).Else(db_cnt.eq(0))
for i in range(databits):
# Write data ---------------------------------------------------------------------------
wbits = []
for p in range(nphases):
_dfi = dfi_hist[1] if p < nphases//2 else dfi_hist[2]
wbits += [
_dfi.phases[p].wrdata[i+0*databits],
_dfi.phases[p].wrdata[i+1*databits],
_dfi.phases[p].wrdata[i+2*databits],
_dfi.phases[p].wrdata[i+3*databits],
]
# Mux datas from 2 cycles to always serialize single cycle.
wbits_2ck = [Cat(*wbits[:2*nphases]), Cat(*wbits[2*nphases:])]
wbits_1ck = Signal(2*nphases)
self.comb += wbits_1ck.eq(Array(wbits_2ck)[db_cnt])
self.comb += db_1ck_data[i].eq(Cat(*wbits_1ck))
# Data mask ----------------------------------------------------------------------------
mask = [
Constant(0), # phase 0
Constant(0), # phase 0
Constant(0), # phase 1
Constant(0), # phase 1
dfi_hist[0].phases[i//8 + 0].wrdata_mask[i%8], # WL-2
dfi_hist[0].phases[i//8 + 2].wrdata_mask[i%8], # WL-2
Constant(1), # WL-1
Constant(1), # WL-1
]
self.comb += db_1ck_mask[i].eq(Cat(*mask))
# DQS --------------------------------------------------------------------------------------
# Strobe pattern can go over 2 sysclk (do not count while transmitting mask)
dqs_cnt = Signal()
self.sync += If(dqs_oe & (~dq_mask_en), dqs_cnt.eq(~dqs_cnt)).Else(dqs_cnt.eq(0))
pattern_2ck = [Signal(2*nphases), Signal(2*nphases)]
self.comb += dqs_1ck_out.eq(Array(pattern_2ck)[dqs_cnt])
# To avoid having to serialize dqs_oe, we serialize predefined pattern on dqs_out
# All the patterns will be shifted back 90 degrees!
data_pattern = [bitpattern("-_-_-_-_"), bitpattern("-_-_-_-_")]
mask_pattern = [bitpattern("__-_-_-_"), bitpattern("-_-_-_-_")]
phase_patterns = {
0: [bitpattern("______-_"), bitpattern("-_______")],
1: [bitpattern("________"), bitpattern("-_-_____")],
2: [bitpattern("________"), bitpattern("__-_-___")],
3: [bitpattern("________"), bitpattern("____-_-_")],
}
pattern_cases = \
If(dq_mask_en,
pattern_2ck[0].eq(mask_pattern[0]),
pattern_2ck[1].eq(mask_pattern[1]),
).Elif(dq_data_en,
pattern_2ck[0].eq(data_pattern[0]),
pattern_2ck[1].eq(data_pattern[1]),
).Else(
pattern_2ck[0].eq(0),
pattern_2ck[1].eq(0),
)
any_phase_valid = 0
for p in range(nphases):
phase_valid = dfi_adapters[p].cmd_valid | dfi_adapters[nphases+p].cmd_valid
pattern_cases = \
If(phase_valid,
pattern_2ck[0].eq(phase_patterns[p][0]),
pattern_2ck[1].eq(phase_patterns[p][1]),
).Else(pattern_cases)
any_phase_valid = any_phase_valid | phase_valid
self.comb += pattern_cases
self.comb += dqs_oe.eq(cmd_valid & (any_phase_valid | dq_mask_en | dq_data_en))
# Read Control Path ------------------------------------------------------------------------
# Creates a shift register of read commands coming from the DFI interface. This shift
# register is used to indicate to the DFI interface that the read data is valid.
self.submodules.rddata_en = rddata_en = ShiftRegister(self.settings.read_latency)
self.comb += rddata_en.i.eq(dfi.phases[self.settings.rdphase].rddata_en)
# -1 because of syncronious assignment
self.sync += [phase.rddata_valid.eq(rddata_en[-1]) for phase in dfi.phases]
# Strobe high when data from DRAM is available, before we can send it to DFI.
self.sync += dq_read_stb.eq(rddata_en[read_db_des_dly-1] | rddata_en[read_db_des_dly-1 + 1])
# Write Control Path -----------------------------------------------------------------------
# Creates a shift register of write commands coming from the DFI interface. This shift
# register is used to control DQ/DQS tristates.
self.submodules.wrdata_en = wrdata_en = ShiftRegister(self.settings.write_latency + 2 + 1)
self.comb += wrdata_en.i.eq(dfi.phases[self.settings.wrphase].wrdata_en & cmd_valid)
# DQS Preamble and data mask are transmitted 1 cycle before data, then 2 cycles of data
self.comb += dq_mask_en.eq(wrdata_en[write_latency])
self.comb += dq_data_en.eq(wrdata_en[write_latency + 1] | wrdata_en[write_latency + 2])
# Hold CS# low until end of write burst (use a latch as there can only be 1 write at a time)
cs_wr_hold = Signal()
self.sync += If(wrdata_en[0], cs_wr_hold.eq(1)).Elif(wrdata_en[-1], cs_wr_hold.eq(0))
cs_rd_hold = Signal()
self.sync += If(rddata_en[0], cs_rd_hold.eq(1)).Elif(rddata_en[-1], cs_rd_hold.eq(0))
self.comb += cs_burst_hold.eq(cs_wr_hold | cs_rd_hold)
# Additional variables for LiteScope -------------------------------------------------------
variables = ["dq_data_en", "dq_mask_en", "dq_cmd_en", "dq_read_stb", "dfi_adapters",
"dq_in_cnt", "db_cnt", "dqs_cnt", "rddata_en", "wrdata_en"]
for v in variables:
setattr(self, v, locals()[v])
def get_rst(self, byte, rst):
return (self._dly_sel.storage[byte] & rst) | self._rst.storage
def get_inc(self, byte, inc):
return self._dly_sel.storage[byte] & inc
def do_finalize(self):
self.do_clock_serialization(self.clk_1ck_out, self.pads.clk_p, self.pads.clk_n)
self.do_stb_serialization(self.stb_1ck_out, self.pads.stb)
self.do_dqs_serialization(self.dqs_1ck_out, self.dqs_1ck_in, self.dqs_oe,
self.pads.dqs_p, self.pads.dqs_n)
self.do_db_serialization(self.db_1ck_out, self.db_1ck_in, self.db_oe, self.pads.db)
self.do_cs_serialization(self.cs_n_1ck_out, self.pads.cs_n)
# I/O implementation ---------------------------------------------------------------------------
def do_clock_serialization(self, clk_1ck_out, clk_p, clk_n):
raise NotImplementedError("Serialize the full-rate clock with 90 deg phase delay")
def do_stb_serialization(self, stb_1ck_out, stb):
raise NotImplementedError("Serialize the STB line")
def do_dqs_serialization(self, dqs_1ck_out, dqs_1ck_in, dqs_oe, dqs_p, dqs_n):
raise NotImplementedError("Tristate and (de)serialize DQS with 90 deg phase delay")
def do_db_serialization(self, db_1ck_out, db_1ck_in, db_oe, db):
raise NotImplementedError("Tristate and (de)serialize DB")
def do_cs_serialization(self, cs_n_1ck_out, cs_n):
raise NotImplementedError("Serialize the chip select line (CS#)")
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"litex.soc.interconnect.csr.CSRStatus"
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#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2018 <NAME> <<EMAIL>>
# Copyright (c) 2020 <NAME> <<EMAIL>>
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc
from litex.build.xilinx import XilinxPlatform
from litex.build.openocd import OpenOCD
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk50", 0, Pins("N14"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("M1"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("A14"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("A13"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("N11")), # BDBUS1
Subsignal("rx", Pins("E11")), # BDBUS0
IOStandard("LVCMOS33")
),
# SRAM
("issiram", 0,
Subsignal("addr", Pins(
"M4 N3 N4 P3 M5 E5 D5 D3",
"B7 B4 J4 H4 H3 G4 E6 A7",
"A5 A4 C4"),
IOStandard("LVCMOS33")),
Subsignal("data", Pins(
"L5 L3 L4 R2 F3 F4 E3 D6"),
IOStandard("LVCMOS33")),
Subsignal("wen", Pins("R1"), IOStandard("LVCMOS33")),
Subsignal("cen", Pins("M6"), IOStandard("LVCMOS33")),
Misc("SLEW=FAST"),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = []
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7a35tftg256-1", _io, _connectors, toolchain="vivado")
def do_finalize(self,fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), self.default_clk_period)
| [
"litex.build.generic_platform.Misc",
"litex.build.generic_platform.IOStandard",
"litex.build.generic_platform.Pins",
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((501, 512), 'litex.build.generic_platform.Pins', 'Pins', (['"""N14"""'], {}), "('N14')\n", (505, 512), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((514, 536), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (524, 536), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((571, 581), 'litex.build.generic_platform.Pins', 'Pins', (['"""M1"""'], {}), "('M1')\n", (575, 581), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((584, 606), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (594, 606), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((629, 640), 'litex.build.generic_platform.Pins', 'Pins', (['"""A14"""'], {}), "('A14')\n", (633, 640), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((642, 664), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (652, 664), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((687, 698), 'litex.build.generic_platform.Pins', 'Pins', (['"""A13"""'], {}), "('A13')\n", (691, 698), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((700, 722), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (710, 722), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((859, 881), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (869, 881), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1333, 1350), 'litex.build.generic_platform.Misc', 'Misc', (['"""SLEW=FAST"""'], {}), "('SLEW=FAST')\n", (1337, 1350), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1716, 1806), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7a35tftg256-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7a35tftg256-1', _io, _connectors,\n toolchain='vivado')\n", (1739, 1806), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((1848, 1890), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (1874, 1890), False, 'from litex.build.xilinx import XilinxPlatform\n'), ((781, 792), 'litex.build.generic_platform.Pins', 'Pins', (['"""N11"""'], {}), "('N11')\n", (785, 792), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((828, 839), 'litex.build.generic_platform.Pins', 'Pins', (['"""E11"""'], {}), "('E11')\n", (832, 839), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((946, 1016), 'litex.build.generic_platform.Pins', 'Pins', (['"""M4 N3 N4 P3 M5 E5 D5 D3"""', '"""B7 B4 J4 H4 H3 G4 E6 A7"""', '"""A5 A4 C4"""'], {}), "('M4 N3 N4 P3 M5 E5 D5 D3', 'B7 B4 J4 H4 H3 G4 E6 A7', 'A5 A4 C4')\n", (950, 1016), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1067, 1089), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (1077, 1089), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1118, 1149), 'litex.build.generic_platform.Pins', 'Pins', (['"""L5 L3 L4 R2 F3 F4 E3 D6"""'], {}), "('L5 L3 L4 R2 F3 F4 E3 D6')\n", (1122, 1149), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1176, 1198), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (1186, 1198), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1226, 1236), 'litex.build.generic_platform.Pins', 'Pins', (['"""R1"""'], {}), "('R1')\n", (1230, 1236), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1238, 1260), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (1248, 1260), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1288, 1298), 'litex.build.generic_platform.Pins', 'Pins', (['"""M6"""'], {}), "('M6')\n", (1292, 1298), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n'), ((1300, 1322), 'litex.build.generic_platform.IOStandard', 'IOStandard', (['"""LVCMOS33"""'], {}), "('LVCMOS33')\n", (1310, 1322), False, 'from litex.build.generic_platform import Pins, Subsignal, IOStandard, Misc\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
# The Colorlight i5 PCB and IOs have been documented by @wuxx
# https://github.com/wuxx/Colorlight-FPGA-Projects
from litex.build.generic_platform import *
from litex.build.lattice import LatticePlatform
from litex.build.lattice.programmer import EcpDapProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io_v7_0 = [ # Documented by @smunaut
# Clk
("clk25", 0, Pins("P3"), IOStandard("LVCMOS33")),
# Led
("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")),
# Reset button
("cpu_reset_n", 0, Pins("K18"), IOStandard("LVCMOS33"), Misc("PULLMODE=UP")),
# Serial
("serial", 0,
Subsignal("tx", Pins("J17")),
Subsignal("rx", Pins("H18")),
IOStandard("LVCMOS33")
),
# SPIFlash (GD25Q16CSIG)
("spiflash", 0,
Subsignal("cs_n", Pins("R2")),
# https://github.com/m-labs/nmigen-boards/pull/38
#Subsignal("clk", Pins("")), driven through USRMCLK
Subsignal("mosi", Pins("W2")),
Subsignal("miso", Pins("V2")),
IOStandard("LVCMOS33"),
),
# SDRAM SDRAM (EM638325-6H)
("sdram_clock", 0, Pins("B9"), IOStandard("LVCMOS33")),
("sdram", 0,
Subsignal("a", Pins(
"B13 C14 A16 A17 B16 B15 A14 A13",
"A12 A11 B12")),
Subsignal("dq", Pins(
"D15 E14 E13 D12 E12 D11 C10 B17",
"B8 A8 C7 A7 A6 B6 A5 B5",
"D5 C5 D6 C6 E7 D7 E8 D8",
"E9 D9 E11 C11 C12 D13 D14 C15")),
Subsignal("we_n", Pins("A10")),
Subsignal("ras_n", Pins("B10")),
Subsignal("cas_n", Pins("A9")),
#Subsignal("cs_n", Pins("")), # gnd
#Subsignal("cke", Pins("")), # 3v3
Subsignal("ba", Pins("B11 C8")), # sdram pin BA0 and BA1
#Subsignal("dm", Pins("")), # gnd
IOStandard("LVCMOS33"),
Misc("SLEWRATE=FAST")
),
# RGMII Ethernet (B50612D)
# The order of the two PHYs is swapped with the naming of the connectors
# on the board so to match with the configuration of their PHYA[0] pins.
("eth_clocks", 0,
Subsignal("tx", Pins("G1")),
Subsignal("rx", Pins("H2")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rst_n", Pins("P4")),
Subsignal("mdio", Pins("P5")),
Subsignal("mdc", Pins("N5")),
Subsignal("rx_ctl", Pins("P2")),
Subsignal("rx_data", Pins("K2 L1 N1 P1")),
Subsignal("tx_ctl", Pins("K1")),
Subsignal("tx_data", Pins("G2 H1 J1 J3")),
IOStandard("LVCMOS33")
),
("eth_clocks", 1,
Subsignal("tx", Pins("U19")),
Subsignal("rx", Pins("L19")),
IOStandard("LVCMOS33")
),
("eth", 1,
Subsignal("rst_n", Pins("P4")),
Subsignal("mdio", Pins("P5")),
Subsignal("mdc", Pins("N5")),
Subsignal("rx_ctl", Pins("M20")),
Subsignal("rx_data", Pins("P20 N19 N20 M19")),
Subsignal("tx_ctl", Pins("P19")),
Subsignal("tx_data", Pins("U20 T19 T20 R20")),
IOStandard("LVCMOS33")
),
]
# From https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/schematic/i5_v6.0-extboard.pdf and
# https://github.com/wuxx/Colorlight-FPGA-Projects/blob/master/doc/i5_extboard_v1.2_pinout.png
_connectors_v7_0 = [
("pmode", "C17 B18 B20 F20 A18 A19 B19 D20"),
("pmodf", "D1 C1 C2 E3 E2 D2 B1 A3"),
]
# PMODS --------------------------------------------------------------------------------------------
def sdcard_pmod_io(pmod):
return [
# SDCard PMOD:
# - https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
("spisdcard", 0,
Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("mosi", Pins(f"{pmod}:1"), Misc("PULLMODE=UP")),
Subsignal("cs_n", Pins(f"{pmod}:0"), Misc("PULLMODE=UP")),
Subsignal("miso", Pins(f"{pmod}:2"), Misc("PULLMODE=UP")),
Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
("sdcard", 0,
Subsignal("data", Pins(f"{pmod}:2 {pmod}:4 {pmod}:5 {pmod}:0"), Misc("PULLMODE=UP")),
Subsignal("cmd", Pins(f"{pmod}:1"), Misc("PULLMODE=UP")),
Subsignal("clk", Pins(f"{pmod}:3")),
Subsignal("cd", Pins(f"{pmod}:6")),
#Misc("SLEWRATE=FAST"),
IOStandard("LVCMOS33"),
),
]
_sdcard_pmod_io = sdcard_pmod_io("pmode") # SDCARD PMOD on P3.
# Platform -----------------------------------------------------------------------------------------
class Platform(LatticePlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/25e6
def __init__(self, revision="7.0", toolchain="trellis"):
assert revision in ["7.0"]
self.revision = revision
device = {"7.0": "LFE5U-25F-6BG381C"}[revision]
io = {"7.0": _io_v7_0}[revision]
connectors = {"7.0": _connectors_v7_0}[revision]
LatticePlatform.__init__(self, device, io, connectors=connectors, toolchain=toolchain)
def create_programmer(self):
return EcpDapProgrammer()
def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/25e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)
| [
"litex.build.lattice.programmer.EcpDapProgrammer",
"litex.build.lattice.LatticePlatform.do_finalize",
"litex.build.lattice.LatticePlatform.__init__"
] | [((5132, 5223), 'litex.build.lattice.LatticePlatform.__init__', 'LatticePlatform.__init__', (['self', 'device', 'io'], {'connectors': 'connectors', 'toolchain': 'toolchain'}), '(self, device, io, connectors=connectors, toolchain\n =toolchain)\n', (5156, 5223), False, 'from litex.build.lattice import LatticePlatform\n'), ((5268, 5286), 'litex.build.lattice.programmer.EcpDapProgrammer', 'EcpDapProgrammer', ([], {}), '()\n', (5284, 5286), False, 'from litex.build.lattice.programmer import EcpDapProgrammer\n'), ((5333, 5376), 'litex.build.lattice.LatticePlatform.do_finalize', 'LatticePlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (5360, 5376), False, 'from litex.build.lattice import LatticePlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2020 Antmicro <www.antmicro.com>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0,
Subsignal("p", Pins("F23"), IOStandard("LVDS")),
Subsignal("n", Pins("E23"), IOStandard("LVDS")),
),
("clk300", 0,
Subsignal("p", Pins("AH18"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("n", Pins("AH17"), IOStandard("DIFF_SSTL12_DCI")),
),
("cpu_reset", 0, Pins("M11"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("D5"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("D6"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("A5"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("B5"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("B4"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("C4"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("B3"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("C3"), IOStandard("LVCMOS33")),
# Switches
("user_dip", 0, Pins("E4"), IOStandard("LVCMOS33")),
("user_dip", 1, Pins("D4"), IOStandard("LVCMOS33")),
("user_dip", 2, Pins("F5"), IOStandard("LVCMOS33")),
("user_dip", 3, Pins("F4"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("cts", Pins("A19")),
Subsignal("rts", Pins("C18")),
Subsignal("tx", Pins("C19")),
Subsignal("rx", Pins("A20")),
IOStandard("LVCMOS18")
),
# I2C
("i2c", 0,
Subsignal("sda", Pins("P12")),
Subsignal("scl", Pins("N12")),
IOStandard("LVCMOS33")
),
# DDR4 SDRAM
("ddram", 0,
Subsignal("a", Pins(
"AH16 AG14 AG15 AF15 AF16 AJ14 AH14 AF17",
"AK17 AJ17 AK14 AK15 AL18 AK18"),
IOStandard("SSTL12_DCI")),
Subsignal("ba", Pins("AL15 AL16"), IOStandard("SSTL12_DCI")),
Subsignal("bg", Pins("AC16 AB16"), IOStandard("SSTL12_DCI")),
Subsignal("ras_n", Pins("AD15"), IOStandard("SSTL12_DCI")), # A16
Subsignal("cas_n", Pins("AA14"), IOStandard("SSTL12_DCI")), # A15
Subsignal("we_n", Pins("AA16"), IOStandard("SSTL12_DCI")), # A14
Subsignal("cs_n", Pins("AA15"), IOStandard("SSTL12_DCI")), # also AL17 AN17 AN16 for larger SODIMMs
Subsignal("act_n", Pins("AC17"), IOStandard("SSTL12_DCI")),
#Subsignal("alert_n", Pins("AB15"), IOStandard("SSTL12_DCI")),
#Subsignal("par", Pins("AD16"), IOStandard("SSTL12_DCI")),
Subsignal("dm", Pins("AH22 AE18 AL20 AP19 AF11 AH12 AK13 AN12"),
IOStandard("POD12_DCI")),
Subsignal("dq", Pins(
"AE24 AE23 AF22 AF21 AG20 AG19 AH21 AG21",
"AA20 AA19 AD19 AC18 AE20 AD20 AC19 AB19",
"AJ22 AJ21 AK20 AJ20 AK19 AJ19 AL23 AL22",
"AN23 AM23 AP23 AN22 AP22 AP21 AN19 AM19",
"AC13 AB13 AF12 AE12 AF13 AE13 AE14 AD14",
"AG8 AF8 AG10 AG11 AH13 AG13 AJ11 AH11",
"AK9 AJ9 AK10 AJ10 AL12 AK12 AL10 AL11",
"AM8 AM9 AM10 AM11 AP11 AN11 AP9 AP10"),
IOStandard("POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_p", Pins("AF23 AA18 AK22 AM21 AC12 AG9 AK8 AN9"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("dqs_n", Pins("AG23 AB18 AK23 AN21 AD12 AH9 AL8 AN8"),
IOStandard("DIFF_POD12_DCI"),
Misc("PRE_EMPHASIS=RDRV_240"),
Misc("EQUALIZATION=EQ_LEVEL2")),
Subsignal("clk_p", Pins("AF18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ16 for larger SODIMMs
Subsignal("clk_n", Pins("AG18"), IOStandard("DIFF_SSTL12_DCI")), # also AJ15 for larger SODIMMs
Subsignal("cke", Pins("AD17"), IOStandard("SSTL12_DCI")), # also AM15 for larger SODIMMs
Subsignal("odt", Pins("AE15"), IOStandard("SSTL12_DCI")), # also AM16 for larger SODIMMs
Subsignal("reset_n", Pins("AB14"), IOStandard("LVCMOS12")),
Misc("SLEW=FAST"),
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xczu7ev-ffvc1156-2-i", _io, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/125e6)
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 65]")
self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 66]")
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((4702, 4781), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu7ev-ffvc1156-2-i"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xczu7ev-ffvc1156-2-i', _io, toolchain=toolchain)\n", (4725, 4781), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((4831, 4849), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (4847, 4849), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((4896, 4938), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4922, 4938), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
from migen import *
from litex.soc.interconnect import stream
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR
from litex.soc.integration.doc import AutoDoc, ModuleDoc
from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter
class PatternMemory(Module):
def __init__(self, data_width, mem_depth, addr_width=32):
self.data = Memory(data_width, mem_depth)
self.addr = Memory(addr_width, mem_depth)
self.specials += self.data, self.addr
class BISTModule(Module):
"""
Provides RAM to store access pattern: `mem_addr` and `mem_data`.
The pattern address space can be limited using the `data_mask`.
For example, having `mem_adr` filled with `[ 0x04, 0x02, 0x03, ... ]`
and `mem_data` filled with `[ 0xff, 0xaa, 0x55, ... ]` and setting
`data_mask = 0b01`, the pattern [(address, data), ...] written will be:
`[(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), ...]` (wraps due to masking).
DRAM memory range that is being accessed can be configured using `mem_mask`.
To use this module, make sure that `ready` is 1, then write the desired
number of transfers to `count`. Writing to the `start` CSR will initialize
the operation. When the operation is ongoing `ready` will be 0.
"""
def __init__(self, pattern_mem):
self.start = Signal()
self.ready = Signal()
self.count = Signal(32)
self.done = Signal(32)
self.mem_mask = Signal(32)
self.data_mask = Signal(32)
self.data_port = pattern_mem.data.get_port()
self.addr_port = pattern_mem.addr.get_port()
self.specials += self.data_port, self.addr_port
def add_csrs(self):
self._start = CSR()
self._start.description = 'Write to the register starts the transfer (if ready=1)'
self._ready = CSRStatus(description='Indicates that the transfer is not ongoing')
self._count = CSRStorage(size=len(self.count), description='Desired number of DMA transfers')
self._done = CSRStatus(size=len(self.done), description='Number of completed DMA transfers')
self._mem_mask = CSRStorage(
size = len(self.mem_mask),
description = 'DRAM address mask for DMA transfers'
)
self._data_mask = CSRStorage(
size = len(self.mem_mask),
description = 'Pattern memory address mask'
)
self.comb += [
self.start.eq(self._start.re),
self._ready.status.eq(self.ready),
self.count.eq(self._count.storage),
self._done.status.eq(self.done),
self.mem_mask.eq(self._mem_mask.storage),
self.data_mask.eq(self._data_mask.storage),
]
class Writer(BISTModule, AutoCSR, AutoDoc):
def __init__(self, dram_port, pattern_mem):
super().__init__(pattern_mem)
self.doc = ModuleDoc("""
DMA DRAM writer.
Allows to fill DRAM with a predefined pattern using DMA.
Pattern
-------
{common}
""".format(common=BISTModule.__doc__))
# FIXME: Increase fifo depth
dma = LiteDRAMDMAWriter(dram_port, fifo_depth=1)
self.submodules += dma
cmd_counter = Signal(32)
self.comb += [
self.done.eq(cmd_counter),
# pattern
self.data_port.adr.eq(cmd_counter & self.data_mask),
self.addr_port.adr.eq(cmd_counter & self.data_mask),
# DMA
dma.sink.address.eq(self.addr_port.dat_r + (cmd_counter & self.mem_mask)),
dma.sink.data.eq(self.data_port.dat_r),
]
self.submodules.fsm = fsm = FSM()
fsm.act("READY",
self.ready.eq(1),
If(self.start,
NextValue(cmd_counter, 0),
NextState("WAIT"),
)
)
fsm.act("WAIT", # TODO: we could pipeline the access
If(cmd_counter >= self.count,
NextState("READY")
).Else(
NextState("RUN")
)
)
fsm.act("RUN",
dma.sink.valid.eq(1),
If(dma.sink.ready,
NextValue(cmd_counter, cmd_counter + 1),
NextState("WAIT")
)
)
class Reader(BISTModule, AutoCSR, AutoDoc):
def __init__(self, dram_port, pattern_mem):
super().__init__(pattern_mem)
self.doc = ModuleDoc("""
DMA DRAM reader.
Allows to check DRAM contents against a predefined pattern using DMA.
Pattern
-------
{common}
Reading errors
--------------
This module allows to check the locations of errors in the memory.
It scans the configured memory area and compares the values read to
the predefined pattern. If `skip_fifo` is 0, this module will stop
after each error encountered, so that it can be examined. Wait until
the `error_ready` CSR is 1. Then use the CSRs `error_offset`,
`error_data` and `error_expected` to examine the errors in the current
transfer. To continue reading, write 1 to `error_continue` CSR.
Setting `skip_fifo` to 1 will disable this behaviour entirely.
The final nubmer of errors can be read from `error_count`.
NOTE: This value represents the number of erroneous *DMA transfers*.
The current progress can be read from the `done` CSR.
""".format(common=BISTModule.__doc__))
error_desc = [
('offset', 32),
('data', dram_port.data_width),
('expected', dram_port.data_width),
]
self.error_count = Signal(32)
self.skip_fifo = Signal()
self.error = stream.Endpoint(error_desc)
# FIXME: Increase fifo depth
dma = LiteDRAMDMAReader(dram_port)
self.submodules += dma
# ----------------- Address FSM -----------------
counter_addr = Signal(32)
self.comb += [
self.addr_port.adr.eq(counter_addr & self.data_mask),
dma.sink.address.eq(self.addr_port.dat_r + (counter_addr & self.mem_mask)),
]
# Using temporary state 'WAIT' to obtain address offset from memory
self.submodules.fsm_addr = fsm_addr = FSM()
fsm_addr.act("READY",
If(self.start,
NextValue(counter_addr, 0),
NextState("WAIT"),
)
)
fsm_addr.act("WAIT", # TODO: we could pipeline the access
If(counter_addr >= self.count,
NextState("READY")
).Else(
NextState("WR_ADDR")
)
)
fsm_addr.act("WR_ADDR",
dma.sink.valid.eq(1),
If(dma.sink.ready,
NextValue(counter_addr, counter_addr + 1),
NextState("WAIT")
)
)
# ------------- Pattern FSM ----------------
counter_gen = Signal(32)
# Unmatched memory offsets
error_fifo = stream.SyncFIFO(error_desc, depth=2, buffered=False)
self.submodules += error_fifo
self.comb += [
self.data_port.adr.eq(counter_gen & self.data_mask),
self.error.offset.eq(error_fifo.source.offset),
self.error.data.eq(error_fifo.source.data),
self.error.expected.eq(error_fifo.source.expected),
self.error.valid.eq(error_fifo.source.valid),
error_fifo.source.ready.eq(self.error.ready | self.skip_fifo),
self.done.eq(counter_gen),
]
self.submodules.fsm_pattern = fsm_pattern = FSM()
fsm_pattern.act("READY",
self.ready.eq(1),
If(self.start,
NextValue(counter_gen, 0),
NextValue(self.error_count, 0),
NextState("WAIT"),
)
)
fsm_pattern.act("WAIT", # TODO: we could pipeline the access
If(counter_gen >= self.count,
NextState("READY")
).Else(
NextState("RD_DATA")
)
)
fsm_pattern.act("RD_DATA",
dma.source.ready.eq(1),
If(dma.source.valid,
NextValue(counter_gen, counter_gen + 1),
If(dma.source.data != self.data_port.dat_r,
NextValue(self.error_count, self.error_count + 1),
NextValue(error_fifo.sink.offset, counter_gen),
NextValue(error_fifo.sink.data, dma.source.data),
NextValue(error_fifo.sink.expected, self.data_port.dat_r),
If(self.skip_fifo,
NextState("WAIT")
).Else(
NextState("WR_ERR")
)
).Else(
NextState("WAIT")
)
)
)
fsm_pattern.act("WR_ERR",
error_fifo.sink.valid.eq(1),
If(error_fifo.sink.ready | self.skip_fifo,
NextState("WAIT")
)
)
def add_csrs(self):
super().add_csrs()
self._error_count = CSRStatus(size=len(self.error_count), description='Number of errors detected')
self._skip_fifo = CSRStorage(description='Skip waiting for user to read the errors FIFO')
self._error_offset = CSRStatus(size=len(self.mem_mask), description='Current offset of the error')
self._error_data = CSRStatus(size=len(self.data_port.dat_r), description='Erroneous value read from DRAM memory')
self._error_expected = CSRStatus(size=len(self.data_port.dat_r), description='Value expected to be read from DRAM memory')
self._error_ready = CSRStatus(description='Error detected and ready to read')
self._error_continue = CSR()
self._error_continue.description = 'Continue reading until the next error'
self.comb += [
self._error_count.status.eq(self.error_count),
self.skip_fifo.eq(self._skip_fifo.storage),
self._error_offset.status.eq(self.error.offset),
self._error_data.status.eq(self.error.data),
self._error_expected.status.eq(self.error.expected),
self.error.ready.eq(self._error_continue.re),
self._error_ready.status.eq(self.error.valid),
]
| [
"litex.soc.interconnect.csr.CSR",
"litex.soc.interconnect.stream.SyncFIFO",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus",
"litex.soc.interconnect.stream.Endpoint"
] | [((1696, 1701), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (1699, 1701), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR\n'), ((1815, 1882), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', ([], {'description': '"""Indicates that the transfer is not ongoing"""'}), "(description='Indicates that the transfer is not ongoing')\n", (1824, 1882), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR\n'), ((3087, 3129), 'litedram.frontend.dma.LiteDRAMDMAWriter', 'LiteDRAMDMAWriter', (['dram_port'], {'fifo_depth': '(1)'}), '(dram_port, fifo_depth=1)\n', (3104, 3129), False, 'from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter\n'), ((5563, 5590), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (['error_desc'], {}), '(error_desc)\n', (5578, 5590), False, 'from litex.soc.interconnect import stream\n'), ((5643, 5671), 'litedram.frontend.dma.LiteDRAMDMAReader', 'LiteDRAMDMAReader', (['dram_port'], {}), '(dram_port)\n', (5660, 5671), False, 'from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter\n'), ((6857, 6909), 'litex.soc.interconnect.stream.SyncFIFO', 'stream.SyncFIFO', (['error_desc'], {'depth': '(2)', 'buffered': '(False)'}), '(error_desc, depth=2, buffered=False)\n', (6872, 6909), False, 'from litex.soc.interconnect import stream\n'), ((9096, 9167), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', ([], {'description': '"""Skip waiting for user to read the errors FIFO"""'}), "(description='Skip waiting for user to read the errors FIFO')\n", (9106, 9167), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR\n'), ((9565, 9622), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', ([], {'description': '"""Error detected and ready to read"""'}), "(description='Error detected and ready to read')\n", (9574, 9622), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR\n'), ((9654, 9659), 'litex.soc.interconnect.csr.CSR', 'CSR', ([], {}), '()\n', (9657, 9659), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus, CSR\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.altera import AlteraPlatform
from litex.build.altera.programmer import USBBlaster
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk50", 0, Pins("23"), IOStandard("3.3-V LVTTL")),
("rst_n", 0, Pins("25"), IOStandard("3.3-V LVTTL")),
# Leds
("user_led", 0, Pins("84"), IOStandard("3.3-V LVTTL")),
("user_led", 1, Pins("85"), IOStandard("3.3-V LVTTL")),
("user_led", 2, Pins("86"), IOStandard("3.3-V LVTTL")),
("user_led", 3, Pins("87"), IOStandard("3.3-V LVTTL")),
# DIP switches shared with buttons
("key", 0, Pins("88"), IOStandard("3.3-V LVTTL")),
("key", 1, Pins("89"), IOStandard("3.3-V LVTTL")),
("key", 2, Pins("90"), IOStandard("3.3-V LVTTL")),
("key", 3, Pins("91"), IOStandard("3.3-V LVTTL")),
# Passive buzzer
("buzzer", 0, Pins("110"), IOStandard("3.3-V LVTTL")),
# LM75A temperature sensor (I2C)
("temp_i2c", 0,
Subsignal("scl", Pins("112")),
Subsignal("sda", Pins("113")),
IOStandard("3.3-V LVTTL")
),
# AT24C08 EEPROM (I2C)
("eeprom_i2c", 0,
Subsignal("scl", Pins("99")),
Subsignal("sda", Pins("98")),
IOStandard("3.3-V LVTTL")
),
# W25Q16JV SPI Flash, IO2 and IO3 pins are hardwired to 3v3 so we cannot use QSPI mode.
("spiflash", 0,
Subsignal("cs_n", Pins("8")),
Subsignal("clk", Pins("12")),
Subsignal("mosi", Pins("6")),
Subsignal("miso", Pins("13")),
IOStandard("3.3-V LVTTL"),
),
# Serial - using DB9 connector through SP3232EEN
("serial", 0,
Subsignal("tx", Pins("114")),
Subsignal("rx", Pins("119")),
IOStandard("3.3-V LVTTL")
),
# VGA
("vga", 0,
Subsignal("hsync", Pins("101")),
Subsignal("vsync", Pins("103")),
Subsignal("r", Pins("106")),
Subsignal("g", Pins("105")),
Subsignal("b", Pins("104")),
IOStandard("3.3-V LVTTL"),
),
# LCD display (HD44780 compatible)
("lcd_display", 0,
Subsignal("data", Pins("142 1 144 3 2 10 7 11")),
Subsignal("rs", Pins("141")),
Subsignal("rw", Pins("138")),
Subsignal("e", Pins("143")),
# Board provides 5V to display power pins, but it works fine with 3V3 on logic pins.
IOStandard("3.3-V LVTTL")
),
# 7 segment display
("segled", 0,
Subsignal("ca", Pins("128")),
Subsignal("cb", Pins("121")),
Subsignal("cc", Pins("125")),
Subsignal("cd", Pins("129")),
Subsignal("ce", Pins("132")),
Subsignal("cf", Pins("126")),
Subsignal("cg", Pins("124")),
Subsignal("dp", Pins("127")),
Subsignal("digits", Pins("133 135 136 137")),
IOStandard("3.3-V LVTTL")
),
# PS/2
("ps2", 0,
Subsignal("clk", Pins("119")),
Subsignal("data", Pins("120")),
IOStandard("3.3-V LVTTL")
),
# IrDA receiver
("irda", 0,
Subsignal("rxd", Pins("100")),
IOStandard("3.3-V LVTTL")
),
# GPIO
# There are only 2 free gpio pins, the rest of the pins in the headers
# are shared with the other peripherals
("gpio", 0, Pins(
"24 111"),
IOStandard("3.3-V LVTTL")
),
# Hynix HY57V641620FTP-7 SDRAM
("sdram_clock", 0, Pins("43"), IOStandard("3.3-V LVTTL")),
("sdram", 0,
Subsignal("a", Pins(
"76 77 80 83 68 67 66 65",
"64 60 75 59")),
Subsignal("ba", Pins("73 74")),
Subsignal("cs_n", Pins("72")),
Subsignal("cke", Pins("58")),
Subsignal("ras_n", Pins("71")),
Subsignal("cas_n", Pins("70")),
Subsignal("we_n", Pins("69")),
Subsignal("dq", Pins(
"28 30 31 32 33 34 38 39",
"54 53 52 51 50 49 46 44")),
Subsignal("dm", Pins("42 55")),
IOStandard("3.3-V LVTTL")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 1e9/50e6
def __init__(self, toolchain="quartus"):
AlteraPlatform.__init__(self, "EP4CE6E22C8", _io, toolchain=toolchain)
self.add_platform_command("set_global_assignment -name FAMILY \"Cyclone IV E\"")
self.add_platform_command("set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION \"USE AS REGULAR IO\"")
self.add_platform_command("set_global_assignment -name ENABLE_BOOT_SEL_PIN ON")
self.add_platform_command("set_global_assignment -name ENABLE_CONFIGURATION_PINS ON")
def create_programmer(self):
return USBBlaster()
def do_finalize(self, fragment):
AlteraPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)
| [
"litex.build.altera.AlteraPlatform.do_finalize",
"litex.build.altera.programmer.USBBlaster",
"litex.build.altera.AlteraPlatform.__init__"
] | [((4472, 4542), 'litex.build.altera.AlteraPlatform.__init__', 'AlteraPlatform.__init__', (['self', '"""EP4CE6E22C8"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'EP4CE6E22C8', _io, toolchain=toolchain)\n", (4495, 4542), False, 'from litex.build.altera import AlteraPlatform\n'), ((5480, 5492), 'litex.build.altera.programmer.USBBlaster', 'USBBlaster', ([], {}), '()\n', (5490, 5492), False, 'from litex.build.altera.programmer import USBBlaster\n'), ((5539, 5581), 'litex.build.altera.AlteraPlatform.do_finalize', 'AlteraPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (5565, 5581), False, 'from litex.build.altera import AlteraPlatform\n')] |
#!/usr/bin/env python3
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
"""
LitePCIE standalone core generator
LitePCIe aims to be directly used as a python package when the SoC is created using LiteX. However,
for some use cases it could be interesting to generate a standalone verilog file of the core:
- integration of the core in a SoC using a more traditional flow.
- need to version/package the core.
- avoid Migen/LiteX dependencies.
- etc...
The standalone core is generated from a YAML configuration file that allows the user to generate
easily a custom configuration of the core.
Current version of the generator is limited to Xilinx 7-Series FPGA / Altera Cyclone V.
"""
import yaml
import argparse
from migen import *
from migen.genlib.resetsync import AsyncResetSynchronizer
from litex.soc.cores.clock import *
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.axi import *
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
from litepcie.frontend.dma import LitePCIeDMA
from litepcie.frontend.wishbone import LitePCIeWishboneBridge
from litex.build.generic_platform import *
# IOs/Interfaces -----------------------------------------------------------------------------------
def get_clkin_ios():
return [
# clk / rst
("clk", 0, Pins(1)),
("rst", 0, Pins(1))
]
def get_clkout_ios():
return [
# clk / rst
("clk125", 0, Pins(1)),
("rst125", 0, Pins(1))
]
def get_pcie_ios(phy_lanes=4):
return [
("pcie", 0,
Subsignal("rst_n", Pins(1)),
Subsignal("clk_p", Pins(1)),
Subsignal("clk_n", Pins(1)),
Subsignal("rx_p", Pins(phy_lanes)),
Subsignal("rx_n", Pins(phy_lanes)),
Subsignal("tx_p", Pins(phy_lanes)),
Subsignal("tx_n", Pins(phy_lanes)),
),
]
def get_axi_lite_mmap_ios(aw, dw):
return [
("mmap_axi_lite", 0,
# aw
Subsignal("awvalid", Pins(1)),
Subsignal("awready", Pins(1)),
Subsignal("awaddr", Pins(aw)),
# w
Subsignal("wvalid", Pins(1)),
Subsignal("wready", Pins(1)),
Subsignal("wstrb", Pins(dw//8)),
Subsignal("wdata", Pins(dw)),
# b
Subsignal("bvalid", Pins(1)),
Subsignal("bready", Pins(1)),
Subsignal("bresp", Pins(2)),
# ar
Subsignal("arvalid", Pins(1)),
Subsignal("arready", Pins(1)),
Subsignal("araddr", Pins(aw)),
# r
Subsignal("rvalid", Pins(1)),
Subsignal("rready", Pins(1)),
Subsignal("rdata", Pins(dw)),
Subsignal("rresp", Pins(2)),
),
]
def get_axi_dma_ios(_id, dw):
return [
("dma{}_writer_axi".format(_id), 0,
Subsignal("tvalid", Pins(1)),
Subsignal("tready", Pins(1)),
Subsignal("tlast", Pins(1)),
Subsignal("tdata", Pins(dw)),
),
("dma{}_reader_axi".format(_id), 0,
Subsignal("tvalid", Pins(1)),
Subsignal("tready", Pins(1)),
Subsignal("tlast", Pins(1)),
Subsignal("tdata", Pins(dw)),
),
]
def get_msi_irqs_ios(width=16):
return [("msi_irqs", 0, Pins(width))]
def get_flash_ios():
return [
("flash", 0,
Subsignal("clk", Pins(1)),
Subsignal("cs_n", Pins(1)),
Subsignal("mosi", Pins(1)),
Subsignal("miso", Pins(1)),
Subsignal("vpp", Pins(1)),
Subsignal("hold", Pins(1)),
),
]
# CRG ----------------------------------------------------------------------------------------------
class LitePCIeCRG(Module):
def __init__(self, platform, clk_external):
self.clock_domains.cd_sys = ClockDomain()
self.rst = CSR() # not used
# # #
if clk_external:
platform.add_extension(get_clkin_ios())
self.comb += self.cd_sys.clk.eq(platform.request("clk"))
self.comb += self.cd_sys.rst.eq(platform.request("rst"))
else:
platform.add_extension(get_clkout_ios())
self.comb += self.cd_sys.clk.eq(ClockSignal("pcie"))
self.specials += AsyncResetSynchronizer(self.cd_sys, ResetSignal("pcie"))
self.comb += [
platform.request("clk125").eq(ClockSignal()),
platform.request("rst125").eq(ResetSignal()),
]
# Core ---------------------------------------------------------------------------------------------
class LitePCIeCore(SoCMini):
SoCMini.mem_map["csr"] = 0x00000000
def __init__(self, platform, core_config):
platform.add_extension(get_pcie_ios(core_config["phy_lanes"]))
for i in range(core_config["dma_channels"]):
platform.add_extension(get_axi_dma_ios(i, core_config["phy_data_width"]))
assert core_config["msi_irqs"] <= 16
platform.add_extension(get_msi_irqs_ios(width=core_config["msi_irqs"]))
sys_clk_freq = float(core_config.get("clk_freq", 125e6))
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq, csr_data_width=32,
ident="LitePCIe standalone core", ident_version=True)
# CRG --------------------------------------------------------------------------------------
clk_external = core_config.get("clk_external", False)
self.submodules.crg = LitePCIeCRG(platform, clk_external)
self.add_csr("crg")
# PCIe PHY ---------------------------------------------------------------------------------
self.submodules.pcie_phy = core_config["phy"](platform, platform.request("pcie"),
data_width = core_config["phy_data_width"],
bar0_size = core_config["phy_bar0_size"])
self.add_csr("pcie_phy")
# PCIe Endpoint ----------------------------------------------------------------------------
self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy, endianness=core_config["endianness"])
# PCIe Wishbone bridge ---------------------------------------------------------------------
pcie_wishbone = LitePCIeWishboneBridge(self.pcie_endpoint, qword_aligned=core_config["qword_aligned"])
self.submodules += pcie_wishbone
self.add_wb_master(pcie_wishbone.wishbone)
# PCIe MMAP --------------------------------------------------------------------------------
if core_config["mmap"]:
platform.add_extension(get_axi_lite_mmap_ios(aw=32, dw=32))
wb = wishbone.Interface(data_width=32)
self.mem_map["mmap"] = core_config["mmap_base"]
self.add_wb_slave(core_config["mmap_base"], wb, core_config["mmap_size"])
self.add_memory_region("mmap", core_config["mmap_base"], core_config["mmap_size"], type="io")
axi = AXILiteInterface(data_width=32, address_width=32)
wb2axi = Wishbone2AXILite(wb, axi)
self.submodules += wb2axi
mmap_ios = platform.request("mmap_axi_lite")
self.comb += [
# aw
mmap_ios.awvalid.eq(axi.aw.valid),
axi.aw.ready.eq(mmap_ios.awready),
mmap_ios.awaddr.eq(axi.aw.addr),
# w
mmap_ios.wvalid.eq(axi.w.valid),
axi.w.ready.eq(mmap_ios.wready),
mmap_ios.wstrb.eq(axi.w.strb),
mmap_ios.wdata.eq(axi.w.data),
# b
axi.b.valid.eq(mmap_ios.bvalid),
mmap_ios.bready.eq(axi.b.ready),
axi.b.resp.eq(mmap_ios.bresp),
# ar
mmap_ios.arvalid.eq(axi.ar.valid),
axi.ar.ready.eq(mmap_ios.arready),
mmap_ios.araddr.eq(axi.ar.addr),
# r
axi.r.valid.eq(mmap_ios.rvalid),
mmap_ios.rready.eq(axi.r.ready),
axi.r.data.eq(mmap_ios.rdata),
axi.r.resp.eq(mmap_ios.rresp),
]
# PCIe DMA ---------------------------------------------------------------------------------
pcie_dmas = []
self.add_constant("DMA_CHANNELS", core_config["dma_channels"])
for i in range(core_config["dma_channels"]):
pcie_dma = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint,
with_buffering = core_config["dma_buffering"] != 0,
buffering_depth = core_config["dma_buffering"],
with_loopback = core_config["dma_loopback"],
with_synchronizer = core_config["dma_synchronizer"],
with_monitor = core_config["dma_monitor"])
setattr(self.submodules, "pcie_dma" + str(i), pcie_dma)
self.add_csr("pcie_dma{}".format(i))
dma_writer_ios = platform.request("dma{}_writer_axi".format(i))
dma_reader_ios = platform.request("dma{}_reader_axi".format(i))
self.add_interrupt("pcie_dma{}_writer".format(i))
self.add_interrupt("pcie_dma{}_reader".format(i))
self.comb += [
# Writer IOs
pcie_dma.sink.valid.eq(dma_writer_ios.tvalid),
dma_writer_ios.tready.eq(pcie_dma.sink.ready),
pcie_dma.sink.last.eq(dma_writer_ios.tlast),
pcie_dma.sink.data.eq(dma_writer_ios.tdata),
# Reader IOs
dma_reader_ios.tvalid.eq(pcie_dma.source.valid),
pcie_dma.source.ready.eq(dma_reader_ios.tready),
dma_reader_ios.tlast.eq(pcie_dma.source.last),
dma_reader_ios.tdata.eq(pcie_dma.source.data),
]
# PCIe MSI ---------------------------------------------------------------------------------
self.submodules.pcie_msi = LitePCIeMSI(width=32)
self.add_csr("pcie_msi")
self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi)
self.interrupts = {}
for i in range(core_config["dma_channels"]):
self.interrupts["pcie_dma" + str(i) + "_writer"] = getattr(self, "pcie_dma" + str(i)).writer.irq
self.interrupts["pcie_dma" + str(i) + "_reader"] = getattr(self, "pcie_dma" + str(i)).reader.irq
for i, (k, v) in enumerate(sorted(self.interrupts.items())):
self.comb += self.pcie_msi.irqs[i].eq(v)
self.add_constant(k.upper() + "_INTERRUPT", i)
assert len(self.interrupts.keys()) <= 16
self.comb += self.pcie_msi.irqs[16:16+core_config["msi_irqs"]].eq(platform.request("msi_irqs"))
# 7-Series specific monitoring/flashing features -------------------------------------------
if platform.device[:3] == "xc7":
from litex.soc.cores.dna import DNA
from litex.soc.cores.xadc import XADC
from litex.soc.cores.icap import ICAP
from litex.soc.cores.spi_flash import S7SPIFlash
self.submodules.dna = DNA()
self.add_csr("dna")
self.submodules.xadc = XADC()
self.add_csr("xadc")
self.submodules.icap = ICAP()
self.add_csr("icap")
platform.add_extension(get_flash_ios())
self.submodules.flash = S7SPIFlash(platform.request("flash"), sys_clk_freq, 25e6)
self.add_csr("flash")
def generate_software_headers(self):
csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False)
tools.write_to_file(os.path.join("csr.h"), csr_header)
soc_header = get_soc_header(self.constants, with_access_functions=False)
tools.write_to_file(os.path.join("soc.h"), soc_header)
mem_header = get_mem_header(self.mem_regions)
tools.write_to_file(os.path.join("mem.h"), mem_header)
# Build --------------------------------------------------------------------------------------------
def main():
parser = argparse.ArgumentParser(description="LitePCIe standalone core generator")
parser.add_argument("config", help="YAML config file")
args = parser.parse_args()
core_config = yaml.load(open(args.config).read(), Loader=yaml.Loader)
# Convert YAML elements to Python/LiteX --------------------------------------------------------
for k, v in core_config.items():
replaces = {"False": False, "True": True, "None": None}
for r in replaces.keys():
if v == r:
core_config[k] = replaces[r]
# Generate core --------------------------------------------------------------------------------
if core_config["phy"] == "C5PCIEPHY":
from litex.build.altera import AlteraPlatform
from litepcie.phy.c5pciephy import C5PCIEPHY
platform = AlteraPlatform("", io=[])
core_config["phy"] = C5PCIEPHY
core_config["qword_aligned"] = True
core_config["endianness"] = "little"
elif core_config["phy"] == "S7PCIEPHY":
from litex.build.xilinx import XilinxPlatform
from litepcie.phy.s7pciephy import S7PCIEPHY
platform = XilinxPlatform(core_config["phy_device"], io=[], toolchain="vivado")
core_config["phy"] = S7PCIEPHY
core_config["qword_aligned"] = False
core_config["endianness"] = "big"
else:
raise ValueError("Unsupported PCIe PHY: {}".format(core_config["phy"]))
soc = LitePCIeCore(platform, core_config)
builder = Builder(soc, output_dir="build", compile_gateware=False)
vns = builder.build(build_name="litepcie_core", regular_comb=True)
soc.generate_software_headers()
if __name__ == "__main__":
main()
| [
"litex.soc.integration.export.get_csr_header",
"litex.soc.interconnect.wishbone.Interface",
"litex.soc.cores.dna.DNA",
"litex.soc.cores.xadc.XADC",
"litex.build.xilinx.XilinxPlatform",
"litex.soc.integration.export.get_mem_header",
"litex.soc.cores.icap.ICAP",
"litex.soc.integration.export.get_soc_hea... | [((12352, 12425), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '"""LitePCIe standalone core generator"""'}), "(description='LitePCIe standalone core generator')\n", (12375, 12425), False, 'import argparse\n'), ((6386, 6455), 'litepcie.core.LitePCIeEndpoint', 'LitePCIeEndpoint', (['self.pcie_phy'], {'endianness': "core_config['endianness']"}), "(self.pcie_phy, endianness=core_config['endianness'])\n", (6402, 6455), False, 'from litepcie.core import LitePCIeEndpoint, LitePCIeMSI\n'), ((6582, 6673), 'litepcie.frontend.wishbone.LitePCIeWishboneBridge', 'LitePCIeWishboneBridge', (['self.pcie_endpoint'], {'qword_aligned': "core_config['qword_aligned']"}), "(self.pcie_endpoint, qword_aligned=core_config[\n 'qword_aligned'])\n", (6604, 6673), False, 'from litepcie.frontend.wishbone import LitePCIeWishboneBridge\n'), ((10246, 10267), 'litepcie.core.LitePCIeMSI', 'LitePCIeMSI', ([], {'width': '(32)'}), '(width=32)\n', (10257, 10267), False, 'from litepcie.core import LitePCIeEndpoint, LitePCIeMSI\n'), ((11822, 11899), 'litex.soc.integration.export.get_csr_header', 'get_csr_header', (['self.csr_regions', 'self.constants'], {'with_access_functions': '(False)'}), '(self.csr_regions, self.constants, with_access_functions=False)\n', (11836, 11899), False, 'from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header\n'), ((11984, 12043), 'litex.soc.integration.export.get_soc_header', 'get_soc_header', (['self.constants'], {'with_access_functions': '(False)'}), '(self.constants, with_access_functions=False)\n', (11998, 12043), False, 'from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header\n'), ((12128, 12160), 'litex.soc.integration.export.get_mem_header', 'get_mem_header', (['self.mem_regions'], {}), '(self.mem_regions)\n', (12142, 12160), False, 'from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header\n'), ((13166, 13191), 'litex.build.altera.AlteraPlatform', 'AlteraPlatform', (['""""""'], {'io': '[]'}), "('', io=[])\n", (13180, 13191), False, 'from litex.build.altera import AlteraPlatform\n'), ((6984, 7017), 'litex.soc.interconnect.wishbone.Interface', 'wishbone.Interface', ([], {'data_width': '(32)'}), '(data_width=32)\n', (7002, 7017), False, 'from litex.soc.interconnect import wishbone\n'), ((8730, 9021), 'litepcie.frontend.dma.LitePCIeDMA', 'LitePCIeDMA', (['self.pcie_phy', 'self.pcie_endpoint'], {'with_buffering': "(core_config['dma_buffering'] != 0)", 'buffering_depth': "core_config['dma_buffering']", 'with_loopback': "core_config['dma_loopback']", 'with_synchronizer': "core_config['dma_synchronizer']", 'with_monitor': "core_config['dma_monitor']"}), "(self.pcie_phy, self.pcie_endpoint, with_buffering=core_config[\n 'dma_buffering'] != 0, buffering_depth=core_config['dma_buffering'],\n with_loopback=core_config['dma_loopback'], with_synchronizer=\n core_config['dma_synchronizer'], with_monitor=core_config['dma_monitor'])\n", (8741, 9021), False, 'from litepcie.frontend.dma import LitePCIeDMA\n'), ((11391, 11396), 'litex.soc.cores.dna.DNA', 'DNA', ([], {}), '()\n', (11394, 11396), False, 'from litex.soc.cores.dna import DNA\n'), ((11464, 11470), 'litex.soc.cores.xadc.XADC', 'XADC', ([], {}), '()\n', (11468, 11470), False, 'from litex.soc.cores.xadc import XADC\n'), ((11539, 11545), 'litex.soc.cores.icap.ICAP', 'ICAP', ([], {}), '()\n', (11543, 11545), False, 'from litex.soc.cores.icap import ICAP\n'), ((13503, 13571), 'litex.build.xilinx.XilinxPlatform', 'XilinxPlatform', (["core_config['phy_device']"], {'io': '[]', 'toolchain': '"""vivado"""'}), "(core_config['phy_device'], io=[], toolchain='vivado')\n", (13517, 13571), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
from litex.build.sim import SimPlatform
from litex.build.generic_platform import Pins, Subsignal
class SimPins(Pins):
def __init__(self, n=1):
Pins.__init__(self, "s "*n)
_io = [
("sys_clk", 0, SimPins(1)),
("sys_rst", 0, SimPins(1)),
("serial", 0,
Subsignal("source_valid", SimPins()),
Subsignal("source_ready", SimPins()),
Subsignal("source_data", SimPins(8)),
Subsignal("sink_valid", SimPins()),
Subsignal("sink_ready", SimPins()),
Subsignal("sink_data", SimPins(8)),
),
("user_led", 0, SimPins(1)),
]
class Platform(SimPlatform):
default_clk_name = "sys_clk"
default_clk_period = 1000 # ~ 1MHz
def __init__(self):
SimPlatform.__init__(self, "SIM", _io)
def do_finalize(self, fragment, *args, **kwargs):
pass
| [
"litex.build.generic_platform.Pins.__init__",
"litex.build.sim.SimPlatform.__init__"
] | [((157, 186), 'litex.build.generic_platform.Pins.__init__', 'Pins.__init__', (['self', "('s ' * n)"], {}), "(self, 's ' * n)\n", (170, 186), False, 'from litex.build.generic_platform import Pins, Subsignal\n'), ((728, 766), 'litex.build.sim.SimPlatform.__init__', 'SimPlatform.__init__', (['self', '"""SIM"""', '_io'], {}), "(self, 'SIM', _io)\n", (748, 766), False, 'from litex.build.sim import SimPlatform\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("sysclk", 0, Pins("H16"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("R14"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("P14"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("N16"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("M14"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("L15"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("G17"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("N15"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("G14"), IOStandard("LVCMOS33")),
("user_led", 8, Pins("L14"), IOStandard("LVCMOS33")),
("user_led", 9, Pins("M15"), IOStandard("LVCMOS33")),
# Switches
("user_sw", 0, Pins("M20"), IOStandard("LVCMOS33")),
("user_sw", 1, Pins("M19"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("D19"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("D20"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("tx", Pins("pmoda:0")),
Subsignal("rx", Pins("pmoda:1")),
IOStandard("LVCMOS33")
),
# Audio
("aud_pwm", 0, Pins("R18"), IOStandard("LVCMOS33")),
("aud_sd", 0, Pins("T17"), IOStandard("LVCMOS33")),
("m_clk", 0, Pins("F17"), IOStandard("LVCMOS33")),
("m_data", 0, Pins("G18"), IOStandard("LVCMOS33")),
# Chipkit Single Ended Analog Input
("ck_an_n", 0, Pins("D18"), IOStandard("LVCMOS33")),
("ck_an_p", 0, Pins("E17"), IOStandard("LVCMOS33")),
("ck_an_n", 1, Pins("E19"), IOStandard("LVCMOS33")),
("ck_an_p", 1, Pins("E18"), IOStandard("LVCMOS33")),
("ck_an_n", 2, Pins("J14"), IOStandard("LVCMOS33")),
("ck_an_p", 2, Pins("K14"), IOStandard("LVCMOS33")),
("ck_an_n", 3, Pins("J16"), IOStandard("LVCMOS33")),
("ck_an_p", 3, Pins("K16"), IOStandard("LVCMOS33")),
("ck_an_n", 4, Pins("H20"), IOStandard("LVCMOS33")),
("ck_an_p", 4, Pins("J20"), IOStandard("LVCMOS33")),
("ck_an_n", 5, Pins("G20"), IOStandard("LVCMOS33")),
("ck_an_p", 5, Pins("G19"), IOStandard("LVCMOS33")),
# Chipkit SPI
("ck_miso", 0, Pins("W15"), IOStandard("LVCMOS33")),
("ck_mosi", 0, Pins("T12"), IOStandard("LVCMOS33")),
("ck_sck", 0, Pins("H15"), IOStandard("LVCMOS33")),
("ck_ss", 0, Pins("F16"), IOStandard("LVCMOS33")),
# Chipkit I2C
("ck_scl", 0, Pins("P16"), IOStandard("LVCMOS33")),
("ck_sda", 0, Pins("P15"), IOStandard("LVCMOS33")),
# Crypto SDA
("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")),
]
_ps7_io = [
# PS7
("ps7_clk", 0, Pins("E7")),
("ps7_porb", 0, Pins("C7")),
("ps7_srstb", 0, Pins("B10")),
("ps7_mio", 0, Pins(
" E6 A7 B8 D6 B7 A6 A5 D8",
" D5 B5 E9 C6 D9 E8 C5 C8",
"A19 E14 B18 D10 A17 F14 B17 D11",
"A16 F15 A15 D13 C16 C13 C15 E16",
"A14 D15 A12 F12 A11 A10 E13 C18"
"D14 C17 E12 A9 F13 B15 D16 B14"
"B12 C12 B13 B9 C10 C11")),
("ps7_ddram", 0,
Subsignal("addr", Pins(
"N2 K2 M3 K3 M4 L1 L4 K4",
"K1 J4 F5 G4 E4 D4 F4")),
Subsignal("ba", Pins("L5 R4 J5")),
Subsignal("cas_n", Pins("P5")),
Subsignal("cke", Pins("N3")),
Subsignal("ck_n", Pins("M2")),
Subsignal("ck_p", Pins("L2")),
Subsignal("cs_n", Pins("N1")),
Subsignal("dm", Pins("A1 F1 T1 Y1")),
Subsignal("dq", Pins(
"C3 B3 A2 A4 D3 D1 C1 E1",
"E2 E3 G3 H3 J3 H2 H1 J1",
"P1 P3 R3 R1 T4 U4 U2 U3",
"V1 Y3 W1 Y4 Y2 W3 V2 V3"),
),
Subsignal("dqs_n", Pins("B2 F2 T2 W4")),
Subsignal("dqs_p", Pins("C2 G2 R2 W5")),
Subsignal("reset_n", Pins("B4")),
Subsignal("odt", Pins("N5")),
Subsignal("ras_n", Pins("P4")),
Subsignal("vrn", Pins("G5")),
Subsignal("vrp", Pins("H5")),
Subsignal("we_n", Pins("M5"))
),
]
_hdmi_rx_io = [
# HDMI Rx
("hdmi_rx", 0,
Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("N18"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")),
Subsignal("hpd", Pins("T19"), IOStandard("LVCMOS33")),
Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")),
),
]
_hdmi_tx_io = [
# HDMI Tx
("hdmi_tx", 0,
Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")),
Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")),
Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")),
Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")),
Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")),
Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")),
Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")),
Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")),
Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")),
Subsignal("hpdn", Pins("R19"), IOStandard("LVCMOS33")),
Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")),
Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")),
),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
("pmoda", "Y18 Y19 Y16 Y17 U18 U19 W18 W19"), # XADC
("pmodb", "W14 Y14 T11 T10 V16 W16 V12 W13"),
("ck_io", "T14 U12 U13 V13 V15 T15 R16 U17 V17 V18 T16 R17 P18 N17 Y11 Y12 W11 V11 T5 U10 B20 C20 F20 F19 A20 B19 U5 V5 V6 U7 V7 U8 V8 V10 W10 W6 Y6 Y7 W8 Y8 W9 Y9 Y13")
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "sysclk"
default_clk_period = 1e9/125e6
def __init__(self):
XilinxPlatform.__init__(self, "xc7z020-clg400-1", _io, _connectors, toolchain="vivado")
self.add_extension(_ps7_io)
self.add_extension(_hdmi_rx_io)
self.add_extension(_hdmi_tx_io)
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("sysclk", loose=True), 1e9/125e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((6738, 6829), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc7z020-clg400-1"""', '_io', '_connectors'], {'toolchain': '"""vivado"""'}), "(self, 'xc7z020-clg400-1', _io, _connectors,\n toolchain='vivado')\n", (6761, 6829), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((6992, 7010), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (7008, 7010), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((7057, 7099), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (7083, 7099), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform
_io = [
# clock
("clk25", 0, Pins("M9"), IOStandard("LVCMOS33")),
# led
("user_led", 0, Pins("F7"), IOStandard("LVCMOS33")),
# button
("user_btn", 0, Pins("P4"), IOStandard("LVCMOS33")),
# serial
("serial", 0,
Subsignal("tx", Pins("H5")),
Subsignal("rx", Pins("G6")),
IOStandard("LVCMOS33")
),
# ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("D1")),
Subsignal("rx", Pins("F1")),
IOStandard("LVCMOS33")
),
("eth", 0,
Subsignal("rx_ctl", Pins("H1")),
Subsignal("rx_data", Pins("F2 F4 G1 G3")),
Subsignal("tx_ctl", Pins("E4")),
Subsignal("tx_data", Pins("E3 E2 E1 F3")),
IOStandard("LVCMOS33")
),
("eth_clocks", 1,
Subsignal("tx", Pins("J1")),
Subsignal("rx", Pins("J3")),
IOStandard("LVCMOS33")
),
("eth", 1,
Subsignal("rx_ctl", Pins("M3")),
Subsignal("rx_data", Pins("L1 L3 M1 M2")),
Subsignal("tx_ctl", Pins("E4")),
Subsignal("tx_data", Pins("I3 K1 K2 H3")),
IOStandard("LVCMOS33")
),
# sdram
("sdram_clock", 0, Pins("K11"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("sdram_clock", 1, Pins("K12"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
("sdram", 0,
Subsignal("a", Pins("L16 M14 M16 K14 J12 J13 J11 H13 H11 G12")),
Subsignal("dq", Pins(
"C15 C16 D14 E15 E16 F14 F16 G14",
"G11 E12 H14 G16 F15 D16 B16 B15",
"N16 P16 P15 R15 R16 R14 T14 R12",
"T12 T13 T15 M13 N14 M15 L12 L13")),
Subsignal("we_n", Pins("H16")),
Subsignal("ras_n", Pins("J14")),
Subsignal("cas_n", Pins("H15")),
Subsignal("cs_n", Pins("J16")),
Subsignal("ba", Pins("K16 K15")),
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
),
]
class Platform(XilinxPlatform):
default_clk_name = "clk25"
default_clk_period = 40.00
def __init__(self):
XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io)
| [
"litex.build.xilinx.XilinxPlatform.__init__"
] | [((2081, 2136), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xc6slx16-2-ftg256"""', '_io'], {}), "(self, 'xc6slx16-2-ftg256', _io)\n", (2104, 2136), False, 'from litex.build.xilinx import XilinxPlatform\n')] |
#!/usr/bin/env python3
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from migen import *
from litex.build.generic_platform import *
from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
from litex_boards.platforms import spartan_edge_accelerator
from litex.soc.cores.clock import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser,WS2812
from litex.soc.cores.video import *
# Serial Port --------------------------------------------------------------------------------------
_serial_io = [
# Use J10 connectors 0/1 IOs + GND.
("serial", 0,
Subsignal("tx", Pins("j10:j10_0")),
Subsignal("rx", Pins("j10:j10_1")),
IOStandard("LVCMOS33")
),
]
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
def __init__(self, platform, sys_clk_freq, with_video_pll):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_hdmi = ClockDomain()
self.clock_domains.cd_hdmi5x = ClockDomain()
# # #
clk100 = platform.request("clk100")
rst_n = platform.request("rst_n")
self.submodules.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~rst_n | self.rst)
pll.register_clkin(clk100, sys_clk_freq)
pll.create_clkout(self.cd_sys, sys_clk_freq)
if with_video_pll:
self.submodules.video_pll = video_pll = S7PLL(speedgrade=-1)
video_pll.reset.eq(~rst_n | self.rst)
video_pll.register_clkin(clk100, 100e6)
video_pll.create_clkout(self.cd_hdmi, 25e6)
video_pll.create_clkout(self.cd_hdmi5x, 5*25e6)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(100e6),
with_led_chaser = True,
with_jtagbone = False,
with_video_terminal = True,
with_neopixel = False,
**kwargs):
platform = spartan_edge_accelerator.Platform()
platform.add_extension(_serial_io)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, sys_clk_freq,
ident = "LiteX SoC on Seeedstudio Spartan Edge Accelerator",
**kwargs)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
# Jtagbone ---------------------------------------------------------------------------------
if with_jtagbone:
self.add_jtagbone()
# Leds -------------------------------------------------------------------------------------
if with_led_chaser:
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq
)
# Video ------------------------------------------------------------------------------------
if with_video_terminal:
self.submodules.videophy = VideoHDMIPHY(platform.request("hdmi"), clock_domain="hdmi")
self.add_video_colorbars(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi")
#self.add_video_terminal(phy=self.videophy, timings="640x480@75Hz", clock_domain="hdmi") #Fixme Not enough BRAM
# Neopixel ---------------------------------------------------------------------------------
# To test Nexpixel with LiteX BIOS:
# - mem_list (to get ws2812_base).
# - mem_write <ws2812_base> 0x00100000
if with_neopixel:
self.submodules.ws2812 = WS2812(platform.request("rgb"), nleds=2, sys_clk_freq=sys_clk_freq)
self.bus.add_slave(name="ws2812", slave=self.ws2812.bus, region=SoCRegion(size=2*4))
# Build --------------------------------------------------------------------------------------------
def main():
from litex.soc.integration.soc import LiteXSoCArgumentParser
parser = LiteXSoCArgumentParser(description="LiteX SoC on Spartan Edge Accelerator")
target_group = parser.add_argument_group(title="Target options")
target_group.add_argument("--build", action="store_true", help="Build bitstream.")
target_group.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")
target_group.add_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.")
target_group.add_argument("--with-video-terminal", action="store_true", help="Enable Video Colorbars (HDMI).")
target_group.add_argument("--with-neopixel", action="store_true", help="Enable onboard 2 Neopixels Leds.")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_jtagbone = args.with_jtagbone,
with_video_terminal = args.with_video_terminal,
with_neopixel = args.with_neopixel,
**soc_core_argdict(args)
)
builder = Builder(soc, **builder_argdict(args))
builder_kwargs = vivado_build_argdict(args)
builder.build(**builder_kwargs, run=args.build)
if __name__ == "__main__":
main()
| [
"litex.build.xilinx.vivado.vivado_build_args",
"litex.soc.integration.soc.SoCRegion",
"litex.build.xilinx.vivado.vivado_build_argdict",
"litex.soc.integration.soc.LiteXSoCArgumentParser"
] | [((4410, 4485), 'litex.soc.integration.soc.LiteXSoCArgumentParser', 'LiteXSoCArgumentParser', ([], {'description': '"""LiteX SoC on Spartan Edge Accelerator"""'}), "(description='LiteX SoC on Spartan Edge Accelerator')\n", (4432, 4485), False, 'from litex.soc.integration.soc import LiteXSoCArgumentParser\n'), ((5166, 5191), 'litex.build.xilinx.vivado.vivado_build_args', 'vivado_build_args', (['parser'], {}), '(parser)\n', (5183, 5191), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((5572, 5598), 'litex.build.xilinx.vivado.vivado_build_argdict', 'vivado_build_argdict', (['args'], {}), '(args)\n', (5592, 5598), False, 'from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict\n'), ((2300, 2335), 'litex_boards.platforms.spartan_edge_accelerator.Platform', 'spartan_edge_accelerator.Platform', ([], {}), '()\n', (2333, 2335), False, 'from litex_boards.platforms import spartan_edge_accelerator\n'), ((4196, 4217), 'litex.soc.integration.soc.SoCRegion', 'SoCRegion', ([], {'size': '(2 * 4)'}), '(size=2 * 4)\n', (4205, 4217), False, 'from litex.soc.integration.soc import SoCRegion\n')] |
import os
import sys
import argparse
import shutil
import pathlib
from litex.soc.integration.builder import Builder
import platform
import trigger
def main():
parser = argparse.ArgumentParser(description="")
parser.add_argument("--load", action="store_true", help="Load bitstream")
args = parser.parse_args()
soc = platform.BaseSoC()
soc.submodules.rgb = platform.RGBLed(soc.platform.request("rgb_led"))
soc.add_csr("rgb")
## Create a 1 kHz clock (1 ms) so that register
## settings are in ms instead of 1/6 us intervals
soc.submodules.wall = trigger.ClockDivider(12000)
io = [soc.platform.request("bank0", num) for num in range(8)]
soc.submodules.trigger = trigger.TriggerController(soc.wall.strobe, 8, io)
soc.add_csr("trigger")
builder = Builder(soc, output_dir="build", csr_csv="build/csr.csv", compile_software=False)
builder.build()
binfile = os.path.join(builder.gateware_dir, soc.build_name + ".bin")
csrfile = os.path.join(builder.gateware_dir, "..", "csr.csv")
gen_dir = os.path.join(pathlib.Path(__file__).parent.absolute(), "..", "generated")
print("Bitstream : {}".format(binfile))
shutil.copy(binfile, gen_dir)
shutil.copy(csrfile, gen_dir)
if __name__ == "__main__":
main() | [
"litex.soc.integration.builder.Builder"
] | [((176, 215), 'argparse.ArgumentParser', 'argparse.ArgumentParser', ([], {'description': '""""""'}), "(description='')\n", (199, 215), False, 'import argparse\n'), ((338, 356), 'platform.BaseSoC', 'platform.BaseSoC', ([], {}), '()\n', (354, 356), False, 'import platform\n'), ((589, 616), 'trigger.ClockDivider', 'trigger.ClockDivider', (['(12000)'], {}), '(12000)\n', (609, 616), False, 'import trigger\n'), ((718, 767), 'trigger.TriggerController', 'trigger.TriggerController', (['soc.wall.strobe', '(8)', 'io'], {}), '(soc.wall.strobe, 8, io)\n', (743, 767), False, 'import trigger\n'), ((810, 896), 'litex.soc.integration.builder.Builder', 'Builder', (['soc'], {'output_dir': '"""build"""', 'csr_csv': '"""build/csr.csv"""', 'compile_software': '(False)'}), "(soc, output_dir='build', csr_csv='build/csr.csv', compile_software=\n False)\n", (817, 896), False, 'from litex.soc.integration.builder import Builder\n'), ((927, 986), 'os.path.join', 'os.path.join', (['builder.gateware_dir', "(soc.build_name + '.bin')"], {}), "(builder.gateware_dir, soc.build_name + '.bin')\n", (939, 986), False, 'import os\n'), ((1001, 1052), 'os.path.join', 'os.path.join', (['builder.gateware_dir', '""".."""', '"""csr.csv"""'], {}), "(builder.gateware_dir, '..', 'csr.csv')\n", (1013, 1052), False, 'import os\n'), ((1196, 1225), 'shutil.copy', 'shutil.copy', (['binfile', 'gen_dir'], {}), '(binfile, gen_dir)\n', (1207, 1225), False, 'import shutil\n'), ((1230, 1259), 'shutil.copy', 'shutil.copy', (['csrfile', 'gen_dir'], {}), '(csrfile, gen_dir)\n', (1241, 1259), False, 'import shutil\n'), ((1081, 1103), 'pathlib.Path', 'pathlib.Path', (['__file__'], {}), '(__file__)\n', (1093, 1103), False, 'import pathlib\n')] |
# This file is Copyright (c) 2019 <NAME> <<EMAIL>>
# License: BSD
import unittest
from migen import *
from litex.soc.cores.spi import SPIMaster, SPISlave
class TestSPI(unittest.TestCase):
def test_spi_master_syntax(self):
spi_master = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6)
self.assertEqual(hasattr(spi_master, "pads"), 1)
def test_spi_master_xfer_loopback(self):
def generator(dut):
yield dut.loopback.eq(1)
yield dut.mosi.eq(0xdeadbeef)
yield dut.length.eq(32)
yield dut.start.eq(1)
yield
yield dut.start.eq(0)
yield
while (yield dut.done) == 0:
yield
self.assertEqual((yield dut.miso), 0xdeadbeef)
dut = SPIMaster(pads=None, data_width=32, sys_clk_freq=100e6, spi_clk_freq=5e6, with_csr=False)
run_simulation(dut, generator(dut))
def test_spi_slave_syntax(self):
spi_slave = SPISlave(pads=None, data_width=32)
self.assertEqual(hasattr(spi_slave, "pads"), 1)
def test_spi_slave_xfer(self):
class DUT(Module):
def __init__(self):
pads = Record([("clk", 1), ("cs_n", 1), ("mosi", 1), ("miso", 1)])
self.submodules.master = SPIMaster(pads, data_width=32,
sys_clk_freq=100e6, spi_clk_freq=5e6,
with_csr=False)
self.submodules.slave = SPISlave(pads, data_width=32)
def master_generator(dut):
yield dut.master.mosi.eq(0xdeadbeef)
yield dut.master.length.eq(32)
yield dut.master.start.eq(1)
yield
yield dut.master.start.eq(0)
yield
while (yield dut.master.done) == 0:
yield
self.assertEqual((yield dut.master.miso), 0x12345678)
def slave_generator(dut):
yield dut.slave.miso.eq(0x12345678)
while (yield dut.slave.start) == 0:
yield
while (yield dut.slave.done) == 0:
yield
self.assertEqual((yield dut.slave.mosi), 0xdeadbeef)
self.assertEqual((yield dut.slave.length), 32)
dut = DUT()
run_simulation(dut, [master_generator(dut), slave_generator(dut)])
| [
"litex.soc.cores.spi.SPIMaster",
"litex.soc.cores.spi.SPISlave"
] | [((252, 342), 'litex.soc.cores.spi.SPIMaster', 'SPIMaster', ([], {'pads': 'None', 'data_width': '(32)', 'sys_clk_freq': '(100000000.0)', 'spi_clk_freq': '(5000000.0)'}), '(pads=None, data_width=32, sys_clk_freq=100000000.0, spi_clk_freq=\n 5000000.0)\n', (261, 342), False, 'from litex.soc.cores.spi import SPIMaster, SPISlave\n'), ((813, 919), 'litex.soc.cores.spi.SPIMaster', 'SPIMaster', ([], {'pads': 'None', 'data_width': '(32)', 'sys_clk_freq': '(100000000.0)', 'spi_clk_freq': '(5000000.0)', 'with_csr': '(False)'}), '(pads=None, data_width=32, sys_clk_freq=100000000.0, spi_clk_freq=\n 5000000.0, with_csr=False)\n', (822, 919), False, 'from litex.soc.cores.spi import SPIMaster, SPISlave\n'), ((1005, 1039), 'litex.soc.cores.spi.SPISlave', 'SPISlave', ([], {'pads': 'None', 'data_width': '(32)'}), '(pads=None, data_width=32)\n', (1013, 1039), False, 'from litex.soc.cores.spi import SPIMaster, SPISlave\n'), ((1315, 1416), 'litex.soc.cores.spi.SPIMaster', 'SPIMaster', (['pads'], {'data_width': '(32)', 'sys_clk_freq': '(100000000.0)', 'spi_clk_freq': '(5000000.0)', 'with_csr': '(False)'}), '(pads, data_width=32, sys_clk_freq=100000000.0, spi_clk_freq=\n 5000000.0, with_csr=False)\n', (1324, 1416), False, 'from litex.soc.cores.spi import SPIMaster, SPISlave\n'), ((1481, 1510), 'litex.soc.cores.spi.SPISlave', 'SPISlave', (['pads'], {'data_width': '(32)'}), '(pads, data_width=32)\n', (1489, 1510), False, 'from litex.soc.cores.spi import SPIMaster, SPISlave\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk / Rst
("clk125", 0,
Subsignal("p", Pins("G21"), IOStandard("LVDS")),
Subsignal("n", Pins("F21"), IOStandard("LVDS")),
),
("clk300", 0,
Subsignal("p", Pins("AL8"), IOStandard("DIFF_SSTL12_DCI")),
Subsignal("n", Pins("AL7"), IOStandard("DIFF_SSTL12_DCI")),
),
("cpu_reset", 0, Pins("AM13"), IOStandard("LVCMOS33")),
# Leds
("user_led", 0, Pins("AG14"), IOStandard("LVCMOS33")),
("user_led", 1, Pins("AF13"), IOStandard("LVCMOS33")),
("user_led", 2, Pins("AE13"), IOStandard("LVCMOS33")),
("user_led", 3, Pins("AJ14"), IOStandard("LVCMOS33")),
("user_led", 4, Pins("AJ15"), IOStandard("LVCMOS33")),
("user_led", 5, Pins("AH13"), IOStandard("LVCMOS33")),
("user_led", 6, Pins("AH14"), IOStandard("LVCMOS33")),
("user_led", 7, Pins("AL12"), IOStandard("LVCMOS33")),
# Buttons
("user_btn", 0, Pins("AG15"), IOStandard("LVCMOS33")),
("user_btn", 1, Pins("AE14"), IOStandard("LVCMOS33")),
("user_btn", 2, Pins("AF15"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("AE15"), IOStandard("LVCMOS33")),
("user_btn", 3, Pins("AG13"), IOStandard("LVCMOS33")),
# Switches
("user_dip", 0, Pins("AN14"), IOStandard("LVCMOS33")),
("user_dip", 1, Pins("AP14"), IOStandard("LVCMOS33")),
("user_dip", 2, Pins("AM14"), IOStandard("LVCMOS33")),
("user_dip", 3, Pins("AN13"), IOStandard("LVCMOS33")),
("user_dip", 4, Pins("AN12"), IOStandard("LVCMOS33")),
("user_dip", 5, Pins("AP12"), IOStandard("LVCMOS33")),
("user_dip", 6, Pins("AL13"), IOStandard("LVCMOS33")),
("user_dip", 7, Pins("AK13"), IOStandard("LVCMOS33")),
# Serial
("serial", 0,
Subsignal("cts", Pins("E12")),
Subsignal("rts", Pins("D12")),
Subsignal("tx", Pins("E13")),
Subsignal("rx", Pins("F13")),
IOStandard("LVCMOS18")
),
# I2C
("i2c", 0,
Subsignal("sda", Pins("J11")),
Subsignal("scl", Pins("J10")),
IOStandard("LVCMOS33")
),
]
# Platform -----------------------------------------------------------------------------------------
class Platform(XilinxPlatform):
default_clk_name = "clk125"
default_clk_period = 1e9/125e6
def __init__(self, toolchain="vivado"):
XilinxPlatform.__init__(self, "xczu9eg-ffvb1156-2-i", _io, toolchain=toolchain)
def create_programmer(self):
return VivadoProgrammer()
def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk125", loose=True), 1e9/125e6)
self.add_period_constraint(self.lookup_request("clk300", loose=True), 1e9/300e6)
| [
"litex.build.xilinx.XilinxPlatform.__init__",
"litex.build.xilinx.VivadoProgrammer",
"litex.build.xilinx.XilinxPlatform.do_finalize"
] | [((2625, 2704), 'litex.build.xilinx.XilinxPlatform.__init__', 'XilinxPlatform.__init__', (['self', '"""xczu9eg-ffvb1156-2-i"""', '_io'], {'toolchain': 'toolchain'}), "(self, 'xczu9eg-ffvb1156-2-i', _io, toolchain=toolchain)\n", (2648, 2704), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((2754, 2772), 'litex.build.xilinx.VivadoProgrammer', 'VivadoProgrammer', ([], {}), '()\n', (2770, 2772), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n'), ((2819, 2861), 'litex.build.xilinx.XilinxPlatform.do_finalize', 'XilinxPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (2845, 2861), False, 'from litex.build.xilinx import XilinxPlatform, VivadoProgrammer\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2015-2019 <NAME> <<EMAIL>>
# Copyright (c) 2019 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from math import log2
from migen import *
from migen.genlib.roundrobin import *
from migen.genlib.record import *
from migen.genlib.fsm import FSM, NextState
from litex.gen import *
from litex.soc.interconnect import stream
# Status -------------------------------------------------------------------------------------------
class Status(Module):
def __init__(self, endpoint):
self.first = Signal(reset=1)
self.last = Signal()
self.ongoing = Signal()
ongoing = Signal()
self.comb += If(endpoint.valid, self.last.eq(endpoint.last & endpoint.ready))
self.sync += ongoing.eq((endpoint.valid | ongoing) & ~self.last)
self.comb += self.ongoing.eq((endpoint.valid | ongoing) & ~self.last)
self.sync += [
If(self.last,
self.first.eq(1)
).Elif(endpoint.valid & endpoint.ready,
self.first.eq(0)
)
]
# Arbiter ------------------------------------------------------------------------------------------
class Arbiter(Module):
def __init__(self, masters, slave):
if len(masters) == 0:
pass
elif len(masters) == 1:
self.grant = Signal()
self.comb += masters.pop().connect(slave)
else:
self.submodules.rr = RoundRobin(len(masters))
self.grant = self.rr.grant
cases = {}
for i, master in enumerate(masters):
status = Status(master)
self.submodules += status
self.comb += self.rr.request[i].eq(status.ongoing)
cases[i] = [master.connect(slave)]
self.comb += Case(self.grant, cases)
# Dispatcher ---------------------------------------------------------------------------------------
class Dispatcher(Module):
def __init__(self, master, slaves, one_hot=False):
if len(slaves) == 0:
self.sel = Signal()
elif len(slaves) == 1:
self.comb += master.connect(slaves.pop())
self.sel = Signal()
else:
if one_hot:
self.sel = Signal(len(slaves))
else:
self.sel = Signal(max=len(slaves))
# # #
status = Status(master)
self.submodules += status
sel = Signal.like(self.sel)
sel_ongoing = Signal.like(self.sel)
self.sync += [
If(status.first,
sel_ongoing.eq(self.sel)
)
]
self.comb += [
If(status.first,
sel.eq(self.sel)
).Else(
sel.eq(sel_ongoing)
)
]
cases = {}
for i, slave in enumerate(slaves):
if one_hot:
idx = 2**i
else:
idx = i
cases[idx] = [master.connect(slave)]
cases["default"] = [master.ready.eq(1)]
self.comb += Case(sel, cases)
# Header -------------------------------------------------------------------------------------------
class HeaderField:
def __init__(self, byte, offset, width):
self.byte = byte
self.offset = offset
self.width = width
class Header:
def __init__(self, fields, length, swap_field_bytes=True):
self.fields = fields
self.length = length
self.swap_field_bytes = swap_field_bytes
def get_layout(self):
layout = []
for k, v in sorted(self.fields.items()):
layout.append((k, v.width))
return layout
def get_field(self, obj, name, width):
if "_lsb" in name:
field = getattr(obj, name.replace("_lsb", ""))[:width]
elif "_msb" in name:
field = getattr(obj, name.replace("_msb", ""))[width:2*width]
else:
field = getattr(obj, name)
if len(field) != width:
raise ValueError("Width mismatch on " + name + " field")
return field
def encode(self, obj, signal):
r = []
for k, v in sorted(self.fields.items()):
start = v.byte*8 + v.offset
end = start + v.width
field = self.get_field(obj, k, v.width)
if self.swap_field_bytes:
field = reverse_bytes(field)
r.append(signal[start:end].eq(field))
return r
def decode(self, signal, obj):
r = []
for k, v in sorted(self.fields.items()):
start = v.byte*8 + v.offset
end = start + v.width
field = self.get_field(obj, k, v.width)
if self.swap_field_bytes:
r.append(field.eq(reverse_bytes(signal[start:end])))
else:
r.append(field.eq(signal[start:end]))
return r
# Packetizer ---------------------------------------------------------------------------------------
class Packetizer(Module):
def __init__(self, sink_description, source_description, header):
self.sink = sink = stream.Endpoint(sink_description)
self.source = source = stream.Endpoint(source_description)
self.header = Signal(header.length*8)
# # #
# Parameters.
data_width = len(self.sink.data)
bytes_per_clk = data_width//8
header_words = (header.length*8)//data_width
header_leftover = header.length%bytes_per_clk
aligned = header_leftover == 0
# Signals.
sr = Signal(header.length*8, reset_less=True)
sr_load = Signal()
sr_shift = Signal()
count = Signal(max=max(header_words, 2))
sink_d = stream.Endpoint(sink_description)
# Header Encode/Load/Shift.
self.comb += header.encode(sink, self.header)
self.sync += If(sr_load, sr.eq(self.header))
if header_words != 1:
self.sync += If(sr_shift, sr.eq(sr[data_width:]))
# FSM.
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm_from_idle = Signal()
fsm.act("IDLE",
sink.ready.eq(1),
NextValue(count, 1),
If(sink.valid,
sink.ready.eq(0),
source.valid.eq(1),
source.last.eq(0),
source.data.eq(self.header[:data_width]),
If(source.valid & source.ready,
sr_load.eq(1),
NextValue(fsm_from_idle, 1),
If(header_words == 1,
NextState("ALIGNED-DATA-COPY" if aligned else "UNALIGNED-DATA-COPY")
).Else(
NextState("HEADER-SEND")
)
)
)
)
fsm.act("HEADER-SEND",
source.valid.eq(1),
source.last.eq(0),
source.data.eq(sr[min(data_width, len(sr)-1):]),
If(source.valid & source.ready,
sr_shift.eq(1),
If(count == (header_words - 1),
sr_shift.eq(0),
NextState("ALIGNED-DATA-COPY" if aligned else "UNALIGNED-DATA-COPY"),
NextValue(count, count + 1)
).Else(
NextValue(count, count + 1),
)
)
)
fsm.act("ALIGNED-DATA-COPY",
source.valid.eq(sink.valid),
source.last.eq(sink.last),
source.data.eq(sink.data),
If(source.valid & source.ready,
sink.ready.eq(1),
If(source.last,
NextState("IDLE")
)
)
)
if not aligned:
header_offset_multiplier = 1 if header_words == 1 else 2
self.sync += If(source.ready, sink_d.eq(sink))
fsm.act("UNALIGNED-DATA-COPY",
source.valid.eq(sink.valid | sink_d.last),
source.last.eq(sink_d.last),
If(fsm_from_idle,
source.data[:max(header_leftover*8, 1)].eq(sr[min(header_offset_multiplier*data_width, len(sr)-1):])
).Else(
source.data[:max(header_leftover*8, 1)].eq(sink_d.data[min((bytes_per_clk-header_leftover)*8, data_width-1):])
),
source.data[header_leftover*8:].eq(sink.data),
If(source.valid & source.ready,
sink.ready.eq(~source.last),
NextValue(fsm_from_idle, 0),
If(source.last,
NextState("IDLE")
)
)
)
# Last BE.
# FIXME: Switch to a simpler Data Qualifier and remove Last BE handling/section.
if hasattr(sink, "last_be") and hasattr(source, "last_be"):
# For an 8-bit data path, last_be really should be 1 when last is
# asserted, other values do not make sense. However, legacy code
# might not set last_be at all, and thus it will be set to 0. To
# remain compatible with this code, this "corrects" last_be for
# 8-bit paths by setting it to the value of last.
if len(sink.last_be) == 1:
sink_last_be = Signal.like(sink.last_be)
self.comb += [ sink_last_be.eq(sink.last) ]
else:
sink_last_be = sink.last_be
# last_be needs to be right-rotated by the number of bytes which
# would be required to have a properly aligned header.
right_rot_by = header_leftover
# Calculate a rotated last_be
new_last_be = Signal.like(sink_last_be)
self.comb += [
new_last_be.eq(Cat([
sink_last_be[(i - right_rot_by) % bytes_per_clk]
for i in range(bytes_per_clk)
]))
]
# Conditionally delay the calculated last_be for one clock cycle, if
# it now applies to the next bus word OR if the source is not ready.
delayed_last_be = Signal.like(sink_last_be)
# FSM used to conveniently assign combinational and synchronous
# signals in the same context.
self.submodules.last_be_fsm = last_be_fsm = FSM(reset_state="DEFAULT")
# Whether the main FSM is in one of the DATA-COPY states. This is
# important as we overwrite sink.ready below and need to have
# different behavior depending on the Packetizer's state
in_data_copy = Signal()
self.comb += [
in_data_copy.eq(self.fsm.ongoing("ALIGNED-DATA-COPY") | self.fsm.ongoing("UNALIGNED-DATA-COPY"))
]
self.last_be_fsm.act("DEFAULT",
# Test whether our right-shift causes a wrap-around. In that
# case apply the last value to the current bus word. Otherwise
# delay it to the next.
If(in_data_copy & sink.last & (sink_last_be > new_last_be),
# Right shift did not wrap around, need to delay the
# calculated last_be value and last by one cycle.
source.last.eq(0),
source.last_be.eq(0),
If(source.ready & source.valid,
NextValue(delayed_last_be, new_last_be),
NextState("DELAYED"),
),
).Elif(in_data_copy,
# Output the calculated last_be value on the current packet
# already. For the next sink packet, ignore any last_be
source.last.eq(sink.last),
source.last_be.eq(new_last_be),
),
If(in_data_copy,
sink.ready.eq(source.ready),
).Elif(self.fsm.ongoing("IDLE"),
sink.ready.eq(~sink.valid),
)
)
self.last_be_fsm.act("DELAYED",
# Output the delayed last and last_be signals
source.last.eq(1),
source.last_be.eq(delayed_last_be),
sink.ready.eq(0),
If(source.ready,
NextState("DEFAULT"),
),
)
# Error.
if hasattr(sink, "error") and hasattr(source, "error"):
self.comb += source.error.eq(sink.error)
# Depacketizer -------------------------------------------------------------------------------------
class Depacketizer(Module):
def __init__(self, sink_description, source_description, header):
self.sink = sink = stream.Endpoint(sink_description)
self.source = source = stream.Endpoint(source_description)
self.header = Signal(header.length*8)
# # #
# Parameters.
data_width = len(sink.data)
bytes_per_clk = data_width//8
header_words = (header.length*8)//data_width
header_leftover = header.length%bytes_per_clk
aligned = header_leftover == 0
# Signals.
sr = Signal(header.length*8, reset_less=True)
sr_shift = Signal()
sr_shift_leftover = Signal()
count = Signal(max=max(header_words, 2))
sink_d = stream.Endpoint(sink_description)
# Header Shift/Decode.
if (header_words) == 1 and (header_leftover == 0):
self.sync += If(sr_shift, sr.eq(sink.data))
else:
self.sync += [
If(sr_shift, sr.eq(Cat(sr[bytes_per_clk*8:], sink.data))),
If(sr_shift_leftover, sr.eq(Cat(sr[header_leftover*8:], sink.data)))
]
self.comb += self.header.eq(sr)
self.comb += header.decode(self.header, source)
# FSM.
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm_from_idle = Signal()
fsm.act("IDLE",
sink.ready.eq(1),
NextValue(count, 1),
If(sink.valid,
sr_shift.eq(1),
NextValue(fsm_from_idle, 1),
If(header_words == 1,
NextState("ALIGNED-DATA-COPY" if aligned else "UNALIGNED-DATA-COPY"),
).Else(
NextState("HEADER-RECEIVE")
)
)
)
fsm.act("HEADER-RECEIVE",
sink.ready.eq(1),
If(sink.valid,
NextValue(count, count + 1),
sr_shift.eq(1),
If(count == (header_words - 1),
NextState("ALIGNED-DATA-COPY" if aligned else "UNALIGNED-DATA-COPY"),
NextValue(count, count + 1),
)
)
)
fsm.act("ALIGNED-DATA-COPY",
source.valid.eq(sink.valid | sink_d.last),
source.last.eq(sink.last | sink_d.last),
sink.ready.eq(source.ready),
source.data.eq(sink.data),
If(source.valid & source.ready,
If(source.last,
NextState("IDLE")
)
)
)
if not aligned:
self.sync += If(sink.valid & sink.ready, sink_d.eq(sink))
fsm.act("UNALIGNED-DATA-COPY",
source.valid.eq(sink.valid | sink_d.last),
source.last.eq(sink.last | sink_d.last),
sink.ready.eq(source.ready),
source.data.eq(sink_d.data[header_leftover*8:]),
source.data[min((bytes_per_clk-header_leftover)*8, data_width-1):].eq(sink.data),
If(fsm_from_idle,
source.valid.eq(sink_d.last),
sink.ready.eq(1),
If(sink.valid,
NextValue(fsm_from_idle, 0),
sr_shift_leftover.eq(1),
)
),
If(source.valid & source.ready,
If(source.last,
NextState("IDLE")
)
)
)
# Error.
if hasattr(sink, "error") and hasattr(source, "error"):
self.comb += source.error.eq(sink.error)
# Last BE.
# FIXME: Switch to a simpler Data Qualifier and remove Last BE handling/section.
if hasattr(sink, "last_be") and hasattr(source, "last_be"):
# For an 8-bit data path, last_be really should be 1 when last is
# asserted, other values do not make sense. However, legacy code
# might not set last_be at all, and thus it will be set to 0. To
# remain compatible with this code, this "corrects" last_be for
# 8-bit paths by setting it to the value of last.
if len(sink.last_be) == 1:
sink_last_be = Signal.like(sink.last_be)
self.comb += [ sink_last_be.eq(sink.last) ]
else:
sink_last_be = sink.last_be
# last_be needs to be left-rotated by the number of bytes which
# would be required to have a properly aligned header.
left_rot_by = (bytes_per_clk - header_leftover) % bytes_per_clk
# Calculate a rotated last_be
new_last_be = Signal.like(sink_last_be)
self.comb += [
new_last_be.eq(Cat([
sink_last_be[(i - left_rot_by) % bytes_per_clk]
for i in range(bytes_per_clk)
]))
]
# Conditionally delay the calculated last_be for one clock cycle, if
# it now applies to the next bus word.
delayed_last_be = Signal.like(sink_last_be)
# FSM used to conveniently assign combinational and synchronous
# signals in the same context.
self.submodules.last_be_fsm = last_be_fsm = FSM(reset_state="DEFAULT")
# Whether the main FSM is / was in one of the DATA-COPY states. This
# is important as we must handle a special case when last is
# asserted while the Depacketizer has just transitioned out of
# writing the header, which we can then detect by checking
# (~was_in_copy & is_in_copy).
is_in_copy = Signal()
was_in_copy = Signal()
self.comb += [
is_in_copy.eq(
self.fsm.ongoing("ALIGNED-DATA-COPY") | self.fsm.ongoing("UNALIGNED-DATA-COPY")
)
]
self.sync += [
was_in_copy.eq(is_in_copy)
]
self.last_be_fsm.act("DEFAULT",
# Test whether our left-shift has caused an wrap-around, in that
# case delay last and last_be and apply to the next bus word.
If(sink.valid & sink.last & (sink_last_be > new_last_be),
# last_be did wrap around. Need to delay the calculated
# last_be value and last by one cycle.
source.last.eq(0),
source.last_be.eq(0),
# Normally just wait until a source bus transaction occurred
# (ready + valid) until the delayed last_be can be
# output. However, if the first word is also the last, this
# will mean that the source isn't valid currently as the
# header is still being sent. Thus, if sink.valid and
# sink.last and we've just transitioned into the data copy
# phase, we can immediately jump into the DELAYED state (as
# the very first bus word containing proper data is also the
# last one, and we've just transitioned to putting that on
# the bus).
If((source.ready & source.valid) | (~was_in_copy & is_in_copy),
NextValue(delayed_last_be, new_last_be),
NextState("DELAYED"),
),
).Elif(sink.last,
# Simply forward the calculated last_be value.
source.last.eq(1),
source.last_be.eq(new_last_be),
),
If(self.fsm.ongoing("ALIGNED-DATA-COPY") \
| (self.fsm.ongoing("UNALIGNED-DATA-COPY") & ~fsm_from_idle),
sink.ready.eq(source.ready),
).Else(
sink.ready.eq(1),
),
)
self.last_be_fsm.act("DELAYED",
# Output the delayed last and last_be signals
source.last.eq(1),
source.last_be.eq(delayed_last_be),
sink.ready.eq(0),
If(source.ready & source.valid,
NextState("DEFAULT"),
),
)
# PacketFIFO ---------------------------------------------------------------------------------------
class PacketFIFO(Module):
def __init__(self, layout, payload_depth, param_depth=None, buffered=False):
self.sink = sink = stream.Endpoint(layout)
self.source = source = stream.Endpoint(layout)
# # #
# Parameters.
param_layout = sink.description.param_layout
payload_layout = sink.description.payload_layout
if param_layout == []:
param_layout = [("dummy", 1)]
if param_depth is None:
param_depth = payload_depth
# Create the FIFOs.
payload_description = stream.EndpointDescription(payload_layout=payload_layout)
param_description = stream.EndpointDescription(param_layout=param_layout)
self.submodules.payload_fifo = payload_fifo = stream.SyncFIFO(payload_description, payload_depth, buffered)
self.submodules.param_fifo = param_fifo = stream.SyncFIFO(param_description, param_depth, buffered)
# Connect Sink to FIFOs.
self.comb += [
sink.connect(param_fifo.sink, keep=set([e[0] for e in param_layout])),
sink.connect(payload_fifo.sink, keep=set([e[0] for e in payload_layout] + ["last"])),
param_fifo.sink.valid.eq(sink.valid & sink.last),
payload_fifo.sink.valid.eq(sink.valid & payload_fifo.sink.ready),
sink.ready.eq(param_fifo.sink.ready & payload_fifo.sink.ready),
]
# Connect FIFOs to Source.
self.comb += [
param_fifo.source.connect(source, omit={"last", "ready", "dummy"}),
payload_fifo.source.connect(source, omit={"valid", "ready"}),
param_fifo.source.ready.eq( source.valid & source.last & source.ready),
payload_fifo.source.ready.eq(source.valid & source.ready),
]
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"litex.soc.interconnect.stream.EndpointDescription",
"litex.soc.interconnect.stream.Endpoint"
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#
# This file is part of LiteX.
#
# Copyright (c) 2015-2022 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
import math
from migen import *
from migen.fhdl.specials import Tristate
from migen.genlib.cdc import MultiReg
from litex.soc.interconnect import stream
from litex.build.io import SDRTristate
# Layout/Helpers -----------------------------------------------------------------------------------
def phy_description(dw):
payload_layout = [("data", dw)]
return stream.EndpointDescription(payload_layout)
def anti_starvation(module, timeout):
en = Signal()
max_time = Signal()
if timeout:
t = timeout - 1
time = Signal(max=t+1)
module.comb += max_time.eq(time == 0)
module.sync += If(~en,
time.eq(t)
).Elif(~max_time,
time.eq(time - 1)
)
else:
module.comb += max_time.eq(0)
return en, max_time
# FT245 Synchronous FIFO Mode ----------------------------------------------------------------------
class FT245PHYSynchronous(Module):
# FIXME: Check/Improve sampling timings.
def __init__(self, pads, clk_freq,
fifo_depth = 64,
read_time = 128,
write_time = 128):
self.dw = dw = len(pads.data)
self.pads = pads
self.sink = stream.Endpoint(phy_description(dw))
self.source = stream.Endpoint(phy_description(dw))
# # #
# Pads Reset.
# -----------
pads.oe_n.reset = 1
pads.rd_n.reset = 1
pads.wr_n.reset = 1
# Read CDC/FIFO (FTDI --> SoC).
# -----------------------------
self.submodules.read_cdc = stream.ClockDomainCrossing(phy_description(dw),
cd_from = "usb",
cd_to = "sys",
with_common_rst = True
)
self.submodules.read_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
self.comb += self.read_cdc.source.connect(self.read_fifo.sink)
self.comb += self.read_fifo.source.connect(self.source)
read_fifo_almost_full = (self.read_fifo.level > (fifo_depth - 4))
read_fifo_almost_full_usb = Signal()
self.specials += MultiReg(read_fifo_almost_full, read_fifo_almost_full_usb)
# Write FIFO/CDC (SoC --> FTDI).
# ------------------------------
self.submodules.write_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
self.submodules.write_cdc = stream.ClockDomainCrossing(phy_description(dw),
cd_from = "sys",
cd_to = "usb",
with_common_rst = True
)
self.comb += self.sink.connect(self.write_fifo.sink)
self.comb += self.write_fifo.source.connect(self.write_cdc.sink)
# Read / Write Anti-Starvation.
# -----------------------------
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
# Read / Write Detection.
# -----------------------
self.wants_write = wants_write = Signal()
self.wants_read = wants_read = Signal()
self.comb += [
wants_write.eq(~pads.txe_n & self.write_cdc.source.valid),
wants_read.eq( ~pads.rxf_n & (self.read_cdc.sink.ready & ~read_fifo_almost_full_usb)),
]
# Data Bus Tristate.
# ------------------
self.data_w = data_w = Signal(dw)
self.data_r = data_r = Signal(dw)
self.data_oe = data_oe = Signal()
for i in range(dw):
self.specials += SDRTristate(
io = pads.data[i],
o = data_w[i],
oe = data_oe,
i = data_r[i],
clk = ClockSignal("usb")
)
if hasattr(pads, "be"):
for i in range(dw//8):
self.specials += SDRTristate(
io = pads.be[i],
o = Signal(reset=0b1),
oe = data_oe,
i = Signal(),
clk = ClockSignal("usb")
)
# Read / Write FSM.
# -----------------
fsm = FSM(reset_state="READ")
fsm = ClockDomainsRenamer("usb")(fsm)
self.submodules.fsm = fsm
fsm.act("READ",
# Arbitration.
read_time_en.eq(1),
If(wants_write,
If(~wants_read | max_read_time,
NextState("READ-TO-WRITE")
)
),
# Control/Data-Path.
data_oe.eq(0),
NextValue(pads.oe_n, ~wants_read),
NextValue(pads.rd_n, pads.oe_n | ~wants_read),
NextValue(pads.wr_n, 1),
)
self.comb += self.read_cdc.sink.data.eq(data_r)
self.sync.usb += self.read_cdc.sink.valid.eq(~pads.rd_n & ~pads.rxf_n)
fsm.act("READ-TO-WRITE",
NextState("WRITE")
)
fsm.act("WRITE",
# Arbitration.
write_time_en.eq(1),
If(wants_read,
If(~wants_write | max_write_time,
NextState("WRITE-TO-READ")
)
),
# Control/Data-Path.
data_oe.eq(1),
NextValue(pads.oe_n, 1),
NextValue(pads.rd_n, 1),
NextValue(pads.wr_n, ~wants_write),
#data_w.eq(write_fifo.source.data),
NextValue(data_w, self.write_cdc.source.data), # FIXME: Add 1 cycle delay.
self.write_cdc.source.ready.eq(wants_write),
)
fsm.act("WRITE-TO-READ",
NextState("READ")
)
def get_litescope_probes(self):
return [
# Physical.
self.pads.oe_n,
self.pads.rd_n,
self.pads.wr_n,
self.pads.txe_n,
self.pads.rxf_n,
self.data_w,
self.data_r,
self.data_oe,
# Core.
self.wants_write,
self.wants_read,
self.fsm,
# FIFOs.
self.write_fifo.source,
self.read_cdc.sink,
]
# FT245 Asynchronous FIFO Mode ---------------------------------------------------------------------
class FT245PHYAsynchronous(Module):
def __init__(self, pads, clk_freq,
fifo_depth = 8,
read_time = 128,
write_time = 128):
dw = len(pads.data)
self.clk_freq = clk_freq
# timings
tRD = self.ns(30) # RD# active pulse width (t4)
tRDDataSetup = self.ns(14) # RD# to DATA (t3)
tWRDataSetup = self.ns(5) # DATA to WR# active setup time (t8)
tWR = self.ns(30) # WR# active pulse width (t10)
tMultiReg = 2
# read fifo (FTDI --> SoC)
read_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
# write fifo (SoC --> FTDI)
write_fifo = stream.SyncFIFO(phy_description(dw), fifo_depth)
self.submodules += read_fifo, write_fifo
# sink / source interfaces
self.sink = write_fifo.sink
self.source = read_fifo.source
# read / write arbitration
wants_write = Signal()
wants_read = Signal()
txe_n = Signal()
rxf_n = Signal()
self.specials += [
MultiReg(pads.txe_n, txe_n),
MultiReg(pads.rxf_n, rxf_n)
]
self.comb += [
wants_write.eq(~txe_n & write_fifo.source.valid),
wants_read.eq(~rxf_n & read_fifo.sink.ready),
]
read_time_en, max_read_time = anti_starvation(self, read_time)
write_time_en, max_write_time = anti_starvation(self, write_time)
fsm = FSM(reset_state="READ")
self.submodules += fsm
read_done = Signal()
write_done = Signal()
commuting = Signal()
fsm.act("READ",
read_time_en.eq(1),
If(wants_write & read_done,
If(~wants_read | max_read_time,
commuting.eq(1),
NextState("RTW")
)
)
)
fsm.act("RTW",
NextState("WRITE")
)
fsm.act("WRITE",
write_time_en.eq(1),
If(wants_read & write_done,
If(~wants_write | max_write_time,
commuting.eq(1),
NextState("WTR")
)
)
)
fsm.act("WTR",
NextState("READ")
)
# databus tristate
data_w = Signal(dw)
data_r_async = Signal(dw)
data_r = Signal(dw)
data_oe = Signal()
self.specials += [
Tristate(pads.data, data_w, data_oe, data_r_async),
MultiReg(data_r_async, data_r)
]
# read actions
pads.rd_n.reset = 1
read_fsm = FSM(reset_state="IDLE")
self.submodules += read_fsm
read_counter = Signal(8)
read_fsm.act("IDLE",
read_done.eq(1),
NextValue(read_counter, 0),
If(fsm.ongoing("READ") & wants_read,
If(~commuting,
NextState("PULSE_RD_N")
)
)
)
read_fsm.act("PULSE_RD_N",
pads.rd_n.eq(0),
NextValue(read_counter, read_counter + 1),
If(read_counter == max(tRD-1, tRDDataSetup + tMultiReg -1),
NextState("ACQUIRE_DATA")
)
)
read_fsm.act("ACQUIRE_DATA",
read_fifo.sink.valid.eq(1),
read_fifo.sink.data.eq(data_r),
NextState("WAIT_RXF_N")
)
read_fsm.act("WAIT_RXF_N",
If(rxf_n,
NextState("IDLE")
)
)
# write actions
pads.wr_n.reset = 1
write_fsm = FSM(reset_state="IDLE")
self.submodules += write_fsm
write_counter = Signal(8)
write_fsm.act("IDLE",
write_done.eq(1),
NextValue(write_counter, 0),
If(fsm.ongoing("WRITE") & wants_write,
If(~commuting,
NextState("SET_DATA")
)
)
)
write_fsm.act("SET_DATA",
data_oe.eq(1),
data_w.eq(write_fifo.source.data),
NextValue(write_counter, write_counter + 1),
If(write_counter == (tWRDataSetup-1),
NextValue(write_counter, 0),
NextState("PULSE_WR_N")
)
)
write_fsm.act("PULSE_WR_N",
data_oe.eq(1),
data_w.eq(write_fifo.source.data),
pads.wr_n.eq(0),
NextValue(write_counter, write_counter + 1),
If(write_counter == (tWR-1),
NextState("WAIT_TXE_N")
)
)
write_fsm.act("WAIT_TXE_N",
If(txe_n,
write_fifo.source.ready.eq(1),
NextState("IDLE")
)
)
def ns(self, t, margin=True):
clk_period_ns = 1e9/self.clk_freq
if margin:
t += clk_period_ns/2
return math.ceil(t/clk_period_ns)
# FT245 FIFO Mode PHY (Automatic Asynchronous/Synchronous selection) -------------------------------
def FT245PHY(pads, *args, **kwargs):
# autodetect PHY
if hasattr(pads, "clkout"):
return FT245PHYSynchronous(pads, *args, **kwargs)
else:
return FT245PHYAsynchronous(pads, *args, **kwargs)
| [
"litex.soc.interconnect.stream.EndpointDescription"
] | [((488, 530), 'litex.soc.interconnect.stream.EndpointDescription', 'stream.EndpointDescription', (['payload_layout'], {}), '(payload_layout)\n', (514, 530), False, 'from litex.soc.interconnect import stream\n'), ((2273, 2331), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['read_fifo_almost_full', 'read_fifo_almost_full_usb'], {}), '(read_fifo_almost_full, read_fifo_almost_full_usb)\n', (2281, 2331), False, 'from migen.genlib.cdc import MultiReg\n'), ((11293, 11321), 'math.ceil', 'math.ceil', (['(t / clk_period_ns)'], {}), '(t / clk_period_ns)\n', (11302, 11321), False, 'import math\n'), ((7459, 7486), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pads.txe_n', 'txe_n'], {}), '(pads.txe_n, txe_n)\n', (7467, 7486), False, 'from migen.genlib.cdc import MultiReg\n'), ((7500, 7527), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['pads.rxf_n', 'rxf_n'], {}), '(pads.rxf_n, rxf_n)\n', (7508, 7527), False, 'from migen.genlib.cdc import MultiReg\n'), ((8852, 8902), 'migen.fhdl.specials.Tristate', 'Tristate', (['pads.data', 'data_w', 'data_oe', 'data_r_async'], {}), '(pads.data, data_w, data_oe, data_r_async)\n', (8860, 8902), False, 'from migen.fhdl.specials import Tristate\n'), ((8916, 8946), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['data_r_async', 'data_r'], {}), '(data_r_async, data_r)\n', (8924, 8946), False, 'from migen.genlib.cdc import MultiReg\n')] |
#
# This file is part of LiteX-Boards.
#
# Copyright (c) 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from litex.build.generic_platform import *
from litex.build.efinix.platform import EfinixPlatform
from litex.build.efinix import EfinixProgrammer
# IOs ----------------------------------------------------------------------------------------------
_io = [
# Clk
("clk25", 0, Pins("B2"), IOStandard("1.8_V_LVCMOS")),
("clk33", 0, Pins("P2"), IOStandard("1.8_V_LVCMOS")),
("clk74_25", 0, Pins("A11"), IOStandard("1.8_V_LVCMOS")),
# SD-Card
("spisdcard", 0,
Subsignal("clk", Pins("B12")),
Subsignal("mosi", Pins("C12"), Misc("WEAK_PULLUP")),
Subsignal("cs_n", Pins("A12"), Misc("WEAK_PULLUP")),
Subsignal("miso", Pins("B14"), Misc("WEAK_PULLUP")),
IOStandard("1.8_V_LVCMOS"),
),
("sdcard", 0,
Subsignal("data", Pins("B14 A14 D12 A12"), Misc("WEAK_PULLUP")),
Subsignal("cmd", Pins("C12"), Misc("WEAK_PULLUP")),
Subsignal("clk", Pins("B12")),
IOStandard("3.3_V_LVCMOS"),
),
# Serial
("serial", 0,
Subsignal("tx", Pins("R4")),
Subsignal("rx", Pins("R3")),
IOStandard("3.3_V_LVCMOS"), Misc("WEAK_PULLUP")
),
# Leds
("user_led", 0,
Subsignal("r", Pins("J15")),
Subsignal("g", Pins("H10")),
Subsignal("b", Pins("K14")),
IOStandard("1.8_V_LVCMOS"),
),
("user_led", 1,
Subsignal("r", Pins("H15")),
Subsignal("g", Pins("H11")),
Subsignal("b", Pins("J14")),
IOStandard("1.8_V_LVCMOS"),
),
# Buttons
("user_btn", 0, Pins("K13"), IOStandard("1.8_V_LVCMOS")),
("user_btn", 1, Pins("J13"), IOStandard("1.8_V_LVCMOS")),
("user_btn", 2, Pins("C5"), IOStandard("1.8_V_LVCMOS")),
("user_btn", 3, Pins("R13"), IOStandard("1.8_V_LVCMOS")),
# Switches
("user_sw", 0, Pins("F3"), IOStandard("1.8_V_LVCMOS")),
("user_sw", 1, Pins("E3"), IOStandard("1.8_V_LVCMOS")),
# SPIFlash
("spiflash", 0,
Subsignal("cs_n", Pins("P1")),
Subsignal("clk", Pins("N1")),
Subsignal("mosi", Pins("M1")),
Subsignal("miso", Pins("L1")),
IOStandard("1.8_V_LVCMOS")
),
# HyperRAM (X16)
("hyperram", 0,
Subsignal("dq", Pins(
"B6 C6 A5 A6 F7 F8 E7 D7",
"B9 A9 F9 E9 C10 D10 A10 B10"
), IOStandard("1.8_V_LVCMOS")),
Subsignal("rwds", Pins("B8 C8"), IOStandard("1.8_V_LVCMOS")),
Subsignal("cs_n", Pins("A8"), IOStandard("1.8_V_LVCMOS")),
Subsignal("rst_n", Pins("D5"), IOStandard("1.8_V_LVCMOS")),
Subsignal("clk", Pins("B7"), IOStandard("1.8_V_LVCMOS")),
Misc("SLEWRATE=FAST")
),
# MIPI
("mipi_tx", 0,
Subsignal("clk", Pins("D13"), IOStandard("1.2_V_LVCMOS")),
Subsignal("data0", Pins("C15"), IOStandard("1.2_V_LVCMOS")),
Subsignal("data1", Pins("D14"), IOStandard("1.2_V_LVCMOS")),
Subsignal("data2", Pins("E14"), IOStandard("1.2_V_LVCMOS")),
Subsignal("data3", Pins("E12"), IOStandard("1.2_V_LVCMOS")),
Misc("SLEWRATE=FAST")
),
]
iobank_info = [
("1A", "1.8 V LVCMOS"),
("1B", "1.8 V LVCMOS"),
("2A", "1.8 V LVCMOS"),
("2B", "1.8 V LVCMOS"),
("3A", "1.2 V LVCMOS"),
("3B", "1.2 V LVCMOS"),
("4A", "1.2 V LVCMOS"),
("4B", "1.2 V LVCMOS"),
("BL", "1.8 V LVCMOS"),
("BR", "1.8 V LVCMOS"),
("TL", "1.8 V LVCMOS"),
("TR", "1.8 V LVCMOS"),
]
# Connectors ---------------------------------------------------------------------------------------
_connectors = [
["P1", " - H14 - G14 - - F12 G13 E12 F13 - - E15 H13 E14 H12 - - C13 G15 D13 F15",
" - - D15 G11 D14 F11 - - C14 N14 C15 P14 - - K4 A4 J3 B5"],
]
# Platform -----------------------------------------------------------------------------------------
class Platform(EfinixPlatform):
default_clk_name = "clk25"
default_clk_period = 1e9/50e6
def __init__(self, toolchain="efinity"):
EfinixPlatform.__init__(self, "Ti60F225C3", _io, _connectors, iobank_info=iobank_info, toolchain=toolchain)
def create_programmer(self):
return EfinixProgrammer()
def do_finalize(self, fragment):
EfinixPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk25", loose=True), 1e9/50e6)
| [
"litex.build.efinix.platform.EfinixPlatform.__init__",
"litex.build.efinix.platform.EfinixPlatform.do_finalize",
"litex.build.efinix.EfinixProgrammer"
] | [((4185, 4297), 'litex.build.efinix.platform.EfinixPlatform.__init__', 'EfinixPlatform.__init__', (['self', '"""Ti60F225C3"""', '_io', '_connectors'], {'iobank_info': 'iobank_info', 'toolchain': 'toolchain'}), "(self, 'Ti60F225C3', _io, _connectors, iobank_info=\n iobank_info, toolchain=toolchain)\n", (4208, 4297), False, 'from litex.build.efinix.platform import EfinixPlatform\n'), ((4342, 4360), 'litex.build.efinix.EfinixProgrammer', 'EfinixProgrammer', ([], {}), '()\n', (4358, 4360), False, 'from litex.build.efinix import EfinixProgrammer\n'), ((4407, 4449), 'litex.build.efinix.platform.EfinixPlatform.do_finalize', 'EfinixPlatform.do_finalize', (['self', 'fragment'], {}), '(self, fragment)\n', (4433, 4449), False, 'from litex.build.efinix.platform import EfinixPlatform\n')] |
# This file is Copyright (c) <NAME> <<EMAIL>>
# License: BSD
from migen import *
from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus
from migen.genlib.cdc import MultiReg
def io_pins():
return Record([("i", 1),("o", 1),("oe", 1)])
class IOPin(Module):
def __init__(self, pad):
self.pad = pad
self.ctrl = []
self.alt = Signal(8, reset=0)
self._ts = ts = TSTriple()
self.specials += ts.get_tristate(pad)
def add_alt(self, alt):
self.ctrl += [alt]
def finalize(self):
_in = Signal()
self.specials += MultiReg(self._ts.i, _in)
# Connect up IO signals depending on alt-setting.
for i,c in zip(range(len(self.ctrl)), self.ctrl):
self.comb += [
If(self.alt == i,
self._ts.o.eq(c.o),
self._ts.oe.eq(c.oe),
c.eq(_in),
)
]
class IOPort(Module, AutoCSR):
def __init__(self, pads):
self.alt_fields = ["csr_control"]
pins = [0,1,5,6,9,10,11,12,13,18,19,20,21]
nbits = len(pins)
fields= []
for n in pins:
fields += [
CSRField(f"io{n}", 1, n ,description=f"Control for I/O pin {n}"),
]
self._oe = CSRStorage(nbits, description="""GPIO Tristate(s) Control.
Write ``1`` enable output driver""", fields=fields)
self._in = CSRStatus(nbits, description="""GPIO Input(s) Status.
Input value of IO pad as read by the FPGA""", fields=fields)
self._out = CSRStorage(nbits, description="""GPIO Ouptut(s) Control.
Value loaded into the output driver""", fields=fields)
# # #
self._io = []
for n,p in zip(pins,pads):
m = IOPin(p)
# Create a connection to the CSR
alt_csr = io_pins()
self.comb += [alt_csr.o.eq(self._out.storage[n]), alt_csr.oe.eq(self._oe.storage[n]), self._in.status.eq(alt_csr.i)]
m.add_alt(alt_csr)
self.submodules += m
self._io += [(n,m)]
def finalize(self):
# create Alt fields
values = []
for i,n in zip(range(len(self.alt_fields)), self.alt_fields):
values += [(i,n)]
f = CSRField("ctrl", size=8, description="Select alternative function on IO pin", values=values)
for n,m in self._io:
csr = CSRStorage(8, name=f"alt{n}", description="""GPIO Alt Control.
IO pin alternative functions""", fields=[f])
setattr(self, f"_alt{n}", csr)
self.comb += m.alt.eq(csr.storage)
def add_alt(self):
... | [
"litex.soc.interconnect.csr.CSRField",
"litex.soc.interconnect.csr.CSRStorage",
"litex.soc.interconnect.csr.CSRStatus"
] | [((613, 638), 'migen.genlib.cdc.MultiReg', 'MultiReg', (['self._ts.i', '_in'], {}), '(self._ts.i, _in)\n', (621, 638), False, 'from migen.genlib.cdc import MultiReg\n'), ((1362, 1489), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['nbits'], {'description': '"""GPIO Tristate(s) Control.\n Write ``1`` enable output driver"""', 'fields': 'fields'}), '(nbits, description=\n """GPIO Tristate(s) Control.\n Write ``1`` enable output driver""",\n fields=fields)\n', (1372, 1489), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1501, 1633), 'litex.soc.interconnect.csr.CSRStatus', 'CSRStatus', (['nbits'], {'description': '"""GPIO Input(s) Status.\n Input value of IO pad as read by the FPGA"""', 'fields': 'fields'}), '(nbits, description=\n """GPIO Input(s) Status.\n Input value of IO pad as read by the FPGA"""\n , fields=fields)\n', (1510, 1633), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1645, 1773), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['nbits'], {'description': '"""GPIO Ouptut(s) Control.\n Value loaded into the output driver"""', 'fields': 'fields'}), '(nbits, description=\n """GPIO Ouptut(s) Control.\n Value loaded into the output driver""",\n fields=fields)\n', (1655, 1773), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((2362, 2459), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['"""ctrl"""'], {'size': '(8)', 'description': '"""Select alternative function on IO pin"""', 'values': 'values'}), "('ctrl', size=8, description=\n 'Select alternative function on IO pin', values=values)\n", (2370, 2459), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((2503, 2631), 'litex.soc.interconnect.csr.CSRStorage', 'CSRStorage', (['(8)'], {'name': 'f"""alt{n}"""', 'description': '"""GPIO Alt Control.\n IO pin alternative functions"""', 'fields': '[f]'}), '(8, name=f\'alt{n}\', description=\n """GPIO Alt Control.\n IO pin alternative functions""",\n fields=[f])\n', (2513, 2631), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n'), ((1261, 1325), 'litex.soc.interconnect.csr.CSRField', 'CSRField', (['f"""io{n}"""', '(1)', 'n'], {'description': 'f"""Control for I/O pin {n}"""'}), "(f'io{n}', 1, n, description=f'Control for I/O pin {n}')\n", (1269, 1325), False, 'from litex.soc.interconnect.csr import AutoCSR, CSRStorage, CSRField, CSRStatus\n')] |
#
# This file is part of LiteX.
#
# Copyright (c) 2019-2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: BSD-2-Clause
from enum import IntEnum
from migen import *
from migen.genlib.cdc import PulseSynchronizer
from litex.soc.interconnect.csr import *
from litex.soc.interconnect import stream
# Constants ----------------------------------------------------------------------------------------
# ICAP Words
ICAP_DUMMY = 0xffffffff
ICAP_SYNC = 0xaa995566
ICAP_NOOP = 0x20000000
ICAP_WRITE = 0x30000000
ICAP_READ = 0x28000000
# Configuration Registers (from UG470).
class ICAPRegisters(IntEnum):
CRC = 0b00000 # CRC Register.
FAR = 0b00001 # Frame Address Register.
FDRI = 0b00010 # Frame Data Register, Input Register.
FDRO = 0b00011 # Frame Data Register, Output Register.
CMD = 0b00100 # Command Register.
CTL0 = 0b00101 # Control Register 0.
MASK = 0b00110 # Masking Register for CTL0 and CTL1.
STAT = 0b00111 # Status Register.
LOUT = 0b01000 # Legacy Output Register for daisy chain.
COR0 = 0b01001 # Configuration Option Register 0.
MFWR = 0b01010 # Multiple Frame Write Register.
CBC = 0b01011 # Initial CBC Value Register.
IDCODE = 0b01100 # Device ID Register.
AXSS = 0b01101 # User Access Register.
COR1 = 0b01110 # Configuration Option Register 1.
WBSTAR = 0b10000 # Warm Boot Start Address Register.
TIMER = 0b10001 # Watchdog Timer Register.
BOOTSTS = 0b10110 # Boot History Status Register.
CTL1 = 0b11000 # Control Register 1.
BSPI = 0b11111 # BPI/SPI Configuration Options Register.
# Commands (from UG470).
class ICAPCMDs(IntEnum):
MFW = 0b00010 # Multiple Frame Write.
LFRM = 0b00011 # Last Frame.
RCFG = 0b00100 # Reads Configuration Data.
START = 0b00101 # Begins the Startup Sequence.
RCAP = 0b00110 # Resets the CAPTURE signal.
RCRC = 0b00111 # Resets CRC.
AGHIGH = 0b01000 # Asserts the GHIGH_B signal.
SWITCH = 0b01001 # Switches the CCLK frequency.
GRESTORE = 0b01010 # Pulses the GRESTORE signal.
SHUTDOWN = 0b01011 # Begin Shutdown Sequence.
GCAPTURE = 0b01100 # Pulses GCAPTURE.
DESYNC = 0b01101 # Resets the DALIGN signal.
IPROG = 0b01111 # Internal PROG for triggering a warm boot.
CRCC = 0b10000 # Recalculates the first readback CRC value after reconfiguration
LTIMER = 0b10001 # Reload Watchdog timer.
BSPI_READ = 0b10010 # BPI/SPI re-initiate bitstream read.
FALL_EDGE = 0b10011 # Switch to negative-edge clocking.
# Xilinx 7-series ----------------------------------------------------------------------------------
class ICAP(Module, AutoCSR):
"""ICAP
Allow writing/reading ICAPE2's registers of Xilinx 7-Series FPGAs.
A warm boot can for example be triggered by writing IPROG CMD (0xf) to CMD register (0b100).
"""
def __init__(self, with_csr=True, simulation=False):
self.write = Signal()
self.read = Signal()
self.done = Signal()
self.addr = Signal(5)
self.write_data = Signal(32)
self.read_data = Signal(32)
# # #
# Create slow ICAP Clk (sys_clk/16).
self.clock_domains.cd_icap = ClockDomain()
icap_clk_counter = Signal(4)
self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
self.sync += self.cd_icap.clk.eq(icap_clk_counter[3])
# Generate ICAP bitstream sequence.
self._csib = _csib = Signal(reset=1)
self._rdwrb = _rdwrb = Signal()
self._i = _i = Signal(32)
self._o = _o = Signal(32)
count = Signal(4)
fsm = FSM(reset_state="WAIT")
fsm = ClockDomainsRenamer("icap")(fsm)
fsm = ResetInserter()(fsm)
self.submodules += fsm
self.comb += fsm.reset.eq(~(self.write | self.read))
# Wait User Command.
fsm.act("WAIT",
# Set ICAP in IDLE state.
_csib.eq(1),
_rdwrb.eq(0),
_i.eq(ICAP_DUMMY),
# Wait User Command.
If(self.write | self.read,
NextValue(count, 0),
NextState("SYNC")
)
)
# Send ICAP Synchronization sequence.
fsm.act("SYNC",
_csib.eq(0),
_rdwrb.eq(0),
Case(count, {
0 : _i.eq(ICAP_NOOP), # No Op.
1 : _i.eq(ICAP_SYNC), # Sync Word.
2 : _i.eq(ICAP_NOOP), # No Op.
3 : _i.eq(ICAP_NOOP), # No Op.
}),
NextValue(count, count + 1),
If(count == (4-1),
NextValue(count, 0),
If(self.write,
NextState("WRITE")
).Else(
NextState("READ")
)
)
)
# Send ICAP Write sequence.
fsm.act("WRITE",
_csib.eq(0),
_rdwrb.eq(0),
Case(count, {
0 : _i.eq(ICAP_WRITE | (self.addr << 13) | 1), # Set Register.
1 : _i.eq(self.write_data), # Set Register Data.
2 : _i.eq(ICAP_NOOP), # No Op.
3 : _i.eq(ICAP_NOOP), # No Op.
}),
NextValue(count, count + 1),
If(count == (4-1),
NextValue(count, 0),
NextState("DESYNC")
)
)
# Send ICAP Read sequence.
fsm.act("READ",
_csib.eq(0),
_rdwrb.eq(0),
Case(count, {
0 : _i.eq(ICAP_READ | (self.addr << 13) | 1), # Set Register.
1 : _i.eq(ICAP_NOOP), # No Op.
2 : _i.eq(ICAP_NOOP), # No Op.
3 : [_csib.eq(1), _rdwrb.eq(1), _i.eq(ICAP_NOOP)], # Idle + No Op.
4 : [_csib.eq(0), _rdwrb.eq(1), _i.eq(ICAP_NOOP)], # No Op.
5 : [_csib.eq(0), _rdwrb.eq(1), _i.eq(ICAP_NOOP)], # No Op.
6 : [_csib.eq(0), _rdwrb.eq(1), _i.eq(ICAP_NOOP)], # No Op.
7 : [_csib.eq(0), _rdwrb.eq(1), _i.eq(ICAP_NOOP)], # No Op.
8 : [_csib.eq(0), _rdwrb.eq(1), _i.eq(ICAP_NOOP)], # No Op.
}),
NextValue(count, count + 1),
If(count == (8-1),
NextValue(self.read_data, _o),
NextValue(count, 0),
NextState("DESYNC")
)
)
# Send ICAP Desynchronization sequence.
fsm.act("DESYNC",
_csib.eq(0),
_rdwrb.eq(0),
Case(count, {
0 : _i.eq(ICAP_WRITE | (ICAPRegisters.CMD << 13) | 1), # Write to CMD Register.
1 : _i.eq(ICAPCMDs.DESYNC), # DESYNC CMD.
2 : _i.eq(ICAP_NOOP), # No Op.
3 : _i.eq(ICAP_NOOP), # No Op.
}),
NextValue(count, count + 1),
If(count == (4-1),
NextValue(count, 0),
NextState("DONE")
)
)
# Done
fsm.act("DONE",
# Set ICAP in IDLE state.
_csib.eq(1),
_rdwrb.eq(0),
_i.eq(ICAP_DUMMY),
self.done.eq(1)
)
# ICAP Instance.
if not simulation:
_i_icape2 = Signal(32)
_o_icape2 = Signal(32)
self.comb += _i_icape2.eq(Cat(*[_i[8*i:8*(i+1)][::-1] for i in range(4)])),
self.comb += _o.eq(Cat(*[_o_icape2[8*i:8*(i+1)][::-1] for i in range(4)])),
self.specials += Instance("ICAPE2",
p_ICAP_WIDTH = "X32",
i_CLK = ClockSignal("icap"),
i_CSIB = _csib,
i_RDWRB = _rdwrb,
i_I = _i_icape2,
o_O = _o_icape2,
)
# CSR.
if with_csr:
self.add_csr()
def add_csr(self):
self._addr = CSRStorage(5, reset_less=True, description="ICAP Address.")
self._data = CSRStorage(32, reset_less=True, description="ICAP Write/Read Data.", write_from_dev=True)
self._write = CSRStorage(description="ICAP Control.\n\n Write ``1`` send a write to the ICAP.")
self._done = CSRStatus(reset=1, description="ICAP Status.\n\n Write command done when read as ``1``.")
self._read = CSRStorage(description="ICAP Control.\n\n Read ``1`` send a read from the ICAP.")
self.comb += [
self.addr.eq(self._addr.storage),
self.write_data.eq(self._data.storage),
self.write.eq(self._write.storage),
self._done.status.eq(self.done),
self.read.eq(self._read.storage),
If(self.done,
self._data.we.eq(1),
self._data.dat_w.eq(self.read_data)
)
]
def add_reload(self):
self.reload = Signal() # Set to 1 to reload FPGA from logic.
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE",
If(self.reload,
NextState("RELOAD")
)
)
fsm.act("RELOAD",
self.addr.eq(ICAPRegisters.CMD),
self.write.eq(1),
self.write_data.eq(ICAPCMDs.IPROG),
)
def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
platform.add_period_constraint(self.cd_icap.clk, 16*1e9/sys_clk_freq)
platform.add_false_path_constraints(self.cd_icap.clk, sys_clk)
class ICAPBitstream(Module, AutoCSR):
"""ICAP Bitstream
Allow sending bitstreams to ICAPE2 of Xilinx 7-Series FPGAs.
The CPU can push stream of data to the ICAPE2 by reading `sink_ready` CSR to verify that there is
space available in the FIFO; then write the data to `sink_data` register. Each word written to the
FIFO is transmitted to the ICAPE2 using the slow icap_clk (with expected bit/byte reordering).
The CPU accesses/FIFO must be fast/large enough to ensure there is no gap in the stream sent to
the ICAPE2.
"""
def __init__(self, fifo_depth=8, icap_clk_div=4, simulation=False):
self.sink_data = CSRStorage(32, reset_less=True)
self.sink_ready = CSRStatus()
# # #
# Create slow icap_clk (sys_clk/4) ---------------------------------------------------------
icap_clk_counter = Signal(log2_int(icap_clk_div))
self.clock_domains.cd_icap = ClockDomain()
self.sync += icap_clk_counter.eq(icap_clk_counter + 1)
self.sync += self.cd_icap.clk.eq(icap_clk_counter[-1])
# FIFO (sys_clk to icap_clk) ---------------------------------------------------------------
fifo = stream.AsyncFIFO([("data", 32)], fifo_depth)
fifo = ClockDomainsRenamer({"write": "sys", "read": "icap"})(fifo)
self.submodules += fifo
self.comb += [
fifo.sink.valid.eq(self.sink_data.re),
fifo.sink.data.eq(self.sink_data.storage),
self.sink_ready.status.eq(fifo.sink.ready),
]
# Generate ICAP commands -------------------------------------------------------------------
self._csib = _csib = Signal(reset=1)
self._i = _i = Signal(32, reset=0xffffffff)
self.comb += [
fifo.source.ready.eq(1),
If(fifo.source.valid,
_csib.eq(0),
_i.eq(fifo.source.data)
)
]
# ICAP instance ----------------------------------------------------------------------------
if not simulation:
self.specials += Instance("ICAPE2",
p_ICAP_WIDTH = "X32",
i_CLK = ClockSignal("icap"),
i_CSIB = _csib,
i_RDWRB = 0,
i_I = Cat(*[_i[8*i:8*(i+1)][::-1] for i in range(4)])
)
def add_timing_constraints(self, platform, sys_clk_freq, sys_clk):
platform.add_period_constraint(self.cd_icap.clk, 16*1e9/sys_clk_freq)
platform.add_false_path_constraints(self.cd_icap.clk, sys_clk)
| [
"litex.soc.interconnect.stream.AsyncFIFO"
] | [((10939, 10983), 'litex.soc.interconnect.stream.AsyncFIFO', 'stream.AsyncFIFO', (["[('data', 32)]", 'fifo_depth'], {}), "([('data', 32)], fifo_depth)\n", (10955, 10983), False, 'from litex.soc.interconnect import stream\n')] |
# SPDX-FileCopyrightText: 2021 <NAME> <<EMAIL>>
# SPDX-License-Identifier: MIT
from migen import *
from litex.soc.interconnect import csr, stream
class MemStreamReader(Module):
def __init__(self, rport):
self.sink = sink = stream.Endpoint([
('address', rport.adr.nbits),
])
self.source = source = stream.Endpoint([
('data', rport.dat_r.nbits),
])
hold = Signal()
hold_data = Signal(rport.dat_r.nbits)
blocking = source.valid & ~source.ready
self.comb += [
sink.ready.eq(
sink.valid & ~blocking
),
rport.adr.eq(sink.address),
If(hold,
source.data.eq(hold_data),
).Else(
source.data.eq(rport.dat_r),
),
]
self.sync += [
If(sink.valid | blocking,
source.valid.eq(1),
).Else(
source.valid.eq(0),
),
If(blocking,
hold.eq(1),
hold_data.eq(source.data),
).Else(
hold.eq(0),
),
]
class MemStreamWriter(Module):
def __init__(self, wrport):
self.sink = sink = stream.Endpoint([
('address', wrport.adr.nbits),
('data', wrport.dat_w.nbits),
])
self.comb += [
sink.ready.eq(sink.valid),
wrport.we.eq(sink.valid),
wrport.adr.eq(sink.address),
wrport.dat_w.eq(sink.data),
]
| [
"litex.soc.interconnect.stream.Endpoint"
] | [((238, 285), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', rport.adr.nbits)]"], {}), "([('address', rport.adr.nbits)])\n", (253, 285), False, 'from litex.soc.interconnect import csr, stream\n'), ((340, 386), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('data', rport.dat_r.nbits)]"], {}), "([('data', rport.dat_r.nbits)])\n", (355, 386), False, 'from litex.soc.interconnect import csr, stream\n'), ((1258, 1336), 'litex.soc.interconnect.stream.Endpoint', 'stream.Endpoint', (["[('address', wrport.adr.nbits), ('data', wrport.dat_w.nbits)]"], {}), "([('address', wrport.adr.nbits), ('data', wrport.dat_w.nbits)])\n", (1273, 1336), False, 'from litex.soc.interconnect import csr, stream\n')] |
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