data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Introduce SMMU_SEC_SID_S to represent SEC_SID == 1, meaning Secure. And
then provide smmu_get_address_space, a SMMU instance-based address space
selector. The helper now returns the per-device memory/secure-memory
AddressSpace and reports missing spaces.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
---
hw/arm... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:26 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | When decoding a Stream Table Entry (STE) from the Secure stream table
that enables stage-2 translation, verify that the SMMU implementation
advertises Secure stage-2 support via S_IDR1.SEL2. If stage-2 is
requested but S_IDR1.SEL2 is 0, mark the STE as ILLEGAL.
This implements the requirement from the Arm SMMUv3 archi... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:28 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | The current definition of the SMMU_CR0_RESERVED mask is incorrect.
It mistakenly treats bit 10 (DPT_WALK_EN) as a reserved bit while
treating bit 9 (RES0) as an implemented bit.
According to the SMMU architecture specification, the layout for CR0 is:
| 31:11| RES0 |
| 10 | DPT_WALK_EN |
| 9 | RES0 ... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:20 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | The FIELD macro for the SMMU enable bit in the CR0 register was
incorrectly named SMMU_ENABLE.
The ARM SMMUv3 Architecture Specification (both older IHI 0070.E.a and
newer IHI 0070.G.b) consistently refers to the SMMU enable bit as SMMUEN.
This change makes our implementation consistent with the manual.
Signed-off-b... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:21 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Cache the SEC_SID inside SMMUTransCfg to keep configuration lookups
tied to the correct register bank.
Plumb the SEC_SID through tracepoints and queue helpers so diagnostics
and event logs always show which security interface emitted the record.
To support this, the SEC_SID is placed in SMMUEventInfo so the bank is
id... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:25 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Extend the register and queue helper routines to accept an explicit
SEC_SID argument instead of hard-coding the non-secure bank.
All existing callers are updated to pass SMMU_SEC_SID_NS, so the
behavior remains identical. This prepares the code for handling
additional security state banks in the future. So Non-secure ... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:24 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi all,
This is v4 of the Secure SMMUv3 series.
Many thanks to everyone who reviewed the earlier versions. This revision focuses
on tightening architectural compliance, improving integration points, and making
the SEC_SID plumbing complete across the fast paths.
This revision contains 31 commits in total. Only one p... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:19 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Rework the SMMUv3 state management by introducing a banked register
structure. This is a purely mechanical refactoring with no functional
changes.
To support multiple security states, a new enum, SMMUSecSID, is
introduced to identify each state, sticking to the spec terminology.
A new structure, SMMUv3RegBank, is the... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:23 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | The Arm SMMUv3 architecture defines a set of registers for managing
secure transactions and context.
This patch introduces the definitions for these secure registers within
the SMMUv3 device model internal header.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Lin... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:02:22 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Adapt the configuration cache to support multiple security states by
introducing a composite key, SMMUConfigKey. This key combines the
SMMUDevice with SEC_SID, preventing aliasing between Secure and
Non-secure configurations for the same device, also the future Realm and
Root configurations.
The cache lookup, insertio... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:14:37 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Add helper macros for NS and NSTable bits and group PTE attribute
accessors for clarity. No functional change beyond the new helpers.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
---
hw/arm/smmu-internal.h | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/hw/arm/smmu-intern... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:15:44 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | With NSCFG definitions in place, record the per-table NSCFG bits
in SMMUTransTableInfo during CD decode for later use.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
---
hw/arm/smmuv3.c | 1 +
include/hw/arm/smmu-common.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/arm/smmuv3.c b/hw/ar... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:16:32 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | This is a non-functional preparation step that adds storage for
resolved security state in SMMUTLBEntry.
Together with the earlier commits that added NSCFG handling and
PTE NS/NSTable helpers, the plumbing is complete and we can now
refactor the PTW flow to handle Secure state.
Signed-off-by: Tao Tang <tangtao1634@ph... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:16:40 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Make smmuv3_cmdq_consume() security-state aware by passing sec_sid
from smmu_writel() call sites (CR0/GERRORN/CMDQ_PROD paths), instead
of hardcoding non-secure state. The related AddressSpace and MemTxAttrs
are also obtained based on sec_sid.
Also move CMD_SSEC legality checking to a single early check before
command... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:17:14 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | The event queue producer path wrote entries through address_space_memory
with MEMTXATTRS_UNSPECIFIED, so produced entries did not use the
sec_sid-selected DMA context.
Pass AddressSpace and MemTxAttrs to queue_write() from sec_sid, and
assert that the selected AddressSpace exists before producing entries.
Signed-off-... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:17:23 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Enhance the page table walker to correctly handle secure and non-secure
memory accesses. This change introduces logic to select the appropriate
address space and enforce architectural security policies during walks.
The page table walker now correctly processes Secure Stage 1
translations. Key changes include:
- The ... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:16:49 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Add a STAGE1_SUPPORTED check in the CMD_CFGI_CD and CMD_CFGI_CD_ALL path
and return CERROR_ILL when stage-1 translation is not implemented,
matching the architecture requirement (IHI 0070G.b, page 176).
Fixes: 32cfd7f39e08 ("hw/arm/smmuv3: Cache/invalidate config data")
Signed-off-by: Tao Tang <tangtao1634@phytium.com... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:17:33 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | To prevent aliasing between secure and non-secure translations for the
same address space, the IOTLB lookup key must incorporate the security
state of the transaction.
This commit:
- expands SMMUIOTLBKey with SEC_SID field for cache key differentiation
- extends SMMUIOTLBPageInvInfo with SEC_SID for invalidation filte... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:16:57 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Refactor CMDQ invalidation paths to carry security state and apply
cache invalidation per sec_sid instead of globally. Extend common
IOTLB/config invalidation helpers with sec_sid filtering, while keeping
SMMU_SEC_SID_NUM as the full-invalidate mode.
In smmuv3, propagate sec_sid/ssec through CFGI and TLBI handling, an... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:17:41 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Extend IOMMU notifier functions to be SEC_SID-aware, ensuring that
invalidation notifications are dispatched to the correct security-aware
address space.
This ensures IOMMU notifier events (e.g., to VFIO) are correctly routed
to the appropriate security world's address space, maintaining isolation
between secure and n... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:17:06 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Add helper functions smmu_msi_supported() and smmu_gerror_irq_cfg_writable()
to check accessibility of GERROR_IRQ_CFG registers. Reading returns RES0
when MSI is not supported. Writing is ignored when GERROR_IRQEN is set.
Additionally, mask reserved bits on writes using SMMU_GERROR_IRQ_CFG0_RESERVED.
Fixes: fae4be38b... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:17:49 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Add access control for SMMU_STRTAB_BASE and SMMU_CR2 registers to
ensure they can only be modified when the SMMU is disabled.
This implements:
- smmuv3_smmu_disabled_stable(): Check whether the SMMU is in a stable
disabled state (CR0.SMMUEN == 0 and CR0ACK.SMMUEN == 0);
- smmu_strtab_base_writable(): returns true o... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:18:16 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Add access control for command queue and event queue related registers
to ensure they can only be modified under proper conditions.
For command queue (CMDQ):
- smmu_cmdq_disabled_stable(): checks CMDQ bit in CR0/CR0ACK
- smmu_cmdq_base_writable(): checks IDR1.QUEUES_PRESET==0 and CMDQ disabled
For event queue (EVTQ):... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:18:23 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Modify the main MMIO handlers (smmu_write_mmio, smmu_read_mmio)
to determine the security state of the target register based on its
memory-mapped offset.
By checking if the offset is within the secure register space (>=
SMMU_SECURE_REG_START), the handlers can deduce the register's
SEC_SID (reg_sec_sid). This SID is t... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:18:29 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Arm SMMUv3 uses a SEC_SID (StreamID Security state) to determine the
security state of the programming interface that controls a transaction.
The architecture explicitly states that the association between a device
and its SEC_SID is a system-defined property, not something derived from
the physical address space.
We ... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:18:50 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | This patch hardens the security validation within the main MMIO
dispatcher functions (smmu_read_mmio and smmu_write_mmio).
First, accesses to the secure register space are now correctly gated by
whether the SECURE_IMPL feature is enabled in the model. This prevents
guest software from accessing the secure programming ... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:18:42 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Implement read/write handlers for the SMMU_S_INIT secure-only register.
Writing INV_ALL provides a mechanism for software to perform a global
invalidation of ALL caches within the SMMU, including IOTLBs and
configuration caches across all security states.
The MMIO dispatcher decodes the target register bank from the ... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:18:36 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Add a secure-impl device property and advertise it through
S_IDR1.SECURE_IMPL.
Usage:
-global arm-smmuv3,secure-impl=true
Add the smmuv3/bank_s migration subsection for the secure register bank.
Serialize secure bank state including GBPA, IRQ config, stream table and
queue state.
Signed-off-by: Tao Tang <tangtao... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:19:26 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Initialize the secure register bank (SMMU_SEC_SID_S) with sane default
values during the SMMU's reset sequence.
This change ensures that key fields, such as the secure ID registers,
GBPA reset value, and queue entry sizes, are set to a known-good state.
The SECURE_IMPL attribute of the S_IDR1 register will be introduc... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:19:18 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Parse each PCI device's sec-sid property during SMMU device initialization
and cache it in SMMUDevice::sec_sid. Support "non-secure" and "secure",
default to non-secure when unspecified, and reject invalid values with an
explicit error. Use sdev->sec_sid in smmuv3_translate() to select the
register bank instead of hard... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:19:07 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Temporarily:
- enable S_IDR1.SEL2,
- change AIDR to 0x2 to indicate SMMUv3.2,
- use smaller SID size and Cmd/Evt queue size.
Signed-off-by: Tao Tang <tangtao1634@phytium.com.cn>
---
hw/arm/smmuv3.c | 3 ++-
include/hw/arm/smmuv3-common.h | 6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
dif... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 21 Feb 2026 18:19:33 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:02 AM, Tao Tang wrote:
Thinking about this one, I don't see any case where we would like to
silently return here.
Instead, could we check that directly in smmuv3_realize?
If arm-smmuv3.secure-impl is enabled, then we should have
s->secure_memory set accordingly.
As well, we can decide to enable secure-... | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 12:36:04 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:02 AM, Tao Tang wrote:
As an alternative, you can simply pass SMMUState where it's missing
(like smmu_ptw_64_s2) and call smmu_get_address_space from there.
It will avoid having to keep this in cfg.
Maybe there is another reason I missed?
Regards,
Pierrick | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 12:52:07 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:02 AM, Tao Tang wrote:
Would that be possible to add all switch values, and use
g_assert_not_reached() for SMMU_SEC_SID_NUM.
This way, when adding SMMU_SEC_SID_R, we'll be directly blocked at
compilation because case is missing.
Regards,
Pierrick | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 12:55:45 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:16 AM, Tao Tang wrote:
Does it requires so much refactor it's better to keep it as a field in
cfg instead?
Having SMMUState passed there would allow to reuse smmu_get_address_space.
Overall looks good, and my remarks above are more suggestions than
blocking comments. | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 13:12:00 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:19 AM, Tao Tang wrote:
I have been able to boot hafnium with:
- instructions at
https://hnusdr.github.io/2025/08/09/Test-Secure-SMMU-with-Hafnium-ENG/
- the current patch
- qemu-system-aarch64 -global arm-smmuv3.secure-impl=on ...
In case someone else wants to reproduce this easily:
```
git clone https... | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 13:31:32 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:17 AM, Tao Tang wrote:
Sounds great!
This will be automatically be handled if we check in smmu_base_realize
that secure smmu support should be available, as mentioned on one of the
previous patch.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 13:35:40 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:17 AM, Tao Tang wrote:
Looks ok overall.
Using SMMU_SEC_SID_NUM as a special value to trigger all
flush/invalidate works, but it's a bit surprising to read to be honest.
It could be more explicit to introduce the two next functions:
smmu_iotlb_inv_by_sec_sid(SMMUState *s, SMMUSecSID sec_sid)
smmuv3_flu... | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 13:47:35 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:18 AM, Tao Tang wrote:
It seems like we use the same pattern a lot of time for various SMMU
registers, and makes me wonder if we could not introduce proper register
definitions with callbacks similar to Arm *_reginfo.
That said, it's definitely out of the scope for this series:
Reviewed-by: Pierrick Bo... | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 13:59:07 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:18 AM, Tao Tang wrote:
In practice, it's not yet clear how will get this TDISP T-bit, since
it's part of encrypted payload. So far, we are detecting config fetch
and dynamically switching a given device to a new sec_sid accordingly.
Thus, we *might* end up reusing this field eventually.
All that said,... | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 14:05:26 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/25/26 1:31 PM, Pierrick Bouvier wrote:
If we could have a device access directly from optee, it could be used
to exercise secure translation as well.
However, I'm not really sure it's how optee is supposed to be used, and
it has very limited hardware support and abstractions. | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 14:07:51 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On 2/21/26 2:19 AM, Tao Tang wrote:
As mentioned before, should we enable it automatically in case
secure-memory address space is available at realize time?
Otherwise, congrats for the great series!
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Wed, 25 Feb 2026 14:20:42 -0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:02:20PM +0800, Tao Tang wrote:
I think fixes as this, should be separate, that would make the series
smaller.
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:31:05 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:02:21PM +0800, Tao Tang wrote:
Same comment about fixes.
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:31:47 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:02:22PM +0800, Tao Tang wrote:
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:33:49 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:02:23PM +0800, Tao Tang wrote:
There are a few warning from scripts/checkpatch.pl, plus some other
nits I mentioned, otherwise:
Reviewed-by: Mostafa Saleh <smostafa@google.com>
Sometimes you have:
SMMUv3RegBank *bank = smmuv3_bank(s, SMMU_SEC_SID_NS);
Others
SMMUv3RegBank *bk = smmuv3_bank... | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:38:03 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:02:25PM +0800, Tao Tang wrote:
What does this defend against?
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:39:18 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:02:28PM +0800, Tao Tang wrote:
The IDR is not currently set, we can just safely return bad_ste for
“SMMU_SEC_SID_S”, no need to complicate things until SEL2 is supported.
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:39:55 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:16:32PM +0800, Tao Tang wrote:
I feel this patch would be better squashed with how it’s used,
but no strong opinion.
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:41:04 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:16:40PM +0800, Tao Tang wrote:
I am not sure about this, when I added stage-2 I re-used the same
TLB instance as it might be used for nesting, and we can have
end-to-end cached entires.
For secure state, I think it’s cleaner to instantiate a new TLB, as
both states can never mix, and in this... | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:45:46 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:17:06PM +0800, Tao Tang wrote:
I don’t think that VFIO cares about secure regime, my guess is to
keep the functions as this and don’t call them for secure invalidations.
Thanks,
Mostafa | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:47:55 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:17:33PM +0800, Tao Tang wrote:
This is a separate fix, it can be sent standalone to make this series
smaller, similarly the first patch.
Also the "Fixes" comment is not accurate, that was probably broken from
the stage-2 implementation which was added later.
Reviewed-by: Mostafa Saleh <smos... | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:49:10 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | On Sat, Feb 21, 2026 at 06:18:29PM +0800, Tao Tang wrote:
This breaks all registers above 4k?
For example, TCU registers/PMU reside on some of this area and if SW
writes to those this might be aliased to something as CR0, which might
disable the SMMU and bypass some security checks. (in case it’s managed
by the hyperv... | {
"author": "Mostafa Saleh <smostafa@google.com>",
"date": "Fri, 27 Feb 2026 14:59:21 +0000",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi Pierrick,
On 2026/2/26 04:52, Pierrick Bouvier wrote:
My original motivation for having an extra ns_as (and caching
as/txattrs) was tied to the architectural semantics: a transaction being
"secure" does not automatically mean the walk can access Secure PAS.
Whether the walk can touch Secure PAS (or is effectiv... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Fri, 27 Feb 2026 23:20:48 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi Pierrick,
On 2026/2/26 04:55, Pierrick Bouvier wrote:
Thanks for the suggestion.
I'll refactor it like below：
switch (sec_sid) {
case SMMU_SEC_SID_S:
return ARMSS_Secure;
case SMMU_SEC_SID_NS:
return ARMSS_NonSecure;
case SMMU_SEC_SID_NUM:
g_assert_not_reached();
... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Fri, 27 Feb 2026 23:35:39 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi Pierrick,
On 2026/2/26 05:47, Pierrick Bouvier wrote:
Thank you for the review and the suggestion. I agree that using
SMMU_SEC_SID_NUM as a special value to trigger a full flush/invalidate
is not ideal in terms of readability.
I will adopt your approach and split the functions in the next version.
Best regard... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Fri, 27 Feb 2026 23:41:31 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi Pierrick,
On 2026/2/26 05:59, Pierrick Bouvier wrote:
Thanks for your suggestion. I will consider refactoring it after merging
the current series.
Best regards,
Tao | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Fri, 27 Feb 2026 23:44:22 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi Pierrick,
On 2026/2/26 05:31, Pierrick Bouvier wrote:
Thanks for the test!
Hafnium is indeed a good way to exercise Secure register and Secure
command queue access.
Best regards,
Tao | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 28 Feb 2026 00:13:24 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | As a preliminary step towards a multi-security-state configuration
cache, introduce MemTxAttrs and AddressSpace * members to the
SMMUTransCfg struct. The goal is to cache these attributes so that
internal functions can use them directly.
To facilitate this, hw/arm/arm-security.h is now included in
smmu-common.h. This ... | null | null | null | [RFC v4 08/31] hw/arm/smmuv3: Plumb transaction attributes into
config helpers | Hi Pierrick,
On 2026/2/26 06:20, Pierrick Bouvier wrote:
Let me take this opportunity to address the same concern you raised
across patches #07, #17, and #30 on the secure-impl vs secure-memory topic.
My initial intent was a demand-driven (lazy) validation model — i.e.
only validate Secure capability when a devi... | {
"author": "Tao Tang <tangtao1634@phytium.com.cn>",
"date": "Sat, 28 Feb 2026 00:16:15 +0800",
"is_openbsd": false,
"thread_id": "aaGsS9ldIqXZqhpk@google.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | If the Guest provides a DMA address that is associated with a ram
device (such as a VFIO PCI device region and not its system memory),
then we can obtain the hva (host virtual address) by invoking
address_space_translate() followed by memory_region_get_ram_ptr().
We cannot use dma_memory_map() because for memory regio... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:06 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | There are cases when a blob resource's backing might get detached
and re-attached again such as when the underlying object is getting
migrated in the Guest. In these situations, we need to obtain a new
dmabuf fd, which can be done by calling virtio_gpu_init_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:05 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Having a way to figure out the region index (or bar) associated
with a memory region is helpful in various scenarios. For example,
this capability can be useful in retrieving the region info needed
for mapping a part of a VFIO region or creating a dmabuf.
Cc: Alex Williamson <alex@shazbot.org>
Cc: Cédric Le Goater <cl... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:11 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | This is prep-work for adding the ability to create dmabuf fds from
VFIO devices in addition to udmabuf.
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson <... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:07 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | In order to mmap a dmabuf, we first need to create a placeholder
mapping that would fit the entire size of the dmabuf. This mapping
would then be replaced with smaller mappings of individual dmabuf
segments.
Cc: Alex Williamson <alex@shazbot.org>
Cc: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Vivek Kasireddy <vi... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:13 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | In addition to memfd, a blob resource can also have its backing
storage in a VFIO device region. Since, there is no effective way
to determine where the backing storage is located, we first try to
create a dmabuf assuming it is in memfd. If that fails, we try to
create a dmabuf assuming it is in VFIO device region.
So... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:14 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | The virtio-gpu driver running in the Guest VM can create Guest blob
resources (by importing dmabufs) that are backed by System RAM. This
is made possible by making use of memfd memory backend and udmabuf
driver on the Host side. However, in order to create Guest blobs
that are backed by vfio-pci device regions (which h... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:04 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | There is no need to wrap the call to qemu_ram_block_from_host() with
rcu_read_lock/unlock as we already hold a reference to the memory
region that owns the ram block. Note that, the reference was obtained
via dma_memory_map() while creating the mapping.
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Benn... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:08 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Make the error handling more robust in virtio_gpu_init_udmabuf()
by introducing 'Error **' parameter to capture errors and an enum
to categorize Guest and Host errors. This allows for better error
reporting and handling of errors from virtio_gpu_create_udmabuf()
and virtio_gpu_remap_dmabuf().
Cc: Marc-André Lureau <ma... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:10 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | In order to create a dmabuf associated with a buffer that spans
multiple ranges, we first need to identify the VFIO region and
index the buffer (represented by iovec) belongs to and then
translate its addresses to offsets within that region.
The qemu_ram_block_from_host() API gives us both the region and
the offset in... | {
"author": "Vivek Kasireddy <vivek.kasireddy@intel.com>",
"date": "Mon, 23 Feb 2026 00:00:12 -0800",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | On 2026/02/23 17:00, Vivek Kasireddy wrote:
This is VFIO's implementation and shouldn't be here. Follow what
hw/vfio/iommufd-stubs.c, the previously-mentioned example, does.
This logic is faulty. err is not set by vfio_device_create_dmabuf(), so
it reports a guest error even when the memory is compatible with
vfio... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Tue, 24 Feb 2026 12:51:55 +0900",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | On 2026/02/23 17:00, Vivek Kasireddy wrote:
include/qapi/error.h says:
Do what it says. Non-negative if *errp is set. Negative otherwise.
It is a valid ramblock even if rb->fd < 0. It is just "incompatible"
with udmabuf.
s/mem/memory/
The log is not that long so we can have a full correct spelling.
This print... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Tue, 24 Feb 2026 12:58:36 +0900",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Hi Akihiko,
Ok, I'll move this file to hw/vfio directory.
Maybe I misunderstood your previous comment about this but I thought
we are going to assume that if both virtio_gpu_create_udmabuf() and
vfio_device_create_dmabuf() fail (assuming Guest error in case of
virtio_gpu_create_udmabuf ()) then it is reasonable to as... | {
"author": "\"Kasireddy, Vivek\" <vivek.kasireddy@intel.com>",
"date": "Wed, 25 Feb 2026 06:03:48 +0000",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Hi Akihiko,
Ok, I'll change the values in the following way:
typedef enum VirtIOGPUErrorType {
VIRTIO_GPU_NO_ERROR = 1,
/* Guest is responsible for this error */
VIRTIO_GPU_GUEST_ERROR = -1,
/* Host is at fault for this error */
VIRTIO_GPU_HOST_ERROR = -2,
} VirtIOGPUErrorType;
Does "IOV memory ad... | {
"author": "\"Kasireddy, Vivek\" <vivek.kasireddy@intel.com>",
"date": "Wed, 25 Feb 2026 06:04:46 +0000",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | On 2026/02/25 15:03, Kasireddy, Vivek wrote:
It's not what I suggested. What I suggested is as follows:
https://lore.kernel.org/qemu-devel/c7c03384-4815-4032-89bd-de1ef90bb949@rsg.ci.i.u-tokyo.ac.jp/
It is not correct to assume vfio_device_create_dmabuf() is failed due to
a guest error when virtio_gpu_create_udmabu... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Wed, 25 Feb 2026 15:14:35 +0900",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | On 2026/02/25 15:04, Kasireddy, Vivek wrote:
scripts/checkpatch.pl explicitly allows to have a longer line for string
literals. Priotize the user-visible behavior than keeping the code tidy.
Do not locally override the behavior of the codebase-wide
infrastructure. If you think a guest error needs to be logged by
... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Wed, 25 Feb 2026 15:33:52 +0900",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Hi Akihiko,
Sounds good. I'll replace mem with memory.
Ok, I'll change it such that error_report_err(local_err) is only done in the
case of Host error. And, in the case of Guest error, I plan to just have
error_free(local_err) in addition to invoking qemu_log_mask().
Thanks,
Vivek | {
"author": "\"Kasireddy, Vivek\" <vivek.kasireddy@intel.com>",
"date": "Thu, 26 Feb 2026 06:18:28 +0000",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Hi Akihiko,
Ok, I plan to add the following enum and make it available to VFIO and
virtio-gpu-dmabuf.c:
typedef enum DmabufCreateErrorType {
DMABUF_CREATE_NO_ERROR = 1,
/* Guest is responsible for this error */
DMABUF_CREATE_GUEST_ERROR = -1,
/* Host is at fault for this error */
DMABUF_CREATE_HOST... | {
"author": "\"Kasireddy, Vivek\" <vivek.kasireddy@intel.com>",
"date": "Thu, 26 Feb 2026 06:22:34 +0000",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | On 2026/02/26 15:22, Kasireddy, Vivek wrote:
When there is no error, vfio_device_create_dmabuf() should return the
file descriptor instead (see e.g., qemu_open()).
I would prefix the names VFIO and put it into
include/hw/vfio/vfio-device.h.
In that case, using it for udmabuf is cheating, but I think it's fine
sinc... | {
"author": "Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>",
"date": "Thu, 26 Feb 2026 18:55:58 +0900",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | Avoid the manual g_free() calls for the list pointer by using
g_autofree in virtio_gpu_create_udmabuf().
Cc: Marc-André Lureau <marcandre.lureau@redhat.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Cc: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
Cc: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Cc: Alex Williamson ... | null | null | null | [PATCH v7 05/10] virtio-gpu-dmabuf: Use g_autofree for the list
pointer | Hi Akihiko,
Ok, I'll remove DMABUF_CREATE_NO_ERROR from this enum and follow
your suggestion to return fd in case of no error.
Ok, got it. I'll rename and move the enum to vfio-device.h.
Thanks,
Vivek | {
"author": "\"Kasireddy, Vivek\" <vivek.kasireddy@intel.com>",
"date": "Fri, 27 Feb 2026 02:06:23 +0000",
"is_openbsd": false,
"thread_id": "20260223080200.468558-1-vivek.kasireddy@intel.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Follow vendor-device syntax used with other RISCV cores
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
---
hw/riscv/opentitan.c | 2 +-
target/riscv/cpu-qom.h | 2 +-
target/riscv/cpu.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/o... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Thu, 27 Apr 2023 19:39:11 +0200",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | This is the start of efforts to contribute code from the lowRISC fork of
QEMU to bring the QEMU support for OpenTitan machines in line with Earl
Grey
1.0 by adding a new machine called ot-earlgrey. This work was done by
Emmanuel Blot and Loïc Lefort from Rivos, and various people at lowRISC.
This patch set in particula... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Fri, 20 Feb 2026 15:02:47 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Loïc Lefort <loic@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
---
include/hw/opentitan/ot_common.h | 93 ++++++++++++++++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 include/hw/opentitan/ot_common.h
diff --git a/include/hw/opentitan/ot_common.h b/include/hw/opentitan/o... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Fri, 17 Feb 2023 16:10:15 +0100",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Use a separate Kconfig symbols for Ibex UART, Timer, and SPI devices:
having an Ibex CPU does not imply usage of these specific implementations.
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
---
hw/char/Kconfig | 3 +++
hw/char/meson.build | 2 +-
hw/riscv/Kconfig... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Mon, 30 Jan 2023 13:14:50 +0100",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 7 ++++
target/riscv/ibex_csr.c | 85 ++++++++++++++++++++++++++++++++++++++++
target/riscv/m... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Tue, 07 Feb 2023 16:59:35 +0100",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
1. Define a generic version of lowrisc-ibex core that can be used in several machines:
- leave MISA empty so that generic properties can be defined for this core
- remove all arbitrary default properties but ISA I,C,U which are mandatory for ibex
- define default mtvec whic... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Thu, 27 Apr 2023 19:45:37 +0200",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
---
target/riscv/cpu.c | 24 ++++++++++++++++++++++++
target/riscv/cpu_cfg_fields.h.inc | 7 +++++++
2 files changed, 31 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 507061e8e9..73aa... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Wed, 15 Feb 2023 18:17:31 +0100",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org>
Includes existing MIT licenced code (already published elsewhere)
---
hw/opentitan/Kconfig | 2 +
hw/opentitan/meson.build | 1 +
hw/opentitan/ot_alert.c | 668 ++++++++++++++++++++++++++++++++
h... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Thu, 16 Feb 2023 17:11:22 +0100",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Lex Bailey <lex.bailey@lowrisc.org>
---
MAINTAINERS | 14 +-
hmp-commands-info.hx | 12 ++
hw/riscv/Kconfig | 3 +
hw/riscv/ibex_common.c | 316 ++++++++++++++++++++++++++++++++
hw/riscv/meson.build ... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Mon, 05 Jun 2023 12:24:08 +0200",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
---
target/riscv/ibex_csr.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target/riscv/ibex_csr.c b/target/riscv/ibex_csr.c
index d62638bbfb..a6e815e782 100644
--- a/target/riscv/ibex_csr.c... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Wed, 29 Mar 2023 19:16:44 +0200",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | From: Emmanuel Blot <eblot@rivosinc.com>
also adds property no_epmp_cfg on EarlGrey machine to disable
default ePMP configuration.
Usage:
qemu-system-riscv32 -M ot-earlgrey,no-epmp-cfg=true [...]
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Loïc Lefort <loic@rivosinc.com>
---
hw/riscv/ot_earlg... | {
"author": "~lexbaileylowrisc <lexbaileylowrisc@git.sr.ht>",
"date": "Wed, 15 Feb 2023 18:18:54 +0100",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | Hey Lex!
For some reason it looks like your patches are all dated to 2023,
probably the original date of the change made. Besides that, it looks
like its not on top of the master branch so they don't apply cleanly
when I try to pull them down (the two quick culprits I saw are the
hw/core/* files that got moved to be j... | {
"author": "Nabih Estefan <nabihestefan@google.com>",
"date": "Fri, 20 Feb 2026 14:33:40 -0800",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | On Thu, 2023-04-27 at 19:39 +0200, ~lexbaileylowrisc wrote:
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair | {
"author": "Alistair Francis <Alistair.Francis@wdc.com>",
"date": "Thu, 26 Feb 2026 23:46:48 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | On Mon, 2023-01-30 at 13:14 +0100, ~lexbaileylowrisc wrote:
Your patch titles are a little long. You don't need to include `qemu`
or `[ot]` in the patch and commit titles.
Why is this required though?
You are missing your SoB here (and in other patches)
Why does this need to be changed?
Alistair | {
"author": "Alistair Francis <Alistair.Francis@wdc.com>",
"date": "Thu, 26 Feb 2026 23:49:26 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | On Mon, 2023-06-05 at 12:24 +0200, ~lexbaileylowrisc wrote:
A change like this should be it's own patch.
But we should leave as is. It seems a bit strange to change it to a
email that has never reviewed or even submitted a patch.
If you guys want to help maintain things that's great! But let's start
off with some re... | {
"author": "Alistair Francis <Alistair.Francis@wdc.com>",
"date": "Thu, 26 Feb 2026 23:58:28 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | On Tue, 2023-02-07 at 16:59 +0100, ~lexbaileylowrisc wrote:
You need to add commit messages
This needs to be above the SoB
We don't want custom CSRs here
Is new MIT code allowed in QEMU?
Alistair | {
"author": "Alistair Francis <Alistair.Francis@wdc.com>",
"date": "Fri, 27 Feb 2026 00:04:06 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | On Thu, 2023-04-27 at 19:45 +0200, ~lexbaileylowrisc wrote:
There seems to be some extra churn in this patch
We want to match the QEMU code style
Alistair | {
"author": "Alistair Francis <Alistair.Francis@wdc.com>",
"date": "Fri, 27 Feb 2026 00:10:40 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | From: Emmanuel Blot <eblot@rivosinc.com>
Signed-off-by: Emmanuel Blot <eblot@rivosinc.com>
Includes existing MIT licenced code (already published elsewhere)
---
include/hw/riscv/ibex_irq.h | 69 +++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 include/hw/riscv/ibex_irq.h
di... | null | null | null | [PATCH qemu 10/11] [ot] hw/riscv: add an IRQ wrapper | On Fri, 2026-02-20 at 15:02 +0000, ~lexbaileylowrisc wrote:
Thanks for the patches!
I think we should just use the existing OpenTitan machine instead of
adding a new one
I gave a bunch of comments and some of them will apply to the entire
series.
In general:
- Commits need SoB lines and commit messages describin... | {
"author": "Alistair Francis <Alistair.Francis@wdc.com>",
"date": "Fri, 27 Feb 2026 00:19:41 +0000",
"is_openbsd": false,
"thread_id": "281f648affa677c3e3b9659b08b780c2abc9bb59.camel@wdc.com.mbox.gz"
} |
lkml_critique | qemu-devel | >From Windows 8.1 onwards ISA serial IRQs cannot be shared when ACPI Revision
5.0 is used in the FACP table. The reason for this is that if a 2-byte IRQ
Descriptor is used then the interrupt is considered to be high true, edge
sensitive, non-shareable. Since legacy serial ports COM1/3 and COM2/4 share
an IRQ then if mo... | null | null | null | [PATCH 0/5] isa-serial: acpi: declare shared IRQs for COM1/3 and
COM2/4 | The existing aml_interrupt() uses the Extended Interrupt Descriptor to store
the interrupt information, however newer Windows will only parse the
standard IRQ Descriptor when enumerating ISA serial ports.
Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
---
include/hw/acpi/aml-build.h | 2 ++
hw/acpi/am... | {
"author": "Mark Cave-Ayland <mark.caveayland@nutanix.com>",
"date": "Fri, 27 Feb 2026 13:44:55 +0000",
"is_openbsd": false,
"thread_id": "20260227134611.1229390-4-mark.caveayland@nutanix.com.mbox.gz"
} |
lkml_critique | qemu-devel | >From Windows 8.1 onwards ISA serial IRQs cannot be shared when ACPI Revision
5.0 is used in the FACP table. The reason for this is that if a 2-byte IRQ
Descriptor is used then the interrupt is considered to be high true, edge
sensitive, non-shareable. Since legacy serial ports COM1/3 and COM2/4 share
an IRQ then if mo... | null | null | null | [PATCH 0/5] isa-serial: acpi: declare shared IRQs for COM1/3 and
COM2/4 | Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
---
tests/qtest/bios-tables-test-allowed-diff.h | 47 +++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..cef44135bc 100644
--- a/te... | {
"author": "Mark Cave-Ayland <mark.caveayland@nutanix.com>",
"date": "Fri, 27 Feb 2026 13:44:57 +0000",
"is_openbsd": false,
"thread_id": "20260227134611.1229390-4-mark.caveayland@nutanix.com.mbox.gz"
} |
lkml_critique | qemu-devel | >From Windows 8.1 onwards ISA serial IRQs cannot be shared when ACPI Revision
5.0 is used in the FACP table. The reason for this is that if a 2-byte IRQ
Descriptor is used then the interrupt is considered to be high true, edge
sensitive, non-shareable. Since legacy serial ports COM1/3 and COM2/4 share
an IRQ then if mo... | null | null | null | [PATCH 0/5] isa-serial: acpi: declare shared IRQs for COM1/3 and
COM2/4 | These functions are required to generate a suitable _PRS entry for the
ISA serial ports.
Signed-off-by: Mark Cave-Ayland <mark.caveayland@nutanix.com>
---
include/hw/acpi/aml-build.h | 2 ++
hw/acpi/aml-build-stub.c | 10 ++++++++++
hw/acpi/aml-build.c | 15 +++++++++++++++
3 files changed, 27 insertions(... | {
"author": "Mark Cave-Ayland <mark.caveayland@nutanix.com>",
"date": "Fri, 27 Feb 2026 13:44:56 +0000",
"is_openbsd": false,
"thread_id": "20260227134611.1229390-4-mark.caveayland@nutanix.com.mbox.gz"
} |
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