data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | qemu-devel | >From Windows 8.1 onwards ISA serial IRQs cannot be shared when ACPI Revision
5.0 is used in the FACP table. The reason for this is that if a 2-byte IRQ
Descriptor is used then the interrupt is considered to be high true, edge
sensitive, non-shareable. Since legacy serial ports COM1/3 and COM2/4 share
an IRQ then if mo... | null | null | null | [PATCH 0/5] isa-serial: acpi: declare shared IRQs for COM1/3 and
COM2/4 | 5.0 is used in the FACP table. The reason for this is that if a 2-byte IRQ
Descriptor is used then the interrupt is considered to be high true, edge
sensitive, non-shareable. Since legacy serial ports COM1/3 and COM2/4 share
an IRQ then if more than 2 serial ports are added, Windows indicates a
conflict in Device Manag... | {
"author": "Mark Cave-Ayland <mark.caveayland@nutanix.com>",
"date": "Fri, 27 Feb 2026 13:44:58 +0000",
"is_openbsd": false,
"thread_id": "20260227134611.1229390-4-mark.caveayland@nutanix.com.mbox.gz"
} |
lkml_critique | qemu-devel | >From Windows 8.1 onwards ISA serial IRQs cannot be shared when ACPI Revision
5.0 is used in the FACP table. The reason for this is that if a 2-byte IRQ
Descriptor is used then the interrupt is considered to be high true, edge
sensitive, non-shareable. Since legacy serial ports COM1/3 and COM2/4 share
an IRQ then if mo... | null | null | null | [PATCH 0/5] isa-serial: acpi: declare shared IRQs for COM1/3 and
COM2/4 | Update the x86 ACPI tables to reflect the IRQ descriptor changes for ISA serial
ports:
Device (COM1)
{
Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID
Name (_UID, One) // _UID: Unique ID
... | {
"author": "Mark Cave-Ayland <mark.caveayland@nutanix.com>",
"date": "Fri, 27 Feb 2026 13:44:59 +0000",
"is_openbsd": false,
"thread_id": "20260227134611.1229390-4-mark.caveayland@nutanix.com.mbox.gz"
} |
lkml_critique | qemu-devel | This function will shortly be used to help find if there is a route to a
device, serving an HPA, under a particular fixed memory window. Rather than
having that new use case subtract the base address in the caller, only to
add it again in cxl_cfmws_find_device(), push the responsibility for
calculating the HPA to the c... | null | null | null | [PATCH v6 1/3] hw/cxl: Use HPA in cxl_cfmws_find_device() rather than
offset in window. | Hey everyone,
This is v6 of performant CXL type 3 regions set:
v5 -> v6:
- Use object_unparent() in the third commit when deleting alias regions.
- Thanks to Gregory for the suggestion and testing.
v4 -> v5:
- Fixed some minor patch style like missing trailing white space and such.
v3... | {
"author": "Alireza Sanaee via qemu development <qemu-devel@nongnu.org>",
"date": "Thu, 26 Feb 2026 15:20:31 +0000",
"is_openbsd": false,
"thread_id": "20260226152034.1523-1-alireza.sanaee@huawei.com.mbox.gz"
} |
lkml_critique | qemu-devel | This function will shortly be used to help find if there is a route to a
device, serving an HPA, under a particular fixed memory window. Rather than
having that new use case subtract the base address in the caller, only to
add it again in cxl_cfmws_find_device(), push the responsibility for
calculating the HPA to the c... | null | null | null | [PATCH v6 1/3] hw/cxl: Use HPA in cxl_cfmws_find_device() rather than
offset in window. | Extend cxl_cfmws_find_device() with a parameter that filters on whether the
address lies in an interleaved range. For now all callers accept
interleave configurations so no functional changes.
Signed-off-by: Alireza Sanaee <alireza.sanaee@huawei.com>
---
Change log:
v5->v6: No change.
hw/cxl/cxl-host.c | 33 ++++++++... | {
"author": "Alireza Sanaee via qemu development <qemu-devel@nongnu.org>",
"date": "Thu, 26 Feb 2026 15:20:33 +0000",
"is_openbsd": false,
"thread_id": "20260226152034.1523-1-alireza.sanaee@huawei.com.mbox.gz"
} |
lkml_critique | qemu-devel | This function will shortly be used to help find if there is a route to a
device, serving an HPA, under a particular fixed memory window. Rather than
having that new use case subtract the base address in the caller, only to
add it again in cxl_cfmws_find_device(), push the responsibility for
calculating the HPA to the c... | null | null | null | [PATCH v6 1/3] hw/cxl: Use HPA in cxl_cfmws_find_device() rather than
offset in window. | The CXL address to device decoding logic is complex because of the need to
correctly decode fine grained interleave. The current implementation
prevents use with KVM where executed instructions may reside in that memory
and gives very slow performance even in TCG.
In many real cases non interleaved memory configuratio... | {
"author": "Alireza Sanaee via qemu development <qemu-devel@nongnu.org>",
"date": "Thu, 26 Feb 2026 15:20:34 +0000",
"is_openbsd": false,
"thread_id": "20260226152034.1523-1-alireza.sanaee@huawei.com.mbox.gz"
} |
lkml_critique | qemu-devel | This function will shortly be used to help find if there is a route to a
device, serving an HPA, under a particular fixed memory window. Rather than
having that new use case subtract the base address in the caller, only to
add it again in cxl_cfmws_find_device(), push the responsibility for
calculating the HPA to the c... | null | null | null | [PATCH v6 1/3] hw/cxl: Use HPA in cxl_cfmws_find_device() rather than
offset in window. | (updated the recipient: s/ppbonzini@redhat.com/pbonzini@redhat.com)
On 26/02/2026 23:20, Alireza Sanaee wrote:
[..snip...]
Since this function always returns false and its return value is never used, it can be defined as void.
With that minor change, the patch looks good to me.
Reviewed-by: Li Zh... | {
"author": "\"Zhijian Li (Fujitsu)\" <lizhijian@fujitsu.com>",
"date": "Fri, 27 Feb 2026 09:50:29 +0000",
"is_openbsd": false,
"thread_id": "20260226152034.1523-1-alireza.sanaee@huawei.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Changelog v7->v8
- Edited documentation
[PATCH v7 01/29] Add boot-certs to s390-ccw-virtio machine type
option
- Updated version number from 10.2 to 11.0
[PATCH v7 02/29] crypto/x509-utils: Refactor with GNUTLS fallback
- Added Reviewed-by: Thomas Huth <thuth@redhat.com>
[PATCH v7 03/29] crypto/x509-utils: Add help... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:21 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Introduce helper functions to support signature verification required by
DIAG 508 subcode 1:
qcrypto_pkcs7_convert_sig_pem() – converts a signature from DER to PEM format
qcrypto_x509_verify_sig() – verifies the provided data against the given signature
These functions enable basic signature verification support.
Si... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:32 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Introduce a new `boot-certs` machine type option for the s390-ccw-virtio
machine. This allows users to specify one or more certificate file paths
or directories to be used during secure boot.
Each entry is specified using the syntax:
boot-certs.<index>.path=/path/to/cert.pem
Multiple paths can be specify using array... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:22 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | From: Collin Walling <walling@linux.ibm.com>
In order to support secure IPL (aka secure boot) for the s390-ccw BIOS,
a new s390 DIAGNOSE instruction is introduced to leverage QEMU for
handling operations such as signature verification and certificate
retrieval.
Currently, only subcode 0 is supported with this patch, ... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:31 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Introduce new helper functions for x509 certificate, which will be used
by the certificate store:
qcrypto_x509_convert_cert_der() - converts a certificate from PEM to DER format
These functions provide support for certificate format conversion.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Acked-by: Daniel P. Be... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:24 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Add secure-boot as a parameter of s390-ccw-virtio machine type option.
The `secure-boot=on|off` parameter is implemented to enable secure IPL.
By default, secure-boot is set to false if not specified in
the command line.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
--... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:44 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Add address range tracking and overlap checks to ensure that no
component overlaps with a signed component during secure IPL.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
---
pc-bios/s390-ccw/secure-ipl.c | 54 +++++++++++++++++++++++++++++++++++
pc-bios/s390-ccw/secure-ipl.h | 6 ++++
2 files changed, 60 inser... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:41 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | DIAG 320 subcode 1 provides information needed to determine
the amount of storage to store one or more certificates from the
certificate store.
Upon successful completion, this subcode returns information of the current
cert store, such as the number of certificates stored and allowed in the cert
store, amount of spac... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:28 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | The IPL information report block (IIRB) contains information used
to locate IPL records and to report the results of signature verification
of one or more secure components of the load device.
IIRB is stored immediately following the IPL Parameter Block. Results on
component verification in any case (failure or succes... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:34 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | The secure-IPL-code-loading-attributes facility (SCLAF)
provides additional security during secure IPL.
Availability of SCLAF is determined by byte 136 bit 3 of the
SCLP Read Info block.
This feature is available starting with the gen16 CPU model.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Collin... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:42 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Add documentation for secure IPL
Signed-off-by: Collin Walling <walling@linux.ibm.com>
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
---
docs/system/s390x/secure-ipl.rst | 96 ++++++++++++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/docs/system/s390x/secure-ipl.rst b/docs/system/s390x/secur... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:51 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | If secure boot in audit mode or True Secure IPL mode is enabled without
specifying a boot device, the boot process will terminate with an error.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
hw/s390x/ipl.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --gi... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:48 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Add documentation for secure IPL
Signed-off-by: Collin Walling <walling@linux.ibm.com>
---
docs/specs/s390x-secure-ipl.rst | 55 +++++++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/docs/specs/s390x-secure-ipl.rst b/docs/specs/s390x-secure-ipl.rst
index e7a93806f6..b20500529a 100644
--- a/... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:50 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Define a memory space for both IPL Parameter Block (IPLB) and
IPL Information Report Block (IIRB) since IIRB is stored immediately
following IPLB.
Convert IPLB to pointer and it points to the start of the defined memory space.
IIRB points to the end of IPLB.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
---
incl... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:35 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Refactor to enhance readability before enabling secure IPL in later
patches.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
pc-bios/s390-ccw/bootmap.c | 51 ++++++++++++++++++++++++--------------
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git a/pc-bios... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:38 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Add functional test for secure IPL.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
---
tests/functional/s390x/meson.build | 2 +
tests/functional/s390x/test_secure_ipl.py | 142 ++++++++++++++++++++++
2 files changed, 144 insertions(+)
create mode 100644 tests/functional/s390x/test_secure_ipl.py
diff --... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:49 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Make the address variable a parameter of zipl_load_segment and return
segment length.
Modify this function to allow the caller to specify a memory address
where segment data should be loaded into.
seg_len variable is necessary to store the calculated segment length and
is used during signature verification. Return th... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:39 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | The current approach to enable secure boot relies on providing
secure-boot and boot-certs parameters of s390-ccw-virtio machine
type option, which apply to all boot devices.
With the possibility of multiple boot devices, secure boot expects all
provided devices to be supported and eligible (e.g.,
virtio-blk/virtio-scs... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:47 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Enable secure IPL in audit mode, which performs signature verification,
but any error does not terminate the boot process. Only warnings will be
logged to the console instead.
Add a comp_len variable to store the length of a segment in
zipl_load_segment. comp_len variable is necessary to store the
calculated segment l... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:40 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Introduce new helper functions to extract certificate metadata:
qcrypto_x509_check_cert_times() - validates the certificate's validity period against the current time
qcrypto_x509_get_pk_algorithm() - returns the public key algorithm used in the certificate
qcrypto_x509_get_cert_key_id() - extracts the key ID from the... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:29 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Add additional checks to ensure that components do not overlap with
signed components when loaded into memory.
Add additional checks to ensure the load addresses of unsigned components
are greater than or equal to 0x2000.
When the secure IPL code loading attributes facility (SCLAF) is installed,
all signed components... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:43 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | When secure boot is enabled (-secure-boot on) and certificate(s) are
provided, the boot operates in True Secure IPL mode.
Any verification error during True Secure IPL mode will cause the
entire boot process to terminate.
Secure IPL in audit mode requires at least one certificate provided in
the key store along with ... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:46 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Always compile x509-utils.c and add a fallback when GNUTLS is
unavailable.
These functions will be needed in the s390x code regardless of whether
GNUTLS is available.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Acked-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.c... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:23 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Create a function to validate the address parameter of DIAGNOSE.
Refactor the function for reuse in the next patch, which allows address
validation in read or write operation of DIAGNOSE.
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Farhan Ali <alifm@linux.ibm.com>
Reviewed-by: Collin Walling <walli... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:27 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | DIAGNOSE 320 is introduced to support Certificate Store (CS)
Facility, which includes operations such as query certificate
storage information and provide certificates in the certificate
store.
Currently, only subcode 0 is supported with this patch, which is
used to query the Installed Subcodes Mask (ISM).
This subco... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:26 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Create a certificate store for boot certificates used for secure IPL.
Load certificates from the `boot-certs` parameter of s390-ccw-virtio
machine type option into the cert store.
Currently, only X.509 certificates in PEM format are supported, as the
QEMU command line accepts certificates in PEM format only.
Signed-... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:25 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | DIAG 320 subcode 2 provides verification-certificates (VCs) that are in the
certificate store. Only X509 certificates in DER format and SHA-256 hash
type are recognized.
The subcode value is denoted by setting the second-left-most bit
of an 8-byte field.
The Verification Certificate Block (VCB) contains the output da... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:30 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | From: Collin Walling <walling@linux.ibm.com>
DIAG 508 subcode 1 performs signature-verification on signed components.
A signed component may be a Linux kernel image, or any other signed
binary. **Verification of initrd is not supported.**
The instruction call expects two item-pairs: an address of a device
component, ... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:33 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | If `-M secure-boot=on` is specified on the command line option, indicating
true secure IPL enabled, set Secure-IPL bit and IPL-Information-Report
bit on in IPIB Flags field, and trigger true secure IPL in the S390 BIOS.
Any error that occurs during true secure IPL will cause the IPL to
terminate.
Signed-off-by: Zhuoy... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:45 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Introduce Secure-IPL (SIPL) facility.
Use fac_ipl to represent bytes 136 and 137 for IPL device facilities
of the SCLP Read Info block.
Availability of SIPL facility is determined by byte 136 bit 1 of the
SCLP Read Info block. Byte 136's facilities cannot be represented
without the availability of the extended-length... | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Thu, 12 Feb 2026 15:43:37 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Zhuoying Cai <zycai@linux.ibm.com> writes:
Does not build:
docs/specs/s390x-secure-ipl.rst:170: WARNING: Title underline too short.
Secure Code Loading Attributes Facility
--------------------------------- [docutils]
Please test with configure --enable-docs.
[...] | {
"author": "Markus Armbruster <armbru@redhat.com>",
"date": "Tue, 17 Feb 2026 09:06:32 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Zhuoying Cai <zycai@linux.ibm.com> writes:
[...]
Does not build:
docs/system/s390x/secure-ipl.rst:172: WARNING: Title underline too short.
Command line options for starting the guest
---------------------------- [docutils]
Please test with configure --enable-docs. | {
"author": "Markus Armbruster <armbru@redhat.com>",
"date": "Tue, 17 Feb 2026 09:06:36 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Zhuoying Cai <zycai@linux.ibm.com> writes:
[...]
Does not build for me:
../target/s390x/diag.c: In function ‘is_cert_valid’:
../target/s390x/diag.c:249:9: error: implicit declaration of function ‘error_report_err’; did you mean ‘error_report’? [-Wimplicit-function-declaration]
249 | error_rep... | {
"author": "Markus Armbruster <armbru@redhat.com>",
"date": "Tue, 17 Feb 2026 09:18:40 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Markus Armbruster <armbru@redhat.com> writes:
With that fixed, I get
docs/specs/s390x-secure-ipl.rst: WARNING: document isn't included in any toctree [toc.not_included]
[...] | {
"author": "Markus Armbruster <armbru@redhat.com>",
"date": "Tue, 17 Feb 2026 09:19:54 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Markus Armbruster <armbru@redhat.com> writes:
With that fixed, I get
docs/specs/s390x-secure-ipl.rst: WARNING: document isn't included in any toctree [toc.not_included] | {
"author": "Markus Armbruster <armbru@redhat.com>",
"date": "Tue, 17 Feb 2026 09:20:30 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | Zhuoying Cai <zycai@linux.ibm.com> writes:
[...]
certificates
You have to indent like this
# @path: path to an X.509 certificate file or a directory containing
# certificate files.
As is, it gets rendered like
Object BootCertificates (Since: 11.0)
Boot certificate for secure IPL.
... | {
"author": "Markus Armbruster <armbru@redhat.com>",
"date": "Tue, 17 Feb 2026 09:30:00 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | On 2/17/26 3:20 AM, Markus Armbruster wrote:
Thank you for the review. I’ll test the series with configure
--enable-docs and will fix the documentation build issues in the next
version. | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Tue, 17 Feb 2026 15:29:23 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | On 2/17/26 3:18 AM, Markus Armbruster wrote:
Thanks for pointing this out. The build error is resolved by adding
#include "qapi/error.h" to the file. I’ll update this in the next version. | {
"author": "Zhuoying Cai <zycai@linux.ibm.com>",
"date": "Tue, 17 Feb 2026 16:29:22 -0500",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | On 12/02/2026 21.43, Zhuoying Cai wrote:
...
...
I'd maybe write it like this to decrease indentation:
g_autofree S390IPLCertificate *cert =
init_cert((char *) cert_path_builder->pdata[i],
&err);
... but up to you, it's just cosmetics.
...
...
Why is there... | {
"author": "Thomas Huth <thuth@redhat.com>",
"date": "Thu, 26 Feb 2026 17:02:05 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | On 12/02/2026 21.43, Zhuoying Cai wrote:
I think I'd rather say "guest code" instead of "userspace" in the above two
sentences, to avoid confusion. "userspace" is normally everything that does
not belong to the kernel, so the term sounds rather misleading here.
Anyway, with that confusion fixed:
Reviewed-by: Thomas ... | {
"author": "Thomas Huth <thuth@redhat.com>",
"date": "Fri, 27 Feb 2026 13:41:33 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | Add IPIB flags to IPL Parameter Block to determine if IPL needs to
perform securely and if IPL Information Report Block (IIRB) exists.
Move DIAG308 flags to a separated header file and add flags for secure IPL.
Secure boot in audit mode will perform if certificate(s) exist in the
key store. IIRB will exist and result... | null | null | null | [PATCH v8 15/30] hw/s390x/ipl: Add IPIB flags to IPL Parameter Block | On 12/02/2026 21.43, Zhuoying Cai wrote:
...
Since this API between QEMU and the guest, maybe add a
QEMU_BUILD_BUG_ON(sizeof(VCStorageSizeBlock) != ...);
here to make sure that there is no accidential padding.
(should not happen since field are naturally aligned, but better be safe
than sorry?)
Thanks for adding ... | {
"author": "Thomas Huth <thuth@redhat.com>",
"date": "Fri, 27 Feb 2026 13:58:06 +0100",
"is_openbsd": false,
"thread_id": "a80ebb96-2f18-4be2-839e-409b3d30defc@redhat.com.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | We allocate the string for the GPIO property name, but never free it.
Use g_autofree to avoid this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/gpio/aspeed_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index d9237d4360..7d0f... | {
"author": "Peter Maydell <peter.maydell@linaro.org>",
"date": "Fri, 27 Feb 2026 13:57:35 +0000",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | The oss-fuzz code uses an lsan_suppressions file to suppress certain
leak-sanitizer cases that are known issues or not our code's bug.
This is useful more widely than just for the fuzzer harness: if you
want to build QEMU with the leak sanitizer enabled and run 'make
check' then you will want to suppress some bogus lea... | {
"author": "Peter Maydell <peter.maydell@linaro.org>",
"date": "Fri, 27 Feb 2026 13:57:33 +0000",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | Running "make check" with the clang leak sanitizer reveals some
leak reports which are either not our problem or else not
a leak which is worth our time to fix. Add some suppressions
for these.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
scripts/lsan_suppressions.txt | 20 ++++++++++++++++++++
1 file ... | {
"author": "Peter Maydell <peter.maydell@linaro.org>",
"date": "Fri, 27 Feb 2026 13:57:34 +0000",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | The QPCIDevice we get via qpci_device_foreach() is allocated
memory, and we need to g_free() it after use.
This fixes asan leaks like this:
Direct leak of 64 byte(s) in 1 object(s) allocated from:
#0 0x622a5f16913d in calloc (/home/pm215/qemu/build/arm-clang/tests/qtest/iommu-smmuv3-test+0x1d413d) (BuildId: bc598... | {
"author": "Peter Maydell <peter.maydell@linaro.org>",
"date": "Fri, 27 Feb 2026 13:57:36 +0000",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | I forgot to cc the 'device fuzzing' maintainers on this patch;
sorry about that.
-- PMM
On Fri, 27 Feb 2026 at 13:57, Peter Maydell <peter.maydell@linaro.org> wrote: | {
"author": "Peter Maydell <peter.maydell@linaro.org>",
"date": "Fri, 27 Feb 2026 15:04:53 +0000",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | Hi, Peter
On 27/02/2026 09:04, Peter Maydell wrote:
The similarity index is under 40%, so `git log --follow` doesn't follow
the move; not a big deal, but separate patches for the move and the new
lines would avoid this and make it easier for folks to get the full
history in one go.
Also, there's a missed reference i... | {
"author": "Yodel Eldar <yodel.eldar@yodel.dev>",
"date": "Fri, 27 Feb 2026 09:32:27 -0600",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | This patchset fixes a couple of minor memory leaks I found by running
"make check" for the arm targets with the clang leak sanitizer enabled.
The first two patches are necessary because there are a few leaks
that are either not interesting to fix or which are not in our code,
and which otherwise clutter up the logs wi... | null | null | null | [PATCH 0/4] arm: Fix some memory leaks | On Fri, 27 Feb 2026 at 15:32, Yodel Eldar <yodel.eldar@yodel.dev> wrote:
Oops, thanks for catching that.
-- PMM | {
"author": "Peter Maydell <peter.maydell@linaro.org>",
"date": "Fri, 27 Feb 2026 15:41:27 +0000",
"is_openbsd": false,
"thread_id": "20260227135736.2280161-3-peter.maydell@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | physmem.c defines 2 stubs which are related to ram-block:
qemu_ram_block_from_host() and qemu_ram_get_fd().
Move them with the other ram-block stubs.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
stubs/physmem.c | 13 -------------
stubs/ram-block.c | 11 +++++++++++
stubs/meson.build | 1 -
3 file... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:19 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | Mark the MemoryRegion structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/memory.h | 28 ++++++++++++++--------------
system/memory.c | 34 ++++++++++++++++++----------------
2 files changed, 32 insertions(+), 30 deletions(-)
diff --gi... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:21 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | Cleaning dust, I had forgotten about this branch. In short,
it improves 'info mtree' readability of addresses.
Currently with Q35:
address-space: I/O
0000000000000000-000000000000ffff (prio 0, i/o): io
0000000000000000-0000000000000003 (prio 0, i/o): acpi-evt
0000000000000004-00000000000... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:18 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | MemoryRegion containers are not I/O regions,
describe them as 'container'.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
system/memory.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/system/memory.c b/system/memory.c
index eeb0d19484f..d5060774834 100644
--- a/system/memory.c
+++ b/system/memo... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:22 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | Use the size of a MR / AS to decide how many address chars
need to be used.
For example, using 'qemu-system-x86_64 -M q35 -S -monitor stdio'
to run 'info mtree' displays before:
address-space: I/O
0000000000000000-000000000000ffff (prio 0, i/o): io
0000000000000000-0000000000000003 (prio 0, i/o): acpi-e... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:25 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | Since AddressSpace root MemoryRegion can be remapped, it is
bogus to use the MemoryRegion address as the AddressSpace
absolute address. Besides, the AddressSpace APIs take an
@addr argument expecting AddressSpaces start at 0x0000.0000.
Substract the MemoryRegion address in mtree_print_mr() to
display AddressSpaces sta... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:23 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | mtree_print_mr() display addresses using 16 chars on 64-bit
binaries, and 8 chars on 32-bit ones. Some MR / AS don't
always benefit of 16 chars, for example the ISA I/O region
fits in 16 bits, and displaying 12 extra '0' in 64-bit
binaries isn't really a good user experience.
Add an extra @width argument to mtree_prin... | {
"author": "=?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Thu, 26 Feb 2026 23:02:24 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | On 2/26/26 2:02 PM, Philippe Mathieu-Daudé wrote:
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Thu, 26 Feb 2026 14:22:03 -0800",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | On Thu, 26 Feb 2026, Philippe Mathieu-Daudé wrote:
Maybe should be the other way around moving what's in subs/ram-block.c to
stubs/physmem.c considering the the functions these stub out are in
system/physmem.c and there's no system/ram-block.c.
Regards,
BALATON Zoltan | {
"author": "BALATON Zoltan <balaton@eik.bme.hu>",
"date": "Thu, 26 Feb 2026 23:22:32 +0100 (CET)",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | On 2/26/26 2:02 PM, Philippe Mathieu-Daudé wrote:
That is so neat!
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> | {
"author": "Pierrick Bouvier <pierrick.bouvier@linaro.org>",
"date": "Thu, 26 Feb 2026 14:26:09 -0800",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | On Thu, 26 Feb 2026, Philippe Mathieu-Daud wrote:
Why 20? HWADDR_FMT_plx this seems to replace is "%016" PRIx64
Regards,
BALATON Zoltan | {
"author": "BALATON Zoltan <balaton@eik.bme.hu>",
"date": "Thu, 26 Feb 2026 23:35:38 +0100 (CET)",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Mark the RAMBlock structure const when is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/system/ramblock.h | 26 +++++++++++++-------------
stubs/ram-block.c | 8 ++++----
system/physmem.c | 26 +++++++++++++-------------
3 files changed, 30 insertions... | null | null | null | [PATCH 2/7] system/ramblock: Constify various RAMBlock arguments | Hi Zoltan,
On 26/2/26 23:35, BALATON Zoltan wrote:
HWADDR_FMT_plx predates support for int128_t and 128-bit wide
addresses. Using 20 chars is sufficient to align our current
uses.
I'll precise that in the patch description.
Regards,
Phil. | {
"author": "=?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>",
"date": "Fri, 27 Feb 2026 17:20:02 +0100",
"is_openbsd": false,
"thread_id": "0a910d27-cb1d-4495-90ee-3674fd8ee564@linaro.org.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Add a helper to allocate an iommufd backed HW queue for a vIOMMU.
While at it, define a struct IOMMUFDHWqueue for use by vendor
implementations.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Shameer Kolothum <... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:27 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
The updated IOMMUFD uAPI introduces the ability for userspace to request
a specific hardware info data type via IOMMU_GET_HW_INFO. Update
iommufd_backend_get_device_info() to set IOMMU_HW_INFO_FLAG_INPUT_TYPE
when a non-zero type is supplied, and adjust all callers to pass a ty... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:25 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Stop walking the object tree to discover SMMUv3 devices when building
the IORT table.
Use the SMMUv3 device array maintained by the virt machine instead,
avoiding recursive object traversal.
No functional change intended.
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/virt-acpi-build.c | 70 ++... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:33 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Introduce a GPtrArray in VirtMachineState to keep track of all
SMMUv3 devices created on the virt machine.
This will avoid relying on object_child_foreach_recursive() walks
of the object tree when accessing SMMUv3 instances. Subsequent
patches will use this list during ACPI IORT table generation and
for CMDQV-related ... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:32 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Introduce a Tegra241 CMDQV backend that plugs into the SMMUv3 accelerated
CMDQV ops interface.
This patch wires up the Tegra241 CMDQV backend and provides a stub
implementation for CMDQV probe, initialization, vIOMMU allocation
and reset handling.
Functional CMDQV support is added in follow-up patches.
Signed-off-by... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:30 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Replace the stub implementation with real vIOMMU allocation for
Tegra241 CMDQV.
Free the vIOMMU ID on teardown.
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/tegra241-cmdqv.c | 19 +++++++++++++++++--
1... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:37 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Tegra241 CMDQV defines a set of global control and status registers
used to configure virtual command queue allocation and interrupt
behavior.
Add read/write emulation for the global CMDQV register page
(offset 0x00000), backed by a simple register cache. This includes
CONFIG,... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:38 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
This is the write side counterpart of the VCMDQ read emulation.
Add write handling for global VCMDQ and VI_VCMDQ register windows.
Per-VCMDQ accesses are decoded into a VCMDQ index and normalized to
VCMDQ0_* offsets, reusing the same layout assumptions as the read path.
VI_VC... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:40 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
VINTF page0 is backed by host memory returned by the kernel via mmap.
Instead of trapping and emulating accesses to this region, map it
directly into the guest-visible MMIO space.
The VINTF page0 MMIO region is created lazily when the first VCMDQ
hardware queue is allocated. W... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:45 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Update the reference IORT blobs after identifier change for SMMUv3 nodes.
This affects the aarch64 'virt' IORT tests.
IORT diff is the identifier change in SMMUv3 nodes:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20230628 (64-bit version)
* Copyright (c) 2000 - 2023 Intel Corporatio... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:53 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Tegra241 CMDQV exposes per-VCMDQ register windows through two MMIO views:
-Global VCMDQ registers at 0x10000/0x20000
-VINTF VCMDQ (VI_VCMDQ) registers at 0x30000/0x40000
The VI_VCMDQ register ranges are an alias of the global VCMDQ registers
and are only meaningful when a... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:39 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Allocate a CMDQV specific vEVENTQ via IOMMUFD, and add the
corresponding teardown path to free the vEVENTQ during cleanup.
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/smmuv3-accel.h | 2 ++
hw/arm/tegra241-cmdqv.h | 1 +
hw/arm/smmuv3-accel.c | 10 ++++++++-
hw/arm/tegra241-cmdqv.c | 47... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:46 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | When a VCMDQ is allocated and VINTF page0 has been mmap'ed from the
kernel, access the VCMDQ registers directly through the VINTF page0
backing instead of using QEMU's cached register state.
VINTF page0 provides the backing memory region for VCMDQ registers
once a hardware queue is created. In that case, reads and wri... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:44 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Introduce a “cmdqv” property to enable Tegra241 CMDQV support.
This is only enabled for accelerated SMMUv3 devices.
Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/smmuv3.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/arm/smmuv3.c b... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:56 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Hi,
Changes from v2:
https://lore.kernel.org/qemu-devel/20260206144823.80655-1-skolothumtho@nvidia.com/
- Addressed feedback on v2 and picked up R-by tags. Thanks!
- Renamed the property from "tegra241-cmdqv" to a generic OnOffAuto
"cmdqv".
- Introduced a probe() callback to detect and initialize CMDQV
... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:24 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Introduce a reset handler for the Tegra241 CMDQV and initialize its
register state.
CMDQV gets initialized early during guest boot, hence the handler verifies
that at least one cold-plugged device is attached to the associated vIOMMU
before proceeding. This is required to retr... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:49 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Add support for selecting and initializing a CMDQV backend based on
the cmdqv OnOffAuto property.
If set to OFF, CMDQV is not used and the default IOMMUFD-backed
allocation path is taken.
If set to AUTO, QEMU attempts to probe a CMDQV backend during
device setup. If probing succeeds, the selected ops are stored
in th... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:31 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Tegra241 CMDQV extends SMMUv3 with support for virtual command queues
(VCMDQs) exposed via a CMDQV MMIO region. The CMDQV MMIO space is split
into 64KB pages:
0x00000: Global CMDQV registers
0x10000: Global VCMDQ registers, Page0
0x20000: Global VCMDQ registers, Page1
0x30000:... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:35 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Add a backend helper to mmap hardware MMIO regions exposed via iommufd for
a vIOMMU instance. This allows user space to access HW-accelerated MMIO
pages provided by the vIOMMU.
The caller is responsible for unmapping the returned region.
Signed-off-by: Nicolin Chen <nicolinc@... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:28 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Move the vEVENTQ read and validation logic into a common helper.
The helper performs the read(), checks for overflow and short reads,
validates the sequence number, and updates the sequence state.
This helper can be reused in the subsequent patch for Tegra241 CMDQV
vEVENTQ support.
Error handling is slightly adjuste... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:47 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Use IOMMU_GET_HW_INFO to check whether the host supports Tegra241 CMDQV.
Validate the returned data type, version, number of vCMDQs and SIDs per
VM. Fail the probe if the host does not meet the expected requirements.
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/tegra241-cmdqv.h | 5 +++++
hw... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:34 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Add support for allocating IOMMUFD hardware queues when the guest
programs the VCMDQ BASE registers.
VCMDQ_EN is part of the VCMDQ_CONFIG register, which is accessed
through the VINTF Page0 region. This region is mapped directly into
the guest address space (introduced in a su... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:43 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Add an "identifier" property to the SMMUv3 device and use it when
building the ACPI IORT SMMUv3 node Identifier field.
This avoids relying on device enumeration order and provides a stable
per-device identifier. A subsequent patch will use the same identifier
when generating the DSDT description for Tegra241 CMDQV, en... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:52 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
CMDQV HW reads guest queue memory in its host physical address setup via
IOMUUFD. This requires the guest queue memory isn't only contiguous in
guest PA space but also in host PA space. With Tegra241 CMDQV enabled, we
must only advertise a CMDQV size that the host can safely ba... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:50 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Introduce address_space_is_ram(), a helper to determine whether
a guest physical address resolves to a RAM-backed MemoryRegion within
an AddressSpace.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
include/system/memory.h | 10 ++++++++++
system/physmem.c... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:42 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Introduce a SMMUv3AccelCmdqvType enum and a helper to query the
CMDQV implementation type associated with an accelerated SMMUv3
instance.
A subsequent patch will use this helper when generating the
Tegra241 CMDQV DSDT.
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/smmuv3-accel.h | 7 +++... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:54 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | The IORT SMMUv3 node Identifier field will be derived from a new
per-device "identifier" property instead of relying on enumeration
order.
Add the affected IORT blobs to allowed-diff list for bios-table tests.
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
tests/qtest/bios-tables-test-allowed-diff.h |... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:51 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Global VCMDQ pages provide a VM wide view of all VCMDQs, while the
VINTF pages expose a logical view local to a given VINTF. Although real
hardware may support multiple VINTFs, the kernel currently exposes a
single VINTF per VM.
The kernel provides an mmap offset for the VINTF... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:41 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | SMMUv3 devices with acceleration may enable CMDQV extensions
after device realize. In that case, additional MMIO regions and
IRQ lines may be registered but not yet mapped to the platform bus.
Ensure SMMUv3 device resources are linked to the platform bus
during machine_done().
This is safe to do unconditionally since... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:36 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
Add ACPI DSDT support for Tegra241 CMDQV when the SMMUv3 instance is
created with tegra241-cmdqv.
The SMMUv3 device identifier is used as the ACPI _UID. This matches
the Identifier field of the corresponding SMMUv3 IORT node, allowing
the CMDQV DSDT device to be correctly asso... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:55 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | From: Nicolin Chen <nicolinc@nvidia.com>
The updated IOMMUFD VIOMMU_ALLOC uAPI allows userspace to provide a data
buffer when creating a vIOMMU (e.g. for Tegra241 CMDQV). Extend
iommufd_backend_alloc_viommu() to pass a user pointer and size to the
kernel.
Update the caller accordingly.
Signed-off-by: Nicolin Chen <n... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:26 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | Install an event handler on the CMDQV vEVENTQ fd to read and propagate
host received CMDQV errors to the guest.
The handler runs in QEMU’s main loop, using a non-blocking fd registered
via qemu_set_fd_handler().
Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
---
hw/arm/tegra241-cmdqv.c | 58 ++++++++++++++... | {
"author": "Shameer Kolothum <skolothumtho@nvidia.com>",
"date": "Thu, 26 Feb 2026 10:50:48 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | Command Queue Virtualization (CMDQV) is a hardware extension available
on certain platforms that allows the SMMUv3 command queue to be
virtualized and passed through to a VM, improving performance.
For example, NVIDIA Tegra241 implements CMDQV to support virtualization
of multiple command queues (VCMDQs).
The term CM... | null | null | null | [PATCH v3 05/32] hw/arm/smmuv3-accel: Introduce CMDQV ops interface | On Thu, 26 Feb 2026 10:50:39 +0000
Shameer Kolothum <skolothumtho@nvidia.com> wrote:
Hi Shameer,
As noted below there are a lot of repeats of 0x80 and the register window offsets in here.
Maybe some defines would make things clearer?
There are a lot of repeated numeric values of offsets and sizes in here.
I'm a bit ... | {
"author": "Jonathan Cameron via qemu development <qemu-devel@nongnu.org>",
"date": "Fri, 27 Feb 2026 15:58:28 +0000",
"is_openbsd": false,
"thread_id": "20260226105056.897-1-skolothumtho@nvidia.com.mbox.gz"
} |
lkml_critique | qemu-devel | The HTTPs curl block driver is a superset of the HTTP driver, reflect
that in the QAPI.
Suggested-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Antoine Damhet <adamhet@scaleway.com>
---
qapi/block-core.json | 13 ++-----------
1 file changed, 2 insertions(... | null | null | null | [PATCH v3 2/3] qapi: block: Refactor HTTP(s) common arguments | Hi,
This series adds the support for S3 presigned URLs that only allow HTTP
GET requests. While working on this I also stumbled upon a deadlock with
concurrent I/O and slipped the fix here. Over the years there was
already an attempt to support these kinds of URLs[1] and at least one
report of a user in need of the fe... | {
"author": "Antoine Damhet <adamhet@scaleway.com>",
"date": "Fri, 27 Feb 2026 13:45:50 +0100",
"is_openbsd": false,
"thread_id": "20260227-fix-curl-v3-v3-1-eb8a4d88feef@scaleway.com.mbox.gz"
} |
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