data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:55PM +0900, Koichiro Den wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 16:03:37 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:56PM +0900, Koichiro Den wrote:
db_count -1 or db_count-2, previous patch use db_count-2
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 16:07:14 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:57PM +0900, Koichiro Den wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 16:09:01 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:58PM +0900, Koichiro Den wrote:
Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 16:11:23 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:59PM +0900, Koichiro Den wrote:
return max(ntb_ndev(ntb)->db_count - 1, 0);
Anyway: Reviewed-by: Frank Li <Frank.Li@nxp.com> | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 16:13:07 -0500",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Wed, Feb 25, 2026 at 03:36:05PM -0500, Frank Li wrote:
I don't think so. ntb_peer_db_set() can be invoked from softirq context.
Thanks for the review,
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 26 Feb 2026 10:02:17 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Wed, Feb 25, 2026 at 04:07:14PM -0500, Frank Li wrote:
pci-epf-vntb.c (struct epf_ntb) and ntb_hw_epf.c (struct ntb_epf_dev) define
"db_count" slightly differently, historically.
In pci-epf-vntb, db_count is configured via configfs and covers the entire
doorbell register range. The capacity is hard-wired into the ... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 26 Feb 2026 10:25:49 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Wed, Feb 25, 2026 at 09:59:46AM -0700, Dave Jiang wrote:
Thanks for the suggestion, that sounds reasonable. I'd be happy to use the enum
names as proposed.
Frank, I'd like to introduce the same kind of enum in Patch 3 to eliminate
0/1/2 magic numbers for clarity and consistency. Please let me know if you have
a di... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 26 Feb 2026 12:17:25 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Wed, Feb 25, 2026 at 09:47:43AM -0700, Dave Jiang wrote:
Will do in v2. Thanks for the suggestion.
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 26 Feb 2026 12:24:22 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Wed, Feb 25, 2026 at 04:02:01PM -0500, Frank Li wrote:
db_count is u32, so it could underflow.
If a one-liner is preferred, something like:
max_t(u32, ndev->db_count, 2U) - 2
would work. Personally, I think the original version is clearer.
Thanks,
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Fri, 27 Feb 2026 15:23:53 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | vntb_epf_peer_db_set() raises an MSI interrupt to notify the RC side of
a doorbell event. pci_epc_raise_irq(..., PCI_IRQ_MSI, interrupt_num)
takes a 1-based MSI interrupt number.
The ntb_hw_epf driver reserves MSI #1 for link events, so doorbells
would naturally start at MSI #2 (doorbell bit 0 -> MSI #2). However,
pci... | null | null | null | [PATCH 01/10] PCI: endpoint: pci-epf-vntb: Document legacy MSI doorbell offset | On Tue, Feb 24, 2026 at 10:34:51PM +0900, Koichiro Den wrote:
I noticed that this kept-as-is comment from Patch #1 is stale. The code below
uses "+2" for the legacy offset, so the explanation no longer matches the
implementation. I'll update the comment in v2.
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Fri, 27 Feb 2026 16:32:29 +0900",
"is_openbsd": false,
"thread_id": "vg4xjeq72djep3je5w35nuxtt3eixl2ppyc6wayj7dgpmwodkq@inn3ozg3p2zu.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Add Device Tree binding documentation for the Eswin EIC7700 PCIe
controller module, the PCIe controller enables the core to correctly
initialize and manage the PCIe bus and connected devices.
Signed-off-by: Yu Ning <ningyu@eswincomputing.com>
Signed-off-by: Yang... | {
"author": "zhangsenchuan@eswincomputing.com",
"date": "Thu, 29 Jan 2026 17:28:40 +0800",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Add driver for the Eswin EIC7700 PCIe host controller, which is based on
the DesignWare PCIe core, IP revision 5.96a. The PCIe Gen.3 controller
supports a data rate of 8 GT/s and 4 channels, support INTx and MSI
interrupts.
Signed-off-by: Yu Ning <ningyu@eswinco... | {
"author": "zhangsenchuan@eswincomputing.com",
"date": "Thu, 29 Jan 2026 17:29:00 +0800",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Thu, 29 Jan 2026 17:26:28 +0800, zhangsenchuan@eswincomputing.com wrote:
Applied, thanks!
[1/2] dt-bindings: PCI: eic7700: Add Eswin PCIe host controller
(no commit info)
[2/2] PCI: eic7700: Add Eswin PCIe host controller driver
(no commit info)
Best regards,
--
Leon Romanovsky <leon@kernel.org> | {
"author": "Leon Romanovsky <leon@kernel.org>",
"date": "Sun, 01 Feb 2026 07:24:54 -0500",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Sun, Feb 01, 2026 at 07:24:54AM -0500, Leon Romanovsky wrote:
Sorry for the noise. The issue was caused by a mistake in my scripts.
Of course, it was never applied.
Thanks | {
"author": "Leon Romanovsky <leon@kernel.org>",
"date": "Sun, 1 Feb 2026 14:28:10 +0200",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Sun, Feb 01, 2026 at 02:28:10PM +0200, Leon Romanovsky wrote:
I was about to scream, but glad that this didn't happen.
- Mani
--
மணிவண்ணன் சதாசிவம் | {
"author": "Manivannan Sadhasivam <mani@kernel.org>",
"date": "Mon, 2 Feb 2026 16:27:26 +0530",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Thu, Jan 29, 2026 at 05:26:28PM +0800, zhangsenchuan@eswincomputing.com wrote:
This version looks good to me, but it'd be good if Bjorn could give an Ack since
there were previous reviews from him. Also, this week is -rc8, so it is too late
for 7.0. I hope we can merge this series early, once v7.0-rc1 is released.
... | {
"author": "Manivannan Sadhasivam <mani@kernel.org>",
"date": "Mon, 2 Feb 2026 16:29:51 +0530",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Mon, Feb 02, 2026 at 04:29:51PM +0530, Manivannan Sadhasivam wrote:
Will do, ping me after v7.0-rc1 to remind me. | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 6 Feb 2026 16:20:42 -0600",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Thu, Jan 29, 2026 at 05:29:00PM +0800, zhangsenchuan@eswincomputing.com wrote:
With 7.0, you can provide a dummy pme_turn_off() API and set
'pci->pp.skip_l23_ready' to reuse the dw_pcie_{suspend/resume}_noirq APIs.
- Mani
--
மணிவண்ணன் சதாசிவம் | {
"author": "Manivannan Sadhasivam <mani@kernel.org>",
"date": "Wed, 18 Feb 2026 18:17:14 +0530",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | Hi Mani,
Setting pci->pp.skip_l23_ready does indeed allow us to reuse the
dw_pcie_suspend_noirq function. However, for the dw_pcie_resume_noirq
function, if the dw_pcie_start_link and dw_pcie_wait_for_link APIs fail to
execute, the clk/reset resources in the pci->pp.ops->init function cannot
be released. Perhaps the d... | {
"author": "zhangsenchuan <zhangsenchuan@eswincomputing.com>",
"date": "Tue, 24 Feb 2026 16:14:16 +0800 (GMT+08:00)",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Tue, Feb 24, 2026 at 04:14:16PM +0800, zhangsenchuan wrote:
Will this help?
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 6ae6189e9b8a..38ad79bbeab1 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller... | {
"author": "Manivannan Sadhasivam <mani@kernel.org>",
"date": "Wed, 25 Feb 2026 19:07:32 +0530",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | Yes, this can release the resources after init, after optimizing the
resume function, i can reuse the dw_pcie_{suspend/resume}_noirq APIs.
I noticed that the dw_pcie_wait_for_link function has been optimized. Is
it necessary to release the resources only when it return -ETIMEOUT?
Perhaps it needs to be slightly impr... | {
"author": "zhangsenchuan <zhangsenchuan@eswincomputing.com>",
"date": "Thu, 26 Feb 2026 16:09:44 +0800 (GMT+08:00)",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Thu, Feb 26, 2026 at 04:09:44PM +0800, zhangsenchuan wrote:
Absolutely! I forgot my own rework ;) I'll cook a patch for the above. Then if
you base your controller driver patch on top of it, we can merge both in a
single tree (if Bjorn agrees).
- Mani
--
மணிவண்ணன் சதாசிவம் | {
"author": "Manivannan Sadhasivam <mani@kernel.org>",
"date": "Thu, 26 Feb 2026 14:06:54 +0530",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | Okey,thanks!
I'm a little unsure. Do I need to send the v11 patch here first? Or should I wait
until you release the new fix patch, and then send the v11 patch?
Kind regards,
Senchuan | {
"author": "zhangsenchuan <zhangsenchuan@eswincomputing.com>",
"date": "Thu, 26 Feb 2026 17:37:48 +0800 (GMT+08:00)",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v10:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Remove devm_clk_bulk_get_all_enabled API, use devm_clk_bulk_get_all
and clk_bulk_prepare_enable. Add resource release codes and add
eic7700_pcie_host_deinit API.
... | null | null | null | [PATCH v10 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Thu, Feb 26, 2026 at 05:37:48PM +0800, zhangsenchuan wrote:
I've just sent the fix:
https://lore.kernel.org/linux-pci/20260226133951.296743-1-mani@kernel.org
You can post your series on top of it. There should be no build dependency, but
there is a functional dependency. So we may put this patch and your series in... | {
"author": "Manivannan Sadhasivam <mani@kernel.org>",
"date": "Thu, 26 Feb 2026 19:16:13 +0530",
"is_openbsd": false,
"thread_id": "7dcea145.3a7f.19c9ed63012.Coremail.zhangsenchuan@eswincomputing.com.mbox.gz"
} |
lkml_critique | linux-pci | During PCIe native AER error recovery, ERR_FATAL status bits are not cleared
after fatal error handling. This causes stale ERR_FATAL bits to be reported
in subsequent AER events, even after reporting "device recovery successful".
Prior to commit bdb5ac85777d ("PCI/ERR: Handle fatal error recovery"), native
AER handled... | null | null | null | [PATCH] PCI/ERR: Clear fatal status of the reporting device | [+cc others interested in error handling]
On Fri, Feb 27, 2026 at 06:25:05PM +0800, Sizhe Liu wrote: | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 10:31:18 -0600",
"is_openbsd": false,
"thread_id": "20260227163118.GA3897131@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
This series adds checks mandated by the PCIe spec before raising MSI and MSI-X
from the DWC EP driver.
Note: I've compiled tested this series only. It'd be good if someone with EP
hardware can test it and report back.
- Mani
Manivannan Sadhasivam (2):
PCI: dwc: ep: Add MSI Enable checks before raising MSI to ... | null | null | null | [PATCH 0/2] PCI: dwc: ep: MSI/MSI-X checks | PCIe spec r7, sec 7.7.1.2 mandates that a Function should raise MSI only if
the MSI Enable bit is set and MSI-X enable bit is clear.
Hence, add those checks to be spec compliant with relevant helpers to avoid
code duplication.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Manivannan Sadhasivam <mani... | {
"author": "Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>",
"date": "Wed, 25 Feb 2026 21:53:58 +0530",
"is_openbsd": false,
"thread_id": "aaFuVOxHvKs9Mseu@ryzen.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
This series adds checks mandated by the PCIe spec before raising MSI and MSI-X
from the DWC EP driver.
Note: I've compiled tested this series only. It'd be good if someone with EP
hardware can test it and report back.
- Mani
Manivannan Sadhasivam (2):
PCI: dwc: ep: Add MSI Enable checks before raising MSI to ... | null | null | null | [PATCH 0/2] PCI: dwc: ep: MSI/MSI-X checks | PCIe spec r7, sec 7.7.2.2 mandates that a Function should raise MSI-X only
if the MSI-X Enable bit is set and MSI enable bit is clear.
Hence, add those checks to be spec compliant.
Suggested-by: Bjorn Helgaas <helgaas@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
---
drive... | {
"author": "Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>",
"date": "Wed, 25 Feb 2026 21:53:59 +0530",
"is_openbsd": false,
"thread_id": "aaFuVOxHvKs9Mseu@ryzen.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
This series adds checks mandated by the PCIe spec before raising MSI and MSI-X
from the DWC EP driver.
Note: I've compiled tested this series only. It'd be good if someone with EP
hardware can test it and report back.
- Mani
Manivannan Sadhasivam (2):
PCI: dwc: ep: Add MSI Enable checks before raising MSI to ... | null | null | null | [PATCH 0/2] PCI: dwc: ep: MSI/MSI-X checks | On Wed, Feb 25, 2026 at 09:53:58PM +0530, Manivannan Sadhasivam wrote:
Since you are doing a readw, I think it looks a bit weird that val
is u32 instead of u16.
Since you are doing a readw, I think it looks a bit weird that val
is u32 instead of u16.
Since you are touching these lines, I think you should change ... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 27 Feb 2026 11:12:27 +0100",
"is_openbsd": false,
"thread_id": "aaFuVOxHvKs9Mseu@ryzen.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
This series adds checks mandated by the PCIe spec before raising MSI and MSI-X
from the DWC EP driver.
Note: I've compiled tested this series only. It'd be good if someone with EP
hardware can test it and report back.
- Mani
Manivannan Sadhasivam (2):
PCI: dwc: ep: Add MSI Enable checks before raising MSI to ... | null | null | null | [PATCH 0/2] PCI: dwc: ep: MSI/MSI-X checks | On Wed, Feb 25, 2026 at 09:53:59PM +0530, Manivannan Sadhasivam wrote:
Same comment as patch 1/2.
Kind regards,
Niklas | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Fri, 27 Feb 2026 11:13:40 +0100",
"is_openbsd": false,
"thread_id": "aaFuVOxHvKs9Mseu@ryzen.mbox.gz"
} |
lkml_critique | linux-pci | fb82437fdd8c ("PCI: Change capability register offsets to hex") incorrectly
converted the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value from decimal 52 to hex
0x32:
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link ... | null | null | null | [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value | Hello,
[...]
Looks good!
Reviewed-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Thank you!
Krzysztof | {
"author": "Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= <kwilczynski@kernel.org>",
"date": "Fri, 27 Feb 2026 22:04:58 +0900",
"is_openbsd": false,
"thread_id": "20260227164722.GA3897909@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | fb82437fdd8c ("PCI: Change capability register offsets to hex") incorrectly
converted the PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value from decimal 52 to hex
0x32:
-#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
+#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 0x32 /* end of v2 EPs w/ link ... | null | null | null | [PATCH] PCI: Correct PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 value | On Fri, Feb 27, 2026 at 06:36:53AM -0600, Bjorn Helgaas wrote:
I applied this to pci/for-linus for v7.0.
Per David, it fixes a VMM issue with PCI capabilities. | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 10:47:22 -0600",
"is_openbsd": false,
"thread_id": "20260227164722.GA3897909@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Fix incorrect reset_control_bulk_deassert() call in the probe error
path. When unwinding from a failed pci_host_probe(), the configuration
resets should be asserted to restore the hardware to its initial state,
not deasserted again.
Fixes: 7ef502fb35b2 ("PCI: Add Renesas RZ/G3S host controller driver")
Reviewed-by: Cl... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:21 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Reorder the reset assertion sequence during suspend from
power_resets -> cfg_resets to cfg_resets -> power_resets.
This change ensures the suspend sequence follows the reverse order
of the probe/init sequence, where power_resets are deasserted first
followed by cfg_resets.
Additionally, this ordering is required for R... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:22 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | The existing inbound window configuration algorithm has two issues that
prevent proper operation on RZ/G3E:
1. Over-mapping: Using roundup_pow_of_two() on the remaining region size
can result in windows that extend beyond the intended memory region.
2. Alignment violation: Addresses are only aligned to 4K regardle... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:23 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Add necessary clocks and reset entries for the PCIe controller
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v7:
- Reused standard clock/reset definition macros
v6: No changes
v5: No changes
v4: No changes
v3:
- Collected Rb tag
... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:24 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Fix a typo in interrupt-names: "ser_cor" should be "serr_cor" (System
Error Correctable).
Also convert interrupt-names, clock-names, and reset-names properties
from "description" to "const" to enable proper validation with
dtbs_check.
Fixes: e7534e790557 ("dt-bindings: PCI: Add Renesas RZ/G3S PCIe controller binding"... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:25 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Extend the existing device tree bindings for Renesas RZ/G3S PCIe
controller to include support for the RZ/G3E (renesas,r9a09g047e57-pcie) PCIe
controller. The RZ/G3E PCIe controller is similar to RZ/G3S but has some key
differences:
- Uses a different device ID
- Supports PCIe Gen3 (8.0 GT/s) link speeds
- Uses a d... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:26 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | In preparation for adding RZ/G3E support, move the RST_RSM_B register
offset and mask into a SoC-specific data structure. Compared with RZ/G3S,
the RZ/G3E SYSC controls different functionalities for the PCIe controller.
Make SYSC operations conditional on the presence of register offset
information, allowing the drive... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:27 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Some SoC variants such as RZ/G3E handle configuration reset
control through PCIe AXI registers instead of dedicated reset
lines. Make cfg_resets optional by using
devm_reset_control_bulk_get_optional_exclusive() to allow
SoCs to use alternative or complementary reset control mechanisms.
Reviewed-by: Claudiu Beznea <cl... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:28 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Add optional cfg_pre_init, cfg_post_init, and cfg_deinit callbacks
to handle SoC-specific configuration methods. While RZ/G3S uses the Linux
reset framework with dedicated reset lines, other SoC variants like RZ/G3E
control configuration resets through PCIe AXI registers.
As Linux reset bulk API gracefully handles opt... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:29 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Program the class code register explicitly during PCIe configuration
initialization. RZ/G3E requires this register to be set, while RZ/G3S
has these values as hardware defaults.
This configuration is harmless for RZ/G3S where these match the hardware
defaults, and necessary for RZ/G3E to properly identify the device a... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:30 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Extend the link speed configuration to support Gen3 (8.0 GT/s) in
additionvto Gen2 (5.0 GT/s). This is required for RZ/G3E PCIe host
support, which is Gen3 capable.
Instead of relying on DT max-link-speed for configuration, read the
hardware capabilities from the PCI_EXP_LNKCAP register to determine the
maximumvsuppor... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:31 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Add support for the PCIe controller found in RZ/G3E SoCs to the existing
RZ/G3S PCIe host driver. The RZ/G3E PCIe controller is similar to the
RZ/G3S's, with the following key differences:
- Supports PCIe Gen3 (8.0 GT/s) link speeds alongside Gen2 (5.0 GT/s)
- Uses a different reset control mechanism via AXI registe... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:32 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | The RZ/G3E SoC family features an x2 PCIe IP. Add the PCIe node.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v7: No changes
v6: No changes
v5: No changes
v4: No changes
v3: No changes
v2: Roerder interrupts and interrupt names to match binding
arch/arm64/boot/dts/renesas/r9a09g047.dtsi ... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:33 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | The RZ/G3E SMARC SoM has a fixed 100 MHz reference clock generator
for PCIe. Model it as a fixed-clock and assign it to the PCIe port.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v7: No changes
v6: No changes
v5: No changes
v4: No changes
v3: No changes
v2: No changes
arch/arm64/boot/dt... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:34 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | The RZ Smarc Crarrier-II board has PCIe slots mounted on it.
Enable PCIe support.
Signed-off-by: John Madieu <john.madieu.xa@bp.renesas.com>
---
Changes:
v7: No changes
v6: No changes
v5: No changes
v4: No changes
v3:
- Splitted enablement into common carrier dtsi and board dts
v2:
- Removed board-specific dma-r... | {
"author": "John Madieu <john.madieu.xa@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 16:32:35 +0100",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with
the existing RZ/G3S PCIe controller, but with several key differences.
This series adds support for the RZ/G3E PCIe controller by extending the existing
RZ/G3S driver and device tree bindings.
Key differences between RZ/G3E and RZ/G3S PCIe... | null | null | null | [PATCH v7 00/15] PCI: renesas: Add RZ/G3E PCIe controller support | Hi John,
If there is any new version of the series, please put a comment
+#define RZG3S_PCI_RESET 0x310 # Only for RZ/G3E
Cheers,
Biju | {
"author": "Biju Das <biju.das.jz@bp.renesas.com>",
"date": "Fri, 27 Feb 2026 15:41:43 +0000",
"is_openbsd": false,
"thread_id": "20260227153236.55988-11-john.madieu.xa@bp.renesas.com.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | The DONE_INT_MASK and ABORT_INT_MASK registers are shared by all DMA
channels, and modifying them requires a read-modify-write sequence.
Because this operation is not atomic, concurrent calls to
dw_edma_v0_core_start() can introduce race conditions if two channels
update these registers simultaneously.
Add a spinlock ... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:21 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | The control field in a DMA link list entry must be updated as the final
step because it includes the CB bit, which indicates whether the entry is
ready. Add dma_wmb() to ensure the correct memory write ordering.
Currently the driver does not update DMA link entries while the DMA is
running, so no visible failure occur... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:22 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | Reusing ll_region.sz as the transfer size is misleading because
ll_region.sz represents the memory size of the EDMA link list, not the
amount of data to be transferred.
Add a new xfer_sz field to explicitly indicate the total transfer size
of a chunk.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/dw-edm... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:23 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | dw_edma_channel_setup() calculates ll_max based on the size of the
ll_region, but the value is later overwritten with -1, preventing the
code from ever reaching the calculated ll_max.
Typically ll_max is around 170 for a 4 KB page and four DMA R/W channels.
It is uncommon for a single DMA request to reach this limit, ... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:24 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | ll_region is identical for all chunks belonging to the same DMA channel,
so there is no need to copy it into each chunk. Move ll_region to
struct dw_edma_chan to avoid redundant copies.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/dw-edma/dw-edma-core.c | 14 ++++----------
drivers/dma/dw-edma/dw-edm... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:25 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | Some helper functions do not use any information from dw_edma_chunk, so
passing a dw_edma_chan pointer directly avoids an unnecessary level of
pointer dereferencing and simplifies data access.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/dw-edma/dw-edma-v0-core.c | 22 ++++++++++------------
drivers/dma... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:26 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | Move the channel-enable logic into a new helper function,
dw_(edma|hdma)_v0_core_ch_enable(), in preparation for supporting dynamic
link entry additions.
No functional changes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/dma/dw-edma/dw-edma-v0-core.c | 128 +++++++++++++++++-----------------
drivers/dma/d... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:27 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | Introduce four new callbacks to fill link list entries in preparation for
replacing dw_(edma|hdma)_v0_core_start().
Filling link list entries is expected to become more complex, and without
this abstraction both eDMA and HDMA paths would need to duplicate the same
logic. Add fill-entry callbacks so the code can be sha... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:28 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | Use common dw_edma_core_start() for both eDMA and HDMA. Remove .start()
callback functions at eDMA and HDMA.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
change in v2
- use eDMA and HDMA
---
drivers/dma/dw-edma/dw-edma-core.c | 24 ++++++++++++++++--
drivers/dma/dw-edma/dw-edma-core.h | 7 -----
drivers/dma/... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:29 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | The current descriptor layout is:
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
Creating a DMA descriptor requires at least three kzalloc() calls because
each burst is allocated as a linked-list node. Since the number of bursts
is already known when the descriptor is created, a linked list is not... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:30 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | The current descriptor layout is:
struct dw_edma_desc *desc
└─ chunk list
└─ burst[]
Creating a DMA descriptor requires at least two kzalloc() calls because
each chunk is allocated as a linked-list node. Since the number of bursts
is already known when the descriptor is created, this linked-list layer is... | {
"author": "Frank Li <Frank.Li@nxp.com>",
"date": "Fri, 09 Jan 2026 10:28:31 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | Hello Frank,
Thanks for doing this work!
Sorry for pointing out a lot of typos here.
However, I do think it gives a better impression if there are fewer typos.
On Fri, Jan 09, 2026 at 10:28:20AM -0500, Frank Li wrote:
Subject: dmaengine: dw-edma: flatten desc structions and simple code
s/structions/structures/
s/... | {
"author": "Niklas Cassel <cassel@kernel.org>",
"date": "Mon, 12 Jan 2026 14:07:38 +0100",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Fri, Jan 09, 2026 at 10:28:21AM -0500, Frank Li wrote:
Hi Frank,
I'm very interested in seeing the work toward the "dynamic append" series land,
but in my opinion this one can be submitted independently.
Even in the current mainline, under concurrent multi-channel load, this race can
already be triggered.
Also, ... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Wed, 25 Feb 2026 17:26:02 +0900",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Fri, Jan 09, 2026 at 10:28:24AM -0500, Frank Li wrote:
Just curious: wasn't this to reserve one slot for the final link element?
Best regards,
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Wed, 25 Feb 2026 17:30:33 +0900",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Wed, Feb 25, 2026 at 05:30:33PM +0900, Koichiro Den wrote:
when calculate avaible entry, always use chan-ll_max -1. ll_max indicate
memory size, final link element actually occupted a space.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 10:43:32 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Wed, Feb 25, 2026 at 05:26:02PM +0900, Koichiro Den wrote:
This patch serial is actually straight forwards. we can ask vnod pick first
one in case have other problems. put together to reduce patch's dependency.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Wed, 25 Feb 2026 10:50:41 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Wed, Feb 25, 2026 at 10:43:32AM -0500, Frank Li wrote:
After the entire series is applied (esp. [PATCH v2 10/11] + [PATCH v2 11/11]),
yes, that makes sense to me. My concern was that before the semantics of
"ll_max" changes, this "-1" was required. In other words, this seemed to me not
a fix but a preparatory patch... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 26 Feb 2026 11:16:26 +0900",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Wed, Feb 25, 2026 at 10:50:41AM -0500, Frank Li wrote:
Yes, I see.
My understanding is that the originally planned dependency chain was:
#1->#2->#3
#1 [PATCH v2 0/8] dmaengine: Add new API to combine onfiguration and descriptor preparation
https://lore.kernel.org/dmaengine/20251218-dma_prep_config-v2-0-c070... | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Thu, 26 Feb 2026 11:22:41 +0900",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Thu, Feb 26, 2026 at 11:16:26AM +0900, Koichiro Den wrote:
Thanks, I found I make mistake, wrong think it as "chan->ll_max = -1".
I will squash this change to patch 10.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 26 Feb 2026 10:21:28 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Thu, Feb 26, 2026 at 11:22:41AM +0900, Koichiro Den wrote:
Vnod said he will review #1 in this week. If not progress, I will create
new one without dependent #1.
Frank | {
"author": "Frank Li <Frank.li@nxp.com>",
"date": "Thu, 26 Feb 2026 10:23:27 -0500",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Thu, Feb 26, 2026 at 10:23:27AM -0500, Frank Li wrote:
Thanks for letting me know that.
Best regards,
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Fri, 27 Feb 2026 15:29:47 +0900",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | This patch week depend on the below serise.
https://lore.kernel.org/imx/20251208-dma_prep_config-v1-0-53490c5e1e2a@nxp.com/
Basic change
struct dw_edma_desc *desc
└─ chunk list
└─ burst list
To
struct dw_edma_desc *desc
└─ burst[n]
And reduce at least 2 times kzalloc() for each dma d... | null | null | null | [PATCH v2 00/11] dmaengine: dw-edma: flatten desc structions and
simple code | On Thu, Feb 26, 2026 at 10:21:28AM -0500, Frank Li wrote:
Thanks for the confirmation. I agree with the idea of squashing.
Best regards,
Koichiro | {
"author": "Koichiro Den <den@valinux.co.jp>",
"date": "Fri, 27 Feb 2026 15:30:50 +0900",
"is_openbsd": false,
"thread_id": "2t6tu7g2jh6tfavrfxkqx5yvd5kq5p3u3bamtjc3awjc7g46vj@cistlknk5qe2.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | On 2/20/26 12:52 PM, Vidya Sagar wrote:
The "Unmask SBR" bit is a toggle bit. It does not give indicator whether the device is capable of SBR or not. The original thought was that if the user is issuing CXL SBR, you know what you are doing and the kernel will set that bit and issue the SBR.
DJ | {
"author": "Dave Jiang <dave.jiang@intel.com>",
"date": "Fri, 20 Feb 2026 14:21:27 -0700",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | On 21/02/26 02:51, Dave Jiang wrote:
Not sure how is this point relevant here. Can you help me understand?
BTW, what do you mean by "whether the device is capable of SBR or not". My understanding is that each downstream port
must support SBR. The patch I made would ensure that 'bus' entry is not shown under 'r... | {
"author": "Vidya Sagar <vidyas@nvidia.com>",
"date": "Mon, 23 Feb 2026 13:11:54 +0000",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | On 2/23/26 6:11 AM, Vidya Sagar wrote:
That means it's not a capability bit. It's a r/w toggle bit to mask or unmask SBR for CXL.
The purpose of introducing the cxl bus reset method is, "you know what you are doing" because you selected this method and the kernel will set the bit to allow the reset. By default the U... | {
"author": "Dave Jiang <dave.jiang@intel.com>",
"date": "Mon, 23 Feb 2026 08:52:29 -0700",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | On 23/02/26 21:22, Dave Jiang wrote:
I'm not really questioning the purpose of 'cxl_bus' reset method.
I'm only wondering why is 'bus' reset method shown if it can't be used.
This doesn't make much sense to me. Since the 'cxl_bus' method is anyway going to update the 'Unmask SBR' before applying the SBR through Brid... | {
"author": "Vidya Sagar <vidyas@nvidia.com>",
"date": "Wed, 25 Feb 2026 13:13:30 +0000",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | {
"author": "Vidya Sagar <vidyas@nvidia.com>",
"date": "Wed, 25 Feb 2026 19:08:01 +0530",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | On 2/25/26 6:13 AM, Vidya Sagar wrote:
Ok I think I see where I made a mistake. You are hiding the regular PCI bus reset method and not the cxl_bus reset method. Yes then I agree what you are doing is fine. This does not impact the cxl_bus reset method. Sorry about the noise.
DJ | {
"author": "Dave Jiang <dave.jiang@intel.com>",
"date": "Wed, 25 Feb 2026 09:09:06 -0700",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | The CXL specification (e.g., CXL r3.1 v1.0, sec 8.1.5.2) defines
the "Unmask SBR" bit in the Port Control Extensions Register.
When this bit is 0 (default), asserting the Secondary Bus Reset (SBR) bit
in the Bridge Control register has no effect on the downstream bus.
Currently, the Linux PCI core checks this conditio... | null | null | null | [PATCH V1] PCI: Hide SBR from reset_methods if masked by CXL | On Wed, 25 Feb 2026 09:34:00 -0700
Dave Jiang <dave.jiang@intel.com> wrote:
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Fri, 27 Feb 2026 13:34:12 +0000",
"is_openbsd": false,
"thread_id": "20260227133412.0000139a@huawei.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | Miscellaneous fixes for pci subsystem
Changes in v4:
- Remove the architecture-specific #ifdef to apply the alignment
check for all platforms (including x86), as device registers are
naturally aligned anyway.
- Fix a potential issue in proc_bus_pci_read() to make it consistent
with proc_bus_pci_write(), as sugge... | {
"author": "Ziming Du <duziming2@huawei.com>",
"date": "Fri, 16 Jan 2026 16:17:17 +0800",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | proc_bus_pci_read() assigns *ppos directly to an unsigned integer variable.
For large offsets, this implicit conversion may truncate the value and
cause reads from an incorrect position.
proc_bus_pci_write() explicitly validates *ppos and rejects values larger
than INT_MAX, while proc_bus_pci_read() currently accepts ... | {
"author": "Ziming Du <duziming2@huawei.com>",
"date": "Fri, 16 Jan 2026 16:17:21 +0800",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | Unaligned access is harmful for non-x86 archs such as arm64. When we
use pwrite or pread to access the I/O port resources with unaligned
offset, system will crash as follows:
Unable to handle kernel paging request at virtual address fffffbfffe8010c1
Internal error: Oops: 0000000096000061 [#1] SMP
Call trace:
_outw in... | {
"author": "Ziming Du <duziming2@huawei.com>",
"date": "Fri, 16 Jan 2026 16:17:18 +0800",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | During the concurrent process of creating and rescanning in VF, the
resource files for the same pci_dev may be created twice. The second
creation attempt fails, resulting the res_attr in pci_dev to kfree(),
but the pointer is not set to NULL. This will subsequently lead to
dereferencing a null pointer when removing the... | {
"author": "Ziming Du <duziming2@huawei.com>",
"date": "Fri, 16 Jan 2026 16:17:19 +0800",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | Hi all,
Gentle ping on this patchset. Any feedback would be greatly appreciated.
On 2026/1/15 15:52, Ziming Du wrote:
Thanx du! | {
"author": "duziming <duziming2@huawei.com>",
"date": "Fri, 30 Jan 2026 15:53:10 +0800",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | On Fri, Jan 30, 2026 at 03:53:10PM +0800, duziming wrote:
Sorry I didn't get to this. Poke again after v6.20-rc1. | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 6 Feb 2026 16:29:23 -0600",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | On Fri, Jan 16, 2026 at 04:17:18PM +0800, Ziming Du wrote:
I assume "IS_ALIGNED(port, 1)" is *always* true, so can we just do
this once before the switch instead of adding it to the "case 2" and
"case 4"? | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Thu, 26 Feb 2026 11:00:50 -0600",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | On Fri, Jan 16, 2026 at 04:17:19PM +0800, Ziming Du wrote:
Where are the two resource file creations? This will help review the
patch.
I think it would be more informative to include an actual sample here.
We can easily substitute the device names and numbers, given a
concrete example. It's a little bit harder to ... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Thu, 26 Feb 2026 11:14:03 -0600",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Yongqiang Liu <liuyongqiang13@huawei.com>
When the value of *ppos over the INT_MAX, the pos is over set to a
negative value which will be passed to get_user() or
pci_user_write_config_dword(). Unexpected behavior such as a soft lockup
will happen as follows:
watchdog: BUG: soft lockup - CPU#0 stuck for 130s! [... | null | null | null | [PATCH v4 3/4] PCI: Prevent overflow in proc_bus_pci_write() | 在 2026/2/27 1:14, Bjorn Helgaas 写道:
The process of creating VFs:
sriov_numvfs_store
hinic_pci_sriov_configure
hinic_pci_sriov_enable
pci_enable_sriov
sriov_enable
sriov_add_vfs
pci_iov_add_virtfn
pci... | {
"author": "duziming <duziming2@huawei.com>",
"date": "Fri, 27 Feb 2026 10:30:50 +0800",
"is_openbsd": false,
"thread_id": "20260226170050.GA3812835@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Dragan Simic already had warned me of potential issues with 5.0 GT/s
speed operation in Rockchip PCIe. However, in recent interactions
with Shawn Lin from Rockchip it came to my attention there's grave
danger in the unknown errata regarding 5.0 GT/s operational speed
of their PCIe core.
Drop all code related to 5.0 GT... | null | null | null | [PATCH v4 0/4] PCI: rockchip: 5.0 GT/s speed discouraged by Rockchip | Hello Geraldo,
On Friday, February 27, 2026 06:36 CET, Geraldo Nascimento <geraldogabriel@gmail.com> wrote:
I'm quite surprised to see what happened here in the v4? The changes
introduced in this diff block in the v3 were perfectly fine, i.e. we need
to correct any runtime occurrences of Gen2 speed setting in the ro... | {
"author": "\"Dragan Simic\" <dsimic@manjaro.org>",
"date": "Fri, 27 Feb 2026 18:33:34 +0100",
"is_openbsd": false,
"thread_id": "92662fce5ebb28d21d0c68631a23ab8afb815a90.1772169998.git.geraldogabriel@gmail.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v11:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Add ".data = &eic7700_data" and ".pme_turn_off" callback, set
skip_l23_ready in eic7700_pcie_pme_turn_off API, because the EIC7700
SoC lacks hardware support for th... | null | null | null | [PATCH v11 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Add Device Tree binding documentation for the Eswin EIC7700 PCIe
controller module, the PCIe controller enables the core to correctly
initialize and manage the PCIe bus and connected devices.
Signed-off-by: Yu Ning <ningyu@eswincomputing.com>
Signed-off-by: Yang... | {
"author": "zhangsenchuan@eswincomputing.com",
"date": "Fri, 27 Feb 2026 19:17:32 +0800",
"is_openbsd": false,
"thread_id": "20260227171554.GA3898780@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v11:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Add ".data = &eic7700_data" and ".pme_turn_off" callback, set
skip_l23_ready in eic7700_pcie_pme_turn_off API, because the EIC7700
SoC lacks hardware support for th... | null | null | null | [PATCH v11 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Add driver for the Eswin EIC7700 PCIe host controller, which is based on
the DesignWare PCIe core, IP revision 5.96a. The PCIe Gen.3 controller
supports a data rate of 8 GT/s and 4 channels, support INTx and MSI
interrupts.
Signed-off-by: Yu Ning <ningyu@eswinco... | {
"author": "zhangsenchuan@eswincomputing.com",
"date": "Fri, 27 Feb 2026 19:18:08 +0800",
"is_openbsd": false,
"thread_id": "20260227171554.GA3898780@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
Changes in v11:
- Updates: eswin,eic7700-pcie.yaml
- None
- Updates: pcie-eic7700.c
- Add ".data = &eic7700_data" and ".pme_turn_off" callback, set
skip_l23_ready in eic7700_pcie_pme_turn_off API, because the EIC7700
SoC lacks hardware support for th... | null | null | null | [PATCH v11 0/2] Add driver support for Eswin EIC7700 SoC PCIe controller | On Fri, Feb 27, 2026 at 07:18:08PM +0800, zhangsenchuan@eswincomputing.com wrote:
Does "4 channels" mean "4 lanes", i.e., what we typically call a "x4
link"? | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 11:15:54 -0600",
"is_openbsd": false,
"thread_id": "20260227171554.GA3898780@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | Currently igc driver calls pci_set_power_state() and pci_restore_state()
and the like to bring the device back from low power states. However,
PCI core handles all this on behalf of the driver. Furthermore with PTM
enabled the PCI core re-enables it on resume but the driver calls
pci_restore_state() which ends up disab... | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Tue, 24 Feb 2026 12:10:41 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | When runtime resuming igc we get:
[ 516.161666] RTNL: assertion failed at ./include/net/netdev_lock.h (72)
Happens because commit 310ae9eb2617 ("net: designate queue -> napi
linking as "ops protected"") added check for this. For this reason drop
the special case for runtime PM from __igc_resume(). This makes it ta... | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Tue, 24 Feb 2026 12:10:40 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | Hi all,
There is (still) an issue with Linux PCIe PTM enabling that happens because
Linux automatically enables PTM if certain capabilities are set. However,
turns out this is not enough because once we enumerate PCIe Switch Upstream
port we also enable PTM but the Downstream Ports are not yet enumerated.
This trigger... | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Tue, 24 Feb 2026 12:10:39 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | This is not used by any of the existing callers so we can simplify the
function slightly and get rid of that.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
---
drivers/net/ethernet/intel/ice/ice_main.c | 2 +-
drivers/net/ethernet/int... | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Tue, 24 Feb 2026 12:10:43 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | Currently we enable PTM automatically for Root and Switch Upstream Ports
if the advertised capabilities support the relevant role. However, there
are few issues with this. First of all if there is no Endpoint that
actually needs the PTM functionality, this is just wasting link
bandwidth. There are just a couple of driv... | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Tue, 24 Feb 2026 12:10:44 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On Tue, Feb 24, 2026 at 12:10:41PM +0100, Mika Westerberg wrote:
I love it, thanks a lot for doing this!
Do we still need the pci_enable_device_mem() and pci_set_master()
in __igc_resume()?
I suppose some of that is related to the pci_disable_device() in the
suspend path (__igc_shutdown()), but there are only a few ... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Tue, 24 Feb 2026 10:58:37 -0600",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On Tue, Feb 24, 2026 at 12:10:39PM +0100, Mika Westerberg wrote:
These last two don't look dependent on the igc patches, so I applied
them to pci/ptm for v7.1, thanks!
Let me know if there is some dependency and I can ack them and drop
them from the PCI tree. | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Tue, 24 Feb 2026 11:13:08 -0600",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | Mika Westerberg <mika.westerberg@linux.intel.com> writes:
Typo in the commit subject: rntl -> rtnl
I think it's worth fixing, anyway:
Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Cheers,
--
Vinicius | {
"author": "Vinicius Costa Gomes <vinicius.gomes@intel.com>",
"date": "Tue, 24 Feb 2026 13:07:45 -0800",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | Mika Westerberg <mika.westerberg@linux.intel.com> writes:
Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com>
Cheers,
--
Vinicius | {
"author": "Vinicius Costa Gomes <vinicius.gomes@intel.com>",
"date": "Tue, 24 Feb 2026 13:08:25 -0800",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On 2/24/2026 3:10 AM, Mika Westerberg wrote:
Presumably, if a driver ever actually needs this ptm_granularity in the
future, they can just read it from the device, or we can add a helper to
access if needed. Makes sense.
Thanks,
Jake | {
"author": "Jacob Keller <jacob.e.keller@intel.com>",
"date": "Tue, 24 Feb 2026 14:26:42 -0800",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
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