data_type large_stringclasses 3
values | source large_stringclasses 29
values | code large_stringlengths 98 49.4M | filepath large_stringlengths 5 161 ⌀ | message large_stringclasses 234
values | commit large_stringclasses 234
values | subject large_stringclasses 418
values | critique large_stringlengths 101 1.26M ⌀ | metadata dict |
|---|---|---|---|---|---|---|---|---|
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On 2/24/2026 3:10 AM, Mika Westerberg wrote:
I'm not one of the main developers for igc, but everything here looks
good to me.
Reviewed-by: Jacob Keller <jacob.e.keller@intel.com> | {
"author": "Jacob Keller <jacob.e.keller@intel.com>",
"date": "Tue, 24 Feb 2026 14:28:56 -0800",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On Tue, Feb 24, 2026 at 10:58:37AM -0600, Bjorn Helgaas wrote:
I think they are just as you describe due the fact there are explicit
pci_disable_device() calls. Probably we can get rid of them as well but
that requires careful testing that nothing accidentally breaks.
@Vitaly, what do you think? I can take a look. | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Wed, 25 Feb 2026 13:26:19 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On Tue, Feb 24, 2026 at 11:13:08AM -0600, Bjorn Helgaas wrote:
Thanks!
They can be separate. No dependency. Just wanted to "ship" them together
due the fact that all of them are needed to get rid of the errors. | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Wed, 25 Feb 2026 13:27:59 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | On Wed, Feb 25, 2026 at 01:26:19PM +0100, Mika Westerberg wrote:
Sorry @Vitaly and @Vinicius I meant :) | {
"author": "Mika Westerberg <mika.westerberg@linux.intel.com>",
"date": "Wed, 25 Feb 2026 13:28:55 +0100",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | Commit c01163dbd1b8 ("PCI/PM: Always disable PTM for all devices during
suspend") made the PCI core to suspend (disable) PTM before driver
suspend hooks are called. In case of igc what happens is that on suspend
path PCI core calls pci_suspend_ptm() then igc suspend hook that calls
igc_down() that ends up calling igc_p... | null | null | null | [PATCH 3/5] igc: Don't reset the hardware on suspend path | Mika Westerberg <mika.westerberg@linux.intel.com> writes:
This series is solving real problems (thank you btw), I think the
pci_disable_device() one would be better as a separate series.
Cheers,
--
Vinicius | {
"author": "Vinicius Costa Gomes <vinicius.gomes@intel.com>",
"date": "Wed, 25 Feb 2026 15:56:44 -0800",
"is_openbsd": false,
"thread_id": "20260226111224.GL2275908@black.igk.intel.com.mbox.gz"
} |
lkml_critique | linux-pci | The code was originally written using no_64bit_msi, which restricts the
device to 32-bit MSI addresses.
Since msi_addr_mask is introduced, use DMA_BIT_MASK(dma_bits) instead of
DMA_BIT_MASK(32) here for msi_addr_mask, describing the restriction more
precisely and allowing these devices to work on platforms with MSI
do... | null | null | null | [PATCH v4 3/4] drm/radeon: Raise msi_addr_mask to dma_bits | On Fri, Feb 27, 2026 at 01:25:03PM +0800, Vivian Wang wrote:
We needed testing on powerpc and sparc, which has now been done,
thanks to Han Gao (SPARC Enterprise T5220), Nathaniel Roach (SPARC
T5-2), and Venkat Rao Bagalkote (IBM Power System LPAR (pseries)).
It would be ideal to have acks from the powerpc and sparc ... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 10:49:19 -0600",
"is_openbsd": false,
"thread_id": "20260227164919.GA3897300@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On Wed, Feb 25, 2026 at 09:08:15AM -0600, Ramesh Errabolu wrote:
This patch sounds like a hack to me. AFAIK, "udevadm trigger"
performs exactly that.
Thanks | {
"author": "Leon Romanovsky <leon@kernel.org>",
"date": "Thu, 26 Feb 2026 10:34:27 +0200",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On 2/26/2026 2:34 AM, Leon Romanovsky wrote:
AFAIK, PCI slots do not yet raise a uevent. Secondly there is no uevent
attribute in slot-id directory to submit requests to raise a uevent.
This patch fills that gap | {
"author": "Ramesh Errabolu <ramesh@linux.ibm.com>",
"date": "Thu, 26 Feb 2026 11:53:32 -0600",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On Thu, Feb 26, 2026 at 11:53:32AM -0600, Ramesh Errabolu wrote:
Right
Please start from the beginning and explain what you mean by 'the gap'.
Which scenario failed before and began working after this patch? From your
description, it sounds like the behavior should already be covered by the
'udevadm trigger' command... | {
"author": "Leon Romanovsky <leon@kernel.org>",
"date": "Thu, 26 Feb 2026 20:39:45 +0200",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On 2/26/2026 12:39 PM, Leon Romanovsky wrote:
PCI slots are surfaced early in the boot process before udev daemon is
able to run and process these uevents. As a consequence any uevents
raised by PCI slots are lost. To apply the relevant udev rules, we need
to raise PCI slot uevents a second time. This cannot happen ... | {
"author": "Ramesh Errabolu <ramesh@linux.ibm.com>",
"date": "Thu, 26 Feb 2026 13:31:07 -0600",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On Thu, Feb 26, 2026 at 01:31:07PM -0600, Ramesh Errabolu wrote:
I don't understand what you are saying. In previous email, we both
agreed that PCI slots doesn't have uevents and here you are again
repeating that these uevents are lost.
On my system:
➜ ~ ls /sys/bus/pci/slots/
0 12 14 8
➜ ~ ls /sys/bus/pci/slots... | {
"author": "Leon Romanovsky <leon@kernel.org>",
"date": "Thu, 26 Feb 2026 21:51:53 +0200",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On 2/26/2026 1:51 PM, Leon Romanovsky wrote:
Thanks for taking time to review. Will use your example to elaborate.
Will reference slot 3
Requirement:
- Be able to define a udev rule to match a PCI slot uevent
- Enable or Disable a PCI device
Before:
- PCI slot 3 raises a uevent during boot
- This ueve... | {
"author": "Ramesh Errabolu <ramesh@linux.ibm.com>",
"date": "Thu, 26 Feb 2026 14:33:48 -0600",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Add a new write-only 'uevent' attribute to PCI slot sysfs
entries. This provides a mechanism for userspace to explicitly
synthesize PCI slot uevents when needed.
For cold-plugged PCI devices, slots may be created before
udev is ready to receive events, causing the initial 'add'
uevents to be missed. As a result, slot ... | null | null | null | [PATCH v1] PCI: Add write-only 'uevent' sysfs attribute for PCI slots | On 2/26/2026 7:39 PM, Leon Romanovsky wrote:
That is only partially true. PCI slots are represented in sysfs by a
kobject (pci_slot.kobj) and pci_hotplug_core generates uevents for these
kobjects during pci_hp_add() [1].
Here is an example for these uevents:
KERNEL[62021.190266] add /bus/pci/slots/000018d0 (slo... | {
"author": "Peter Oberparleiter <oberpar@linux.ibm.com>",
"date": "Fri, 27 Feb 2026 12:23:03 +0100",
"is_openbsd": false,
"thread_id": "5d30ad0a-9c16-4802-adfe-e795c38f5990@linux.ibm.com.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | The TDI interface report is defined in PCIe r7.0,
chapter "11.3.11 DEVICE_INTERFACE_REPORT". The report enumerates
MMIO resources and their properties which will take effect upon
transitioning to the RUN state.
Store the report in pci_tsm.
Define macros and helpers to parse the binary blob.
Signed-off-by: Alexey Kar... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:44 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Define a structure with all info about a TDI such as TDISP status,
bind state, used START_INTERFACE options and the report digest.
This will be extended and shared to the userspace.
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
---
Make it uapi? We might want a sysfs node per a field so probably not.
For now its... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:45 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Prepare for SEV-TIO support as it is going to equal or bigger
than the existing sev_guest.c which is already 700 lines and
keeps growing.
No behavioural change expected.
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
---
drivers/virt/coco/sev-guest/Makefile | 3 ++-
drivers/virt/coco/sev-guest/sev-guest.h | 1... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:46 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | SWIOTLB is enforced when encrypted guest memory is detected
in pci_swiotlb_detect() which is required for legacy devices.
Skip SWIOTLB for TDISP devices.
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
---
include/linux/swiotlb.h | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/include/linux/swiotlb.h ... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:47 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | The DMA subsystem does is forcing private-to-shared
page conversion in force_dma_unencrypted().
Return false from force_dma_unencrypted() for TDISP devices.
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
---
arch/x86/mm/mem_encrypt.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/x8... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:48 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | TDISP devices operate in CoCo VMs only and capable of accessing
encrypted guest memory.
Currently when SME is on, the DMA subsystem forces the SME mask in
DMA handles in phys_to_dma() which assumes IOMMU pass through
which is never the case with CoCoVM running with a TDISP device.
Define X86's version of phys_to_dma(... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:49 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Implement the SEV-TIO (Trusted I/O) support in for AMD SEV-SNP guests.
The implementation includes Device Security Manager (DSM) operations
for:
- binding a PCI function (GHCB extension) to a VM and locking
the device configuration;
- receiving TDI report and configuring MMIO and DMA/sDTE;
- accepting the device into ... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:50 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Once locked, a TDI's MSE and BME are not allowed to be cleared.
Skip INTx test as TEE-capable PCI functions are most likely IOV VFs
anyway and those do not support INTx at all.
Add a quirk preventing the probing code from disabling MSE when
updating 64bit BAR (which cannot be done atomically).
Note that normally thi... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:51 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Add another resource#d_enc to allow mapping MMIO as
an encrypted/private region.
Unlike resourceN_wc, the node is added always as ability to
map MMIO as private depends on negotiation with the TSM which
happens quite late.
Signed-off-by: Alexey Kardashevskiy <aik@amd.com>
---
include/linux/pci.h | 2 +-
drivers... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Wed, 25 Feb 2026 16:37:52 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On February 25, 2026 5:37:50 AM UTC, Alexey Kardashevskiy <aik@amd.com> wrote:
Just from staring at that huuuge diff, those bullets and things above are basically begging to be separate patches...
--
Small device. Typos and formatting crap | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Wed, 25 Feb 2026 06:00:59 +0000",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
[..]
Those should be __le64 and le32, right? But see below for another
option...
So we all have a version of a patch like this and the general style
suggestion I have is to just parse this layout with typical
offsets+bitfield definitions.
This follows the precedent, admittedly tiny, of t... | {
"author": "<dan.j.williams@intel.com>",
"date": "Tue, 24 Feb 2026 22:16:59 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
Say more about what this uapi when sysfs already has lock+accept
indications?
Or are you just talking about exporting the TDISP report as a binary
blob?
I think the kernel probably wants a generic abstraction for asserting
that the tsm layer believes the report remains valid between fetch... | {
"author": "<dan.j.williams@intel.com>",
"date": "Tue, 24 Feb 2026 22:33:58 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On Wed, Feb 25, 2026, at 07:16, dan.j.williams@intel.com wrote:
If these come from DMA transfers from a device, yes.
The structure appears to be allocated with kzalloc, so it is always
aligned to __alignof__(u64) or higher, and it's better to drop the
__packed annotation.
I assume by bitfield you mean the macros a... | {
"author": "\"Arnd Bergmann\" <arnd@arndb.de>",
"date": "Wed, 25 Feb 2026 11:10:49 +0100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
I worry this further muddies the meaning of the swiotlb force option.
What if you want to force swiotlb operation on accepted devices?
For example:
@@ -173,7 +176,13 @@ static inline bool is_swiotlb_force_bounce(struct device *dev)
{
struct io_tlb_mem *mem = dev->dma_io_tlb_mem;
... | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 25 Feb 2026 08:30:00 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 2026-02-25 5:37 am, Alexey Kardashevskiy wrote:
This seems backwards - how does it make sense for arch code to force
SWIOTLB globally on the grounds that all DMA must be to shared memory,
but then generic code override that because it claims to know better?
I'd expect to see something more like:
if (is_cc_plat... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Wed, 25 Feb 2026 16:48:38 +0000",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
Looks ok, but I would not reference "TDISP" here. TDISP is the PCI
"accept" protocol. Other buses might accept devices via other
bus-specific protocols. | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 25 Feb 2026 08:51:08 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 2026-02-25 5:37 am, Alexey Kardashevskiy wrote:
That smells a bit off... In CCA we should be in the same boat, wherein a
trusted device can access memory at a DMA address based on its "normal"
(private) GPA, rather than having to be redirected to the shared alias
(it's really not an "SME mask" in that sense at a... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Wed, 25 Feb 2026 17:08:37 +0000",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 2026-02-25 4:30 pm, dan.j.williams@intel.com wrote:
For that we'd need a whole other private SWIOTLB plus the logic to
decide which one to use in the first place. And if you really wanted an
option to forcibly expose all DMA through shared memory regardless of
TDISP and friends, that would logically want to be a... | {
"author": "Robin Murphy <robin.murphy@arm.com>",
"date": "Wed, 25 Feb 2026 18:00:55 +0000",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Robin Murphy wrote:
In this case I was still considering that swiotlb is still implicitly
only shared address bouncining. Indeed, a whole other "private_swiotlb"
mechanism would be needed for private bouncing. Not clear there is a
need for that at present.
Even for this swiotlb=force for "accepted" devices I only see... | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 25 Feb 2026 12:57:01 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Robin Murphy wrote:
Not quite, no, CCA *is* in the same boat as TDX, not SEV-SNP. Only
SEV-SNP has this concept that the DMA handle for private memory is the
dma_addr_unencrypted() conversion (C-bit masked) of the CPU physical
address. For CCA and TDX the typical expectation of dma_addr_encrypted()
for accepted device... | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 25 Feb 2026 13:35:22 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 25/2/26 17:33, dan.j.williams@intel.com wrote:
I mean that between lock and accept the guest userspace wants to read certs/measurements/report to do the attestation. And it will want to know these blobs digests. And probably the TDI state. Although successful write to lock() is an indication of CONFIG_LOCKED, and a... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 10:42:40 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 25/2/26 17:16, dan.j.williams@intel.com wrote:
Oh yes.
I cannot easily see from these what the sizes are. And how many of each.
My variant is just like this (may be need to put it in the comment):
tdi_report_header
tdi_report_mmio_range[]
tdi_report_footer
imho easier on eyes. I can live with either if the ... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 11:09:11 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 26/2/26 03:48, Robin Murphy wrote:
True. I have the itch to remove SWIOTLB_FORCE from pci_swiotlb_detect(), this may be the other way to go.
device_cc_accepted() implies is_cc_platform.
At the moment it is a property of the device though, for AMD, at least.
True. With vTOM ("everything above TopOfMemory is sha... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 11:09:46 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On Wed, Feb 25, 2026 at 04:37:51PM +1100, Alexey Kardashevskiy wrote:
Disallowed by hardware, by spec, by convention? Spec reference would
be helpful.
"Most likely" doesn't sound like a convincing argument for skipping
something.
Say more about this please. If there's something special about this
device, I'd lik... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Wed, 25 Feb 2026 18:24:59 -0600",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
Locked command register management is handled by QEMU. This patch needs
quite a bit more explanation about what use case it is trying to solve. | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 25 Feb 2026 16:34:10 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
[..]
Same as any other offset+bitmask code, the size is encoded in the accessor.
Arnd caught that I misspoke when I said offset+bitfield.
Does the kernel have any use for the footer besides conveying it to
userspace?
Aneesh also already has 'structs+bitmask', I will switch to that. | {
"author": "<dan.j.williams@intel.com>",
"date": "Wed, 25 Feb 2026 18:34:06 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 25/2/26 17:00, Borislav Petkov wrote:
I struggle to separate these more without making individual patches useless for any purpose, even splitting between maintainership area. People often define things in separate patches and then use them and I dislike such approach for reviewing purposes - hard to follow. I can d... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 14:39:37 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 26/2/26 13:34, dan.j.williams@intel.com wrote:
PCIe says:
Example of such device specific information include:
• A network device may include receive-side scaling (RSS) related information such as the RSS hash and
mappings to the virtual station interface (VSI) queues, etc.
• A NVMe device may include information ... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 14:49:33 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 26/2/26 11:24, Bjorn Helgaas wrote:
By the PCIe spec, the TDISP part. Once the device in CONFIG_LOCKED or RUN, clearing MSE or BME will destroy this state == will go to the ERROR state. PCIe r7, "Figure 11-5 TDISP State Machine".
Then, if it was CONFIG_LOCKED - the device won't be able to go to the RUN state which... | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 16:58:29 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On 26/2/26 08:35, dan.j.williams@intel.com wrote:
OTOH TDX and SNP do not leak SME mask to DMA handles, and ARM does.
Sounds like what, we need sme_dma_me_mask in addition to sme_me_mask? Scary.
--
Alexey | {
"author": "Alexey Kardashevskiy <aik@amd.com>",
"date": "Thu, 26 Feb 2026 17:22:23 +1100",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | On February 26, 2026 3:39:37 AM UTC, Alexey Kardashevskiy <aik@amd.com> wrote:
You sound like someone who hasn't been reviewing patches and scratching his head how to approach such a conglomerate as yours which does many things at once...
The rule is very simple actually: a patch should do one logical thing only. And... | {
"author": "Borislav Petkov <bp@alien8.de>",
"date": "Thu, 26 Feb 2026 19:52:33 +0000",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Here are some patches to continue enabling SEV-TIO on AMD.
SEV-TIO allows guests to establish trust in a device that supports TEE
Device Interface Security Protocol (TDISP, defined in PCIe r6.0+) and
then interact with the device via private memory.
In order to streamline upstreaming process, a common TSM infrastruct... | null | null | null | [PATCH kernel 0/9] PCI/TSM: coco/sev-guest: Implement SEV-TIO PCIe TDISP (phase2) | Alexey Kardashevskiy wrote:
[..]
That is not the concern. The concern is how does Linux maintain a
convention around these use case so that common semantics converge on a
common implementation expectations.
I have a patch brewing that moves interface report consumption into
encrypted resource population for ioremap(... | {
"author": "<dan.j.williams@intel.com>",
"date": "Thu, 26 Feb 2026 13:08:14 -0800",
"is_openbsd": false,
"thread_id": "69a0b63e3e547_1cc5100ae@dwillia2-mobl4.notmuch.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | Recent changes replaced the use of no_64bit_msi with msi_addr_mask.
As a result, msi_addr_mask is now expected to be initialized to
DMA_BIT_MASK(64) when a pci_dev is set up. However, this initialization
was missed on powerpc due to differences in the device initialization
path compared to other (x86) architecture. Due... | {
"author": "Nilay Shroff <nilay@linux.ibm.com>",
"date": "Fri, 20 Feb 2026 12:32:27 +0530",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | Recent changes replaced the use of no_64bit_msi with msi_addr_mask,
which is now expected to be initialized to DMA_BIT_MASK(64) during PCI
device setup. On SPARC systems, this initialization was inadvertently
missed for devices instantiated from device tree nodes, leaving
msi_addr_mask unset for OF-created pci_dev inst... | {
"author": "Nilay Shroff <nilay@linux.ibm.com>",
"date": "Fri, 20 Feb 2026 12:32:28 +0530",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | Hi Nilay,
On 2/20/26 15:02, Nilay Shroff wrote:
This series is:
Reviewed-by: Vivian Wang <wangruikang@iscas.ac.cn>
With the caveat that I have neither powerpc nor sparc machines to test,
so it really is only reviewed.
Thanks and with apologies,
Vivian "dramforever" Wang | {
"author": "Vivian Wang <wangruikang@iscas.ac.cn>",
"date": "Fri, 20 Feb 2026 18:14:57 +0800",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | Hi,
On Fri, 2026-02-20 at 18:14 +0800, Vivian Wang wrote:
Then please make sure that the changes have been tested on actual hardware.
We've seen some regressions with changes on SPARC that went in without testing.
Adrian
--
.''`. John Paul Adrian Glaubitz
: :' : Debian Developer
`. `' Physicist
`- GPG: 6... | {
"author": "John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>",
"date": "Fri, 20 Feb 2026 14:15:49 +0100",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | Tested and passed on SPARC Enterprise T5220.
Without this patch, the e1000e would use intx.
Tested-by: Han Gao <gaohan@iscas.ac.cn <mailto:gaohan@iscas.ac.cn>> # on SPARC Enterprise T5220 | {
"author": "Han Gao <gaohan@iscas.ac.cn>",
"date": "Sun, 22 Feb 2026 00:36:22 +0800",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | Tested-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Tested on an IBM Power System LPAR (pseries).
On an unpatched kernel, all LPFC functions failed MSI/MSI-X setup with:
[ 0.175139] Running MSI bitmap self-tests ...
[ 1.521630] lpfc 0152:60:00.0: arch assigned 64-bit MSI address 0xffff3840 above device MS... | {
"author": "Venkat <venkat88@linux.ibm.com>",
"date": "Sun, 22 Feb 2026 16:16:40 +0530",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | Hi,
Recent changes [1] which replaced pci_dev::no_64bit_msi with pci_dev::
msi_addr_mask inadvertently missed to initialize the pci_dev::msi_addr_mask
to the DMA_BIT_MASK(64) on powerpc platform. Due to this, later the
validation the programmed MSI address against the msi_addr_mask fails.
This causes pci device probe... | null | null | null | [PATCHv2 0/2] pci: fix msi_addr_mask on powerpc and sparc systems | [cc->to powerpc, sparc maintainers for ack]
On Fri, Feb 20, 2026 at 12:32:26PM +0530, Nilay Shroff wrote:
These fix regressions on powerpc and sparc caused by 386ced19e9a3
("PCI/MSI: Convert the boolean no_64bit_msi flag to a DMA address
mask").
These fixes have been tested by Han Gao (SPARC Enterprise T5220),
Natha... | {
"author": "Bjorn Helgaas <helgaas@kernel.org>",
"date": "Fri, 27 Feb 2026 10:44:27 -0600",
"is_openbsd": false,
"thread_id": "20260227164427.GA3897611@bhelgaas.mbox.gz"
} |
lkml_critique | linux-pci | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the forma patch set.
Signed-off-by: Zhiping ... | null | null | null | [RFC 2/2] RMDA MLX5: get tph for p2p access when registering dmabuf mr | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:53 -0800",
"is_openbsd": false,
"thread_id": "aaDxmGoqpjnvmVs9@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the forma patch set.
Signed-off-by: Zhiping ... | null | null | null | [RFC 2/2] RMDA MLX5: get tph for p2p access when registering dmabuf mr | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the formal patch set.
Signed-off-by: Zhiping... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:55 -0800",
"is_openbsd": false,
"thread_id": "aaDxmGoqpjnvmVs9@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the forma patch set.
Signed-off-by: Zhiping ... | null | null | null | [RFC 2/2] RMDA MLX5: get tph for p2p access when registering dmabuf mr | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:54 -0800",
"is_openbsd": false,
"thread_id": "aaDxmGoqpjnvmVs9@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the forma patch set.
Signed-off-by: Zhiping ... | null | null | null | [RFC 2/2] RMDA MLX5: get tph for p2p access when registering dmabuf mr | The subject prefix should be lower case "vfio" to match the subsystem
commit style.
On Tue, Feb 10, 2026 at 11:39:54AM -0800, Zhiping Zhang wrote:
I don't think you can add fields to a uapi struct like this since it
breaks comptibility. Instead, I think you may be able to carve it out of
the "flags" field since it's ... | {
"author": "Keith Busch <kbusch@kernel.org>",
"date": "Thu, 26 Feb 2026 17:56:07 -0700",
"is_openbsd": false,
"thread_id": "aaDxmGoqpjnvmVs9@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the forma patch set.
Signed-off-by: Zhiping ... | null | null | null | [RFC 2/2] RMDA MLX5: get tph for p2p access when registering dmabuf mr | On Tue, Feb 10, 2026 at 11:39:55AM -0800, Zhiping Zhang wrote:
You defined the "get_tph" function to take a pointer to a raw steering
tag value, but you're passing in the steering index to it's table.
But in general, since you're letting the user put whatever they want in
the vfio private area, should there be some v... | {
"author": "Keith Busch <kbusch@kernel.org>",
"date": "Thu, 26 Feb 2026 18:21:28 -0700",
"is_openbsd": false,
"thread_id": "aaDxmGoqpjnvmVs9@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | null | null | null | [RFC 1/2] Vfio: add callback to get tph info for dmabuf | Currently, the steering tag can be used for a CPU on the motherboard; the
ACPI check is in place to query and obtain the supported tph settings. Here
we intend to use the tph info to improve RDMA NIC memory access on a vfio-based
accelerator device via PCIe peer-to-peer. When an applicantion register a
RDMA memory regi... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:53 -0800",
"is_openbsd": false,
"thread_id": "aaDrp7teQoutU79s@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | null | null | null | [RFC 1/2] Vfio: add callback to get tph info for dmabuf | The patch adds a local function to check and get tph info when available during
dmabuf mr registration. Note the DMAH workflow for CPU still takes precedence in
the process. Currently, it only works with the direct st_mode. Compatibility
with other st_modes will be added in the formal patch set.
Signed-off-by: Zhiping... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:55 -0800",
"is_openbsd": false,
"thread_id": "aaDrp7teQoutU79s@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | null | null | null | [RFC 1/2] Vfio: add callback to get tph info for dmabuf | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | {
"author": "Zhiping Zhang <zhipingz@meta.com>",
"date": "Tue, 10 Feb 2026 11:39:54 -0800",
"is_openbsd": false,
"thread_id": "aaDrp7teQoutU79s@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | null | null | null | [RFC 1/2] Vfio: add callback to get tph info for dmabuf | The subject prefix should be lower case "vfio" to match the subsystem
commit style.
On Tue, Feb 10, 2026 at 11:39:54AM -0800, Zhiping Zhang wrote:
I don't think you can add fields to a uapi struct like this since it
breaks comptibility. Instead, I think you may be able to carve it out of
the "flags" field since it's ... | {
"author": "Keith Busch <kbusch@kernel.org>",
"date": "Thu, 26 Feb 2026 17:56:07 -0700",
"is_openbsd": false,
"thread_id": "aaDrp7teQoutU79s@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | This RFC patch adds a callback to get the tph info on DMA buffer exporters.
The tph info includes both the steering tag and the process hint (ph).
Signed-off-by: Zhiping Zhang <zhipingz@meta.com>
---
drivers/vfio/pci/vfio_pci_dmabuf.c | 15 ++++++++++++++-
include/linux/dma-buf.h | 30 +++++++++++++++++++++... | null | null | null | [RFC 1/2] Vfio: add callback to get tph info for dmabuf | On Tue, Feb 10, 2026 at 11:39:55AM -0800, Zhiping Zhang wrote:
You defined the "get_tph" function to take a pointer to a raw steering
tag value, but you're passing in the steering index to it's table.
But in general, since you're letting the user put whatever they want in
the vfio private area, should there be some v... | {
"author": "Keith Busch <kbusch@kernel.org>",
"date": "Thu, 26 Feb 2026 18:21:28 -0700",
"is_openbsd": false,
"thread_id": "aaDrp7teQoutU79s@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | From: Keith Busch <kbusch@kernel.org>
Make the code a little easier to navigate with more descriptive
function names. The two renamed functions here "try" to do to a reset,
so make that clear in the name to distinguish them from other similarly
named functions.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Sig... | null | null | null | [PATCHv5 1/3] PCI: rename __pci_bus_reset and __pci_slot_reset | From: Keith Busch <kbusch@kernel.org>
Use the slot reset method when resetting the bridge if the bus contains
hot plug slots. This fixes spurious hot plug events that are triggered
by the secondary bus reset that bypasses the slot's detection disabling.
Resetting a bridge's subordinate bus can be done like this:
#... | {
"author": "Keith Busch <kbusch@meta.com>",
"date": "Tue, 17 Feb 2026 08:08:36 -0800",
"is_openbsd": false,
"thread_id": "aaDL_cY4oDfRsFU2@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | From: Keith Busch <kbusch@kernel.org>
Make the code a little easier to navigate with more descriptive
function names. The two renamed functions here "try" to do to a reset,
so make that clear in the name to distinguish them from other similarly
named functions.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Sig... | null | null | null | [PATCHv5 1/3] PCI: rename __pci_bus_reset and __pci_slot_reset | From: Keith Busch <kbusch@kernel.org>
A pcie hotplug slot applies to the entire subordinate bus. Thus, pciehp
only allocates a single hotplug_slot for the bridge to that bus. The pci
slot, though, would only match to functions on device 0, meaning all
device beyond that are not matched to any slot even though they sha... | {
"author": "Keith Busch <kbusch@meta.com>",
"date": "Tue, 17 Feb 2026 08:08:35 -0800",
"is_openbsd": false,
"thread_id": "aaDL_cY4oDfRsFU2@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | From: Keith Busch <kbusch@kernel.org>
Make the code a little easier to navigate with more descriptive
function names. The two renamed functions here "try" to do to a reset,
so make that clear in the name to distinguish them from other similarly
named functions.
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Sig... | null | null | null | [PATCHv5 1/3] PCI: rename __pci_bus_reset and __pci_slot_reset | From: Keith Busch <kbusch@kernel.org>
Previous version:
https://lore.kernel.org/linux-pci/20260212224112.1913980-1-kbusch@meta.com/
Changes from previous version:
* Fix subject line to match convenction (s/pci/PCI)
* Added example kernel panic logs for fatal hardware errors observed
without the slot hand... | {
"author": "Keith Busch <kbusch@meta.com>",
"date": "Tue, 17 Feb 2026 08:08:33 -0800",
"is_openbsd": false,
"thread_id": "aaDL_cY4oDfRsFU2@kbusch-mbp.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | The AER driver has historically avoided reading the configuration space of
an endpoint or RCiEP that reported a fatal error, considering the link to
that device unreliable. Consequently, when a fatal error occurs, the AER
and DPC drivers do not report specific error types, resulting in logs like:
pcieport 0015:00:00... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 24 Jan 2026 15:45:55 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | changes since v6:
- add aer_report_frozen_error helper per Lukas
- add explicit log for reset case per Lukas
- add comments for pci_dev_put per Kuppuswamy and Lukas
- init info in call site per Kuppuswamy
- rename back to add_error_device per Kuppushwamy and Lukas
- highlight newly added log per Kuppuswamy
- drop orig... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 24 Jan 2026 15:45:52 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | dpc_handler() is registered for error port which recevie DPC interrupt
and acpi_dpc_port_get() locate the port that experienced the containment
event.
Rename edev and pdev to err_port for clear so that later patch will
avoid misused err_port in pcie_do_recovery().
No functional changes intended.
Reviewed-by: Kuppusw... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 24 Jan 2026 15:45:53 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | The DPC driver clears AER fatal status for the port that reported the
error, but not for the downstream device that deteced the error. The
current recovery code only clears non-fatal AER status, leaving fatal
status bits set in the error device.
Use pci_aer_raw_clear_status() to clear both fatal and non-fatal error
s... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 24 Jan 2026 15:45:56 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | Currently, pcie_clear_device_status() clears the entire PCIe Device
Status register (PCI_EXP_DEVSTA), which includes both error status bits
and other status bits such as AUX Power Detected (AUXPD) and
Transactions Pending (TRPND).
Clearing non-error status bits can interfere with other drivers or
subsystems that may r... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 24 Jan 2026 15:45:57 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, 24 Jan 2026 15:45:53 +0800
Shuai Xue <xueshuai@linux.alibaba.com> wrote:
Seems like a good readability improvement to me.
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Tue, 27 Jan 2026 10:10:49 +0000",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, 24 Jan 2026 15:45:54 +0800
Shuai Xue <xueshuai@linux.alibaba.com> wrote:
Maybe it makes sense to carry the err_port naming for the pci_dev
in here as well? Seems stronger than just relying on people
reading the documentation you've added.
Bunch of replication in her with the pci_warn(). Maybe some local v... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Tue, 27 Jan 2026 10:24:02 +0000",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, 24 Jan 2026 15:45:55 +0800
Shuai Xue <xueshuai@linux.alibaba.com> wrote:
Hi Shuai,
With the structure zeroed below (just to make this easier to review, not because
there is a bug as far as I can see)
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
struct aer_err_info has a bunch of fields. I'd ... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Tue, 27 Jan 2026 10:36:43 +0000",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, 24 Jan 2026 15:45:56 +0800
Shuai Xue <xueshuai@linux.alibaba.com> wrote:
Shouldn't this be first patch in series to make it easier to backport?
Otherwise seems reasonable to me, but others know these flows better than me
so hopefully we'll get some more review.
Reviewed-by: Jonathan Cameron <jonathan.cameron@... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Tue, 27 Jan 2026 10:39:31 +0000",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, 24 Jan 2026 15:45:57 +0800
Shuai Xue <xueshuai@linux.alibaba.com> wrote:
Similar to previous. Drag to start of series to make backports easier if
we think this is a fix that affects real cases. For stuff that's defined
in the PCI 6.2 spec, AUX power and Transactions Pending are RO, but
the interesting one is ... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Tue, 27 Jan 2026 10:45:20 +0000",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/27/26 6:24 PM, Jonathan Cameron wrote:
Good point. I think renaming the parameter would improve clarity. However,
I'd prefer to handle it in a separate patch to keep this change focused on
the functional modification. Would that work for you?
Agreed. Here's the improved version:
--- a/drivers/pci/pcie/dpc.c
++... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Wed, 28 Jan 2026 20:27:31 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/27/26 6:36 PM, Jonathan Cameron wrote:
Got it. Will fix it in next verison.
Thanks for valuable comments.
Best Regards,
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Wed, 28 Jan 2026 20:29:25 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/27/26 6:39 PM, Jonathan Cameron wrote:
Yes, you are right. Will move it as the first one.
Thanks.
Best Regards,
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Wed, 28 Jan 2026 20:30:46 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/27/26 6:45 PM, Jonathan Cameron wrote:
Thank you for the detailed feedback.
I'll move this patch to the start of the series for easier backporting.
You're absolutely right - the commit
message should be more explicit about the different bit types and their
implications.
The revised the commit message is:
PCI... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Wed, 28 Jan 2026 20:45:36 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Wed, 28 Jan 2026 20:27:31 +0800
Shuai Xue <xueshuai@linux.alibaba.com> wrote:
Hi Shuai,
...
Sure. Ideal would be a precursor patch, but if it's much easier to
do on top of this I'm fine with that.
You are absolutely correct that it should be a separate patch!
Maybe don't bother with local variables for the thin... | {
"author": "Jonathan Cameron <jonathan.cameron@huawei.com>",
"date": "Wed, 28 Jan 2026 15:02:43 +0000",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | Hi,
On 1/23/2026 11:45 PM, Shuai Xue wrote:
LGTM. Few suggestions inline.
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Since this function focuses specifically on printing fatal error details, would
aer_print_fatal_error() be a more descriptive name?
The 'prior to reset' ... | {
"author": "Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>",
"date": "Wed, 28 Jan 2026 08:50:46 -0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/23/2026 11:45 PM, Shuai Xue wrote:
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer | {
"author": "Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>",
"date": "Wed, 28 Jan 2026 08:58:59 -0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/23/2026 11:45 PM, Shuai Xue wrote:
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
To align with other macros, use 0x000F?
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer | {
"author": "Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>",
"date": "Wed, 28 Jan 2026 09:01:16 -0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/28/26 11:02 PM, Jonathan Cameron wrote:
Got it.
Sure, will remove local devfn and err_type.
Thanks for valuable comments.
Best Regards,
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Thu, 29 Jan 2026 13:49:58 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | Hi, Kuppuswamy,
On 1/29/26 12:50 AM, Kuppuswamy Sathyanarayanan wrote:
Thank you for the thorough review and the Reviewed-by tag!
Good point. aer_print_fatal_error() is indeed more descriptive and aligns
better with the existing aer_print_error() naming convention. I'll rename
it in next version.
Agreed. Moving t... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Thu, 29 Jan 2026 19:46:31 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 1/29/26 1:01 AM, Kuppuswamy Sathyanarayanan wrote:
Sure, will fix it.
Thanks.
Best Regards,
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Thu, 29 Jan 2026 20:09:57 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, Jan 24, 2026 at 03:45:54PM +0800, Shuai Xue wrote:
You're assuming that the parent of the Requester is always identical
to the containing Downstream Port. But that's not necessarily the case:
E.g., imagine a DPC-capable Root Port with a PCIe switch below
whose Downstream Ports are not DPC-capable. Let's say... | {
"author": "Lukas Wunner <lukas@wunner.de>",
"date": "Mon, 2 Feb 2026 15:02:54 +0100",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Mon, Feb 02, 2026 at 03:02:54PM +0100, Lukas Wunner wrote:
Thinking about this some more, I realized there's another problem:
In a scenario like the one I've outlined above, after your change,
pcie_do_recovery() will only broadcast error_detected (and other
callbacks) below the downstream port of the PCIe switch -... | {
"author": "Lukas Wunner <lukas@wunner.de>",
"date": "Mon, 2 Feb 2026 22:09:27 +0100",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Wed, Jan 28, 2026 at 08:45:36PM +0800, Shuai Xue wrote:
Always cite the latest spec revision, i.e. PCIe r7.0 sec 7.5.3.5.
It would be good to explicitly call out that this bit was introduced with
PCIe r5.0 in 2019 and that it's currently the only writable bit in the
register besides the error bits.
Wrong, they'... | {
"author": "Lukas Wunner <lukas@wunner.de>",
"date": "Tue, 3 Feb 2026 08:44:59 +0100",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, Jan 24, 2026 at 03:45:57PM +0800, Shuai Xue wrote:
I don't think there's any harm to write error bits which are currently 0,
so I'd just get rid of the pcie_capability_read_word() and directly write
the error bits.
There's only one user of PCI_EXP_DEVSTA_ERR and it feels a little
awkward to define a macro in... | {
"author": "Lukas Wunner <lukas@wunner.de>",
"date": "Tue, 3 Feb 2026 08:53:37 +0100",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Sat, Jan 24, 2026 at 03:45:56PM +0800, Shuai Xue wrote:
That's not quite accurate:
The error device has undergone a Hot Reset as a result of the Link Down
event. To be able to use it again, pci_restore_state() is invoked by
the driver's ->slot_reset() callback. And pci_restore_state() does
clear fatal status bit... | {
"author": "Lukas Wunner <lukas@wunner.de>",
"date": "Tue, 3 Feb 2026 09:06:50 +0100",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 2/3/26 3:53 PM, Lukas Wunner wrote:
Good point. I will remove the read step.
Agreed, will move PCI_EXP_DEVSTA_ERR to drivers/pci/pci.c.
Got it. Will send a individual patch.
Thanks for valuable comments.
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Fri, 6 Feb 2026 15:39:29 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 2/3/26 3:44 PM, Lukas Wunner wrote:
Sure, I will update the cite version.
Sure, will add it.
Thanks for correcting me. Will fix it.
Thanks for valuable comments.
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Fri, 6 Feb 2026 16:12:39 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 2/2/26 10:02 PM, Lukas Wunner wrote:
I see. Goot point.
See my reply in your later patch.
Sure, I wll use the common "dport" and "req" term from spec to make it more readable.
Thanks for valuable comments.
Shuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Fri, 6 Feb 2026 16:41:06 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 2/3/26 5:09 AM, Lukas Wunner wrote:
Thanks again for the very detailed analysis and for the pointers to
your earlier mail.
You are right, thanks for pointing it out.
In the AER path, pcie_do_recovery() is indeed invoked with the Error
Source device found by find_source_device(), and internally it treats
that dev... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 7 Feb 2026 15:48:07 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 2/3/26 4:06 PM, Lukas Wunner wrote:
You're right that many drivers call pci_restore_state() in their
->slot_reset() callback, which clears all AER status bits. However,
since ->slot_reset() is driver-defined and not all drivers invoke
pci_restore_state(), there could be cases where fatal AER status bits
remain set... | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Sat, 7 Feb 2026 16:34:23 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On Fri, Feb 27, 2026 at 04:28:59PM +0800, Shuai Xue wrote:
The problem is that if the hierarchy that was reset is deeper than
one level, you first need to call pci_restore_state() on all the
PCIe Upstream and Downstream Ports that were reset before you can
access the Endpoints at the bottom of the hierarchy.
E.g. if ... | {
"author": "Lukas Wunner <lukas@wunner.de>",
"date": "Fri, 27 Feb 2026 11:47:24 +0100",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | The current implementation of pcie_do_recovery() assumes that the
recovery process is executed for the device that detected the error.
However, the DPC driver currently passes the error port that experienced
the DPC event to pcie_do_recovery().
Use the SOURCE ID register to correctly identify the device that
detected ... | null | null | null | [PATCH v7 2/5] PCI/DPC: Run recovery on device that detected the error | On 2/27/26 6:47 PM, Lukas Wunner wrote:
Sure, glad to hear you have been working on that.
Thanks.
SHuai | {
"author": "Shuai Xue <xueshuai@linux.alibaba.com>",
"date": "Fri, 27 Feb 2026 20:28:17 +0800",
"is_openbsd": false,
"thread_id": "a0ec1ce8-06cc-463d-86b4-a6d6a625a808@linux.alibaba.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Since the PCI subsystem has started enabling all ASPM states for all
devicetree based platforms, the ASPM enablement code from this driver can
now be dropped.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https:... | null | null | null | [PATCH v2 2/2] PCI: qcom: Remove the custom ASPM enablement code | Hi,
This series is one of the 'let's bite the bullet' kind, where we have decided to
enable all ASPM and Clock PM states by default on devicetree platforms [1]. The
reason why devicetree platforms were chosen because, it will be of minimal
impact compared to the ACPI platforms. So seemed ideal to test the waters.
Pro... | {
"author": "Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org>",
"date": "Mon, 22 Sep 2025 21:46:43 +0530",
"is_openbsd": false,
"thread_id": "26ad62ff-4972-4b29-8f9e-1868cd20ee00@nvidia.com.mbox.gz"
} |
lkml_critique | linux-pci | From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Since the PCI subsystem has started enabling all ASPM states for all
devicetree based platforms, the ASPM enablement code from this driver can
now be dropped.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https:... | null | null | null | [PATCH v2 2/2] PCI: qcom: Remove the custom ASPM enablement code | From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
So far, the PCI subsystem has honored the ASPM and Clock PM states set by
the BIOS (through LNKCTL) during device initialization, if it relies on the
default state selected using:
* Kconfig: CONFIG_PCIEASPM_DEFAULT=y, or
* cmdline: "pcie_aspm=off", ... | {
"author": "Manivannan Sadhasivam via B4 Relay <devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org>",
"date": "Mon, 22 Sep 2025 21:46:44 +0530",
"is_openbsd": false,
"thread_id": "26ad62ff-4972-4b29-8f9e-1868cd20ee00@nvidia.com.mbox.gz"
} |
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