text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
*/
#define SPI_MEM_PER_END_INT_ENA (BIT(0))
#define SPI_MEM_PER_END_INT_ENA_M (BIT(0))
#define SPI_MEM_PER_END_INT_ENA_V 0x1
#define SPI_MEM_PER_END_INT_ENA_S 0
#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C4)
/* SPI_MEM_MST_ST_END_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
/*description: Th... | 1,440 |
*/
#define SPI_MEM_PES_END_INT_CLR (BIT(1))
#define SPI_MEM_PES_END_INT_CLR_M (BIT(1))
#define SPI_MEM_PES_END_INT_CLR_V 0x1
#define SPI_MEM_PES_END_INT_CLR_S 1
/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: The clear bit for SPI_MEM_PER_END_INT interrupt.*/
#define SPI_MEM_PER_END_I... | 1,440 |
1: Triggered
when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
#define SPI_MEM_SLV_ST_END_INT_RAW (BIT(3))
#define SPI_MEM_SLV_ST_END_INT_RAW_M (BIT(3))
#define SPI_MEM_SLV_ST_END_INT_RAW_V 0x1
#define SPI_MEM_SLV_ST_END_INT_RAW_S 3
/* SPI_MEM_WPE_END_INT... | 1,440 |
1: Triggered when
Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
#define SPI_MEM_PER_END_INT_RAW (BIT(0))
#define SPI_MEM_PER_END_INT_RAW_M (BIT(0))
#define SPI_MEM_PER_END_INT_RAW_V 0x1
#define SPI_MEM_PER_END_INT_RAW_S 0
#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0x0CC... | 1,440 |
*/
#define SPI_MEM_WPE_END_INT_ST (BIT(2))
#define SPI_MEM_WPE_END_INT_ST_M (BIT(2))
#define SPI_MEM_WPE_END_INT_ST_V 0x1
#define SPI_MEM_WPE_END_INT_ST_S 2
/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The status bit for SPI_MEM_PES_END_INT interrupt.*/
#define SPI_MEM_PES_END_INT_S... | 1,440 |
1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (cl... | 1,440 |
/*
*/
#pragma once
#define ADC1_GPIO0_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO1_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO4_CHA... | 1,442 |
/*
*/
/*
*/
#pragma once
/* COMMON CAPS */
#define SOC_ADC_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_TWAI_SUP... | 1,444 |
We check ECO revision in
#define SOC_SECURE_BOOT_SUPPORTED 1
#define SOC_MEMPROT_SUPPORTED 1
#define SOC_BOD_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
#define SOC_ASSIST_DEBUG_SUPPORTED 1
#define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1
... | 1,444 |
RTC functions are still supported
#define SOC_RTCIO_PIN_COUNT (0U)
/* MPI CAPS */
#define SOC_MPI_MEM_BLOCKS_NUM (4)
#define SOC_MPI_OPERATIONS_NUM (3)
/* RSA CAPS */
#define SOC_RSA_MAX_BIT_LEN (3072)
/* SHA CAPS */
/* Max amount of bytes in a single DMA operation is 4095,
for SHA this means that the big... | 1,444 |
5
#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
/* TIMER GROUP CAPS */
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TI... | 1,444 |
< The UART hardware FIFO length */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_SUPPORT_APB_CLK (1) /*!< Support APB as the clock source */
#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
#define SOC_UART_SUPPORT... | 1,444 |
< Support to connect an external low frequency crystal */
/* Temperature Sensor CAPS */
#define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
#define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
/* WI-FI CAPS */
#define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */
#def... | 1,444 |
< Support BLE MESH */
#define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */
#define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */
#define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */
/* PHY CAPS */
#define SOC_PHY_COMBO_MODULE (1)... | 1,444 |
0: external XTAL_32K*/
uint32_t reserved24: 6;
uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/
uint32_t ctr_en: 1;
};
uint32_t val;
} ext_xtl_conf;
union {
struct {
uint32_t reser... | 1,445 |
Clear vld before set reg_ck8m_div_sel*/
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actuall... | 1,445 |
0: XTAL div 2*/
uint32_t ana_clk_rtc_sel: 2;
};
uint32_t val;
} clk_conf;
union {
struct {
uint32_t reserved0: 22;
uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/... | 1,445 |
About 800mA/(8+d)*/
uint32_t sdio_modecurlim: 1; /*select current limit mode*/
uint32_t sdio_encurlim: 1; /*enable current limit*/
uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0... | 1,445 |
8v or lower )*/
uint32_t rtculator_force_pu: 1;
};
uint32_t val;
} rtc;
union {
struct {
uint32_t reserved0: 21;
uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/
uint32_t reserved22: 10;
};
... | 1,445 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct spi_mem_dev_s {
union {
struct {
uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/
uint32_t st: 4; /*The current status of S... | 1,447 |
1: enable 0: disable.*/
uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the po... | 1,447 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pp... | 1,447 |
Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0:... | 1,447 |
*/
uint32_t reserved4: 3; /*reserved*/
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
ui... | 1,447 |
1: enable 0: disable.*/
uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
uint32_t reserved16: 2; /*reserved*/
uint32_t q_pol: 1; ... | 1,447 |
1: enable 0: disable.*/
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
uint32_t reserved25: 7; /*reserved*/
};
uint32_t val;
} ctrl;
union {
struc... | 1,447 |
0: Not error.*/
};
uint32_t val;
} ctrl1;
union {
struct {
uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
uint32_t cs_hold_time: 5; /*Spi cs signal is de... | 1,447 |
*/
uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24: 7; /*reserved*/
uint32_t clk_equ_sysclk: 1; /*Set this bit in 1... | 1,447 |
*/
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
uint32_t reserved16: 8; /*reserved*/
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_mem_... | 1,447 |
*/
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen: 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (... | 1,447 |
The register value shall be (bit_num-1).*/
uint32_t reserved10: 22; /*reserved*/
};
uint32_t val;
} mosi_dlen;
union {
struct {
uint32_t usr_miso_bit_len: 10; /*The length in bits of read-data. The register value shall be (bit_num... | 1,447 |
*/
uint32_t cs1_dis: 1; /*SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active to select SPI device such as flash external RAM and so on.*/
uint32_t reserved2: 1; /*reserved*/
uint32_t mst_st_trans_end: 1; /*The ... | 1,447 |
*/
uint32_t reserved11: 21; /*reserved*/
};
uint32_t val;
} misc;
uint32_t tx_crc; /*SPI1 TX CRC data register.*/
union {
struct {
uint32_t req_en: 1; /*For SPI0 Cache access en... | 1,447 |
1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
uint32_t fdin_quad: 1; /*For SPI1 din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
uint32_t fdout_quad: 1; /*For SPI1 dout phase apply 4... | 1,447 |
*/
uint32_t spi0_mst_st: 3; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state 1:EM_CACHE_GRANT 2: program/erase suspend state 3: SPI0 read data state 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO 5: SPI0 write data state.*/
uint32_t cspi_lock_d... | 1,447 |
The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
uint32_... | 1,447 |
If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out status_in[15:0] is valid when two bytes of data are read out) SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
uint32_t frd_sus_2b: 1; /*1: Read two bytes when... | 1,447 |
*/
uint32_t flash_pes_command: 8; /*Program/Erase suspend command.*/
uint32_t wait_pesr_command: 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
... | 1,447 |
*/
uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
uint32_t reserved5: 27; ... | 1,447 |
..*/
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 ... | 1,447 |
*/
uint32_t pes_end_int_ena: 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
uint32_t wpe_end_int_ena: 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
uint32_t st_end_int_ena: 1; /*The enable bit for SPI_MEM_SLV_ST_END_I... | 1,447 |
*/
uint32_t mst_st_end: 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
uint32_t reserved5: 27; /*reserved*/
};
uint32_t val;
} int_clr;
union {
struct {
uint32_t per_end: 1; /*T... | 1,447 |
It means that SPI_CS raises high. 0: Others*/
uint32_t mst_st_end: 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
uint32_t reserved5: 27; /*reserved*/
... | 1,447 |
1: Enable. 0: Disable.*/
uint32_t reserved1: 31; /*reserved*/
};
uint32_t val;
} clock_gate;
union {
struct {
uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 4... | 1,447 |
");
#endif
#ifdef __cplusplus
}
#endif
| 1,447 |
/*
*/
#ifndef _DPORT_ACCESS_H_
#define _DPORT_ACCESS_H_
#include
#include "soc.h"
#include "uart_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
// Target does not have DPORT bus, so these macros are all same as the non-DPORT versions
#define DPORT_INTERRUPT_DISABLE()
#define DPORT_INTERRUPT_RESTORE()
/**
*/
voi... | 1,448 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,449 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte; /*a*/
};
uint32_t val;
} ahb_fifo;
union {
struct {
uint32_t rxfifo_full: 1; ... | 1,451 |
*/
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
... | 1,451 |
*/
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.*/
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has ke... | 1,451 |
*/
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
uint32_t wakeup: 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_thr... | 1,451 |
*/
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
uint32_t cts_chg: ... | 1,451 |
*/
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
uint32_t tx_brk_idle_done: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
uint3... | 1,451 |
*/
uint32_t wakeup: 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
uint32_t reserved20: 12; /*Reserved*/
};
uint32_t val;
} int_st;
union {
struct {
uint32_t rxfifo... | 1,451 |
*/
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
uint32_t sw_xon: 1; /*This is the enable bit for sw_x... | 1,451 |
*/
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
uint32_t at_cmd_char_det: 1; /*This is the enable bit... | 1,451 |
*/
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_... | 1,451 |
.*/
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
uint32_t rs485_parity_err: 1; /*Set this bit to clear t... | 1,451 |
*/
uint32_t reserved12: 8;
uint32_t div_frag: 4; /*The decimal part of the frequency divider factor.*/
uint32_t reserved24: 8; /*Reserved*/
};
uint32_t val;
} clk_div;
union {
struct {
uint32_t gli... | 1,451 |
*/
uint32_t rxd: 1; /*This register represent the level value of the internal uart rxd signal.*/
uint32_t txfifo_cnt:10; /*Stores the byte number of data in Tx-FIFO.*/
uint32_t reserved26: 3; /*Reserved*/
... | 1,451 |
*/
uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit.*/
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
uint32_t sw_dtr: 1; ... | 1,451 |
*/
uint32_t irda_rx_inv: 1; /*Set this bit to invert the level of IrDA receiver.*/
uint32_t loopback: 1; /*Set this bit to enable uart loopback test mode.*/
uint32_t tx_flow_en: 1; /*Set this bit to enable flow control func... | 1,451 |
*/
uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/
uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/
uint32_t dtr_inv: 1; /*Set this bit to inv... | 1,451 |
*/
uint32_t txfifo_empty_thrhd: 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
uint32_t dis_rx_dat_ovf: 1; /*Disable UART Rx data overflow detect.*/
uint32_t rx_tout_flow_dis: 1; ... | 1,451 |
It is used in baud rate-detect process.*/
uint32_t reserved12: 20; /*Reserved*/
};
uint32_t val;
} highpulse;
union {
struct {
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change. It is used in baud r... | 1,451 |
It is cleared by hardware automatically.*/
uint32_t send_xoff: 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
uint32_t reserved6: 26; /*Reserved*/
};
uint32_t val;
} flow_conf;
union {
stru... | 1,451 |
*/
uint32_t xon_char: 8; /*This register stores the Xon flow control char.*/
uint32_t reserved17: 15; /*Reserved*/
};
uint32_t val;
} swfc_conf1;
union {
struct {
uint32_t tx_brk_num: 8; /*Th... | 1,451 |
*/
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
uint32_t tx_rx_en: 1; /*Set this bit to enable receiver could receive dat... | 1,451 |
*/
uint32_t reserved16: 16; /*Reserved*/
};
uint32_t val;
} at_cmd_precnt;
union {
struct {
uint32_t post_idle_num:16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/
... | 1,451 |
*/
uint32_t reserved16: 16; /*Reserved*/
};
uint32_t val;
} at_cmd_char;
union {
struct {
uint32_t reserved0: 1;
uint32_t rx_size: 3; /*This register is used to configure the amount of mem allocated for rec... | 1,451 |
*/
uint32_t force_pu: 1; /*Set this bit to force power up UART memory.*/
uint32_t reserved28: 4;
};
uint32_t val;
} mem_conf;
union {
struct {
uint32_t apb_tx_waddr:10; /*This register stores the offset addres... | 1,451 |
UART0 is 10'h100. UART1 is 10'h180.*/
uint32_t reserved21: 11; /*Reserved*/
};
uint32_t val;
} mem_rx_status;
union {
struct {
uint32_t st_urx_out: 4; /*This is the status register of receiver.*/
uint32_t st_utx_... | 1,451 |
It is used in boudrate-detect process.*/
uint32_t reserved12: 20; /*Reserved*/
};
uint32_t val;
} negpulse;
union {
struct {
uint32_t sclk_div_b: 6; /*The denominator of the frequency divider factor.*/
uint32_t ... | 1,451 |
*/
uint32_t tx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx.*/
uint32_t rx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Rx.*/
uint32_t reserved28: 4;
};
uint32_t val;
} clk_conf;
uint32_t... | 1,451 |
*/
};
uint32_t val;
} id;
} uart_dev_t;
extern uart_dev_t UART0;
extern uart_dev_t UART1;
#ifdef __cplusplus
}
#endif
| 1,451 |
/*
*/
// This file defines GPIO lookup macros for available UART IO_MUX pins on ESP32C3.
#ifndef _SOC_UART_CHANNEL_H
#define _SOC_UART_CHANNEL_H
//UART channels
#define UART_GPIO21_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 21
#define UART_GPIO20_DIRECT_CHANNEL UART_NUM_0
#define UA... | 1,452 |
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
/** Configuration Register */
/** Type of conf register
*/
typedef union {
struct {
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
*/
uint32_t systimer_clk_fo: 1... | 1,453 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include
/* Register Layout */
/* The TWAI peripheral's registers are 8bits, however the ESP32-C3 can only access
*/
typedef volatile struct twai_dev_s {
//Configuration and Control Registers
union {
struct {
uint32_t rm: 1... | 1,454 |
2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; ... | 1,454 |
8 Miss Status */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti... | 1,454 |
0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4:... | 1,454 |
7 Sampling*/
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; ... | 1,454 |
8 CLKOUT enable/disable */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");... | 1,454 |
/*
*/
#pragma once
#include "interrupt_core0_reg.h"
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
#define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
| 1,455 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,458 |
1'b0: Support clock only when
application writes registers.*/
#define UHCI_CLK_EN (BIT(11))
#define UHCI_CLK_EN_M (BIT(11))
#define UHCI_CLK_EN_V 0x1
#define UHCI_CLK_EN_S 11
/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
/*description: Set this bit to enable data integrity checking by appending a
... | 1,458 |
*/
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
#define UHCI_UART_IDLE_EOF_EN_M (BIT(8))
#define UHCI_UART_IDLE_EOF_EN_V 0x1
#define UHCI_UART_IDLE_EOF_EN_S 8
/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/
#define UHCI_CRC_REC_EN (BIT(7))
... | 1,458 |
*/
#define UHCI_UART1_CE (BIT(3))
#define UHCI_UART1_CE_M (BIT(3))
#define UHCI_UART1_CE_V 0x1
#define UHCI_UART1_CE_S 3
/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
/*description: Set this bit to link up HCI and UART0.*/
#define UHCI_UART0_CE (BIT(2))
#define UHCI_UART0_CE_M (BIT(2))
#define UHCI_UART0... | 1,458 |
/*
*/
#pragma once
/**
*/
#define I2C_BIAS 0X6A
#define I2C_BIAS_HOSTID 0
#define I2C_BIAS_DREG_1P1_PVT 1
#define I2C_BIAS_DREG_1P1_PVT_MSB 3
#define I2C_BIAS_DREG_1P1_PVT_LSB 0
| 1,459 |
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,460 |
/*
*/
#pragma once
/**
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 0
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_IR_FORCE_XPD_CK 0
#define I2C_ULP_IR_FORCE_XPD_CK_MSB 2
#define I2C_ULP_IR_FORCE_XPD_CK_LSB 2
#define I2C_ULP_IR_FORCE_XPD_IPH 0
#de... | 1,461 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/
uint32_t reserved20: 12;
};
uint32_t val;
} scl_low;
union {... | 1,463 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct spi_dev_s {
union {
struct {
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
uint32_t reserved18 ... | 1,464 |
Can be configured in CONF state.*/
uint32_t reserved4 : 1; /*reserved*/
uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
uint32_t faddr_quad : 1; ... | 1,464 |
Can be configured in CONF state.*/
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t reserved16 : 1; /*reserved*/
uint32_t reserved17 ... | 1,464 |
*/
uint32_t reserved22 : 3; /*reserved*/
uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
uint32_t wr_bit_order : 1; /*In command address write-data (M... | 1,464 |
So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
uint32_t reserved22 : 9; /*reserve... | 1,464 |
*/
uint32_t reserved4 : 1; /*reserved*/
uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
uint32_t cs_hold : 1; /*spi cs... | 1,464 |
Can be configured in CONF state.*/
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
uint32_t reserved14 : 1; /*reserved*/
uint32_t usr_conf_nxt : 1... | 1,464 |
1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
uint32_t usr_dummy_idle : 1; /*spi cloc... | 1,464 |
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