text stringlengths 1 9.98k | __index_level_0__ int64 0 4.17k |
|---|---|
Can be configured in CONF state.*/
};
uint32_t val;
} user;
union {
struct {
uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
uint32_t rese... | 1,464 |
The register value shall be (bit_num-1). Can be configured in CONF state.*/
};
uint32_t val;
} user1;
union {
struct {
uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/
uint32_t reserved16 ... | 1,464 |
The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
uint32_t reserved18 : 14; /*reserved*/
};
uint32_t val;
} ms_dlen;
union {
struct {
... | 1,464 |
*/
uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Ca... | 1,464 |
Can be configured in CONF state.*/
uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
uint32_t quad_din_pin_swap : 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured ... | 1,464 |
Can be configured in CONF state.*/
uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
... | 1,464 |
.. Can be configured in CONF state.*/
uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
uint32_t din2_num : 2; /*the input sig... | 1,464 |
Can be configured in CONF state.*/
uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
uint32_t dout2_mode ... | 1,464 |
1: enable. 0: disable.*/
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave ... | 1,464 |
*/
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlle... | 1,464 |
*/
uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/
uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/
uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 int... | 1,464 |
*/
uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
uint32_t buf_addr_err : 1; /*The enable bit for... | 1,464 |
*/
uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/
uint32_t en_qpi : 1; /*The clear bit for SPI ... | 1,464 |
*/
uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
uint32_t trans_done : 1; /*The clear bit for SPI... | 1,464 |
*/
uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/
uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val... | 1,464 |
1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 in... | 1,464 |
1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
uint32_t wr_buf_done : 1; /*The raw bit for SPI_SL... | 1,464 |
1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger tha... | 1,464 |
The value is only controlled by application.*/
uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/
uint32_t reserved21 : 11; /*reserved*/
};
uint32_t val;
} dma_int_ra... | 1,464 |
*/
uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/
uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/
uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DON... | 1,464 |
*/
uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI... | 1,464 |
0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first e... | 1,464 |
0: others*/
uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-writ... | 1,464 |
0: This is not seg-trans mode.*/
uint32_t reserved29 : 3; /*reserved*/
};
uint32_t val;
} slave;
union {
struct {
uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */
... | 1,464 |
*/
uint32_t reserved28 : 4; /*reserved*/
};
uint32_t val;
} date;
} spi_dev_t;
extern spi_dev_t GPSPI2;
#ifdef __cplusplus
}
#endif
| 1,464 |
/**
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define EFUSE_WRITE_OP_CODE 0x5a5a
#define EFUSE_READ_OP_CODE 0x5aa5
#define EFUSE_PKG_VERSION_ESP32C3 0 // QFN32
#define EFUSE_PKG_VERSION_ESP8685 1 // QFN28
#define EFUSE_PKG_VERSION_ESP32C3AZ 2 // QFN32
#define EFUSE_PKG_VERSION_ESP8686 ... | 1,465 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/sensitive_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef union {
struct {
uint32_t cat0 : 2;
uint32_t cat1 : 2;
uint32_t cat2 : 2;
uint32_t res0 : 8;
uint32_t s... | 1,466 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicab... | 1,467 |
/*
*/
#pragma once
/**
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 0
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_C... | 1,468 |
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,469 |
/*
*/
#ifndef _SOC_I2S_REG_H_
#define _SOC_I2S_REG_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "soc.h"
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
#de... | 1,470 |
0: Disable.*/
#define I2S_RX_PDM_EN (BIT(20))
#define I2S_RX_PDM_EN_M (BIT(20))
#define I2S_RX_PDM_EN_V 0x1
#define I2S_RX_PDM_EN_S 20
/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/
#define I2S_RX_TDM_EN (BIT(19))
#define I2S_RX_TDM_EN_M (BIT(19))... | 1,470 |
0:store 24 channel bits to 24 bits.*/
#define I2S_RX_24_FILL_EN (BIT(16))
#define I2S_RX_24_FILL_EN_M (BIT(16))
#define I2S_RX_24_FILL_EN_V 0x1
#define I2S_RX_24_FILL_EN_S 16
/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
... | 1,470 |
*/
#define I2S_RX_CLKM_DIV_X 0x000001FF
#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V) a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
#define I2S_RX_CLKM_DIV_Y 0x000001FF
#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V) a/2
the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
#define I2S_RX_CLKM_DIV_Z 0x000001F... | 1,470 |
It will trigger i2s_in_suc_eof_int.*/
#define I2S_RX_EOF_NUM 0x00000FFF
#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
#define I2S_RX_EOF_NUM_V 0xFFF
#define I2S_RX_EOF_NUM_S 0
#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068)
/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;defaul... | 1,470 |
/**
*/
#pragma once
#include
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** XTS_AES_PLAIN_MEM register
*/
#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
/** XTS_AES_LINESIZE_REG register
*/
#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
/... | 1,472 |
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,473 |
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,474 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
uint32_t reserved_8;
union {
struct {
uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int... | 1,475 |
0: low addr with low addr value.*/
uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
uint32_t rx_mono_fst_vld: 1; /*1: The first channel data va... | 1,475 |
0: I2S RX right alignment mode.*/
uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 ... | 1,475 |
0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
uint32_t tx_update: 1; /*Set 1 to update I2S ... | 1,475 |
0: I2S TX right alignment mode.*/
uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should... | 1,475 |
*/
uint32_t reserved28: 4; /*Reserved*/
};
uint32_t val;
} tx_conf;
union {
struct {
uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
uint32_t rx_bck_div_num: ... | 1,475 |
*/
uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/
uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/
uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*... | 1,475 |
*/
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
uint32_t reser... | 1,475 |
*/
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
uint32_t reserved30: 2; /*Reserved*/
};
uint32_t val;
} tx_clkm_conf;
union {
struct {
uint32_t rx_clkm_div_z: 9; /*For b a/2 the value of ... | 1,475 |
*/
uint32_t tx_clkm_div_x: 9; /*For b a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
uint32_t tx_clkm_div_yn1: 1; /*For b a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
uint32_t reserved28: 4; /*Reserved*/
};
uint32... | 1,475 |
0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_pdm_chan1_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_pdm_chan2_en : 1; /*1: Enable the valid data input of I2S RX ... | 1,475 |
0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_pdm_chan7_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan8_en : 1; /*1: Enable the valid data input of I2S RX ... | 1,475 |
*/
uint32_t rx_tdm_chan13_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
uint32_t rx_tdm_chan14_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this ... | 1,475 |
0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0... | 1,475 |
0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0... | 1,475 |
0: Disable just output 0 in this channel.*/
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/
uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enab... | 1,475 |
*/
uint32_t reserved18: 2;
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved22: 2;
uint32_t rx_ws_in_dm: 2; /*The delay mode... | 1,475 |
0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved6 : 10; /* Reserved*/
uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.... | 1,475 |
0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
uint32_t reserved30 : 2; /* Reserved*/
};
uint32_t val;
} tx_timing;
union {
struct {
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s... | 1,475 |
0: i2s_tx is working.*/
uint32_t reserved1: 31; /*Reserved*/
};
uint32_t val;
} state;
uint32_t reserved_70;
uint32_t reserved_74;
uint32_t reserved_78;
uint32_t reserved_7c;
union {
struct {
uint32_t date: 28; ... | 1,475 |
0: external XTAL_32K*/
#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23))
#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23))
#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1
#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23
/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */
/*description: state of 32k_wdt*/
#define RTC_CNTL_WDT_STATE... | 1,476 |
0: XTAL div 2*/
#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29))
#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29))
#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1
#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29
/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W ;bitpos:[28] ;default: 1'b1 ; */
/*description: */
#define RTC_CNTL_XTAL_GLOBAL_FORCE... | 1,476 |
00: div128*/
#define RTC_CNTL_CK8M_DIV 0x00000003
#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
#define RTC_CNTL_CK8M_DIV_V 0x3
#define RTC_CNTL_CK8M_DIV_S 4
/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
/*description: used to sync reg_ck8m_div_sel bus. Clear vld b... | 1,476 |
clear vld before set reg_rtc_ana_clk_div*/
#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22))
#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22))
#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1
#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22
#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078)
/* RTC_CNTL_XPD_SDIO_REG : R/W ;bit... | 1,476 |
Only active when reg_sdio_force = 1*/
#define RTC_CNTL_DREFL_SDIO 0x00000003
#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
#define RTC_CNTL_DREFL_SDIO_V 0x3
#define RTC_CNTL_DREFL_SDIO_S 25
/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
/*description: read only re... | 1,476 |
Only active when reg_sdio_force = 0*/
#define RTC_CNTL_SDIO_PD_EN (BIT(21))
#define RTC_CNTL_SDIO_PD_EN_M (BIT(21))
#define RTC_CNTL_SDIO_PD_EN_V 0x1
#define RTC_CNTL_SDIO_PD_EN_S 21
/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
/*description: enable current limit*/
#define RTC_CNTL_SDIO_ENCURLI... | 1,476 |
0: no res*/
#define RTC_CNTL_SDIO_INITI 0x00000003
#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
#define RTC_CNTL_SDIO_INITI_V 0x3
#define RTC_CNTL_SDIO_INITI_S 13
/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
/*description: ability to prevent LDO from overshoo... | 1,476 |
Switch rtc main state*/
#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14))
#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14))
#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1
#define RTC_CNTL_COCPU_STATE_SWITCH_S 14
/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: ulp/cocpu should start to work*... | 1,476 |
/*
*/
#pragma once
#include "esp_bit_defs.h"
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
#define ANA_CONFIG_REG 0x6000E044
#define ANA_CONFIG_S (8)
#define ANA_CONFIG_M (0x3FF)... | 1,478 |
/*
*/
#ifndef _SOC_GPIO_SIG_MAP_H_
#define _SOC_GPIO_SIG_MAP_H_
#define SPICLK_OUT_MUX_IDX SPICLK_OUT_IDX
#define SPIQ_IN_IDX 0
#define SPIQ_OUT_IDX 0
#define SPID_IN_IDX 1
#define SPID_OUT_IDX 1
#define SPIHD_IN_IDX 2
#... | 1,479 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/periph_defs.h"
#include "soc/soc_caps.h"
#if SOC_I2S_SUPPORTED
#include "soc/i2s_struct.h"
#include "soc/i2s_reg.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_I2S_SUPPORTED
/*
Stores a bunch of per-I2S-peripheral data.
*/
typedef struct {
const ... | 1,482 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/*
Stores a bunch of USB-peripheral data.
*/
typedef struct {
const uint8_t extphy_vp_in;
const uint8_t extphy_vm_in;
const uint8_t extphy_rcv_in;
const uint8_t extphy_oen_out;... | 1,483 |
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,484 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_MCPWM_SUPPORTED
typedef struct {
struct {
const periph_module_t module; // Peripheral module
const int irq_id;
struct {
struct {
... | 1,485 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#if SOC_PARLIO_SUPPORTED
#include "soc/parl_io_reg.h"
#include "soc/parl_io_struct.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_PARLIO_SUPPORTED
typedef struct {
struct {
struct {
const int data_... | 1,486 |
/*
*/
#pragma once
#include
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#if SOC_RTCIO_PIN_COUNT > 0
#include "soc/rtc_io_channel.h"
#endif
#if SOC_ADC_RTC_CTRL_SUPPORTED
#include "soc/sens_struct.h"
#endif
#ifdef __cplusplus
extern "C"
{
#endif
#if SOC_RTCIO_PIN_COUNT > 0
#if SOC_RTC... | 1,487 |
/*
*/
#pragma once
#include
#include
#include "esp_assert.h"
#include "esp_bit_defs.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_PAU_SUPPORTED
#define REGDMA_LINK_ENTRY_NUM (SOC_PM_PAU_LINK_NUM) /* Maximum number of REG DMA linked list entries */
#ifndef ARRAY_SIZE
# define ARR... | 1,488 |
continuous = { \
.next = NULL, \
.backup = (void *)_backup, \
.restore = (void *)_restore, \
.mem = NULL \
}, \
.id = (_id) \
}
... | 1,488 |
map = {__VA_ARGS__} \
}, \
.id = (_id) \
}
#define REGDMA_LINK_WRITE_INIT(_id, _backup, _val, _mask, _skip_b, _skip_r) \
{ \
.head = REGDMA_LINK_HEAD_INIT( \
0,... | 1,488 |
head = REGDMA_LINK_HEAD_INIT( \
0, \
REGDMA_LINK_MODE_WAIT, \
0, \
_skip_r, \
_skip_b \
), \
... | 1,488 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_TWAI_SUPPORTED
typedef struct {
struct {
const periph_module_t module; // peripheral module
const int irq_id; // interrupt source ID
const in... | 1,489 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/interrupts.h"
#if SOC_ANA_CMPR_SUPPORTED
#include "soc/ana_cmpr_channel.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_ANA_CMPR_SUPPORTED
typedef struct {
int src_gpio;
int ext_ref_gpio;
int intr_src;
} ana_cmpr_periph_t;
e... | 1,490 |
/*
*/
#pragma once
#include
#include "esp_rom_lldesc.h"
//the size field has 12 bits, but 0 not for 4096.
//to avoid possible problem when the size is not word-aligned, we only use 4096-4 per desc.
/** Maximum size of data in the buffer that a DMA descriptor can hold. */
#define LLDESC_MAX_NUM_PER_DESC (4096-4)
//... | 1,491 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
const periph_module_t module; // peripheral module
const int irq_id; // interrupt source ID
} ieee802154_conn_t;
extern const ieee802154_conn_t ieee8021... | 1,492 |
/*
*/
#pragma once
#include
#include "rtc_io_periph.h"
#include "rtc_cntl_periph.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __cplusplus
}
#endif
| 1,493 |
/*
*/
#pragma once
#include
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#if SOC_SDIO_SLAVE_SUPPORTED
#include "soc/slc_reg.h"
#include "soc/slc_struct.h"
#include "soc/host_reg.h"
#include "soc/host_struct.h"
#include "soc/hinf_reg.h"
#include "soc/hinf_struct.h"... | 1,494 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C"
{
#endif
#if SOC_MPI_SUPPORTED
extern const uint32_t MPI_LL_BLOCK_BASES[SOC_MPI_MEM_BLOCKS_NUM];
extern const uint32_t MPI_LL_OPERATIONS[SOC_MPI_OPERATIONS_NUM];
#endif // SOC_MPI_SUPPORTED
#ifdef __cplusplus
}
#endif
| 1,495 |
/*
*/
#pragma once
#include
#include "sdkconfig.h"
#include "soc/soc.h"
#include "soc/periph_defs.h"
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#include "soc/spi_reg.h"
#include "soc/spi_struct.h"
#include "soc/spi_pins.h"
#include "soc/gpio_sig_map.h"
#if SOC... | 1,496 |
/*
*/
#pragma once
#include
#include
#include "soc/soc_pins.h"
#include "soc/soc_caps.h"
#include "soc/gpio_sig_map.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_USB_OTG_SUPPORTED
/**
*/
typedef struct {
const int pin;
const int func;
const bool is_output;
const int ext_phy_only;
} usb_iopi... | 1,497 |
/*
*/
#pragma once
#include
//include soc related (generated) definitions
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#if SOC_SDMMC_HOST_SUPPORTED
#include "soc/sdmmc_reg.h"
#include "soc/sdmmc_struct.h"
#include "soc/gpio_sig_map.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_SDMMC_HOST_SUPPORTE... | 1,498 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C"
{
#endif
#if SOC_DAC_SUPPORTED
typedef struct {
const uint8_t dac_channel_io_num[SOC_DAC_CHAN_NUM];
} dac_signal_conn_t;
extern const dac_signal_conn_t dac_periph_signal;
#endif // SOC_DAC_SUPPORTED
#ifdef __cplusplus
}
#e... | 1,499 |
/*
*/
#pragma once
#include "sdkconfig.h"
// TODO: IDF-5645
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5
#include "soc/lp_io_reg.h"
#include "soc/lp_io_struct.h"
#include "soc/lp_aon_reg.h"
// ESP32H2-TODO: IDF-6327
#elif CONFIG_IDF_TARGET_ESP32H2
#include "soc/lp_aon_reg.h"
#elif CONFIG_IDF_TARGET_E... | 1,500 |
h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_wdt_reg.h"
#include "soc/lp_wdt_struct.h"
#else
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#endif
| 1,500 |
/*
*/
#pragma once
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
/* included here for ESP-IDF v4.x compatibility */
#include "soc/dport_reg.h"
#endif
#include "soc/hwcrypto_reg.h"
| 1,501 |
/*
*/
#pragma once
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
#include "soc/sens_reg.h"
#include "soc/sens_struct.h"
#endif // CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
| 1,502 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
#include "soc/uart_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_TX_PIN_IDX (0)
#define SOC_UART_RX_PIN_IDX (1)
#define SOC_UART_RTS_PIN_IDX (2)
#define SOC_UART_CT... | 1,503 |
/*
*/
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
uint32_t start_mbps; /*!< Start frequency of the range (included) */
uint32_t end_mbps; /*!< End frequency of the range (included) */
uint8_t hs_freq_range_sel; /*!< HS operating frequen... | 1,504 |
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,505 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#if SOC_PM_SUPPORT_TOP_PD
#include "soc/regdma.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_GDMA_SUPPORTED
typedef struct {
struct {
const periph_module_t module;
struct {
const int rx_irq_id;
... | 1,506 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_RMT_SUPPORTED
typedef struct {
struct {
const int irq;
const periph_module_t module;
struct {
struct {
const int tx_sig;
... | 1,507 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#if SOC_TOUCH_SENSOR_SUPPORTED
#include "soc/touch_sensor_channel.h"
#include "soc/rtc_cntl_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/sens_reg.h"
#include "soc/sens_struct.h"
#include "soc/rtc_io_struct.h"
#endif // SOC_TOUCH_SENSOR_SUPPORTED
#ifdef __cpluspl... | 1,508 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LCDCAM_SUPPORTED
typedef struct {
struct {
const periph_module_t module;
const int irq_id;
const int data_sigs[SOC_LCD_I80_BUS_WIDTH];
const int cs_sig;
... | 1,509 |
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