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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,510 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
#define ESP_CHIP_REV_ABOVE(rev, min_rev) ((min_rev) = (min_rev)))
#ifdef __cplusplus
}
#endif
| 1,511 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_PCNT_SUPPORTED
typedef struct {
struct {
struct {
struct {
const uint32_t pulse_sig;
const uint32_t control_sig;
} ... | 1,512 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TEMPERATURE_SENSOR_ATTR_RANGE_NUM (5)
typedef struct {
int offset;
int reg_val;
int range_min;
int range_max;
int error_max;
} temperature_sensor_attribute_t;
extern const temperature_sensor_attribute_t temperature_sensor_attrib... | 1,513 |
/*
*/
#pragma once
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/adc_channel.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
extern const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM];
#ifdef __cplusplus
}
#endif
| 1,514 |
/*
*/
#pragma once
#include "soc/efuse_reg.h"
#include "soc/efuse_struct.h"
#include "hal/misc.h"
| 1,515 |
/*
*/
#pragma once
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_SDM_SUPPORTED
typedef struct {
struct {
const int sd_sig;
} channels[SOC_SDM_CHANNELS_PER_GROUP];
} sigma_delta_signal_conn_t;
extern const sigma_delta_signal_conn_t sigma_delta_periph_signals;
#endif // ... | 1,516 |
/*
*/
#pragma once
#include
#include "soc/timer_group_reg.h"
#include "soc/timer_group_struct.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
#define TIMG_WDT_WKEY_VALUE 0x5... | 1,517 |
/*
*/
#pragma once
/* Todo: Remove in ESP-IDF v6.0 (IDF-9052) */
#warning "This header is deprecated, please use usb_dwc_periph.h instead"
#include "soc/usb_dwc_periph.h"
| 1,518 |
/*
*/
#pragma once
#include
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_DMA2D_SUPPORTED
typedef struct {
struct {
const int tx_irq_id[SOC_DMA2D_TX_CHANNELS_PER_GROUP];
const int rx_irq_id[SOC_DMA2D_RX_CHANNELS_PER_GROUP];
} groups[SOC_DMA2D_GROUPS];
} dma2d_sig... | 1,519 |
/*
*/
#pragma once
#include "soc/periph_defs.h"
| 1,520 |
/*
*/
#pragma once
#include "soc/i2c_reg.h"
#include "soc/i2c_struct.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#if SOC_PM_SUPPORT_TOP_PD
#include "soc/regdma.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
const uint8_t sda_out_sig;
const uint8_t sda_in_sig;
const uint8... | 1,521 |
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,522 |
/*
*/
#pragma once
#include
#include
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef struct {
uint32_t start_mbps; /*!< Start frequency of the range (included) */
uint32_t end_mbps; /*!< End frequency of the range (included) */
uint8_t hs_freq_range_sel; /*!< HS operating frequen... | 1,523 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of ... | 1,524 |
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicab... | 1,525 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
/**
*/
typedef enum {
GPIO_NUM_NC = -1, /*!< Use to signal not connected to S/W */
GPIO_NUM_0 = 0, /*!< GPIO0, input and output */
GPIO_NUM_1 = 1, /*!< GPIO1, input and output */
GPIO_NUM_2 = 2, /*!< GPIO2, input and output */
... | 1,527 |
< GPIO15, input and output */
GPIO_NUM_16 = 16, /*!< GPIO16, input and output */
GPIO_NUM_17 = 17, /*!< GPIO17, input and output */
GPIO_NUM_18 = 18, /*!< GPIO18, input and output */
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
G... | 1,527 |
< GPIO34, input mode only */
GPIO_NUM_35 = 35, /*!< GPIO35, input mode only */
GPIO_NUM_36 = 36, /*!< GPIO36, input mode only */
GPIO_NUM_37 = 37, /*!< GPIO37, input mode only */
GPIO_NUM_38 = 38, /*!< GPIO38, input mode only */
GPIO_NUM_39 = 39, /*!< GPIO39, input mode only */
GPIO_NU... | 1,527 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,528 |
clear this bit to sample data in SCL high level.*/
uint32_t reserved3: 1;
uint32_t ms_mode: 1; /*Set this bit to configure the module as i2c master clear this bit to configure the module as i2c slave.*/
uint32_t trans_start: 1; /*Set this bi... | 1,528 |
*/
uint32_t slave_rw: 1; /*when in slave mode 1：master read slave 0: master write slave.*/
uint32_t time_out: 1; /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
uint32_t arb_lost: ... | 1,528 |
*/
uint32_t scl_main_state_last: 3; /*This register stores the value of state machine for i2c module. 3'h0: SCL_MAIN_IDLE 3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS 3'h3: SCL_RX_DATA 3'h4 SCL_TX_DATA 3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
uint32_t reserved27: 1;
... | 1,528 |
*/
uint32_t reserved15: 16;
uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
};
uint32_t val;
} slave_addr;
union {
struct {
uint32_t rx_fifo_start_addr: 5; /*This is the offset address of th... | 1,528 |
*/
uint32_t fifo_addr_cfg_en: 1; /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
uint32_t rx_fifo_rst: 1; /*Set this bit to reset rx fifo when using apb fifo access.*/
uint32_t tx_fifo_rst: 1; ... | 1,528 |
*/
uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
uint32_t end_detect: 1; ... | 1,528 |
*/
uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. wh... | 1,528 |
when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
uint32_t reserved13: 19;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrup... | 1,528 |
*/
uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/
uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/
uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.... | 1,528 |
*/
uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/
uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.... | 1,528 |
*/
uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
uint32_t end_detect: 1; /*The masked interrupt status ... | 1,528 |
*/
uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/
uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
uint32_t tx_send_empty: 1; /*The masked interrupt status for tx... | 1,528 |
*/
uint32_t reserved14: 18;
};
uint32_t val;
} scl_high_period;
uint32_t reserved_3c;
union {
struct {
uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
... | 1,528 |
*/
uint32_t reserved10: 22;
};
uint32_t val;
} scl_stop_setup;
union {
struct {
uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
uint32_t en: 1; ... | 1,528 |
*/
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
uint32_t op_code: 3; /*op_code is ... | 1,528 |
*/
} i2c_dev_t;
extern i2c_dev_t I2C0;
extern i2c_dev_t I2C1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_I2C_STRUCT_H_ */
| 1,528 |
/*
*/
#pragma once
#include
#ifdef __cplusplus
extern "C" {
#endif
typedef struct gpio_sd_dev_t {
volatile union {
struct {
uint32_t duty: 8;
uint32_t prescale: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} channel[8];
volatile uni... | 1,530 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,531 |
2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
uint32_t sig_out_en: 1; /*This is the output enable control bit for high speed channel*/
uint32_t idle_lv: 1; /*This bit is used to control the output value when high spe... | 1,531 |
When hstimerx(x=[0 3]) chosen by high speed channel has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent the ... | 1,531 |
*/
uint32_t duty_inc: 1; /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
uint32_t duty_start: 1; /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has b... | 1,531 |
The max bit width of the counter is 20.*/
uint32_t clock_divider: 18; /*This register is used to configure the divider of clock at the entry of timer. The least significant eight bits represent the decimal part.*/
uint32_t pause: 1; /*This bit is used to p... | 1,531 |
*/
uint32_t hstimer1_ovf: 1; /*The interrupt raw bit for high speed channel1 counter overflow.*/
uint32_t hstimer2_ovf: 1; /*The interrupt raw bit for high speed channel2 counter overflow.*/
uint32_t hstimer3_ovf: 1; /*The interrup... | 1,531 |
*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt raw bit for high speed channel 2 duty change done.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt raw bit for high speed channel 3 duty change done.*/
uint32_t duty_chng_end_hsch4: 1; /*The interrup... | 1,531 |
*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt raw bit for low speed channel 3 duty change done.*/
uint32_t duty_chng_end_lsch4: 1; /*The interrupt raw bit for low speed channel 4 duty change done.*/
uint32_t duty_chng_end_lsch5: 1; /*The interrupt ... | 1,531 |
*/
uint32_t hstimer2_ovf: 1; /*The interrupt status bit for high speed channel2 counter overflow event.*/
uint32_t hstimer3_ovf: 1; /*The interrupt status bit for high speed channel3 counter overflow event.*/
uint32_t lstimer0_ovf: 1; ... | 1,531 |
*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt status bit for high speed channel 2 duty change done event.*/
uint32_t duty_chng_end_hsch3: 1; /*The interrupt status bit for high speed channel 3 duty change done event.*/
uint32_t duty_chng_end_hsch4: 1; ... | 1,531 |
*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt status bit for low speed channel 2 duty change done event.*/
uint32_t duty_chng_end_lsch3: 1; /*The interrupt status bit for low speed channel 3 duty change done event.*/
uint32_t duty_chng_end_lsch4: 1; ... | 1,531 |
*/
uint32_t hstimer1_ovf: 1; /*The interrupt enable bit for high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*The interrupt enable bit for high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1... | 1,531 |
*/
uint32_t duty_chng_end_hsch1: 1; /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1... | 1,531 |
*/
uint32_t duty_chng_end_lsch1: 1; /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; ... | 1,531 |
*/
uint32_t hstimer1_ovf: 1; /*Set this bit to clear high speed channel1 counter overflow interrupt.*/
uint32_t hstimer2_ovf: 1; /*Set this bit to clear high speed channel2 counter overflow interrupt.*/
uint32_t hstimer3_ovf: 1; ... | 1,531 |
*/
uint32_t duty_chng_end_hsch1: 1; /*Set this bit to clear high speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_hsch2: 1; /*Set this bit to clear high speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_hsch3: 1; ... | 1,531 |
*/
uint32_t duty_chng_end_lsch1: 1; /*Set this bit to clear low speed channel 1 duty change done interrupt.*/
uint32_t duty_chng_end_lsch2: 1; /*Set this bit to clear low speed channel 2 duty change done interrupt.*/
uint32_t duty_chng_end_lsch3: 1; ... | 1,531 |
1'b1:80mhz 1'b0:8mhz, (only used by LEDC low speed channels/timers)*/
uint32_t reserved: 31;
};
uint32_t val;
} conf;
uint32_t reserved_194;
uint32_t reserved_198;
uint32_t reserved_19c;
uint32_t reserved_1a0;
uint32_t reserved_1a4;
uint32_t reserved_1a8;
u... | 1,531 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define TRACEMEM_BLK0_ADDR 0x3FFFC000UL
#define TRACEMEM_BLK1_ADDR 0x3FFF8000UL
#ifdef __cplusplus
}
#endif
| 1,532 |
// Copyright 2016-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,533 |
Not used directly as the data will be
*/
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x01c)
/* Interrupt registers; since the interrupt from RTC_I2C is not connected,
*/
/* Interrupt raw status register */
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x020)
/* RTC_I2C_TIME_OUT_INT_RAW : R... | 1,533 |
*/
#define RTC_I2C_INT_EN_REG (DR_REG_RTC_I2C_BASE + 0x028)
/* Masked interrupt status register.
*/
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x02c)
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x030)
/* RTC_I2C_SDA_DUTY : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
/*descript... | 1,533 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,534 |
1*/
#define IS_01101(v) (((v)&0x1f)==0x0d)
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP))
/*do not include download mode*/
#define ETS_IS_UART_BOOT() IS_01111(BOOT_MODE_GET())
/*all spi boot including spi/hspi/legacy*/
#define ETS_IS_FLASH_BOOT() (IS_1XXXX(BOOT_MODE_GE... | 1,534 |
/*
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#ifdef __cplusplus
}
#endif
| 1,535 |
/*
*/
#ifndef _SOC_DPORT_REG_H_
#define _SOC_DPORT_REG_H_
#include "soc.h"
#ifndef __ASSEMBLER__
#include "dport_access.h"
#endif
/* Registers defined in this header file must be accessed using special macros,
*/
#define DPORT_PRO_BOOT_REMAP_CTRL_REG (DR_REG_DPORT_BASE + 0x000)
/* DPORT_PRO_BOOT_REMAP : ... | 1,537 |
See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL 0x04 /* Control transfer bubble */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM 0x08 /* I-cache miss (incl uncached miss) */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM 0x0C /* D-cache miss (excl uncached mis... | 1,537 |
*/
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM 0x1A /* ITLB miss */
#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB 0x1C /* HW DTLB refill. The refill address and data are available on
DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
#define DPORT_RECORD_PDEBUGS... | 1,537 |
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,538 |
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_w... | 1,538 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,539 |
*/
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
uint32_t reserved27: 5;
};
uint32_t val;
}saradc_ctrl;
union {
struct {
uint32_t meas_num_limit: 1;
uint32... | 1,539 |
// Copyright 2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applic... | 1,540 |
/*
*/
#pragma once
#include "soc.h"
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
/*description: */
#define GPIO_SD0_PRESCALE 0x000000FF
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
#define GPIO_SD0... | 1,541 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by a... | 1,542 |
0x007FFFFF:0xffffffff)
#define FRC_TIMER_COUNT_S 0
#define FRC_TIMER_CTRL_REG(i) (REG_FRC_TIMER_BASE(i) + 0x8)
#define FRC_TIMER_INT_STATUS (BIT(8)) // interrupt status (RO)
#define FRC_TIMER_ENABLE (BIT(7)) // enable timer
#define FRC_TIMER_AUTOLOAD ... | 1,542 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,543 |
*/
#define LEDC_IDLE_LV_HSCH0 (BIT(3))
#define LEDC_IDLE_LV_HSCH0_M (BIT(3))
#define LEDC_IDLE_LV_HSCH0_V 0x1
#define LEDC_IDLE_LV_HSCH0_S 3
/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for high speed channel0*/
#define LEDC_SIG_OUT_EN_HSCH0 (B... | 1,543 |
When hstimerx(x=[0
3]) choosed by high speed channel0 has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4]) (1) reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1) (2) The least four bits in this register represent t... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH0 (BIT(30))
#define LEDC_DUTY_INC_HSCH0_M (BIT(30))
#define LEDC_DUTY_INC_HSCH0_V 0x1
#define LEDC_DUTY_INC_HSCH0_S 30
/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH0 0x000003FF
#define LEDC_DUTY_SCALE_HSCH0_M ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))
#define LEDC_DUTY_SCALE_HSCH0_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH0_S 0
#define LEDC_HSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010)
/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;defau... | 1,543 |
2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
#define LEDC_TIMER_SEL_HSCH1 0x00000003
#define LEDC_TIMER_SEL_HSCH1_M ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))
#define LEDC_TIMER_SEL_HSCH1_V 0x3
#define LEDC_TIMER_SEL_HSCH1_S 0
#define LEDC_HSCH... | 1,543 |
reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4]) (1) reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH1 0x01FFFFFF
#define LEDC_DUTY_HSCH1_... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH1 (BIT(30))
#define LEDC_DUTY_INC_HSCH1_M (BIT(30))
#define LEDC_DUTY_INC_HSCH1_V 0x1
#define LEDC_DUTY_INC_HSCH1_S 30
/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH1 0x000003FF
#define LEDC_DUTY_SCALE_HSCH1_M ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))
#define LEDC_DUTY_SCALE_HSCH1_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH1_S 0
#define LEDC_HSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024)
/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;defau... | 1,543 |
2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
#define LEDC_TIMER_SEL_HSCH2 0x00000003
#define LEDC_TIMER_SEL_HSCH2_M ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))
#define LEDC_TIMER_SEL_HSCH2_V 0x3
#define LEDC_TIMER_SEL_HSCH2_S 0
#define LEDC_HSCH... | 1,543 |
reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4]) (1) reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH2 0x01FFFFFF
#define LEDC_DUTY_HSCH2_... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH2 (BIT(30))
#define LEDC_DUTY_INC_HSCH2_M (BIT(30))
#define LEDC_DUTY_INC_HSCH2_V 0x1
#define LEDC_DUTY_INC_HSCH2_S 30
/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH2 0x000003FF
#define LEDC_DUTY_SCALE_HSCH2_M ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))
#define LEDC_DUTY_SCALE_HSCH2_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH2_S 0
#define LEDC_HSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038)
/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;defau... | 1,543 |
2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
#define LEDC_TIMER_SEL_HSCH3 0x00000003
#define LEDC_TIMER_SEL_HSCH3_M ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))
#define LEDC_TIMER_SEL_HSCH3_V 0x3
#define LEDC_TIMER_SEL_HSCH3_S 0
#define LEDC_HSCH... | 1,543 |
reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4]) (1) reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH3 0x01FFFFFF
#define LEDC_DUTY_HSCH3_... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH3 (BIT(30))
#define LEDC_DUTY_INC_HSCH3_M (BIT(30))
#define LEDC_DUTY_INC_HSCH3_V 0x1
#define LEDC_DUTY_INC_HSCH3_S 30
/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH3 0x000003FF
#define LEDC_DUTY_SCALE_HSCH3_M ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))
#define LEDC_DUTY_SCALE_HSCH3_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH3_S 0
#define LEDC_HSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C)
/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;defau... | 1,543 |
2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
#define LEDC_TIMER_SEL_HSCH4 0x00000003
#define LEDC_TIMER_SEL_HSCH4_M ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))
#define LEDC_TIMER_SEL_HSCH4_V 0x3
#define LEDC_TIMER_SEL_HSCH4_S 0
#define LEDC_HSCH... | 1,543 |
reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4]) (1) reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH4 0x01FFFFFF
#define LEDC_DUTY_HSCH4_... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH4 (BIT(30))
#define LEDC_DUTY_INC_HSCH4_M (BIT(30))
#define LEDC_DUTY_INC_HSCH4_V 0x1
#define LEDC_DUTY_INC_HSCH4_S 30
/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH4 0x000003FF
#define LEDC_DUTY_SCALE_HSCH4_M ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))
#define LEDC_DUTY_SCALE_HSCH4_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH4_S 0
#define LEDC_HSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060)
/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_SIG_OUT_EN_HSCH5 (BIT(2))
#define LEDC_SIG_OUT_EN_HSCH5_M (BIT(2))
#define LEDC_SIG_OUT_EN_HSCH5_V 0x1
#define LEDC_SIG_OUT_EN_HSCH5_S 2
/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: There are four high speed timers the two bits are used to select
one of them for h... | 1,543 |
When hstimerx(x=[0
3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4]) (1) reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1) (2) The least four bits in this register represent th... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH5 (BIT(30))
#define LEDC_DUTY_INC_HSCH5_M (BIT(30))
#define LEDC_DUTY_INC_HSCH5_V 0x1
#define LEDC_DUTY_INC_HSCH5_S 30
/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH5 0x000003FF
#define LEDC_DUTY_SCALE_HSCH5_M ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))
#define LEDC_DUTY_SCALE_HSCH5_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH5_S 0
#define LEDC_HSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074)
/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;defau... | 1,543 |
2'b00: seletc hstimer0. 2'b01: select hstimer1. 2'b10: select hstimer2. 2'b11: select hstimer3.*/
#define LEDC_TIMER_SEL_HSCH6 0x00000003
#define LEDC_TIMER_SEL_HSCH6_M ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))
#define LEDC_TIMER_SEL_HSCH6_V 0x3
#define LEDC_TIMER_SEL_HSCH6_S 0
#define LEDC_HSCH... | 1,543 |
reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4]) (1) reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1) (2) The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
#define LEDC_DUTY_HSCH6 0x01FFFFFF
#define LEDC_DUTY_HSCH6_... | 1,543 |
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