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*/
#define LEDC_DUTY_INC_HSCH6 (BIT(30))
#define LEDC_DUTY_INC_HSCH6_M (BIT(30))
#define LEDC_DUTY_INC_HSCH6_V 0x1
#define LEDC_DUTY_INC_HSCH6_S 30
/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH6 0x000003FF
#define LEDC_DUTY_SCALE_HSCH6_M ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))
#define LEDC_DUTY_SCALE_HSCH6_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH6_S 0
#define LEDC_HSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088)
/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_SIG_OUT_EN_HSCH7 (BIT(2))
#define LEDC_SIG_OUT_EN_HSCH7_M (BIT(2))
#define LEDC_SIG_OUT_EN_HSCH7_V 0x1
#define LEDC_SIG_OUT_EN_HSCH7_S 2
/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
/*description: There are four high speed timers the two bits are used to select
one of them for h... | 1,543 |
When hstimerx(x=[0
3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4]) (1) reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1) (2) The least four bits in this register represent th... | 1,543 |
*/
#define LEDC_DUTY_INC_HSCH7 (BIT(30))
#define LEDC_DUTY_INC_HSCH7_M (BIT(30))
#define LEDC_DUTY_INC_HSCH7_V 0x1
#define LEDC_DUTY_INC_HSCH7_S 30
/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for high spee... | 1,543 |
*/
#define LEDC_DUTY_SCALE_HSCH7 0x000003FF
#define LEDC_DUTY_SCALE_HSCH7_M ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))
#define LEDC_DUTY_SCALE_HSCH7_V 0x3FF
#define LEDC_DUTY_SCALE_HSCH7_S 0
#define LEDC_HSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C)
/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH0 (BIT(3))
#define LEDC_IDLE_LV_LSCH0_M (BIT(3))
#define LEDC_IDLE_LV_LSCH0_V 0x1
#define LEDC_IDLE_LV_LSCH0_S 3
/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel0.*/
#define LEDC_SIG_OUT_EN_LSCH0 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4]) (1) reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH0 (BIT(30))
#define LEDC_DUTY_INC_LSCH0_M (BIT(30))
#define LEDC_DUTY_INC_LSCH0_V 0x1
#define LEDC_DUTY_INC_LSCH0_S 30
/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH0 0x000003FF
#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH0_S 0
#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00B0)
/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH1 (BIT(3))
#define LEDC_IDLE_LV_LSCH1_M (BIT(3))
#define LEDC_IDLE_LV_LSCH1_V 0x1
#define LEDC_IDLE_LV_LSCH1_S 3
/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel1.*/
#define LEDC_SIG_OUT_EN_LSCH1 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4]) (1) reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH1 (BIT(30))
#define LEDC_DUTY_INC_LSCH1_M (BIT(30))
#define LEDC_DUTY_INC_LSCH1_V 0x1
#define LEDC_DUTY_INC_LSCH1_S 30
/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH1 0x000003FF
#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH1_S 0
#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00C4)
/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH2 (BIT(3))
#define LEDC_IDLE_LV_LSCH2_M (BIT(3))
#define LEDC_IDLE_LV_LSCH2_V 0x1
#define LEDC_IDLE_LV_LSCH2_S 3
/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel2.*/
#define LEDC_SIG_OUT_EN_LSCH2 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4]) (1) reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH2 (BIT(30))
#define LEDC_DUTY_INC_LSCH2_M (BIT(30))
#define LEDC_DUTY_INC_LSCH2_V 0x1
#define LEDC_DUTY_INC_LSCH2_S 30
/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH2 0x000003FF
#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH2_S 0
#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00D8)
/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH3 (BIT(3))
#define LEDC_IDLE_LV_LSCH3_M (BIT(3))
#define LEDC_IDLE_LV_LSCH3_V 0x1
#define LEDC_IDLE_LV_LSCH3_S 3
/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel3.*/
#define LEDC_SIG_OUT_EN_LSCH3 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4]) (1) reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH3 (BIT(30))
#define LEDC_DUTY_INC_LSCH3_M (BIT(30))
#define LEDC_DUTY_INC_LSCH3_V 0x1
#define LEDC_DUTY_INC_LSCH3_S 30
/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH3 0x000003FF
#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH3_S 0
#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x00EC)
/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH4 (BIT(3))
#define LEDC_IDLE_LV_LSCH4_M (BIT(3))
#define LEDC_IDLE_LV_LSCH4_V 0x1
#define LEDC_IDLE_LV_LSCH4_S 3
/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel4.*/
#define LEDC_SIG_OUT_EN_LSCH4 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4]) (1) reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH4 (BIT(30))
#define LEDC_DUTY_INC_LSCH4_M (BIT(30))
#define LEDC_DUTY_INC_LSCH4_V 0x1
#define LEDC_DUTY_INC_LSCH4_S 30
/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH4 0x000003FF
#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH4_S 0
#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0100)
/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH5 (BIT(3))
#define LEDC_IDLE_LV_LSCH5_M (BIT(3))
#define LEDC_IDLE_LV_LSCH5_V 0x1
#define LEDC_IDLE_LV_LSCH5_S 3
/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel5.*/
#define LEDC_SIG_OUT_EN_LSCH5 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4]) (1) reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH5 (BIT(30))
#define LEDC_DUTY_INC_LSCH5_M (BIT(30))
#define LEDC_DUTY_INC_LSCH5_V 0x1
#define LEDC_DUTY_INC_LSCH5_S 30
/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH5 0x000003FF
#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH5_S 0
#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0114)
/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH6 (BIT(3))
#define LEDC_IDLE_LV_LSCH6_M (BIT(3))
#define LEDC_IDLE_LV_LSCH6_V 0x1
#define LEDC_IDLE_LV_LSCH6_S 3
/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel6.*/
#define LEDC_SIG_OUT_EN_LSCH6 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4]) (1) reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH6 (BIT(30))
#define LEDC_DUTY_INC_LSCH6_M (BIT(30))
#define LEDC_DUTY_INC_LSCH6_V 0x1
#define LEDC_DUTY_INC_LSCH6_S 30
/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH6 0x000003FF
#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))
#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH6_S 0
#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0128)
/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_IDLE_LV_LSCH7 (BIT(3))
#define LEDC_IDLE_LV_LSCH7_M (BIT(3))
#define LEDC_IDLE_LV_LSCH7_V 0x1
#define LEDC_IDLE_LV_LSCH7_S 3
/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: This is the output enable control bit for low speed channel7.*/
#define LEDC_SIG_OUT_EN_LSCH7 (B... | 1,543 |
When lstimerx(x=[0
3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4]) (1) reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1) (2) The least four bits in this register represent the... | 1,543 |
*/
#define LEDC_DUTY_INC_LSCH7 (BIT(30))
#define LEDC_DUTY_INC_LSCH7_M (BIT(30))
#define LEDC_DUTY_INC_LSCH7_V 0x1
#define LEDC_DUTY_INC_LSCH7_S 30
/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
/*description: This register is used to control the num of increased or decreased
times for low speed... | 1,543 |
*/
#define LEDC_DUTY_SCALE_LSCH7 0x000003FF
#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))
#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF
#define LEDC_DUTY_SCALE_LSCH7_S 0
#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x013C)
/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;defau... | 1,543 |
*/
#define LEDC_HSTIMER0_RST (BIT(24))
#define LEDC_HSTIMER0_RST_M (BIT(24))
#define LEDC_HSTIMER0_RST_V 0x1
#define LEDC_HSTIMER0_RST_S 24
/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: This bit is used to pause the counter in high speed timer0*/
#define LEDC_HSTIMER0_PAUSE (BIT(23))... | 1,543 |
the counter range is [0 2**reg_hstimer0_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER0_DUTY_RES 0x0000001F
#define LEDC_HSTIMER0_DUTY_RES_M ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
#define LEDC_HSTIMER0_DUTY_RES_V 0x1F
#define LEDC_HSTIMER0_DUTY_RES_S 0
// Keep the definitions be... | 1,543 |
1'b1:apb_clk 0:ref_tick*/
#define LEDC_TICK_SEL_HSTIMER1 (BIT(25))
#define LEDC_TICK_SEL_HSTIMER1_M (BIT(25))
#define LEDC_TICK_SEL_HSTIMER1_V 0x1
#define LEDC_TICK_SEL_HSTIMER1_S 25
/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
/*description: This bit is used to reset high speed timer1 the counter ... | 1,543 |
the counter range is [0 2**reg_hstimer1_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER1_DUTY_RES 0x0000001F
#define LEDC_HSTIMER1_DUTY_RES_M ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
#define LEDC_HSTIMER1_DUTY_RES_V 0x1F
#define LEDC_HSTIMER1_DUTY_RES_S 0
// Keep the definitions be... | 1,543 |
1'b1:apb_clk 0:ref_tick*/
#define LEDC_TICK_SEL_HSTIMER2 (BIT(25))
#define LEDC_TICK_SEL_HSTIMER2_M (BIT(25))
#define LEDC_TICK_SEL_HSTIMER2_V 0x1
#define LEDC_TICK_SEL_HSTIMER2_S 25
/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
/*description: This bit is used to reset high speed timer2 the counter ... | 1,543 |
the counter range is [0 2**reg_hstimer2_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER2_DUTY_RES 0x0000001F
#define LEDC_HSTIMER2_DUTY_RES_M ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
#define LEDC_HSTIMER2_DUTY_RES_V 0x1F
#define LEDC_HSTIMER2_DUTY_RES_S 0
// Keep the definitions be... | 1,543 |
1'b1:apb_clk 0:ref_tick*/
#define LEDC_TICK_SEL_HSTIMER3 (BIT(25))
#define LEDC_TICK_SEL_HSTIMER3_M (BIT(25))
#define LEDC_TICK_SEL_HSTIMER3_V 0x1
#define LEDC_TICK_SEL_HSTIMER3_S 25
/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
/*description: This bit is used to reset high speed timer3 the counter ... | 1,543 |
the counter range is [0 2**reg_hstimer3_lim] the max bit width for counter is 20.*/
#define LEDC_HSTIMER3_DUTY_RES 0x0000001F
#define LEDC_HSTIMER3_DUTY_RES_M ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
#define LEDC_HSTIMER3_DUTY_RES_V 0x1F
#define LEDC_HSTIMER3_DUTY_RES_S 0
// Keep the definitions be... | 1,543 |
*/
#define LEDC_LSTIMER0_PARA_UP (BIT(26))
#define LEDC_LSTIMER0_PARA_UP_M (BIT(26))
#define LEDC_LSTIMER0_PARA_UP_V 0x1
#define LEDC_LSTIMER0_PARA_UP_S 26
/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: This bit is used to choose slow_clk or ref_tick for low speed
timer0. 1'b1:slow... | 1,543 |
*/
#define LEDC_DIV_NUM_LSTIMER0 0x0003FFFF
#define LEDC_DIV_NUM_LSTIMER0_M ((LEDC_DIV_NUM_LSTIMER0_V)<<(LEDC_DIV_NUM_LSTIMER0_S))
#define LEDC_DIV_NUM_LSTIMER0_V 0x3FFFF
#define LEDC_DIV_NUM_LSTIMER0_S 5
/* LEDC_LSTIMER0_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of... | 1,543 |
*/
#define LEDC_LSTIMER0_CNT 0x000FFFFF
#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
#define LEDC_LSTIMER0_CNT_V 0xFFFFF
#define LEDC_LSTIMER0_CNT_S 0
#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x0168)
/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
/*... | 1,543 |
*/
#define LEDC_LSTIMER1_RST (BIT(24))
#define LEDC_LSTIMER1_RST_M (BIT(24))
#define LEDC_LSTIMER1_RST_V 0x1
#define LEDC_LSTIMER1_RST_S 24
/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: This bit is used to pause the counter in low speed timer1.*/
#define LEDC_LSTIMER1_PAUSE (BIT(23))... | 1,543 |
the counter range is [0 2**reg_lstimer1_lim] the max bit width for counter is 20.*/
#define LEDC_LSTIMER1_DUTY_RES 0x0000001F
#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
#define LEDC_LSTIMER1_DUTY_RES_V 0x1F
#define LEDC_LSTIMER1_DUTY_RES_S 0
// Keep the definitions be... | 1,543 |
*/
#define LEDC_LSTIMER2_PARA_UP (BIT(26))
#define LEDC_LSTIMER2_PARA_UP_M (BIT(26))
#define LEDC_LSTIMER2_PARA_UP_V 0x1
#define LEDC_LSTIMER2_PARA_UP_S 26
/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
/*description: This bit is used to choose slow_clk or ref_tick for low speed
timer2. 1'b1:slow... | 1,543 |
*/
#define LEDC_DIV_NUM_LSTIMER2 0x0003FFFF
#define LEDC_DIV_NUM_LSTIMER2_M ((LEDC_DIV_NUM_LSTIMER2_V)<<(LEDC_DIV_NUM_LSTIMER2_S))
#define LEDC_DIV_NUM_LSTIMER2_V 0x3FFFF
#define LEDC_DIV_NUM_LSTIMER2_S 5
/* LEDC_LSTIMER2_LIM : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
/*description: This register controls the range of... | 1,543 |
*/
#define LEDC_LSTIMER2_CNT 0x000FFFFF
#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
#define LEDC_LSTIMER2_CNT_V 0xFFFFF
#define LEDC_LSTIMER2_CNT_S 0
#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x0178)
/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
/*... | 1,543 |
*/
#define LEDC_LSTIMER3_RST (BIT(24))
#define LEDC_LSTIMER3_RST_M (BIT(24))
#define LEDC_LSTIMER3_RST_V 0x1
#define LEDC_LSTIMER3_RST_S 24
/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: This bit is used to pause the counter in low speed timer3.*/
#define LEDC_LSTIMER3_PAUSE (BIT(23))... | 1,543 |
the counter range is [0 2**reg_lstimer3_lim] the max bit width for counter is 20.*/
#define LEDC_LSTIMER3_DUTY_RES 0x0000001F
#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
#define LEDC_LSTIMER3_DUTY_RES_V 0x1F
#define LEDC_LSTIMER3_DUTY_RES_S 0
// Keep the definitions be... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(23))
#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(23))
#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 23
/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
/*description: The interrupt raw bit for l... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(20))
#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(20))
#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 20
/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: The interrupt raw bit for l... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(17))
#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(17))
#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 17
/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
/*description: The interrupt raw bit for l... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW (BIT(14))
#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M (BIT(14))
#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S 14
/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
/*description: The interrupt raw bit for h... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW (BIT(11))
#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M (BIT(11))
#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S 11
/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
/*description: The interrupt raw bit for h... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW (BIT(8))
#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M (BIT(8))
#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S 8
/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
/*description: The interrupt raw bit for low speed ch... | 1,543 |
*/
#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(4))
#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(4))
#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1
#define LEDC_LSTIMER0_OVF_INT_RAW_S 4
/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
/*description: The interrupt raw bit for high speed channel3 counter overflow.*/... | 1,543 |
*/
#define LEDC_HSTIMER0_OVF_INT_RAW (BIT(0))
#define LEDC_HSTIMER0_OVF_INT_RAW_M (BIT(0))
#define LEDC_HSTIMER0_OVF_INT_RAW_V 0x1
#define LEDC_HSTIMER0_OVF_INT_RAW_S 0
#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x0184)
/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */
/*descriptio... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(21))
#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(21))
#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 21
/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: The interrupt status bit for low... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(18))
#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(18))
#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 18
/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
/*description: The interrupt status bit for low... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST (BIT(15))
#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M (BIT(15))
#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S 15
/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
/*description: The interrupt status bit for hig... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST (BIT(12))
#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M (BIT(12))
#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S 12
/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
/*description: The interrupt status bit for hig... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST (BIT(9))
#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M (BIT(9))
#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S 9
/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
/*description: The interrupt status bit for high sp... | 1,543 |
*/
#define LEDC_LSTIMER2_OVF_INT_ST (BIT(6))
#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(6))
#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1
#define LEDC_LSTIMER2_OVF_INT_ST_S 6
/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
/*description: The interrupt status bit for low speed channel1 counter overflow event... | 1,543 |
*/
#define LEDC_HSTIMER2_OVF_INT_ST (BIT(2))
#define LEDC_HSTIMER2_OVF_INT_ST_M (BIT(2))
#define LEDC_HSTIMER2_OVF_INT_ST_V 0x1
#define LEDC_HSTIMER2_OVF_INT_ST_S 2
/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
/*description: The interrupt status bit for high speed channel1 counter overflow even... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(23))
#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(23))
#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 23
/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: The interrupt enable bit f... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(20))
#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(20))
#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 20
/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: The interrupt enable bit f... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(17))
#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(17))
#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 17
/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
/*description: The interrupt enable bit f... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA (BIT(14))
#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M (BIT(14))
#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S 14
/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
/*description: The interrupt enable bit f... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA (BIT(11))
#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M (BIT(11))
#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S 11
/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
/*description: The interrupt enable bit f... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA (BIT(8))
#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M (BIT(8))
#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S 8
/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
/*description: The interrupt enable bit for low spee... | 1,543 |
*/
#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(5))
#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(5))
#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1
#define LEDC_LSTIMER1_OVF_INT_ENA_S 5
/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: The interrupt enable bit for low speed channel0 counter overflow... | 1,543 |
*/
#define LEDC_HSTIMER1_OVF_INT_ENA (BIT(1))
#define LEDC_HSTIMER1_OVF_INT_ENA_M (BIT(1))
#define LEDC_HSTIMER1_OVF_INT_ENA_V 0x1
#define LEDC_HSTIMER1_OVF_INT_ENA_S 1
/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The interrupt enable bit for high speed channel0 counter overflo... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(22))
#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(22))
#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 22
/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
/*description: Set this bit to clear low... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(19))
#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(19))
#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 19
/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
/*description: Set this bit to clear low... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(16))
#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(16))
#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1
#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 16
/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
/*description: Set this bit to clear hig... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR (BIT(13))
#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M (BIT(13))
#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S 13
/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
/*description: Set this bit to clear hig... | 1,543 |
*/
#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR (BIT(10))
#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M (BIT(10))
#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V 0x1
#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S 10
/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
/*description: Set this bit to clear high... | 1,543 |
*/
#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(7))
#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(7))
#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1
#define LEDC_LSTIMER3_OVF_INT_CLR_S 7
/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
/*description: Set this bit to clear low speed channel2 counter overflow inter... | 1,543 |
*/
#define LEDC_HSTIMER3_OVF_INT_CLR (BIT(3))
#define LEDC_HSTIMER3_OVF_INT_CLR_M (BIT(3))
#define LEDC_HSTIMER3_OVF_INT_CLR_V 0x1
#define LEDC_HSTIMER3_OVF_INT_CLR_S 3
/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to clear high speed channel2 counter overflow inte... | 1,543 |
1'b1:80mhz 1'b0:8mhz*/
#define LEDC_APB_CLK_SEL (BIT(0))
#define LEDC_APB_CLK_SEL_M (BIT(0))
#define LEDC_APB_CLK_SEL_V 0x1
#define LEDC_APB_CLK_SEL_S 0
#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x01FC)
/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h16031700 ; */
/*description: This register represents... | 1,543 |
// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,544 |
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by app... | 1,545 |
*/
uint32_t ahbm_rst: 1; /*Set this bit to reset dma ahb interface.*/
uint32_t in_loop_test: 1; /*Set this bit to enable loop test for in links.*/
uint32_t out_loop_test: 1; /*Set this bit to enable loop test for out ... | 1,545 |
*/
uint32_t outdscr_burst_en: 1; /*Set this bit to enable DMA in links to use burst mode.*/
uint32_t indscr_burst_en: 1; /*Set this bit to enable DMA out links to use burst mode.*/
uint32_t out_data_burst_en: 1; /*Set this bit to ena... | 1,545 |
*/
uint32_t len_eof_en: 1; /*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/
uint32_t encode_crc_en: 1; /*Set this bit to enable crc calculation for data frame... | 1,545 |
*/
uint32_t rx_hung: 1; /*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
uint32_t tx_hung: 1; /*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
... | 1,545 |
*/
uint32_t in_dscr_err: 1; /*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
uint32_t out_dscr_err: 1; /*when there are some errors about the in link descriptor it will produce uhci_out_dscr_... | 1,545 |
*/
uint32_t dma_in_fifo_full_wm: 1;
uint32_t reserved17: 15;
};
uint32_t val;
} int_raw;
union {
struct {
uint32_t rx_start: 1;
uint32_t tx_start: 1;
uint32_t rx_hung: 1;
uin... | 1,545 |
*/
uint32_t empty: 1; /*1:DMA in link descriptor's fifo is empty.*/
uint32_t reserved2: 30;
};
uint32_t val;
} dma_out_status;
union {
struct {
uint32_t fifo_wdata: 9; /*This is the data need to be pushed ... | 1,545 |
*/
uint32_t reserved12: 4;
uint32_t fifo_pop: 1; /*Set this bit to pop data in in link descriptor's fifo.*/
uint32_t reserved17: 15;
};
uint32_t val;
} dma_in_pop;
union {
struct {
uint32_t addr: 20; ... | 1,545 |
*/
uint32_t auto_ret: 1; /*1:when a packet is wrong in link descriptor returns to the descriptor which is lately used.*/
uint32_t reserved21: 7;
uint32_t stop: 1; /*Set this bit to stop dealing with the in link descriptors.*/
... | 1,545 |
*/
uint32_t crc_disable: 1; /*Set this bit to disable crc calculation.*/
uint32_t save_head: 1; /*Set this bit to save packet header .*/
uint32_t tx_check_sum_re: 1; /*Set this bit to enable hardware replace check_sum in pa... | 1,545 |
*/
uint32_t reserved21: 11;
};
uint32_t val;
} conf1;
uint32_t state0; /**/
uint32_t state1; /**/
uint32_t dma_out_eof_des_addr; /*This register stores the address of... | 1,545 |
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